ADS5102CPFB_技术文档

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

1.8-V ANALOG SUPPLY, 10-BIT, 65/40 MSPS

ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE

D

Imaging

FEATURES

Communications

Baseband Digitization

D

ADS5102 (65 MSPS) ADS5103 (40 MSPS)

Differential Input

1.8 V Analog/Digital Supply

DESCRIPTION

Digital Outputs Compatible With 1.8 V or 3.3 V

Logic

The ADS5102/3 are low-power CMOS, 10-bit, analog-

to-digital converters (ADC) that operate from a single

1.8-V supply. The internal reference can be bypassed

to use an external reference to suit the dc accuracy and

temperature drift requirements of the application. A

10-bit parallel output data bus is provided with 3-state

outputs. For power sensitive systems, a standby mode

is provided which reduces power consumption to

336 µW. Also, if using external voltage reference, then

the internal VREF circuit can be powered down. The

analog input is differential, which provides excellent

common-mode noise rejection as well as superior

performance from the ADS5102/3.

D

Signal-to-Noise: 58 dB at 20 MHz (ADS5103)

Spurious Free Dynamic Range: 71 dB at

20 MHz (ADS5102)

D

105-mW Power Dissipation (ADS5103)

336 µW Power-Down Mode

APPLICATIONS

D

Ultrasound

Digital Cameras

FUNCTIONAL BLOCK DIAGRAM

AV

DD

STBY

DRV

DD

DV

DD

Timing Circuitry

CLK

AIN+

AIN–

3-State

Output

Buffers

Sample

and Hold

D[0–9]

OE

10 Bit

ADC

CM

NC

RBIAS

NC

Internal

Reference

Circuit

AGND

BG

PDREF REFT REFB CML

DRGND

DGND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

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ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

PFB PACKAGE

(TOP VIEW)

36 35 34 33 32 31 30 29 28 27 26 25

24

23

22

21

20

19

18

17

16

15

14

13

DRV

NC

DRGND

NC

37

38

39

40

41

42

DD

DV

DD

DGND

CLK

STBY

OE

PDREF

NC

RBIAS

NC

DGND

AV

DD

AGND

AIN– 43

AIN+ 44

AGND 45

AV

46

DD

NC 47

NC 48

1

2

3

4

5

6

7

8

9 10 11 12

NC – No internal connection

ORDERING INFORMATION

48-TQFP (PFB)

Tape and Reel

48-TQFP (PFB)

Tray

48-TQFP (PFB)

Tape and Reel

48-TQFP (PFB)

Tray

T

A

40 MSPS

65 MSPS

0°C to 70°C

ADS5103CPFBR ADS5103CPFB

ADS5102CPFBR ADS5102CPFB

–40°C to 85°C

Evaluation module

ADS5103IPFBR

ADS5103EVM

ADS5103IPFB

ADS5103EVM

ADS5102IPFBR

ADS5102EVM

ADS5102IPFB

ADS5102EVM

2

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ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

Terminal Functions

TERMINAL

NO.

I/O

DESCRIPTION

NAME

AV

2, 41, 46

I

Analog supply, 1.8V ±5%

DD

AGND

3, 9, 42, 45

Analog ground

Reference top

Reference bottom

REFT

REFB

CML

4

5

I/O

O

I

6

Common mode level output—nominally 1.0 V

BG

7

Band-gap decoupling—decouple with 1 µF to GND and 100 kΩ to AV

(refer to Figure 30)

DD

PDREF

17

Powerdown reference when using external voltage reference 0 = internal VREF, 1 = external VREF.

In external VREF mode, connect pins BG and REFT together.

RBIAS

14

O

Connect a resistor between this pin and AGND. This resistor value is determined by speed grade

selected and is used to set amplifier internal bias currents. (see Table 2)

OE

18

19

I

1 = 3-state the data outputs , 0 = data bus enable

0 = power down mode, 1 = normal operation mode

Clock Input

STBY

CLK

20

I

DGND

21, 40

22, 39

24

I

Digital ground

DV

I

Digital supply—1.8 V nominally

Driver digital supply—1.8 V or 3.3 V nominally

Digital Bit 9 (MSB)

DD

DRV

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

I

DD

25

O

I

26

Digital Bit 8

27

Digital Bit 7

28

Digital Bit 6

29

Digital Bit 5

30

Digital Bit 4

31

Digital Bit 3

32

Digital Bit 2

33

Digital Bit 1

34

Digital Bit 0 (LSB)

DRGND

AIN+

AIN–

NC

37

Driver digital ground

Positive analog input

Negative analog input

No internal connection on this pin

44

I

43

I

1,8,10,11,12,

13,15,16,23,35,

36, 38,47,48

NA

3

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ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage:

V

DRV

to AGND, DV

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 2.2 V

DD

to DRGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V

DD

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 0.3 V

AV to DV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –2.2 V to 2.2 V

DD

Reference voltage input range REFT, REFB, to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AV

CML, analog input voltage range AIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AV

Clock input CLK to DRGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DRV

Digital inputs to DRGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DRV

Digital outputs to DRGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DRV

+ 0.3 V

DD

Operating junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 150°C

Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

J

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN

REFB

0.8

TYP

MAX

REFT

1.1

UNIT

Analog Inputs

Analog input voltage (AIN+, AIN–)

Input voltage, differential full scale

Input common-mode voltage, (REFT+REFB)/2

V

1

V

pp

V

pF

Input capacitance (C ), measured to ground

i

5

10

Overvoltage recovery time, 1.8-V input voltage

Analog input bandwidth

ns

950

38.5

62.5

MHz

ADS5102

Input impedance (switch capacitor)

kΩ

ADS5103

Supplies and References

Operating free-air temperature, T

–40

1.65

1.30

0.78

0.85

1.22

85

2.00

3.6

°C

V

A

Analog supply voltage, AV

1.80

1.34

0.81

1.05

1.27

DD

Digital supply voltage, DV

DD

Digital driver supply voltage, DRV

Reference top voltage, VREFT

DD

1.39

0.84

1.15

1.32

Reference bottom voltage, VREFB

Common-mode voltage, VCML

Bandgap voltage, VBG

Clock Inputs CLK

ADS5102

ADS5103

1

65

40

Sampling rate

MSPS

4

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ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

electrical characteristics over recommended operating conditions, AV

= DV

= 1.8 V,

DD

DRV

= 3.3 V, F = 40, 65 MSPS (as appropriate)/50% duty cycle, –1 dBFS input span, C = 10 pF

DD

s

L

at D0–D9, internal reference, T

to T

, typical data at 25°C (unless otherwise noted)

(min)

(max)

internal reference voltages

PARAMETER

MIN

1.30

0.78

0.85

1.22

TYP

1.34

0.81

1.05

1.27

MAX

1.39

0.84

1.15

1.32

UNIT

VREFT

VREFB

VCML

VBG

Reference top voltage

Reference bottom voltage

Common-mode voltage

Bandgap voltage

V

external reference voltages

PARAMETER

Reference input voltage (top)

Reference input voltage (bottom)

MIN

1.15

0.70

0.45

TYP

1.25

0.75

0.50

200

MAX

1.35

0.85

0.55

UNIT

V

REFT

REFB

V

REFT–REFB

Differential input

Input resistance

V

Ω

digital outputs

PARAMETER

TEST CONDITIONS

MIN

– 0.1

– 0.2

TYP

MAX

UNIT

DRV

= 1.8 V

= 3.3 V

= 1.8 V

= 3.3 V

DRV

DD

V

High-level output voltage

I

= 50 µA

V

OH

DD

0.1

0.2

Low-level output voltage

External load capacitance

V

OL

C

15

pF

L

digital inputs

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DRV

= 1.8 V

= 3.3 V

= 1.8 V

= 3.3 V

0.8 × DRV

DD

V

High-level input voltage

Low-level input voltage

V

IH

0.8 × DRV

DD

0.2 × DRV

DD

V

IL

DD

I

High-level input current

Low-level input current

V

= DRV

±5

µA

IH

IL

DD

V

= 0 V

±5

IL

dc accuracy

PARAMETER

TEST CONDITIONS

MIN

TYP

±1

MAX

±2.5

±1.5

±1

UNIT

LSB

ADS5102

ADS5103

ADS5102

ADS5103

(INL)

Integral nonlinearity

±0.5

±0.4

(DNL)

Differential nonlinearity

±0.8

Missing code

Offset error

Gain error

No missing code assured

REFT = 1.25 V, REFB = 0.75 V

±0.4

±1.4

±1.5 %FSR

±2 %FSR

5

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ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

electrical characteristics over recommended operating conditions, AV

= DV

= 1.8 V,

DD

DRV

= 3.3 V, F = 40, 65 MSPS (as appropriate)/50% duty cycle, –1 dBFS input span, C = 10 pF

DD

s

L

at D0–D9, internal reference, T

to T

, typical data at 25°C (unless otherwise noted)

(max)

(min)

(continued)

dynamic performance

PARAMETER

TEST CONDITIONS

f = 3.5 MHz

f = 20 MHz

f = 3.5 MHz

f = 20 MHz

f = 3.5 MHz

f = 20 MHz

f = 3.5 MHz

f = 20 MHz

f = 3.5 MHz

f = 20 MHz

f = 3.5 MHz

f = 20 MHz

f = 3.5 MHz

f = 20 MHz

f = 3.5 MHz

f = 20 MHz

f = 3.5 MHz

f = 20 MHz

f = 3.5 MHz

f = 20 MHz

MIN

TYP

9.2

9

MAX

UNIT

8.7

ADS5102

Bits

ENOB

SFDR

THD

Effective number of bits

9.0

58

64

9.3

9.2

73

ADS5103

ADS5102

ADS5103

ADS5102

ADS5103

ADS5102

ADS5103

ADS5102

ADS5103

Bits

dBc

71

Spurious free dynamic range

Total harmonic distortion

Signal-to-noise ratio

69

66

–71

–65

–68

58

–55

–62

56

57

54

56

57

SNR

59

58

57

SINAD

Signal-to-noise and distortion

58

57

†

power supply

PARAMETER

TEST CONDITIONS

MIN

1.65

TYP

1.8

70

MAX

2

UNIT

AV

DD

DV

2

Operating voltage

V

DD

DRV

3.6

80

53

9

DD

ADS5102

ADS5103

ADS5102

ADS5103

ADS5102

ADS5103

ADS5102

ADS5103

ADS5102

ADS5103

I(AV

DD

)

Analog supply current

Digital supply current

Output driver supply current

Total current consumption

Power dissipation

AV

= DV

= 1.8 V,

DRV

= 3.3 V

mA

mW

DD

45

8

I(DV

DD

)

= DV = 1.8 V,

DD

5

7

6.5

4.8

84

8

I(DRV

)

= DV

= 1.8 V,

DD

5.5

97

66

188

126

390

I

(TOTAL)

54

160

105

336

0.25

P

D

Standby power

CLK running

µW

Power supply rejection

%FS

†

Sinewave input, f = 3.5 MHz, –1 dBFS input span

i

6

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ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

electrical characteristics over recommended operating conditions, AV

= DV

= 1.8 V,

DD

DRV

= 3.3 V, F = 40, 65 MSPS (as appropriate)/50% duty cycle, –1 dBFS input span, C = 10 pF

DD

s

L

at D0–D9, internal reference, T

to T

, typical data at 25°C (unless otherwise noted)

(max)

(min)

(continued)

timing characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

%

Clock duty cycle

50 ±10

t

Output propagation delay

9

6

12

ns

d(o)

OE ↓ to outputs enabled time

ns

(en)

OE ↑ rising to outputs 3-state disable time

Pipeline latency

10

5.5

1

ns

dis

cyc

ns

d(latency)

d(ap)

Aperture delay

Aperture uncertainty

2

ps rms

timing diagram

S1

S2

S3

Analog

CLK

10

1

2

3

4

5

6

7

8

9

t

d(latency)

OE

t

(en)

d(o)

S1

dis

S3

D[0–9]

S2

7

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ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

TYPICAL CHARACTERISTICS

ADS5103

ANALOG SUPPLY CURRENT

vs

ADS5102

ANALOG SUPPLY CURRENT

vs

TEMPERATURE

50.0

49.5

49.0

48.5

48.0

47.5

47.0

46.5

46.0

45.5

45.0

78

77

76

75

74

73

72

71

AV

DRV

= DV

= 1.8 V

AV

DRV

= DV

= 1.8 V

DD

= 3.3 V

DD

= 3.3 V

DD

= 40 MHz

DD

= 65 MHz

F

clk

F

clk

f = 19.99 MHz at –1 dBFS

f = 32.49 MHz at –1 dBFS

i

–40–30–20–10 0 10 20 30 40 50 60 70 80 90

T – Temperature – °C

Figure 1

Figure 2

ADS5102

DIGITAL SUPPLY CURRENT

vs

ADS5103

DIGITAL SUPPLY CURRENT

vs

TEMPERATURE

20.0

19.5

19.0

18.5

18.0

17.5

17.0

16.5

16.0

15.5

15.0

15

14

13

12

11

10

9

AV

= DV

= 1.8 V

AV

= DV

= 1.8 V

DD

= 3.3 V

= 65 MHz

DD

= 3.3 V

= 40 MHz

DRV

DD

DRV

DD

F

clk

f = 32.49 MHz at –1 dBFS

clk

f = 19.99 MHz at –1 dBFS

i

8

7

6

5

–40–30–20–10 0 10 20 30 40 50 60 70 80 90

T – Temperature – °C

Figure 3

Figure 4

8

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ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

TYPICAL CHARACTERISTICS

ADS5102

INTEGRAL NONLINEARITY

vs

ADS5103

INTEGRAL NONLINEARITY

vs

TEMPERATURE

2.05

1.85

1.65

1.45

1.25

1.05

0.85

0.65

0.45

0.25

2.05

1.85

1.65

1.45

1.25

1.05

0.85

0.65

0.45

0.25

AV

= DV

= 1.8 V

AV

DRV

DD

F

clk

= DV

= 1.8 V

DD

= 3.3 V

= 65 MHz

DD

= 3.3 V

= 40 MHz

DRV

DD

F

clk

–40–30–20–10 0 10 20 30 40 50 60 70 80 90

T – Temperature – °C

Figure 5

Figure 6

ADS5102

DIFFERENTIAL NONLINEARITY

0.4

0.3

0.2

0.1

0

AV

= DV

= 1.8 V

DD

= 3.3 V

= 65 MHz

DRV

DD

F

clk

–0.1

–0.2

–0.3

0

64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024

Code

Figure 7

9

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ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

TYPICAL CHARACTERISTICS

ADS5103

DIFFERENTIAL NONLINEARITY

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

AV

= DV

= 1.8 V

DD

= 3.3 V

= 40 MHz

DRV

DD

–0.4

–0.5

F

clk

0

64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024

Code

Figure 8

ADS5102

INTEGRAL NONLINEARITY

0.8

0.6

0.4

0.2

0

AV

= DV

= 1.8 V

DD

= 3.3 V

= 65 MHz

DRV

DD

F

clk

–0.2

–0.4

–0.6

–0.8

0

64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024

Code

Figure 9

ADS5103

INTEGRAL NONLINEARITY

0.8

0.6

0.4

0.2

AV

= DV

= 1.8 V

DD

= 3.3 V

= 40 MHz

DRV

DD

F

clk

0

–0.2

–0.4

–0.6

0

64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024

Code

Figure 10

10

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ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

TYPICAL CHARACTERISTICS

ADS5102

INTERNAL VREF VALUES

vs

ADS5102

INTERNAL VREF VALUES

vs

TEMPERATURE

ANALOG SUPPLY VOLTAGE

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

AV

DRV

= DV

= 1.8 V

DD

DV

DRV

= 1.8 V

= 3.3 V

= 65 MHz

DD

= 3.3 V

DD

F

clk

= 65 MHz

F

clk

f = 32.49 MHz at –1 dBFS

i

REFT

REFB

REFT-REFB

–40–30–20–10 0 10 20 30 40 50 60 70 80 90

1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10

T – Temperature – °C

Analog Supply Voltage – V

Figure 11

Figure 12

ADS5103

SPURIOUS FREE DYNAMIC RANGE

vs

ADS5102

SPURIOUS FREE DYNAMIC RANGE

vs

ANALOG INPUT LEVEL

80

75

70

65

60

55

50

80

75

70

65

60

55

50

AV

DRV

= DV

= 1.8 V

AV

DRV

= DV

= 1.8 V

DD

= 3.3 V

DD

= 3.3 V

DD

= 40 MHz

DD

= 65 MHz

F

clk

F

clk

f = 19.99 MHz

f = 32.49 MHz

i

–20 –18 –16 –14 –12 –10 –8 –6 –4 –2

0

–20 –18 –16 –14 –12 –10 –8 –6 –4 –2

0

Analog Input Level – dB

Figure 13

Figure 14

11

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ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

TYPICAL CHARACTERISTICS

ADS5102

TOTAL HARMONIC DISTORTION

vs

ADS5103

TOTAL HARMONIC DISTORTION

vs

ANALOG INPUT FREQUENCY

–66

–68

–70

–72

–74

–76

–78

–80

–60

–62

–64

–66

–68

–70

AV

DRV

DD

= DV

= 1.8 V

DD

= 3.3 V

= 40 MHz

F

clk

f = 1–19.99 MHz at –1 dBFS

i

AV

= DV

= 1.8 V

DD

= 3.3 V

= 65 MHz

DRV

DD

F

clk

f = 1–32 MHz at –1 dBFS

i

0

4

8

12

16

20

24

28

32

0

2

4

6

8

10 12 14 16 18 20

Analog Input Frequency – MHz

Figure 15

Figure 16

ADS5102

SIGNAL-TO-NOISE RATIO

vs

ADS5103

SIGNAL-TO-NOISE RATIO

vs

ANALOG INPUT FREQUENCY

61

60

59

58

57

56

61

60

59

58

57

56

AV

DRV

= DV

= 1.8 V

AV

DRV

= DV

= 1.8 V

DD

= 3.3 V

DD

= 3.3 V

DD

= 65 MHz

DD

= 40 MHz

F

clk

F

clk

f = 1–32 MHz at –1 dBFS

f = 1–19.99 MHz at –1 dBFS

i

0

4

8

12

16

20

24

28

32

0

2

4

6

8

10 12 14 16 18 20

Analog Input Frequency – MHz

Figure 17

Figure 18

12

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ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

TYPICAL CHARACTERISTICS

ADS5102

SIGNAL-TO-NOISE RATIO and DISTORTION

vs

ADS5103

SIGNAL-TO-NOISE RATIO and DISTORTION

vs

ANALOG INPUT FREQUENCY

61

60

59

58

57

56

61

60

59

58

57

56

AV

DRV

= DV

= 1.8 V

AV

DRV

= DV

= 1.8 V

DD

= 3.3 V

DD

= 3.3 V

DD

= 65 MHz

DD

= 40 MHz

F

clk

F

clk

f = 1–32 MHz at –1 dBFS

f = 1–19.99 MHz at –1 dBFS

i

0

4

8

12

16

20

24

28

32

0

2

4

6

8

10 12 14 16 18 20

Analog Input Frequency – MHz

Figure 19

Figure 20

ADS5102

EFFECTIVE NUMBER OF BITS

vs

ADS5103

EFFECTIVE NUMBER OF BITS

vs

ANALOG INPUT FREQUENCY

11.0

10.5

10.0

9.5

11.0

10.5

10.0

9.5

AV

DRV

= DV

= 1.8 V

AV

DRV

= DV

= 1.8 V

DD

= 3.3 V

DD

= 3.3 V

DD

= 65 MHz

DD

= 40 MHz

F

clk

F

clk

f = 1–32 MHz at –1 dBFS

f = 1–19.99 MHz at –1 dBFS

i

9.0

8.5

8.0

0

4

8

12

16

20

24

28

32

0

2

4

6

8

10 12 14 16 18 20

Analog Input Frequency – MHz

Figure 21

Figure 22

13

www.ti.com

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

TYPICAL CHARACTERISTICS

ADS5103

SPURIOUS FREE DYNAMIC RANGE

vs

ADS5102

SPURIOUS FREE DYNAMIC RANGE

vs

ANALOG INPUT FREQUENCY

70

69

68

67

66

65

64

63

62

61

60

80

78

76

74

72

70

68

AV

DRV

= DV

= 1.8 V

DD

= 3.3 V

DD

= 40 MHz

F

clk

f = 1–19.99 MHz at –1 dBFS

i

AV

DRV

= DV

= 1.8 V

DD

= 3.3 V

DD

= 65 MHz

F

clk

f = 1–32 MHz at –1 dBFS

i

0

2

4

6

8

10 12 14 16 18 20

0

4

8

12

16

20

24

28

32

Analog Input Frequency – MHz

Figure 23

Figure 24

ADS5103

SFDR, SINAD

vs

ADS5102

SFDR, SINAD

vs

CLOCK DUTY CYCLE

75

70

65

60

55

50

45

80

75

70

65

60

55

50

45

40

35

SFDR

SINAD

AV

DRV

= DV

= 1.8 V

AV

DRV

= DV

= 1.8 V

DD

= 3.3 V

DD

= 3.3 V

DD

= 40 MHz

DD

= 65 MHz

F

clk

F

clk

f = 3.58 MHz at –1 dBFS

i

30

35

40

45

50

55

60

65

70

30

35

40

45

50

55

60

65

70

Clock Duty Cycle – %

Figure 25

Figure 26

14

www.ti.com

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

TYPICAL CHARACTERISTICS

ADS5102

SFDR, SINAD

vs

ADS5103

SFDR, SINAD

vs

CLOCK DUTY CYCLE

80

75

70

65

60

55

50

45

40

35

75

70

65

60

55

50

45

SFDR

SINAD

AV

DRV

= DV

= 1.8 V

AV

DRV

= DV

= 1.8 V

DD

= 3.3 V

DD

= 3.3 V

DD

= 65 MHz

DD

= 40 MHz

F

clk

F

clk

f = 32.49 MHz at –1 dBFS

f = 19.99 MHz at –1 dBFS

i

30

35

40

45

50

55

60

65

70

30

35

40

45

50

55

60

65

70

Clock Duty Cycle – %

Figure 27

Figure 28

PRINCIPLES OF OPERATION

analog-to-digital converter

The ADS5102/3 is designed using a switched capacitor pipeline architecture fabricated in CMOS process. The

pipeline architecture is implemented with 10 stages, thus allowing for high conversion speed and exceptionally

low power. Each of these 10 stages produces one digital bit per stage. Both rising and falling edges of the clock

are used so the signal propagates thru the pipeline every half clock or five total clocks. Digital error correction

uses another 1/2 clock cycle at the end; thus the total pipeline latency is 5.5 clocks. (Refer to timing diagram

on page 7)

10-stage operation

The signal is sampled by the SHA. The first stage is digitized by 1.5 bits and sent to the digital error correction

block. This digitized value is then applied to a DAC, which recreates the analog value that has been digitized.

This value is then fed into a summing junction with the original input signal. The summing junction subtracts the

converted value from the original signal. This is known as the residue voltage. This residue voltage is then

amplified by a factor of 2x and transferred to the next stage. This is repeated for each of the 10 stages.

Each of the 10 pipeline stages, as well as the sample and hold amplifier, is differential in nature. This allows

rejection of any common mode signal. Thus a signal seen on Ain+ and Ain– is differentially seen as 0 V on the

output. This fully differential architecture allows higher ac performance of the ADC by reducing noise

susceptibility.

15

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ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

PRINCIPLES OF OPERATION

analog input sample and hold amplifier circuit

The sample and hold amplifier is implemented using switch capacitor techniques. A simplified functional block

diagram is shown in Figure 29. The SHA is in sample mode when CLK is high and in hold mode when CLK is

low. In sample mode, the input switches, P1, are closed and the differential input signal is sampled onto caps

Cs. An internal common-mode voltage is applied to the sampling caps (C ) when the two P1P switches are

s

closed. As the CLK falling edge occurs, the SHA is now placed into hold or amplification mode. In this mode,

P1 switches are now opened and switches P2 are closed. This is the amplification state and the signal is

transferred to the output of the amplifier with a nominal gain of 1. C of Figure 29 represents the load

L

capacitance of the following stage. R-C values of the input determine the analog input bandwidth of the SHA

(and therefore the whole ADC) which is 950 MHz for the ADS5102/3. This wide bandwidth assures no distortion

to the Nyquist frequency of 32.5 MHz. In under sampling applications, it is common to require the analog input

bandwidth to be 5 times greater than the IF Nyquist frequency. As such, the ADS5102/3 supports IF frequencies

approaching 200 MHz in under sampling applications.

P2

P1

V

INP

C

S

_

+

C

+

_

L

P1

P1P

V

C

I

V

IN

P1

P2

Figure 29. Simplified Functional Block Diagram

Becausetheinputtothesampleandholdamplifierisaswitchedcapacitorcircuit, theinputresistanceisdynamic

and based on the sampling rate of the converter. The impedance of each input is defined by the equation:

1

Z +

Where:

I

F C

s

C = Sampling capacitor = 0.4 pF typical

s

F = CLK frequency in Hz

The key for selecting an amplifier to correctly drive the ADS5102/3 is to ensure that the output frequency of the

amplifier is much lower than the input impedance of the ADS5102/3, which at 65 MSPS is 38.46 kΩ . For system

accuracy comparable to 1 LSB, this means selecting an amplifier with output impedance of ~ 31 Ω for sampling

rates of 65 MSPS.

reference configurations

The ADS5102/3 provides an internal voltage reference which should be suitable for most 10 bit systems. The

typical full scale voltage for the device is determined by VFS = VREFT – VREFB. Since the input is fully

differential, the full scale input is twice the single ended value or 1 V differential. It is recommended to externally

de-couple both VREFT and VREFB with a 0.1 µF capacitor to bypass all high frequency noise to ground. It is

necessary to connect BG and AV

to Figure 30 for correct configuration).

with a 100 kΩ resistor and decouple with a 1 µF capacitor to AGND (refer

DD

16

www.ti.com

ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

PRINCIPLES OF OPERATION

AV

DD

100 kΩ

BG

1 µF

Figure 30. BG Reference Configuration

For systems that require more absolute accuracy or lower temperature coefficient drift than provided by the

internal VREF, an external voltage reference can be applied to the VREFB and VREFT inputs. To use external

reference, connect the PDREF pin to a logic high and this internally disconnects the VREF from the ADC. In

this mode it is also necessary to connect the BG and REFT pins together on the PWB. It is recommended to

use the input levels of VREFB = 0.75 V and VREFB = 1.25 V to achieve optimum ADC performance. It is also

recommended to apply a common-mode voltage to the input of 1 V.

clock input

The clock input is designed for 1.8 V or 3.3 V CMOS logic levels (depends on DR

to use standard CMOS logic levels as inputs. The logic threshold internally is set to DRV /2 or nominally 1.65

) and it is recommended

VDD

DD

V. Since both edges of the clock are used in the switch capacitor architecture, it is important to provide a clock

with (ideally) a 50% duty cycle. The performance variation with clock duty cycle can be examined from

Figures 25, 26, 27 and 28.

ClockjitterisalsoimportantforperformanceoftheADCtobemaintained. Anyclockjitterappearsasnoisewhen

sampling input frequencies. Clock Jitter reduces the signal to noise ratio (SNR) and is more severe as the input

frequency increases. The theoretical SNR limits based on clock jitter can be calculated as follows:

1

Theoretical SNR

Where:

(dB) + 20 log

ǒ

Ǔ

(clock jitter)

2 p F CLK

I

(jitter)

F = Highest input frequency to the ADC in Hz

I

CLK

= the amount of jitter on the clock in sec

(jitter)

Therefore for a Nyquist frequency input of 32.5 MHz and a design trying to achieve the most available

performance from the ADS5102/3, the clock jitter must be less than 3.98 ps rms. In under sampling applications,

the same equations apply and clock jitter becomes more critical and may be the limiting factor in system

performance. The aperture jitter of the SHA also contributes to overall jitter. For worst case designs, the jitter

of clock and aperture can be considered to add in quadrature, i.e.

2

Total Jitter = Square root of ( CLK

+ Aperture

)

jitter

The aperture jitter of the ADS5103 is 2 ps rms and at frequencies approaching Nyquist, the total jitter should

be accounted for.

17

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ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

PRINCIPLES OF OPERATION

digital outputs

The outputs of the ADS5102/3 are also CMOS and are programmable for either 3.3 V or 1.8 V CMOS logic

levels. This is controlled by the DRV supply. Either 3.3 V or 1.8 V can be applied to DRV with excellent

DD

results. The output format is offset binary with D0 (LSB) and D9 (MSB). See Table 1 for output coding with a

differential input signal applied. There is a 5.5 clock latency from the sampling to valid data output on D0–D9.

The outputs can be placed into active mode by taking OE low or 3-state by taking OE high. The timing relations

between OE and output bus enable/disable times are shown in the timing diagram (refer to page 7). The

capacitive loading on the digital outputs is very important to achieve best performance. The total load

capacitance is typically made up of two sources, next stage input capacitance and PWB etch run capacitance.

The total capacitance of these two loads should be held to less than 15 pF. If for some reason, this cannot be

met, it is recommended to use logic buffers such as ‘244 placed physically very close to the ADC output. This

isolates the ADC output from the load capacitance and performance specs are achieved. Another technique

is to place a small resistor in series with the outputs. This resistance dampens the current spikes into the

capacitive loads and thus improve ADC performance. The value of this resistor varies with sampling rate but

generally 22 Ω is a good value. Again this depends on the load capacitance.

The digital output of these devices is offset binary and follows the following format.

Table 1. Output Coding

DIGITAL OUTPUT CODE

ANALOG INPUT

IN +

SIGNAL VOLTAGE

STEP

IN –

MSB

LSB

†

REFT

REFB

1023

1

•

1

•

1

•

1

•

1

•

1

•

1

•

1

•

1

•

1

•

512

511

•

(REFT – REFB) / 2

1

0

•

0

1

•

0

1

•

0

1

•

0

1

•

0

1

•

0

1

•

0

1

•

0

1

•

0

1

•

REFB

REFT

0

†

Where there is either an internal voltage reference or an external voltage reference applied to the REFT and REFB pins.

driving the analog input

Since many real world signals are single ended and most modern high speed ADC’s employ differential inputs,

it is necessary in many cases to perform single ended to differential conversion prior to the ADC. Also, the ADC

performs optimally if a differential signal is applied to the inputs. In some cases, signal conditioning is required

in the form of the amplification or filtering. The two preferred techniques for driving the ADC input are: 1) With

an active amplifier specifically designed to drive ADC’s; 2) With an RF transformer.

driving the analog input with a differential amplifier

Texas Instruments has developed a family of high quality operational amplifiers that have been designed

specifically for driving the input stage of modern ADC’s. These devices allow for amplification and filtering prior

to the ADC. This stage can be used to set the maximum signal voltage to match the full scale input of the ADC.

The best solution for driving the ADS5102/3 ADC’s is the THS4501 amplifier. Figure 31 shows how to use this

device with a gain of 2. The ADC common mode output voltage can be directly connected to the op amp to

provide the proper levels. The THS4501 provides optimum matching of op amp output to the input of the

ADS5102/3. This configuration provides signal amplification, filtering, and single-ended to differential

conversion. It is recommended to provide de-coupling capacitors of 0.1 µF and 0.001 µF on the CML output.

This filters out any high frequency noise prior the ADC input.

18

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ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

PRINCIPLES OF OPERATION

750 Ω

49.9 Ω

THS4501

AIN–

374 Ω

V

+

_

(source)

68 pF

ADS5102,

ADS5103

V

O–

Digital

Outputs

V

O+

VOCM

49.9 Ω

AIN+

CML

750 Ω

0.1 µF

0.001 µF

Figure 31. Driving the ADS5102/3 With Differential Amp (Gain = 2)

driving the analog input with a transformer

When little or no signal conditioning is required, a simple transformer is an excellent way to drive the input of

the ADS5102/3 family. The transformer provides single-ended to differential conversion and at frequencies

under 200 MHz produces very little distortion of the incoming signal. Figure 32 shows the preferred circuit

diagram for implementing a transformer-coupled input. The signal source is ac-coupled and fed to the primary

side of the RF transformer. Since the ADC input must be biased to the correct common mode voltage, the CML

output of the ADC is connected to the secondary center tap. It is recommended to provide decoupling capacitors

of 0.1 µF and 0.001 µF on the CML output. This filters out any high frequency noise prior the ADC input.

0.1 µF

V

AIN–

(source)

ADS5102,

ADS5103

Digital

Outputs

49.9 Ω

CML

AIN+

T1 – 1T-KK81

Mini-Circuits

0.001 µF

0.1 µF

Figure 32. Driving the ADS5102/3 With a Transformer

19

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ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

PRINCIPLES OF OPERATION

REFT

AIN+

3 kΩ

AIN+

ADS5102

ADS5103

AIN–

3 kΩ

REFB

Figure 33. Driving the Analog Inputs

setting the bias resistor—RBIAS

Each device in this family requires an external resistor be connected from pin 14 to ground. The value of this

resistor is determined by which device is being used. Refer to Table 2 for the correct resistor value. This resistor

only dissipates less than 1 mW of power. The resistor accuracy of 1% is adequate.

Table 2. Resistor Value

DEVICE

ADS5103

ADS5102

RBIAS VALUE

8.25 kΩ

CONNECT FROM

Pin 14 to AGND

4.42 kΩ

20

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ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

DEFINITION OF SPECIFICATIONS

Analog Input Bandwidth—The analog input frequency at which the spectral power of the fundamental

frequency (as determined by the FFT analysis) is reduced by 3 dB.

Aperture Delay—The delay between the 50% point of the rising edge of the clock and the instant at which the

analog input is sampled.

Aperture Uncertainity (Jitter)—The sample-to-sample variation in aperture delay.

Differential Nonlinearity (DNL)—The maximum deviation of any single LSB transition at the digital output from

an ideal 1 LSB step at the analog input. Ideally, each transition step is 1 LSB wide. DNL is the measured error

from theoretical in step size. A DNL of less than –1 LSB implies no missing codes.

Integral Nonlinearity (INL)—is the summation of the differential nonlinearity errors and indicates the worst

case deviation from an best fit straight line that is drawn from 1/2 LSB of the first transition to 1/2 LSB above

the last transition. The best fit is determined using the least squares curve fitting method.

Duty Cycle—is the ratio of the clock time high over the full clock period (time high plus time low) and then also

the time low over the total clock period. At a given clock rate, these specs define the acceptable duty cycle

allowed on the clock.

Sampling Rate (Fs)—The rate at which the converter tested to ensure conversion of analog signals to digital.

The maximum rate specified is the rate and which the device is production tested to ensure performance specs

are met. Expressed in mega samples per second (MSPS).

Output Propagation Delay—The delay between the 50% point of the falling edge of clock signal and the time

when all output data bits are within valid logic levels.

OffsetError—In an ideal ADC the first transition from 0000000000 should occur at 1/2 LSBaboveREFB. Offset

Error is defined as the difference between this ideal first transition and the voltage level where the first transition

actuallyoccurs. Expressedin%fullscalerange(%FSR)butmayalsobeexpressedinvolts. Thiscanbethought

of as shifting the transfer function either left or right along the X-axis.

Overvoltage Recovery Time—The amount of time required for the converter to recover to 0.2% accuracy after

an analog input signal 150% of full scale is reduced to midscale.

Power Supply Rejection Ratio—The ratio of a change in input offset voltage to a change in power supply

voltage.

Total Harmonic Distortion (THD)—The ratio of the peak signal amplitude to the summation of the harmonic

components. This is expressed in – dB. THD = 20 Log [input amplitude/(summation of harmonic bins)]. For

calculation purposes, the first 7 harmonics are included in the calculations.

Signal To Noise Distortion (SINAD)—The ratio of the rms signal amplitude (set 1 dB below full scale) to rms

value of the sum of all other spectral noise and harmonic components, but excluding dc.

Signal to Noise Ratio (SNR)—The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms

value of the the sum of all other spectral components, excluding the first five harmonics and dc. Reported in

dB.

Spurious Free Dynamic Range (SFDR)—The difference between the peak amplitude of a fundamental input

sine wave and the largest peak spurious component that appears, excluding dc and the input. The peak

spurious component may or may not be a harmonic frequency. May be reported in dBc (i.e., degrades as signal

levels is lowered), or in dBFS (always related back to converter full scale).

21

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ADS5102

ADS5103

SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001

MECHANICAL DATA

PFB (S-PQFP-G48)

PLASTIC QUAD FLATPACK

0,27

0,50

M

0,08

0,17

36

25

37

24

48

13

0,13 NOM

1

12

5,50 TYP

7,20

SQ

Gage Plane

6,80

9,20

SQ

8,80

0,25

0,05 MIN

0°–ā7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4073176/B 10/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

22

www.ti.com

IMPORTANT NOTICE

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enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

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and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

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Mailing Address:

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Post Office Box 655303

Dallas, Texas 75265


型号：	ADS5102CPFB
厂家：	TEXAS INSTRUMENTS
描述：	1.8-V ANALOG SUPPLY, 10-BIT, 65/40 MSPS ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE 1.8 V模拟电源， 10位， 65/40 MSPS模拟数字转换器具有内部参考转换器
文件：	总23页 (文件大小：335K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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