ADS5401IZAYR [TI]
12 位、800MSPS 模数转换器 (ADC) | ZAY | 196 | -40 to 85;
| 型号： | ADS5401IZAYR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12 位、800MSPS 模数转换器 (ADC) | ZAY | 196 | -40 to 85 转换器 模数转换器 |
| 文件： | 总41页 (文件大小：1632K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS5409
www.ti.com
SLAS935 –MAY 2013
Dual Channel 12-Bit 900Msps Analog-to-Digital Converter
Check for Samples: ADS5409
1
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
Dual Channel
•
•
•
•
•
•
•
•
•
Test and Measurement Instrumentation
Ultra-Wide Band Software Defined Radio
12-Bit Resolution
Maximum Clock Rate: 900 Msps
Low Swing Full-Scale Input: 1.0 Vpp
Analog Input Buffer with High Impedance Input
Input Bandwidth (3dB): >1.2GHz
Data Output Interface: DDR LVDS
Data Acquisition
Power Amplifier Linearization
Signal Intelligence and Jamming
Radar and Satellite Systems
Microwave Receivers
Optional 2x Decimation with Low Pass or High
Pass Filter
Cable Infrastructure
Non-Destructive Testing
•
•
196-Pin BGA Package (12x12mm)
KEY SPECIFICATIONS
Number of
Device Part No.
Speed Grade
Channels
–
–
Power Dissipation: 1.1W/ch
ADS5402
ADS5401
ADS5404
ADS5403
ADS5407
ADS5409
2
1
2
1
2
2
800Msps
800Msps
500Msps
500Msps
500Msps
900Msps
Spectral Performance at fin = 230 MHz IF
–
–
SNR: 61.0 dBFS
SFDR: 76 dBc
–
Spectral Performance at fin = 700 MHz IF
–
–
SNR: 59.4 dBFS
SFDR: 70 dBc
DESCRIPTION
The ADS5409 is a high linearity dual channel 12-bit, 900 Msps analog-to-digital converter (ADC) easing front end
filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the on-chip
track-and-hold from disturbing the signal source as well as providing a high-impedance input. Optionally the
output data can be decimated by two. Designed for high SFDR, the ADC has low-noise performance and
outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196pin
BGA package and is specified over the full industrial temperature range (–40°C to 85°C).
12bit
900Msps
Digital
Block
INA
DA[11:0]
DACLK
Clk
Buffer
CLKIN
SYNCIN
12bit
900Msps
Digital
Block
INB
DB[11:0]
DBCLK
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
ADS5409
SLAS935 –MAY 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DETAILED BLOCK DIAGRAM
SCLK
PROGRAMMING
DATA
SDIO
SDO
CONTROL
OVERRANGE
THRESHOLD
VREF
VCM
VOLTAGE
SDENB
REFERENCE
CLKOUT
DACLKP/N
DC or
Fs/2
GEN
BUFFER
INTERLEAVING
CORRECTION
Estimator
INA_P/N
ADC
DEC
x2
FIR FILTER
Gain Correction
Offset Correction
DA[11:0]P/N
CLOCK
CLKP/N
DISTRIBUTION
MULTICHIP
SYNC
SYNCP/N
DB[11:0]P/N
INTERLEAVING
CORRECTION
DEC
x2
FIR FILTER
INB_P/N
ADC
Estimator
Gain Correction
Offset Correction
DC or
Fs/2
CLKOUT
GEN
BUFFER
DBCLKP/N
OVERRANGE
THRESHOLD
SYNCOUTP/M
SYNCOUTP/N
Figure 1. Detailed Block Diagram
2
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SLAS935 –MAY 2013
PINOUT INFORMATION
A
B
C
D
E
F
G
H
J
K
L
M
N
P
14
13
12
11
10
9
VREF
SDENB
SCLK
SDIO
SDO
VCM
GND
GND
GND
GND
GND
GND
DVDD
INB_N
GND
INB_P
GND
GND
GND
AVDDC AVDDC
GND
GND
INA_P
GND
INA_N
GND
GND
GND
GND
GND
GND
GND
DVDD
GND
GND
CLKINP
14
13
12
11
10
9
TEST
GND
GND
CLKINN
MODE
SRESET
B
AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 AVDD33
AVDD18 AVDD18 AVDD18 AVDD18 AVDD18 AVDD18 AVDD18 AVDD18
AVDD33 AVDD33
AVDD18 AVDD18
ENABLE
IOVDD
DVDD
DVDD
DB0P
DB1P
DB2P
DB3P
DB4P
DB5P
DB6P
B
AVDD18
GND
GND
GND
GND
GND
GND
GND
NC
GND
GND
GND
GND
GND
GND
NC
GND
GND
GND
GND
GND
GND
NC
GND
GND
GND
GND
GND
GND
DA0P
DA0N
GND
GND
GND
GND
GND
GND
DA2P
DA2N
DA1P
DA1N
J
GND
GND
GND
GND
GND
GND
DA4P
DA4N
DA3P
DA3N
K
AVDD18
GND
NC
NC
DVDD
DVDD
DB0N
DB1N
DB2N
DB3N
DB4N
DB5N
DB6N
A
SYNCN SYNCP
8
DVDD
DVDD
DVDD
NC
DVDD
NC
8
DVDD
LVDS
DVDD
LVDS
DVDD
LVDS
DVDD
LVDS
7
7
DVDD
LVDS
DVDD
LVDS
DVDD
LVDS
DVDD
LVDS
6
NC
NC
6
SYNC
OUTN
SYNC
OUTP
5
OVRBN OVRBP
OVRAN OVRAP
5
4
DB8P
DB8N
DB7P
DB7N
C
DB10P
DB10N
DB9P
DB9N
D
DA6P
DA6N
DA5P
DA5N
L
DA8P
DA8N
DA7P
DA7N
M
NC
DA11N
DA10N
DA9N
N
NC
DA11P
DA10P
DA9P
P
4
3
NC
NC
NC
3
SYNC
OUTP
2
DB11P
DB11N
E
DBCLKP DACLKP
DBCLKN DACLKN
2
SYNC
OUTN
1
1
F
G
H
Figure 2. Pinout in DDR output mode (top down view)
PIN ASSIGNMENTS
PIN
I/O
DESCRIPTION
NAME
NUMBER
INPUT/REFERENCE
INA_P/N
K14, L14
D14, E14
I
I
Analog ADC A differential input signal.
Analog ADC B differential input signal.
INB_P/N
Output of the analog input common mode (nominally 1.9V). A 0.1μF capacitor to AGND is
recommended.
VCM
B14
A14
O
O
Reference voltage output (2V nominal). A 0.1μF capacitor to AGND is recommended, but not
required.
VREF
CLOCK/SYNC
CLKINP/N
P14, P13
P9, N9
I
I
Differential input clock
Synchronization input. Inactive if logic low. When clocked in a high state initially, this is used
for resetting internal clocks and digital logic and starting the SYNCOUT signal. Internal 100Ω
termination.
SYNCP/N
CONTROL/SERIAL
Serial interface reset input. Active low. Initialized internal registers during high to low
transition. Asynchronous. Internal 50kΩ pull up resistor to IOVDD.
SRESET
B12
I
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PIN ASSIGNMENTS (continued)
PIN
I/O
DESCRIPTION
NAME
ENABLE
SCLK
NUMBER
B11
Chip enable – active high. Power down function can be controlled through SPI register
assignment. Internal 50kΩ pull up resistor to IOVDD.
I
I
A12
Serial interface clock. Internal 50kΩ pull-down resistor.
Bi-directional serial data in 3 pin mode (default). In 4-pin interface mode (register x00, D16),
the SDIO pin is an input only. Internal 50kΩ pull-down.
SDIO
A11
I/O
I
SDENB
SDO
A13
Serial interface enable. Internal 50kΩ pull-down resistor.
Uni-directional serial interface data in 4 pin mode (register x00, D16). The SDO pin is tri-
stated in 3-pin interface mode (default). Internal 50kΩ pull-down resistor.
A10
O
–
TESTMODE
B13
Factory internal test, do not connect
DATA INTERFACE
P3, N3, P2, N2,
P1, N1, M4, M3,
M2, M1, L4, L3,
L2, L1, K4, K3,
K2, K1, J4, J3,
J2, J1, H4, H3
DA[11:0]P/N
DB[11:0]P/N
O
O
ADC A Data Bits 11 (MSB) to 0 (LSB) in DDR output mode. Standard LVDS output.
E2, E1, D4, D3,
D2, D1, C4, C3,
C2, C1, B1, A1,
B2, A2, B3, A3,
B4, A4, B5, A5,
B6, A6, B7, A7
ADC B Data Bits 11 (MSB) to 0 (LSB) in DDR output mode. Standard LVDS output.
DDR differential output data clock for Bus A. Register programmable to provide either rising
or falling edge to center of stable data nominal timing.
DACLKP/N
DBCLKP/N
H2, H1
O
O
DDR differential output data clock for Bus B. Register programmable to provide either rising
or falling edge to center of stable data nominal timing. Optionally Bus B can be latched with
DACLKP/N.
G2, G1
SYNCOUTP/N
OVRAP/N
F2, F1, P5, N5
M5, L5
O
O
Synchronization output signal for synchronizing multiple ADCs. Can be disabled via SPI.
Bus A, Overrange indicator, LVDS output. A logic high signals an analog input in excess of
the full-scale range. Optional SYNC output.
Bus B, Overrange indicator, LVDS output. A logic high signals an analog input in excess of
the full-scale range. Optional SYNC output.
OVRBP/N
D5, C5
O
–
E3, E4, F3, F4,
G3, G4, N4, N6,
N7, N10, P4, P6,
P7, P10
NC
Don’t connect to pin
POWER SUPPLY
AVDD33
AVDDC
D12, E12, F12,
G12, H12, J12,
K12, L12, N12,
P12
I
I
I
3.3V analog supply
G14, H14
1.8V supply for clock input
1.8V analog supply
D10, D11, E11,
F11, G11, H11,
J11, K11, L10,
L11, N11, P11
AVDD18
A8, A9, B8, B9,
C8, D8, L8, M8,
N8, P8
DVDD
I
I
1.8V supply for digital block
1.8V supply for LVDS outputs
C6, C7, D6, D7,
L6, L7, M6, M7
DVDDLVDS
IOVDD
GND
B10
I
I
1.8V for digital I/Os
Ground
4
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SLAS935 –MAY 2013
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
LEAD/
BALL
FINISH
TRANSPORT
MEDIA,
QUANTITY
ECO
PLAN(2)
ORDERING
NUMBER
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
PACKAGE
MARKING
PRODUCT
GREEN
ADS5409IZAY
Tray
ADS5409
196-BGA
ZAY
–40C to 85C
ADS5409I
(RoHS & no
Sb/Br)
ADS5409IZAYR
Tape and Reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE
UNIT
MAX
MIN
Supply voltage range, AVDD33
Supply voltage range, AVDDC
Supply voltage range, AVDD18
Supply voltage range, DVDD
Supply voltage range, DVDDLVDS
Supply voltage range, IOVDD
INA/B_P, INA/B_N
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–40
4
V
V
2.3
2.3
V
2.3
V
2.3
V
4
AVDD33 + 0.5
AVDDC + 0.5
AVDD33 + 0.5
IOVDD + 0.5
85
V
V
CLKINP, CLKINN
Voltage applied to input pins
V
SYNCP, SYNCN
V
SRESET, SDENB, SCLK, SDIO, SDO, ENABLE
Operating free-air temperature range, TA
Operating junction temperature range, TJ
Storage temperature range
V
°C
°C
°C
kV
150
–65
150
ESD, Human Body Model
2
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
ADS5409
THERMAL METRIC(1)
nFBGA
196 PINS
37.6
UNITS
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
θJCtop
θJB
6.8
16.8
°C/W
ψJT
0.2
ψJB
16.4
θJCbot
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX UNIT
Recommended operating junction temperature
Maximum rated operating junction temperature(1)
105
°C
TJ
125
TA
Recommended free-air temperature
–40
25
85
°C
(1) Prolonged use at this junction temperature may increase the device failure-in-time (FIT) rate.
ELECTRICAL CHARACTERISTICS
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 900Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, –1dBFS differential input (unless
otherwise noted).
PARAMETER
ADC Clock Frequency
TEST CONDITIONS
MIN
100
12
TYP MAX UNITS
900 MSPS
Bits
Resolution
SUPPLY
AVDD33
3.15
1.7
3.3 3.45
1.8 1.9
V
V
V
AVDDC, AVDD18, DVDD, DVDDLVDS
IOVDD
1.7
1.8 3.45
POWER SUPPLY
IAVDD33
IAVDD18
IAVDDC
IDVDD
3.3V Analog supply current
1.8V Analog supply current
1.8V Clock supply current
1.8V Digital supply current
1.8V Digital supply current
1.8V Digital supply current
325 365
106 120
mA
mA
mA
mA
mA
mA
mA
mA
W
46
60
Auto Correction Enabled
370 420
214
IDVDD
Auto Correction Disabled
IDVDD
Auto Correction Disabled, decimation filter enabled
254
IDVDDLVDS 1.8V LVDS supply current
150 170
IIOVDD
Pdis
1.8V I/O Voltage supply current
Total power dissipation
1
2.27
1.9
2
Auto Correction Enabled, decimation filter disabled
Auto Correction Disabled, decimation filter disabled
250kHz to 500MHz
2.6
Pdis
Total power dissipation
W
PSRR
40
dB
Shut-down power dissipation
Shut-down wake up time
Standby power dissipation
Standby wake up time
7
2.5
7
mW
ms
mW
µs
100
435
570
20
Auto correction disabled
Auto correction enabled
mW
mW
µs
Deep-sleep mode power dissipation
Deep-sleep mode wakeup time
Light-sleep mode power dissipation
Light-sleep mode wakeup time
Auto correction disabled
Auto correction enabled
770
900
2
mW
mW
µs
6
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ELECTRICAL CHARACTERISTICS
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 900Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDD/DRVDD/IOVDD = 1.8V, –1dBFS differential input (unless otherwise noted).
PARAMETER
ANALOG INPUTS
TEST CONDITIONS
MIN
TYP MAX UNITS
Differential input full-scale
Input common mode voltage
Input resistance
1.0 1.25
1.9 ±0.1
Vpp
V
Differential at DC
1
2
kΩ
pF
Input capacitance
Each input to GND
VCM common mode voltage output
Analog input bandwidth (3dB)
DYNAMIC ACCURACY
1.9
V
1200
MHz
Auto Correction Disabled
Auto Correction Enabled
-20
-1
±6
0
20
1
mV
mV
Offset Error
Offset temperature coefficient
Gain error
-10
µV/°C
%FS
%FS/°C
LSB
-10
±2
10
Gain temperature coefficient
Differential nonlinearity
Integral nonlinearity
CLOCK INPUT
0.003
±0.8
±0.5
fIN = 230 MHz
fIN = 230 MHz
-1
2
-10
10
LSB
Input clock frequency
Input clock amplitude
Input clock duty cycle
Internal clock biasing
100
40
900
60
MHz
Vpp
%
2
50
0.9
V
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ELECTRICAL CHARACTERISTICS
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 900Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, –1dBFS differential input (unless
otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
58
65
65
63
56
63
TYP MAX
Enabled
MIN
TYP MAX UNITS
Auto Correction
DYNAMIC AC CHARACTERISTICS(1)
Disabled
Vpp
fIN = 10 MHz
61.5
61.5
61.0
60.2
59.4
78
61.5
61.4
61.0
60.3
59.8
81
fIN = 100 MHz
fIN = 230 MHz
fIN = 400 MHz
fIN = 700 MHz
fIN = 10 MHz
fIN = 100 MHz
fIN = 230 MHz
fIN = 400 MHz
fIN = 700 MHz
fIN = 10 MHz
fIN = 100 MHz
fIN = 230 MHz
fIN = 400 MHz
fIN = 700 MHz
fIN = 10 MHz
fIN = 100 MHz
fIN = 230 MHz
fIN = 400 MHz
fIN = 700 MHz
fIN = 10 MHz
fIN = 100 MHz
fIN = 230 MHz
fIN = 400 MHz
fIN = 700 MHz
fIN = 10 MHz
fIN = 100 MHz
fIN = 230 MHz
fIN = 400 MHz
fIN = 700 MHz
Signal to Noise Ratio
SNR
dBFS
(excluding Fs/2-Fin spur)
77
80
Second and third harmonic
distortion
HD2,3
77
77
dBc
dBc
71
72
75
76
78
78
Spur Free Dynamic Range
79
78
Non
HD2,3
(excluding second and third
harmonic distortion and
Fs/2 – FIN spur)
79
79
76
76
72
77
88
80
80
77
IL
Fs/2-Fin interleaving spur
76
71
dBc
72
68
70
66
61.3
61.2
60.9
59.7
59.2
74
61.3
61.2
60.8
59.8
59.5
74
Signal to noise and distortion
ratio
SINAD
dBFS
73
74
THD
Total Harmonic Distortion
Inter modulation distortion
75
74
dBc
68
68
72
72
Fin = 229.5 and 230.5 MHz,
-7dBFS
79
73
77
71
IMD3
dBFS
Fin = 649.5 and 650.5 MHz,
-7dBFS
Crosstalk
90
90
dB
Bit
ENOB
Effective number of bits
fIN = 230 MHz
9.8
9.8
(1) SFDR and SNR calculations do not include the DC or Fs/2 bins when Auto Correction is disabled.
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ELECTRICAL CHARACTERISTICS
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 900Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, –1dBFS differential input (unless
otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
OVER-DRIVE RECOVERY ERROR
Recovery to within 5% (of final value) for 6dB
overload with sine wave input
Output
Clock
Input overload recovery
2
SAMPLE TIMING CHARACTERISTICS
rms
Aperture Jitter
Sample uncertainty
100
38
fs rms
ADC sample to digital output, auto correction disabled
ADC sample to digital output, auto correction enabled
Clock
Cycles
50
Data Latency
Sampling
Clock
Cycles
ADC sample to digital output, Decimation filter
enabled, Auto correction disabled
74
12
Clock
Cycles
Over-range Latency
ADC sample to over-range output
ELECTRICAL CHARACTERISTICS
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1. AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
DIGITAL INPUTS – SRESET, SCLK, SDENB, SDIO, ENABLE
0.7 x
IOVDD
High-level input voltage
V
All digital inputs support 1.8V and 3.3V logic
levels.
0.3 x
V
Low-level input voltage
IOVDD
High-level input current
Low-level input current
–50
–50
200
µA
µA
pF
50
Input capacitance
5
DIGITAL OUTPUTS – SDO
IOVDD –
0.2
Iload = -100µA
High-level output voltage
V
V
0.8 x
IOVDD
Iload = -2mA
Iload = 100µA
Iload = 2mA
0.2
Low-level output voltage
0.22 x
IOVDD
DIGITAL INPUTS – SYNCP/N
VID
VCM
tSU
Differential input voltage
250
1.125
500
350
1.2
450
mV
V
Input common mode voltage
1.375
ps
DIGITAL OUTPUTS – DA[11:0]P/N, DACLKP/N, OVRAP/N, SYNCOUTP/N, DB[11:0]P/N, DBCLKP/N, OVRBP/N
VOD
Output differential voltage
Iout = 3.5mA
Iout = 3.5mA
250
350
450
mV
V
VOCM
Output common mode voltage
1.125
1.25
1.375
Fs = 900Msps, Data valid to zero-crossing of
DACLK, DBCLK
tsu
th
230
230
336
380
ps
ps
ns
Fs = 900Msps, Zero-crossing of DACLK,
DBCLK to data becoming invalid
Fs = 900Msps, CLKIN falling edge to
DACLK, DBCLK rising edge
tPD
3.36
3.69
3.92
tRISE
tFALL
10% - 90%
90% - 10%
100
100
150
150
200
200
ps
ps
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Data Latency ? Clock Cycles
SAMPLE N
CLKINP
tPD
DACLKP
DBCLKP
DCLK edges are centered within
the data valid window
DA[11:0]P/N
DB[11:0]P/N
OVRAP/N
N-1
N
N+1
ORVBP/N
CLKIN, DCLK are differential:
Only the ‘P’ positive signal shown for clarity
tsu
th
Figure 3. Timing Diagram for 12-bit DDR Output
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TYPICAL CHARACTERISTICS
Typical values at TA = +25°C, full temperature range is TMIN = -40°C to TMAX = +85°C, ADC sampling rate = 900Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, -1dBFS differential input, unless
otherwise noted.
FFT FOR 10 MHz INPUT SIGNAL (auto on)
FFT FOR 10 MHz INPUT SIGNAL (auto off)
0
−20
0
−20
SNR = 61.3dBFS
SFDR = 75dBc
THD = 72dBc
SNR = 61.5dBFS
SFDR = 78dBc
THD = 78dBc
SINAD = 61.0dBFS
SINAD = 61.4dBFS
−40
−40
−60
−60
−80
−80
−100
−100
0
0
0
50
100 150 200 250 300 350 400 450
Frequency (MHz)
0
0
0
50
100 150 200 250 300 350 400 450
Frequency (MHz)
G000
G000
Figure 4.
Figure 5.
FFT FOR 230 MHz INPUT SIGNAL (auto on)
FFT FOR 230 MHz INPUT SIGNAL (auto off)
0
−20
0
−20
SNR = 61.1dBFS
SFDR = 78dBc
THD = 78dBc
SNR = 61.1dBFS
SFDR = 75dBc
THD = 77dBc
SINAD = 61.0dBFS
SINAD = 61.0dBFS
−40
−40
−60
−60
−80
−80
−100
−100
50
100 150 200 250 300 350 400 450
Frequency (MHz)
50
100 150 200 250 300 350 400 450
Frequency (MHz)
G000
G000
Figure 6.
Figure 7.
FFT FOR 400 MHz INPUT SIGNAL (auto on)
FFT FOR 400 MHz INPUT SIGNAL (auto off)
0
−20
0
−20
SNR = 60.6dBFS
SFDR = 67dBc
THD = 67dBc
SNR = 60.7dBFS
SFDR = 69dBc
THD = 69dBc
SINAD = 59.8dBFS
SINAD = 60.2dBFS
−40
−40
−60
−60
−80
−80
−100
−100
50
100 150 200 250 300 350 400 450
Frequency (MHz)
50
100 150 200 250 300 350 400 450
Frequency (MHz)
G000
G000
Figure 8.
Figure 9.
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TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = -40°C to TMAX = +85°C, ADC sampling rate = 900Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, -1dBFS differential input, unless
otherwise noted.
FFT FOR 700 MHz INPUT SIGNAL (auto on)
FFT FOR 700 MHz INPUT SIGNAL (auto off)
0
0
SNR = 60.1dBFS
SFDR = 71dBc
THD = 71dBc
SNR = 60.2dBFS
SFDR = 68dBc
THD = 74dBc
−20
−20
SINAD = 59.9dBFS
SINAD = 60.2dBFS
−40
−40
−60
−60
−80
−80
−100
−100
0
50
100 150 200 250 300 350 400 450
Frequency (MHz)
0
50
100 150 200 250 300 350 400 450
Frequency (MHz)
G000
G000
Figure 10.
Figure 11.
FFT FOR TWO TONE INPUT SIGNAL (auto on)
FFT FOR TWO TONE INPUT SIGNAL (auto off)
0
−20
0
−20
Ain = −7dBFS
Worst Spur = −80dBFS
F1 = 229.5MHz
Ain = −7dBFS
Worst Spur = −82dBFS
F1 = 229.5MHz
F2 = 230.5MHz
F2 = 230.5MHz
−40
−40
−60
−60
−80
−80
−100
−100
0
50
100 150 200 250 300 350 400 450
Frequency (MHz)
0
50
100 150 200 250 300 350 400 450
Frequency (MHz)
G000
G000
Figure 12.
Figure 13.
SFDR
vs
INPUT FREQUENCY
SNR
vs
INPUT FREQUENCY
80
75
70
65
60
55
62
61
60
59
58
57
56
55
Auto Correction Off
Auto Correction On
Auto Correction Off
Auto Correction On
0
250
500
750
1000
1250
1500
0
250
500
750
1000
1250
1500
Input Frequency (MHz)
Input Frequency (MHz)
G000
G000
Figure 14.
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = -40°C to TMAX = +85°C, ADC sampling rate = 900Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, -1dBFS differential input, unless
otherwise noted.
SFDR
SNR
vs
vs
AMPLITUDE (fin = 230MHz)
Amplitude (fin = 230 MHz)
100
90
80
70
60
50
40
30
20
63
62.5
62
61.5
61
dBc, auto off
dBc, auto on
dBFS, auto off
dBFS, auto on
60.5
60
auto off
auto on
−60
−50
−40
−30
−20
−10
0
−60
−50
−40
−30
−20
−10
0
Amplitude (dBFS)
Amplitude (dBFS)
G000
G000
Figure 16.
Figure 17.
SFDR
vs
Vref (auto on)
Tow Tone Performance Across Input Amplitude
(fin = 170 MHz)
−60
−70
75
70
65
60
55
dBFS, auto off
dBFS, auto on
Vref = 0.8V
Vref = 0.9V
Vref = 1.0V
Vref = 1.15V
Vref = 1.25V
−80
−90
−100
−90 −80 −70 −60 −50 −40 −30 −20 −10
Input Amplitude (dB)
0
0
250
500
750
1000
1250
1500
Input Frequency (MHz)
G000
G000
Figure 18.
Figure 19.
SFDR
vs
Vref (auto off)
SNR
vs
Vref (auto on)
80
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Vref = 0.8V
Vref = 0.9V
Vref = 1.0V
Vref = 1.15V
Vref = 1.25V
Vref = 0.8V
Vref = 0.9V
Vref = 1.0V
Vref = 1.15V
Vref = 1.25V
75
70
65
60
55
0
250
500
750
1000
1250
1500
0
250
500
750
1000
1250
1500
Input Frequency (MHz)
Input Frequency (MHz)
G000
G000
Figure 20.
Figure 21.
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TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = -40°C to TMAX = +85°C, ADC sampling rate = 900Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, -1dBFS differential input, unless
otherwise noted.
SNR
vs
Performance Across Input Common Mode Voltage
Vref (auto off)
(fin = 230 MHz)
75
70
65
60
55
50
45
40
62
64
63
62
61
60
59
58
57
56
55
54
53
Vref = 0.8V
Vref = 0.9V
Vref = 1.0V
Vref = 1.15V
Vref = 1.25V
61
60
59
58
SFDR (auto off)
SFDR (auto on)
SNR (auto off)
SNR (auto on)
57
56
55
1.6
1.8
2
2.2
2.4
0
250
500
750
1000
1250
1500
Common Mode Input Voltage (VCM) (V)
G000
Input Frequency (MHz)
G000
Figure 22.
Figure 23.
Performance Across Temperature (fin = 230MHz)
Performance Across AVDD33 (fin = 230MHz)
85
80
75
70
65
63
SFDR (auto off)
SFDR (auto on)
SNR (auto off)
80
75
70
65
60
64
62
63
62
61
60
SNR (auto on)
61
60
59
SFDR (auto off)
SFDR (auto on)
SNR (auto off)
SNR (auto on)
−40
−20
0
20
40
60
80
100
3.0
3.1
3.2
3.3
3.4
3.5
3.6
Temperature (°C)
AVDD33 (V)
G000
G000
Figure 24.
Figure 25.
Performance Across AVDD18 (fin = 230MHz)
Performance Across Clock Amplitude
75
70
65
60
62
75
70
65
60
55
50
45
62
61
60
59
58
57
56
61
60
59
SFDR (auto off)
SFDR (auto on)
SNR (auto off)
SNR (auto on)
dBc, auto off
dBc, auto on
dBFS, auto off
dBFS, auto on
1.6
1.7
1.8
1.9
2.0
0
0.5
1
1.5
2
2.5
3
AVDD18 (V)
Differential Clock Amplitude (Vpp)
G000
G000
Figure 26.
Figure 27.
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TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = -40°C to TMAX = +85°C, ADC sampling rate = 900Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, -1dBFS differential input, unless
otherwise noted.
INL
DNL
2
1.5
1
1.5
1
Auto off
Auto on
0.5
0
0.5
0
−0.5
−1
−0.5
−1
Auto off
Auto on
−1.5
−2
−1.5
0
1k
2k
3k
4k
0
1k
2k
3k
4k
Output Code (LSB)
Figure 28.
Output Code (LSB)
Figure 29.
G015
G016
CMRR Across Frequency
PSRR Across Frequency
0
−10
−20
−30
−40
−50
−40
−50
−60
−70
−80
−90
−100
AVDD33
AVDD18
AVDDC
DVDD
1
10
100
500
1
10
100
Frequency Of common mode signal (MHz)
Frequency (MHz)
G017
G018
Figure 30.
Figure 31.
Power Across Sampling Frequency
2.2
2.1
2
Auto Correction Off
Auto Correction On
1.9
1.8
1.7
1.6
1.5
1.4
1.3
0
100 200 300 400 500 600 700 800 900 1000
Sampling Frequency (Msps)
G016
Figure 32.
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TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = -40°C to TMAX = +85°C, ADC sampling rate = 900Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, -1dBFS differential input, unless
otherwise noted.
SFDR Across Input and Sampling Frequencies (auto on)
Figure 33.
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TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = -40°C to TMAX = +85°C, ADC sampling rate = 900Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, -1dBFS differential input, unless
otherwise noted.
SFDR Across Input and Sampling Frequencies (auto off)
Figure 34.
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TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = -40°C to TMAX = +85°C, ADC sampling rate = 900Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, -1dBFS differential input, unless
otherwise noted.
SNR Across Input and Sampling Frequencies (auto on)
Figure 35.
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TYPICAL CHARACTERISTICS (continued)
Typical values at TA = +25°C, full temperature range is TMIN = -40°C to TMAX = +85°C, ADC sampling rate = 900Msps, 50%
clock duty cycle, AVDD33 = 3.3V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8V, -1dBFS differential input, unless
otherwise noted.
SNR Across Input and Sampling Frequencies (auto on)
Figure 36.
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DESCRIPTION
POWER DOWN MODES
The ADS5409 can be configured via SPI write (address x37) to a stand-by, light or deep sleep power mode
which is controlled by the ENABLE pin. The sleep modes are active when the ENABLE pin goes low. Different
internal functions stay powered up which results in different power consumption and wake up time between the
two sleep modes.
Power Consumption Auto
correction disabled
Power Consumption Auto
correction enabled
Sleep mode
Wake up time
Complete Shut Down
Stand-by
2.5 ms
100µs
20µs
2µs
7mW
7mW
7mW
7mW
Deep Sleep
435mW
770mW
570mW
900mW
Light Sleep
TEST PATTERN OUTPUT
The ADS5409 can be configured to output different test patterns that can be used to verify the digital interface is
connected and working properly. To enable the test pattern mode, the high performance mode 1 has to be
disabled first via SPI register write. Then different test patterns can be selected by configuring registers x3C, x3D
and x3E. All three registers must be configured for the test pattern to work properly.
First set HP1 = 0 (Addr 0x01, D01)
Register Address
All 0s
0x8000
0x0000
0x0000
All 1s
0xBFFC
0x3FFC
0x3FFC
Toggle (0xAAA => 0x555)
Toggle (0xFFF => 0x000)
0xBFFC
0x3C
0x3D
0x3E
0x9554
0x2AA8
0x1554
0x0000
0x3FFC
Register
Address
Custom Pattern
D15
1
D14
0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
0
D0
0
x3C
x3D
x3E
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
For normal operation, set HP1 = 1 (Addr 0x01, D01) and 0x3C, 0x3D, 0x3E all to 0.
CLOCK INPUT
The ADS5409 clock input can be driven differentially with a sine wave, LVPECL or LVDS source with little or no
difference in performance. The common mode voltage of the clock input is set to 0.9V using internal 2kΩ
resistors. This allows for AC coupling of the clock inputs. The termination resistors should be placed as close as
possible to the clock inputs in order to minimize signal reflections and jitter degradation.
0.1uF
CLKINP
CLKINP
2kΩ
2kΩ
RT
0.9V
0.1uF
RT
CLKINN
CLKINN
0.1uF
Recommended differential clock driving circuit
Figure 37. Recommended Differential Clock Driving Circuit
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SNR AND CLOCK JITTER
The signal to noise ratio of the ADC is limited by three different factors: the quantization noise is typically not
noticeable in pipeline converters and is 74dB for a 12bit ADC. The thermal noise limits the SNR at low input
frequencies while the clock jitter sets the SNR for higher input frequencies.
ö2
æ
ö2
æ
ö2
SNRQuantization _Noise
æ
SNRThermalNoise
SNRJitter
20
SNRADC[dBc] = -20´log 10 -
+ 10 -
+ 10 -
ç
÷
ç
÷
ç
÷
ç
è
÷
20
20
è
ø
è
ø
ø
(1)
(2)
The SNR limitation due to sample clock jitter can be calculated as following:
SNRJitter [dBc] = -20´log(2p´ fin ´ TJitter
)
The total clock jitter (TJitter) has three components – the internal aperture jitter (100fs for ADS5409) which is set
by the noise of the clock input buffer, the external clock jitter and the jitter from the analog input signal. It can be
calculated as following:
2
TJitter
=
(TJitter,Ext.Clock _Input )2 + (TAperture _ ADC )2 + (TJitter,Analog_input
)
(3)
External clock jitter can be minimized by using high quality clock sources and jitter cleaners as well as bandpass
filters at the clock input while a faster clock slew rate improves the ADC aperture jitter.
The ADS5409 has a thermal noise of 61.5 dBFS and internal aperture jitter of 100fs. The SNR depending on
amount of external jitter for different input frequencies is shown in the following figure.
SNR vs Input Frequency and External Clock Jitter
62
61
35 fs
60
50 fs
100 fs
59
150 fs
200 fs
58
57
56
55
10
100
1000
Fin (MHz)
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ANALOG INPUTS
The ADS5409 analog signal inputs are designed to be driven differentially. The analog input pins have internal
analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high
impedance input across a very wide frequency range to the external driving source which enables great flexibility
in the external analog filter design as well as excellent 50Ω matching for RF applications. The buffer also helps to
isolate the external driving circuit from the internal switching currents of the sampling circuit which results in a
more constant SFDR performance across input frequencies.
The common-mode voltage of the signal inputs is internally biased to 1.9V using 500Ω resistors which allows for
AC coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM +
0.25V) and (VCM – 0.25V), resulting in a 1.0Vpp (default) differential input swing. The input sampling circuit has
a 3dB bandwidth that extends up to 1.2GHz.
2nH
0.5Ω
20Ω
INA_P
1.3pF
1.4pF
500Ω
Vcm= 1.9V
500Ω
2nH
0.5Ω
20Ω
INA_N
1.3pF
1.4pF
OVER-RANGE INDICATION
The ADS5409 provides a fast over-range indication on the OVRA/B pins. The fast OVR is triggered if the input
voltage exceeds the programmable overrange threshold and it gets presented after just 12 clock cycles enabling
a quicker reaction to an overrange event. The OVR threshold can be configured using SPI register writes.
The input voltage level at which the overload is detected is referred to as the threshold and is programmable
using the Over-range threshold bits. The threshold at which fast OVR is triggered is (full-scale × [the decimal
value of the FAST OVR THRESH bits] /16). After reset, the default value of the over-range threshold is set to 15
(decimal) which corresponds to a threshold of 0.56dB below full scale (20*log(15/16)).
OVR Detection Threshold
0
-5
-10
-15
-20
-25
0
2
4
6
8
10
12
14
16
Programmed Value (1-15)
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INTERLEAVING CORRECTION
Each of the two data converter channels consists of two interleaved ADCs each operating at half of the ADC
sampling rate but 180º out of phase from each other. The front end track and hold circuitry is operating at the full
ADC sampling rate which minimizes the timing mismatch between the two interleaved ADCs. In addition the
ADS5409 is equipped with internal interleaving correction logic that can be enabled via SPI register write.
ADC
ODD
Interleaving
Correction
Track &
Input
Hold
Fs/2
0 deg
ADC
EVEN
Estimator
Fs
Fs/2
180 deg
The interleaving operation creates 2 distinct and interleaving products:
•
Fs/2 – Fin: this spur is created by gain timing mismatch between the ADCs. Since internally the front end
track and hold is operated at the full sampling rate, this component is greatly improved and mostly dependent
on gain mismatch.
•
Fs/2 Spur: due to offset mismatch between ADCs
Input
Signal
Fs/2 Spur
Fs/2 - Fin
Fs/2
The auto correction loop can be enabled via SPI register write in address 0x01 and resetting the correction circuit
in addresses 0x03 and 0x1A. By default it is disabled for lowest possible power consumption. The default
settings for the auto correction function should work for most applications. However please contact Texas
Instruments if further fine tuning of the algorithm is required.
The auto correction function yields best performance for input frequencies below 250MHz. For input frequencies
greater than 250MHz it is recommended to disable the auto gain correction loop.
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RECEIVE MODE: DECIMATION FILTER
Each channel has a digital filter in the data path as shown in Figure 38. The filter can be programmed as a low-
pass or a high-pass filter and the normalized frequency response of both filters is shown in Figure 39.
Lowpass/
Highpass
selection
900 MSPS
Low Latency Filter
450 MSPS
ADC
2
0, Fs/2
Figure 38.
The decimation filter response has a 0.1dB pass band ripple with approximately 41% pass-band bandwidth. The
stop-band attenuation is approximately 40dB.
Decimation Filter Response
Decimation Filter Response
10
0
0.1
0.08
0.06
0.04
0.02
0
LowPass Filter
High Pass Filter
-10
-20
-30
-40
-50
-60
-0.02
-0.04
-0.06
-0.08
-0.1
LowPass Filter
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency(MHz)
Frequency(MHz)
Figure 39.
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MULTI DEVICE SYNCHRONIZATION
The ADS5409 simplifies the synchronization of data from multiple ADCs in one common receiver. Upon receiving
the initial SYNC input signal, the ADS5409 resets all the internal clocks and digital logic while also starting a
SYNCOUT signal which operates on a 5bit counter (32 clock cycles). Therefore by providing a common SYNC
signal to multiple ADCs their output data can be synchronized as the SYNCOUT signal marks a specific sample
with the same latency in all ADCs. The SYNCOUT signal then can be used in the receiving device to
synchronize the FIFO pointers across the different input data streams. Thus the output data of multiple ADCs can
be aligned properly even if there are different trace lengths between the different ADCs.
ADS5409
FIFO
Pointer
DxCLK
SYNCOUT
Dx[11:0]
Sample x
Sample 1
Sample 2
Sample 3
Sample 4
Sample 5
Sample 6
ChA
ChB
FPGA
ASIC
SYNC
ADS5409
FIFO
Pointer
DxCLK
SYNCOUT
Dx[11:0]
Sample x
Sample 1
Sample 2
Sample 3
Sample 4
Sample 5
Sample 6
ChA
ChB
The SYNC input signal should be a periodic signal repeating every 32 CLKIN clock cycles. It gets registered on
the rising edge of the ADC input clock (CLKIN). Upon registering the initial rising edge of the SYNC signal, the
internal clocks and logic get reset which results in invalid output data for 36 samples (1 complete sync cycle and
4 additional samples). The SYNCOUT signal starts with the next output clock (DACLK) rising edge and operates
on a 5-bit counter independent from the SYNC signal frequency and duty cycle.
Since the ADS5409 output interface operates with a DDR clock, the synchronization can happen on the rising
edge or falling edge sample. Synchronization on the falling edge sample will result in a half cycle clock stretch of
DA/BCLK. For convenience the SYNCOUT signal is available on the ChA/B output LVDS bus. When using
decimation the SYNCOUT signal still operates on 32 clock cycles of CLKIN but since the output data is
decimated by 2, only the first 18 samples should be discarded.
CLKIN
16 clock cycles
SYNC
16 clock cycles
DACLK
16 clock cycles
SYNCOUT
16 clock cycles
DA[11:0]
Data invalid – 36 samples
16 clock cycles
SYNC
16 clock cycles
DACLK
16 clock cycles
SYNCOUT
16 clock cycles
DA[11:0]
Data invalid – 36 samples
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PROGRAMMING INTERFACE
The serial interface (SIF) included in the ADS5409 is a simple 3 or 4 pin interface. In normal mode, 3 pins are
used to communicate with the device. There is an enable (SDENB), a clock (SCLK) and a bi-directional IO port
(SDIO). If the user would like to use the 4 pin interface one write must be implemented in the 3 pin mode to
enable 4 pin communications. In this mode, the SDO pin becomes the dedicated output. The serial interface has
an 8-bit address word and a 16-bit data word. The first rising edge of SCLK after SDENB goes low will latch the
read/write bit. If a high is registered then a read is requested, if it is low then a write is requested. SDENB must
be brought high again before another transfer can be requested. The signal diagram is shown below:
Register Initialization
After power up, the internal registers must be initialized to the default values. This initialization can be
accomplished in one of two ways:
1. Either through hardware reset by applying a low pulse on SRESET pin
2. By applying a software reset. When using the serial interface, a reset can be performed by addressing
register x2C. This setting initializes the internal registers to the default values and then self-resets the
RESET register to 0. In this case the SRESET pin can be kept high.
Serial Register Write
The internal register of the ADS5409 can be programmed following these steps:
1. Drive SDENB pin low
2. Set the R/W bit to ‘0’ (bit A7 of the 8 bit address)
3. Initiate a serial interface cycle specifying the address of the register (A6 to A0) whose content has to be
written
4. Write 16bit data which is latched on the rising edge of SCLK
SCLK
SDENB
RWB
A6
A5
A4
A3
A2
A1
A0 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDIO
Read = 1
Write = 0
7 bit address space
16bit data: D15 is MSB, D0 is LSB
Figure 40. Serial Register Write Timing Diagram
PARAMETER
MIN
>DC
25
TYP(1)
MAX
UNIT
MHz
ns
fSCLK
SCLK frequency (equal to 1/tSCLK)
SDENB to SCLK setup time
SCLK to SDENB hold time
SDIO setup time
20
tSLOADS
tSLOADH
tDSU
25
ns
25
ns
tDH
SDIO hold time
25
ns
(1) Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD33 =
3.3V, AVDD, DRVDD = 1.9V, unless otherwise noted.
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Serial Register Readout
The device includes a mode where the contents of the internal registers can be read back using the SDO/SDIO
pins. This read-back mode may be useful as a diagnostic check to verify the serial interface communication
between the external controller and the ADC.
1. Drive SDENB pin low
2. Set the RW bit (A7) to '1'. This setting disables any further writes to the registers
3. Initiate a serial interface cycle specifying the address of the register (A6 to A0) whose content has to be
read.
4. The device outputs the contents (D15 to D0) of the selected register on the SDO/SDIO pin
5. The external controller can latch the contents at the SCLK rising edge.
6. To enable register writes, reset the RW register bit to '0'.
SCLK
SDENB
RWB
A6
A5
A4
A3
A2
A1
A0 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDIO
Read = 1
Write = 0
7 bit address space
16bit data: D15 is MSB, D0 is LSB
Figure 41. Serial Register Read Timing Diagram
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SERIAL REGISTER MAP(2)
(2) Multiple functions in a register can be programmed in a single write operation.
Register
Address
Register Data
A7–A0 IN
HEX
D15
D14
D13
D12
D11
D10
0
D9
D8
0
D7
0
D6
D5
D4
D3
D2
D1
D0
Decima-
tion
Filter
EN
ChA
High/
Low
ChB
High/
Low
3/4 Wire
SPI
0
0
0
0
0
0
0
0
0
0
Pass
Pass
ChA
Corr EN
ChB
Corr EN
Data
Format
Hp
Mode1
1
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Over-range threshold
0
1
0
0
Start
Auto
Corr
ChA
3
0
0
1
0
1
1
0
0
0
1
0
0
E
F
Sync Select
0
0
0
0
Sync Select
0
1
0
0
0
0
0
1
0
0
0
0
0
VREF Set
0
0
1
0
0
Start
Auto
Corr
ChB
1A
0
0
0
0
0
0
1
0
0
1
0
0
2B
2C
37
0
Temp Sensor
0
Reset
Sleep Modes
0
0
0
0
0
0
0
0
0
0
0
0
0
BIAS
EN
SYNC
EN
LP
Mode 1
38
3A
HP Mode2
Internal LVDS
Termination
DACLK DBCLK
EN EN
OVRA
EN
OVRB
EN
LVDS Current Strength
LVDS SW
0
0
0
66
67
LVDS Output Bus A EN
LVDS Output Bus B EN
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DESCRIPTION OF SERIAL INTERFACE REGISTERS
Register
Address
Register Data
A7-A0 in hex
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
3/4
Wire ima-
SPI
Dec-
0
ChA
High/
Low
0
0
ChB
High/
Low
0
0
0
0
0
0
0
0
0
tion
Filter
EN
Pass
Pass
D15
3/4 Wire SPI
Enables 4-bit serial interface when set
Default 0
0
1
3 wire SPI is used with SDIO pin operating as bi-directional I/O port
4 wire SPI is used with SDIO pin operating as data input and SDO pin as data output port.
D14
Decimation
Filter EN
Default 0
2x decimation filter is enabled when bit is set
0
1
Normal operation with data output at full sampling rate
2x decimation filter enabled
D12
ChA High/Low
Pass
(Decimation filter must be enabled first: set bit D14)
Default 0
0
1
Low Pass
High Pass
D9
ChB High/Low
Pass
(Decimation filter must be enabled first: set bit D14)
Default 0
0
1
Low Pass
High Pass
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Register
Address
Register Data
A7-A0 in hex
1
D15
D14
0
D13
0
D12
0
D11
0
D10
0
D9
D8
0
D7
0
D6
0
D5
0
D4
0
D3
D2
0
D1
D0
0
ChA
Corr
EN
ChB
Corr
EN
Data
Format
HP
Mode1
D15
ChA Corr EN (should be enabled for maximum performance)
Default 0
0
1
Auto correction disabled
Auto correction enabled
D9
ChB Corr EN (should be enabled for maximum performance)
Default 0
0
1
Auto correction disabled
Auto correction enabled
D3
Data Format
Default 0
0
1
Two's complement
Offset Binary
D1
1
HP Mode 1
Default 1
Must be set to 1 for optimum performance
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Register
Address
Register Data
D8 D7
Over-range threshold
A7-A0 in
hex
D15
0
D14
0
D13
0
D12
0
D11
0
D10
D9
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
2
D10-D7 Over-range threshold The over-range detection is triggered 12 output clock cycles after the
overload condition occurs. The threshold at which the OVR is triggered =
1.0V x [decimal value of <Over-range threshold>]/16. After power up or
reset, the default value is 15 (decimal) which corresponds to a OVR
threshold of 0.56dB below fullscale (20*log(15/16)). This OVR threshold is
applicable to both channels.
Default 1111
OVR Detection Threshold
0
-5
-10
-15
-20
-25
0
2
4
6
8
10
12
14
16
Programmed Value (1-15)
Register
Address
Register Data
A7-A0 in
hex
D15
0
D14
D13
0
D12
0
D11
1
D10
0
D9
1
D8
1
D7
0
D6
0
D5
0
D4
1
D3
1
D2
0
D1
0
D0
0
3
Start
Auto
Coff
ChA
D14
Start Auto Corr ChA
Starts DC offset and Gain correction loop for ChA
Default 1
0
1
Starts the DC offset and Gain correction loops
Clears DC offset correction value to 0 and Gain correction value to 1
D11, 9, 8, 4, 3 Must be set to 1 for maximum performance
Default 1
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Register
Address
Register Data
D8 D7
Sync Select
A7-A0 in
hex
D15
D14
D13
D12
D11
D10
D9
D6
D5
D4
D3
D2
D1
D0
0
E
0
D15-D2
Sync Select
Default 1010 1010
1010 10
Sync selection for the clock generator block (also
need to see address 0x0F)
0000 0000 0000 00
0101 0101 0101 01
1010 1010 1010 10
1111 1111 1111 11
Sync is disabled
Sync is set to one shot (one time synchronization only)
Sync is derived from SYNC input pins
not supported
Register
Address
Register Data
A7-A0 in
hex
D15
D14
D13
D12
D11
0
D10
0
D9
0
D8
0
D7
0
D6
D5
D4
D3
0
D2
0
D1
0
D0
0
F
Sync Select
VREF Sel
D15-D12
Sync Select
Sync selection for the clock generator block
Default 1010
0000
0101
1010
1111
Sync is disabled
Sync is set to one shot (one time synchronization only)
Sync is derived from SYNC input pins
not supported
D6-D4
VREF SEL
Internal voltage reference selection
Default 000
000
1.0V
001
1.25V
010
0.9V
011
0.8V
100
1.15V
Others
external reference
Register
Address
Register Data
A7-A0 in
hex
D15
0
D14
D13
0
D12
0
D11
1
D10
0
D9
1
D8
1
D7
0
D6
0
D5
0
D4
1
D3
1
D2
0
D1
0
D0
0
1A
Start
Auto
Corr
ChB
D14
Start Auto Corr ChB
Starts DC offset and Gain correction loop for ChB
Default 1
0
1
Starts the DC offset and Gain correction loops
Clears DC offset correction value to 0 and Gain correction value to 1
D11, 9, 8, 4, 3
Must be set to 1 for maximum performance
Default 1
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Register
Address
Register Data
D8 D7
A7-A0 in
hex
D15
0
D14
0
D13
0
D12
0
D11
0
D10
0
D9
0
D6
D5
D4
D3
D2
D1
D0
2B
Temp Sensor
D8-D0
Temp Sensor
Internal temperature sensor value – read only
Register
Address
Register Data
A7-A0 in
hex
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
2C
Reset
D15-D0
Reset
Default
0000
This is a software reset to reset all SPI registers to their default value. Self
clears to 0.
1101001011110000
Perform software reset
Register
Address
Register Data
A7-A0 in
hex
D15
D14
D13
D12
D11
D10
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
37
Sleep Modes
D15-D14
Sleep Modes
Default 00
Sleep mode selection which is controlled by the ENABLE pin. Sleep modes are active when
ENABLE pin goes low.
000000
100000
110000
110101
Complete shut down
Stand-by mode
Wake up time 2.5 ms
Wake up time 100 µs
Wake up time 20 µs
Wake up time 2 µs
Deep sleep mode
Light sleep mode
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Register
Address
Register Data
D8 D7
A7-A0 in
hex
D15
D14
D13
D12
D11
D10
D9
D6
D5
D4
D3
0
D2
0
D1
D0
0
38
HP Mode 2
Bias SYNC
EN EN
LP
Mode
1
0
D15-D7 HP Mode 2
Default 111111111
1
Set to 1 for normal operation
D6
BIAS EN
Default 1
Enables internal fuse bias voltages – can be disabled after
power up to save power.
0
Internal bias powered
down
1
Internal bias enabled
D5
SYNC EN
Enables the SYNC input buffer.
Default 1
0
SYNC input buffer
disabled
1
SYNC input bffer enabled
D4
LP Mode 1
Low power mode 1 to disable unused internal input buffer.
Default 1
0
1
Internal input buffer
disabled
Internal input buffer
enabled
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Register
Address
Register Data
A7-A0 in hex D15 D14 D13 D12 D11 D10
D9
D8
D7
0
D6
D5
0
D4
DACLK DBCLK
EN EN
D3
D2
0
D1
OVRA OVRB
EN EN
D0
3A
LVDS Current
Strength
LVDS SW
Internal
0
0
LVDS
Termination
D15-D13
LVDS Current
LVDS output current strength.
Strength
Default 110
000
001
010
011
2 mA
100 3 mA
2.25 mA
2.5 mA
2.75 mA
101 3.25 mA
110 3.5 mA
111 3.75 mA
D12-D11
LVDS SW
LVDS driver internal switch setting – correct range must be set for setting in D15-D13
Default 01
01
2 mA to 2.75 mA
3mA to 3.75mA
11
D10-D9
Internal LVDS
Termination
Default 00
Internal termination
00
01
10
11
2 kΩ
200 Ω
200 Ω
100 Ω
D4
DACLK EN
Enable DACLK output buffer
Default 1
0
1
DACLK output buffer powered down
DACLK output buffer enabled
D3
DBCLK EN
Enable DBCLK output buffer
Default 1
0
1
DBCLK output buffer powered down
DBCLK output buffer enabled
D1
OVRA EN
Enable OVRA output buffer
Default 1
0
1
OVRA output buffer powered down
OVRA output buffer enabled
D0
OVRB EN
Enable OVRB output buffer
Default 1
0
1
OVRB output buffer powered down
OVRB output buffer enabled
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Register
Address
Register Data
D8 D7
LVDS Output Bus A EN
Individual LVDS output pin power down for channel A
A7-A0 in
hex
D15
D14
D13
D12
D11
D10
D9
D6
D5
D4
D3
D2
D1
D0
66
D15-D10
LVDS Output Bus A EN
Default FFFF
0
1
Output is powered down
Output is enabled
D15
D14
Pins N7, P7 (no connect pins) which are not used and should be powered down for
power savings
Pins N6, P6 (no connect pins) which are not used and should be powered down for
power savings
D13
D12
SYNCOUTP/N (pins P5, N5)
Pins N4, P4 (no connect pins) which are not used and should be powered down for
power savings
D11-D0
corresponds to DA11-DA0
Register
Address
Register Data
A7-A0 in
hex
D15
D14
D13
D12
D11
D10
D9
LVDS Output Bus B EN
Individual LVDS output pin power down for channel B
D8
D7
D6
D5
D4
D3
D2
D1
D0
67
D15-D10
LVDS Output Bus B EN
Default FFFF
0
1
Output is powered down
Output is enabled
D15
D14
Pins G3, G4 (no connect pins) which are not used and should be powered down for
power savings
Pins F3, F4 (no connect pins) which are not used and should be powered down for
power savings
D13
D12
SYNCOUTP/N (pins F1, F2)
Pins E3, E4 (no connect pins) which are not used and should be powered down for
power savings
D11-D0
corresponds to DB11-DB0
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PACKAGE OPTION ADDENDUM
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12-Jun-2013
PACKAGING INFORMATION
Orderable Device
ADS5409IZAY
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
NFBGA
NFBGA
ZAY
196
196
160
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
Level-3-260C-168 HR
ADS5409I
ADS5409I
ADS5409IZAYR
ACTIVE
ZAY
1000
Green (RoHS
& no Sb/Br)
Level-3-260C-168 HR
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jun-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS5409IZAYR
NFBGA
ZAY
196
1000
330.0
24.4
12.3
12.3
2.3
16.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jun-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
NFBGA ZAY 196
SPQ
Length (mm) Width (mm) Height (mm)
336.6 336.6 31.8
ADS5409IZAYR
1000
Pack Materials-Page 2
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