ADS5424IPJYR [TI]
14 BIT, 105 MSPS ANALOG TO DIGITAL CONVERTER; 14位， 105 MSPS模数转换器
| 型号： | ADS5424IPJYR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 14 BIT, 105 MSPS ANALOG TO DIGITAL CONVERTER |
| 文件： | 总25页 (文件大小：577K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢀꢆ ꢇ ꢈ ꢉꢊ ꢉ
ꢋ ꢌ ꢍꢎ ꢏꢐꢑ ꢄ ꢏꢑ ꢒ ꢃꢐ ꢃꢄ ꢍꢎ ꢓꢏ ꢌꢔꢕ ꢖ ꢄꢕ ꢖ
D
52 Pin HTQFP Package With Exposed
Heatsink
FEATURES
D
D
D
D
D
D
D
D
D
D
14 Bit Resolution
105 MSPS Maximum Sample Rate
SNR = 74 dBc at 105 MSPS and 50-MHz IF
D
Pin Compatible to the AD6644/45
D
Industrial Temperature Range = −405C to 855C
SFDR = 93 dBc at 105 MSPS and 50-MHz IF
APPLICATIONS
2.2 V Differential Input Range
pp
5 V Supply Operation
D
D
D
D
Single and Multichannel Digital Receivers
Base Station Infrastructure
Instrumentation
3.3 V CMOS Compatible Outputs
1.9 W Total Power Dissipation
2s Complement Output Format
Video and Imaging
RELATED DEVICES
On-Chip Input Analog Buffer, Track and Hold,
and Reference Circuit
D
Clocking: CDC7005
Amplifiers: OPA695, THS4509
D
DESCRIPTION
The ADS5424 is a 14 bit 105 MSPS analog-to-digital converter (ADC) that operates from a 5 V supply, while providing 3.3 V
CMOS compatible digital outputs. The ADS5424 input buffer isolates the internal switching of the on-chip Track and Hold
(T&H) from disturbing the signal source. An internal reference generator is also provided to further simplify the system
design. The ADS5424 has outstanding low noise and linearity, over input frequency. With only a 2.2 VPP input range,
simplifies the design of multicarrier applications, where the carriers are selected on the digital domain.
The ADS5424 is available in a 52 pin HTQFP with heatsink package and is pin compatible to the AD6645. The ADS5424
is built on state of the art Texas Instruments complementary bipolar process (BiCom3) and is specified over full industrial
temperature range (−40°C to 85°C).
FUNCTIONAL BLOCK DIAGRAM
AV
DD
DRV
DD
A
IN
A
IN
+
+
A3
A2
TH3
TH2
TH1
ADC3
Σ
Σ
A1
−
−
ADC1
DAC1
ADC2
DAC2
VREF
Reference
5
5
6
C1
C2
Digital Error Correction
CLK+
CLK−
Timing
DMID OVR DRY
D[13:0]
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPad is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
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Copyright 2005, Texas Instruments Incorporated
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE LEAD
(1)
HTQFP-52
PowerPAD
ADS5424IPJY
Tray, 160
ADS5424
PJY
−40°C to +85°C
ADS5424I
ADS5424IPJYR
Tape and Reel, 1000
(1)
Thermal pad size: Octagonal 2,5 mm side
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handledwith appropriate precautions. Failure to observe
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
proper handling and installation procedures can cause damage.
ADS5424
UNIT
AV
DD
to GND
to GND
6
5
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because small parametric changes could cause
the device not to meet its published specifications.
Supply voltage
V
V
DRV
DD
−0.3 to
AV
DD
Analog input to GND
+ 0.3
−0.3 to
AV + 0.3
Clock input to GND
CLK to CLK
V
V
V
RECOMMENDED OPERATING CONDITIONS
DD
2.5
−0.3 to
MIN
TYP
MAX
UNIT
PARAMETER
Supplies
Digital data output to GND
DRV
+ 0.3
DD
Analog supply voltage, AV
4.75
3
5
5.25
3.6
V
V
DD
Operating temperature range
Maximum junction temperature
Storage temperature range
−40 to 85
°C
°C
°C
Output driver supply voltage,
DRV
DD
3.3
150
−65 to 150
Analog Input
Differential input range
2.2
2.4
V
(1)
PP
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
Input common-mode voltage,
V
V
CM
Digital Output
Maximum output load
Clock Input
10
pF
(1)
THERMAL CHARACTERISTICS
ADCLK input sample rate (sine
TEST
CONDITIONS
30
105
85
MSPS
PARAMETER
TYP
22.5
15.8
33.3
25.9
UNIT
°C/W
°C/W
°C/W
°C/W
wave) 1/t
C
Clock amplitude, sine wave,
Soldered slug, no
airflow
3
V
PP
(1)
differential
θ
JA
(2)
Clock duty cycle
50%
Soldered slug,
200-LPFM airflow
θ
JA
θ
JA
θ
JA
Open free-air temperature range −40
°C
(1)
(2)
See Figure 22 and Figure 23 for more information.
See Figure 21 for more information.
Unsoldered slug,
no airflow
Unsoldered slug,
200-LPFM airflow
Bottom of
package
(heatslug)
θ
JC
2
°C/W
(1)
Using 25 thermal vias (5 x 5 array). See the Application Section.
2
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
ELECTRICAL CHARACTERISTICS
Over full temperature range (T
= −40°C to T
MAX
= 85°C), sampling rate = 105 MSPS, 50% clock duty cycle, AV
= 5 V, DRV = 3.3 V,
DD
MIN
DD
−1 dBFS differential input, and 3 V
differential sinusoidal clock, unless otherwise noted
PP
PARAMETER
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
14
Bits
Analog Inputs
Differential input range
Differential input resistance
Differential input capacitance
Analog input bandwidth
Internal Reference Voltages
2.2
1
V
PP
kΩ
pF
See Figure 32
See Figure 32
1.5
570
MHz
Reference voltage, V
Dynamic Accuracy
No missing codes
2.4
V
REF
Tested
0.5
1.5
0
Differential linearity error, DNL
Integral linearity error, INL
Offset error
f
IN
f
IN
= 5 MHz
= 5 MHz
−0.95
−5
1.5
5
LSB
LSB
mV
Offset temperature coefficient
Gain error
1.7
0.9
1
ppm/°C
%FS
−5
5
PSRR
mV/V
ppm/°C
Gain temperature coefficient
Power Supply
77
F
S
F
S
F
S
F
S
= 92.16 MSPS
= 105 MSPS
= 92.16 MSPS
= 105 MSPS
355
355
38
Analog supply current, I
AVDD
V
= full scale, f = 70 MHz
IN
mA
mA
IN
410
47
Output buffer supply current, I
V
= full scale, f = 70 MHz
DRVDD
IN IN
40
Total power with 10-pF load
on each digital output to
F
= 92.16 MSPS
1.9
S
Power dissipation
Power-up time
W
F
= 105 MSPS
= 105 MSPS
1.9
20
2.2
S
S
ground, f = 70 MHz
IN
F
100
ms
3
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
ELECTRICAL CHARACTERISTICS
Over full temperature range (T
= −40°C to T
MAX
= 85°C), sampling rate = 105 MSPS, 50% clock duty cycle, AV
= 5 V, DRV = 3.3 V,
DD
MIN
DD
−1 dBFS differential input, and 3 V
differential sinusoidal clock, unless otherwise noted
PP
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Dynamic AC Characteristics
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
F
S
= 92.16 MSPS
= 105 MSPS
= 92.16 MSPS
= 105 MSPS
= 92.16 MSPS
= 105 MSPS
= 92.16 MSPS
= 105 MSPS
= 92.16 MSPS
= 105 MSPS
= 92.16 MSPS
= 105 MSPS
= 92.16 MSPS
= 105 MSPS
= 92.16 MSPS
= 105 MSPS
= 92.16 MSPS
= 105 MSPS
= 92.16 MSPS
= 105 MSPS
= 92.16 MSPS
= 105 MSPS
= 92.16 MSPS
= 105 MSPS
= 92.16 MSPS
= 105 MSPS
= 92.16 MSPS
= 105 MSPS
= 92.16 MSPS
= 105 MSPS
= 92.16 MSPS
= 105 MSPS
= 92.16 MSPS
= 105 MSPS
= 92.16 MSPS
= 105 MSPS
= 92.16 MSPS
= 105 MSPS
= 92.16 MSPS
= 105 MSPS
= 92.16 MSPS
= 105 MSPS
74.5
74.4
74.4
74.3
74.2
74.2
74
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
= 10 MHz
= 30 MHz
= 50 MHz
= 70 MHz
= 100 MHz
= 170 MHz
= 230 MHz
= 10 MHz
= 30 MHz
= 50 MHz
= 70 MHz
= 100 MHz
= 170 MHz
= 230 MHz
= 10 MHz
= 30 MHz
= 50 MHz
= 70 MHz
= 100 MHz
= 170 MHz
= 230 MHz
dBc
dBc
dBc
73
dBc
dBc
dBc
dBc
dBc
dBc
Signal-to-noise ratio, SNR
72.5
74
73.5
73.5
72
72
71.5
71.5
94
93
95
dBc
dBc
85
95
94
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
93
89
Spurious-free dynamic range, SFDR
88
88
87
73
73
64
64
74.4
74.3
74.3
74.3
74.1
74
72.8
74
Signal-to-noise + distortion, SINAD
73.9
73.3
73.3
69.3
69.1
63.4
63.4
4
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
ELECTRICAL CHARACTERISTICS
Over full temperature range (T
= −40°C to T
MAX
= 85°C), sampling rate = 105 MSPS, 50% clock duty cycle, AV
= 5 V, DRV
= 3.3 V,
MIN
DD
DD
−1 dBFS differential input, and 3 V
differential sinusoidal clock, unless otherwise noted
PP
PARAMETER
TEST CONDITIONS
MIN
TYP
100
105
98
98
98
98
96
93
95
93
87
73
64
93
95
93
88
88
88
88
0.9
MAX
UNIT
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
= 10 MHz
= 30 MHz
= 50 MHz
= 70 MHz
= 100 MHz
= 170 MHz
= 230 MHz
= 10 MHz
= 30 MHz
= 50 MHz
= 100 MHz
= 170 MHz
= 230 MHz
= 10 MHz
= 30 MHz
= 50 MHz
= 70 MHz
= 100 MHz
= 170 MHz
= 230 MHz
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
LSB
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Second harmonic, HD2
Third harmonic, HD3
Worst-harmonic / spur (other than HD2
and HD3)
RMS idle channel noise
Input pins tied together
DIGITAL CHARACTERISTICS
Over full temperature range (T
= −40°C to T
MAX
= 85°C), AV
DD
= 5 V, DRV = 3.3 V, unless otherwise noted
DD
MIN
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Outputs
(1)
= 10 pF
(1)
= 10 pF
Low-level output voltage
High-level output voltage
Output capacitance
DMID
C
LOAD
C
LOAD
0.1
0.6
V
V
2.6
3.2
3
pF
V
DRV /2
DD
(1)
Equivalent capacitance to ground of (load + parasitics of transmission lines).
5
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
(3)
TIMING CHARACTERISTICS
Over full temperature range, AV
= 5 V, DRV
DD
= 3.3 V, sampling rate = 105 MSPS
DD
PARAMETER
Aperture Time
DESCRIPTION
MIN
TYP
MAX
UNIT
t
t
Aperture delay
500
150
50
ps
fs
A
J
Clock slope independent aperture uncertainity (jitter)
Clock slope dependent jitter factor
k
µV
J
Clock Input
t
t
t
Clock period
9.5
ns
ns
ns
CLK
(1)
Clock pulsewidth high
Clock pulsewidth low
4.75
4.75
CLKH
(1)
CLKL
Clock to DataReady (DRY)
t
t
t
Clock rising 50% to DRY falling 50%
2.8
7.6
3.9
4.7
9.5
ns
ns
ns
DR
t
t
+
DR
Clock rising 50% to DRY rising 50%
C_DR
CLKH
Clock rising 50% to DRY rising 50% with 50% duty cycle clock
8.7
C_DR_50%
(4)
Clock to DATA, OVR
t
t
Data V
Data V
to data V
OH
to data V
OL
(rise time)
(fall time)
2
2
ns
ns
r
OL
f
OH
L
Latency
Valid DATA to clock 50% with 50% duty cycle clock (setup time)
(2)
3
Cycles
ns
(2)
t
t
1.8
2.6
3.4
3.6
su(C)
Clock 50% to invalid DATA (hold time)
(4)
ns
H(C)
DataReady (DRY) to DATA, OVR
(2)
Valid DATA to DRY 50% with 50% duty cycle clock (setup time)
(2)
DRY 50% to invalid DATA with 50% duty cycle clock (hold time)
t
t
1.8
3.9
2.6
4.4
ns
ns
su(DR)_50%
h(DR)_50%
(1)
(2)
(3)
(4)
See Figure 21 for more information.
See V and V levels.
All values obtained from design and characterization.
OH OL
Data is updated with clock rising edge or DRY falling edge.
t
A
N+3
N
AIN
N+1
N+2
N+4
t
t
CLKL
t
CLKH
CLK
CLK, CLK
N + 1
N + 2
N + 3
N + 4
N
t
h(C)
t
t
su(C)
C_DR
D[13:0], OVR
DRY
N−3
N−2
N−1
N
t
t
h(DR)
su(DR)
t
r
t
f
t
DR
Figure 1. Timing Diagram
6
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
PIN CONFIGURATION
PJY PACKAGE
(TOP VIEW)
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
38
37
36
35
34
33
32
31
30
29
28
27
DRV
D3
D2
D1
D0 (LSB)
DMID
GND
DRV
OVR
DNC
DD
2
GND
VREF
GND
CLK
CLK
GND
3
4
5
6
7
GND
DD
8
AV
AV
DD
9
DD
10
11
12
13
GND
AIN
AIN
AV
DD
GND
AV
DD
GND
GND
14 15 16 17 18 19 20 21 22 23 24 25 26
PIN ASSIGNMENTS
TERMINAL
DESCRIPTION
NAME
DRV
NO.
1, 33, 43
3.3 V power supply, digital output stage only
DD
GND
2, 4, 7, 10, 13, 15, Ground
17, 19, 21, 23, 25,
27, 29, 34, 42
VREF
CLK
3
5
6
2.4 V reference. Bypass to ground with a 0.1-µF microwave chip capacitor.
Clock input. Conversion initiated on rising edge.
Complement of CLK, differential input
CLK
AV
DD
8, 9, 14, 16, 18,
22, 26, 28, 30
5 V analog power supply
AIN
11
Analog input
AIN
12
Complement of AIN, differential analog input
C1
20
Internal voltage reference. Bypass to ground with a 0.1-µF chip capacitor.
Internal voltage reference. Bypass to ground with a 0.1-µF chip capacitor.
Do not connect
C2
24
DNC
31
OVR
32
Overrange bit. A logic level high indicates the analog input exceeds full scale.
DMID
35
Output data voltage midpoint. Approximately equal to (DV )/2
CC
D0 (LSB)
D1−D5, D6−D12
D13 (MSB)
DRY
36
Digital output bit (least significant bit); two’s complement
Digital output bits in two’s complement
Digital output bit (most significant bit); two’s complement
Data ready output
37−41, 44−50
51
52
7
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
DEFINITION OF SPECIFICATIONS
Offset Error
Analog Bandwidth
The analog input frequency at which the power of the
fundamental is reduced by 3 dB with respect to the low
frequency value.
The offset error is the difference, given in number of
LSBs, between the ADC’s actual value average idle
channel output code and the ideal average idle channel
output code. This quantity is often mapped into mV.
Aperture Delay
Temperature Drift
The temperature drift coefficient (with respect to gain
error and offset error) specifies the change per degree
celcius of the paramter from T
computed as the maximum variation of that parameter
over the whole temperature range divided by T
The delay between the rising edge of the input sampling
clock and the actual time at which the sampling occurs.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
or T
. It is
MIN
MAX
−
MAX
Clock Pulse Width/Duty Cycle
T
.
MIN
The duty cycle of a clock signal is the ratio of the time
the clock signal remains at a logic high (clock pulse
width) to the period of the clock signal. Duty cycle is
typically expressed as a percentage. A perfect
differential sine wave clock results in a 50% duty cycle.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (P )
S
to the noise floor power (P ), excluding the power at dc
N
and the first five harmonics.
Maximum Conversion Rate
PS
SNR + 10Log
10 PN
The maximum sampling rate at which certified
operation is given. All parametric testing is performed
at this sampling rate unless otherwise noted.
SNR is either given in units of dBc (dB to carrier) when
the absolute power of the fundamental is used as the
reference or dBFS (dB to full scale) when the power of
the fundamental is extrapolated to the converter’s
full-scale range.
Minimum Conversion Rate
The minimum sampling rate at which the ADC
functions.
Differential Nonlinearity (DNL)
Signal-to-Noise and Distortion (SINAD)
An ideal ADC exhibits code transitions at analog input
values spaced exactly 1 LSB apart. The DNL is the
deviation of any single step from this ideal value,
measured in units of LSB.
SINAD is the ratio of the power of the fundamental (P )
to the power of all the other spectral components
S
including noise (P ) and distortion (P ), but excluding
N
D
dc.
Integral Nonlinearity (INL)
PS
SINAD + 10Log
10 PN ) PD
The INL is the deviation of the ADC’s transfer function
from a best fit line determined by a least squares curve
fit of that transfer function, measured in units of LSB.
SINAD is either given in units of dBc (dB to carrier) when
the absolute power of the fundamental is used as the
reference or dBFS (dB to full scale) when the power of
the fundamental is extrapolated to the converter’s
full-scale range.
Gain Error
The gain error is the deviation of the ADC’s actual input
full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale range.
8
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Total Harmonic Distortion (THD)
Two-Tone Intermodulation Distortion
THD is the ratio of the fundamental power (P ) to the
IMD3 is the ratio of the power of the fundamental (at
frequiencies f1, f2) to the power of the worst spectral
component at either frequency 2f1 − f2 or 2f2 − f1). IMD3 is
either given in units of dBc (dB to carrier) when the
absolute power of the fundamental is used as the
reference or dBFS (dB to full scale) when it is referred to
the full-scale range.
S
power of the first five harmonics (P ).
D
PS
THD + 10Log
10 PD
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR)
The ratio of the power of the fundamental to the highest
other spectral component (either spur or harmonic). SFDR
is typically given in units of dBc (dB to carrier).
9
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TYPICAL CHARACTERISTICS
Typical values are at T = 25°C, AV
= 5 V, DRV = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 105 MSPS, 3 V
DD PP
A
DD
sinusoidal clock, 50% duty cycle, 16k FFT points, unless otherwise noted
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
1
1
0
0
−20
f
f
= 105 MSPS
f = 105 MSPS
S
S
= 2 MHz
f
IN
= 30 MHz
IN
−20
−40
SNR = 74.4 dBc
SINAD = 74.4 dBc
SFDR = 93 dBc
THD = 95 dBc
SNR = 74.4 dBc
SINAD = 74.3 dBc
SFDR = 94 dBc
THD = 93 dBc
−40
−60
−60
−80
−80
X
X
3
4
5
5
3
2
6
−100
−120
−100
−120
6
2
0
0
0
10
20
30
40
50
0
0
0
10
20
30
40
50
f − Frequency − MHz
f − Frequency − MHz
Figure 2
Figure 3
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
1
1
0
−20
0
−20
f
f
= 105 MSPS
= 70 MHz
SNR = 74 dBc
SINAD = 73.9 dBc
SFDR = 92 dBc
THD = 91 dBc
f = 105 MSPS
S
= 100 MHz
IN
SNR = 73.5 dBc
SINAD = 73.3 dBc
SFDR = 87 dBc
THD = 86 dBc
S
IN
f
−40
−40
−60
−60
−80
−80
3
3
X
5
X
2
4
−100
−120
−100
−120
4
2
5
6
6
10
20
30
40
50
10
20
30
40
50
f − Frequency − MHz
f − Frequency − MHz
Figure 4
Figure 5
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
1
1
0
−20
0
−20
f
f
= 105 MSPS
= 170 MHz
SNR = 71.9 dBc
SINAD = 69.1 dBc
SFDR = 72 dBc
THD = 72 dBc
f = 105 MSPS
S
= 230 MHz
SNR = 71 dBc
SINAD = 64.2 dBc
SFDR = 65 dBc
THD = 65 dBc
S
IN
f
IN
−40
−40
−60
−60
3
3
X
−80
−80
5
X
2
4
4
6
5
2
6
−100
−120
−100
−120
10
20
30
40
50
10
20
30
40
50
f − Frequency − MHz
f − Frequency − MHz
Figure 6
Figure 7
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
Typical values are at T = 25°C, AV
DD
= 5 V, DRV
DD
= 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 105 MSPS, 3 V
PP
A
sinusoidal clock, 50% duty cycle, 16k FFT points, unless otherwise noted
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
1
1
0
0
−20
f
f
= 92.16 MSPS
f = 92.16 MSPS
S
S
= 70 MHz
f
IN
= 170 MHz
IN
−20
−40
SNR = 73.9 dBc
SINAD = 73.8 dBc
SFDR = 96 dBc
THD = 95 dBc
SNR = 71.6 dBc
SINAD = 69 dBc
SFDR = 73 dBc
THD = 73 dBc
−40
−60
−60
3
−80
−80
X
4
2
X
5
4
5
2
6
6
−100
−120
−100
−120
0
0
0
10
20
30
40
40
40
0
0
0
10
20
30
40
f − Frequency − MHz
f − Frequency − MHz
Figure 8
Figure 9
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
−20
0
−20
f
f
f
= 92.16 MSPS
1 = 69.2 MHz, −7 dBFS
2 = 70.7 MHz, −7 dBFS
S
IN
IN
f
f
f
= 92.16 MSPS
1 = 169.6 MHz, −7 dBFS
2 = 170.4 MHz, −7 dBFS
S
IN
IN
IMD3 = −93 dBFS
IMD3 = −82 dBFS
−40
−40
−60
−60
−80
−80
−100
−120
−140
−100
−120
−140
10
20
30
10
20
30
40
f − Frequency − MHz
f − Frequency − MHz
Figure 10
Figure 11
WCDMA CARRIER
WCDMA CARRIER
0
−20
0
−20
f
= 92.16 MSPS
= 70 MHz
PAR = 5 dB
ACPR Adj Top = 79.2 dB
ACPR Adj Low = 79.7 dB
f = 92.16 MSPS
S
S
f
IN
f
= 170 MHz
IN
PAR = 5 dB
ACPR Adj Top = 73.3 dB
ACPR Adj Low = 74 dB
−40
−40
−60
−60
−80
−80
−100
−120
−140
−100
−120
−140
10
20
30
f − Frequency − MHz
Figure 12
10
20
30
40
f − Frequency − MHz
Figure 13
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Typical values are at T = 25°C, AV
DD
= 5 V, DRV = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 105 MSPS, 3 V
DD PP
A
sinusoidal clock, 50% duty cycle, 16k FFT points, unless otherwise noted
AC PERFORMANCE
AC PERFORMANCE
vs
INPUT AMPLITUDE
vs
INPUT AMPLITUDE
120
120
100
80
100
SFDR (dBFS)
SFDR (dBFS)
SNR (dBFS)
80
SNR (dBFS)
60
60
SFDR (dBc)
40
SFDR (dBc)
40
20
20
SNR (dBc)
SNR (dBc)
f
= 92.16 MSPS
S
f
f
= 92.16 MSPS
0
S
0
f
IN
= 170 MHz
= 70 MHz
IN
−20
−20
−90 −80 −70 −60 −50 −40 −30 −20 −10
0
−90 −80 −70 −60 −50 −40 −30 −20 −10
0
A
− Input Amplitude − dB
IN
A
− Input Amplitude − dBFS
IN
Figure 14
Figure 15
TWO-TONE SPURIOUS-FREE DYNAMIC RANGE
vs
INPUT AMPLITUDE
NOISE HISTOGRAM WITH INPUTS SHORTED
40
35
30
25
20
15
10
5
120
100
80
SFDR (dBFS)
60
40
SFDR (dBc)
20
90 dBFS Line
f
f
f
= 69 MHz
= 71 MHz
= 92.16 MSPS
IN1
IN2
S
0
−20
0
8174
8175
8176
8177
8178
8179
−110−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
0
Code Number
A
− Input Amplitude − dBFS
IN
Figure 16
Figure 17
TOTAL POWER
vs
SAMPLING FREQUENCY
INPUT BANDWIDTH
1.90
1.89
1.88
1.87
1.86
1.85
1.84
1.83
1.82
1.81
2
0
f
= 70 MHz
IN
−2
−4
−6
−8
−10
f
A
= 105 MSPS
S
= −1 dBFS
IN
0
20
40
60
80
100
120
140
1
10
100
1k
f
− Sampling Frequency − MSPS
f − Frequency − MHz
S
Figure 18
Figure 19
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Typical values are at T = 25°C, AV
DD
= 5 V, DRV
DD
= 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 105 MSPS, 3 V
PP
A
sinusoidal clock, 50% duty cycle, 16k FFT points, unless otherwise noted
AC PERFORMANCE
vs
SPURIOUS-FREE DYNAMIC RANGE
vs
CLOCK COMMON MODE
DUTY CYCLE
100
100
95
90
85
80
75
70
65
f
f
= 105 MSPS
= 69.6 MHz
S
IN
f
= 2 MHz
IN
95
90
85
80
75
70
65
60
SFDR (dBc)
f
= 50 MHz
IN
f
= 70 MHz
IN
SNR (dBc)
0
1
2
3
4
5
40
45
50
55
60
Clock Common Mode − V
Duty Cycle − %
Figure 20
Figure 21
AC PERFORMANCE
vs
AC PERFORMANCE
vs
CLOCK LEVEL
CLOCK LEVEL
95
90
85
80
75
70
65
60
55
50
75
70
65
60
55
50
SFDR (dBc)
SFDR (dBc)
SNR (dBc)
SNR (dBc)
f
f
= 105 MSPS
= 70 MHz
f
f
= 105 MSPS
S
IN
S
= 170 MHz
IN
0
1
2
3
4
0
1
2
3
4
Differential Clock Level − V
Differential Clock Level − V
PP
PP
Figure 22
Figure 23
SPURIOUS-FREE DYNAMIC RANGE
vs
SIGNAL-TO-NOISE RATIO
vs
SUPPLY VOLTAGE AND AMBIENT TEMPERATURE
SUPPLY VOLTAGE AND AMBIENT TEMPERATURE
94
93
92
91
90
89
88
87
86
85
74.8
74.6
74.4
74.2
74.0
73.8
73.6
73.4
73.2
73.0
f
f
= 105 MSPS
= 69.6 MHz
f
f
= 105 MSPS
= 69.6 MHz
S
IN
S
IN
−40°C
100°C
85°C
−20°C
85°C
60°C
−20°C
20°C
60°C
100°C
20°C
−40°C
2.6
2.8
3.0
DRV
3.2
3.4
3.6
3.8
2.6
2.8
3.0
3.2
3.4
3.6
3.8
− Supply Voltage − V
DRV
DD
− Supply Voltage − V
DD
Figure 24
Figure 25
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
Typical values are at T = 25°C, AV
DD
= 5 V, DRV
DD
= 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 105 MSPS, 3 V
PP
A
sinusoidal clock, 50% duty cycle, 16k FFT points, unless otherwise noted
SPURIOUS-FREE DYNAMIC RANGE
SIGNAL-TO-NOISE RATIO
vs
vs
SUPPLY VOLTAGE AND AMBIENT TEMPERATURE
SUPPLY VOLTAGE AND AMBIENT TEMPERATURE
74.6
74.4
74.2
74.0
73.8
73.6
73.4
73.2
73.0
91.0
f
f
= 105 MSPS
= 69.6 MHz
f
f
= 105 MSPS
= 69.6 MHz
S
IN
S
IN
90.5
90.0
89.5
89.0
88.5
88.0
87.5
87.0
86.5
86.0
60°C
−40°C
0°C
−20°C
85°C
40°C
60°C
100°C
85°C
20°C
−40°C
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
4.6
4.8
AV
5.0
5.2
5.4
AV
DD
− Supply Voltage − V
− Supply Voltage − V
DD
Figure 26
Figure 27
DIFFERENTIAL NONLINEARITY
INTEGRAL NONLINEARITY
1.0
0.8
1.5
1.0
0.6
0.4
0.5
0.2
−0.0
−0.2
−0.4
−0.6
−0.8
−1.0
0.0
−0.5
−1.0
−1.5
0
5000
10000
15000
0
5000
10000
Code
15000
Code
Figure 28
Figure 29
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Typical values are at T = 25°C, AV
DD
= 5 V, DRV
DD
= 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 105 MSPS, 3 V
PP
A
sinusoidal clock, 50% duty cycle, 16k FFT points, unless otherwise noted
73
120
71
71
74
110
74
72
100
90
80
70
60
50
40
30
20
10
73
72
74
72
73
70
71
74
69
68
72
70
74
69
73
71
70
67
68
67
69
66
65
62
73
68
71
70
66
69
64
65
63
0
20
40
60
80
100
120
140
160
180
200
220
f
IN
− Input Frequency − MHz
62
64
66
68
70
72
74
SNR − dBc
Figure 30.
79
82
85
76
64
73
70
120
110
100
90
88
88
91
67
85
82
79
91
94
85
91
88
73
76
70
94
91
94
67
80
94
82
94
94
94
85
70
79
94
91
60
94
94
76
73
94
88
73
50
94
94
67
70
40
91
94
85
82
91
94
91
30
79
94
64
20
91
61
70
76
85
10
0
20
40
60
80
100
120
140
160
85
180
200
220
f
IN
− Input Frequency − MHz
60
65
70
75
80
90
SFDR − dBc
Figure 31.
15
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EQUIVALENT CIRCUITS
AV
DD
AIN
BUF
T/H
AV
DD
500 Ω
+
−
25 Ω
V
REF
BUF
V
REF
Bandgap
AV
DD
1.2 kΩ
500 Ω
1.2 kΩ
AIN
BUF
T/H
Figure 35. Reference
Figure 32. Analog Input
DRV
DD
AV
DD
−
+
I
I
P
OUT
OUT
DAC
M
Bandgap
C1, C2
Figure 33. Digital Output
Figure 36. Decoupling Pin
AV
DD
DRV
DD
10 kΩ
CLK
1 kΩ
1 kΩ
Clock Buffer
DMID
Bandgap
AV
DD
10 kΩ
CLK
Figure 37. DMID Generation
Figure 34. Clock Input
16
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APPLICATION INFORMATION
of 2.2 V . The maximum swing is determined by the
PP
internal reference voltage generator eliminating any
external circuitry for this purpose.
THEORY OF OPERATION
The ADS5424 is a 14 bit, 105 MSPS, monolithic
pipeline analog to digital converter. Its bipolar analog
core operates from a 5 V supply, while the output uses
3.3 V supply for compatibility with the CMOS family. The
conversion process is initiated by the rising edge of the
external input clock. At that instant, the differential input
signal is captured by the input track and hold (T&H) and
the input sample is sequentially converted by a series
of small resolution stages, with the outputs combined in
a digital correction logic block. Both the rising and the
falling clock edges are used to propagate the sample
through the pipeline every half clock cycle. This process
results in a data latency of three clock cycles, after
which the output data is available as a 14 bit parallel
word, coded in binary two’s complement format.
The ADS5424 obtains optimum performance when the
analog inputs are driven differentially. The circuit in
Figure 38 shows one possible configuration using an
RF transformer with termination either on the primary or
on the secondary of the transformer. If voltage gain is
required a step up transformer can be used. For higher
gains that would require impractical higher turn ratios on
the transformer, a single-ended amplifier driving the
transformer can be used (see Figure 39). Another
circuit optimized for performance would be the one on
Figure 40, using the THS4304 or the OPA695. Texas
Instruments has shown excellent performance on this
configuration up to 10 dB gain with the THS4304 and at
14 dB gain with the OPA695. For the best performance,
they need to be configured differentially after the
transformer (as shown) or in inverting mode for the
OPA695 (see SBAA113); otherwise, HD2 from the op
amps limits the useful frequency.
INPUT CONFIGURATION
The analog input for the ADS5424 (see Figure 32)
consists of an analog differential buffer followed by a
bipolar track-and-hold. The analog buffer isolates the
source driving the input of the ADC from any internal
switching. The input common mode is set internally
through a 500 Ω resistor connected from 2.4 V to each
of the inputs. This results in a differential input
impedance of 1 kΩ.
R0
Z0
W
50
W
50
AIN
1:1
R
50
AC Signal
Source
ADS5424
W
For a full-scale differential input, each of the differential
lines of the input signal (pins 11 and 12) swings
symmetrically between 2.4 +0.55 V and 2.4 –0.55 V.
This means that each input is driven with a signal of up
to 2.4 0.55 V, so that each input has a maximum signal
AIN
ADT1−1WT
Figure 38. Converting a Single-Ended Input to a
Differential Signal Using RF Transformers
swing of 1.1 V for a total differential input signal swing
PP
5 V
−5 V
R
100 Ω
S
0.1 µF
+
V
IN
R
1:1
IN
AIN
OPA695
R
100 Ω
T
−
ADS5424
AIN
C
IN
R
IN
1000 µF
R
400 Ω
1
A
= 8V/V
R
V
2
(18 dB)
57.5 Ω
Figure 39. Using the OPA695 With the ADS5424
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APPLICATION INFORMATION
R
G
R
F
CM
5 V
−
THS4304
+
1:1
V
IN
AIN
ADS5424
CM
49.9 Ω
5 V
V
REF
From
50 Ω
Source
AIN
+
THS4304
−
CM
R
G
R
F
CM
Figure 40. Using the THS4304 With the ADS5424
Besides these, Texas Instruments offers a wide
selection of single-ended operational amplifiers
(including the THS3201, THS3202 and OPA847) that
can be selected depending on the application. An RF
gain block amplifier, such as Texas Instrument’s
THS9001, can also be used with an RF transformer for
high input frequency applications. For applications
requiring dc-coupling with the signal source, instead of
using a topology with three single ended amplifiers, a
differential input/differential output amplifier like the
THS4509 (see Figure 41) can be used, which
minimizes board space and reduce number of
components.
For this test, an Agilent signal generator is used for the
signal source. The generator is an ac-coupled 50 Ω
source. A band-pass filter is inserted in series with the
input to reduce harmonics and noise from the signal
source.
Input termination is accomplished via the 69.8 Ω
resistor and 0.22 µF capacitor to ground in conjunction
with the input impedance of the amplifier circuit. A
0.22 µF capacitor and 49.9 Ω resistor is inserted to
ground across the 69.8 Ω resistor and 0.22 µF capacitor
on the alternate input to balance the circuit.
Gain is a function of the source impedance, termination,
and 348 Ω feedback resistor. See the THS4509 data
sheet for further component values to set proper 50 Ω
termination for other common gains.
Figure 43 shows their combined SNR and SFDR
performance versus frequency with −1 dBFS input
signal level and sampling at 80MSPS.
Since
common-mode voltage is +2.4 V, the THS4509 is
operated from a single power supply input with V
the
ADS5424
recommended
input
On this configuration, the THS4509 amplifier circuit
provides 10 dB of gain, converts the single-ended input
to differential, and sets the proper input common-mode
voltage to the ADS5424.
=
S+
+5 V and V = 0 V (ground). This maintains maximum
S−
headroom on the internal transistors of the THS4509.
The 225 Ω resistors and 2.7 pF capacitor between the
THS4509 outputs and ADS5424 inputs (along with the
input capacitance of the ADC) limit the bandwidth of the
signal to about 100 MHz (−3 dB).
18
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APPLICATION INFORMATION
V
IN
From
50 Ω
Source
100 Ω
348 Ω
+5V
configurations. In low input frequency applications,
where jitter may not be a big concern, the use of
single-ended clock (see Figure 43) could save some
cost and board space without any trade-off in
performance. When driven on this configuration, it is
best to connect CLKM (pin 11) to ground with a 0.01 µF
capacitor, while CLKP is ac-coupled with a 0.01 µF
capacitor to the clock source, as shown in Figure 40.
14-Bit
105 MSPS
69.8 Ω
225 Ω
225 Ω
0.22 µF
100 Ω
A
IN
2.7 pF
ADS5424
THS4509
CM
A
IN
V
REF
49.9 Ω
69.8 Ω
49.9 Ω
0.1 µF
0.22 µF
0.22 µF
0.1 µF
348 Ω
0.1 µF
1:4
Clock
CLK
Figure 41. Using the THS4509 With the ADS5424
Source
ADS5424
MA3X71600LCT−ND
PERFORMANCE
vs
CLK
INPUT FREQUENCY
95
90
Figure 44. Differential Clock
Nevertheless, for jitter sensitive applications, the use of
a differential clock will have some advantages (as with
any other ADCs) at the system level. The first
advantage is that it allows for common-mode noise
rejection at the PCB level. A further analysis (see
Clocking High Speed Data Converters, SLYT075)
reveals one more advantage. The following formula
describes the different contributions to clock jitter:
SFDR (dBc)
85
80
SNR (dBFS)
75
70
2
2
2
2
(Jittertotal) = (EXT_jitter) + (ADC_jitter) =
10
20
30
40
50
60
70
2
2
(EXT_jitter) + (ADC_int) + (K/clock_slope)
f
− Input Frequency − MHz
IN
The first term would represent the external jitter, coming
from the clock source, plus noise added by the system
on the clock distribution, up to the ADC. The second
term is the ADC contribution, which can be divided in
two portions. The first does not depend directly on any
external factor. That is the best we can get out of our
ADC. The second contribution is a term inversely
proportional to the clock slope. The faster the slope, the
smaller this term will be. As an example, we could
compute the ADC jitter contribution from a sinusoidal
Figure 42. Performance vs Input Frequency for
the THS4509 + ADS5424 Configuration
CLK
Square Wave or
Sine Wave
0.01 µF
0.01 µF
ADS5424
CLK
input clock of 3 V amplitude and Fs = 80 MSPS:
pp
2
−5
ADC_jitter = sqrt ((150fs) + (5 x 10 /(1.5 x 2 x PI x 80
x 10 )) ) = 164fs
6 2
Figure 43. Single-Ended Clock
The use of differential clock allows for the use of bigger
clock amplitudes without exceeding the absolute
maximum ratings. This, on the case of sinusoidal clock,
results on higher slew rates which minimizes the impact
of the jitter factor inversely proportional to the clock
slope.
CLOCK INPUTS
The ADS5424 clock input can be driven with either a
differential clock signal or a single-ended clock input,
with little or no difference in performance between both
19
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
APPLICATION INFORMATION
Figure 44 shows this approach. The back-to-back
Schottky can be added to limit the clock amplitude in
cases where this would exceed the absolute maximum
ratings, even when using a differential clock. Figure 22
and Figure 23 show the performance versus input clock
amplitude for a sinusoidal clock.
DIGITAL OUTPUTS
The ADC provides 14 data outputs (D13 to D0, with D13
being the MSB and D0 the LSB), a data-ready signal
(DRY, pin 52), and an out-of-range indicator (OVR, pin
32) that equals 1 when the output reaches the full-scale
limits.
The output format is two’s complement. When the input
voltage is at negative full scale (around −1.1 V
differential), the output will be, from MSB to LSB, 10
0000 0000 0000. Then, as the input voltage is
increased, the output switches to 10 0000 0000 0001,
10 0000 0000 0010 and so on until 11 1111 1111 1111
right before mid-scale (when both inputs are tight
together if we neglect offset errors). Further increases
on input voltage, outputs the word 00 0000 0000 0000,
to be followed by 00 0000 0000 0001, 00 0000 0000
0010 and so on until reaching 01 1111 1111 1111 at
full-scale input (1.1-V differential).
100 nF
MC100EP16DT
Q
100 nF
100 nF
CLK
D
D
V
BB
Q
ADS5424
CLK
100 nF
499 W
499 W
50 Ω
50 Ω
100 nF
113 Ω
Although the output circuitry of the ADS5424 has been
designed to minimize the noise produced by the
transients of the data switching, care must be taken
when designing the circuitry reading the ADS5424
outputs. Output load capacitance should be minimized
by minimizing the load on the output traces, reducing
their length and the number of gates connected to them,
and by the use of a series resistor with each pin. Typical
numbers on the data sheet tables and graphs are
obtained with 100 Ω series resistor on each digital
output pin, followed by a 74AVC16244 digital buffer as
the one used in the evaluation board.
Figure 45. Differential Clock Using PECL Logic
Another possibility is the use of a logic based clock, as
PECL. In this case, the slew rate of the edges will most
likely be much higher than the one obtained for the
same clock amplitude based on a sinusoidal clock. This
solution would minimize the effect of the slope
dependent ADC jitter. Nevertheless, observe that for
the ADS5424, this term is small and has been
optimized. Using logic gates to square a sinusoidal
clock may not produce the best results as logic gates
may not have been optimized to act as comparators,
adding too much jitter while squaring the inputs.
POWER SUPPLIES
The use of low noise power supplies with adequate
decoupling is recommended, being the linear supplies
the first choice versus switched ones, which tend to
generate more noise components that can be coupled
to the ADS5424.
The common-mode voltage of the clock inputs is set
internally to 2.4 V using internal 1 kΩ resistors. It is
recommended to use an ac coupling, but if for any
reason, this scheme is not possible, due to, for
instance, asynchronous clocking, the ADS5424
presents a good tolerance to clock common-mode
variation (see Figure 20).
Additionally, the internal ADC core uses both edges of
the clock for the conversion process. This means that,
ideally, a 50% duty cycle should be provided. Figure 21
shows the performance variation of the ADC versus
clock duty cycle.
20
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
APPLICATION INFORMATION
The ADS5424 uses two power supplies. For the analog
portion of the design, a 5 V AV is used, while for the
LAYOUT INFORMATION
DD
The evaluation board represents a good guideline of
how to layout the board to obtain the maximum
performance out of the ADS5424. General design rules
as the use of multilayer boards, single ground plane for
both, analog and digital ADC ground connections and
local decoupling ceramic chip capacitors should be
applied. The input traces should be isolated from any
external source of interference or noise, including the
digital outputs as well as the clock traces. Clock should
also be isolated from other signals, especially on
applications where low jitter is required, as high IF
sampling.
digital outputs supply (DRV ), we recommend the use
DD
of 3.3 V. All the ground pins are marked as GND,
although AGND pins and DRGND pins are not tied
together inside the package. Customers willing to
experiment with different grounding schemes should
know that AGND pins are 4, 7, 10, 13, 15, 17, 19, 21,
23, 25, 27, and 29, while DRGND pins are 2, 34, and 42.
Nevertheless, we recommend that both grounds are
tied together externally, using a common ground plane.
That is the case on the production test boards and
modules provided to customer for evaluation. In order
to obtain the best performance, user should layout the
board to guarantee that the digital return currents do not
flow under the analog portion of the board. This can be
achieved without the need to split the board and just
with careful component placing and increasing the
number of vias and ground planes.
Besides performance oriented rules, special care has
to be taken when considering the heat dissipation out
of the device. The thermal heat sink (octagonal, with
2,5 mm on each side) should be soldered to the board,
and provision for more than 16 ground vias should be
made. The thermal package information describes the
Finally, notice that the metallic heat sink under the
package is also connected to analog ground.
T
values obtained on the different configurations.
JA
21
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
MECHANICAL DATA
Center Power Pad Solder Stencil Opening
Stencil Thicknes s
0.1m m
X
7.0
6.5
Y
7.0
6.5
0.127m m
0.152m m
0.178m m
6.0
5.6
6.0
5.6
22
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SLWS157A − JANUARY 2005 − REVISED MAY 2005
MECHANICAL DATA
PJY (S−PQFP−G52)
PLASTIC QUAD FLATPACK
23
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