ADS5433IPJY [TI]
14 BIT, 80 MSPS ANALOG-TO-DIGITAL CONVERTER; 14位， 80 MSPS模拟数字转换器
| 型号： | ADS5433IPJY |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 14 BIT, 80 MSPS ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总22页 (文件大小：1318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS5433
ADS5433
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SLAS503–APRIL 2006
14 BIT, 80 MSPS ANALOG-TO-DIGITAL CONVERTER
FEATURES
•
•
•
52 Pin HTQFP Package With Exposed
Heatsink
•
•
•
14 Bit Resolution
Pin Compatible to the ADS5423, ADS5424,
and AD6644/45
80 MSPS Maximum Sample Rate
Typical SNR = 74.4 dBc at 80 MSPS and
30 MHz IF
Industrial Temperature Range = –40°C to
85°C
•
•
Typical SFDR = 96.5 dBc at 80 MSPS and
30 MHz IF
APPLICATIONS
Assured SFDR = 91 dBc at 80 MSPS and
30 MHz IF
•
•
•
•
Single and Multichannel Digital Receivers
Base Station Infrastructure
Instrumentation
•
•
•
•
•
•
2.2 Vpp Differential Input Range
5 V Supply Operation
Video and Imaging
3.3 V CMOS Compatible Outputs
1.85 W Total Power Dissipation
2s Complement Output Format
RELATED DEVICES
•
•
Clocking: CDC7005
Amplifiers: OPA695, THS4509
On-Chip Input Analog Buffer, Track and Hold,
and Reference Circuit
DESCRIPTION
The ADS5433 is a 14 bit 80 MSPS analog-to-digital converter (ADC) that operates from 5 V and 3.3 V supplies
while providing 3.3 V CMOS compatible digital outputs. The ADS5433 is optimized for spurious-free dynamic
range (SFDR). Pin-compatible to the ADS5423, ADS5424, and AD6644/45, the ADS5433 provides enhanced
SFDR for input frequencies up to 100 MHz. At 80 MSPS, SFDR is typically 96.5 dBc and is guaranteed to 91
dBc over the industrial temperature range (-40°C to 85°C) with a -1 dBFS 30 MHz input signal.
The ADS5433 input buffer isolates the internal switching of the on-chip Track and Hold (T&H) from disturbing the
signal source. A 2.2 VPP input range and internal reference generator simplify system design. The ADS5433 is
available in a 52 pin HTQFP package and is built on Texas Instrument’s complementary bipolar process
(BiCom3).
FUNCTIONAL BLOCK DIAGRAM
AV
DRV
DD
DD
AIN
AIN
+
+
A3
A2
TH3
TH2
TH1
ADC3
Σ
Σ
A1
−
−
ADC1
DAC1
VREF
ADC2
DAC2
Reference
6
5
5
C1
C2
Digital Error Correction
CLK
CLK
Timing
DMID OVR DRY
D[13:0]
GND
B0061-02
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS5433
www.ti.com
SLAS503–APRIL 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
LEAD
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QTY
PRODUCT
ADS5433IPJY
Tray, 160
HTQFP-
ADS5433
PJY
-40°C to 85°C
ADS5433I
52(1)PowerPAD™
ADS5433IPJYR Tape and Reel, 1000
(1) Thermal pad size: Octagonal 2,5 mm side
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
ADS5433
UNIT
AVDD to GND
Supply voltage
6
5
V
DRVDD to GND
Analog input to GND
–0.3 to AVDD + 0.3
–0.3 to AVDD + 0.3
±2.5
V
V
Clock input to GND
CLK to CLK
V
Digital data output to GND
Operating temperature range
Maximum junction temperature
Storage temperature range
–0.3 to DRVDD + 0.3
–40 to 85
V
°C
°C
°C
150
–65 to 150
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
THERMAL CHARACTERISTICS(1)
PARAMETER
TEST CONDITIONS
TYP
22.5
15.8
33.3
25.9
2
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
θJA
θJA
θJA
θJA
θJC
Soldered slug, no airflow
Soldered slug, 200-LPFM airflow
Unsoldered slug, no airflow
Unsoldered slug, 200-LPFM airflow
Bottom of package (heatslug)
(1) Using 25 thermal vias (5 × 5 array). See the Application Section.
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RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage
4.75
3
5
5.25
3.6
V
V
DRVDD
Output driver supply voltage
3.3
ANALOG INPUT
Differential input range
Input common-mode voltage
DIGITAL OUTPUT
Maximum output load
CLOCK INPUT
ADCLK input sample rate (sine wave) 1/tC
2.2
2.4
VPP
V
VCM
10
pF
30
80
85
MSPS
VPP
Clock amplitude, sine wave, differential(1)
Clock duty cycle(2)
3
50%
Open free-air temperature range
–40
°C
(1) See Figure 12 and Figure 13 for more information.
(2) See Figure 11 for more information.
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ELECTRICAL CHARACTERISTICS
Over full temperature range (TMIN = –40°C to TMAX = 85°C), sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 5 V,
DRVDD = 3.3 V, –1 dBFS differential input, and 3 VPP differential sinusoidal clock, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
ANALOG INPUTS
Differential input range
14
Bits
2.2
1
VPP
kΩ
Differential input resistance
Differential input capacitance
See Figure 27
See Figure 27
1.5
570
pF
Analog input bandwidth
MHz
INTERNAL REFERENCE VOLTAGES
VREF
DYNAMIC ACCURACY
No missing codes
Reference voltage
2.4
V
Tested
±0.5
±1.5
0
DNL
INL
Differential linearity error
Integral linearity error
Offset error
fIN = 10 MHz
fIN = 10 MHz
–0.95
–5
1.5
5
LSB
LSB
mV
Offset temperature coefficient
Gain error
1.7
0.9
1
ppm/°C
%FS
–5
5
PSRR
mV/V
ppm/°C
Gain temperature coefficient
77
POWER SUPPLY
IAVDD
Analog supply current
VIN = full scale, fIN = 30 MHz
VIN = full scale, fIN = 30 MHz
355
35
410
47
mA
mA
IDRVDD
Output buffer supply current
Total power with 10-pF load on each digital
output to ground, fIN = 70 MHz
Power dissipation
1.85
20
2.2
W
Power-up time
100
ms
DYNAMIC AC CHARACTERISTICS
fIN = 10 MHz
fIN = 30 MHz
fIN = 50 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 30 MHz
fIN = 50 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
74.6
74.4
74.3
74
73
73
SNR
Signal-to-noise ratio
dBc
73.4
71.9
70.5
95.3
96.5
95.7
90.8
84
91
SFDR
Spurious-free dynamic range
dBc
70
61.3
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ELECTRICAL CHARACTERISTICS (Continued)
Over full temperature range (TMIN = –40°C to TMAX = 85°C), sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 5 V,
DRVDD = 3.3 V, –1 dBFS differential input, and 3 VPP differential sinusoidal clock, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC AC CHARACTERISTICS (Continued)
fIN = 10 MHz
fIN = 30 MHz
fIN = 50 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 30 MHz
fIN = 50 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 30 MHz
fIN = 50 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 30 MHz
fIN = 50 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
72.8
74.5
74.4
74.2
73.8
73
SINAD
Signal-to-noise + distortion
dBc
67.4
59.9
105
103
103
94
HD2
Second harmonic
dBc
96
77
67
97
101
97
HD3
Third harmonic
91
dBc
84
70
61
99
98
99
Worst-harmonic/spur (other than
HD2 and HD3)
98
dBc
LSB
98
94
92
RMS idle channel noise
Input pins tied together
0.9
DIGITAL CHARACTERISTICS
Over full temperature range (TMIN = –40°C to TMAX = 85°C), AVDD = 5 V, DRVDD = 3.3 V, unless otherwise noted
PARAMETER
DIGITAL OUTPUTS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Low-level output voltage
High-level output voltage
Output capacitance
DMID
CLOAD = 10 pF(1)
CLOAD = 10 pF(1)
0.1
3.2
0.6
V
V
2.6
3
pF
V
DRVDD/2
(1) Equivalent capacitance to ground of (load + parasitics of transmission lines).
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TIMING REQUIREMENTS(1)
Over full temperature range, AVDD = 5 V, DRVDD = 3.3 V, sampling rate = 80 MSPS
PARAMETER
MIN
TYP
MAX
UNIT
APERTURE TIME
tA
tJ
Aperture delay
500
150
50
ps
fs
Clock slope independent aperture uncertainity (jitter)
Clock slope dependent jitter factor
kJ
µV
CLOCK INPUT
tCLK
Clock period
12.5
6.25
6.25
ns
ns
ns
(2)
(2)
tCLKH
tCLKL
Clock pulsewidth high
Clock pulsewidth low
CLOCK TO DATAREADY (DRY)
tDR
Clock rising 50% to DRY falling 50%
2.8
9
3.9
tDR + tCLKH
10.1
4.7
11
ns
ns
ns
tC_DR
Clock rising 50% to DRY rising 50%
tC_DR_50%
Clock rising 50% to DRY rising 50% with 50% duty cycle clock
CLOCK TO DATA, OVR(4)
tr
Data VOL to data VOH (rise time)
2
2
ns
ns
tf
Data VOH to data VOL (fall time)
L
Latency
3
Cycles
ns
tsu(C)
tH(C)
Valid DATA(3) to clock 50% with 50% duty cycle clock (setup time)
Clock 50% to invalid DATA(3) (hold time)
4.8(4)
2.6
6.3
3.6
ns
DATAREADY (DRY) to DATA, OVR(5)
tsu(DR)_50%
Valid DATA(3) to DRY 50% with 50% duty cycle clock (setup time)
th(DR)_50%
DRY 50% to invalid DATA(3) with 50% duty cycle clock (hold time)
3.3(6)
5.4
4
ns
ns
5.9
(1) All values obtained from design and characterization.
(2) See Figure 1 for more information.
(3) See VOH and VOL levels.
(4) tSU(C) = tCLK– tCLK(min) + tSU(C)(min), where tCLK(min) = 12.5 ns and tSU(C)(min) = 4.8 ns for all sample rates equal to or below 80MSPS.
(5) Data is updated with clock rising edge or DRY falling edge.
(6) tSU(DR)50% = (tCLK / 2) – (tCLK(min) / 2) + tSU(DR)(min), where tCLK(min) = 12.5 ns and tSU(DR)(min) = 3.3 ns for all sample rates equal to or
below 80MSPS.
t
A
N+3
N
AIN
N+1
N+2
N+4
t
t
CLKL
t
CLKH
CLK
CLK, CLK
N + 1
N + 2
N + 3
N + 4
N
t
h(C)
t
t
su(C)
C_DR
D[13:0], OVR
DRY
N−3
N−2
N−1
N
t
t
h(DR)
su(DR)
t
r
t
f
t
DR
T0073-02
Figure 1. Timing Diagram
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PIN CONFIGURATION
PJY PACKAGE
(TOP VIEW)
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
38
37
36
35
34
33
32
31
30
29
28
27
DRV
D3
D2
D1
D0 (LSB)
DMID
GND
DD
2
GND
VREF
GND
CLK
CLK
GND
3
4
5
6
7
GND
DRV
DD
8
AV
AV
OVR
DNC
DD
9
DD
10
11
12
13
GND
AIN
AIN
AV
DD
GND
AV
DD
GND
GND
14 15 16 17 18 19 20 21 22 23 24 25 26
P0041-01
PIN ASSIGNMENTS
TERMINAL
NAME
DESCRIPTION
3.3 V power supply, digital output stage only
NO.
DRVDD
GND
1, 33, 43
2, 4, 7, 10, 13, 15, Ground
17, 19, 21, 23, 25,
27, 29, 34, 42
VREF
CLK
3
5
6
2.4 V reference. Bypass to ground with a 0.1-µF microwave chip capacitor.
Clock input. Conversion initiated on rising edge.
CLK
Complement of CLK, differential input
AVDD
8, 9, 14, 16, 18, 22, 5 V analog power supply
26, 28, 30
AIN
11
Analog input
AIN
12
Complement of AIN, differential analog input
Internal voltage reference. Bypass to ground with a 0.1-µF chip capacitor.
Internal voltage reference. Bypass to ground with a 0.1-µF chip capacitor.
Do not connect
C1
20
C2
24
DNC
31
OVR
32
Overrange bit. A logic level high indicates the analog input exceeds full scale.
Output data voltage midpoint. Approximately equal to (DVCC)/2
Digital output bit (least significant bit); two's complement
Digital output bits in two's complement
DMID
35
D0 (LSB)
D1–D5, D6–D12
D13 (MSB)
DRY
36
37–41, 44–50
51
52
Digital output bit (most significant bit); 2s complement
Data ready output
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DEFINITION OF SPECIFICATIONS
Offset Error
Analog Bandwidth
The analog input frequency at which the power of the
fundamental is reduced by 3 dB with respect to the
low frequency value.
The offset error is the difference, given in number of
LSBs, between the ADC's actual value average idle
channel output code and the ideal average idle
channel output code. This quantity is often mapped
into mV.
Aperture Delay
The delay in time between the rising edge of the
input sampling clock and the actual time at which the
sampling occurs.
PSRR
The maximum change in offset voltage divided by
the total change in supply voltage, in units of mV/V.
Aperture Uncertainty (Jitter)
Temperature Drift
The sample-to-sample variation in aperture delay.
The temperature drift coefficient (with respect to gain
error and offset error) specifies the change per
degree celcius of the paramter from TMIN or TMAX. It
is computed as the maximum variation of that
parameter over the whole temperature range divided
Clock Pulse Width/Duty Cycle
The duty cycle of a clock signal is the ratio of the
time the clock signal remains at a logic high (clock
pulse width) to the period of the clock signal. Duty
cycle is typically expressed as a percentage. A
perfect differential sine wave clock results in a 50%
duty cycle.
by TMAX – TMIN
.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at
dc and the first five harmonics.
Maximum Conversion Rate
The maximum sampling rate at which certified
operation is given. All parametric testing is performed
at this sampling rate unless otherwise noted.
PS
10 PN
SNR + 10Log
(1)
SNR is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference or dBFS (dB to full scale) when the
power of the fundamental is extrapolated to the
converter's full-scale range.
Minimum Conversion Rate
The minimum sampling rate at which the ADC
functions.
Differential Nonlinearity (DNL)
Signal-to-Noise and Distortion (SINAD)
An ideal ADC exhibits code transitions at analog
input values spaced exactly 1 LSB apart. The DNL is
the deviation of any single step from this ideal value,
measured in units of LSB.
SINAD is the ratio of the power of the fundamental
(PS) to the power of all the other spectral
components including noise (PN) and distortion (PD),
but excluding dc.
Integral Nonlinearity (INL)
PS
SINAD + 10Log
10 PN ) PD
The INL is the deviation of the ADC's transfer
function from a best fit line determined by a least
squares curve fit of that transfer function, measured
in units of LSB.
(2)
SINAD is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference or dBFS (dB to full scale) when the
power of the fundamental is extrapolated to the
converter's full-scale range.
Gain Error
The gain error is the deviation of the ADC's actual
input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input
full-scale range.
Total Harmonic Distortion (THD)
THD is the ratio of the fundamental power (PS) to the
power of the first five harmonics (PD).
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PS
Two-Tone Intermodulation Distortion
THD + 10Log
10 PD
(3)
IMD3 is the ratio of the power of the fundamental (at
frequiencies f1, f2) to the power of the worst spectral
component at either frequency 2f1 – f2 or 2f2 – f1).
IMD3 is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference or dBFS (dB to full scale) when it is
referred to the full-scale range.
THD is typically given in units of dBc (dB to carrier).
Power Up Time
The difference in time from the point where the
supplies are stable at ±5% of the final value, to the
time the ac test is past.
Spurious-Free Dynamic Range (SFDR)
The ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc
(dB to carrier).
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TYPICAL CHARACTERISTICS
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 80 MSPS,
3.3 VPP sinusoidal clock, 50% duty cycle, 16k FFT points, unless otherwise noted
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
−20
0
−20
f
f
= 80 MSPS
f
f
= 80 MSPS
S
S
= 30 MHz
= 2 MHz
IN
IN
SNR = 74.4 dBc
SINAD = 74.3 dBc
SFDR = 97.2 dBc
THD = 95.5 dBc
SNR = 74.5 dBc
SINAD = 74.4 dBc
SFDR = 95.7 dBc
THD = 89.9 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
0
0
5
10
15
20
25
30
35
40
0
0
0
5
10
15
20
25
30
35
40
f − Frequency − MHz
f − Frequency − MHz
G002
G001
G003
G005
Figure 2.
Figure 3.
SPECTRAL PERFORMANCE
TWO-TONE INTERMODULATION DISTORTION
0
−20
0
−20
f
f
= 80 MSPS
= 70 MHz
SNR = 74 dBc
SINAD = 73.9 dBc
SFDR = 93.7 dBc
THD = 90.6 dBc
f
f
= 19.8 MHz, −7 dBFS
= 20.2 MHz, −7 dBFS
IMD3 = −100.1 dBFS
S
IN1
IN2
IN
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
5
10
15
20
25
30
35
40
5
10
15
20
25
30
35
40
f − Frequency − MHz
f − Frequency − MHz
G004
Figure 4.
Figure 5.
TWO-TONE INTERMODULATION DISTORTION
TWO-TONE INTERMODULATION DISTORTION
0
−20
0
−20
f
f
= 59.8 MHz, −7 dBFS
= 60.2 MHz, −7 dBFS
IMD3 = −103.6 dBFS
f
f
= 19.8 MHz, −15 dBFS
= 20.2 MHz, −15 dBFS
IMD3 = −105.9 dBFS
IN1
IN2
IN1
IN2
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
5
10
15
20
25
30
35
40
5
10
15
20
25
30
35
40
f − Frequency − MHz
f − Frequency − MHz
G006
Figure 6.
Figure 7.
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TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 80 MSPS,
3.3 VPP sinusoidal clock, 50% duty cycle, 16k FFT points, unless otherwise noted
TWO-TONE INTERMODULATION DISTORTION
AC PERFORMANCE vs INPUT AMPLITUDE
0
−20
120
100
80
SFDR (dBFS)
f
f
= 59.8 MHz, −15 dBFS
= 60.2 MHz, −15 dBFS
IN1
IN2
IMD3 = −110.3 dBFS
SNR (dBFS)
−40
60
−60
SFDR (dBc)
40
−80
20
SNR (dBc)
−100
−120
f
= 80 MSPS
0
S
f
IN
= 30 MHz
−20
0
5
10
15
20
25
30
35
40
−90 −80 −70 −60 −50 −40 −30 −20 −10
0
f − Frequency − MHz
A
IN
− Input Amplitude − dBFS
G007
G008
Figure 8.
Figure 9.
AC PERFORMANCE vs INPUT AMPLITUDE
TWO-TONE SPURIOUS-FREE DYNAMIC RANGE vs INPUT
AMPLITUDE
120
100
80
120
SFDR (dBFS)
100
SFDR (dBFS)
SNR (dBFS)
80
60
60
SFDR (dBc)
40
40
SFDR (dBc)
20
20
90 dBFS Line
SNR (dBc)
f
f
f
= 80 MSPS
S
f
f
= 80 MSPS
0
0
S
= 69 MHz
= 71 MHz
IN1
IN2
= 70 MHz
IN
−20
−20
−90 −80 −70 −60 −50 −40 −30 −20 −10
0
−110−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
0
A
IN
− Input Amplitude − dBFS
A
IN
− Input Amplitude − dBFS
G009
G010
Figure 10.
Figure 11.
NOISE HISTOGRAM WITH INPUTS SHORTED
SPURIOUS-FREE DYNAMIC RANGE vs DUTY CYCLE
45
40
35
30
25
20
15
10
5
100
95
90
85
80
75
f
= 2 MHz
IN
f
= 30 MHz
IN
0
8169 8170 8171 8172 8173 8174 8175 8176 8177
30
40
50
60
70
Code Number
Duty Cycle − %
G011
G012
Figure 12.
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 80 MSPS,
3.3 VPP sinusoidal clock, 50% duty cycle, 16k FFT points, unless otherwise noted
AC PERFORMANCE vs CLOCK LEVEL
AC PERFORMANCE vs CLOCK LEVEL
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
SFDR (dBc)
SFDR (dBc)
SNR (dBc)
SNR (dBc)
f
f
= 80 MSPS
= 30 MHz
f
f
= 80 MSPS
= 70 MHz
S
S
IN
IN
0
1
2
3
4
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Clock Level − V
Clock Level − V
PP
PP
G013
G014
Figure 14.
AC PERFORMANCE vs CLOCK COMMON MODE
Figure 15.
SPURIOUS-FREE DYNAMIC RANGE vs ANALOG SUPPLY
VOLTAGE
120
110
100
90
99
40°C
f
f
= 80 MSPS
= 30 MHz
S
−20°C
0°C
IN
98
97
96
95
94
93
SFDR (dBc)
SNR (dBc)
80
70
60
60°C
85°C
50
−40°C
f
f
= 80 MSPS
= 30 MHz
S
40
IN
30
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
4.65
4.75
4.85
4.95
5.05
5.15
5.25
5.35
Clock Common Mode − V
AV − Analog Supply Voltage − V
DD
G015
G016
Figure 16.
Figure 17.
SIGNAL-TO-NOISE RATIO vs ANALOG SUPPLY VOLTAGE
SPURIOUS-FREE DYNAMIC RANGE vs DIGITAL SUPPLY
VOLTAGE
75.2
99
−20°C
−40°C
0°C
−20°C
75.0
74.8
74.6
74.4
74.2
74.0
73.8
73.6
73.4
98
97
96
0°C
40°C
85°C
40°C
95
−40°C
60°C
94
60°C
f
f
= 80 MSPS
= 30 MHz
f
f
= 80 MSPS
= 30 MHz
S
S
85°C
IN
IN
93
4.65
4.75
4.85
4.95
5.05
5.15
5.25
5.35
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
AV − Analog Supply Voltage − V
DD
DRV − Digital Supply Voltage − V
DD
G017
G018
Figure 18.
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 80 MSPS,
3.3 VPP sinusoidal clock, 50% duty cycle, 16k FFT points, unless otherwise noted
SIGNAL-TO-NOISE RATIO vs DIGITAL SUPPLY VOLTAGE
DIFFERENTIAL NONLINEARITY
75.2
1.0
0.8
f
= 10 MHz
−40°C
IN
−20°C
75.0
0.6
74.8
74.6
0.4
0.2
0°C
74.4
0.0
74.2
74.0
−0.2
−0.4
−0.6
−0.8
−1.0
73.8
40°C
60°C
85°C
f
f
= 80 MSPS
= 30 MHz
S
73.6
73.4
IN
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
0
5000
10000
15000
DRV − Digital Supply Voltage − V
DD
Code
G019
G020
Figure 20.
Figure 21.
DIFFERENTIAL NONLINEARITY
INTEGRAL NONLINEARITY
1.5
1.0
1.0
0.8
f
= 30 MHz
IN
f
= 10 MHz
IN
0.6
0.4
0.5
0.2
0.0
0.0
−0.2
−0.4
−0.6
−0.8
−1.0
−0.5
−1.0
−1.5
0
5000
10000
Code
15000
0
5000
10000
15000
Code
G021
G022
Figure 22.
Figure 23.
INTEGRAL NONLINEARITY
2.0
f
= 30 MHz
IN
1.5
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
0
5000
10000
Code
15000
G023
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3 V, differential input amplitude = –1 dBFS, sampling rate = 80 MSPS,
3.3 VPP sinusoidal clock, 50% duty cycle, 16k FFT points, unless otherwise noted
SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY AND SAMPLING FREQUENCY
120
72
74
73
110
74
100
90
73
80
72
70
74
60
73
72
50
74
70
40
70
73
72
68
30
70
68
66
64
20
20
40
60
80
100
120
140
160
f
- Input Frequency - MHz
IN
62
64
66
68
70
72
74
SNR - dBc
M0048-07
Figure 25.
SPURIOUS-FREE DYNAMIC RANGE vs INPUT FREQUENCY AND SAMPLING FREQUENCY
90
120 94
110
100
90
84
92
84
76
72
90
80
88
88
94
92
90
88
92
84
94
96
80
96
76
70
72
90
92
80
96
60
50
40
30
20
88
96
94
96
92
90
84
94
72
76
88
96
80
20
40
60
80
100
120
140
160
f
- Input Frequency - MHz
IN
70
75
80
85
90
95
100
SFDR - dBc
M0048-08
Figure 26.
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EQUIVALENT CIRCUITS
DRV
AV
DD
DD
AIN
BUF
T/H
500 Ω
VREF
BUF
AV
DD
500 Ω
S0187-01
AIN
BUF
T/H
S0186-01
Figure 27. Analog Input
Figure 28. Digital Output
AV
AV
DD
DD
+
−
25 Ω
CLK
VREF
Bandgap
1 kΩ
Clock Buffer
1.2 kΩ
Bandgap
1.2 kΩ
AV
DD
1 kΩ
S0189-01
CLK
S0188-01
Figure 29. Clock Input
Figure 30. Reference
DRV
AV
DD
DD
10 kΩ
DMID
−
+
I
I
P
OUT
DAC
M
OUT
Bandgap
10 kΩ
C1, C2
S0190-01
S0191-01
Figure 31. Decoupling Pin
Figure 32. DMID Generation
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APPLICATION INFORMATION
maximum signal swing of 1.1 VPP for a total
differential input signal swing of 2.2 VPP. The
maximum swing is determined by the internal
reference voltage generator eliminating any external
circuitry for this purpose.
THEORY OF OPERATION
The ADS5433 is a 14 bit, 80 MSPS, monolithic
pipeline analog to digital converter. Its bipolar analog
core operates from a 5 V supply, while the output
uses 3.3 V supply for compatibility with the CMOS
family. The conversion process is initiated by the
rising edge of the external input clock. At that instant,
the differential input signal is captured by the input
track and hold (T&H) and the input sample is
sequentially converted by a series of small resolution
stages, with the outputs combined in a digital
correction logic block. Both the rising and the falling
clock edges are used to propagate the sample
through the pipeline every half clock cycle. This
process results in a data latency of three clock
cycles, after which the output data is available as a
14 bit parallel word, coded in binary two's
complement format.
The ADS5433 obtains optimum performance when
the analog inputs are driven differentially. The circuit
in Figure 33 shows one possible configuration using
an RF transformer with termination either on the
primary or on the secondary of the transformer. If
voltage gain is required a step up transformer can be
used. For higher gains that would require impractical
higher turn ratios on the transformer, a single-ended
amplifier driving the transformer can be used (see
Figure 34). Another circuit optimized for performance
would be the one on Figure 35, using the THS4304
or the OPA695. Texas Instruments has shown
excellent performance on this configuration up to 10
dB gain with the THS4304 and at 14 dB gain with the
OPA695. For the best performance, they need to be
configured differentially after the transformer (as
shown) or in inverting mode for the OPA695 (see
SBAA113); otherwise, HD2 from the op amps limits
the useful frequency.
INPUT CONFIGURATION
The analog input for the ADS5433 (see Figure 27)
consists of an analog differential buffer followed by a
bipolar track-and-hold. The analog buffer isolates the
source driving the input of the ADC from any internal
switching. The input common mode is set internally
through a 500 Ω resistor connected from 2.4 V to
each of the inputs. This results in a differential input
impedance of 1 kΩ.
R0
Z0
W
50
W
50
AIN
1:1
R
50
AC Signal
Source
ADS5433
W
For
a full-scale differential input, each of the
AIN
ADT1−1WT
differential lines of the input signal (pins 11 and 12)
swings symmetrically between 2.4 +0.55 V and 2.4
–0.55 V. This means that each input is driven with a
signal of up to 2.4 ±0.55 V, so that each input has a
S0176-02
Figure 33. Converting a Single-Ended Input to
a Differential Signal Using RF Transformers
5 V
−5 V
R
100 Ω
S
0.1 µF
+
V
IN
R
1:1
IN
AIN
OPA695
R
100 Ω
T
−
ADS5433
AIN
C
IN
R
IN
1000 µF
R
1
400 Ω
A
V
= 8V/V
R
2
(18 dB)
57.5 Ω
S0177-02
Figure 34. Using the OPA695 With the ADS5433
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R
G
R
F
CM
5 V
−
THS4304
+
1:1
V
IN
AIN
ADS5433
VREF
CM
49.9 Ω
5 V
From
50 Ω
AIN
Source
+
THS4304
−
CM
R
G
R
F
CM
S0192-01
Figure 35. Using the THS4304 With the ADS5433
Besides these, Texas Instruments offers a wide
selection of single-ended operational amplifiers
(including the THS3201, THS3202, and OPA847)
that can be selected depending on the application.
An RF gain block amplifier, such as Texas
Instrument's THS9001, can also be used with an RF
transformer for high input frequency applications. For
applications requiring dc-coupling with the signal
source, instead of using a topology with three single
Input termination is accomplished via the 69.8 Ω
resistor and 0.22 mF capacitor to ground in
conjunction with the input impedance of the amplifier
circuit. A 0.22 µF capacitor and 49.9 Ω resistor is
inserted to ground across the 69.8 W resistor and
0.22 µF capacitor on the alternate input to balance
the circuit.
Gain is
a function of the source impedance,
ended amplifiers,
a
differential input/differential
termination, and 348 Ω feedback resistor. See the
THS4509 data sheet for further component values to
set proper 50 Ω termination for other common gains.
output amplifier like the THS4509 (see Figure 36)
can be used, which minimizes board space and
reduce number of components.
Since
common-mode voltage is +2.4 V, the THS4509 is
operated from a single power supply input with VS+
the
ADS5433
recommended
input
Figure 38 shows their combined SNR and SFDR
performance versus frequency with –1 dBFS input
signal level and sampling at 80 MSPS.
=
+5 V and VS– = 0 V (ground). This maintains
maximum headroom on the internal transistors of the
THS4509.
On this configuration, the THS4509 amplifier circuit
provides 10 dB of gain, converts the single-ended
input to differential, and sets the proper input
common-mode voltage to the ADS5433.
V
IN
From
50 Ω
Source
100 Ω
348 Ω
+5V
14-Bit
69.8 Ω
The 225 Ω resistors and 2.7 pF capacitor between
the THS4509 outputs and ADS5433 inputs (along
with the input capacitance of the ADC) limit the
bandwidth of the signal to about 100 MHz (–3 dB).
80 MSPS
225 Ω
225 Ω
0.22 µF
100 Ω
AIN
ADS5433
2.7 pF
THS
4509
CM
AIN
VREF
49.9 Ω
69.8 Ω
49.9 Ω
For this test, an Agilent signal generator is used for
the signal source. The generator is an ac-coupled 50
Ω source. A band-pass filter is inserted in series with
the input to reduce harmonics and noise from the
signal source.
0.22 µF
0.22 µF
0.1 µF
0.1 µF
348 Ω
S0193-01
Figure 36. Using the THS4509 With the ADS5433
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with any other ADCs) at the system level. The first
advantage is that it allows for common-mode noise
rejection at the PCB level. A further analysis (see
Clocking High Speed Data Converters, SLYT075)
reveals one more advantage. The following formula
describes the different contributions to clock jitter:
95
90
85
80
75
70
SFDR (dBc)
(Jittertotal)2
=
(EXT_jitter)2+ (ADC_jitter)2=
(EXT_jitter)2 + (ADC_int)2 + (K/clock_slope)2
SNR (dBFS)
The first term would represent the external jitter,
coming from the clock source, plus noise added by
the system on the clock distribution, up to the ADC.
The second term is the ADC contribution, which can
be divided in two portions. The first does not depend
directly on any external factor. That is the best we
can get out of our ADC. The second contribution is a
term inversely proportional to the clock slope. The
faster the slope, the smaller this term will be. As an
example, we could compute the ADC jitter
contribution from a sinusoidal input clock of 3 VPP
amplitude and Fs = 80 MSPS:
10
20
30
40
50
60
70
f
IN
− Input Frequency − MHz
G024
Figure 37. Performance vs Input Frequency for
the THS4509 + ADS5433 Configuration
CLK
Square Wave or
Sine Wave
0.01 µF
0.01 µF
ADC_jitter = sqrt ((150fs)2+ (5 × 10-5/(1.5 × 2 ×
ADS5433
CLK
PI × 80 × 106))2) = 164fs
The use of differential clock allows for the use of
bigger clock amplitudes without exceeding the
absolute maximum ratings. This, on the case of
sinusoidal clock, results on higher slew rates which
minimizes the impact of the jitter factor inversely
proportional to the clock slope.
S0168-03
Figure 38. Single-Ended Clock
Figure 39 shows this approach. The back-to-back
Schottky can be added to limit the clock amplitude in
cases where this would exceed the absolute
maximum ratings, even when using a differential
clock. Figure 12 and Figure 13 show the
performance versus input clock amplitude for a
sinusoidal clock.
CLOCK INPUTS
The ADS5433 clock input can be driven with either a
differential clock signal or a single-ended clock input,
with little or no difference in performance between
both configurations. In low input frequency
applications, where jitter may not be a big concern,
the use of single ended clock (see Figure 38) could
save some cost and board space without any
trade-off in performance. When driven on this
configuration, it is best to connect CLKM (pin 11) to
ground with a 0.01 µF capacitor, while CLKP is
ac-coupled with a 0.01 µF capacitor to the clock
source, as shown in Figure 35.
100 nF
MC100EP16DT
Q
100 nF
100 nF
CLK
D
D
V
Q
ADS5433
CLK
BB
100 nF
0.1 µF
499 W
1:4
Clock
499 W
CLK
Source
50 Ω
50 Ω
ADS5433
100 nF
MA3X71600LCT−ND
113 Ω
CLK
S0195-01
S0194-01
Figure 40. Differential Clock Using PECL Logic
Figure 39. Differential Clock
Another possibility is the use of a logic based clock,
as PECL. In this case, the slew rate of the edges will
most likely be much higher than the one obtained for
Nevertheless, for jitter sensitive applications, the use
of a differential clock will have some advantages (as
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the same clock amplitude based on a sinusoidal
clock. This solution would minimize the effect of the
slope dependent ADC jitter. Nevertheless, observe
that for the ADS5433, this term is small and has
been optimized. Using logic gates to square a
sinusoidal clock may not produce the best results as
logic gates may not have been optimized to act as
comparators, adding too much jitter while squaring
the inputs.
POWER SUPPLIES
The use of low noise power supplies with adequate
decoupling is recommended, being the linear
supplies the first choice vs switched ones, which
tend to generate more noise components that can be
coupled to the ADS5433.
The ADS5433 uses two power supplies. For the
analog portion of the design, a 5 V AVDD is used,
while for the digital outputs supply (DRVDD), we
recommend the use of 3.3 V. All the ground pins are
marked as GND, although AGND pins and DRGND
pins are not tied together inside the package.
Customers willing to experiment with different
grounding schemes should know that AGND pins are
4, 7, 10, 13, 15, 17, 19, 21, 23, 25, 27, and 29, while
DRGND pins are 2, 34, and 42. Nevertheless, we
recommend that both grounds are tied together
externally, using a common ground plane. That is the
case on the production test boards and modules
provided to customer for evaluation. In order to
obtain the best performance, the user should layout
the board to assure that the digital return currents do
not flow under the analog portion of the board. This
can be achieved without the need to split the board
and just with careful component placing and
increasing the number of vias and ground planes.
The common-mode voltage of the clock inputs is set
internally to 2.4 V using internal 1 kΩ resistors. It is
recommended using an ac coupling, but if for any
reason, this scheme is not possible, due to, for
instance, asynchronous clocking, the ADS5433
presents a good tolerance to clock common-mode
variation (see Figure 14).
Additionally, the internal ADC core uses both edges
of the clock for the conversion process. This means
that, ideally, a 50% duty cycle should be provided.
Figure 11 shows the performance variation of the
ADC versus clock duty cycle.
DIGITAL OUTPUTS
The ADC provides 14 data outputs (D13 to D0, with
D13 being the MSB and D0 the LSB), a data-ready
signal (DRY, pin 52), and an out-of-range indicator
(OVR, pin 32) that equals 1 when the output reaches
the full-scale limits.
Finally, notice that the metallic heat sink under the
package is also connected to analog ground.
The output format is two's complement. When the
input voltage is at negative full scale (around –1.1 V
differential), the output will be, from MSB to LSB, 10
0000 0000 0000. Then, as the input voltage is
increased, the output switches to 10 0000 0000
0001, 10 0000 0000 0010 and so on until 11 1111
1111 1111 right before mid-scale (when both inputs
are tied together if we neglect offset errors). Further
increase on input voltages, outputs the word 00 0000
0000 0000, to be followed by 00 0000 0000 0001, 00
0000 0000 0010 and so on until reaching 01 1111
1111 1111 at full-scale input (1.1 V differential).
LAYOUT INFORMATION
The evaluation board represents a good guideline of
how to layout the board to obtain the maximum
performance out of the ADS5433. General design
rules as the use of multilayer boards, single ground
plane for both, analog and digital ADC ground
connections and local decoupling ceramic chip
capacitors should be applied. The input traces
should be isolated from any external source of
interference or noise, including the digital outputs as
well as the clock traces. The clock should also be
isolated from other signals, especially on applications
where low jitter is required, as high IF sampling.
Although the output circuitry of the ADS5433 has
been designed to minimize the noise produced by
the transients of the data switching, care must be
taken when designing the circuitry reading the
ADS5433 outputs. Output load capacitance should
be minimized by minimizing the load on the output
traces, reducing their length and the number of gates
connected to them, and by the use of a series
resistor with each pin. Typical numbers on the data
sheet tables and graphs are obtained with 100 Ω
series resistor on each digital output pin, followed by
a 74AVC16244 digital buffer as the one used in the
evaluation board.
Besides performance oriented rules, special care has
to be taken when considering the heat dissipation
out of the device. The thermal heat sink (octagonal,
with 2,5 mm on each side) should be soldered to the
board, and provision for more than 16 ground vias
should be made. The thermal package information
describes the TJA values obtained on the different
configurations.
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相关型号：
ADS5433IPJYG3
1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP52, GREEN, PLASTIC, HTQFP-52
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