ADS5474 [TI]

14-Bit, 400-MSPS Analog-to-Digital Converter; 14位, 400 MSPS模拟数字转换器
ADS5474
型号: ADS5474
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

14-Bit, 400-MSPS Analog-to-Digital Converter
14位, 400 MSPS模拟数字转换器

转换器
文件: 总38页 (文件大小:1620K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
ADS5474  
www.ti.com  
SLAS525JULY 2007  
14-Bit, 400-MSPS Analog-to-Digital Converter  
FEATURES  
On-Chip Analog Buffer, Track-and-Hold, and  
Reference Circuit  
400-MSPS Sample Rate  
TQFP-80 PowerPAD™ Package  
(14 mm × 14 mm footprint)  
14-Bit Resolution, 11.2-Bits ENOB  
1.4-GHz Input Bandwidth  
Industrial Temperature Range:  
–40°C to +85°C  
SFDR = 80 dBc at 230 MHz and 400 MSPS  
SNR = 69.8 dBFS at 230 MHz and 400 MSPS  
2.2 VPP Differential Input Voltage  
LVDS-Compatible Outputs  
Pin-Similar/Compatible with 12-, 13-, and  
14-Bit Family:  
ADS5463 and ADS5440/ADS5444  
Total Power Dissipation: 2.5 W  
Power Down Mode: 50mW  
APPLICATIONS  
Test and Measurement Instrumentation  
Software-Defined Radio  
Data Acquisition  
Power Amplifier Linearization  
Communication Instrumentation  
Radar  
Offset Binary Output Format  
Output Data Transitions on the Rising and  
Falling Edges of a Half-Rate Output Clock  
DESCRIPTION  
The ADS5474 is a 14-bit, 400-MSPS analog-to-digital converter (ADC) that operates from both a 5-V supply and  
3.3-V supply while providing LVDS-compatible digital outputs. This ADC is one of a family of 12-, 13-, and 14-bit  
ADCs that operate from 210 MSPS to 500 MSPS. The ADS5474 input buffer isolates the internal switching of  
the onboard track and hold (T&H) from disturbing the signal source while providing a high-impedance input. An  
internal reference generator is also provided to simplify the system design.  
Designed with a 1.4-GHz input bandwidth for the conversion of wide-bandwidth signals that exceed 400 MHz of  
input frequency at 400 MSPS, the ADS5474 has outstanding low noise performance and spurious-free dynamic  
range over a large input frequency range.  
The ADS5474 is available in an TQFP-80 PowerPAD package. The device is built on Texas Instruments  
complementary bipolar process (BiCom3) and is specified over the full industrial temperature range (–40°C to  
+85°C).  
VIN  
VIN  
+
+
A1  
TH1  
TH2  
A2  
TH3  
A3  
ADC3  
S
S
ADC1  
DAC1  
ADC2  
DAC2  
VREF  
Reference  
5
5
6
Digital Error Correction  
CLK  
CLK  
Timing  
OVR  
OVR  
DRY  
DRY  
D[13:0]  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PowerPAD is a trademark of Texas Instruments.  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
ADS5474  
www.ti.com  
SLAS525JULY 2007  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be  
more susceptible to damage because very small parametric changes could cause the device not to meet its published  
specifications.  
PACKAGE/ORDERING INFORMATION(1)  
SPECIFIED  
PACKAGE  
DESIGNATOR  
TEMPERATURE  
RANGE  
PACKAGE  
MARKING  
ORDERING  
NUMBER  
TRANSPORT  
MEDIA, QUANTITY  
PRODUCT  
PACKAGE-LEAD  
HTQFP-80(2)  
PowerPAD  
ADS5474IPFP  
Tray, 96  
ADS5474  
PFP  
–40°C to +85°C  
ADS5474I  
ADS5474IPFPR  
Tape and Reel, 1000  
(1) For the most current product and ordering information see the Package Option Addendum located at the end of this document, or see  
the TI web site at www.ti.com.  
(2) Thermal pad size: 9.5 mm × 9.5 mm (minimum), 10 mm × 10 mm (maximum).  
ABSOLUTE MAXIMUM RATINGS(1)  
Over operating free-air temperature range, unless otherwise noted.  
ADS5474  
UNIT  
V
AVDD5 to GND  
AVDD3 to GND  
DVDD3 to GND  
6
Supply voltage  
5
V
5
–0.3 to (AVDD5 + 0.3)  
–0.3 to (AVDD5 + 0.3)  
±2.5  
V
Analog input to GND  
Clock input to GND  
CLK to CLK  
V
V
V
Digital data output to GND  
–0.3 to (DVDD3 + 0.3)  
–40 to +85  
V
Operating temperature range  
Maximum junction temperature  
Storage temperature range  
ESD, human-body model (HBM)  
°C  
°C  
°C  
kV  
+150  
–65 to +150  
2
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may  
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond  
those specified is not implied. Kirkendall voidings and current density information for calculation of expected lifetime are available upon  
request.  
THERMAL CHARACTERISTICS(1)  
PARAMETER  
TEST CONDITIONS  
TYP  
23.7  
17.8  
16.4  
2.99  
UNIT  
°C/W  
°C/W  
Soldered thermal pad, no airflow  
(2)  
RθJA  
Soldered thermal pad, 150-LFM airflow  
Soldered thermal pad, 250-LFM airflow  
Bottom of package (thermal pad)  
(3)  
RθJP  
(1) Using 36 thermal vias (6 × 6 array). See PowerPAD Package in the Application Information section.  
(2)  
(3)  
R
θJA is the thermal resistance from the junction to ambient.  
RθJP is the thermal resistance from the junction to the thermal pad.  
2
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SLAS525JULY 2007  
RECOMMENDED OPERATING CONDITIONS  
ADS5474  
TYP  
MIN  
MAX  
UNIT  
SUPPLIES  
AVDD5  
AVDD3  
DVDD3  
Analog supply voltage  
Analog supply voltage  
Output driver supply voltage  
4.75  
3.1  
3
5
3.3  
3.3  
5.25  
3.6  
V
V
V
3.6  
ANALOG INPUT  
Differential input range  
Input common mode  
2.2  
3.1  
VPP  
V
VCM  
DIGITAL OUTPUT (DRY, DATA, OVR)  
Maximum differential output load  
CLOCK INPUT (CLK)  
10  
pF  
CLK input sample rate (sine wave)  
20  
0.5  
40  
400 MSPS  
Clock amplitude, differential sine wave (see Figure 42)  
5
60  
VPP  
%
Clock duty cycle (see Figure 46)  
Operating free-air temperature  
50  
TA  
–40  
+85  
°C  
ELECTRICAL CHARACTERISTICS  
Typical values at TA = +25°C: minimum and maximum values over full temperature range TMIN = –40°C to TMAX = +85°C,  
sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,  
and 3-VPP differential clock, unless otherwise noted.  
ADS5474  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Resolution  
ANALOG INPUTS  
Differential input range  
14  
Bits  
2.2  
3.1  
VPP  
V
Analog input common-mode voltage  
Input resistance (dc)  
Self-biased; see VCM specification below  
Each input to VCM  
500  
1.8  
Input capacitance  
Each input to GND  
pF  
Analog input bandwidth (–3dB)  
1.44  
GHz  
Common-mode signal < 50 MHz  
(see Figure 27)  
CMRR  
Common-mode rejection ratio  
100  
dB  
INTERNAL REFERENCE VOLTAGE  
VREF  
VCM  
Reference voltage  
2.4  
V
With internal VREF. Provided as an output  
via the VCM pin for dc-coupled  
applications. If an external VREF is used,  
the VCM pin tracks as illustrated in  
Figure 39  
Analog input common-mode voltage  
reference output  
2.9  
3.1  
3.3  
V
VCM temperature coefficient  
–0.8  
mV/°C  
DYNAMIC ACCURACY  
No missing codes  
Assured  
±0.7  
DNL  
INL  
Differential linearity error  
Integral linearity error  
Offset error  
fIN = 70 MHz  
fIN = 70 MHz  
–0.99  
–3  
1.5  
3
LSB  
LSB  
±1  
–11  
11  
mV  
Offset temperature coefficient  
Gain error  
0.02  
mV/°C  
%FS  
–5  
5
Gain temperature coefficient  
–0.02  
%FS/°C  
3
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SLAS525JULY 2007  
ELECTRICAL CHARACTERISTICS (continued)  
Typical values at TA = +25°C: minimum and maximum values over full temperature range TMIN = –40°C to TMAX = +85°C,  
sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,  
and 3-VPP differential clock, unless otherwise noted.  
ADS5474  
PARAMETER  
POWER SUPPLY  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
IAVDD5  
IAVDD3  
5-V analog supply current  
3.3-V analog supply current  
338  
185  
75  
372  
201  
83  
mA  
mA  
VIN = full-scale, fIN = 70 MHz,  
fS = 400 MSPS  
3.3-V digital supply current  
(includes LVDS)  
IDVDD3  
mA  
Total power dissipation  
Power-up time  
2.5  
50  
2.797  
W
From turn-on of AVDD5  
μs  
From PDWN pin switched from HIGH  
(PDWN active) to LOW (ADC awake)  
(see Figure 28)  
Wake-up time  
5
μs  
Power-down power dissipation  
PDWN pin = logic HIGH  
50  
75  
90  
350  
mW  
dB  
Power-supply rejection ratio,  
AVDD5 supply  
PSRR  
PSRR  
PSRR  
Power-supply rejection ratio,  
AVDD3 supply  
Without 0.1-μF board supply capacitors,  
with < 1-MHz supply noise (see Figure 49)  
dB  
dB  
Power-supply rejection ratio,  
DVDD3 supply  
110  
DYNAMIC AC CHARACTERISTICS  
fIN = 30 MHz  
fIN = 70 MHz  
fIN = 130 MHz  
fIN = 230 MHz  
fIN = 351 MHz  
fIN = 451 MHz  
fIN = 651 MHz  
fIN = 751 MHz  
fIN = 999 MHz  
fIN = 30 MHz  
fIN = 70 MHz  
fIN = 130 MHz  
fIN = 230 MHz  
fIN = 351 MHz  
fIN = 451 MHz  
fIN = 651 MHz  
fIN = 751 MHz  
fIN = 999 MHz  
fIN = 30 MHz  
fIN = 70 MHz  
fIN = 130 MHz  
fIN = 230 MHz  
fIN = 351 MHz  
fIN = 451 MHz  
fIN = 651 MHz  
fIN = 751 MHz  
fIN = 999 MHz  
70.3  
70.2  
70.1  
69.8  
69.1  
68.4  
67.5  
66.6  
64.7  
88  
68.3  
68  
SNR  
SFDR  
HD2  
Signal-to-noise ratio  
dBFS  
74  
71  
86  
80  
80  
Spurious-free dynamic range  
76  
dBc  
71  
60  
55  
46  
89  
87  
90  
84  
Second-harmonic  
76  
dBc  
71  
74  
70  
55  
4
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SLAS525JULY 2007  
ELECTRICAL CHARACTERISTICS (continued)  
Typical values at TA = +25°C: minimum and maximum values over full temperature range TMIN = –40°C to TMAX = +85°C,  
sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,  
and 3-VPP differential clock, unless otherwise noted.  
ADS5474  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
DYNAMIC AC CHARACTERISTICS (continued)  
fIN = 30 MHz  
93  
86  
80  
80  
85  
71  
60  
55  
46  
95  
93  
85  
85  
87  
87  
90  
87  
80  
86  
83  
78  
77  
75  
68  
60  
55  
45  
fIN = 70 MHz  
fIN = 130 MHz  
fIN = 230 MHz  
fIN = 351 MHz  
fIN = 451 MHz  
fIN = 651 MHz  
fIN = 751 MHz  
fIN = 999 MHz  
fIN = 30 MHz  
fIN = 70 MHz  
fIN = 130 MHz  
fIN = 230 MHz  
fIN = 351 MHz  
fIN = 451 MHz  
fIN = 651 MHz  
fIN = 751 MHz  
fIN = 999 MHz  
fIN = 30 MHz  
fIN = 70 MHz  
fIN = 130 MHz  
fIN = 230 MHz  
fIN = 351 MHz  
fIN = 451 MHz  
fIN = 651 MHz  
fIN = 751 MHz  
fIN = 999 MHz  
HD3  
Third-harmonic  
dBc  
Worst harmonic/spur  
(other than HD2 and HD3)  
dBc  
THD  
Total harmonic distortion  
dBc  
5
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SLAS525JULY 2007  
ELECTRICAL CHARACTERISTICS (continued)  
Typical values at TA = +25°C: minimum and maximum values over full temperature range TMIN = –40°C to TMAX = +85°C,  
sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,  
and 3-VPP differential clock, unless otherwise noted.  
ADS5474  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
DYNAMIC AC CHARACTERISTICS (continued)  
fIN = 30 MHz  
69.2  
68.9  
68.5  
68.2  
67.3  
64.8  
58.5  
54  
fIN = 70 MHz  
fIN = 130 MHz  
fIN = 230 MHz  
fIN = 351 MHz  
fIN = 451 MHz  
fIN = 651 MHz  
fIN = 751 MHz  
fIN = 999 MHz  
67  
65.5  
SINAD  
Signal-to-noise and distortion  
dBc  
45.4  
fIN1 = 69 MHz, fIN2 = 70 MHz,  
each tone at –7 dBFS  
93  
95  
85  
83  
fIN1 = 69 MHz, fIN2 = 70 MHz,  
each tone at –16 dBFS  
Two-tone SFDR  
dBFS  
fIN1 = 297.5 MHz, fIN2 = 302.5 MHz,  
each tone at –7 dBFS  
fIN1 = 297.5 MHz, fIN2 = 302.5 MHz,  
each tone at –16 dBFS  
fIN = 70 MHz  
10.8  
10.6  
11.2  
10.9  
1.8  
ENOB  
Effective number of bits  
RMS idle-channel noise  
Bits  
fIN = 230 MHz  
Inputs tied to common-mode  
LSB  
LVDS DIGITAL OUTPUTS  
VOD  
VOC  
Differential output voltage (±)  
Common-mode output voltage  
247  
350  
454  
mV  
V
1.125  
1.375  
6
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SLAS525JULY 2007  
TIMING INFORMATION  
Sample  
N–1  
N+4  
N+2  
ta  
N
N+1  
N+3  
N+5  
tCLKH  
tCLKL  
CLK  
CLK  
Latency = 3.5 Clock Cycles  
tDRY  
DRY  
DRY(1)  
tDATA  
D[13:0], OVR  
N–1  
N
N+1  
D[13:0], OVR  
(1) Polarity of DRY is undetermined. For further information, see the Digital Outputs section.  
Figure 1. Timing Diagram  
TIMING CHARACTERISTICS(1)  
Typical values at TA = +25°C: minimum and maximum values over full temperature range TMIN = –40°C to TMAX = +85°C,  
sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential  
clock, unless otherwise noted.  
PARAMETER  
Aperture delay  
TEST CONDITIONS  
MIN  
TYP  
200  
103  
3.5  
MAX  
UNIT  
ps  
ta  
Aperture jitter, rms  
Latency  
Internal jitter of the ADC  
fs  
cycles  
ns  
tCLK  
Clock period  
2.5  
1
50  
tCLKH  
tCLKL  
tDRY  
Clock pulse duration, high  
Clock pulse duration, low  
CLK to DRY delay(2)  
ns  
1
ns  
Zero crossing, 10-pF parasitic loading to GND on each  
output pin  
1000  
1400  
1400  
0
1800  
2000  
500  
ps  
tDATA  
tSKEW  
CLK to DATA/OVR delay(2)  
DATA to DRY skew  
Zero crossing, 10-pF parasitic loading to GND on each  
output pin  
800  
ps  
ps  
tDATA – tDRY, 10-pF parasitic loading to GND on each output  
pin  
–500  
tRISE  
tFALL  
DRY/DATA/OVR rise time  
DRY/DATA/OVR fall time  
10-pF parasitic loading to GND on each output pin  
10-pF parasitic loading to GND on each output pin  
500  
500  
ps  
ps  
(1) Timing parameters are assured by design or characterization, but not production tested.  
(2) DRY, DATA, and OVR are updated on the falling edge of CLK. The latency must be added to tDATA to determine the overall propagation  
delay.  
7
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PIN CONFIGURATION  
PFP PACKAGE  
(TOP VIEW)  
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61  
DVDD3  
1
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
D5  
GND  
AVDD5  
NC  
2
D5  
3
D4  
4
D4  
5
D3  
NC  
VREF  
GND  
AVDD5  
GND  
CLK  
6
D3  
7
D2  
8
D2  
9
GND  
DVDD3  
D1  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
ADS5474  
CLK  
GND  
AVDD5  
AVDD5  
GND  
AIN  
D1  
D0  
D0  
NC  
NC  
NC  
NC  
OVR  
OVR  
AIN  
GND  
AVDD5  
GND  
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40  
8
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PIN CONFIGURATION (continued)  
Table 1. TERMINAL FUNCTIONS  
TERMINAL  
NAME  
NO.  
16  
DESCRIPTION  
Differential input signal (positive)  
AIN  
AIN  
17  
Differential input signal (negative)  
3, 8, 13, 14, 19, 21,  
23, 25, 27, 31  
AVDD5  
Analog power supply (5 V)  
Analog power supply (3.3 V) (Suggestion for 250 MSPS: leave option to connect to 5 V for  
ADS5440/ADS5444 13-bit compatibility)  
AVDD3  
DVDD3  
35, 37, 39  
1, 51, 66  
Digital and output driver power supply (3.3 V)  
2, 7, 9, 12, 15, 18,  
20, 22, 24, 26, 28,  
30, 32, 34, 36, 38,  
40, 52, 65  
GND  
Ground  
CLK  
10  
11  
Differential input clock (positive). Conversion is initiated on rising edge.  
Differential input clock (negative)  
CLK  
D0, D0  
48, 47  
LVDS digital output pair, least significant bit (LSB)  
D1–D12,  
D1–D10  
49, 50, 53–64,  
67–76  
LVDS digital output pairs  
D13, D13  
78, 77  
80, 79  
LVDS digital output pair, most significant bit (MSB)  
Data ready LVDS output pair  
DRY, DRY  
No connect (pins 4 and 5 should be left floating; pins 43 to 46 are possible future bit additions for this  
pinout and therefore can be connected to a digital bus or left floating)  
NC  
4, 5, 43–46  
42, 41  
Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-scale  
range.  
OVR, OVR  
Common-mode voltage output (3.1 V nominal). Commonly used in DC-coupled applications to set  
the input signal to the correct common-mode voltage.  
VCM  
29  
(This pin is not used on the ADS5440, ADS5444, and ADS5463)  
Power-down (active high). Device is in sleep mode when PDWN pin is logic HIGH. ADC converter is  
awake when PDWN is logic LOW (grounded).  
(This pin is not used on the ADS5440, ADS5444, and ADS5463)  
PDWN  
VREF  
33  
6
Reference voltage input/output (2.4 V nominal)  
9
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TYPICAL CHARACTERISTICS  
At TA = +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =  
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.  
SPECTRAL PERFORMANCE  
FFT FOR 30 MHz INPUT SIGNAL  
SPECTRAL PERFORMANCE  
FFT FOR 70 MHz INPUT SIGNAL  
0
0
SFDR = 88.4 dBc  
SFDR = 86.6 dBc  
SNR = 70.3 dBFS  
SINAD = 70.2 dBFS  
THD = 86 dBc  
SNR = 70.1 dBFS  
SINAD = 69.9 dBFS  
THD = 82.9 dBc  
-20  
-20  
-40  
-40  
-60  
-60  
-80  
-80  
-100  
-120  
-100  
-120  
0
20  
40  
60  
80 100 120 140 160 180 200  
0
20  
40  
60  
80 100 120 140 160 180 200  
Frequency - MHz  
Frequency - MHz  
Figure 2.  
Figure 3.  
SPECTRAL PERFORMANCE  
FFT FOR 130 MHz INPUT SIGNAL  
SPECTRAL PERFORMANCE  
FFT FOR 230 MHz INPUT SIGNAL  
0
0
SFDR = 78.5 dBc  
SNR = 70.1 dBFS  
SINAD = 69.5 dBFS  
THD = 77.4 dBc  
SFDR = 79.7 dBc  
SNR = 69.8 dBFS  
SINAD = 69.2 dBFS  
THD = 76.9 dBc  
-20  
-40  
-20  
-40  
-60  
-60  
-80  
-80  
-100  
-120  
-100  
-120  
0
20  
40  
60  
80 100 120 140 160 180 200  
0
20  
40  
60  
80 100 120 140 160 180 200  
Frequency - MHz  
Frequency - MHz  
Figure 4.  
Figure 5.  
10  
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TYPICAL CHARACTERISTICS (continued)  
At TA = +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =  
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.  
SPECTRAL PERFORMANCE  
FFT FOR 351 MHz INPUT SIGNAL  
SPECTRAL PERFORMANCE  
FFT FOR 451 MHz INPUT SIGNAL  
0
0
SFDR = 75.5 dBc  
SFDR = 71.4 dBc  
SNR = 69.2 dBFS  
SINAD = 68.3 dBFS  
THD = 74.7 dBc  
SNR = 68.4 dBFS  
SINAD = 65.8 dBFS  
THD = 68.3 dBc  
-20  
-20  
-40  
-40  
-60  
-60  
-80  
-80  
-100  
-120  
-100  
-120  
0
20  
40  
60  
80 100 120 140 160 180 200  
0
20  
40  
60  
80 100 120 140 160 180 200  
Frequency - MHz  
Frequency - MHz  
Figure 6.  
Figure 7.  
SPECTRAL PERFORMANCE  
FFT FOR 751 MHz INPUT SIGNAL  
SPECTRAL PERFORMANCE  
FFT FOR 999 MHz INPUT SIGNAL  
0
0
SFDR = 54.5 dBc  
SFDR = 46 dBc  
SNR = 66.6 dBFS  
SINAD = 55.1 dBFS  
THD = 54.4 dBc  
SNR = 64.7 dBFS  
SINAD = 46.4 dBFS  
THD = 45.5 dBc  
-20  
-20  
-40  
-40  
-60  
-60  
-80  
-80  
-100  
-120  
-100  
-120  
0
20  
40  
60  
80 100 120 140 160 180 200  
0
20  
40  
60  
80 100 120 140 160 180 200  
Frequency - MHz  
Frequency - MHz  
Figure 8.  
Figure 9.  
11  
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TYPICAL CHARACTERISTICS (continued)  
At TA = +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =  
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.  
TWO-TONE INTERMODULATION DISTORTION  
(FFT for 69 MHz and 70 MHz at –7 dBFS)  
TWO-TONE INTERMODULATION DISTORTION  
(FFT for 297.5 MHz and 302.5 MHz at –7 dBFS)  
0
0
fIN1 = 69 MHz, -7 dBFS  
fIN2 = 70 MHz, -7 dBFS  
IMD3 = 97.3 dBFS  
fIN1 = 297.5 MHz, -7 dBFS  
fIN2 = 302.5 MHz, -7 dBFS  
IMD3 = 85.1 dBFS  
SFDR = 85 dBFS  
-20  
-20  
SFDR = 93.4 dBFS  
-40  
-40  
-60  
-60  
-80  
-80  
-100  
-120  
-100  
-120  
0
20  
40  
60  
80 100 120 140 160 180 200  
0
20  
40  
60  
80 100 120 140 160 180 200  
Frequency - MHz  
Frequency - MHz  
Figure 10.  
Figure 11.  
TWO-TONE INTERMODULATION DISTORTION  
(FFT for 69 MHz and 70 MHz at –16 dBFS)  
TWO-TONE INTERMODULATION DISTORTION  
(FFT for 297.5 MHz and 302.5 MHz at –16 dBFS)  
0
0
fIN1 = 297.5 MHz, -16 dBFS  
fIN2 = 302.5 MHz, -16 dBFS  
fIN1 = 69 MHz, -16 dBFS  
fIN2 = 70 MHz, -16 dBFS  
IMD3 = 94.4 dBFS  
SFDR = 83.1 dFBS  
IMD3 = 98 dBFS  
-20  
-40  
-20  
-40  
SFDR = 95.7 dFBS  
-60  
-60  
-80  
-80  
-100  
-120  
-100  
-120  
0
20  
40  
60  
80 100 120 140 160 180 200  
0
20  
40  
60  
80 100 120 140 160 180 200  
Frequency - MHz  
Frequency - MHz  
Figure 12.  
Figure 13.  
12  
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TYPICAL CHARACTERISTICS (continued)  
At TA = +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =  
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.  
NORMALIZED GAIN RESPONSE  
vs  
INPUT FREQUENCY  
DIFFERENTIAL NONLINEARITY  
3
0
0.5  
0.4  
fS = 400 MSPS  
fIN = 70 MHz  
0.3  
-3  
0.2  
-6  
0.1  
-9  
0
-0.1  
-0.2  
-0.3  
-0.4  
-0.5  
-12  
-15  
-18  
-21  
fS = 400 MSPS  
AIN = ±0.38 VPP  
10 M  
100 M  
1 G  
5 G  
0
2048 4096 6144 8192 10240 12288 14336 16384  
Code  
Frequency - Hz  
Figure 14.  
Figure 15.  
INTEGRAL NONLINEARITY  
NOISE HISTOGRAM WITH INPUTS SHORTED  
25  
20  
15  
10  
5
2.0  
1.5  
fS = 400 MSPS  
fIN = 70 MHz  
fS = 400 MSPS  
fIN = VCM  
1.0  
0.5  
0
-0.5  
-1.0  
-1.5  
-2.0  
0
0
2048 4096 6144 8192 10240 12288 14336 16384  
Code  
Output Code  
Figure 16.  
Figure 17.  
13  
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TYPICAL CHARACTERISTICS (continued)  
At TA = +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =  
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.  
AC PERFORMANCE  
AC PERFORMANCE  
vs  
vs  
INPUT AMPLITUDE (70 MHz Input Signal)  
INPUT AMPLITUDE (230 MHz Input Signal)  
120  
100  
80  
120  
100  
80  
SFDR (dBFS)  
SNR (dBFS)  
SFDR (dBFS)  
SNR (dBFS)  
60  
60  
40  
40  
SFDR (dBc)  
SFDR (dBc)  
20  
20  
0
0
SNR (dBc)  
SNR (dBc)  
-20  
-40  
-20  
-40  
fS = 400 MSPS  
fIN = 70 MHz  
fS = 400 MSPS  
fIN = 230 MHz  
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10  
0
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10  
0
Input Amplitude - dBFS  
Input Amplitude - dBFS  
Figure 18.  
Figure 19.  
TWO-TONE PERFORMANCE  
vs  
INPUT AMPLITUDE (f1 = 297.5 MHz and f2 = 302.5 MHz)  
SFDR  
vs  
AVDD5 OVER TEMPERATURE  
90  
88  
86  
84  
82  
80  
78  
76  
74  
72  
70  
100  
fS = 400 MSPS  
fIN = 230 MHz  
2f2 - f1 (dBc)  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
2f1 - f2 (dBc)  
+40°C  
+65°C  
+25°C  
0°C  
+85°C  
-40°C  
+100°C  
Worst Spur (dBc)  
4.7  
4.8  
4.9  
5.0  
5.1  
5.2  
5.3  
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10  
0
AVDD5 - Supply Voltage - V  
AIN - dBFS  
Figure 20.  
Figure 21.  
14  
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TYPICAL CHARACTERISTICS (continued)  
At TA = +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =  
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.  
SNR  
SFDR  
vs  
vs  
AVDD5 OVER TEMPERATURE  
AVDD3 OVER TEMPERATURE  
71.0  
70.5  
70.0  
69.5  
69.0  
68.5  
68.0  
90  
88  
86  
84  
82  
80  
78  
76  
74  
72  
70  
fS = 400 MSPS  
fS = 400 MSPS  
fIN = 230 MHz  
fIN = 230 MHz  
+25°C  
+65°C  
+40°C  
+40°C  
+25°C  
+65°C  
-40°C  
+85°C  
0°C  
+85°C  
+100°C  
0°C  
+100°C  
-40°C  
4.7  
4.8  
4.9  
5.0  
5.1  
5.2  
5.3  
3.0  
3.1  
3.2  
3.3  
3.4  
3.5  
3.6  
AVDD5 - Supply Voltage - V  
AVDD3 - Supply Voltage - V  
Figure 22.  
Figure 23.  
SNR  
vs  
SFDR  
vs  
AVDD3 OVER TEMPERATURE  
DVDD3 OVER TEMPERATURE  
71.0  
70.5  
70.0  
69.5  
69.0  
68.5  
68.0  
90  
88  
86  
84  
82  
80  
78  
76  
74  
72  
70  
fS = 400 MSPS  
fIN = 230 MHz  
fS = 400 MSPS  
fIN = 230 MHz  
+25°C  
+65°C  
+40°C  
+25°C  
+65°C  
+40°C  
+85°C  
0°C  
-40°C  
+100°C  
+85°C  
0°C  
+100°C  
-40°C  
3.0  
3.1  
3.2  
3.3  
3.4  
3.5  
3.6  
3.0  
3.1  
3.2  
3.3  
3.4  
3.5  
3.6  
AVDD3 - Supply Voltage - V  
DVDD3 - Supply Voltage - V  
Figure 24.  
Figure 25.  
15  
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TYPICAL CHARACTERISTICS (continued)  
At TA = +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =  
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.  
SNR  
CMRR  
vs  
vs  
DVDD3 OVER TEMPERATURE  
COMMON-MODE INPUT FREQUENCY  
71.0  
70.5  
70.0  
69.5  
69.0  
68.5  
68.0  
0
-10  
fS = 400 MSPS  
fIN = 230 MHz  
-20  
+25°C  
-30  
+40°C  
0°C  
+65°C  
-40  
-50  
-60  
-70  
+85°C  
+100°C  
-40°C  
-80  
-90  
400 MSPS  
-100  
-110  
-120  
-130  
300 MSPS  
3.0  
3.1  
3.2  
3.3  
3.4  
3.5  
3.6  
100 k  
1 M  
10 M  
100 M  
1 G  
10 G  
DVDD3 - Supply Voltage - V  
Frequency - Hz  
Figure 26.  
Figure 27.  
ADC WAKEUP TIME  
75  
Wake from PDWN  
70  
65  
60  
55  
50  
45  
40  
35  
30  
25  
20  
15  
10  
5
Wake from 5 V Supply  
0
0
10  
20  
30  
40  
50  
60  
70  
80  
90 100  
Time - ms  
Figure 28.  
16  
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TYPICAL CHARACTERISTICS (continued)  
At TA = +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude =  
–1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.  
SNR vs INPUT FREQUENCY AND SAMPLING FREQUENCY  
400  
68  
70  
69  
350  
300  
250  
200  
150  
100  
40  
70  
68  
69  
67  
70  
69  
68  
69  
70  
66  
67  
68  
300  
10  
100  
200  
400  
500  
600  
fIN - Input Frequency - MHz  
54  
56  
58  
60  
62 64  
66  
68  
70  
SNR - dBFS  
Figure 29.  
SFDR vs INPUT FREQUENCY AND SAMPLING FREQUENCY  
400  
350  
300  
250  
200  
150  
100  
40  
80  
77  
65  
73  
85  
80  
70  
77  
80  
85  
65  
73  
77  
80  
85  
70  
77  
85  
85  
73  
65  
70  
60  
600  
80  
300  
77  
85  
10  
100  
200  
400  
500  
fIN - Input Frequency - MHz  
50  
55  
60  
65  
70  
75  
80  
85  
90  
SFDR - dBc  
Figure 30.  
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APPLICATIONS INFORMATION  
Theory of Operation  
The ADS5474 is a 14-bit, 400-MSPS, monolithic pipeline ADC. Its bipolar analog core operates from 5-V and  
3.3-V supplies, while the output uses a 3.3-V supply to provide LVDS-compatible outputs. The conversion  
process is initiated by the rising edge of the external input clock. At that instant, the differential input signal is  
captured by the input track-and-hold (T&H), and the input sample is converted sequentially by a series of lower  
resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling  
clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results  
in a data latency of 3.5 clock cycles, after which the output data are available as a 14-bit parallel word, coded in  
offset binary format.  
Input Configuration  
The analog input for the ADS5474 consists of an analog pseudo-differential buffer followed by a bipolar  
transistor T&H. The analog buffer isolates the source driving the input of the ADC from any internal switching  
and presents a high impedance that is easy to drive at high input frequencies, compared to an ADC without a  
buffered input. The input common-mode is set internally through a 500-resistor connected from 3.1 V to each  
of the inputs. This configuration results in a differential input impedance of 1 k.  
AVDD5  
Buffer  
AIN  
1.6 pF  
500 W  
GND  
VCM  
AVDD5  
GND  
1.6 pF  
500 W  
AIN  
Buffer  
GND  
ADS5474  
Figure 31. Analog Input Circuit  
For a full-scale differential input, each of the differential lines of the input signal (pins 16 and 17) swings  
symmetrically between (3.1 V + 0.55 V) and (3.1 V – 0.55 V). This range means that each input has a maximum  
signal swing of 1.1 VPP for a total differential input signal swing of 2.2 VPP. Operation below 2.2 VPP is allowable,  
with the characteristics of performance versus input amplitude demonstrated in Figure 18 and Figure 19. For  
instance, for performance at 1.1 VPP rather than 2.2 VPP, refer to the SNR and SFDR at –6 dBFS (0 dBFS =  
2.2 VPP). The maximum swing is determined by the internal reference voltage generator, eliminating the need for  
any external circuitry for this purpose.  
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Applications Information (continued)  
The ADS5474 performs optimally when the analog inputs are driven differentially. The circuit in Figure 32 shows  
one possible configuration using an RF transformer with termination either on the primary or on the secondary of  
the transformer. In addition, the evaluation module is configured with two back-to-back transformers, also  
demonstrating good performance. If voltage gain is required, a step-up transformer can be used.  
Z0  
R0  
50 W  
50 W  
AIN  
R
ADS5474  
AC Signal  
Source  
200 W  
AIN  
Mini-Circuits  
JTX-4-10T  
Figure 32. Converting a Single-Ended Input to a Differential Signal Using an RF Transformer  
In addition to the transformer configurations, Texas Instruments offers a wide selection of single-ended  
operational amplifiers that can be selected depending on the application. An RF gain-block amplifier, such as  
Texas Instruments' THS9001, can also be used for high-input-frequency applications. For large voltage gains at  
intermediate-frequencies in the 50 MHz to 400 MHz range, the configuration shown in Figure 33 can be used.  
The component values can be tuned for different intermediate frequencies. The example shown in Figure 33 is  
located on the evaluation module and is tuned for an IF of 170 MHz. More information regarding this  
configuration can be found in the ADS5474 EVM User Guide (SLAU194) and the THS9001 50-MHz to 350-MHz  
Cascadeable Amplifier data sheet (SLOS426), both available for download at www.ti.com.  
1000 pF  
1000 pF  
THS9001  
VIN  
AIN  
50 W  
50 W  
18 mH  
39 pF  
ADS5474  
0.1 mF  
THS9001  
VIN  
AIN  
1000 pF  
1000 pF  
Figure 33. Using the THS9001 IF Amplifier With the ADS5474  
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Applications Information (continued)  
For applications requiring dc-coupling with the signal source, a differential input/differential output amplifier such  
as the THS4509 (shown in Figure 34) provides good harmonic performance and low noise over a wide range of  
frequencies.  
VIN  
100 W  
348 W  
From  
50 W  
Source  
+5V  
78.9 W  
49.9 W  
49.9 W  
0.22 mF  
100 W  
AIN  
ADS5474  
THS4509  
18 pF  
VCM  
AIN  
CM  
49.9 W  
78.9 W  
49.9 W  
0.22 mF  
0.22 mF  
0.1 mF  
0.1 mF  
348 W  
Figure 34. Using the THS4509 or THS4520 With the ADS5474  
In this configuration, the THS4509 amplifier circuit provides 10 dB of gain, converts the single-ended input to  
differential, and sets the proper input common-mode voltage to the ADS5474 by utilizing the VCM output pin of  
the ADC. The 50-resistors and 18-pF capacitor between the THS4509 outputs and ADS5474 inputs (along  
with the input capacitance of the ADC) limit the bandwidth of the signal to about 70 MHz (–3 dB). Input  
termination is accomplished via the 78.9-resistor and 0.22-μF capacitor to ground, in conjunction with the  
input impedance of the amplifier circuit. A 0.22-μF capacitor and 49.9-resistor are inserted to ground across  
the 78.9-resistor and 0.22-μF capacitor on the alternate input to balance the circuit. Gain is a function of the  
source impedance, termination, and 348-feedback resistor. See the THS4509 data sheet for further  
component values to set proper 50-termination for other common gains. Because the ADS5474  
recommended input common-mode voltage is 3.1 V, the THS4509 operates from a single power-supply input  
with VS+ = 5 V and VS– = 0 V (ground). This configuration has the potential to slightly exceed the recommended  
output voltage from the THS4509 of 3.6V due to the ADC input common-mode of 3.1V and the +0.55V full-scale  
signal. This will not harm the THS4509 but may result in a degradation in the harmonic performance of the  
THS4509. An amplifier with a wider recommended output voltage range is the THS4520, which is optimized for  
low noise and low distortion in the range of frequencies up to ~20MHz. Applications that are not sensitive to  
harmonic distortion could consider either device at higher frequencies.  
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Applications Information (continued)  
External Voltage Reference  
For systems that require the analog signal gain to be adjusted or calibrated, this can be performed by using an  
external reference. The dependency on the signal amplitude to the value of the external reference voltage is  
characterizaed typically by Figure 35 (VREF = 2.4 V is normalized to 0 dB as this is the internal reference  
voltage). As can be seen in the linear fit, this equates to approximately –0.3 dB of signal adjustment per 100 mV  
of reference adjustment. The range of allowable variation depends on the analog input amplitude that is applied  
to the inputs and the desired spectral performance, as can be seen in the performance versus external  
reference graphs in Figure 36 and Figure 37. As the applied analog signal amplitude is reduced, more variation  
in the reference voltage is allowed in the positive direction (which equates to a reduction in signal amplitude),  
whereas an adjustment in reference voltage below the nominal 2.4 V (which equates to an increase in signal  
amplitude) is not recommended below approximately 2.35 V. The power consumption versus reference voltage  
and operating temperature should also be considered, especially at high ambient temperatures, because the  
lifetime of the device is affected by internal junction temperature, see Figure 50.  
For dc-coupled applications that use the VCM pin of the ADS5474 as the common mode of the signal in the  
analog signal gain path prior to the ADC inputs, the information in Figure 39 is useful to consider versus the  
allowable common-mode range of the device that is receiving the VCM voltage, such as an operational amplifier.  
Because it is pin-compatible, it is important to note that the ADS5463 does not have a VCM pin and primarily  
uses the VREF pin to provide the common-mode voltage in dc-coupled applications. The ADS5463 (VCM = 2.4  
V) and ADS5474 (VCM = 3.1V) do not have the same common-mode voltage. To create a board layout that may  
accomodate both devices in dc-coupled applications, route VCM and VREF both to a common point that can be  
selected via a switch, jumper, or a 0 resistor.  
1.0  
90  
80  
70  
60  
50  
40  
fS = 400 MSPS  
fIN = 70 MHz  
AIN = -5 dBFS  
AIN = -6 dBFS  
0.5  
AIN = < -1 dBFS  
0
Best Fit:  
y = -3.14x + 7.5063  
AIN = -4 dBFS  
-0.5  
-1.0  
-1.5  
-2.0  
-2.5  
-3.0  
AIN = -3 dBFS  
AIN = -2 dBFS  
AIN = -1 dBFS  
fS = 400 MSPS  
fIN = 70 MHz  
2.2  
2.3  
2.4  
2.5  
2.6  
2.7  
2.8  
2.9  
3.0  
3.1  
2.05 2.15 2.25 2.35 2.45 2.55 2.65 2.75  
2.95 3.05 3.15  
2.85  
External VREF Applied - V  
External VREF Applied - V  
Figure 35. Signal Gain Adjustment versus External  
Reference (VREF)  
Figure 36. SFDR versus External VREF and AIN  
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Applications Information (continued)  
75  
3.4  
fS = 400 MSPS  
fIN = 70 MHz  
fS = 400 MSPS  
AIN = -6 dBFS  
fIN = 70 MHz  
3.2  
70  
65  
60  
55  
50  
45  
40  
3.0  
2.8  
AIN = -4 dBFS  
AIN = -3 dBFS  
2.6  
2.4  
2.2  
2.0  
AIN = -2 dBFS  
AIN = -5 dBFS  
AIN = -1 dBFS  
2.05 2.15 2.25 2.35 2.45 2.55 2.65 2.75  
2.95 3.05 3.15  
2.05 2.15 2.25 2.35  
2.45 2.55 2.65 2.75 2.85 2.95 3.05 3.15  
2.85  
External VREF Applied - V  
External VREF Applied - V  
Figure 37. SNR versus External VREF and AIN  
Figure 38. Total Power Consumption versus External  
VREF  
3.8  
fS = 400 MSPS  
fIN = 70 MHz  
3.7  
3.6  
3.5  
3.4  
3.3  
3.2  
3.1  
3.0  
2.9  
2.8  
2.05 2.15 2.25 2.35 2.45 2.55 2.65 2.75  
2.95 3.05 3.15  
2.85  
External VREF Applied - V  
Figure 39. VCM Pin Output versus External VREF  
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Applications Information (continued)  
Clock Inputs  
The ADS5474 clock input can be driven with either a differential clock signal or a single-ended clock input, as  
shown in Figure 40. The characterization of the ADS5474 is typically performed with a 3-VPP differential clock,  
but the ADC performs well with a differential clock amplitude down to ~0.5 VPP, as shown in Figure 42. The  
clock amplitude becomes more of a factor in performance as the analog input frequency increases. In  
low-input-frequency applications, where jitter may not be a big concern, the use of a single-ended clock (as  
shown in Figure 41) could save cost and board space without much performance tradeoff. When clocked with  
this configuration, it is best to connect CLK to ground with a 0.01-μF capacitor, while CLK is ac-coupled with a  
0.01-μF capacitor to the clock source, as shown in Figure 41.  
AVDD5  
CLK  
Parasitic  
1 kW  
~200 fF  
GND  
Clock  
Buffer  
~2.4 V  
AVDD5  
GND  
Parasitic  
~200 fF  
1 kW  
CLK  
GND  
ADS5474  
Figure 40. Clock Input Circuit  
90  
fS = 400 MSPS  
fIN = 230 MHz  
85  
80  
SFDR (dBc)  
Square Wave or  
Sine Wave  
CLK  
0.01 mF  
ADS5474  
CLK  
75  
70  
65  
60  
0.01 mF  
SNR (dBFS)  
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
Clock Amplitude - VPP  
Figure 41. Single-Ended Clock  
Figure 42. AC Performance versus Clock Level  
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For jitter-sensitive applications, the use of a differential clock has some advantages at the system level. The  
differential clock allows for common-mode noise rejection at the printed circuit board (PCB) level. With a  
differential clock, the signal-to-noise ratio of the ADC is better for jitter-sensitive, high-frequency applications  
because the board level clock jitter is superior.  
Larger clock amplitude levels are recommended for high analog input frequencies or slow clock frequencies. In  
the case of a sinusoidal clock, larger amplitudes result in higher clock slew rates and reduces the impact of  
clock noise on jitter. At high analog input frequencies, the sampling process is sensitive to jitter. And at slow  
clock frequencies, a small amplitude sinusoidal clock has a lower slew rate and can create jitter-related SNR  
degradation. Figure 43 demonstrates a recommended method for converting a single-ended clock source into a  
differential clock; it is similar to the configuration found on the evaluation board and was used for much of the  
characterization. See also Clocking High Speed Data Converters (SLYT075) for more details.  
0.1 mF  
Clock  
CLK  
Source  
ADS5474  
CLK  
Figure 43. Differential Clock  
The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-kresistors. It is  
recommended to use ac coupling, but if this scheme is not possible, the ADS5474 features good tolerance to  
clock common-mode variation (as shown in Figure 44 and Figure 45). Additionally, the internal ADC core uses  
both edges of the clock for the conversion process. Ideally, a 50% duty-cycle clock signal should be provided.  
Performance degradation as a result of duty cycle can be seen in Figure 46.  
90  
85  
80  
75  
70  
65  
60  
55  
50  
75  
70  
65  
60  
55  
50  
10 MHz  
230 MHz  
70 MHz  
10 MHz  
70 MHz  
351 MHz  
351 MHz  
230 MHz  
fS = 400 MSPS  
VCLK = 3 VPP  
fS = 400 MSPS  
VCLK = 3 VPP  
4
5
0
1
2
3
Clock Common Mode - V  
4
5
0
1
2
3
Clock Common Mode - V  
Figure 44. SFDR versus Clock Common Mode  
Figure 45. SNR versus Clock Common Mode  
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90  
85  
80  
75  
70  
65  
60  
55  
50  
fIN = 10 MHz  
fIN = 70 MHz  
fIN = 230 MHz  
fIN = 300 MHz  
fS = 400 MSPS  
Clock Input = 3 VPP  
20  
30  
40  
50  
60  
70  
80  
Clock Duty Cycle - %  
Figure 46. SFDR vs Clock Duty Cycle  
The ADS5474 is capable of achieving 69.2 dBFS SNR at 350 MHz of analog input frequency. In order to  
achieve the SNR at 350 MHz the clock source rms jitter must be at least 144 fsec in order for the total rms jitter  
to be 177 fsec. A summary of maximum recommended rms clock jitter as a function of analog input frequency is  
provided in Table 2. The equations used to create the table are also presented.  
Table 2. Recommended RMS Clock Jitter  
INPUT FREQUENCY  
(MHz)  
MEASURED SNR  
(dBc)  
TOTAL JITTER  
(fsec rms)  
MAXIMUM CLOCK JITTER  
(fsec rms)  
30  
70  
69.3  
69.1  
69.1  
68.8  
68.2  
67.4  
65.6  
63.7  
1818  
798  
429  
251  
177  
151  
111  
104  
1816  
791  
417  
229  
144  
110  
42  
130  
230  
350  
450  
750  
1000  
14  
Equation 1 and Equation 2 are used to estimate the required clock source jitter.  
SNR (dBc) = -20 ´ LOG10 (2 ´ p ´ fIN ´ jTOTAL  
)
(1)  
(2)  
2
1/2  
jTOTAL = (jADC2 + jCLOCK  
)
where:  
jTOTAL = the rms summation of the clock and ADC aperture jitter;  
jADC = the ADC internal aperture jitter which is located in the data sheet;  
jCLOCK = the rms jitter of the clock at the clock input pins to the ADC; and  
fIN = the analog input frequency.  
Notice that the SNR is a strong function of the analog input frequency, not the clock frequency. The slope of the  
clock source edges can have a mild impact on SNR as well and is not taken into account for these estimates.  
For this reason, maximizing clock source amplitudes at the ADC clock inputs is recommended, though not  
required (faster slope is desireable for jitter-related SNR). For more information on clocking high-speed ADCs,  
see Application Note SLWA034, Implementing a CDC7005 Low Jitter Clock Solution For High-Speed, High-IF  
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ADC Devices, on the Texas Instruments web site. Recommended clock distribution chips (CDCs) are the TI  
CDC7005 and CDCM7005. Depending on the jitter requirements, a band pass filter (BPF) is sometimes required  
between the CDC and the ADC. If the insertion loss of the BPF causes the clock amplitude to be too low for the  
ADC, or the clock source amplitude is too low to begin with, an inexpensive amplifier can be placed between the  
CDC and the BPF.  
Figure 47 represents a scenario where an LVCMOS single-ended clock output is used from a TI CDCM7005  
with the clock signal path optimized for maximum amplitude and minimum jitter. This type of conditioning might  
generally be well-suited for use with greater than 150 MHz of input frequency. The jitter of this setup is difficult to  
estimate and requires a careful phase noise analysis of the clock path. The BPF (and possibly a low-cost  
amplifier because of insertion loss in the BPF) can improve the jitter between the CDC and ADC when the jitter  
provided by the CDC is still not adequate. The total jitter at the CDCM7005 output depends largely on the phase  
noise of the VCXO selected, as well as the CDCM7005, and typically has 50–100 fs of rms jitter. If it is  
determined that the jitter from the CDCM7005 with a VCXO is sufficient without further conditioning, it is possible  
to clock the ADS5474 directly from the CDCM7005 using differential LVPECL outputs, as illustrated in Figure 48  
(see the CDCM7005 data sheet for the exact schematic). This scenario may be more suitable for less than 150  
MHz of input frequency where jitter is not as critical. A careful analysis of the required jitter is recommended  
before determining the proper approach.  
Low-Jitter Clock Distribution  
AMP and/or BPF are Optional  
Board Master  
CLKIN  
Reference Clock  
BPF  
LVCMOS  
AMP  
XFMR  
REF  
(high or low jitter)  
10 MHz  
CLKIN  
400 MHz  
ADC  
800 MHz (to transmit DAC)  
100 MHz (to DSP)  
ADS5474  
LVPECL  
or  
LVCMOS  
Low-Jitter Oscillator  
800 MHz  
200 MHz (to FPGA)  
To Other  
VCXO  
CDC  
(Clock Distribution Chip)  
CDCM7005  
This is an example block diagram.  
Consult the CDCM7005 data sheet for proper schematic and specifications regarding allowable input and output  
frequency and amplitude ranges.  
Figure 47. Optimum Jitter Clock Circuit  
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Low-Jitter Clock Distribution  
400 MHz  
Board Master  
CLKIN  
CLKIN  
Reference Clock  
(high or low jitter)  
10 MHz  
LVPECL  
REF  
ADC  
800 MHz (to transmit DAC)  
100 MHz (to DSP)  
ADS5474  
LVPECL  
or  
LVCMOS  
Low-Jitter Oscillator  
800 MHz  
200 MHz (to FPGA)  
To Other  
VCXO  
CDC  
(Clock Distribution Chip)  
CDCM7005  
This is an example block diagram.  
Consult the CDCM7005 data sheet for proper schematic and specifications regarding allowable input and output  
frequency and amplitude ranges.  
Figure 48. Acceptable Jitter Clock Circuit  
Digital Outputs  
The ADC provides 14 LVDS-compatible, offset binary data outputs (D13 to D0; D13 is the MSB and D0 is the  
LSB), a data-ready signal (DRY), and an over-range indicator (OVR). It is recommended to use the DRY signal  
to capture the output data of the ADS5474. DRY is source-synchronous to the DATA/OVR outputs and operates  
at the same frequency, creating a half-rate DDR interface that updates data on both the rising and falling edges  
of DRY. It is recommended that the capacitive loading on the digital outputs be minimized. Higher capacitance  
shortens the data-valid timing window. The values given for timing (see Figure 1) were obtained with a  
measured 10-pF parasitic board capacitance to ground on each LVDS line (or 5-pF differential parasitic  
capacitance). When setting the time relationship between DRY and DATA at the receiving device, it is generally  
recommended that setup time be maximized, but this partially depends on the setup and hold times of the  
device receiving the digital data (like an FPGA or Field Programmable Field Array). Since DRY and DATA are  
coincident, it will likely be necessary to delay either DRY or DATA such that setup time is maximized.  
Referencing Figure 1, the polarity of DRY with respect to the sample N data output transition is undetermined  
because of the unknown startup logic level of the clock divider that generates the DRY signal (DRY is a  
frequency divide-by-two of CLK). Either the rising or the falling edge of DRY will be coincident with sample N  
and the polarity of DRY could invert when power is cycled off/on or when the power-down pin is cycled. Data  
capture from the transition and not the polarity of DRY is recommended, but not required. If the synchronization  
of multiple ADS5474 devices is required, it might be necessary to use a form of the CLKIN signal rather than  
DRY to capture the data.  
The DRY frequency is identical on the ADS5474 to the ADS5463 (where DRY equals 1/2 CLK frequency), but  
different than it is on the pin-similar ADS5444/ADS5440 (where DRY equals the CLK frequency). The LVDS  
outputs all require an external 100-load between each output pair in order to meet the expected LVDS voltage  
levels. For long trace lengths, it may be necessary to place a 100-load on each digital output as close to the  
ADS5474 as possible and another 100-differential load at the end of the LVDS transmission line to provide  
matched impedance and avoid signal reflections. The effective load in this case reduces the LVDS voltage  
levels by half.  
The OVR output equals a logic high when the 14-bit output word attempts to exceed either all 0s or all 1s. This  
flag is provided as an indicator that the analog input signal exceeded the full-scale input limit of approximately  
2.2 VPP (± gain error). The OVR indicator is provided for systems that use gain control to keep the analog input  
signal within acceptable limits.  
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Power Supplies  
The ADS5474 uses three power supplies. For the analog portion of the design, a 5-V and 3.3-V supply (AVDD5  
and AVDD3) are used, while the digital portion uses a 3.3-V supply (DVDD3). All the ground pins are marked as  
GND, although analog and digital grounds are not tied together inside the package. The use of low-noise power  
supplies with adequate decoupling is recommended. Linear supplies are preferred to switched supplies;  
switched supplies tend to generate more noise components that can be coupled to the ADS5474. However, the  
PSRR value and plot shown in Figure 49 were obtained without bulk supply decoupling capacitors. When bulk  
(0.1 μF) decoupling capacitors are used, the board-level PSRR is much higher than the stated value for the  
ADC. The user may be able to supply power to the device with a less-than-ideal supply and still achieve very  
good performance. It is not possible to make a single recommendation for every type of supply and level of  
decoupling for all systems. If the noise characteristics of the available supplies are understood, a study of the  
PSRR data for the ADS5474 may provide the user with enough information to select noisy supplies if the  
performance is still acceptable within the frequency range of interest. The power consumption of the ADS5474  
does not change substantially over clock rate or input frequency as a result of the architecture and process. The  
total maximum ensured power supersedes the summation of the maximum individual supply currents.  
0
fS = 400 MSPS  
-10  
-20  
-30  
-40  
AVDD5  
-50  
-60  
-70  
-80  
AVDD3  
-90  
-100  
-110  
DVDD3  
-120  
100 k  
1 M  
10 M  
100 M  
1 G  
Frequency - Hz  
Figure 49. PSRR versus Supply Injected Frequency  
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Operational Lifetime  
It is important for applications that anticipate running continously for long periods of time near the  
maximum-rated ambient temperature of +85°C to consider the data shown in Figure 50. Referring to the  
Thermal Characteristics table, the worst-case operating condition with no airflow has a thermal rise of 23.7°C/W.  
At approximately 2.5 W of normal power dissipation, at a maximum ambient of +85°C with no airflow, the  
junction temperature of the ADS5474 reaches approximately +85°C + 23.7°C/W × 2.5 W = +144°C. Being even  
more conservative and accounting for the maximum possible power dissipation that is ensured (2.755 W), the  
junction temperature becomes nearly +150°C. As Figure 50 shows, this performance limits the expected lifetime  
of the ADS5474. Operation at +85°C continously may require airflow or an additional heatsink in order to  
decrease the internal junction temperature and increase the expected lifetime (because of electromigration  
failures). An airflow of 250 LFM (linear feet per minute) reduces the thermal resistance to 16.4°C/W and,  
therefore, the maximum junction temperature to +130°C, assuming a worst-case of 2.755 W and +85°C ambient.  
The ADS5474 performance over temperature is quite good and can be seen starting in Figure 21. Though the  
typical plots show good performance at +100°C, the device is only rated from –40°C to +85°C. For continuous  
operation at temperatures near or above the maximum, the expected primary negative effect is a shorter device  
lifetime because of the electromigration failures at high junction temperatures. The maximum recommended  
continuous junction temperature is +150°C.  
1000  
100  
10  
1
80  
90 100 110 120 130 140 150 160 170 180  
Continuous Junction Temperature - °C  
Figure 50. Operating Life Derating Chart, Electromigration Fail Mode  
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Layout Information  
The evaluation board represents a good model of how to lay out the printed circuit board (PCB) to obtain the  
maximum performance from the ADS5474. Follow general design rules, such as the use of multilayer boards, a  
single ground plane for ADC ground connections, and local decoupling ceramic chip capacitors. The analog  
input traces should be isolated from any external source of interference or noise, including the digital outputs as  
well as the clock traces. The clock signal traces should also be isolated from other signals, especially in  
applications such as high IF sampling where low jitter is required. Besides performance-oriented rules, care  
must be taken when considering the heat dissipation of the device. The thermal heatsink included on the bottom  
of the package should be soldered to the board as described in the PowerPad Package section. See the  
ADS5474 EVM User Guide (SLAU194) on the TI web site for the evaluation board schematic.  
PowerPAD Package  
The PowerPAD package is a thermally-enhanced, standard-size IC package designed to eliminate the use of  
bulky heatsinks and slugs traditionally used in thermal packages. This package can be easily mounted using  
standard PCB assembly techniques, and can be removed and replaced using standard repair procedures.  
The PowerPAD package is designed so that the leadframe die pad (or thermal pad) is exposed on the bottom of  
the IC. This pad design provides an extremely low thermal resistance path between the die and the exterior of  
the package. The thermal pad on the bottom of the IC can then be soldered directly to the PCB, using the PCB  
as a heatsink.  
Assembly Process  
1. Prepare the PCB top-side etch pattern including etch for the leads as well as the thermal pad as  
illustrated in the Mechanical Data section (at the end of this data sheet).  
2. Place a 6-by-6 array of thermal vias in the thermal pad area. These holes should be 13 mils (0.013 in or  
0.3302 mm) in diameter. The small size prevents wicking of the solder through the holes.  
3. It is recommended to place a small number of 25 mil (0.025 in or 0.635 mm) diameter holes under the  
package, but outside the thermal pad area, to provide an additional heat path.  
4. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such  
as a ground plane).  
5. Do not use the typical web or spoke via-connection pattern when connecting the thermal vias to the  
ground plane. The spoke pattern increases the thermal resistance to the ground plane.  
6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area.  
7. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking.  
8. Apply solder paste to the exposed thermal pad area and all of the package terminals.  
For more detailed information regarding the PowerPAD package and its thermal properties, see either the  
PowerPAD Made Easy application brief (SLMA004) or the PowerPAD Thermally Enhanced Package application  
report (SLMA002), both available for download at www.ti.com.  
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DEFINITION OF SPECIFICATIONS  
The injected frequency level is translated into dBFS,  
the spur in the output FFT is measured in dBFS, and  
the difference is the PSRR in dB. The measurement  
calibrates out the benefit of the board supply  
decoupling capacitors.  
Analog Bandwidth  
The analog input frequency at which the power of the  
fundamental is reduced by 3 dB with respect to the  
low-frequency value.  
Signal-to-Noise Ratio (SNR)  
Aperture Delay  
SNR is the ratio of the power of the fundamental (PS)  
to the noise floor power (PN), excluding the power at  
dc and in the first five harmonics.  
The delay in time between the rising edge of the  
input sampling clock and the actual time at which the  
sampling occurs.  
P
10  
P
S
SNR + 10log  
Aperture Uncertainty (Jitter)  
The sample-to-sample variation in aperture delay.  
N
(4)  
SNR is either given in units of dBc (dB to carrier)  
when the absolute power of the fundamental is used  
as the reference, or dBFS (dB to full-scale) when the  
power of the fundamental is extrapolated to the  
converter full-scale range.  
Clock Pulse Duration/Duty Cycle  
The duty cycle of a clock signal is the ratio of the  
time the clock signal remains at a logic high (clock  
pulse duration) to the period of the clock signal,  
expressed as a percentage.  
Signal-to-Noise and Distortion (SINAD)  
SINAD is the ratio of the power of the fundamental  
(PS) to the power of all the other spectral  
components including noise (PN) and distortion (PD),  
but excluding dc.  
Differential Nonlinearity (DNL)  
An ideal ADC exhibits code transitions at analog  
input values spaced exactly 1 LSB apart. DNL is the  
deviation of any single step from this ideal value,  
measured in units of LSB.  
P
Common-Mode Rejection Ratio (CMRR)  
S
SINAD + 10log  
10  
CMRR measures the ability to reject signals that are  
presented to both analog inputs simultaneously. The  
injected common-mode frequency level is translated  
into dBFS, the spur in the output FFT is measured in  
dBFS, and the difference is the CMRR in dB.  
P
) P  
N
D
(5)  
SINAD is either given in units of dBc (dB to carrier)  
when the absolute power of the fundamental is used  
as the reference, or dBFS (dB to full-scale) when the  
power of the fundamental is extrapolated to the  
converter full-scale range.  
Effective Number of Bits (ENOB)  
ENOB is a measure in units of bits of converter  
performance as compared to the theoretical limit  
based on quantization noise:  
Temperature Drift  
Temperature drift (with respect to gain error and  
offset error) specifies the change from the value at  
the nominal temperature to the value at TMIN or TMAX  
It is computed as the maximum variation the  
parameters over the whole temperature range  
ENOB = (SINAD – 1.76)/6.02  
.
Gain Error  
Gain error is the deviation of the ADC actual input  
full-scale range from its ideal value, given as a  
percentage of the ideal input full-scale range.  
divided by TMIN – TMAX  
.
Total Harmonic Distortion (THD)  
THD is the ratio of the power of the fundamental (PS)  
to the power of the first five harmonics (PD).  
Integral Nonlinearity (INL)  
INL is the deviation of the ADC transfer function from  
a best-fit line determined by a least-squares curve fit  
of that transfer function. The INL at each analog  
input value is the difference between the actual  
transfer function and this best-fit line, measured in  
units of LSB.  
P
S
THD + 10log  
10  
P
D
(6)  
THD is typically given in units of dBc (dB to carrier).  
Two-Tone Intermodulation Distortion (IMD3)  
IMD3 is the ratio of the power of the fundamental (at  
frequencies f1, f2) to the power of the worst spectral  
component at either frequency 2f1 – f2 or 2f2 – f1).  
IMD3 is given in units of either dBc (dB to carrier)  
when the absolute power of the fundamental is used  
as the reference, or dBFS (dB to full-scale) when the  
power of the fundamental is extrapolated to the  
converter full-scale range.  
Offset Error  
Offset error is the deviation of output code from  
mid-code when both inputs are tied to  
common-mode.  
Power-Supply Rejection Ratio (PSRR)  
PSRR is  
a measure of the ability to reject  
frequencies present on the power supply.  
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PACKAGE OPTION ADDENDUM  
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PACKAGING INFORMATION  
Orderable Device  
ADS5474IPFP  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
HTQFP  
PFP  
80  
80  
80  
80  
96 Green (RoHS & CU NIPDAU Level-4-260C-72 HR  
no Sb/Br)  
ADS5474IPFPG4  
ADS5474IPFPR  
ADS5474IPFPRG4  
HTQFP  
HTQFP  
HTQFP  
PFP  
PFP  
PFP  
96 Green (RoHS & CU NIPDAU Level-4-260C-72 HR  
no Sb/Br)  
1000 Green (RoHS & CU NIPDAU Level-4-260C-72 HR  
no Sb/Br)  
1000 Green (RoHS & CU NIPDAU Level-4-260C-72 HR  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
8-Oct-2007  
TAPE AND REEL BOX INFORMATION  
Device  
Package Pins  
Site  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) (mm) Quadrant  
(mm)  
(mm)  
ADS5474IPFPR  
PFP  
80  
SITE 60  
330  
24  
15.0  
15.0  
1.5  
20  
24  
Q2  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
8-Oct-2007  
Device  
Package  
Pins  
Site  
Length (mm) Width (mm) Height (mm)  
ADS5474IPFPR  
PFP  
80  
SITE 60  
0.0  
0.0  
0.0  
Pack Materials-Page 2  
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