ADS54J69IRMPT [TI]
双通道、16 位、500MSPS 模数转换器 (ADC) | RMP | 72 | -40 to 85;型号: | ADS54J69IRMPT |
厂家: | TEXAS INSTRUMENTS |
描述: | 双通道、16 位、500MSPS 模数转换器 (ADC) | RMP | 72 | -40 to 85 转换器 模数转换器 |
文件: | 总81页 (文件大小:3998K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ADS54J69
ZHCSEJ4C –MAY 2015–REVISED JANUARY 2017
ADS54J69 双通道、16 位、500MSPS 模数转换器
1 特性
3 说明
1
•
16 位分辨率、双通道、500 MSPS 模数转换器
ADS54J69 是一款低功耗、高带宽 16 位、500MSPS
(DAC)
双通道模数转换器 (ADC)。该器件经设计具有高信噪
比 (SNR),可提供 -159dBFS/Hz 的噪底,从而 协助应
用在宽瞬时带宽内 实现最高动态范围。该器件支持
JESD204B 串行接口,数据传输速率高达 10Gbps,每
个 ADC 可支持 1 或 2 条通道。经缓冲的模拟输入可
在较宽频率范围内提供统一输入阻抗并最大程度地降低
采样和保持毛刺脉冲能量。可选择将每条 ADC 通道直
接与宽带数字下变频器 (DDC) 模块相连。ADS54J69
以超低功耗在宽输入频率范围内提供出色的无杂散动态
范围 (SFDR)。
•
•
空闲通道噪底:-159dBFS/Hz
频谱性能(–1dBFS 时的 fIN = 170MHz):
–
–
–
–
信噪比 (SNR):73dBFS
噪声频谱密度 (NSD):–157dBFS/Hz
无杂散动态范围 (SFDR):93dBc
SFDR:94dBc(不包括 HD2、HD3 和交错音
调)
•
频谱性能(–1dBFS 时的 fIN = 310MHz):
–
–
–
–
SNR:71.7dBFS
NSD:–155.7dBFS/Hz
SFDR:81dBc
JESD204B 接口减少了接口线路数,从而实现高系统
集成度。内部锁相环 (PLL) 会将 ADC 采样时钟加倍,
以获得串行化各通道的 16 位数据时所使用的位时钟。
SFDR:94dBc(不包括 HD2、HD3 和交错音
调)
•
•
•
•
•
•
通道隔离:fIN = 170MHz 时为 100dBc
输入满量程:1.9 VPP
器件信息
器件编号
ADS54J69
封装
封装尺寸(标称值)
VQFNP (72)
10.00mm x 10.00mm
输入带宽 (3dB):1.2GHz
片上抖动
(1) 要了解所有可用封装,请参见数据表末尾的可订购产品附录。
集成 2 倍抽取率滤波器
支持 JESD204B 子类 1 接口:
–
–
–
10.0Gbps 时每个 ADC 1 条通道
5.0Gbps 时每个 ADC 2 条通道
支持多芯片同步
170MHz 中频 (IF) 时的频谱
0
SNR = 73 dBFS
SFDR = 93 dBc
Non HD2, HD3 Spur = 94 dBc
-20
-40
•
•
功耗:500MSPS 时为 1.35W/通道
72 引脚超薄型四方扁平无引线 (VQFN) 封装
(10mm × 10mm)
-60
2 应用
•
•
•
•
•
•
•
•
雷达和天线阵列
-80
无线宽带
-100
-120
电缆 CMTS、DOCSIS 3.1 接收器
通信测试设备
0
50
100 150
Input Frequency (MHz)
200
250
微波接收器
D003
软件定义无线电 (SDR)
数字转换器
医疗成像和诊断功能
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBAS713
ADS54J69
ZHCSEJ4C –MAY 2015–REVISED JANUARY 2017
www.ti.com.cn
目录
8.3 Feature Description................................................. 25
8.4 Device Functional Modes........................................ 30
8.5 Register Maps......................................................... 39
Application and Implementation ........................ 63
9.1 Application Information............................................ 63
9.2 Typical Application .................................................. 68
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 4
Pin Configuration and Functions......................... 5
Specifications......................................................... 7
7.1 Absolute Maximum Ratings ...................................... 7
7.2 ESD Ratings.............................................................. 7
7.3 Recommended Operating Conditions....................... 7
7.4 Thermal Information.................................................. 8
7.5 Electrical Characteristics........................................... 8
7.6 AC Characteristics .................................................... 9
7.7 Digital Characteristics ............................................. 11
7.8 Timing Characteristics............................................. 12
7.9 Typical Characteristics............................................ 14
Detailed Description ............................................ 24
8.1 Overview ................................................................. 24
8.2 Functional Block Diagram ....................................... 24
9
10 Power Supply Recommendations ..................... 70
10.1 Power Sequencing and Initialization..................... 71
11 Layout................................................................... 72
11.1 Layout Guidelines ................................................. 72
11.2 Layout Example .................................................... 73
12 器件和文档支持 ..................................................... 74
12.1 文档支持................................................................ 74
12.2 接收文档更新通知 ................................................. 74
12.3 社区资源................................................................ 74
12.4 商标....................................................................... 74
12.5 静电放电警告......................................................... 74
12.6 Glossary................................................................ 74
13 机械、封装和可订购信息....................................... 74
8
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Revision B (February 2016) to Revision C
Page
•
•
•
•
•
•
•
•
•
•
•
Added Device Comparison Table........................................................................................................................................... 5
Added the FOVR latency parameter to the Timing Characteristics table............................................................................. 12
Added SYSREF Not Present (Subclass 0, 2) section .......................................................................................................... 27
Changed the number of clock cycles in the Fast OVR section ............................................................................................ 28
Changed the Register Map................................................................................................................................................... 40
Deleted register 39h, 3Ah, and 56h ..................................................................................................................................... 40
Changed the SNR versus Input Frequency and External Clock Jitter figure ....................................................................... 67
Changed Power Supply Recommendations section ........................................................................................................... 70
Added the Power Sequencing and Initialization section....................................................................................................... 71
已添加 文档支持和接收文档更新通知部分............................................................................................................................ 74
已添加 接收文档更新通知部分.............................................................................................................................................. 74
Changes from Revision A (January 2016) to Revision B
Page
•
•
•
•
•
•
Changed Sample Timing, Aperture jitter parameter in Timing Characteristics table .......................................................... 12
Changed Table 35 ................................................................................................................................................................ 51
Changed Table 42 ................................................................................................................................................................ 54
Changed Table 44 ................................................................................................................................................................ 55
Changed SNR and Clock Jitter section: changed Figure 130 and last sentence of section................................................ 67
Changed Application Curves section ................................................................................................................................... 70
2
版权 © 2015–2017, Texas Instruments Incorporated
ADS54J69
www.ti.com.cn
ZHCSEJ4C –MAY 2015–REVISED JANUARY 2017
Changes from Original (May 2015) to Revision A
Page
•
已发布为“量产数据”................................................................................................................................................................. 1
Copyright © 2015–2017, Texas Instruments Incorporated
3
ADS54J69
ZHCSEJ4C –MAY 2015–REVISED JANUARY 2017
www.ti.com.cn
5 Device Comparison Table
PART NUMBER
ADS54J20
ADS54J42
ADS54J40
ADS54J60
ADS54J66
ADS54J69
SPEED GRADE (MSPS)
RESOLUTION (Bits)
CHANNEL
1000
625
12
14
14
16
14
16
2
2
2
2
4
2
1000
1000
500
500
4
Copyright © 2015–2017, Texas Instruments Incorporated
ADS54J69
www.ti.com.cn
ZHCSEJ4C –MAY 2015–REVISED JANUARY 2017
6 Pin Configuration and Functions
RMP Package
72-Pin VQFNP
Top View
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
1
2
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
DB3M
DB3P
DA3M
DA3P
DGND
IOVDD
PDN
3
DGND
IOVDD
SDIN
4
5
6
SCLK
RES
7
SEN
RESET
DVDD
AVDD
AVDD3V
AVDD
AVDD
INAP
8
DVDD
AVDD
AVDD3V
SDOUT
AVDD
INBP
9
GND Pad
(Back Side)
10
11
12
13
14
15
16
17
18
INBM
INAM
AVDD
AVDD3V
AVDD
AGND
AVDD
AVDD3V
AVDD
AGND
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Copyright © 2015–2017, Texas Instruments Incorporated
5
ADS54J69
ZHCSEJ4C –MAY 2015–REVISED JANUARY 2017
www.ti.com.cn
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
CLOCK, SYSREF
CLKINM
28
27
34
33
I
I
I
I
Negative differential clock input for the ADC
Positive differential clock input for the ADC
Negative external SYSREF input
CLKINP
SYSREFM
SYSREFP
Positive external SYSREF input
CONTROL, SERIAL INTERFACE
Power-down. Can be configured via an SPI register setting.
Can be configured to fast overrange output for channel A via the SPI.
PDN
50
I/O
RESET
SCLK
SDIN
48
6
I
I
I
Hardware reset; active high. This pin has an internal 20-kΩ pulldown resistor.
Serial interface clock input
5
Serial interface data input
Serial interface data output.
Can be configured to fast overrange output for channel B via the SPI.
SDOUT
11
7
O
I
SEN
Serial interface enable
DATA INTERFACE
DA0M
DA1M
DA2M
DA3M
DA0P
62
59
56
54
61
58
55
53
65
68
71
1
O
O
O
JESD204B serial data negative outputs for channel A
DA1P
JESD204B serial data positive outputs for channel A
JESD204B serial data negative outputs for channel B
DA2P
DA3P
DB0M
DB1M
DB2M
DB3M
DB0P
66
69
72
2
DB1P
O
I
JESD204B serial data positive outputs for channel B
Synchronization input for JESD204B port
DB2P
DB3P
SYNC
INPUT, COMMON MODE
INAM
63
41
42
14
13
I
I
I
I
Differential analog negative input for channel A
Differential analog positive input for channel A
Differential analog negative input for channel B
Differential analog positive input for channel B
Common-mode voltage, 2.1 V.
INAP
INBM
INBP
VCM
22
O
Note that analog inputs are internally biased to this pin through 600 Ω (effective), no external
connection from the VCM pin to the INxP or INxM pin is required.
POWER SUPPLY
AGND
AVDD
18, 23, 26, 29, 32, 36, 37
I
I
Analog ground
9, 12, 15, 17, 25, 30, 35, 38,
40, 43, 44, 46
Analog 1.9-V power supply
AVDD3V
DGND
DVDD
IOVDD
NC, RES
NC
10, 16, 24, 31, 39, 45
3, 52, 60, 67
8, 47
I
I
I
I
Analog 3.0-V power supply for the analog buffer
Digital ground
Digital 1.9-V power supply
4, 51, 57, 64, 70
Digital 1.15-V power supply for the JESD204B transmitter
19, 20, 21
49
—
I
Unused pins, do not connect
RES
Reserved pin. Connect to DGND.
6
Copyright © 2015–2017, Texas Instruments Incorporated
ADS54J69
www.ti.com.cn
ZHCSEJ4C –MAY 2015–REVISED JANUARY 2017
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.2
–0.3
–0.3
–0.3
–0.3
–0.2
–65
MAX
UNIT
V
AVDD3V
3.6
AVDD
Supply voltage range
DVDD
2.1
2.1
IOVDD
Voltage between AGND and DGND
INAP, INBP, INAM, INBM
1.4
0.3
3
V
CLKINP, CLKINM
Voltage applied to input pins
AVDD + 0.3
AVDD + 0.3
2.1
V
SYSREFP, SYSREFM
SCLK, SEN, SDIN, RESET, SYNC, PDN
Storage temperature, Tstg
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±1000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V HBM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
2.85
1.8
NOM
3.0
MAX
3.6
UNIT
AVDD3V
AVDD
1.9
2.0
Supply voltage range
Analog inputs
V
DVDD
1.7
1.9
2.0
IOVDD
1.1
1.15
1.9
1.2
Differential input voltage range
Input common-mode voltage
VPP
V
2.0
Maximum analog input frequency for 1.9-VPP input amplitude(3)(4)
Input clock frequency, device clock frequency
Sine wave, ac-coupled
400
MHz
MHz
500
0.75
0.8
1000
1.5
1.6
Input clock amplitude differential
Clock inputs
Temperature
LVPECL, ac-coupled
VPP
(VCLKP – VCLKM
)
LVDS, ac-coupled
0.7
Input device clock duty cycle
Operating free-air, TA
45%
–40
50%
55%
85
ºC
Operating junction, TJ
105(5)
125
(1) SYSREF must be applied for the device to initialize; see the SYSREF Signal section for details.
(2) After power-up, always use a hardware reset to reset the device for the first time; see Table 60 for details.
(3) Operating 0.5 dB below the maximum-supported amplitude is recommended to accommodate gain mismatch in interleaving ADCs.
(4) At high frequencies, the maximum supported input amplitude reduces; see Figure 51 for details.
(5) Prolonged use above the nominal junction temperature can increase the device failure-in-time (FIT) rate.
Copyright © 2015–2017, Texas Instruments Incorporated
7
ADS54J69
ZHCSEJ4C –MAY 2015–REVISED JANUARY 2017
www.ti.com.cn
7.4 Thermal Information
ADS54J69
THERMAL METRIC(1)
RMP (VQFNP)
UNIT
72 PINS
22.3
5.1
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
2.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.1
ψJB
2.3
RθJC(bot)
0.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency =
1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD =
1.15 V, –1-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GENERAL
Device clock frequency
Output sample rate
Resolution
1000 MSPS
500 MSPS
Bits
16
POWER SUPPLIES
AVDD3V
AVDD
DVDD
IOVDD
IAVDD3V
IAVDD
3.0-V analog supply
2.85
1.8
3.0
1.9
3.6
2.0
V
V
1.9-V analog supply
1.9-V digital supply
1.7
1.9
2.0
V
1.15-V SERDES supply
3.0-V analog supply current
1.9-V analog supply current
1.9-V digital supply current
1.15-V SERDES supply current
Total power dissipation
1.1
1.15
293
354
188
512
2.66
195
559
2.73
1.2
V
VIN = full-scale on both channels
VIN = full-scale on both channels
360
510
260
920
3.1
mA
mA
mA
mA
W
IDVDD
Four-lane output mode
(default after reset)
IIOVDD
Pdis
IDVDD
1.9-V digital supply current
1.15-V SERDES supply current
Total power dissipation
mA
mA
W
IIOVDD
Pdis
Two-lane output mode
Using the GLOBAL PDN register
bit in the master page
Global power-down power dissipation
204
315
mW
8
Copyright © 2015–2017, Texas Instruments Incorporated
ADS54J69
www.ti.com.cn
ZHCSEJ4C –MAY 2015–REVISED JANUARY 2017
7.6 AC Characteristics
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency =
1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD =
1.15 V, –1-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fIN = 10 MHz, AIN = –1 dBFS
fIN = 140 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
fIN = 210 MHz, AIN = –1 dBFS
fIN = 310 MHz, AIN = –1 dBFS
fIN = 370 MHz, AIN = –1 dBFS
fIN = 470 MHz, AIN = –3 dBFS
fIN = 10 MHz, AIN = –1 dBFS
fIN = 140 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
fIN = 210 MHz, AIN = –1 dBFS
fIN = 310 MHz, AIN = –1 dBFS
fIN = 370 MHz, AIN = –1 dBFS
fIN = 470 MHz, AIN = –3 dBFS
fIN = 10 MHz, AIN = –1 dBFS
fIN = 140 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
fIN = 210 MHz, AIN = –1 dBFS
fIN = 310 MHz, AIN = –1 dBFS
fIN = 370 MHz, AIN = –1 dBFS
fIN = 470 MHz, AIN = –3 dBFS
fIN = 10 MHz, AIN = –1 dBFS
fIN = 140 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
fIN = 210 MHz, AIN = –1 dBFS
fIN = 310 MHz, AIN = –1 dBFS
fIN = 370 MHz, AIN = –1 dBFS
fIN = 470 MHz, AIN = –3 dBFS
fIN = 10 MHz, AIN = –1 dBFS
fIN = 140 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
fIN = 210 MHz, AIN = –1 dBFS
fIN = 310 MHz, AIN = –1 dBFS
fIN = 370 MHz, AIN = –1 dBFS
fIN = 470 MHz, AIN = –3 dBFS
fIN = 10 MHz, AIN = –1 dBFS
fIN = 140 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
fIN = 210 MHz, AIN = –1 dBFS
fIN = 310 MHz, AIN = –1 dBFS
fIN = 370 MHz, AIN = –1 dBFS
fIN = 470 MHz, AIN = –3 dBFS
MIN
TYP
74.2
73.4
73
MAX
UNIT
71.3
SNR
Signal-to-noise ratio
72.7
71.7
70.3
70.5
158.2
157.4
157.0
156.7
155.7
154.3
154.5
73.8
73.3
72.9
72.5
71.2
70.2
69.4
86
dBFS
155.3
69.8
79
NSD
Noise spectral density
dBFS/Hz
dBFS
dBc
SINAD
SFDR
HD2
Signal-to-noise and distortion ratio
95
94
Spurious free dynamic range
(excluding IL spurs)
89
81
87
73
86
104
102
95
85
Second-order harmonic distortion
dBc
81
87
96
89
103
101
100
98
86
HD3
Third-order harmonic distortion
dBc
95
73
Copyright © 2015–2017, Texas Instruments Incorporated
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ADS54J69
ZHCSEJ4C –MAY 2015–REVISED JANUARY 2017
www.ti.com.cn
AC Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency =
1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD =
1.15 V, –1-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fIN = 10 MHz, AIN = –1 dBFS
fIN = 140 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
fIN = 210 MHz, AIN = –1 dBFS
fIN = 310 MHz, AIN = –1 dBFS
fIN = 370 MHz, AIN = –1 dBFS
fIN = 470 MHz, AIN = –3 dBFS
fIN = 10 MHz, AIN = –1 dBFS
fIN = 140 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
fIN = 210 MHz, AIN = –1 dBFS
fIN = 310 MHz, AIN = –1 dBFS
fIN = 370 MHz, AIN = –1 dBFS
fIN = 470 MHz, AIN = –3 dBFS
fIN = 10 MHz, AIN = –1 dBFS
fIN = 140 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
fIN = 210 MHz, AIN = –1 dBFS
fIN = 310 MHz, AIN = –1 dBFS
fIN = 370 MHz, AIN = –1 dBFS
fIN = 470 MHz, AIN = –3 dBFS
fIN = 10 MHz, AIN = –1 dBFS
fIN = 140 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
fIN = 210 MHz, AIN = –1 dBFS
fIN = 310 MHz, AIN = –1 dBFS
fIN = 370 MHz, AIN = –1 dBFS
fIN = 470 MHz, AIN = –3 dBFS
MIN
TYP
98
MAX
UNIT
95
84
94
Non
Spurious-free dynamic range
HD2, HD3 (excluding HD2, HD3, and IL spur)
89
dBc
92
97
92
12
11.9
11.9
11.8
11.5
11.4
11.2
84
11.3
ENOB
Effective number of bits
Total harmonic distortion
Interleaving spur
Bits
95
79
89
THD
85
dBc
80
85
72
90
90
75
87
SFDR_IL
85
dBc
85
86
82
fIN1 = 185 MHz, fIN2 = 190 MHz,
AIN = –7 dBFS
86
79
78
Two-tone, third-order
intermodulation distortion
fIN1 = 365 MHz, fIN2 = 370 MHz,
AIN = –7 dBFS
IMD3
dBFS
fIN1 = 465 MHz, fIN2 = 470 MHz,
AIN = –10 dBFS
10
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7.7 Digital Characteristics
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency =
1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD =
1.15 V, –1-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, SYNC, PDN)(1)
VIH
VIL
High-level input voltage
Low-level input voltage
All digital inputs support 1.2-V and 1.8-V logic levels
All digital inputs support 1.2-V and 1.8-V logic levels
SEN
0.8
V
V
0.4
0
50
50
0
IIH
High-level input current
Low-level input current
µA
µA
RESET, SCLK, SDIN, PDN, SYNC
SEN
IIL
RESET, SCLK, SDIN, PDN, SYNC
DIGITAL INPUTS (SYSREFP, SYSREFM)
VD
Differential input voltage
Common-mode voltage for SYSREF(2)
0.35
0.45
1.3
1.4
V
V
V(CM_DIG)
DIGITAL OUTPUTS (SDOUT, PDN(3)
)
DVDD –
0.1
VOH
VOL
High-level output voltage
Low-level output voltage
DVDD
V
V
0.1
DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM)(4)
VOD
VOC
Output differential voltage
With default swing setting
700
450
mVPP
mV
Output common-mode voltage
Transmitter pins shorted to any voltage between
–0.25 V and 1.45 V
Transmitter short-circuit current
Single-ended output impedance
Output capacitance
–100
100
mA
Ω
zos
50
2
Output capacitance inside the device,
from either output to ground
pF
(1) The RESET, SCLK, SDIN, and PDN pins have a 20-kΩ (typical) internal pulldown resistor to ground, and the SEN pin has a 20-kΩ
(typical) pullup resistor to IOVDD.
(2) The SYSREFP and SYSREFM pins are internally biased to the 1.3-V common-mode voltage through a 5-kΩ resistor.
(3) When functioning as an OVR pin for channel B.
(4) 100-Ω differential termination.
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7.8 Timing Characteristics
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency =
1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD =
1.15 V, and –1-dBFS differential input (unless otherwise noted)
MIN
TYP
MAX
UNITS
SAMPLE TIMING
Aperture delay
0.75
1.6
ns
ps
ps
Aperture delay matching between two channels on the same device
±70
±270
145
Aperture delay matching between two devices at the same temperature and supply voltage
Actual jitter of sampling clock buffer
Aperture jitter
fS rms
Effective jitter after decimation filtering
102
WAKE-UP TIMING
Wake-up time to valid data after coming out of global power-down
150
µs
LATENCY
Input
clock
cycles
Data latency(1): ADC sample to digital output
OVR latency: ADC sample to OVR bit
134(2)
62
Input
clock
cycles
Input
clock
cycles
FOVR latency: ADC sample to FOVR signal on pin
18 + 4 ns
4
tPD
Propagation delay: logic gates and output buffers delay (does not change with fS)
ns
SYSREF TIMING
tSU_SYSREF Setup time for SYSREF, referenced to the input clock falling edge
300
100
900
ps
ps
tH_SYSREF
Hold time for SYSREF, referenced to the input clock falling edge
JESD OUTPUT INTERFACE TIMING CHARACTERISTICS
Unit interval
100
2.5
400
10
ps
Gbps
ps
Serial output data rate
Total jitter for BER of 1E-15 and lane rate = 10 Gbps
Random jitter for BER of 1E-15 and lane rate = 10 Gbps
Deterministic jitter for BER of 1E-15 and lane rate = 10 Gbps
26
0.75
12
ps rms
ps, pk-pk
Data rise time, data fall time: rise and fall times are measured from 20% to 80%,
differential output waveform, 2.5 Gbps ≤ bit rate ≤ 10 Gbps
tR, tF
35
ps
(1) Overall latency = data latency + decimation filter delay + tPDI
.
(2) Decimation filter latency is not included in this specification.
Sample N
ts_min
ts_max
CLKIN
1.0 GSPS
SYSREF
Figure 1. SYSREF Timing
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N+1
N+2
N
N+3
Sample
tPD
Data Latency: 134 Clock Cycles
CLKINM
CLKINP
DA0P, DA0M,
DB0P, DB0M
D20
D11 D20
D11 D20
Sample N-1
Sample N
Sample N+1
Sample N+2
DA1P, DA1M,
DB1P, DB1M
D10
D1
D10
D1
D10
Sample N-1
Sample N
Sample N+1
Sample N+2
Figure 2. Sample Timing Requirements
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7.9 Typical Characteristics
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency =
1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD =
1.15 V, and –1-dBFS differential input (unless otherwise noted)
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
50
100
150
200
250
0
50
100
150
200
250
Input Frequency (MHz)
Input Frequency (MHz)
D001
D002
SNR = 74.2 dBFS; SFDR = 86 dBc; SINAD = 73.8 dBFS;
THD = 83 dBc; HD2 = 86 dBc; HD3 = 89 dBc;
IL spur = 99 dBc; non HD2, HD3 spur = 98 dBc
SNR = 73.3 dBFS; SFDR = 94 dBc; SINAD = 73.25 dBFS;
THD = 93 dBc; HD2 = 104 dBc; HD3 = 111 dBc;
IL spur = 95 dBc; non HD2, HD3 spur = 94 dBc
Figure 3. FFT for 10-MHz Input Signal
Figure 4. FFT for 140-MHz Input Signal
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
50
100
150
200
250
0
50
100
150
200
250
Input Frequency (MHz)
Input Frequency (MHz)
D003
D004
SNR = 73 dBFS; SFDR = 93 dBc; SINAD = 73.18 dBFS;
THD = 89 dBc; HD2 = 93 dBc; HD3 = 103 dBc;
IL spur = 99 dBc; non HD2, HD3 spur = 94 dBc
SNR = 72.8 dBFS; SFDR = 89 dBc; SINAD = 72.63 dBFS;
THD = 86 dBc; HD2 = 97 dBc; HD3 = 99 dBc;
IL spur = 84 dBc; non HD2, HD3 spur = 89 dBc
Figure 5. FFT for 170-MHz Input Signal
Figure 6. FFT for 210-MHz Input Signal
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
50
100
150
200
250
0
50
100
150
200
250
Input Frequency (MHz)
Input Frequency (MHz)
D005
D007
SNR = 71.6 dBFS; SFDR = 80 dBc; SINAD = 71 dBFS;
THD = 79 dBc; HD2 = –80 dBc; HD3 = –96 dBc;
IL spur = 85 dBc; non HD2, HD3 spur = 92 dBc
SNR = 70.5 dBFS; SFDR = 86 dBc; SINAD = 70.4 dBFS;
THD = 85 dBc; HD2 = –86 dBc; HD3 = –96 dBc;
IL spur = 98 dBc; non HD2, HD3 spur = 98 dBc
Figure 7. FFT for 310-MHz Input Signal
Figure 8. FFT for 370-MHz Input Signal
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Typical Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency =
1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD =
1.15 V, and –1-dBFS differential input (unless otherwise noted)
0
0
-20
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
50
100
150
200
250
0
50
100
150
200
250
Input Frequency (MHz)
Input Frequency (MHz)
D007
D008
SNR = 70.6 dBFS; SFDR = 86 dBc; SINAD = 70.55 dBFS;
THD = 85 dBc; tone at –3 dBFS; HD2 = 102 dBc; HD3 = 86 dBc;
IL spur = 97 dBc; non HD2, HD3 spur = 96 dBc
fIN1 = 185 MHz, fIN2 = 190 MHz, each tone at –7 dBFS,
IMD = 86 dBFS
Figure 9. FFT for 470-MHz Input Signal
Figure 10. FFT for Two-Tone Input Signal (–7 dBFS)
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
50
100
150
200
250
0
50
100
150
200
250
Input Frequency (MHz)
Input Frequency (MHz)
D009
D010
fIN1 = 185 MHz, fIN2 = 190 MHz, each tone at –36 dBFS,
IMD = 101 dBFS
fIN1 = 300 MHz, fIN2 = 310 MHz, each tone at –7 dBFS,
IMD = 79 dBFS
Figure 11. FFT for Two-Tone Input Signal (–36 dBFS)
Figure 12. FFT for Two-Tone Input Signal (–7 dBFS)
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
50
100
150
200
250
0
50
100
150
200
250
Input Frequency (MHz)
Input Frequency (MHz)
D011
D012
fIN1 = 300 MHz, fIN2 = 310 MHz, each tone at –36 dBFS,
IMD3 = 102 dBFS
fIN1 = 470 MHz, fIN2 = 465 MHz, each tone at –10 dBFS,
IMD = 78 dBFS
Figure 13. FFT for Two-Tone Input Signal (–36 dBFS)
Figure 14. FFT for Two-Tone Input Signal (–10 dBFS)
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Typical Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency =
1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD =
1.15 V, and –1-dBFS differential input (unless otherwise noted)
-80
0
-85
-20
-90
-40
-95
-60
-100
-105
-110
-80
-100
-120
-35
-31
-27
-23
-19
-15
-11
-7
0
50
100
150
200
250
Each Tone Amplitude (dBFS)
D014
Input Frequency (MHz)
D013
fIN1 = 185 MHz, fIN2 = 190 MHz
fIN1 = 470 MHz, fIN2 = 465 MHz, each tone at –36 dBFS,
IMD3 = 104 dBFS
Figure 16. Intermodulation Distortion vs
Input Amplitude (185 MHz and 190 MHz)
Figure 15. FFT for Two-Tone Input Signal (–36 dBFS)
-75
-80
-50
-60
-85
-70
-90
-80
-95
-90
-100
-105
-110
-100
-110
-35
-31
-27
-23
-19
-15
-11
-7
-35
-30
-25
-20
-15
-10
Each Tone Amplitude (dBFS)
Each Tone Amplitude (dBFS)
D015
D016
fIN1 = 300 MHz, fIN2 = 310 MHz
fIN1 = 465 MHz, fIN2 = 470 MHz
Figure 17. Intermodulation Distortion vs
Input Amplitude (365 MHz and 370 MHz)
Figure 18. Intermodulation Distortion vs
Input Amplitude (465 MHz and 470 MHz)
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
AIN = -6 dBFS
AIN = -3 dBFS
AIN = -1 dBFS
fS/4 - fIN
fS/2 - fIN
3fS/4 - fIN
0
100
200
300
400
500
600
700
0
100
200
300
400
500
600
700
Input Frequency (MHz)
Input Frequency (MHz)
D017
D018
Figure 19. Spurious-Free Dynamic Range vs
Input Frequency
Figure 20. IL Spur vs Input Frequency
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Typical Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency =
1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD =
1.15 V, and –1-dBFS differential input (unless otherwise noted)
75
74.5
74
75
74
73
72
71
70
69
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.95 V
AVDD = 2 V
AIN = -6 dBFS
AIN = -3 dBFS
AIN = -1 dBFS
73.5
73
72.5
72
71.5
71
0
100
200
300
400
500
600
700
-40
-15
10
35
60
85
Input Frequency (MHz)
Temperature (°C)
D019
D020
fIN = 185 MHz
Figure 21. Signal-to-Noise Ratio vs Input Frequency
Figure 22. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
74
73.5
73
98
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.95 V
AVDD = 2 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.95 V
AVDD = 2 V
96
94
92
90
88
86
72.5
72
71.5
71
70.5
70
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D021
D022
fIN = 185 MHz
fIN = 300 MHz
Figure 23. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
Figure 24. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
85
84
83
82
81
80
79
75
74.5
74
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.95 V
AVDD = 2 V
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
DVDD = 1.95 V
DVDD = 2 V
73.5
73
72.5
72
71.5
71
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D023
D024
fIN = 300 MHz
fIN = 185 MHz
Figure 25. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
Figure 26. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
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Typical Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency =
1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD =
1.15 V, and –1-dBFS differential input (unless otherwise noted)
96
94
92
90
88
75
74.5
74
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
DVDD = 1.95 V
DVDD = 2 V
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
DVDD = 1.95 V
DVDD = 2 V
73.5
73
72.5
72
71.5
71
70.5
70
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D025
D026
fIN = 185 MHz
fIN = 300 MHz
Figure 27. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
Figure 28. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
75.5
75
86
84
82
80
78
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
DVDD = 1.95 V
DVDD = 2 V
AVDD3V = 2.85 V
AVDD3V = 3 V
AVDD3V = 3.1 V
AVDD3V = 3.2 V
AVDD3V = 3.3 V
AVDD3V = 3.4 V
AVDD3V = 3.5 V
AVDD3V = 3.6 V
74.5
74
73.5
73
72.5
72
71.5
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D027
D028
fIN = 300 MHz
fIN = 185 MHz
Figure 29. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
Figure 30. Signal-to-Noise Ratio vs
AVDD3V Supply and Temperature
74
73.5
73
96
94
92
90
88
AVDD3V = 2.85 V
AVDD3V = 3 V
AVDD3V = 3.1 V
AVDD3V = 3.2 V
AVDD3V = 3.3 V
AVDD3V = 3.4 V
AVDD3V = 3.5 V
AVDD3V = 3.6 V
AVDD3V = 2.85 V
AVDD3V = 3 V
AVDD3V = 3.1 V
AVDD3V = 3.2 V
AVDD3V = 3.3 V
AVDD3V = 3.4 V
AVDD3V = 3.5 V
AVDD3V = 3.6 V
72.5
72
71.5
71
70.5
70
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D030
D029
fIN = 300 MHz
fIN = 185 MHz
Figure 32. Signal-to-Noise Ratio vs
AVDD3V Supply and Temperature
Figure 31. Spurious-Free Dynamic Range vs
AVDD3V Supply and Temperature
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Typical Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency =
1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD =
1.15 V, and –1-dBFS differential input (unless otherwise noted)
84
83
82
81
80
83
80
77
74
71
68
65
62
59
AVDD3V = 2.85 V
AVDD3V = 3 V
AVDD3V = 3.1 V
AVDD3V = 3.2 V
AVDD3V = 3.3 V
AVDD3V = 3.4 V
AVDD3V = 3.5 V
AVDD3V = 3.6 V
Gain = 0 dB
Gain = 2 dB
Gain = 4 dB
Gain = 6 dB
Gain = 8 dB
Gain = 10 dB
Gain = 12 dB
-40
-15
10
35
60
85
0
80
160
240
320
400
480
Temperature (°C)
Input Frequency (MHz)
D031
D032
fIN = 300 MHz
Figure 33. Spurious-Free Dynamic Range vs
AVDD3V Supply and Temperature
Figure 34. Signal-to-Noise Ratio vs
Gain and Input Frequency
110
105
100
95
120
115
110
105
100
95
Gain = 0 dB
Gain = 2 dB
Gain = 4 dB
Gain = 6 dB
Gain = 8 dB
Gain = 10 dB
Gain = 12 dB
Gain = 0 dB
Gain = 2 dB
Gain = 4 dB
Gain = 6 dB
Gain = 8 dB
Gain = 10 dB
Gain = 12 dB
90
85
80
90
75
85
70
80
65
75
0
80
160
240
320
400
480
0
80
160
240
320
400
480
D034
Input Frequency (MHz)
Input Frequency (MHz)
D033
Figure 35. Spurious-Free Dynamic Range vs
Gain and Input Frequency
Figure 36. Second-Order Harmonic Distortion vs
Gain and Input Frequency
125
115
105
95
115
Gain = 0 dB
Gain = 2 dB
Gain = 4 dB
Gain = 6 dB
Gain = 8 dB
Gain = 10 dB
Gain = 12 dB
Gain = 0 dB
Gain = 2 dB
Gain = 4 dB
Gain = 6 dB
Gain = 8 dB
Gain = 10 dB
Gain = 12 dB
110
105
100
95
85
90
75
85
65
80
0
80
160
240
320
400
480
0
80
160
240
320
400
480
Input Frequency (MHz)
Input Frequency (MHz)
D035
D036
Figure 37. Third-Order Harmonic Distortion vs
Gain and Input Frequency
Figure 38. IL Spur vs Gain and Input Frequency
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Typical Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency =
1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD =
1.15 V, and –1-dBFS differential input (unless otherwise noted)
78
76
74
72
70
68
200
160
120
80
77
75.5
74
180
150
120
90
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
72.5
71
60
40
69.5
30
0
68
0
-70
-60
-50
-40
-30
-20
-10
0
-70
-60
-50
-40
-30
-20
-10
0
Amplitude (dBFS)
Amplitude (dBFS)
D037
D038
fIN = 185 MHz
fIN = 310 MHz
Figure 39. Performance vs Amplitude
Figure 40. Performance vs Amplitude
120
110
100
90
120
110
100
90
fS / 4 - fIN
fS / 2 - fIN
3fS / 4 - fIN
fS / 4 - fIN
fS / 2 - fIN
3fS / 4 - fIN
80
80
70
70
60
60
50
50
40
40
30
30
-70
-60
-50
-40
-30
-20
-10
0
-70
-60
-50
-40
-30
-20
-10
0
Amplitude (dBFS)
Amplitude (dBFS)
D039
D040
fIN = 185 MHz
fIN = 310 MHz
Figure 41. IL Spur vs Amplitude
Figure 42. IL Spur vs Amplitude
78
110
80
120
SNR
SNR
SFDR
SFDR
76
74
72
70
68
100
90
80
70
60
77
74
71
68
65
100
80
60
40
20
0.2
0.6
1
1.4
1.8
2.2
0.2
0.6
1
1.4
1.8
2.2
Differential Clock Amplitude (VPP
)
Differential Clock Amplitude (VPP)
D041
D042
fIN = 185 MHz
fIN = 310 MHz
Figure 43. Performance vs Differential Clock Amplitude
Figure 44. Performance vs Differential Clock Amplitude
20
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Typical Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency =
1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD =
1.15 V, and –1-dBFS differential input (unless otherwise noted)
76
75
74
73
72
71
100
95
90
85
80
75
75
74
73
72
71
70
90
85
80
75
70
65
SNR
SFDR
SNR
SFDR
35
40
45
50
55
60
65
30
35
40
45
50
55
60
Input Clock Duty Cycle (%)
Input Clock Duty Cycle (%)
D043
D044
fIN = 185 MHz
fIN = 300 MHz
Figure 45. Performance vs Input Clock Duty Cycle
Figure 46. Performance vs Input Clock Duty Cycle
-10
0
PSRR with 50-mVPP Signal on AVDD
PSRR with 50-mVPP Signal on AVDD3V
-20
-20
-40
-30
-40
-50
-60
-70
-60
-80
-100
-120
0
50
100
150
200
250
300
0
50
100
150
200
250
Frequency of Signal on Supply (MHz)
D046
Input Frequency (MHz)
D045
fIN = 185 MHz
AIN = –1 dBFS, SFDR = 84 dBc, SINAD = 70 dBFS,
fPSRR = 5 MHz, APSRR = 50 mVPP, fIN = 185 MHz,
amplitude: fIN – fPSRR = 85 dBc, fIN + fPSRR = 84 dBc
Figure 48. Power-Supply Rejection Ratio vs
Noise Signal Frequency
Figure 47. Power-Supply Rejection Ratio FFT for
AVDD Supply
-20
-25
-30
-35
-40
-45
-50
-55
-60
0
-20
-40
-60
-80
-100
-120
0
50
100
150
200
250
300
0
50
100
150
200
250
Frequency of Input Common-Mode Signal (MHz)
D048
Input Frequency (MHz)
D047
fIN = 185 MHz
AIN = –1 dBFS, SFDR = 78 dBc, SINAD = 71 dBFS,
fCMRR = 5 MHz, ACMRR = 50 mVPP, fIN = 185 MHz,
amplitude: fIN – fCMRR = 79 dBc, fIN + fCMRR = 80 dBc
Figure 50. Common-Mode Rejection Ratio vs
Common-Mode Signal Frequency
Figure 49. Common-Mode Rejection Ratio FFT
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Typical Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency =
1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD =
1.15 V, and –1-dBFS differential input (unless otherwise noted)
2
4
3.2
2.4
1.6
0.8
0
AVDD
IOVDD
DVDD
TOTAL POWER
0
AVDD3V
-2
-4
-6
-8
-10
0
100 200 300 400 500 600 700 800 900 1000
250
300
350
400
450
500
Input Frequency (MHz)
Output Sample Rate (MSPS)
D049
D050
Figure 51. Maximum-Supported Amplitude vs
Input Frequency
Figure 52. Power Consumption vs Sampling Speed
76
105
AIN = -3 dBFS
AIN = -1 dBFS
AIN = -3 dBFS
AIN = -1 dBFS
100
95
90
85
80
75
70
65
75
74
73
72
71
70
0
100
200
300
400
500
600
0
100
200
300
400
500
600
Input Frequency (MHz)
Input Frequency (MHz)
D051
D052
Figure 53. Signal-to-Noise Ratio vs
Figure 54. Spurious-Free Dynamic Range vs
Input Frequency (Output Sample Rate = 300 MSPS)
Input Frequency (Output Sample Rate = 300 MSPS)
105
76
AIN = -3 dBFS
AIN = -3 dBFS
AIN = -1 dBFS
AIN = -1 dBFS
100
75
95
90
85
80
75
70
65
74
73
72
71
70
0
100
200
300
400
500
600
0
100
200
300
400
500
600
Input Frequency (MHz)
Input Frequency (MHz)
D053
D054
Figure 55. Signal-to-Noise Ratio vs Input Frequency
(Output Sample Rate = 350 MSPS)
Figure 56. Spurious-Free Dynamic Range vs
Input Frequency (Output Sample Rate = 350 MSPS)
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Typical Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency =
1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD =
1.15 V, and –1-dBFS differential input (unless otherwise noted)
105
101
97
76
75
74
73
72
71
70
AIN = -3 dBFS
AIN = -1 dBFS
AIN = -3 dBFS
AIN = -1 dBFS
93
89
85
0
100
200
300
400
500
0
100
200
300
400
500
Input Frequency (MHz)
Input Frequency (MHz)
D055
D056
Figure 57. Signal-to-Noise Ratio vs Input Frequency
(Output Sample Rate = 400 MSPS)
Figure 58. Spurious-Free Dynamic Range vs
Input Frequency (Output Sample Rate = 400 MSPS)
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8 Detailed Description
8.1 Overview
The ADS54J69 is a low-power, wide-bandwidth, 16-bit, 500-MSPS, dual-channel, analog-to-digital converter
(ADC). The ADS54J69 employs four interleaving ADCs for each channel to achieve a noise floor of
–159 dBFS/Hz.
The ADS54J69 uses TI's proprietary interleaving and dither algorithms to achieve a clean spectrum with high
spurious-free dynamic range (SFDR). Built-in, half-band, decimate-by-2 filters further enhance the capability of
the ADS54J69 to deliver excellent signal-to-noise ratio (SNR) and SFDR over a wide range of frequencies.
Analog input buffers isolate the ADC driver from glitch energy generated from sampling process, thereby simplify
the driving network on-board.
The JESD204B interface reduces the number of interface lines with two-lane and four-lane options, allowing a
high system integration density. The JESD204B interface operates in subclass-1, enabling multi-chip
synchronization with the SYSREF input.
8.2 Functional Block Diagram
DDC Block
DA0P, DA0M,
DA1P, DA1M
Buffer
Interleaving
Correction,
Digital Gain
2
2
ADC
INAP, INAM
DA2P, DA2M,
DA3P, DA3M
PLL:
x20
x40
Divide-
by-4
CLKINP,
CLKINM
SYNC
SYSREFP,
SYSREFM
DDC Block
DB0P, DB0M,
DB1P, DB1M
Buffer
2
Interleaving
Correction,
Digital Gain
ADC
INBP, INBM
VCM
2
DB2P, DB2M,
DB3P, DB3M
FOVR
Control and SPI
Common-
Mode
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8.3 Feature Description
8.3.1 Analog Inputs
The ADS54J69 analog signal inputs are designed to be driven differentially. The analog input pins have internal
analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high
impedance input across a very wide frequency range to the external driving source that enables great flexibility in
the external analog filter design as well as excellent 50-Ω matching for RF applications. The buffer also helps
isolate the external driving circuit from the internal switching currents of the sampling circuit, resulting in a more
constant SFDR performance across input frequencies.
The common-mode voltage of the signal inputs is internally biased to VCM using 600-Ω resistors, allowing for ac-
coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM +
0.475 V) and (VCM – 0.475 V), resulting in a 1.9-VPP (default) differential input swing. The input sampling circuit
has a 3-dB bandwidth that extends up to 1.2 GHz. An equivalent analog input network diagram is shown in
Figure 59.
0.77 W
1 W
3.3 W
2 nH
0.6 W
150 fF
200 fF
3 pF
375 fF
375 fF
375 fF
375 fF
INP
40 W
500 fF
150 fF
0.77 W
1 W
3.3 W
600 W
150 fF
200 fF
3 pF
VCM
40 W
600 W
0.77 W
1 W
3.3 W
150 fF
200 fF
3 pF
2 nH
0.6 W
INM
40 W
500 fF
150 fF
0.77 W
1 W
3.3 W
150 fF
200 fF
3 pF
40 W
Figure 59. Analog Input Network
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Feature Description (continued)
The input bandwidth shown in Figure 60 is measured with respect to a 50-Ω differential input termination at the
ADC input pins.
0
-3
-6
-9
-12
-15
-18
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Input Frequency (MHz)
D057
Figure 60. Transfer Function versus Frequency
8.3.2 DDC Block
The ADS54J69 has an optional DDC block that can be enabled via an SPI register write. Each ADC channel is
followed by a DDC block consisting of a decimate-by-2, half-band, finite impulse response (FIR) filter with low-
pass and high-pass options programmable via the SPI interface.
8.3.2.1 Decimate-by-2 Filter
This decimation filter has 41 taps. The stop-band attenuation is approximately 90 dB and the pass-band flatness
is ±0.05 dB. Table 1 shows corner frequencies for the low-pass and high-pass filter options.
Table 1. Corner Frequencies for the Decimate-by-2 Filter
CORNERS (dB)
LOW PASS
0.202 × fS
0.210 × fS
0.215 × fS
0.227 × fS
HIGH PASS
0.298 × fS
0.290 × fS
0.285 × fS
0.273 × fS
–0.1
–0.5
–1
–3
Figure 61 and Figure 62 show the frequency response of the decimate-by-2 filter from dc to fS / 2.
5
-20
0.5
0
-0.5
-1
-45
-1.5
-2
-70
-95
-2.5
-3
-120
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Frequency Response
0
0.05
0.1
0.15
0.2
0.25
Frequency Response
D013
D014
Figure 61. Decimate-by-2 Filter Response
Figure 62. Decimate-by-2 Filter Response (Zoomed)
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8.3.3 SYSREF Signal
The SYSREF signal is a periodic signal that is sampled by the ADS54J69 device clock and used to align the
boundary of the local multi-frame clock inside the data converter. SYSREF is required to be a sub-harmonic of
the local multi-frame clock (LMFC) internal timing. To meet this requirement, the timing of SYSREF is dependent
on the device clock frequency and the LMFC frequency, as determined by the selected DDC decimation and
frames per multi-frame settings. The SYSREF signal is recommended be a low-frequency signal in the range of
1 MHz to 5 MHz in order to reduce coupling to the signal path both on the printed circuit board (PCB) as well as
internal in the device.
The external SYSREF signal must be a sub-harmonic of the internal LMFC clock, as shown in Equation 1 and
Table 2.
SYSREF = LMFC / 2N
where
•
N = 0, 1, 2, and so forth
(1)
Table 2. LMFC Clock Frequency
LMFS CONFIGURATION
DECIMATION
LMFC CLOCK(1)(2)
(fS / 4) / k
4222
2242
2X
2X
(fS / 4) / k
(1) K = Number of frames per multi-frame (JESD digital page 6900h, address 06h, bits 4-0).
(2) fS = sampling (device) clock frequency.
8.3.3.1 SYSREF Not Present (Subclass 0, 2)
A SYSREF pulse is required by the ADS54J69 to reset internal counters. If SYSREF is not present, as can be
the case in subclass 0 or 2, this pulse can be done by doing the following register writes shown in Table 3.
Table 3. Internally Pulsing SYSREF Twice Using Register Writes
ADDRESS (Hex)
0-011h
DATA (Hex)
80h
COMMENT
Set the master page
Enable manual SYSREF
Set SYSREF high
Set SYSREF low
0-054h
80h
0-053h
01h
0-053h
00h
0-053h
01h
Set SYSREF high
Set SYSREF low
0-053h
00h
8.3.4 Overrange Indication
The ADS54J69 provides a fast overrange indication that can be presented in the digital output data stream via an
SPI configuration. Alternatively, if not used, the SDOUT (pin 11) and PDN (pin 50) pins can be configured via the
SPI to output the fast overrange (FOVR) indicator.
When the FOVR indication is embedded in the output data stream, the FOVR replaces the LSB of the 16-bit data
stream going to the 8b/10b encoder, as shown in Figure 63.
16-Bit Data Output
D0/
OVR
D15
D14
D13 D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
16-Bit Data Going to 8b/10b Encoder
Figure 63. Overrange Indication in a Data Stream
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8.3.4.1 Fast OVR
The fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and is presented
after only 18 clock cycles + tPD (tPD of the gates and buffers is approximately 4 ns), thus enabling a quicker
reaction to an overrange event.
The input voltage level at which the overload is detected is referred to as the threshold. The threshold is
programmable using the FOVR THRESHOLD bits, as shown in Figure 64. The FOVR is triggered 18 clock cycles
+ tPD (tPD of the gates and buffers is approximately 4 ns) after the overload condition occurs.
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
0
32
64
96
128
160
192
224
255
Threshold Decimal Value
D055
Figure 64. Programming Fast OVR Thresholds
The input voltage level at which the fast OVR is triggered is defined by Equation 2:
Full-Scale × [Decimal Value of the FOVR Threshold Bits] / 255)
(2)
(3)
The default threshold is E3h (227d), corresponding to a threshold of –1 dBFS.
In terms of full-scale input, the fast OVR threshold can be calculated as Equation 3:
20log (FOVR Threshold / 255)
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8.3.5 Power-Down Mode
The ADS54J69 provides a highly-configurable power-down mode. Power-down can be enabled by using the
PDN pin or via SPI register writes.
A power-down mask can be configured that allows a trade-off between wake-up time and power consumption in
power-down mode. Two independent power-down masks can be configured: MASK 1 and MASK 2, as shown in
Table 4. See the master page registers in Table 10 for further details.
Table 4. Register Address for Power-Down Modes
REGISTER
ADDRESS
REGISTER DATA
COMMENT
A[7:0] (Hex)
MASTER PAGE (80h)
20
7
6
5
4
3
2
1
0
PDN ADC CHA
PDN BUFFER CHB
PDN ADC CHA
PDN BUFFER CHB
GLOBAL OVERRIDE
PDN ADC CHB
MASK 1
21
23
24
PDN BUFFER CHA
PDN BUFFER CHA
0
0
0
0
PDN ADC CHB
MASK 2
CONFIG
0
0
0
0
0
0
0
0
PDN MASK
26
0
PDN
PDN PIN
SEL
MASK
SYSREF
53
55
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PDN MASK
To save power, the device can be put in complete power-down by using the GLOBAL PDN register bit. However,
when the JESD link is required to be active during power-down, the ADC and analog buffer can be selectively
powered down by using the PDN ADC CHx and PDN BUFFER CHx register bits after enabling the PDN MASK
register bit. The PDN MASK SEL register bit can be used to select between MASK 1 or MASK 2. Table 5 shows
power consumption for different combinations of the GLOBAL PDN, PDN ADC CHx, and PDN BUFF CHx
register bits.
Table 5. Power Consumption in Different Power-Down Settings
TOTAL
IAVDD3V
(mA)
IAVDD
(mA)
IDVDD
(mA)
IIOVDD
(mA)
POWER
(W)
REGISTER BIT
Default
COMMENT
After reset, with a full-scale input signal to both
channels
346
3
354
6
188
21
512
127
2.66
0.2
GBL PDN = 1
The device is in a complete power-down state
GBL PDN = 0,
PDN ADC CHx = 1
(x = A or B)
The ADC of one channel is powered down
284
270
221
352
130
188
461
516
2.05
2.43
GBL PDN = 0,
PDN BUFF CHx = 1
(x = A or B)
The input buffer of one channel is powered down
GBL PDN = 0,
PDN ADC CHx = 1,
PDN BUFF CHx = 1
(x = A or B)
The ADC and input buffer of one channel are
powered down
206
64
220
84
129
67
465
389
1.82
0.93
GBL PDN = 0,
PDN ADC CHx = 1,
PDN BUFF CHx = 1
(x = A and B)
The ADC and input buffer of both channels are
powered down
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8.4 Device Functional Modes
8.4.1 Device Configuration
The ADS54J69 can be configured by using a serial programming interface, as described in the Serial Interface
section. In addition, the device has one dedicated parallel pin (PDN) for controlling the power-down mode.
The ADS54J69 supports a 24-bit (16-bit address, 8-bit data) SPI operation and uses paging (see the Register
Maps section) to access all register bits.
8.4.1.1 Serial Interface
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), and SDIN (serial interface data) pins, as shown in Figure 65.
Legends used in Figure 65 are explained in Table 6. Serially shifting bits into the device is enabled when SEN is
low. Serial data on SDIN are latched at every SCLK rising edge when SEN is active (low). The interface can
function with SCLK frequencies from 2 MHz down to very low speeds (of a few Hertz) and also with a non-50%
SCLK duty cycle.
Register Address[11:0]
Register Data[7:0]
SDIN
R/W
M
P
CH
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
tDH
D0
tSCLK
tDSU
SCLK
SEN
tSLOADS
tSLOADH
RESET
Figure 65. SPI Timing Diagram
Table 6. SPI Timing Diagram Legend
SPI BITS
DESCRIPTION
BIT SETTINGS
0 = SPI write
1 = SPI read back
R/W
Read/write bit
0 = Analog SPI bank (master and ADC pages)
M
P
SPI bank access
1 = JESD SPI bank (main digital, analog JESD, and digital
JESD pages)
0 = Page access
1 = Register access
JESD page selection bit
0 = Channel A
CH
SPI access for a specific channel of the JESD SPI bank
1 = Channel B
By default, both channels are being addressed.
A[11:0]
D[7:0]
SPI address bits
SPI data bits
—
—
30
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Table 7 shows the timing requirements for the serial interface signals in Figure 65.
Table 7. SPI Timing Requirements
MIN
TYP
MAX
UNIT
MHz
ns
fSCLK
tSLOADS
tSLOADH
tDSU
SCLK frequency (equal to 1 / tSCLK
SEN to SCLK setup time
SCLK to SEN hold time
SDIN setup time
)
> dc
100
100
100
100
2
ns
ns
tDH
SDIN hold time
ns
8.4.1.2 Serial Register Write: Analog Bank
The analog SPI bank contains two pages (the master and ADC page). The internal register of the ADS54J69
analog SPI bank can be programmed by:
1. Driving the SEN pin low.
2. Initiating a serial interface cycle specifying the page address of the register whose content must be written.
–
–
Master page: write address 0011h with 80h.
ADC page: write address 0011h with 0Fh.
3. Writing the register content, as shown in Figure 66. When a page is selected, multiple writes into the same
page can be done.
Register Address[11:0]
Register Data[7:0]
0
0
0
0
SDIN
SCLK
R/W
M
P
CH A11 A10
A9
A8
A7 A6 A5 A4
A3
A2
A1
A0
D7
D6
D5 D4 D3 D2
D1
D0
SEN
RESET
Figure 66. Serial Register Write Timing Diagram
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8.4.1.3 Serial Register Readout: Analog Bank
The content from one of the two analog banks can be read out by:
1. Driving the SEN pin low.
2. Selecting the page address of the register whose content must be read.
–
–
Master page: write address 0011h with 80h.
ADC page: write address 0011h with 0Fh.
3. Setting the R/W bit to 1 and writing the address to be read back.
4. Reading back the register content on the SDOUT pin, as shown in Figure 67. When a page is selected,
multiple read backs from the same page can be done.
Register Address[11:0]
Register Data[7:0] = XX
1
0
0
0
SDIN
SCLK
R/W
M
P
CH
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SEN
RESET
SDOUT
D7
D6
D5
D4
D3
D2
D1
D0
SDOUT[7:0]
Figure 67. Serial Register Read Timing Diagram
8.4.1.4 JESD Bank SPI Page Selection
The JESD SPI bank contains four pages (main digital, digital, and analog JESD pages). The individual pages can
be selected by:
1. Driving the SEN pin low.
2. Setting the M bit to 1 and specifying the page with two register writes. Note that the P bit must be set to 0, as
shown in Figure 68.
–
–
Write address 4003h with 00h (LSB byte of page address).
Write address 4004h with the MSB byte of the page address.
–
–
–
For the main digital page: write address 4004h with 68h.
For the digital JESD page: write address 4004h with 69h.
For the analog JESD page: write address 4004h with 6Ah.
Register Address[11:0]
Register Data[7:0]
D5 D4 D3 D2
0
1
0
0
SDIN
R/W
M
P
CH A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D1
D0
SCLK
SEN
RESET
Figure 68. SPI Page Selection
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8.4.1.5 Serial Register Write: JESD Bank
The ADS54J69 is a dual-channel device and the JESD204B portion is configured individually for each channel by
using the CH bit. Note that the P bit must be set to 1 for register writes.
1. Drive the SEN pin low.
2. Select the JESD bank page. Note that the M bit = 1 and the P bit = 0.
–
–
–
–
–
Write address 4003h with 00h.
If separate control for both channels is desired, write address 4005h with 01h.
For the main digital page: write address 4004h with 68h.
For the digital JESD page: write address 4004h with 69h.
For the analog JESD page: write address 4004h with 6Ah.
3. Set the M and P bits to 1, select channel A (CH = 0) or channel B (CH = 1), and write the register content as
shown in Figure 69. When a page is selected, multiple writes into the same page can be done.
Register Address[11:0]
Register Data[7:0]
0
1
1
0
SDIN
SCLK
R/W
M
P
CH A11 A10
A9
A8
A7 A6 A5 A4
A3
A2
A1
A0
D7
D6
D5 D4 D3 D2
D1
D0
SEN
RESET
Figure 69. JESD Serial Register Write Timing Diagram
8.4.1.5.1 Individual Channel Programming
By default, register writes are applied to both channels. To enable individual channel writes, write address 4005h
with 01h (default is 00h).
8.4.1.6 Serial Register Readout: JESD Bank
The content from one of the pages of the JESD bank can be read out by:
1. Driving the SEN pin low.
2. Select the JESD bank page. Note that the M bit = 1 and the P bit = 0.
–
–
–
–
–
Write address 4003h with 00h.
If separate control for both channels is desired, write address 4005h with 01h.
For the main digital page: write address 4004h with 68h.
For the digital JESD page: write address 4004h with 69h.
For the analog JESD page: write address 4004h with 6Ah.
3. Setting the R/W, M, and P bits to 1, selecting channel A or channel B, and writing the address to be read
back.
4. Reading back the register content on the SDOUT pin; see Figure 70. When a page is selected, multiple read
backs from the same page can be done.
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Register Address[11:0]
A7 A6 A5 A4
Register Data[7:0] = XX
D5 D4 D3 D2
1
1
1
0
SDIN
SCLK
R/W
M
P
CH A11 A10 A9
A8
A3
A2
A1
A0
D7
D6
D1
D0
SEN
RESET
SDOUT
D7
D6
D5
D4
D3
D2
D1
D0
SDOUT[7:0]
Figure 70. JESD Serial Register Read Timing Diagram
8.4.2 JESD204B Interface
The ADS54J69 supports device subclass 1 with a maximum output data rate of 10.0 Gbps for each serial
transmitter.
An external SYSREF signal is used to align all internal clock phases and the local multi-frame clock to a specific
sampling clock edge, allowing synchronization of multiple devices in a system and minimizing timing and
alignment uncertainty. The SYNC input is used to control the JESD204B SERDES blocks.
Depending on the ADC output data rate, the JESD204B output interface can be operated with either two or four
active lanes (out of total 8 lanes), as shown in Figure 71. The JESD204B setup and configuration of the frame
assembly parameters is controlled via the SPI interface.
SYSREF
SYNC
JESD204B
DA[3:0]
INA
INB
JESD204B
JESD204B
JESD204B
DB[3:0]
Sample Clock
Figure 71. ADS54J69 Block Diagram
34
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The JESD204B transmitter block shown in Figure 72 consists of the transport layer, the data scrambler, and the
link layer. The transport layer maps the ADC output data into the selected JESD204B frame data format. The link
layer performs the 8b/10b data encoding as well as the synchronization and initial lane alignment using the
SYNC input signal. Optionally, data from the transport layer can be scrambled.
JESD204B Block
Transport Layer
Link Layer
8b, 10b
Encoding
Frame Data
Mapping
Scrambler
1 + x14 + x15
D[3:0]
Comma Characters,
Initial Lane Alignment
SYNC
Figure 72. JESD204B Transmitter Block
8.4.2.1 JESD204B Initial Lane Alignment (ILA)
The initial lane alignment process is started when the receiving device de-asserts the SYNC signal, as shown in
Figure 73. When a logic low is detected on the SYNC input pin, the ADS54J69 starts transmitting comma (K28.5)
characters to establish a code group synchronization.
When synchronization is complete, the receiving device asserts the SYNC signal and the ADS54J69 starts the
initial lane alignment sequence with the next local multi-frame clock boundary. The ADS54J69 transmits four
multi-frames, each containing K frames (K is SPI programmable). Each of the multi-frames contains the frame
start and end symbols and the second multi-frame also contains the JESD204 link configuration data.
SYSREF
LMFC Clock
LMFC Boundary
Multi
Frame
SYNC
Transmit Data
xxx
K28.5
Code Group
K28.5
Initial Lane
ILA
ILA
DATA
DATA
Data Transmission
Synchronization
Alignment
Figure 73. Lane Alignment Sequence
8.4.2.2 JESD204B Test Patterns
There are three different test patterns available in the transport layer of the JESD204B interface. The ADS54J69
supports a clock output, encoded, and a PRBS (215 – 1) pattern. These test patterns can be enabled via an SPI
register write and are located in the JESD digital page of the JESD bank.
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8.4.2.3 JESD204B Frame
The JESD204B standard defines the following parameters:
•
•
•
•
L is the number of lanes per link
M is the number of converters per device
F is the number of octets per frame clock period, per lane
S is the number of samples per frame per converter
8.4.2.4 JESD204B Frame Assembly with Decimation
Table 8 lists the available JESD204B formats and interface rate at maximum sampling frequency. At lower
sampling frequencies, interface rates scale down proportionally.
Figure 74 shows the detailed frame assembly for the decimated output.
Table 8. Interface Rates with Decimation Filter
MAX ADC
OUTPUT RATE
(MSPS)
JESD MODE
REGISTER BIT
JESD PLL MODE
SETTING
MAX fSERDES
(Gbps)
L
M
F
S
DECIMATION
4
2
2
2
2
4
2
2
001
010
20x
40x
2X
2X
500
500
5.0
10.0
Channel Output Sample Clock
(Chip Clock / 2 = 500 MSPS)
Frame Clock
(250 MHz)
One Frame Period
One Frame Period
PIN
LMFS = 4222, 2X DECIMATION
LMFS = 2242, 2X DECIMATION
DA0
DA1
DA2
DA3
DB0
DB1
DB2
DB3
A1[15:8]
A0[15:8]
A1[7:0]
A0[7:0]
A3[15:8]
A2[15:8]
A3[7:0]
A2[7:0]
Lane DA0 is Unused
A0[15:8] A0[7:0] A1[15:8] A1[7:0]
Lane DA2 is Unused
Lane DA2 is Unused
Lane DA3 is Unused
Lane DA3 is Unused
Lane DB0 is Unused
B1[15:8]
B0[15:8]
B1[7:0]
B0[7:0]
B3[15:8]
B3[7:0]
B2[7:0]
B2[15:8]
B0[15:8] B0[7:0] B1[15:8] B1[7:0]
Lane DB2 is Unused
Lane DB2 is Unused
Lane DB3 is Unused
Lane DB3 is Unused
Figure 74. Frame Assembly with Decimation Filter
36
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Note that after power-up, the JESD output bus must be reordered to obtain correct link parameters in the ILA
sequence. Table 9 shows the required register writes to reorder the JESD output bus.
Table 9. Configuring LMFS for the JESD Link
JESD MODE
REGISTER BIT
(In JESD
JESD PLL MODE
(In JESD
Analog Page)
DA_BUS_REORDER
REGISTER BIT
(In JESD Digital Page)
DB_BUS_REORDER
REGISTER BIT
(In JESD Digital Page)
REGISTER 52
(In Main
Digital Page)
REGISTER 72
(In Main
Digital Page)
L
M
F
S
DECIMATION
Digital Page)
4
2
2
2
2
4
2
2
2X
2X
00h
10h
01h
02h
0Ah
0Ah
0Ah
0Ah
80h
80h
08h
08h
8.4.2.4.1 JESD Transmitter Interface
Each of the 10.0-Gbps SERDES JESD transmitter outputs requires ac-coupling between the transmitter and
receiver. The differential pair must be terminated with 100-Ω resistors as close to the receiving device as
possible to avoid unwanted reflections and signal degradation, as shown in Figure 75.
0.1 mF
DA[3:0]P,
DB[3:0]P
Rt = ZO
Transmission Line, Zo
VCM
Receiver
Rt = ZO
DA[3:0]M,
DB[3:0]M
0.1 mF
Figure 75. Output Connection to Receiver
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8.4.2.4.2 Eye Diagrams
Figure 76 to Figure 79 show the serial output eye diagrams of the ADS54J69 at 5.0 Gbps and 10 Gbps with
default and increased output voltage swing against the JESD204B mask.
Figure 76. Eye Diagram at 5-Gbps Bit Rate with
Default Output Swing
Figure 77. Eye Diagram at 5-Gbps Bit Rate with
Increased Output Swing
Figure 79. Eye Diagram at 10-Gbps Bit Rate with
Increased Output Swing
Figure 78. Eye Diagram at 10-Gbps Bit Rate with
Default Output Swing
38
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8.5 Register Maps
Figure 80 shows a conceptual diagram of the serial registers.
Initiate an SPI Cycle
R/W, M, P, CH, Bits Decoder(1)
M = 0
M = 1
Analog Bank
JESD Bank
General Register
General Register
(Address 005h,
Keep M = 1, P = 0)
JESD Bank Page Selection
(Address 003h and Address 004h,
Keep M = 1, P = 0)
Unused Registers
(Address 01h, Address 02h.
Keep M = 1, P = 0)
Analog Bank Page Selection
(Address 00h,
(Address 011h, Keep M = 0, P = 0)
Keep M = 0, P = 0)
Value 80h
Addr 5Fh
Value 0Fh
Value 6800h
Value 6900h
Value 6A00h
Addr 0h
Addr 20h
Addr 0h
Addr 12h
Main
Digital Page
JESD
ADC Page
(Fast OVR)
JESD
Digital Page
Master Page
(PDN, OVR,
DC Coupling)
Analog Page
(PLL Configuration,
Output Swing,
(Nyquist Zone,
Gain,
OVR, Filter)
Keep
M = 0, P = 0
(JESD
Configuration)
Pre-Emphasis)
Keep
M = 0, P = 0
Keep M = 1,
P = 1
Keep M = 1,
P = 1
Keep M = 1,
P = 1
Addr F7h
Addr 59h
Addr 32h
Addr 1Bh
Figure 80. Serial Interface Registers
8.5.1 Detailed Register Info
The ADS54J69 contains two main SPI banks: the analog SPI bank and the digital SPI bank. The analog SPI bank gives access to the ADC analog blocks
and the JESD SPI bank controls the digital features and anything related to the JESD204B serial interface. The analog SPI bank is divided into two
pages (master and ADC) and the JESD SPI bank is divided into three pages (main digital, JESD digital, and JESD analog). Table 10 lists a register map
for the ADS54J69.
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Register Maps (continued)
Table 10. Register Map
REGISTER
ADDRESS
REGISTER DATA
4
A[11:0] (Hex)
7
6
5
3
2
1
0
GENERAL REGISTERS
0
3
4
RESET
0
0
0
0
0
0
RESET
JESD BANK PAGE SEL[7:0]
JESD BANK PAGE SEL[15:8]
DISABLE
BROADCAST
5
0
0
0
0
0
0
0
11
ANALOG BANK PAGE SEL
MASTER PAGE (80h)
20
21
23
24
PDN ADC CHA
PDN ADC CHA
PDN ADC CHB
PDN ADC CHB
PDN BUFFER CHB
PDN BUFFER CHA
0
0
0
0
PDN BUFFER CHB
PDN BUFFER CHA
0
0
0
0
0
0
0
0
OVERRIDE PDN
PIN
26
4F
53
GLOBAL PDN
PDN MASK SEL
0
0
0
0
EN INPUT DC
COUPLING
0
0
0
0
0
0
0
0
0
0
0
0
0
EN SYSREF DC
COUPLING
MASK SYSREF
0
SET SYSREF
0
ENABLE MANUAL
SYSREF
54
0
55
0
0
0
0
PDN MASK
0
0
0
0
0
0
0
0
0
59
ADC PAGE (0Fh)
5F
FOVR CHB
ALWAYS WRITE 1
FOVR THRESHOLD PROG
MAIN DIGITAL PAGE (6800h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PULSE RESET
41
42
43
44
4B
0
0
0
0
0
DECFIL MODE[3]
0
DECFIL MODE[2:0]
NYQUIST ZONE
0
0
0
0
0
0
0
FORMAT SEL
0
DIGITAL GAIN
0
0
FORMAT EN
0
0
MAIN DIGITAL PAGE (6800h) (continued)
40
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Register Maps (continued)
Table 10. Register Map (continued)
REGISTER
ADDRESS
REGISTER DATA
A[11:0] (Hex)
7
6
0
0
0
0
0
0
0
5
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
3
2
0
0
0
0
0
0
0
1
0
0
0
0
0
0
4D
4E
52
0
DEC MODE EN
0
CTRL NYQUIST
0
0
ALWAYS WRITE 1
0
DIG GAIN EN
0
72
0
0
0
0
ALWAYS WRITE 1
AB
AD
F7
0
0
0
LSB SEL EN
LSB SELECT
0
DIG RESET
JESD DIGITAL PAGE (6900h)
0
1
CTRL K
0
0
0
TESTMODE EN
0
FLIP ADC DATA
0
LANE ALIGN
0
FRAME ALIGN
JESD MODE
TX LINK DIS
SYNC REG
SYNC REG EN
LINK LAYER
RPAT
LMFC MASK
RESET
2
3
LINK LAYER TESTMODE
0
0
FORCE LMFC
COUNT
LMFC COUNT INIT
0
RELEASE ILANE SEQ
5
6
SCRAMBLE EN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FRAMES PER MULTI FRAME (K)
7
0
SUBCLASS
0
31
32
DA_BUS_REORDER[7:0]
DB_BUS_REORDER[7:0]
JESD ANALOG PAGE (6A00h)
12
13
14
15
SEL EMP LANE 1
SEL EMP LANE 0
SEL EMP LANE 2
SEL EMP LANE 3
0
0
0
0
0
0
0
0
16
1A
1B
0
0
0
0
0
0
0
0
0
0
0
0
JESD PLL MODE
0
0
FOVR CHA
0
0
0
JESD SWING
FOVR CHA EN
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8.5.2 Example Register Writes
This section provides three different example register writes. Table 11 describes a global power-down register
write, Table 12 describes the register writes to enable the high-pass filter in the default four-lane output mode
(LMFS = 4222), and Table 13 describes the register writes to enable the high-pass filter in the two-lane output
mode (LMFS = 2242).
Note that by default after reset, the low-pass filter and four-lane output mode are enabled and register writes are
applied to both channels together.
Table 11. Global Power-Down
ADDRESS (Hex)
DATA (Hex)
80h
COMMENT
11h
26h
Set the master page
C0h
Set the global power-down
Table 12. Selecting 2X Decimation with Four-Lane Mode (LMFS = 4222)
ADDRESS (Hex)
4-004h
DATA (Hex)
68h
COMMENT
Select the main digital page (6800h)
4-003h
00h
6-041h
16h
Set decimate-by-2 (high-pass filter)
Enable decimation filter control
6-04Dh
6-072h
08h
08h
Enable the ALWAYS WRITE 1 register bit (for output bus reorder)
Enable the ALWAYS WRITE 1 register bit (for output bus reorder)
6-052h
80h
6-000h
01h
Pulse the PULSE RESET register bit so that registers programmed in the main
digital page (6800h) become effective.
6-000h
00h
4-004h
69h
Select the JESD digital page (6900h)
4-003h
00h
6-031h
0Ah
Output bus reorder for channel A
6-032h
0Ah
Output bus reorder for channel B
6-001h
01h
JESD filter mode + 4-lanes output selection
Table 13. Selecting 2X Decimation with Two-Lane Mode (LMFS = 2242)
ADDRESS (Hex)
4-004h
4-003h
6-041h
6-04Dh
6-072h
6-052h
6-000h
6-000h
4-004h
4-003h
6-031h
6-032h
6-001h
4-004h
4-003h
6-016h
DATA (Hex)
68h
COMMENT
Select the main digital page (6800h)
00h
16h
Set decimate-by-2 (high-pass filter)
Enable decimation filter control
08h
08h
Set the ALWAYS WRITE 1 register bit (for output bus reorder)
Set the ALWAYS WRITE 1 register bit (for output bus reorder)
80h
01h
Pulse the PULSE RESET register bit so that registers programmed in the main
digital page (6800h) become effective.
00h
69h
Select the JESD digital page (6900h)
00h
0Ah
0Ah
02h
Output bus reorder for channel A
Output bus reorder for channel B
JESD filter mode + 2-lanes output selection
6Ah
00h
Select the JESD analog page (6A00h)
02h
JESD PLL MODE 40x selection in the analog page
42
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8.5.3 Register Descriptions
8.5.3.1 General Registers
8.5.3.1.1 Register 0h (address = 0h)
Figure 81. Register 0h
7
6
0
5
0
4
0
3
0
2
0
1
0
0
RESET
W-0h
RESET
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: W = Write only; -n = value after reset
Table 14. Register 0h Field Descriptions
Bit
Field
Type
Reset
Description
7
RESET
W
0h
0 = Normal operation
1 = Internal software reset, clears back to 0
6-1
0
0
W
W
0h
0h
Must write 0
RESET
0 = Normal operation
1 = Internal software reset, clears back to 0
8.5.3.1.2 Register 3h (address = 3h)
Figure 82. Register 3h
7
6
5
4
3
2
1
0
JESD BANK PAGE SEL[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 15. Register 3h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
JESD BANK PAGE SEL[7:0]
R/W
0h
Program these bits to access the desired page in the JESD
bank.
6800h = Main digital page selected
6900h = JESD digital page selected
6A00h = JESD analog page selected
8.5.3.1.3 Register 4h (address = 4h)
Figure 83. Register 4h
7
6
5
4
3
2
1
0
JESD BANK PAGE SEL[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 16. Register 4h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
JESD BANK PAGE SEL[15:8]
R/W
0h
Program these bits to access the desired page in the JESD
bank.
6800h = Main digital page selected
6900h = JESD digital page selected
6A00h = JESD analog page selected
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8.5.3.1.4 Register 5h (address = 5h)
Figure 84. Register 5h
7
0
6
0
5
0
4
3
0
2
1
0
0
0
0
DISABLE BROADCAST
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 17. Register 5h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
DISABLE BROADCAST
R/W
0h
0 = Normal operation; channel A and B are programmed as a pair
1 = Channel A and B can be individually programmed based on the
CH bit (keep CH = 0 for channel A, CH = 1 for channel B).
8.5.3.1.5 Register 11h (address = 11h)
Figure 85. Register 11h
7
6
5
4
3
2
1
0
ANALOG PAGE SELECTION
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 18. Register 11h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
ANALOG BANK PAGE SEL
R/W
0h
Program these bits to access the desired page in the analog bank.
Master page = 80h
ADC page = 0Fh
8.5.3.2 Master Page (080h) Registers
8.5.3.2.1 Register 20h (address = 20h), Master Page (080h)
Figure 86. Register 20h
7
6
5
4
3
2
1
0
PDN ADC CHA
R/W-0h
PDN ADC CHB
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 19. Registers 20h Field Descriptions
Bit
7-4
3-0
Field
Type
R/W
R/W
Reset
0h
Description
PDN ADC CHA
PDN ADC CHB
There are two power-down masks that are controlled via the
PDN mask register bit in address 55h. Power-down mask 1 or
mask 2 are selected via register bit 5 in address 26h.
Power-down mask 1: addresses 20h and 21h.
Power-down mask 2: addresses 23h and 24h.
0Fh = Power-down CHB only.
0h
F0h = Power-down CHA only.
FFh = Power-down both.
44
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8.5.3.2.2 Register 21h (address = 21h), Master Page (080h)
Figure 87. Register 21h
7
6
5
4
3
0
2
0
1
0
0
0
PDN BUFFER CHB
R/W-0h
PDN BUFFER CHA
R/W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 20. Register 21h Field Descriptions
Bit
7-6
5-4
Field
Type
R/W
R/W
Reset
0h
Description
PDN BUFFER CHB
PDN BUFFER CHA
There are two power-down masks that are controlled via the
PDN mask register bit in address 55h. Power-down mask 1 or
mask 2 are selected via register address 26h, bit 5.
Power-down mask 1: addresses 20h and 21h.
Power-down mask 2: addresses 23h and 24h.
There are two buffers per channel. One buffer drives two ADC
cores.
0h
PDN BUFFER CHx:
00 = Both buffers of a channel are active.
11 = Both buffers are powered down.
01–10 = Do not use.
3-0
0
W
0h
Must write 0
8.5.3.2.3 Register 23h (address = 23h), Master Page (080h)
Figure 88. Register 23h
7
6
5
4
3
2
1
0
PDN ADC CHA
R/W-0h
PDN ADC CHB
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 21. Register 23h Field Descriptions
Bit
7-4
3-0
Field
Type
R/W
R/W
Reset
0h
Description
PDN ADC CHA
PDN ADC CHB
There are two power-down masks that are controlled via the
PDN mask register bit in address 55h. Power-down mask 1 or
mask 2 are selected via register address 26h, bit 5.
Power-down mask 1: addresses 20h and 21h.
Power-down mask 2: addresses 23h and 24h.
0Fh = Power-down CHB only.
0h
F0h = Power-down CHA only.
FFh = Power-down both.
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8.5.3.2.4 Register 24h (address = 24h), Master Page (080h)
Figure 89. Register 24h
7
6
5
4
3
0
2
0
1
0
0
0
PDN BUFFER CHB
R/W-0h
PDN BUFFER CHA
R/W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 22. Register 24h Field Descriptions
Bit
7-6
5-4
Field
Type
R/W
R/W
Reset
0h
Description
PDN BUFFER CHB
PDN BUFFER CHA
There are two power-down masks that are controlled via the
PDN mask register bit in address 55h. Power-down mask 1 or
mask 2 are selected via register address 26h, bit 5.
Power-down mask 1: addresses 20h and 21h.
Power-down mask 2: addresses 23h and 24h.
Power-down mask 2: addresses 23h and 24h.
There are two buffers per channel. One buffer drives two ADC
cores.
0h
PDN BUFFER CHx:
00 = Both buffers of a channel are active.
11 = Both buffers are powered down.
01–10 = Do not use.
3-0
0
W
0h
Must write 0
46
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8.5.3.2.5 Register 26h (address = 26h), Master Page (080h)
Figure 90. Register 26h
7
6
5
4
0
3
0
2
0
1
0
0
0
OVERRIDE
PDN PIN
PDN MASK
SEL
GLOBAL PDN
R/W-0h
R/W-0h
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 23. Register 26h Field Descriptions
Bit
Field
Type
Reset
Description
7
GLOBAL PDN
R/W
0h
Bit 6 (OVERRIDE PDN PIN) must be set before this bit can be
programmed.
0 = Normal operation
1 = Global power-down via the SPI
6
5
OVERRIDE PDN PIN
R/W
R/W
W
0h
0h
0h
This bit ignores the power-down pin control.
0 = Normal operation
1 = Ignores inputs on the power-down pin
PDN MASK SEL
0
This bit selects power-down mask 1 or mask 2.
0 = Power-down mask 1
1 = Power-down mask 2
4-0
Must write 0
8.5.3.2.6 Register 39h (address = 39h), Master Page (080h)
Figure 91. Register 39h
7
6
5
0
4
3
2
0
1
0
0
0
PERF MODE[1:0]
R/W-0h
0
0
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 24. Register 39h Field Descriptions
Bit
Field
Type
Reset
Description
7-6
PERF MODE[1:0]
R/W
0h
Set all four PERF MODE[3:0] bits together.
Bits are located in register address 39h, 3Ah, and 56h in the
master page.
5-0
0
W
0h
Must write 0
8.5.3.2.7 Register 3Ah (address = 3Ah), Master Page (080h)
Figure 92. Register 3Ah
7
0
6
5
0
4
3
2
0
1
0
0
0
PERF MODE[2]
R/W-0h
0
0
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 25. Register 3Ah Field Descriptions
Bit
7
Field
Type
W
Reset
0h
Description
0
Must write 0
6
PERF MODE[2]
R/W
0h
Set all four PERF MODE[3:0] bits together.
Bits are located in register address 39h, 3Ah, and 56h in the
master page.
5-0
0
W
0h
Must write 0
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8.5.3.2.8 Register 4Fh (address = 4Fh), Master Page (080h)
Figure 93. Register 4Fh
7
0
6
0
5
0
4
3
2
1
0
0
0
0
0
EN INPUT DC COUPLING
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 26. Register 4Fh Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
EN INPUT DC COUPLING
R/W
0h
Enables dc-coupling between the analog inputs and driver by
changing the internal biasing resistor between the analog inputs
and VCM from 600 Ω to 5 kΩ.
0 = Disable dc-coupling support
1 = Enable dc-coupling support
8.5.3.2.9 Register 53h (address = 53h), Master Page (080h)
Figure 94. Register 53h
7
0
6
5
0
4
3
2
0
1
0
MASK
SYSREF
EN SYSREF
DC COUPLING
0
0
SET SYSREF
R/W-0h
W-0h
R/W-0h
W-0h
W-0h
W-0h
W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 27. Register 53h Field Descriptions
Bit
7
Field
Type
W
Reset
0h
Description
0
Must write 0
6
MASK SYSREF
R/W
0h
0 = Normal operation
1 = Ignores the SYSREF input
5-2
1
0
W
0h
0h
Must write 0
EN SYSREF DC COUPLING
R/W
Enables a higher common-mode voltage input on the SYSREF
signal (up to 1.6 V).
0 = Normal operation
1 = Enables a higher SYSREF common-mode voltage support
0
SET SYSREF
R/W
0h
0 = Set SYSREF low
1 = Set SYSREF high
8.5.3.2.10 Register 54h (address = 54h), Master Page (080h)
Figure 95. Register 54h
7
6
0
5
0
4
3
2
0
1
0
0
0
ENABLE
MANUAL
SYSREF
0
0
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 28. Register 54h Field Descriptions
Bit
7
Field
Type
R/W
W
Reset
0h
Description
ENABLE MANUAL SYSREF
0
This bit enables manual SYSREF
Must write 0
6-0
0h
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8.5.3.2.11 Register 55h (address = 55h), Master Page (080h)
Figure 96. Register 55h
7
0
6
0
5
0
4
3
0
2
0
1
0
0
0
PDN MASK
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 29. Register 55h Field Descriptions
Bit
7-5
4
Field
Type
W
Reset
0h
Description
0
Must write 0
PDN MASK
R/W
0h
This bit enables power-down via a register bit.
0 = Normal operation
1 = Power-down is enabled by powering down internal blocks as
specified in the selected power-down mask
3-0
0
W
0h
Must write 0
8.5.3.2.12 Register 56h (address = 56h), Master Page (080h)
Figure 97. Register 56h
7
0
6
0
5
0
4
3
2
1
0
0
0
0
0
PERF MODE[3]
W-0h
W-0h
W-0h
W-0h
R/W-0h
W-0h
W-0h
W-0h
LEGEND: W = Write only; -n = value after reset
Table 30. Register 56h Field Descriptions
Bit
7-3
2
Field
Type
W
Reset
0h
Description
0
Must write 0
PERF MODE[3]
W
0h
Set all four PERF MODE[3:0] bits together.
Bits are located in register address 39h, 3Ah, and 56h in the
master page.
1-0
0
W
0h
Must write 0
8.5.3.2.13 Register 59h (address = 59h), Master Page (080h)
Figure 98. Register 59h
7
6
0
5
4
0
3
0
2
0
1
0
0
0
FOVR CHB
W-0h
ALWAYS WRITE 1
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 31. Register 59h Field Descriptions
Bit
Field
Type
Reset
Description
7
FOVR CHB
W
0h
Outputs the FOVR signal for channel B on the SDOUT pin.
0 = Normal operation
1 = Outputs FOVR on the SDOUT pin
6
5
0
W
0h
0h
0h
Must write 0
Must write 1
Must write 0
ALWAYS WRITE 1
0
R/W
W
4-0
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8.5.3.3 ADC Page (0Fh) Registers
8.5.3.3.1 Registers 5F (addresses = 5F), ADC Page (0Fh)
Figure 99. Register 5F
7
6
5
4
3
2
1
0
FOVR THRESHOLD PROG
R/W-E3h
LEGEND: R/W = Read/Write; -n = value after reset
Table 32. Registers 5F Field Descriptions
Bit
Field
Type
Reset
Description
7-0
FOVR THRESHOLD PROG
R/W
E3h
Program the fast OVR thresholds together for channel A and B,
as described in the Overrange Indication section.
50
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8.5.3.4 Main Digital Page (6800h) Registers
8.5.3.4.1 Register 0h (address = 0h), Main Digital Page (6800h)
Figure 100. Register 0h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
PULSE RESET
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 33. Register 0h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
PULSE RESET
R/W
0h
Must be pulsed after power-up or after configuring registers in
the main digital page of the JESD bank. Any register bits in the
main digital page (6800h) take effect only after this bit is pulsed;
see the Start-Up Sequence section for the correct sequence.
0 = Normal operation
0 → 1 → 0 = Bit is pulsed
8.5.3.4.2 Register 41h (address = 41h), Main Digital Page (6800h)
Figure 101. Register 41h
7
0
6
0
5
0
4
3
2
1
0
DECFIL MODE[3]
R/W-0h
0
DECFIL MODE[2:0]
R/W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 34. Register 41h Field Descriptions
Bit
7-5
4
Field
Type
W
Reset
0h
Description
Must write 0
Refer Table 35.
Must write 0
0
DECFIL MODE[3]
0
R/W
W
0h
3
0h
2-0
DECFIL MODE[2:0]
R/W
2h
These bits select the decimation filter mode. Table 35 lists the bit
settings.
Register bit DEC MODE EN (register 4Dh, bit 3) must also be
enabled.
Table 35. DECFIL MODE Bit Settings
DEC MODE EN (REGISTER 4Dh, BIT 3)
BITS (4, 2-0)
XXXX
FILTER MODE
DECIMATION
0
1
1
1
Low-pass filter
Low-pass filter
High-pass filter
Do not use
2X
2X
2X
—
1010
1110
Others
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8.5.3.4.3 Register 42h (address = 42h), Main Digital Page (6800h)
Figure 102. Register 42h
7
0
6
0
5
0
4
0
3
0
2
1
0
NYQUIST ZONE
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 36. Register 42h Field Descriptions
Bit
7-3
2-0
Field
Type
W
Reset
0h
Description
0
Must write 0
NYQUIST ZONE
R/W
0h
The Nyquist zone must be selected for proper interleaving
correction. Here Nyquist refers to Device Clock/2. For 1 GSPS
Device clock, Nyquist frequency is 500 MHz. Also set register bit
CTRL NYQUIST (4Eh, bit 7).
000 = 1st Nyquist zone (0 MHz to 500 MHz)
001 = 2nd Nyquist zone (500 MHz to 1000 MHz)
010 = 3rd Nyquist zone (1000 MHz to 1500 MHz)
All others = Not used
8.5.3.4.4 Register 43h (address = 43h), Main Digital Page (6800h)
Figure 103. Register 43h
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
FORMAT SEL
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 37. Register 43h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
FORMAT SEL
R/W
0h
Changes the output format. Set the FORMAT EN bit (register
4Bh, bit 5) to enable control using this bit.
0 = Twos complement
1 = Offset binary
8.5.3.4.5 Register 44h (address = 44h), Main Digital Page (6800h)
Figure 104. Register 44h
7
0
6
5
4
3
2
1
0
DIGITAL GAIN
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 38. Register 44h Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
0h
Description
0
Must write 0
6-0
DIGITAL GAIN
0h
Digital gain setting. Digital gain must be enabled (register 52h,
bit 0).
Gain in dB = 20log (digital gain / 32).
7Fh = 127, equals digital gain of 9.5 dB.
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8.5.3.4.6 Register 4Bh (address = 4Bh), Main Digital Page (6800h)
Figure 105. Register 4Bh
7
0
6
0
5
4
0
3
0
2
0
1
0
0
0
FORMAT EN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 39. Register 4Bh Field Descriptions
Bit
7-6
5
Field
Type
W
Reset
0h
Description
0
Must write 0
FORMAT EN
R/W
0h
This bit enables control for data format selection using the
FORMAT SEL register bit.
0 = Default, output is in twos complement format
1 = Output is in offset binary format after the FORMAT SEL bit is
set
4-0
0
W
0h
Must write 0
8.5.3.4.7 Register 4Dh (address = 4Dh), Main Digital Page (6800h)
Figure 106. Register 4Dh
7
0
6
0
5
0
4
0
3
2
0
1
0
0
0
DEC MOD EN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 40. Register 4Dh Field Descriptions
Bit
7-4
3
Field
Type
W
Reset
0h
Description
0
Must write 0
DEC MOD EN
R/W
0h
This bit enables control of decimation filter mode via the DECFIL
MODE[3:0] register bits.
0 = Default
1 = Decimation modes control is enabled
2-0
0
W
0h
Must write 0
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8.5.3.4.8 Register 4Eh (address = 4Eh), Main Digital Page (6800h)
Figure 107. Register 4Eh
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
CTRL NYQUIST
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 41. Register 4Eh Field Descriptions
Bit
Field
Type
Reset
Description
7
CTRL NYQUIST
R/W
0h
This bit enables selecting the Nyquist zone using register 42h,
bits 2-0.
0 = Selection disabled
1 = Selection enabled
6-0
0
W
0h
Must write 0
8.5.3.4.9 Register 52h (address = 52h), Main Digital Page (6800h)
Figure 108. Register 52h
7
6
0
5
0
4
0
3
0
2
0
1
0
0
ALWAYS WRITE 1
W-0h
DIG GAIN EN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 42. Register 52h Field Descriptions
Bit
Field
Type
Reset
Description
7
ALWAYS WRITE 1
W
0h
This bit enables output bus reorder using the
Dx_BUS_REORDER[7:0] bits. Set this bit along with register
72h, bit 3 in the main digital page.
6-1
0
0
W
0h
0h
Must write 0
DIG GAIN EN
R/W
Enables selecting the digital gain for register 44h.
0 = Digital gain disabled
1 = Digital gain enabled
8.5.3.4.10 Register 72h (address = 72h), Main Digital Page (6800h)
Figure 109. Register 72h
7
0
6
0
5
0
4
0
3
2
0
1
0
0
0
ALWAYS WRITE 1
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
R/W-0h
LEGEND: W = Write only; -n = value after reset
Table 43. Register 72h Field Descriptions
Bit
7-4
3
Field
Type
W
Reset
0h
Description
0
Must write 0
ALWAYS WRITE 1
W
0h
This bit enables output bus reorder using the
Dx_BUS_REORDER[7:0] bits. Set this bit along with register
52h, bit 7 in the main digital page.
2-0
0
W
0h
Must write 0
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8.5.3.4.11 Register ABh (address = ABh), Main Digital Page (6800h)
Figure 110. Register ABh
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
LSB SEL EN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 44. Register ABh Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
LSB SEL EN
R/W
0h
Enables control for the LSB SELECT register bit.
0 = Default
1 = The LSB of the 16-bit ADC data can be programmed as fast
OVR using the LSB SELECT bit
8.5.3.4.12 Register ADh (address = ADh), Main Digital Page (6800h)
Figure 111. Register ADh
7
0
6
0
5
0
4
0
3
0
2
0
1
0
LSB SELECT
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 45. Register ADh Field Descriptions
Bit
7-2
1-0
Field
Type
W
Reset
0h
Description
0
Must write 0
LSB SELECT
R/W
0h
Enables output of the FOVR flag instead of the output data LSB.
00 = Output is 16-bit data
11 = Output data LSB is replaced by the FOVR information for
each channel
8.5.3.4.13 Register F7h (address = F7h), Main Digital Page (6800h)
Figure 112. Register F7h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
DIG RESET
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: W = Write only; -n = value after reset
Table 46. Register F7h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
DIG RESET
W
0h
Self-clearing reset for the digital block. Does not include the
interleaving correction.
0 = Normal operation
1 = Digital reset
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8.5.3.5 JESD Digital Page (6900h) Registers
8.5.3.5.1 Register 0h (address = 0h), JESD Digital Page (6900h)
Figure 113. Register 0h
7
6
0
5
0
4
3
2
1
0
TESTMODE
EN
FLIP ADC
DATA
CTRL K
R/W-0h
LANE ALIGN
R/W-0h
FRAME ALIGN
R/W-0h
TX LINK DIS
R/W-0h
W-0h
W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 47. Register 0h Field Descriptions
Bit
Field
Type
Reset
Description
7
CTRL K
R/W
0h
Enable bit for a number of frames per multi-frame.
0 = Default is five frames per multi-frame
1 = Frames per multi-frame can be set in register 06h
6-5
4
0
W
0h
0h
Must write 0
TESTMODE EN
R/W
This bit generates the long transport layer test pattern mode, as
per section 5.1.6.3 of the JESD204B specification.
0 = Test mode disabled
1 = Test mode enabled
3
2
FLIP ADC DATA
LANE ALIGN
R/W
R/W
0h
0h
0 = Normal operation
1 = Output data order is reversed: MSB to LSB
This bit inserts the lane alignment character (K28.3) for the
receiver to align to the lane boundary, as per section 5.3.3.5 of
the JESD204B specification.
0 = Normal operation
1 = Inserts lane alignment characters
1
0
FRAME ALIGN
TX LINK DIS
R/W
R/W
0h
0h
This bit inserts the lane alignment character (K28.7) for the
receiver to align to the lane boundary, as per section 5.3.3.5 of
the JESD204B specification.
0 = Normal operation
1 = Inserts frame alignment characters
This bit disables sending the initial link alignment (ILA) sequence
when SYNC is de-asserted.
0 = Normal operation
1 = ILA disabled
56
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8.5.3.5.2 Register 1h (address = 1h), JESD Digital Page (6900h)
Figure 114. Register 1h
7
6
5
0
4
0
3
0
2
1
0
SYNC REG
R/W-0h
SYNC REG EN
R/W-0h
JESD MODE
R/W-1h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 48. Register 1h Field Descriptions
Bit
Field
Type
Reset
Description
7
SYNC REG
R/W
0h
Register control for sync request.
0 = Normal operation
1 = ADC output data are replaced with K28.5 characters; the SYNC
REG EN register bit must also be set to 1
6
SYNC REG EN
R/W
0h
Enables register control for sync request.
0 = Use the SYNC pin for sync requests
1 = Use the SYNC REG register bit for sync requests
5-3
2-0
0
W
0h
1h
Must write 0
JESD MODE
R/W
These bits select the number of active output lanes. The JESD PLL
MODE register bit located in the JESD analog page must also be
set accordingly. Active lanes carry serial JESD data whereas
inactive lanes don't carry any data.
001 = 20X mode, four active lanes per device (default)
010 = 40X mode, two active lanes per device
All others = Not used
8.5.3.5.3 Register 2h (address = 2h), JESD Digital Page (6900h)
Figure 115. Register 2h
7
6
5
4
3
2
0
1
0
0
0
LINK LAYER TESTMODE
R/W-0h
LINK LAYER RPAT
R/W-0h
LMFC MASK RESET
R/W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 49. Register 2h Field Descriptions
Bit
Field
Type
Reset
Description
7-5
LINK LAYER TESTMODE
R/W
0h
These bits generate a pattern according to section 5.3.3.8.2 of the
JESD204B document.
000 = Normal ADC data
001 = D21.5 (high-frequency jitter pattern)
010 = K28.5 (mixed-frequency jitter pattern)
011 = Repeat initial lane alignment (generates a K28.5 character
and continuously repeats lane alignment sequences)
100 = 12-octet RPAT jitter pattern
All others = Not used
4
LINK LAYER RPAT
R/W
0h
This bit changes the running disparity in the modified RPAT pattern
test mode (only when the link layer test mode = 100).
0 = Normal operation
1 = Changes disparity
3
LMFC MASK RESET
0
R/W
W
0h
0h
Masks the LMFC reset coming to the digital block.
0 = LMFC reset is not masked
1 = Ignore the LMFC reset request
2-0
Must write 0
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8.5.3.5.4 Register 3h (address = 3h), JESD Digital Page (6900h)
Figure 116. Register 3h
7
6
5
4
3
2
1
0
FORCE LMFC
COUNT
LMFC COUNT INIT
R/W-0h
RELEASE ILANE SEQ
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 50. Register 3h Field Descriptions
Bit
Field
Type
Reset
Description
7
FORCE LMFC COUNT
R/W
0h
This bit forces the LMFC count.
0 = Normal operation
1 = Enables using a different starting value for the LMFC
counter
6-2
1-0
MASK SYSREF
R/W
R/W
0h
0h
When SYSREF transmits to the digital block, the LMFC count
resets to 0 and K28.5 stops transmitting when the LMFC count
reaches 31. The initial value that the LMFC count resets to can
be set using LMFC COUNT INIT. In this manner, the receiver
can be synchronized early because the LANE ALIGNMENT
SEQUENCE is received early. The FORCE LMFC COUNT
register bit must be enabled.
RELEASE ILANE SEQ
These bits delay the generation of the lane alignment sequence
by 0, 1, 2 or 3 multi-frames after the code group
synchronization.
00 = 0
01 = 1
10 = 2
11 = 3
8.5.3.5.5 Register 5h (address = 5h), JESD Digital Page (6900h)
Figure 117. Register 5h
7
6
0
5
4
3
2
0
1
0
0
0
SCRAMBLE EN
R/W-Undefined
0
0
0
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 51. Register 5h Field Descriptions
Bit
Field
Type
Reset
Description
7
SCRAMBLE EN
R/W
Undefined Scrambles the enable bit in the JESD204B interface.
0 = Scrambling disabled
1 = Scrambling enabled
6-0
0
W
0h
Must write 0
58
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8.5.3.5.6 Register 6h (address = 6h), JESD Digital Page (6900h)
Figure 118. Register 6h
7
0
6
0
5
0
4
3
2
1
0
FRAMES PER MULTI FRAME (K)
R/W-8h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 52. Register 6h Field Descriptions
Bit
7-5
4-0
Field
Type
W
Reset
0h
Description
0
Must write 0
FRAMES PER MULTI FRAME (K)
R/W
8h
These bits set the number of multi-frames.
Actual K is the value in hex + 1 (that is, 0Fh is K = 16).
8.5.3.5.7 Register 7h (address = 7h), JESD Digital Page (6900h)
Figure 119. Register 7h
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
SUBCLASS
R/W-1h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 53. Register 7h Field Descriptions
Bit
7-4
3
Field
Type
W
Reset
0h
Description
0
Must write 0
SUBCLASS
R/W
1h
This bit sets the JESD204B subclass.
000 = Subclass 0 is backward compatible with JESD204A
001 = Subclass 1 deterministic latency using the SYSREF signal
2-0
0
W
0h
Must write 0
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8.5.3.5.8 Register 31h (address = 31h), JESD Digital Page (6900h)
Figure 120. Register 31h
7
6
5
4
3
2
1
0
DA_BUS_REORDER[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 54. Register 31h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DA_BUS_REORDER[7:0]
R/W
0h
Use these bits to program output connections between data
streams and output lanes in decimate-by-2 mode. Table 12 lists
the supported combinations of these bits.
8.5.3.5.9 Register 32h (address = 32h), JESD Digital Page (6900h)
Figure 121. Register 32h
7
6
5
4
3
2
1
0
DB_BUS_REORDER[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 55. Register 32h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DB_BUS_REORDER[7:0]
R/W
0h
Use these bits to program output connections between data
streams and output lanes in decimate-by-2 mode. Table 12 lists
the supported combinations of these bits.
60
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8.5.3.6 JESD Analog Page (6A00h) Register
8.5.3.6.1 Registers 12h-5h (address = 12h-5h), JESD Analog Page (6A00h)
Figure 122. Register 12h
7
6
5
4
3
2
2
2
2
1
0
0
0
SEL EMP LANE 1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
W-0h
W-0h
Figure 123. Register 13h
7
6
5
4
3
1
0
0
0
SEL EMP LANE 0
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
W-0h
W-0h
Figure 124. Register 14h
7
6
5
4
3
1
0
0
0
SEL EMP LANE 2
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
W-0h
W-0h
Figure 125. Register 15h
7
6
5
4
3
1
0
0
0
SEL EMP LANE 3
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
W-0h
W-0h
Table 56. Registers 12h-15h Field Descriptions
Bit
Field
Type
Reset
Description
7-2
SEL EMP LANE 1, 0, 2, or 3
R/W
0h
Selects the amount of de-emphasis for the JESD output
transmitter. The de-emphasis value in dB is measured as the
ratio between the peak value after the signal transition to the
settled value of the voltage in one bit period.
000000 = 0 dB
000001 = –1 dB
000011 = –2 dB
000111 = –4.1 dB
001111 = –6.2 dB
011111 = –8.2 dB
111111 = –11.5 dB
1-0
0
W-0h
0h
Must write 0
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8.5.3.6.2 Register 16h (address = 16h), JESD Analog Page (6A00h)
Figure 126. Register 16h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
JESD PLL MODE
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 57. Register 16h Field Descriptions
Bit
7-2
1-0
Field
Type
W
Reset
0h
Description
0
Must write 0
JESD PLL MODE
R/W
0h
These bits select the JESD PLL multiplication factor and must
match the JESD MODE setting.
00 = 20X mode, four active lanes per device
01 = Not used
10 = 40X mode, two active lanes per device
11 = Not used
8.5.3.6.3 Register 1Ah (address = 1Ah), JESD Analog Page (6A00h)
Figure 127. Register 1Ah
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
FOVR CHA
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 58. Register 1Ah Field Descriptions
Bit
7-2
1
Field
Type
W
Reset
0h
Description
0
Must write 0
FOVR CHA
R/W
0h
Outputs the FOVR signal for channel A on the PDN pin. FOVR
CHA EN (register 1Bh, bit 3) must be enabled.
0 = Normal operation
1 = FOVR on the PDN pin
0
0
W
0h
Must write 0
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8.5.3.6.4 Register 1Bh (address = 1Bh), JESD Analog Page (6A00h)
Figure 128. Register 1Bh
7
6
5
4
0
3
2
0
1
0
0
0
JESD SWING
R/W-0h
FOVR CHA EN
R/W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 59. Register 1Bh Field Descriptions
Bit
Field
Type
Reset
Description
7-5
JESD SWING
R/W
0h
Selects the output differential amplitude VOD (mVPP) of the JESD
transmitter (for all lanes).
0 = 860 mVPP
1 = 810 mVPP
2 = 770 mVPP
3 = 745 mVPP
4 = 960 mVPP
5 = 930 mVPP
6 = 905 mVPP
7 = 880 mVPP
4
3
0
W
0h
0h
Must write 0
FOVR CHA EN
R/W
Enables overwriting the PDN pin with the FOVR signal from
channel A.
0 = Normal operation
1 = PDN is overwritten
2-0
JESD PLL MODE
R/W
0h
Must write 0
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Start-Up Sequence
The steps described in Table 60 are the recommended power-up sequence with the ADS54J69 in 20X or 40X
mode.
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Table 60. Initialization Sequence
PAGE BEING
PROGRAMMED
STEP
SEQUENCE
DESCRIPTION
COMMENT
Bring up IOVDD to 1.15 V before applying power to DVDD. Bring up
DVDD to 1.9 V, AVDD to 1.9 V, and AVDD3V to 3.0 V.
See the Power Sequencing and Initialization section for power sequence
requirements.
1
Power-up the device
—
Hardware reset
Apply a hardware reset by pulsing pin 48 (low->high->low).
Software reset: Register writes equivalent to a hardware reset are:
—
A hardware reset clears all registers to their default values.
Reset registers in the ADC page and master page of the analog bank This bit
is a self-clearing bit.
Write address 0-000h with 81h.
General register
This bit is a self-clearing bit.
2
Reset the device
Write address 4-001h with 00h and address 4-002h with 00h.
Write address 4-003h with 00h and address 4-004h with 68h.
Unused page
—
Clear any unwanted content from the unused pages of the JESD bank.
Select the main digital page of the JESD bank.
Use the DIG RESET register bit to reset all pages in the JESD bank.
This bit is a self-clearing bit.
Write address 6-0F7h with 01h for channel A.
Main digital page
(JESD bank)
Write address 6-000h with 01h, then address 6-000h with 00h.
Write address 0-011h with 80h.
Pulse the PULSE RESET register bit for both channels.
Select the master page of the analog bank.
—
3
Performance modes
Master page
(analog bank)
Write address 0-059h with 20h.
Set the ALWAYS WRITE 1 bit.
The JESD mode (in the JESD digital page) and JESD PLL mode (in the JESD analog page) register bits control 20X or 40X serialization. By default after reset,
the device is in 20X serialization mode (4-lanes output).
Write address 4-003h with 00h and address 4-004h with 69h.
Write address 6-000h with 80h.
—
Select the JESD digital page.
Set the CTRL K bit for both channels to program K for the SYSREF signal
frequency in step 5.
JESD
digital page
(JESD bank)
Write address 6-001h with 01h.
Enable 20X serialization (4-lane output, default setting after reset).
Enable 40X serialization (2-lane output).
Write address 6-001h with 02h.
Write address 4-003h with 00h and address 4-004h with 6Ah.
Write address 6-016h with 00h
Select the JESD analog page.
JESD
analog page
(JESD bank)
Program registers for
20X or 40X serialization
and program the HPF or LPF
filter
Enable 20X serialization (4-lane output, default setting after reset).
To enable 40X serialization (2-lane output).
Select the main digital page.
4
Write address 6-016h with 02h
Write address 4-003h with 00h and address 4-004h with 68h.
Set the ALWAYS WRITE 1 bit (enables correct order of the JESD output
lanes).
Write address 6-052h with 80h and address 6-072h with 08h.
Write address 6-04Dh with 08h
Write address 6-041h with 12h
Write address 6-041h with 16h
Enable the decimation filter programming.
Enable the low-pass filter (default setting after reset).
Enable the high-pass filter.
Main digital page
(JESD bank)
Pulse the PULSE RESET register bit. All settings programmed in the main
digital page take effect only after this bit is pulsed.
Write address 6-000h with 01h and address 6-000h with 00h.
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Table 60. Initialization Sequence (continued)
PAGE BEING
SEQUENCE
DESCRIPTION
PROGRAMMED
COMMENT
Write address 4-003h with 00h and address 4-004h with 69h.
—
Select the JESD digital page.
Default value of K is 8 for 20X (4-lane) mode and 4 for 40X (2-lane) mode.
However, K can be programmed for higher values than the default by using
bits 4-0 of address 6-006 in the JESD digital page. For example, if K = 31 by
writing address 6-006h with 1Fh in the JESD digital page, then the SYSREF
signal frequency must be kept less than or equal to 250 MHz / 32 =
7.8125 MHz.
Set the value of K and the
SYSREF signal frequency
accordingly
JESD
digital page
(JESD bank)
5
6
Write address 6-006h with XXh (choose the value of K).
Pull the SYNC pin (pin 63) low.
Pull the SYNC pin high.
Transmit K28.5 characters.
JESD lane alignment
—
After the receiver is synchronized, initiate an ILA phase and subsequent
transmissions of ADC data.
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9.1.2 Hardware Reset
Figure 129 and Table 61 show the timing for a hardware reset.
Power Supplies
t1
RESET
t2
t3
SEN
Figure 129. Hardware Reset Timing Diagram
Table 61. Timing Requirements for Figure 129
MIN
TYP
MAX
UNIT
ms
ns
t1
t2
t3
Power-on delay from power-up to active high RESET pulse
1
10
Reset pulse duration: active high RESET pulse duration
Register write delay: delay from RESET disable to SEN active
100
ns
9.1.3 SNR and Clock Jitter
The signal-to-noise ratio (SNR) of the ADC is limited by three different factors: quantization noise, thermal noise,
and jitter, as shown in Equation 4. The quantization noise is typically not noticeable in pipeline converters and is
98 dB for a 16-bit ADC. The thermal noise limits SNR at low input frequencies and the clock jitter sets SNR for
higher input frequencies. The decimation-by-2 process gives approximately an additional 3-dB improvement in
SNR.
2
2
2
504
,EPPAN
20
F
¨
20
20
>
?
504#&% @$? = F3 F 20HKC l10
3Q=JPEV=PEKJ 0KEOA p + l10F 5046DANI=H 0KEOA p + l 10F 504
p
(4)
The SNR limitation resulting from the sample clock jitter can be calculated by Equation 5:
(5)
The total clock jitter (TJitter) has two components: the internal aperture jitter (145 fS) is set by the noise of the
clock input buffer and the external clock jitter. TJitter can be calculated by Equation 6:
(6)
External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass
filters at the clock input. A faster clock slew rate also improves the ADC aperture jitter.
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The ADS54J69 has a thermal noise of approximately 71.1 dBFS and an internal aperture jitter of 120 fS. The
SNR, depending on the amount of external jitter for different input frequencies, is shown in Figure 130.
75
35 fS
50 fS
100 fS
150 fS
200 fS
73
71
69
67
65
10
100
Input Frequency (MHz)
D052
Figure 130. SNR versus Input Frequency and External Clock Jitter
Half-band decimation filtering employed by the ADS54J69 reduces the affect of all contributors to SNR by 3 dB.
Filtering makes the SNR curve in Figure 130 start at 74 dBFS despite a thermal noise of 71.1 dBFS.
Decimation filtering also improves the affect of jitter noise by 3 dB, and is equivalent to having 102 fS as the
effective aperture jitter instead of 120 fS.
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9.2 Typical Application
The ADS54J69 is designed for wideband receiver applications demanding excellent dynamic range over a large
input frequency range. A typical schematic for an ac-coupled receiver is shown in Figure 131.
DVDD
10 kꢀ
5 W
5 W
50 W
50 W
Driver
0.1 mF
2 pF
0.1 mF
SPI Master
GND
GND
IOVDD GND
0.1 mF
0.1 mF
0.1 mF
10nF
GND
0.1 mF
AVDD3V
AVDD
AVDD
AVDD3V
DVDD
100-W Differential
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
10 nF
DB2P
DB2M
IOVDD
DB1P
DB1M
DGND
DB0P
DB0M
IOVDD
SYNC
DA0M
DA0P
DGND
DA1M
DA1P
IOVDD
DA2M
DA2P
NC
NC
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
IOVDD
10 nF
GND
NC
10 nF
10 nF
VCM
0.1 mF
AGND
AVDD3V
AVDD
AGND
CLKINP
CLKINM
AGND
AVDD
AVDD3V
AGND
GND
0.1 mF
AVDD3V
GND
AVDD
0.1 mF
GND
10 nF
IOVDD
0.1 mF
GND
GND Pad
(Back Side)
GND
0.1 mF
FPGA
Low-Jitter Clock
Generator
AVDD3V
0.1 mF
GND
10 nF
10 nF
GND
SYSREFP
SYSREFM
AVDD
100 W
IOVDD
10 nF
GND
AVDD
AGND
GND
10 nF
10 nF
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
100-W Differential
AVDD3V
DVDD
AVDD
AVDD
AVDD3V
0.1 mF
GND
GND
0.1 mF
IOVDD GND
0.1 mF
GND
5 W
5 W
50 W
50 W
Driver
0.1 mF
0.1 mF
2 pF
GND
NOTE: GND = AGND and DGND connected in the PCB layout.
Figure 131. AC-Coupled Receiver
68
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ADS54J69
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ZHCSEJ4C –MAY 2015–REVISED JANUARY 2017
Typical Application (continued)
9.2.1 Design Requirements
9.2.1.1 Transformer-Coupled Circuits
Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as
ADT1-1WT or WBC1-1) can be used up to 300 MHz to achieve good phase and amplitude balances at the ADC
inputs. When designing dc driving circuits, the ADC input impedance must be considered. Figure 132 and
Figure 133 show the impedance (ZIN = RIN || CIN) across the ADC input pins.
5
4.75
4.5
1.4
1.2
1
4.25
4
0.8
0.6
0.4
0.2
0
3.75
3.5
3.25
3
2.75
2.5
2.25
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
Frequency (MHz)
Frequency (MHz)
D103
D102
Figure 132. RIN vs Input Frequency
Figure 133. CIN vs Input Frequency
By using the simple drive circuit of Figure 134, uniform performance can be obtained over a wide frequency
range. The buffers present at the analog inputs of the device help isolate the external drive source from the
switching currents of the sampling circuit.
0.1 ꢁF
T2
CHx_INP
T1
5 ꢀ
0.1 ꢁF
25 ꢀ
0.1 ꢁF
RIN
CIN
25 ꢀ
5 ꢀ
0.1 ꢁF
CHx_INM
1:1
1:1
Device
Figure 134. Input Drive Circuit
9.2.2 Detailed Design Procedure
For optimum performance, the analog inputs must be driven differentially. This architecture improves common-
mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input
pin is recommended to damp out ringing caused by package parasitics, as shown in Figure 134.
Copyright © 2015–2017, Texas Instruments Incorporated
69
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ZHCSEJ4C –MAY 2015–REVISED JANUARY 2017
www.ti.com.cn
Typical Application (continued)
9.2.3 Application Curves
Figure 135 and Figure 136 show the typical performance at 170 MHz and 230 MHz, respectively.
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
50
100
150
200
250
0
50
100
150
200
250
D005
Input Frequency (MHz)
Input Frequency (MHz)
D003
SNR = 73 dBFS; SFDR = 93 dBc; SINAD = 73.18 dBFS;
THD = 89 dBc; HD2 = 93 dBc; HD3 = 103 dBc;
IL spur = 99 dBc; non HD2, HD3 spur = 94 dBc
SNR = 71.6 dBFS; SFDR = 80 dBc; SINAD = 71 dBFS;
THD = 79 dBc; HD2 = –80 dBc; HD3 = –96 dBc;
IL spur = 85 dBc; non HD2, HD3 spur = 92 dBc
Figure 135. FFT for 170-MHz Input Signal
Figure 136. FFT for 310-MHz Input Signal
10 Power Supply Recommendations
The device requires a 1.15-V nominal supply for IOVDD, a 1.9-V nominal supply for DVDD, a 1.9-V nominal
supply for AVDD, and a 3.0-V nominal supply for AVDD3V. For detailed information regarding the operating
voltage minimum and maximum specifications of different supplies, see the Recommended Operating Conditions
table.
70
Copyright © 2015–2017, Texas Instruments Incorporated
ADS54J69
www.ti.com.cn
ZHCSEJ4C –MAY 2015–REVISED JANUARY 2017
10.1 Power Sequencing and Initialization
Figure 137 shows the suggested power-up sequencing for the device. Note that the 1.15-V IOVDD supply must
rise before the 1.9-V DVDD supply. If the 1.9-V DVDD supply rises before the 1.15-V IOVDD supply, then the
internal default register settings may not load properly. The other supplies (the 3-V AVDD3V and the 1.9-V
AVDD), can come up in any order during the power sequence. The power supplies can ramp up at any rate and
there is no hard requirement for the time delay between IOVDD ramp up to DVDD ramp-up (can be in orders of
microseconds but is recommend to be a few milliseconds).
IOVDD = 1.15 V
DVDD = 1.9 V
AVDD = 1.9 V
AVDD = 3 V
Figure 137. Power Sequencing for the ADS54Jxx Family of Devices
Copyright © 2015–2017, Texas Instruments Incorporated
71
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ZHCSEJ4C –MAY 2015–REVISED JANUARY 2017
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
The device evaluation module (EVM) layout can be used as a reference layout to obtain the best performance. A
layout diagram of the EVM top layer is provided in Figure 138. A complete layout of the EVM is available from
the ADS54J69EVM folder. Some important points to remember during board layout are:
•
•
•
Analog inputs are located on opposite sides of the device pinout to ensure minimum crosstalk on the package
level. To minimize crosstalk onboard, the analog inputs must exit the pinout in opposite directions, as
illustrated in the reference layout of Figure 138 as much as possible.
In the device pinout, the sampling clock is located on a side perpendicular to the analog inputs in order to
minimize coupling between them. This configuration is also maintained on the reference layout of Figure 138
as much as possible.
Keep digital outputs away from the analog inputs. When these digital outputs exit the pinout, the digital output
traces must not be kept parallel to the analog input traces because this configuration can result in coupling
from the digital outputs to the analog inputs and degrade performance. All digital output traces to the receiver
[such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)] must be
matched in length to avoid skew among outputs.
•
At each power-supply pin (AVDD, DVDD, or AVDDD3V), keep a 0.1-µF decoupling capacitor close to the
device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF
capacitors can be kept close to the supply source.
72
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ADS54J69
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ZHCSEJ4C –MAY 2015–REVISED JANUARY 2017
11.2 Layout Example
Figure 138. ADS54J69EVM layout
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73
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ZHCSEJ4C –MAY 2015–REVISED JANUARY 2017
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12 器件和文档支持
12.1 文档支持
12.1.1 相关文档ꢀ
相关文档如下:
•
•
•
•
•
•
ADS54J20双通道 12 位 1.0GSPS 模数转换器
ADS54J40 双通道 14 位 1.0GSPS 模数转换器
ADS54J42 双通道、14 位、625MSPS 模数转换器
ADS54J60 双通道 16 位 1.0GSPS 模数转换器
ADS54J66 具有集成 DDC 的四通道、14 位、500MSPS ADC
《ADS54J69EVM 用户指南》
12.2 接收文档更新通知
如需接收文档更新通知,请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后,即可每周定期收到已更改的产品信息。有关更改的详细信息,请查阅已修订文档中包含的修订历史记录。
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
74
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS54J69IRMP
ADS54J69IRMPT
ACTIVE
ACTIVE
VQFN
VQFN
RMP
RMP
72
72
168
250
RoHS & Green
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
AZ54J69
AZ54J69
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
ADS54J69IRMP
RMP
VQFNP
72
168
8 X 21
150
315 135.9 7620 14.65
11
11.95
Pack Materials-Page 1
PACKAGE OUTLINE
RMP0072A
VQFN - 0.9 mm max height
SCALE 1.700
VQFN
10.1
9.9
A
B
PIN 1 ID
10.1
9.9
0.9 MAX
0.05
0.00
C
SEATING PLANE
0.08 C
(0.2)
4X (45 X0.42)
19
36
18
37
SYMM
4X
8.5
8.5 0.1
PIN 1 ID
(R0.2)
1
54
0.30
0.18
72X
72
55
68X 0.5
SYMM
0.5
0.3
0.1
C B
A
72X
0.05
C
4221047/B 02/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RMP0072A
VQFN - 0.9 mm max height
VQFN
(
8.5)
SYMM
72X (0.6)
SEE DETAILS
55
72
1
54
72X (0.24)
(0.25) TYP
SYMM
(9.8)
(1.315) TYP
68X (0.5)
(
0.2) TYP
VIA
37
18
19
36
(1.315) TYP
(9.8)
LAND PATTERN EXAMPLE
SCALE:8X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4221047/B 02/2014
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON PCB application report
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RMP0072A
VQFN - 0.9 mm max height
VQFN
(9.8)
72X (0.6)
(1.315) TYP
72
55
1
54
72X (0.24)
(1.315)
TYP
(0.25) TYP
SYMM
(9.8)
(1.315)
TYP
68X (0.5)
METAL
TYP
37
18
(
0.2) TYP
VIA
19
36
36X ( 1.115)
(1.315) TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
62% PRINTED SOLDER COVERAGE BY AREA
SCALE:8X
4221047/B 02/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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