ADS5527_技术文档

ADS5527

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SLWS196–DECEMBER 2006

12-BIT, 210 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

FEATURES

DESCRIPTION

•

Maximum Sample Rate: 210 MSPS

ADS5527 is a high performance 12-bit, 210-MSPS

A/D converter. It offers state-of-the art functionality

and performance using advanced techniques to

minimize board space. With high analog bandwidth

and low jitter input clock buffer, the ADC supports

both high SNR and high SFDR at high input

frequencies. It features programmable gain options

that can be used to improve SFDR performance at

lower full-scale analog input ranges.

12-Bit Resolution

No Missing Codes

Total Power Dissipation 1.23 W

Internal Sample and Hold

70.5-dBFS SNR at 70-MHz IF

84-dBc SFDR at 70-MHz IF, 0-dB gain

High Analog Bandwith up to 800 MHz

In a compact 48-pin QFN, the device offers fully

differential LVDS DDR (Double Data Rate) interface

while parallel CMOS outputs can also be selected.

Flexible output clock position programmability is

available to ease capture and trade-off setup for hold

times. At lower sampling rates, the ADC can be

operated at scaled down power with no loss in

performance. The ADS5527 includes an internal

reference, while eliminating the traditional reference

pins and associated external decoupling. The device

also supports an external reference mode.

Double Data Rate (DDR) LVDS and Parallel

CMOS Output Options

•

Programmable Gain up to 6 dB for SNR/SFDR

Trade-Off at High IF

Reduced Power Modes at Lower Sample

Rates

Supports Input Clock Amplitude Down to

400 mV_PP

•

Clock Duty Cycle Stabilizer

The device is specified over the industrial

temperature range (-40°C to 85°C).

No External Reference Decoupling Required

Internal and External Reference Support

Programmable Output Clock Position to Ease

Data Capture

ADS5527 PRODUCT FAMILY

210 MSPS

ADS5547

ADS5527

190 MSPS

ADS5546

-

170 MSPS

ADS5545

ADS5525

•

3.3-V Analog and Digital Supply

14 bit

12 bit

48-QFN Package (7 mm × 7 mm)

APPLICATIONS

•

Wireless Communications Infrastructure

Software Defined Radio

Power Amplifier Linearization

802.16d/e

Test and Measurement Instrumentation

High Definition Video

Medical Imaging

Radar Systems

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADS5527

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SLWS196–DECEMBER 2006

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be

more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

CLKP

CLKOUTP

CLKOUTM

CLOCKGEN

CLKM

D0_D1_P

D0_D1_M

D2_D3_P

D2_D3_M

D4_D5_P

D4_D5_M

Digital

Encoder

and

INP

INM

12-Bit

ADC

D6_D7_P

D6_D7_M

SHA

Serializer

D8_D9_P

D8_D9_M

D10_D11_P

D10_D11_M

Control

Interface

VCM

Reference

OVR

LVDS MODE

PACKAGE/ORDERING INFORMATION⁽¹⁾

SPECIFIED

TEMPERATURE

RANGE

TRANSPORT

MEDIA,

QUANTITY

PACKAGE-

PACKAGE

DESIGNATOR

PACKAGE

MARKING

ORDERING

NUMBER

PRODUCT

LEAD

Tape and Reel,

250

ADS5527IRGZT

ADS5527IRGZR

ADS5527

QFN-48⁽²⁾

RGZ

–40°C to 85°C

AZ5527

Tape and Reel,

2500

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

(2) For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θ_JA= 25.41°C/W (0 LFM air flow),

θ_JC= 16.5°C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in x 3 in PCB.

2

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ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

VALUE

–0.3 V to 3.9

-0.3 to 0.3

-0.3 to 3.3

-0.3 to 1.8

UNIT

Supply voltage range, AVDD

V

Supply voltage range, DRVDD

Voltage between AGND and DRGND

Voltage between AVDD to DRVDD

Voltage applied to VCM pin (in external reference mode)

Voltage applied to analog input pins, INP and INM

Voltage applied to input clock pins, CLKP and CLKM

–0.3 V to minimum (3.6, AVDD + 0.3 V)

V

-0.3 V to AVDD + 0.3 V

–40 to 85

V

T_A

Operating free-air temperature range

Operating junction temperature range

Storage temperature range

°C

T_J

125

T_stg

–65 to 150

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

TYP

MAX

UNIT

SUPPLIES

Analog supply voltage, AVDD

Digital supply voltage, DRVDD

ANALOG INPUTS

3

3.3

3.6

V

Differential input voltage range

2

1.5 ±0.1

1.5

V_PP

V

Input common-mode voltage

Voltage applied on VCM in external reference mode

1.45

1.55

V

CLOCK INPUT

Input clock sample rate

(1)

MSPS

DEFAULT SPEED mode

LOW SPEED mode

50

1

210

60

Input clock amplitude differential (V_(CLKP)- V_(CLKM)

)

Sine wave, ac-coupled

LVPECL, ac-coupled

0.4

1.5

1.6

V_PP

V

LVDS, ac-coupled

0.7

LVCMOS, single-ended, ac-coupled

3.3

Input clock duty cycle (See Figure 31)

DIGITAL OUTPUTS

35%

50%

65%

C_L

Maximum external load capacitance from each output pin to DRGND (LVDS and CMOS modes)

Without internal termination (default after

reset)

5

pF

(2)

With 100 Ω internal termination

10

pF

Ω

R_L

Differential load resistance between the LVDS output pairs (LVDS mode)

100

Operating free-air temperature

–40

85

°C

(1) See the section on Low Sampling Frequency Operation for more information.

(2) See the section on LVDS Buffer Internal termination for more information.

3

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ELECTRICAL CHARACTERISTICS

Typical values are at 25°C, min and max values are across the full temperature range T_MIN= –40°C to T_MAX= 85°C,

AVDD = DRVDD = 3.3 V, sampling rate = 210 MSPS, sine wave input clock, 1.5 V_PPdifferential clock amplitude, 50% clock

duty cycle, –1 dBFS differential analog input, internal reference mode, 0-db gain, DDR LVDS data output (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

12

bits

ANALOG INPUT

Differential input voltage range

Differential input capacitance

Analog input bandwidth

2

7

V_PP

pF

800

MHz

Analog input common mode current

(per input pin)

342

µA

REFERENCE VOLTAGES

V_(REFB)

V_(REFT)

V_CM

Internal reference bottom voltage

Internal reference top voltage

Common mode output voltage

VCM output current capability

Internal reference mode

0.5

2.5

1.5

±4

V

Internal reference mode

V

mA

DC ACCURACY

No Missing Codes

Assured

0.5

DNL

INL

Differential non-linearity

Integral non-linearity

Offset error

-0.8

-2

1.0

2

LSB

1

-10

5

10

mV

Offset temperature coefficient

Gain error

0.002

± 1

ppm/°C

%FS

Gain temperature coefficient

DC Power supply rejection ratio

0.01

0.6

∆%/°C

mV/V

PSRR

POWER SUPPLY

I_(AVDD)

I_(DRVDD)

I_CC

Analog supply current

306

66

mA

LVDS mode, I_O= 3.5 mA,

R_L= 100 Ω, C_L= 5 pF

Digital supply current

CMOS mode, F_IN= 2.5 MHz,

C_L= 5 pF

47

mA

Total supply current

Total power dissipation

Standby power

LVDS mode

372

1.23

100

mA

W

LVDS mode

1.375

150

In STANDBY mode with clock stopped

With input clock stopped

mW

Clock stop power

150

4

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SLWS196–DECEMBER 2006

ELECTRICAL CHARACTERISTICS

Typical values are at 25°C, min and max values are across the full temperature range T_MIN= –40°C to T_MAX= 85°C,

AVDD = DRVDD = 3.3 V, sampling rate = 210 MSPS, sine wave input clock, 1.5 V_PPdifferential clock amplitude, 50% clock

duty cycle, –1 dBFS differential analog input, internal reference mode, 0-db gain, DDR LVDS data output (unless otherwise

noted)

PARAMETER

AC CHARACTERISTICS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

F_IN= 20 MHz

F_IN= 70 MHz

F_IN= 100 MHz

F_IN= 170 MHz

70.7

70.5

70.3

69.5

69.4

68

0 dB gain, 2 V_PPFS⁽¹⁾

SNR

Signal to noise ratio

F_IN= 230 MHz

F_IN= 300 MHz

F_IN= 400 MHz

dBFS

LSB

dBc

3 dB gain, 1.4 V_PPFS

0 dB gain, 2 V_PPFS

3 dB gain, 1.4 V_PPFS

0 dB gain, 2 V_PPFS

3 dB gain, 1.4 V_PPFS

68.5

67.4

67.3

66.4

0.35

86

RMS output noise

Inputs tied to common-mode

F_IN= 20 MHz

F_IN= 70 MHz

75

67.5

75

84

F_IN= 100 MHz

78

F_IN= 170 MHz

79

0 dB gain, 2 V_PPFS

75

SFDR

Spurious free dynamic range

F_IN= 230 MHz

F_IN= 300 MHz

F_IN= 400 MHz

3 dB gain, 1.4 V_PPFS

0 dB gain, 2 V_PPFS

3 dB gain, 1.4 V_PPFS

0 dB gain, 2 V_PPFS

3 dB gain, 1.4 V_PPFS

78

74

76

68

70

F_IN= 20 MHz

F_IN= 70 MHz

F_IN= 100 MHz

F_IN= 170 MHz

F_IN= 230 MHz

70.5

70.2

69.3

68.0

67.4

67.1

66.4

66.3

63.5

65.0

91

0 dB gain, 2 V_PPFS

3 dB gain, 1.4 V_PPFS

0 dB gain, 2 V_PPFS

3 dB gain, 1.4 V_PPFS

0 dB gain, 2 V_PPFS

3 dB gain, 1.4 V_PPFS

SINAD Signal to noise and distortion ratio

dBFS

F_IN= 300 MHz

F_IN= 400 MHz

F_IN= 20 MHz

F_IN= 70 MHz

F_IN= 100 MHz

F_IN= 170 MHz

F_IN= 230 MHz

88

87

0 dB gain, 2 V_PPFS

3 dB gain, 1.4 V_PPFS

0 dB gain, 2 V_PPFS

3 dB gain, 1.4 V_PPFS

0 dB gain, 2 V_PPFS

3 dB gain, 1.4 V_PPFS

86

HD2

Second harmonic

dBc

88

78

F_IN= 300 MHz

F_IN= 400 MHz

80

69

71

(1) FS = Full scale range

5

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ELECTRICAL CHARACTERISTICS (continued)

Typical values are at 25°C, min and max values are across the full temperature range T_MIN= –40°C to T_MAX= 85°C,

AVDD = DRVDD = 3.3 V, sampling rate = 210 MSPS, sine wave input clock, 1.5 V_PPdifferential clock amplitude, 50% clock

duty cycle, –1 dBFS differential analog input, internal reference mode, 0-db gain, DDR LVDS data output (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

86

84

78

79

75

78

74

76

68

70

95

92

90

88

87

83

82

76

77

73

72

65

11.4

91

MAX

UNIT

F_IN= 20 MHz

F_IN= 70 MHz

F_IN= 100 MHz

F_IN= 170 MHz

75

0 dB gain, 2 V_PPFS

HD3

Third harmonic

F_IN= 230 MHz

F_IN= 300 MHz

F_IN= 400 MHz

dBc

3 dB gain, 1.4 V_PPFS

0 dB gain, 2 V_PPFS

3 dB gain, 1.4 V_PPFS

0 dB gain, 2 V_PPFS

3 dB gain, 1.4 V_PPFS

F_IN= 20 MHz

F_IN= 70 MHz

F_IN= 100 MHz

F_IN= 170 MHz

F_IN= 230 MHz

F_IN= 300 MHz

F_IN= 400 MHz

F_IN= 20 MHz

F_IN= 70 MHz

F_IN= 100 MHz

F_IN= 170 MHz

F_IN= 230 MHz

F_IN= 300 MHz

F_IN= 400 MHz

F_IN= 70 MHz

Worst harmonic (other than HD2, HD3)

dBc

73

THD

Total harmonic distortion

dBc

ENOB

IMD

Effective number of bits

10.9

bits

dBFS

dBc

F_IN1= 50.03 MHz, F_IN2= 46.03 MHz,

-7 dBFS each tone

Two-tone intermodulation distortion

F_IN1= 190.1 MHz, F_IN2= 185.02 MHz,

-7 dBFS each tone

86

35

1

PSRR

AC power supply rejection ratio

Voltage overload recovery time

30 MHz, 200 mV_PPsignal on 3.3-V supply

Recovery to 1% (of final value) for 6-dB overload

with sine-wave input at Nyquist frequency

Clock

cycles

6

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DIGITAL CHARACTERISTICS⁽¹⁾

The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic

level 0 or 1 AVDD = DRVDD = 3.3 V, I_O= 3.5 mA, R_L= 100 Ω⁽²⁾

PARAMETER

DIGITAL INPUTS

TEST CONDITIONS

MIN

TYP

MAX UNIT

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

Input capacitance

2.4

V

0.8

V

33

–33

4

µA

pF

DIGITAL OUTPUTS – CMOS MODE

High-level output voltage

Low-level output voltage

Output capacitance

3.3

0

V

Output capacitance inside the device, from each output to

ground

2

pF

DIGITAL OUTPUTS – LVDS MODE

High-level output voltage

1375

1025

350

mV

Low-level output voltage

Output differential voltage, |V_OD

|

225

425

V_OSOutput offset voltage, single-ended Common-mode voltage of OUTP and OUTM

1200

Output capacitance inside the device, from either output to

Output capacitance

ground

2

pF

(1) All LVDS and CMOS specifications are characterized, but not tested at production.

(2) I_Orefers to the LVDS buffer current setting, R_Lis the differential load resistance between the LVDS output pair.

TIMING CHARACTERISTICS – LVDS AND CMOS MODES⁽¹⁾

Typical values are at 25°C, min and max values are across the full temperature range T_MIN= –40°C to T_MAX= 85°C, AVDD =

DRVDD = 3.3 V, sampling frequency = 210 MSPS, sine wave input clock, 1.5 V_PPclock amplitude, C_L= 5 pF⁽²⁾, I_O= 3.5 mA,

R_L= 100 Ω⁽³⁾, no internal termination, unless otherwise noted.

For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this data

sheet.

PARAMETER

Aperture delay

TEST CONDITIONS

MIN

TYP

1.2

MAX

UNIT

ns

t_a

t_j

Aperture jitter

150

fs rms

Time to valid data after coming out of

STANDBY mode

100

Wake-up time

µs

Time to valid data after stopping and

restarting the input clock

clock

cycles

Latency

14

DDR LVDS MODE⁽⁴⁾

t_su

Data setup time⁽⁵⁾

Data valid ⁽⁶⁾to zero-cross of CLKOUTP

1.0

1.5

0.8

ns

Zero-cross of CLKOUTP to data becoming

invalid⁽⁶⁾

t_h

Data hold time⁽⁵⁾

0.35

(1) Timing parameters are specified by design and characterization and not tested in production.

(2) C_Lis the effective external single-ended load capacitance between each output pin and ground.

(3) I_Orefers to the LVDS buffer current setting; R_Lis the differential load resistance between the LVDS output pair.

(4) Measurements are done with a transmission line of 100 Ω characteristic impedance between the device and the load.

(5) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume

that the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear

as reduced timing margin.

(6) Data valid refers to logic high of +50 mV and logic low of –50 mV.

7

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TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued)

For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this data

sheet.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input clock rising edge zero-cross to

output clock rising edge zero-cross

t_PDI

Clock propagation delay⁽⁷⁾

3.7

4.4

5.1

ns

Duty cycle of differential clock,

(CLKOUTP-CLKOUTM)

80 ≤ Fs ≤ 210 MSPS

LVDS bit clock duty cycle

45%

50

50%

100

55%

200

Rise time measured from –50 mV to 50

mV

Fall time measured from 50 mV to –50 mV

1 ≤ Fs ≤ 210 MSPS

t_r,

t_f

Data rise time,

Data fall time

ps

Rise time measured from –50 mV to 50

mV

Fall time measured from 50 mV to –50 mV

1 ≤ Fs ≤ 210 MSPS

t_CLKRISE

,

Output clock rise time,

50

100

120

200

1

t_CLKFALLOutput clock fall time

Output clock jitter

Cycle-to-cycle jitter

ps pp

Output enable (OE) to valid data

delay

Time to valid data after OE becomes

active

t_OE

µs

PARALLEL CMOS MODE

Data valid⁽⁸⁾to 50% of CLKOUT rising

edge

ns

(5)

t_su

t_h

Data setup time

1.8

0.4

2.6

0.8

50% of CLKOUT rising edge to data

becoming invalid⁽¹⁰⁾

(9)

Data hold time

ns

Input clock rising edge zero-cross to 50%

of CLKOUT rising edge

t_PDI

Clock propagation delay⁽¹¹⁾

Output clock duty cycle

3.4

4.2

2.0

Duty cycle of output clock (CLKOUT)

80 ≤ Fs ≤ 210 MSPS

45%

Rise time measured from 20% to 80% of

DRVDD

Fall time measured from 80% to 20% of

DRVDD

t_r,

t_f

Data rise time,

Data fall time

0.8

0.4

1.5

0.8

ns

1 ≤ Fs ≤ 210 MSPS

Rise time measured from 20% to 80% of

DRVDD

Fall time measured from 80% to 20% of

DRVDD

t_CLKRISE

,

Output clock rise time,

t_CLKFALLOutput clock fall time

1.2

50

ns

1 ≤ Fs ≤ 210 MSPS

Output enable (OE) to valid data

delay

Time to valid data after OE becomes

active

t_OE

(7) To use the input clock as the data capture clock, it is necessary to delay the input clock by a delay (t_D) to get the desired setup and hold

times. Use either of these equations to calculate t_D:

Desired setup time = t_D- (t_PDI- t_su

Desired hold time = (t_PDI+ t_h) - t_D

)

(8) Data valid refers to logic high of 2 V and logic low of 0.8 V

(9) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume

that the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear

as reduced timing margin.

(10) Data valid refers to logic high of 2 V and logic low of 0.8 V

(11) To use the input clock as the data capture clock, it is necessary to delay the input clock by a delay (t_D) to get the desired setup and hold

times. Use either of these equations to calculate t_D:

Desired setup time = t_D- (t_PDI- t_su

Desired hold time = (t_PDI+ t_h) - t_D

)

8

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N+17

N+16

N+4

N+3

N+15

N+2

Sample

N

N+1

N+14

Input

Signal

t_a

CLKP

Input

Clock

CLKM

CLKOUTM

CLKOUTP

t_su

t_h

t_PDI

14 Clock Cycles

DDR

LVDS

Output Data

DXP, DXM

E

O

E

O

E

O

E

O

E

O

E

O

E

O

E

O

E

O

E

O

E – Even Bits D0,D2,D4,D6,D8,D10

O – Odd Bits D1,D3,D5,D7,D9,D11

N–14

N–13

N–12

N–11

N–10

N–1

N

N+1

N+2

t_PDI

CLKOUT

t_su

Parallel

CMOS

14 Clock Cycles

t_h

Output Data

D0–D11

N–14

N–13

N–12

N–11

N–10

N–1

N

N+1

N+2

Figure 1. Latency

9

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CLKM

CLKP

Input

Clock

t_PDI

CLKOUTP

CLKOUTM

Output

Clock

t_h

t_su

t_h

Dn^{(Note A)}

Dn+1^{(Note B)}

Output

Data Pair

Dn_Dn+1_P,

Dn_Dn+1_M

A. Dn – Bits D0, D2, D4, D6, D8, and D10

B. Dn+1 – Bits D1, D3, D5, D7, D9, and D11

Figure 2. LVDS Mode Timing

CLKM

Input

Clock

CLKP

t_PDI

Output

Clock

CLKOUT

t_h

t_su

Dn^{(Note A)}

Output

Data

Dn

A. Dn – Bits D0–D11

Figure 3. CMOS Mode Timing

10

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DEVICE PROGRAMMING MODES

ADS5527 offers flexibility with several programmable features that are easily configured.

The device can be configured independently using either parallel interface control or serial interface

programming.

In addition, the device supports a third configuration mode, where both the parallel interface and the serial

control registers are used. In this mode, the priority between the parallel and serial interfaces is determined by a

priority table (Table 2). If this additional level of flexibility is not required, the user can select either the serial

interface programming or the parallel interface control.

USING PARALLEL INTERFACE CONTROL ONLY

To control the device using parallel interface, keep RESET tied to high (DRVDD). Pins DFS, MODE, SEN,

SCLK, and SDATA are used to directly control certain modes of the ADC. The device is configured by

connecting the parallel pins to the correct voltage levels (as described in Table 3 to Table 7). There is no need

to apply reset.

In this mode, SEN, SCLK, and SDATA function as parallel interface control pins. Frequently used functions are

controlled in this mode—standby, selection between LVDS/CMOS output format, internal/external reference,

two's complement/straight binary output format, and position of the output clock edge.

Table 1 has a description of the modes controlled by the four parallel pins.

Table 1. Parallel Pin Definition

DFS

CONTROL MODES

DATA FORMAT and the LVDS/CMOS output interface

MODE

SEN

Internal or external reference

CLKOUT edge programmability

SCLK

SDATA

LOW SPEED mode control for low sampling frequencies (< 50 MSPS)

STANDBY mode – Global (ADC, internal references and output buffers are powered down)

USING SERIAL INTERFACE PROGRAMMING ONLY

To program using the serial interface, the internal registers must first be reset to their default values, and the

RESET pin must be kept low. In this mode, SEN, SDATA, and SCLK function as serial interface pins and are

used to access the internal registers of ADC. The registers are reset either by applying a pulse on the RESET

pin, or by a high setting on the <RST> bit (D1 in register 0x6C). The serial interface section describes the

register programming and register reset in more detail.

Since the parallel pins DFS and MODE are not used in this mode, they must be tied to ground.

USING BOTH THE SERIAL INTERFACE AND PARALLEL CONTROLS

For increased flexibility, a combination of serial interface registers and parallel pin controls (DFS, MODE) can

also be used to configure the device.

The serial registers must first be reset to their default values and the RESET pin must be kept low. In this mode,

SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC.

The registers are reset either by applying a pulse on RESET pin or by a high setting on the <RST> bit (D1 in

register 0x6C). The serial interface section describes the register programming and register reset in more detail.

The parallel interface control pins DFS and MODE are used and their function is determined by the appropriate

voltage levels as described in Table 6 and Table 7. The voltage levels are derived by using a resistor string as

illustrated in Figure 4. Since some functions are controlled using both the parallel pins and serial registers, the

priority between the two is determined by a priority table (Table 2).

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Table 2. Priority Between Parallel Pins and Serial Registers

FUNCTIONS SUPPORTED

PRIORITY

When using the serial interface, bit <REF> (register 0x6D, bit D4) controls this mode, ONLY

if the MODE pin is tied low.

MODE

Internal/External reference

DATA FORMAT

When using the serial interface, bit <DF> (register 0x63, bit D3) controls this mode, ONLY if

the DFS pin is tied low.

DFS

When using the serial interface, bit <ODI> (register 0x6C, bits D3-D4) controls LVDS/CMOS

selection independent of the state of DFS pin

LVDS/CMOS

AVDD

(2/3) AVDD

R

(2/3) AVDD

(1/3) AVDD

GND

AVDD

R

(1/3) AVDD

To Parallel Pin

Figure 4. Simple Scheme to Configure Parallel Pins

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DESCRIPTION OF PARALLEL PINS

Table 3. SCLK Control Pin

SCLK (Pin 29)

DESCRIPTION

0

LOW SPEED mode Disabled - Use for sampling frequencies above 50 MSPS.

LOW SPEED mode Enabled - Use for sampling frequencies below 50 MSPS.

DRVDD

Table 4. SDATA Control Pin

SDATA (Pin 28)

DESCRIPTION

0

Normal operation (Default)

DRVDD

STANDBY. This is a global power down, where ADC, internal references and the output buffers are powered down.

Table 5. SEN Control Pin

SEN (Pin 27)

0

DESCRIPTION

CMOS mode: CLKOUT edge later by (3/12)Ts ⁽¹⁾; LVDS mode: CLKOUT edge aligned with data transition

CMOS mode: CLKOUT edge later by (2/12)Ts ; LVDS mode: CLKOUT edge aligned with data transition

CMOS mode: CLKOUT edge later by (1/12)Ts ; LVDS mode: CLKOUT edge earlier by (1/12)Ts

Default CLKOUT position

(1/3)DRVDD

(2/3)DRVDD

DRVDD

(1) Ts = 1/Sampling Frequency

Table 6. DFS Control Pin

DFS (Pin 6)

DESCRIPTION

0

2's complement data and DDR LVDS output (Default)

2's complement data and parallel CMOS output

(1/3)DRVDD

(2/3)DRVDD

DRVDD

Offset binary data and parallel CMOS output

Offset binary data and DDR LVDS output

Table 7. MODE Control Pin

MODE (Pin 23)

0

DESCRIPTION

Internal reference

External reference

Internal reference

(1/3)AVDD

(2/3)AVDD

AVDD

SERIAL INTERFACE

The ADC has a set of internal registers, which can be accessed through the serial interface formed by pins SEN

(Serial interface Enable), SCLK (Serial Interface Clock), SDATA (Serial Interface Data) and RESET. After device

power-up, the internal registers must be reset to their default values by applying a high-going pulse on RESET

(of width greater than 10 ns).

Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge

of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge

when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data is loaded in

multiples of 16-bit words within a single active SEN pulse.

The first 8 bits form the register address and the remaining 8 bits form the register data.

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REGISTER INITIALIZATION

After power-up, the internal registers must be reset to their default values. This is done in one of two ways:

1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10 ns)

as shown in Figure 5.

OR

2. By applying software reset. Using the serial interface, set the <RST> bit (D1 in register 0x6C) to high.

This initializes the internal registers to their default values and then self-resets the <RST> bit to low. In

this case the RESET pin is kept low.

Register Address

Register Data

SDATA

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

t_(DH)

D1

D0

t_(SCLK)

t_(DSU)

SCLK

t_(SLOADH)

t_(SLOADS)

SEN

RESET

Figure 5. Serial Interface Timing Diagram

SERIAL INTERFACE TIMING CHARACTERISTICS

Typical values at 25°C, min and max values across the full temperature range T_MIN= –40°C to T_MAX= 85°C,

AVDD = DRVDD = 3.3 V (unless otherwise noted)

MIN

TYP

MAX

UNIT

t_SCLK

SCLK period

50

ns

SCLK duty cycle

50%

25

t_SLOADS

t_SLOADH

t_DSU

SEN to SCLK setup time

SCLK to SEN hold time

SDATA setup time

SDATA hold time

ns

25

t_DH

25

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RESET TIMING

Typical values at 25°C, min and max values across the full temperature range T_MIN= –40°C to T_MAX= 85°C,

AVDD = DRVDD = 3.3 V (unless otherwise noted)

PARAMETER

Power-on delay

Reset pulse width

Register write delay

Power-up time

TEST CONDITIONS

MIN

5

TYP

MAX

UNIT

ms

ns

t₁

Delay from power-up of AVDD and DRVDD to RESET pulse active

Pulse width of active RESET signal

t₂

10

25

t₃

Delay from RESET disable to SEN active

ns

t_PO

Delay from power-up of AVDD and DRVDD to output stable

6.5

ms

Power Supply

AVDD, DRVDD

t₁

RESET

t₂

t₃

SEN

NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset.

For parallel interface operation, RESET has to be tied permanently HIGH.

Figure 6. Reset Timing Diagram

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DESCRIPTION OF SERIAL REGISTERS

Table 8 gives a summary of all the modes that can be programmed through the serial interface.

Table 8. Serial Interface Register Map

REGISTER ADDRESS

REGISTER DATA

D4 D3 D2 D1 D0

DESCRIPTION

A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5

<STBY> – Global Power Down

NORMAL converter operation (Default after

reset)

0

1

0

1

0

1

0

STANDBY

<RST> – Software Reset

0

1

0

1

0

1

0

Resets all registers to default values

<DF> – Output Data Format

2's complement output format (Default after

reset)

0

1

0

1

0

1

0

Straight binary output format

<ODI> – Output Data Interface

DDR LVDS outputs (D4:D3 defaults to 00

after reset)

0

1

0

1

0

1

0

Parallel CMOS outputs

<REF> –Internal/External reference mode

0

1

0

1

0

1

0

Internal reference (Default after reset)

External reference – Force voltage on VCM

0

1

0

<TEST PATTERN> – Output test pattern on data outputs

0

1

0

1

0

1

0

1

0

1

0

Normal operation (Default after reset)

All zeros

All ones

Toggle pattern Alternate 1s and 0s on each

data output and across the data outputs.

0

1

0

1

0

1

0

1

0

1

0

Ramp pattern – Output data ramps from

0x0000 to 0x3FFF every clock cycle

Custom pattern. Write the custom pattern in

CUSTOM PATTERN registers A and B.

0

1

0

1

0

1

0

1

0

X

NOT USED

<CUSTOM PATTERN> – Output custom pattern on data outputs

0

1

0

1

0

1

0

D7 D6 D5

D4

D3

D2 D1 D0 CUSTOM PATTERN D7-D0

0

D11 D10 D9 D8 CUSTOM PATTERN D11-D8

<CLK GAIN> – Clock Buffer gain programmability, Gain decreases monotonically from Gain 4 to Gain 0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Gain 4

Gain 3

Gain 2

Gain 1 (Default after reset)

Gain 0 Minimum gain

<POWER SCALING> Power scaling vs sampling frequency. The ADC can be operated at reduced power at lower sampling rates

with no loss in performance.

0

1

0

1

0

1

0

1

0

1

0

1

0

Default Fs > 150 MSPS (Default after reset)

Power Mode 1 – 105 < Fs ≤ 150 MSPS

Power Mode 2 – 50 < Fs ≤ 105 MSPS

Power Mode 3 – Fs ≤ 50 MSPS

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Table 8. Serial Interface Register Map (continued)

REGISTER ADDRESS

REGISTER DATA

DESCRIPTION

A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5

D4

D3

D2 D1 D0

<GAIN> Gain programming - Channel gain can be programmed from 0 to 6 dB for SFDR/SNR trade-off. For each gain setting, the

input full-scale range has to be proportionally scaled. For 6 dB gain, the full-scale range will be 1 V_PPcompared to 2 V_PPat 0 dB

gain.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0 dB (Default after reset)

1 dB

2 dB

3 dB

4 dB

5 dB

6 dB

<LVDS CURRENT> – LVDS Output data and clock buffers nominal current programmability

0

1

0

1

0

1

0

1

3.5 mA (Default after reset)

2.5 mA

4.5 mA

1.75 mA

<CURRENT DOUBLE> – The output data and clock buffer currents are doubled from the value selected by the <LVDS CURRENT>

register.

value specified by <LVDS CURRENT>

(Default after reset)

0

1

0

1

0

1

0

1

0

2x data, 2x clock currents

1x data, 2x clock currents

2x data, 4x clock currents

<DATA TERM> Internal termination - Option to terminate the LVDS DATA buffers inside the ADC to improve signal integrity. By

default, internal termination is disabled.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

No termination (Default after reset)

325 Ω

200 Ω

125 Ω

170 Ω

120 Ω

100 Ω

75 Ω

<CLK TERM> Internal termination - Option to terminate the LVDS CLK buffers inside the ADC to improve signal integrity. By

default, internal termination is disabled.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

No termination (Default after reset)

325 Ω

200 Ω

125 Ω

170 Ω

120 Ω

100 Ω

75 Ω

(1)

<CLKOUT POSN CMOS> – Output clock rising edge programmability in CMOS mode

0

1

0

1

0

1

0

1

0

1

Default position

CLKOUT rising edge later by (1/12)Ts

CLKOUT rising edge later by (3/12)Ts

CLKOUT rising edge later by (2/12)Ts

(1) Ts = 1/Sampling Frequency

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Table 8. Serial Interface Register Map (continued)

REGISTER ADDRESS

REGISTER DATA

DESCRIPTION

A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5

D4

D3

D2 D1 D0

(2)

<CLKOUT POSN CMOS> – Output clock falling edge programmability in CMOS mode

0

1

0

1

0

1

0

1

0

1

0

1

Default position

CLKOUT falling edge later by (1/12)Ts

CLKOUT falling edge later by (3/12)Ts

CLKOUT falling edge later by (2/12)Ts

(2)

<CLKOUT POSN LVDS> – Output clock rising edge programmability in LVDS mode

0

1

0

1

0

1

Default position

CLKOUT rising edge earlier by (1/12)Ts

CLKOUT rising edge aligned with data

transition

0

1

0

1

0

1

0

1

CLKOUT rising edge aligned with data

transition

(2)

<CLKOUT POSN LVDS> – Output clock falling edge programmability in LVDS mode

0

1

0

1

0

1

0

1

Default position

CLKOUT falling edge earlier by (1/12)Ts

CLKOUT falling edge aligned with data

transition

0

1

0

1

0

1

0

1

0

1

CLKOUT falling edge aligned with data

transition

<LOW SPEED> – For low sampling frequency operation

DEFAULT SPEED mode - for 50 < Fs ≤ 210

MSPS

0

1

0

1

0

1

0

LOW SPEED mode - for 1 < Fs ≤ 50 MSPS

(2) Ts = 1/Sampling Frequency

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PIN CONFIGURATION (LVDS MODE)

RGZ PACKAGE

(TOP VIEW)

1

36

35

34

33

32

31

30

29

28

27

26

25

DRGND

DRVDD

OVR

DRGND

2

DRVDD

NC

3

4

CLKOUTM

CLKOUTP

DFS

NC

5

NC

6

NC

7

OE

RESET

SCLK

SDATA

SEN

8

AVDD

9

AGND

CLKP

10

11

12

CLKM

AVDD

AGND

Figure 7. LVDS Mode Pinout

PIN ASSIGNMENTS – LVDS Mode

TYPE

NUMBER

OF PINS

PIN NAME

DESCRIPTION

8, 18, 20,

22, 24, 26

AVDD

Analog power supply

I

6

9, 12, 14,

17, 19, 25

AGND

Analog ground

I

CLKP, CLKM

INP, INM

Differential clock input

I

10, 11

15, 16

2

Differential analog input

Internal reference mode – Common-mode voltage output.

External reference mode – Reference input. The voltage forced on this pin sets

the internal references.

VCM

IREF

I/O

I

13

21

1

Current-set resistor, 56.2-kΩ resistor to ground.

Serial interface RESET input.

When using the serial interface mode, the user MUST initialize internal registers

through hardware RESET by applying a high-going pulse on this pin, or by using

the software reset option. See the SERIAL INTERFACE section.

In parallel interface mode, the user has to tie the RESET pin permanently HIGH.

(SDATA and SEN are used as parallel pin controls in this mode)

The pin has an internal 100-kΩ pull-down resistor.

RESET

I

30

1

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PIN CONFIGURATION (LVDS MODE) (continued)

PIN ASSIGNMENTS – LVDS Mode (continued)

TYPE

NUMBER

OF PINS

PIN NAME

DESCRIPTION

This pin functions as serial interface clock input when RESET is low.

It functions as LOW SPEED control pin when RESET is tied high. Tie SCLK to

LOW for Fs > 50 MSPS and SCLK to HIGH for Fs ≤ 50 MSPS. See Table 3.

The pin has an internal 100-kΩ pull-down resistor.

SCLK

SDATA

SEN

I

29

28

27

1

This pin functions as serial interface data input when RESET is low. It functions

as STANDBY control pin when RESET is tied high.

I

See Table 4 for detailed information.

The pin has an internal 100 kΩ pull-down resistor.

This pin functions as serial interface enable input when RESET is low. It functions

as CLKOUT edge programmability when RESET is tied high. See Table 5 for

detailed information.

The pin has an internal 100-kΩ pull-up resistor to DRVDD.

Output buffer enable input, active high. The pin has an internal 100-kΩ pull-up

resistor to DRVDD.

OE

I

7

6

1

Data Format Select input. This pin sets the DATA FORMAT (Twos complement or

Offset binary) and the LVDS/CMOS output mode type. See Table 6 for detailed

information.

DFS

MODE

Mode select input. This pin selects the Internal or External reference mode. See

Table 7 for detailed information.

23

CLKOUTP

CLKOUTM

D0_D1_P

D0_D1_M

D2_D3_P

D2_D3_M

D4_D5_P

D4_D5_M

D6_D7_P

D6_D7_M

D8_D9_P

D8_D9_M

D10_D11_P

D10_D11_M

OVR

Differential output clock, true

O

I

5

4

1

2

Differential output clock, complement

Differential output data D0 and D1 multiplexed, true

Differential output data D0 and D1 multiplexed, complement.

Differential output data D2 and D3 multiplexed, true

Differential output data D2 and D3 multiplexed, complement

Differential output data D4 and D5 multiplexed, true

Differential output data D4 and D5 multiplexed, complement

Differential output data D6 and D7 multiplexed, true

Differential output data D6 and D7 multiplexed, complement

Differential output data D8 and D9 multiplexed, true

Differential output data D8 and D9 multiplexed, complement

Differential output data D10 and D11 multiplexed, true

Differential output data D10 and D11 multiplexed, complement

Out-of-range indicator, CMOS level signal

38

37

40

39

42

41

44

43

46

45

48

47

3

DRVDD

Digital and output buffer supply

2, 35

1, 36

DRGND

Digital and output buffer ground

I

31, 32, 33,

34

NC

Do not connect

4

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PIN CONFIGURATION (CMOS MODE)

RGZ PACKAGE

(TOP VIEW)

1

36

35

34

33

32

31

30

29

28

27

26

25

DRGND

DRVDD

OVR

DRGND

DRVDD

NC

2

3

4

UNUSED

CLKOUT

DFS

NC

5

NC

6

NC

7

OE

RESET

SCLK

SDATA

SEN

8

AVDD

AGND

CLKP

9

10

11

12

CLKM

AGND

AVDD

AGND

Figure 8. CMOS Mode Pinout

PIN ASSIGNMENTS – CMOS Mode

TYPE

NUMBER

OF PINS

PIN NAME

AVDD

DESCRIPTION

8, 18, 20,

22, 24, 26

Analog power supply

Analog ground

I

6

9, 12, 14, 17,

19, 25

AGND

I

CLKP, CLKM Differential clock input

I

10, 11

15, 16

2

INP, INM

Differential analog input

Internal reference mode – Common-mode voltage output.

External reference mode – Reference input. The voltage forced on this pin sets

the internal references.

VCM

I/O

I

13

21

1

IREF

Current-set resistor, 56.2-kΩ resistor to ground.

Serial interface RESET input.

When using the serial interface mode, the user MUST initialize internal registers

through hardware RESET by applying a high-going pulse on this pin, or by using

the software reset option. See the SERIAL INTERFACE section.

RESET

SCLK

I

30

29

1

In parallel interface mode, the user has to tie RESET pin permanently HIGH.

(SDATA and SEN are used as parallel pin controls in this mode).

The pin has an internal 100-kΩ pull-down resistor.

This pin functions as serial interface clock input when RESET is low.

It functions as LOW SPEED control pin when RESET is tied high. Tie SCLK to

LOW for Fs > 50 MSPS and SCLK to HIGH for Fs ≤ 50 MSPS. See Table 3.

The pin has an internal 100-kΩ pull-down resistor.

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PIN CONFIGURATION (CMOS MODE) (continued)

PIN ASSIGNMENTS – CMOS Mode (continued)

NUMBER

OF PINS

PIN NAME

DESCRIPTION

TYPE

This pin functions as serial interface data input when RESET is low. It functions as

STANDBY control pin when RESET is tied high.

SDATA

SEN

I

28

27

1

See Table 4 for detailed information.

The pin has an internal 100 kΩ pull-down resistor.

This pin functions as serial interface enable input when RESET is low. It functions

as CLKOUT edge programmability when RESET is tied high. See Table 5 for

detailed information.

The pin has an internal 100-kΩ pull-up resistor to DRVDD.

Output buffer enable input, active high. The pin has an internal 100-kΩ pull-up

resistor to DRVDD.

OE

I

7

6

1

Data Format Select input. This pin sets the DATA FORMAT (Twos complement or

Offset binary) and the LVDS/CMOS output mode type. See Table 6 for detailed

information.

DFS

MODE

Mode select input. This pin selects the internal or external reference mode. See

Table 7 for detailed information.

23

CLKOUT

D0

CMOS output clock

O

I

5

37

38

39

40

41

42

43

44

45

46

47

48

3

1

2

1

CMOS output data D0

D1

CMOS output data D1

D2

CMOS output data D2

D3

CMOS output data D3

D4

CMOS output data D4

D4

CMOS output data D5

D6

CMOS output data D6

D7

CMOS output data D7

D8

CMOS output data D8

D9

CMOS output data D9

D10

D11

OVR

DRVDD

DRGND

UNUSED

CMOS output data D10

CMOS output data D11

Out-of-range indicator, CMOS level signal

Digital and output buffer supply

Digital and output buffer ground

Unused pin in CMOS mode

2, 35

1, 36

4

I

31, 32, 33,

34

NC

Do not connect

4

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TYPICAL CHARACTERISTICS

All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 210 MSPS, sine wave input clock, 1.5 V_PPdifferential

clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS

data output (unless otherwise noted)

FFT for 30 MHz INPUT SIGNAL

FFT for 70 MHz INPUT SIGNAL

0

-20

0

-20

SFDR = 85.57 dBc,

SNR = 70.76 dBFS,

SINAD = 70.46 dBFS

SFDR = 88.99 dBc,

SNR = 70.63 dBFS,

SINAD = 70.4 dBFS

-40

-60

-80

-100

-120

-140

-120

-140

20 30 40 50 60 70 80 90 100

0

10

0

10

f - Frequency - MHz

Figure 9.

Figure 10.

FFT for 100 MHz INPUT SIGNAL

FFT for 170 MHz INPUT SIGNAL

0

-20

0

-20

SFDR = 81.61 dBc,

SNR = 70.3 dBFS,

SINAD = 69.58 dBFS

SFDR = 82.94 dBc,

SNR = 69.77 dBFS,

SINAD = 69.26 dBFS

-40

-60

-80

-100

-120

-140

-120

-140

20 30 40 50 60 70 80 90 100

10

f - Frequency - MHz

Figure 11.

Figure 12.

FFT for 220 MHz INPUT SIGNAL

FFT for 300 MHz INPUT SIGNAL

0

-20

0

-20

SFDR = 74.59 dBc,

SNR = 68.08 dBFS,

SINAD = 66.52 dBFS

SFDR = 80.94 dBc,

SNR = 69.38 dBFS,

SINAD = 68.86 dBFS

-40

-60

-80

-100

-120

-140

-120

-140

20 30 40 50 60 70 80 90 100

10

f - Frequency - MHz

Figure 13.

Figure 14.

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TYPICAL CHARACTERISTICS (continued)

All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 210 MSPS, sine wave input clock, 1.5 V_PPdifferential

clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS

data output (unless otherwise noted)

FFT for 400 MHz INPUT SIGNAL

FFT for 600 MHz INPUT SIGNAL

0

-20

0

-20

SFDR = 70.96 dBc,

SNR = 67.31 dBFS,

SINAD = 64.4 dBFS

SFDR = 65.51 dBc,

SNR = 65.17 dBFS,

SINAD = 60.97 dBFS

-40

-60

-80

-100

-120

-140

-120

-140

20 30 40 50 60 70 80 90 100

0

10

0

10

f - Frequency - MHz

Figure 15.

Figure 16.

INTERMODULATION DISTORTION (IMD) vs FREQUENCY

0

f

= 50 MHz, -7 dBFS,

= 46 MHz, -7 dBFS,

f

= 190.1 MHz, -7 dBFS,

= 185 MHz, -7 dBFS,

IN1

IN2

IN1

IN2

-20

-40

-20

-40

SFDR = 94.5 dBFS,

2-Tone IMD, 91.1 dBFS

SFDR = 91 dBFS,

2-Tone IMD, 86.5 dBFS

-60

-80

-100

-120

-140

-120

-140

20 30 40 50 60 70 80 90 100

0

10

0

10

f - Frequency - MHz

Figure 17.

Figure 18.

SFDR vs INPUT FREQUENCY

SNR vs INPUT FREQUENCY

73

72

71

70

69

68

67

90

86

82

78

74

70

66

LVDS Mode

66

65

62

0

50 100 150 200 250 300 350 400

f_IN− Input Frequency − MHz

50

100 150 200 250 300 350 400

f

- Input Frequency - MHz

IN

Figure 19.

Figure 20.

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TYPICAL CHARACTERISTICS (continued)

All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 210 MSPS, sine wave input clock, 1.5 V_PPdifferential

clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS

data output (unless otherwise noted)

SNR vs INPUT FREQUENCY

SFDR vs GAIN

73

72

71

70

69

68

67

96

92

88

1 dB

2 dB

3 dB

CMOS Mode

84

80

5 dB

6 dB

4 dB

76

72

68

0 dB

66

65

0

50

100

150

200

250

300

0

50

100 150 200 250 300 350 400

f_IN− Input Frequency − MHz

f

- Input Frequency - MHz

IN

Figure 21.

Figure 22.

SNR vs GAIN

PERFORMANCE vs AVDD

74

72

70

68

92

74

0 dB

90

73

1 dB

2 dB 3 dB

SFDR

72

F_IN= 70 MHz

88

86

DRV_DD= 3.3 V

71

SNR

70

84

82

5 dB

66

64

4 dB

69

6 dB

3

3.1

3.2

AV

3.3

3.4

3.5

3.6

- Supply Voltage - V

0

50

100 150 200 250 300 350 400

f_IN− Input Frequency − MHz

DD

Figure 23.

Figure 24.

PERFORMANCE vs DRVDD

PERFORMANCE vs TEMPERATURE

74

90

74

92

f_IN= 70 MHz

SFDR

73

72

71

88

86

73

72

90

88

SFDR

SNR

f_IN= 70 MHz

AV_DD= 3.3 V

84

71

86

SNR

82

80

70

69

70

69

84

82

−40

−15

10

35

50

85

3.0

3.1

3.2

3.3

3.4

3.5

3.6

T_A− Free-Air Temperature − ^oC

DRV_DD− Supply Voltage − V

Figure 25.

Figure 26.

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TYPICAL CHARACTERISTICS (continued)

All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 210 MSPS, sine wave input clock, 1.5 V_PPdifferential

clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS

data output (unless otherwise noted)

SNR vs SAMPLING FREQUENCY

ACROSS POWER SCALING MODES

POWER DISSIPATION vs

SAMPLING FREQUENCY

1.24

1.18

1.12

73

72

71

70

69

68

67

LVDS Mode

f_IN= 70 MHz

Default

1.06

1.00

0.94

0.88

0.82

0.76

Power Mode 1

Power Mode 3

Power Mode 2

66

65

0.70

0.64

Power Mode 3

0

20 40 60 80 100 120 140 160 180 200 220

F_S− Sampling Frequency − MSPS

40

60

80 100 120 140 160 180 200 220

F_S− Sampling Frequency − MSPS

Figure 27.

Figure 28.

PERFORMANCE vs INPUT AMPLITUDE

PERFORMANCE vs CLOCK AMPLITUDE

105

74

73

72

71

70

69

68

67

66

89

75

95

85

75

65

55

45

35

25

SFDR

74

85

81

SFDR (dBFS)

SNR (dBFS)

73

f

= 70 MHz

IN

Sine Wave Input Clock

72

77

73

69

SFDR (dBc)

71

70

SNR

f_IN= 70 MHz

−40

−50

−30

−20

−10

0

0.3 0.5 0.8 1.1 1.3 1.5 1.8 2.1 2.3 2.5 2.8

Clock Amplitude - V

PP

Input Amplitude − dBFS

Figure 29.

Figure 30.

OUTPUT NOISE HISTOGRAM WITH

INPUTS TIED TO COMMON-MODE

PERFORMANCE vs INPUT CLOCK DUTY CYCLE

-84

-86

74

100

RMS Noise = 0.35 LSB

f_IN= 10 MHz

90

80

70

60

50

40

30

20

73

SFDR

72

-88

-90

71

SNR

70

-92

-94

10

0

69

35

40

45

50

55

60

65

Input Clock Duty Cycle − %

Output Code

Figure 31.

Figure 32.

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TYPICAL CHARACTERISTICS (continued)

All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 210 MSPS, sine wave input clock, 1.5 V_PPdifferential

clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS

data output (unless otherwise noted)

PERFORMANCE IN EXTERNAL REFERENCE MODE

COMMON-MODE REJECTION RATIO vs FREQUENCY

-35

86

85

74

-40

SFDR

73

-45

-50

-55

-60

72

84

83

71

SNR

70

69

82

81

-65

-70

1.4

1.45

1.5

1.55

1.6

0

20

40

60

80

100

Voltage Forced on the CM Pin − V

f - Frequency of AC Common-Mode Voltage - MHz

Figure 33.

Figure 34.

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TYPICAL CHARACTERISTICS (continued)

All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 210 MSPS, sine wave input clock, 1.5 V_PPdifferential

clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS

data output (unless otherwise noted)

200

180

160

140

120

100

80

100

200

65

300

400

500

600

700

73

f

- Input Frequency - MHz

IN

62

63

64

66

67

68

69

70

71

72

SNR - dBFS

Figure 35. SNR Contour in dBFS

210

200

180

160

140

120

100

80

65

100

200

300

400

500

80

600

85

700

90

f

- Input Frequency - MHz

IN

55

60

65

70

75

SFDR - dBc

Figure 36. SFDR Contour in dBc

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APPLICATION INFORMATION

THEORY OF OPERATION

ADS5527 is a low power 12-bit 210 MSPS pipeline ADC in a CMOS process. ADS5527 is based on switched

capacitor technology and runs off a single 3.3-V supply. The conversion process is initiated by a rising edge of

the external input clock. Once the signal is captured by the input sample and hold, the input sample is

sequentially converted by a series of lower resolution stages, with the outputs combined in a digital correction

logic block. At every clock edge, the sample propagates through the pipeline resulting in a data latency of 14

clock cycles. The output is available as 12-bit data, in DDR LVDS or CMOS and coded in either straight offset

binary or binary 2’s complement format.

ANALOG INPUT

The analog input consists of a switched-capacitor based differential sample and hold architecture, shown in

Figure 37.

This differential topology results in good ac-performance even for high input frequencies at high sampling rates.

The INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V available on VCM

pin 13. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM +

0.5 V and VCM – 0.5 V, resulting in a 2-V_PPdifferential input swing. The maximum swing is determined by the

internal reference voltages REFP (2.5 V nominal) and REFM (0.5 V, nominal).

Sampling

Switch

Lpkg

6 nH

Sampling

Capacitor

R-C-R Filter

INP

Ron

15 W

10 W

Csamp

2.4 pF

Cbond

2 pF

Cpar2

1 pF

50 W

1.6 pF

50 W

Resr

200 W

Ron

10 W

Cpar1

0.8 pF

Lpkg

6 nH

Csamp

2.4 pF

Ron

15 W

10 W

INM

Sampling

Capacitor

Cbond

2 pF

Cpar2

1 pF

Resr

200 W

Sampling

Switch

Figure 37. Input Stage

The input sampling circuit has a high 3-dB bandwidth that extends up to 800 MHz (measured from the input pins

to the voltage across the sampling capacitors)

Drive Circuit Requirements

The input sampling circuit of the ADS5527 has a high 3-dB analog bandwidth of 800 MHz making it possible to

sample input signals up to very high frequencies. To get best performance, it is recommended to have an

external R-C-R filter across the input pins (Figure 38). This helps to filter the glitches due to the switching of the

sampling capacitors. The R-C-R filter has to be designed to provide adequate filtering (for good performance)

and at the same time ensure sufficient bandwidth over the desired frequency range.

In addition, it is recommended to have a 15-Ω series resistor on each input line to damp out ringing caused by

the package parasitic. At higher input frequencies (> 100 MHz), a lower series resistance around 5 Ω to 10 Ω

should be used. It is also necessary to present low impedance (< 50 Ω) for the common-mode switching

currents. For example, this could be achieved by using two resistors from each input terminated to the

common-mode voltage (Vcm).

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APPLICATION INFORMATION (continued)

Using 10-Ω series resistance and 25 Ω-3.3 pF-25 Ω as the R-C-R filter, high effective bandwidth (700 MHz) can

be achieved, (see Figure 39, transfer function from the analog input pins to the voltage across the sampling

capacitors).

In addition to the above ADC requirements, the drive circuit may have to be designed to provide a low insertion

loss over the desired frequency range and matched impedance to the source. For this, the ADC input

impedance has to be taken into account (Figure 40).

Example Drive Circuits

A suitable configuration using RF transformers and including the R-C-R filter is shown in Figure 38. Note the

15-Ω series resistors and the low common-mode impedance (using 33-Ω resistors terminated to VCM).

Z and TFADC

i

15 W

(Note A)

WBC1-1TLB

0.1 mF

INP

100 W

25 W

3.3 pF

25 W

33 W

0.1 mF

INM

15 W

(Note A)

1:1

VCM

A. Use lower series resistance (≈ 5 Ω to 10 Ω) at high input frequencies (> 100 MHz)

Figure 38. Example Drive Circuit With RF Transformers

2

1

0

-1

-2

-3

-4

-5

-6

0

100

200 300 400

500 600 700

800 900 1000

f − Frequency − MHz

Figure 39. Analog Input Bandwidth, TFADC (Actual Silicon Data)

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APPLICATION INFORMATION (continued)

500

450

400

350

300

250

200

150

100

50

0

100

200 300 400

500 600 700

800 900 1000

f − Frequency − MHz

Figure 40. Input Impedance, Z_I

Using RF transformers

For optimum performance, the analog inputs have to be driven differentially. This improves the common-mode

noise immunity and even order harmonic rejection. The single-ended signal is fed to the primary winding of the

RF transformer. The transformer is terminated on the secondary side. Putting the termination on the secondary

side helps to shield the kickbacks caused by the sampling circuit from the RF transformer’s leakage

inductances. The termination is accomplished by two resistors connected in series, with the center point

connected to the 1.5 V common-mode (VCM pin 13).

At higher input frequencies, the mismatch in the transformer parasitic capacitance (between the windings)

results in degraded even-order harmonic performance. Connecting two identical RF transformers back to back

helps minimize this mismatch and good performance is obtained for high frequency input signals. An additional

termination resistor pair (Figure 38) may be required between the two transformers to improve the balance

between the P and M sides. The center point of this termination must be connected to ground. (Note that the

drive circuit has to be tuned to account for this additional termination, to get the desired S11 and impedance

match).

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APPLICATION INFORMATION (continued)

Input Common-Mode

To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1-µF low-inductance capacitor

connected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADC

sinks a common-mode current in the order of 342 µA (at 210 MSPS). Equation 1 describes the dependency of

the common-mode current and the sampling frequency.

(342 mA) x Fs

210 MSPS

This equation helps to design the output capability and impedance of the CM driving circuit accordingly.

Reference

ADS5527 has built-in internal references REFP and REFM, requiring no external components. Design schemes

are used to linearize the converter load seen by the references; this and the integration of the requisite

reference capacitors on-chip eliminates the need for external decoupling. The full-scale input range of the

converter can be controlled in the external reference mode as explained below. The internal or external

reference modes can be selected by controlling the MODE pin 23 (see Table 7 for details) or by programming

the serial interface register bit <REF>.

INTREF

Internal

Reference

VCM

INTREF

EXTREF

REFM

REFP

Figure 41. Reference Section

Internal Reference

When the device is in internal reference mode, the REFP and REFM voltages are generated internally.

Common-mode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analog

input pins.

External Reference

When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on

the VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential

input voltage corresponding to full-scale is given by Equation 2.

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APPLICATION INFORMATION (continued)

Full−scale differential input pp + (Voltage forced on VCM) 1.33

In this mode, the 1.5 V common-mode voltage to bias the input pins has to be generated externally. There is no

change in performance compared to internal reference mode.

Low Sampling Frequency Operation

For best performance at high sampling frequencies, ADS5527 uses a clock generator circuit to derive internal

timing for the ADC. The clock generator operates from 210 MSPS down to 50 MSPS in the DEFAULT SPEED

mode. The ADC enters this mode after applying reset (with serial interface configuration) or by tying SCLK pin to

low (with parallel configuration).

For low sampling frequencies (below 50 MSPS), the ADC must be put in the LOW SPEED mode. This mode

can be entered by:

•

setting the register bit <LOW SPEED> through the serial interface, OR

tying the SCLK pin to high (see Table 3) using the parallel configuration.

Clock Input

ADS5527 clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS), with

little or no difference in performance between configurations. The common-mode voltage of the clock inputs is

set to VCM using internal 5-kΩ resistors as shown in Figure 42. This allows the use of transformer-coupled drive

circuits for sine wave clock, or ac-coupling for LVPECL, LVDS clock sources (Figure 43 and Figure 44)

VCM

5 kW

CLKP

CLKM

Figure 42. Internal Clock Buffer

For best performance, it is recommended to drive the clock inputs differentially, reducing susceptibility to

common-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with

0.1-µF capacitors, as shown in Figure 43.

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APPLICATION INFORMATION (continued)

0.1 mF

CLKP

Differential Sine-Wave

or PECL or LVDS

Clock Input

0.1 mF

CLKM

Figure 43. Differential Clock Driving Circuit

A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin 11) connected to ground with

a 0.1-µF capacitor, as shown in Figure 44.

0.1 mF

CMOS Clock Input

CLKP

0.1 mF

CLKM

Figure 44. Single-Ended Clock Driving Circuit

For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode

noise. For high input frequency sampling, the use a clock source with very low jitter is recommended. Bandpass

filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a

non-50% duty cycle clock input. Figure 31 shows the performance variation of the ADC versus clock duty cycle

Clock Buffer Gain

When using a sinusoidal clock input, the noise contributed by clock jitter improves as the clock amplitude is

increased. Therefore, using a large amplitude clock is recommended. In addition, the clock buffer has a

programmable gain option to amplify the input clock. The clock buffer gain can be set by programming the

register bits <CLK GAIN>. The clock buffer gain decreases monotonically from Gain 4 to Gain 0 settings.

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APPLICATION INFORMATION (continued)

Table 9. Clock Buffer Gain Programming

REGISTER DATA

REGISTER ADDRESS

A5 A4 A3 A2

<CLK GAIN> – Clock buffer gain programmability, Gain decreases monotonically from Gain 4 to Gain 0

DESCRIPTION

A7

A6

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Gain 4

Gain 3

Gain 2

Gain 1 Default gain

Gain 0 Minimum gain

Programmable Gain

ADS5527 has programmable gain from 0 dB to 6 dB in steps of 1 dB. The corresponding full-scale input range

varies from 2 V_PPdown to 1 V_PP, with 0 dB being the default gain. At high IF, this is especially useful as the

SFDR improvement is significant with marginal degradation in SNR.

The gain can be programmed using the serial interface (bits D3-D0 in register 0x68).

Table 10. Programmable Gain

REGISTER ADDRESS

A5 A4 A3 A2

REGISTER DATA

D5 D4 D3 D2

DESCRIPTION

A7

A6

A1

A0

D7

D6

D1

D0

<GAIN> Gain programming - Channel gain can be programmed from 0 to 6 dB for SFDR/SNR trade-off. For each gain setting, the

input full-scale range has to be proportionally scaled. For 6 dB gain, the full-scale range will be 1 V_PPcompared to 2 V_PPat 0 dB

gain.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0 dB ^{Default after reset}

1 dB

2 dB

3 dB

4 dB

5 dB

6 dB

Power Down

ADS5527 has three power-down modes – global STANDBY, output buffer disabled, and input clock stopped.

Global STANDBY

This mode can be initiated by controlling SDATA (pin 28) or by setting the register bit <STBY> through the serial

interface. In this mode, the A/D converter, reference block and the output buffers are powered down and the

total power dissipation reduces to about 100 mW. The output buffers are in high impedance state. The wake-up

time from the global power down to data becoming valid normal mode is maximum 100 µs.

Output Buffer Disable

The output buffers can be disabled using OE pin 7 in both the LVDS and CMOS modes, reducing the total

power by about 100 mW. With the buffers disabled, the outputs are in high impedance state. The wake-up time

from this mode to data becoming valid in normal mode is maximum 1 µs in LVDS mode and 50 ns in CMOS

mode.

Input Clock Stop

The converter enters this mode when the input clock frequency falls below 1 MSPS. The power dissipation is

about 100 mW and the wake-up time from this mode to data becoming valid in normal mode is maximum

100 µs.

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Power Scaling Modes

ADS5527 has a power scaling mode in which the device can be operated at reduced power levels at lower

sampling frequencies with no difference in performance. (See Figure 27)⁽¹⁾There are four power scaling modes

for different sampling clock frequency ranges, using the serial interface register bits <POWER SCALING>. Only

the AVDD power is scaled, leaving the DRVDD power unchanged.

Table 11. Power Scaling vs Sampling Speed

Sampling Frequency

MSPS

Analog Power

(Typical)

Power Scaling Mode

Analog Power in Default Mode

> 150

105 to 150

50 to 105

< 50

Default

1010 mW at 210 MSPS

841 mW at 150 MSPS

670 mW at 105 MSPS

525 mW at 50 MSPS

1010 mW at 210 MSPS

917 mW at 150 MSPS

830 mW at 105 MSPS

760 mW at 50 MSPS

Power Mode 1

Power Mode 2

Power Mode 3

(1) The performance in the power scaling modes is from characterization and not tested in production.

REGISTER ADDRESS REGISTER DATA

A5 A4 A3 A2 D5 D4 D3 D2

DESCRIPTION

A7

A6

A1

A0

D7

D6

D1

D0

<POWER SCALING> Power scaling vs sampling frequency. The ADC can be operated at reduced power at lower sampling rates

with no loss in performance.

0

1

0

1

0

1

0

1

0

Default Fs > 150 MSPS ^{Default after}

reset

Power Mode1 105 < Fs ≤ 150

MSPS

0

1

0

1

0

1

0

1

0

Power Mode2 50 < Fs ≤ 105

MSPS

0

1

0

1

0

1

0

1

0

Power Mode3 Fs ≤ 50 MSPS

Power Supply Sequence

During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are

separated inside the device. Externally, they can be driven from separate supplies or from a single supply.

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Digital Output Information

ADS5527 provides 12-bit data, an output clock synchronized with the data and an out-of-range indicator that

goes high when the output reaches the full-scale limits. In addition, output enable control (OE pin 7) is provided

to power down the output buffers and put the outputs in high-impedance state.

Output Interface

Two output interface options are available – Double Data Rate (DDR) LVDS and parallel CMOS. They can be

selected using the DFS (see Table 6) or the serial interface register bit <ODI>.

DDR LVDS Outputs

In this mode, the 12 data bits and the output clock are available as LVDS (Low Voltage Differential Signal)

levels. Two successive data bits are multiplexed and output on each LVDS differential pair as shown in

Figure 45. So, there are 6 LVDS output pairs for the 12 data bits and 1 LVDS output pair for the output clock.

Pins

CLKOUTP

Output Clock

CLKOUTM

D0_D1_P

Data Bits D0. D1

D0_D1_M

D2_D3_P

Data Bits D2, D3

D2_D3_M

D4_D5_P

Data Bits D4, D5

D4_D5_M

D6_D7_P

Data Bits D6, D7

D6_D7_M

D8_D9_P

Data Bits D8, D9

D8_D9_M

D10_D11_P

Data Bits D10, D11

D10_D11_M

OVR

Out-of-Range Indicator

Figure 45. DDR LVDS Outputs

Even data bits D0, D2, D4, D6, D8, and D10 are output at the falling edge of CLKOUTP and the odd data bits

D1, D3, D5, D7, D9, and D11 are output at the rising edge of CLKOUTP. Both the rising and falling edges of

CLKOUTP have to be used to capture all the 12 data bits (see Figure 46).

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CLKOUTP

CLKOUTM

D0_D1_P,

D0_D1_M

D0

D2

D1

D3

D5

D7

D9

D11

D0

D2

D1

D3

D5

D7

D9

D11

D2_D3_P,

D2_D3_M

D4_D5_P,

D4_D5_M

D4

D6_D7_P,

D6_D7_M

D6

D8_D9_P,

D8_D9_M

D8

D10_D11_P,

D10_D11_M

D10

Sample N

Sample N+1

Figure 46. DDR LVDS Interface

LVDS Buffer Current Programmability

The default LVDS buffer output current is 3.5 mA. When terminated by 100 Ω, this results in a 350-mV

single-ended voltage swing (700-mV_PPdifferential swing). The LVDS buffer currents can also be programmed to

2.5 mA, 4.5 mA, and 1.75 mA using the serial interface. In addition, there exists a current double mode, where

this current is doubled for the data and output clock buffers.

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Table 12. LVDS Buffer Currents Programming

REGISTER ADDRESS

REGISTER DATA

DESCRIPTION

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

<LVDS CURRENT> – Output data and clock buffers current programmability

0

1

0

1

0

1

0

1

3.5 mA ^{Default after reset}

2.5 mA

4.5 mA

1.75 mA

<CURRENT DOUBLE> – The output data and clock buffer currents are doubled from the value selected by the <LVDS CURRENT>

register.

Value specified by <LVDS

0

1

0

CURRENT>^{Default after reset}

2x data, 2x clock currents

1x data, 2x clock currents

2x data, 4x clock currents

0

1

0

1

0

1

0

LVDS Buffer Internal Termination

An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially

terminated inside the device. The termination resistences available are – 325, 200, and 170 Ω (nominal with

±20% variation). Any combination of these three terminations can be programmed; the effective termination is

the parallel combination of the selected resistences. This results in eight effective terminations from open (no

termination) to 75 Ω.

The internal termination helps to absorb any reflections coming from the receiver end, improving the signal

integrity. With 100-Ω internal and 100-Ω external termination, the voltage swing at the receiver end is halved

(compared to no internal termination). The voltage swing can be restored by using the LVDS current double

mode (see Table 12). Figure 47 shows the eye diagram of one of the LVDS data outputs with a 10-pF load

capacitance (from each pin to ground) and 100-Ω internal termination enabled.

Figure 47. Eye Diagram of LVDS Data Output With Internal Termination

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Table 13. Programming Internal Termination for LVDS Data and Clock

REGISTER ADDRESS

A5 A4 A3 A2

REGISTER DATA

D5 D4 D3 D2

DESCRIPTION

A7

A6

A1

A0

D7

D6

D1

D0

<DATA TERM> Internal termination - Option to terminate the LVDS DATA buffers inside the ADC to improve signal integrity. By

default, internal termination is disabled.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

No termination ^{Default after reset}

325 Ω

200 Ω

125 Ω

170 Ω

120 Ω

100 Ω

75 Ω

<CLK TERM> Internal termination – Option to terminate the LVDS CLK buffers inside the ADC to improve signal integrity. By

default, internal termination is disabled.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

No termination ^{Default after reset}

325 Ω

200 Ω

125 Ω

170 Ω

120 Ω

100 Ω

75 Ω

Parallel CMOS

In this mode, the 12 data outputs and the output clock are available as 3.3-V CMOS voltage levels. Each data

bit and the output clock is available on a separate pin in parallel. By default, the data outputs are valid during the

rising edge of the output clock. The output clock is CLKOUT (pin 5).

Output Clock Position Programmability

In both the LVDS and CMOS modes, the output clock can be moved around its default position. This can be

done using SEN pin 27 (as described in Table 5) or using the serial interface register bits <CLKOUT POSN>.

Using this allows to trade-off the setup and hold times leading to reliable data capture. There also exists an

option to align the output clock edge with the data transition.

Note that programming the output clock position also affects the clock propagation delay times.

Table 14. CLKOUT Position Programing

REGISTER ADDRESS

A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4

<CLKOUT POSN CMOS> – Output clock rising edge programmability in CMOS mode

REGISTER DATA

DESCRIPTION

A7

D3 D2 D1 D0

0

1

0

1

0

1

0

1

0

1

Default position

Output clock rising edge later by (1/12)Ts

Output clock rising edge later by (3/12)Ts

Output clock rising edge later by (2/12)Ts

<CLKOUT POSN CMOS> – Output clock falling edge programmability in CMOS mode

0

1

0

1

0

1

0

1

0

1

0

1

Default position

Output clock falling edge later by (1/12)Ts

Output clock falling edge later by (3/12)Ts

Output clock falling edge later by (2/12)Ts

40

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Table 14. CLKOUT Position Programing (continued)

REGISTER ADDRESS

REGISTER DATA

DESCRIPTION

A7

A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4

D3

D2 D1 D0

<CLKOUT POSN LVDS> – Output clock rising edge programmability in LVDS mode

0

1

0

1

0

1

0

1

0

1

Default position

Output clock rising edge earlier by (1/12)Ts

Output clock rising edge aligned with data

transition

0

1

0

1

0

1

Output clock rising edge aligned with data

transition

<CLKOUT POSN LVDS> – Output clock falling edge programmability in LVDS mode

0

1

0

1

0

1

0

1

0

1

Default position

Output clock falling edge earlier by (1/12)Ts

Output clock falling edge aligned with data

transition

0

1

0

1

0

1

0

1

Output clock falling edge aligned with data

transition

Output Data Format

Two output data formats are supported – 2's complement and offset binary. They can be selected using the DFS

(pin 6) or the serial interface register bit <DFS>.

Out-of-range Indicator (OVR)

When the input voltage exceeds the full-scale range of the ADC, OVR (pin 3) goes high, and the output code is

clamped to the appropriate full-scale level for the duration of the overload. For a positive overdrive, the output

code is 0x3FFF in offset binary output format, and 0x1FFF in 2's complement output format. For a negative input

overdrive, the output code is 0x0000 in offset binary output format and 0x2000 in 2's complement output format.

Figure 48 shows the behavior of OVR during the overload. Note that OVR and the output code react to the

overload after a latency of 14 clock cycles.

Figure 48. OVR During Input Overvoltage

41

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Output Timing

For the best performance at high sampling frequencies, ADS5527 uses a clock generator circuit to derive

internal timing for ADC. This results in optimal setup and hold times of the output data and 50% output clock

duty cycle for sampling frequencies from 80 MSPS to 210 MSPS. See Table 15 for timing information above 80

MSPS.

(1)

Table 15. Timing Characteristics (80 MSPS to 210 MSPS)

t_suDATA SETUP TIME, ns

t_hDATA HOLD TIME, ns

TYP

t_PDICLOCK PROPAGATION DELAY, ns

Fs, MSPS

MIN

TYP

MAX

MIN

MAX

MIN

TYP

MAX

DDR LVDS

190

1.2

1.3

1.6

2.0

3.6

1.7

1.8

2.1

2.5

4.1

0.4

0.5

0.6

0.8

1.6

0.9

1.0

1.1

1.3

2.1

4.0

3.9

4.3

4.5

4.7

4.6

5.0

5.2

5.7

5.4

5.3

5.7

5.9

6.7

170

150

130

80

PARALLEL CMOS

190

170

150

130

80

2.2

2.5

2.8

3.3

6.0

3.0

3.3

3.6

4.1

7.0

0.5

0.8

1.2

1.7

3.7

0.9

1.2

1.6

2.1

4.1

2.4

1.9

3.2

2.7

2.5

1.9

12

4.0

3.5

1.7

3.3

1.1

2.7

10.8

13.2

(1) Timing parameters are specified by design and characterization and not tested in production.

Below 80 MSPS, the setup and hold times do not scale with the sampling frequency. The output clock duty cycle

also progressively moves away from 50% as the sampling frequency is reduced from 80 MSPS.

See Table 16 for timings at sampling frequencies below 80 MSPS. Figure 49 shows the clock duty cycle across

sampling frequencies in the DDR LVDS and CMOS modes.

(1)

Table 16. Timing Characteristics (1 MSPS to 80 MSPS)

t_suDATA SETUP TIME, ns

MIN TYP MAX

t_hDATA HOLD TIME, ns

TYP

t_PDICLOCK PROPAGATION DELAY, ns

Fs, MSPS

MIN

1.6

MAX

MIN

TYP

5.7

12

MAX

DDR LVDS

1 to 80

3.6

6

PARALLEL CMOS

1 to 80

3.7

(1) Timing parameters are specified by design and characterization and not tested in production.

100

90

80

70

DDR LVDS

50% Duty Cycle

60

50

40

CMOS

45% Duty Cycle

30

20

10

0

20 40 60 80 100 120 140 160 180 210

Sampling Frequency − MHz

Figure 49. Output Clock Duty Cycle (Typical) vs Sampling Frequency

42

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The latency of ADS5527 is 14 clock cycles from the sampling instant (input clock rising edge). In the LVDS

mode, the latency remains constant across sampling frequencies. In the CMOS mode, the latency is 14 clock

cycles above 80 MSPS and 13 clock cycles below 80 MSPS.

43

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DEFINITION OF SPECIFICATIONS

Analog Bandwidth

The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low

frequency value.

Aperture Delay

The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling

occurs.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Clock Pulse Width/Duty Cycle

The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width)

to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential

sine-wave clock results in a 50% duty cycle.

Maximum Conversion Rate

The maximum sampling rate at which certified operation is given. All parametric testing is performed at this

sampling rate unless otherwise noted.

Minimum Conversion Rate

The minimum sampling rate at which the ADC functions.

Differential Nonlinearity (DNL)

An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the

deviation of any single step from this ideal value, measured in units of LSBs

Integral Nonlinearity (INL)

The INL is the deviation of the ADC’s transfer function from a best fit line determined by a least squares curve fit

of that transfer function, measured in units of LSBs.

Gain Error

The gain error is the deviation of the ADC’s actual input full-scale range from its ideal value. The gain error is

given as a percentage of the ideal input full-scale range.

Offset Error

The offset error is the difference, given in number of LSBs, between the ADC’s actual average idle channel

output code and the ideal average idle channel output code. This quantity is often mapped into mV.

Temperature Drift

The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree

Celsius of the parameter from T_MINto T_MAX. It is calculated by dividing the maximum deviation of the parameter

across the T_MINto T_MAXrange by the difference T_MAX–T_MIN

.

44

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DEFINITION OF SPECIFICATIONS (continued)

Signal-to-Noise Ratio

SNR is the ratio of the power of the fundamental (P_S) to the noise floor power (P_N), excluding the power at dc

and the first nine harmonics.

P

s

SNR + 10Log¹⁰

N

SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the

reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s

full-scale range.

Signal-to-Noise and Distortion (SINAD)

SINAD is the ratio of the power of the fundamental (P_S) to the power of all the other spectral components

including noise (P_N) and distortion (P_D), but excluding dc.

P

s

SINAD + 10Log¹⁰

P

) P

N

D

SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the

reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s

full-scale range.

Effective Number of Bits (ENOB)

The ENOB is a measure of a converter’s performance as compared to the theoretical limit based on quantization

noise.

SINAD * 1.76

ENOB +

6.02

Total Harmonic Distortion (THD)

THD is the ratio of the power of the fundamental (P_S) to the power of the first nine harmonics (P_D).

P

s

THD + 10Log¹⁰

N

THD is typically given in units of dBc (dB to carrier).

Spurious-Free Dynamic Range (SFDR)

The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic).

SFDR is typically given in units of dBc (dB to carrier).

Two-Tone Intermodulation Distortion

IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral

component at either frequency 2f1–f2 or 2f2–f1. IMD3 is either given in units of dBc (dB to carrier) when the

absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the

fundamental is extrapolated to the converter’s full-scale range.

DC Power Supply Rejection Ratio (DC PSRR)

The DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The DC PSRR is

typically given in units of mV/V.

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DEFINITION OF SPECIFICATIONS (continued)

AC Power Supply Rejection Ratio (AC PSRR)

AC PSRR is the measure of rejection of variations in the supply voltage of the ADC. If ∆V_SUPis the change in

the supply voltage and ∆V_OUTis the resultant change in the ADC output code (referred to the input), then

DV_OUT

PSRR = 20Log¹⁰

(Expressed in dBc)

DV_SUP

Common Mode Rejection Ratio (CMRR)

CMRR is the measure of rejection of variations in the input common-mode voltage of the ADC. If ∆Vcm is the

change in the input common-mode voltage and ∆V_OUTis the resultant change in the ADC output code (referred

to the input), then

DV_OUT

10

CMRR = 20Log

(Expressed in dBc)

DV_CM

Voltage Overload Recovery

The number of clock cycles taken to recover to less than 1% error for a 6-dB overload on the analog inputs. A

6-dBFS sine wave at Nyquist frequency is used as the test stimulus.

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PACKAGE OPTION ADDENDUM

www.ti.com

8-Jan-2007

PACKAGING INFORMATION

Orderable Device

ADS5527IRGZR

ADS5527IRGZRG4

ADS5527IRGZT

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

QFN

RGZ

48

2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

QFN

RGZ

2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

ADS5527IRGZTG4

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

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型号：	ADS5527
厂家：	TEXAS INSTRUMENTS
描述：	12-BIT, 210 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS 12 - BIT ， 210 MSPS的DDR LVDS / CMOS输出的ADC 输出元件双倍数据速率
文件：	总49页 (文件大小：1537K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS5527 [TI]

相关型号：

ADS5527IRGZ25

ADS5527IRGZR

ADS5527IRGZRG4

ADS5527IRGZT

ADS5527IRGZTG4

ADS5527_07

ADS5541

ADS5541

ADS5541IPAP

ADS5541IPAPR

ADS5542

ADS5542