ADS5560EVM [TI]
16-BIT, 40/80 MSPS ADCs WITH DDR LVDS/CMOS OUTPUTS;
| 型号： | ADS5560EVM |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT, 40/80 MSPS ADCs WITH DDR LVDS/CMOS OUTPUTS 双倍数据速率 输出元件 |
| 文件： | 总53页 (文件大小：1338K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS5560
ADS5562
www.ti.com ....................................................................................................................................................................................................... SLWS207–MAY 2008
16-BIT, 40/80 MSPS ADCs WITH DDR LVDS/CMOS OUTPUTS
1
FEATURES
•
•
•
•
Internal/External Reference Support
3.3-V Analog and Digital Supply
Pin-for-pin with ADS5547 Family
48-QFN Package (7 mm × 7 mm)
•
16-Bit Resolution
•
Maximum Sample Rate
–
–
ADS5562 - 80 MSPS
ADS5560 - 40 MSPS
APPLICATIONS
•
Total Power
•
•
•
•
•
Medical Imaging - MRI
Wireless Communications Infrastructure
Software Defined Radio
Test and Measurement Instrumentation
High Definition Video
–
–
865 mW at 80MSPS
674 mW at 40MSPS
•
•
•
•
•
•
No Missing Codes
High SNR 84 dBFS (3 MHz IF)
85 dBc SFDR (3 MHz IF)
Low Frequency Noise Suppression Mode
Programmable Fine Gain, 1dB steps till 6dB
Double Data Rate (DDR) LVDS and Parallel
CMOS Output Options
DESCRIPTION
ADS556X is a high performance 16-bit A/D converter family with sampling rates up to 80 MSPS. It supports very
high SNR for input frequencies in the first Nyquist zone. The device includes a low frequency noise suppression
mode that improves the noise from dc to about 1MHz.
In addition to high performance, the device offers several flexible features such as output interface (either Double
Data Rate LVDS or parallel CMOS) and fine gain (in 1 dB steps till 6 dB).
Innovative techniques, such as DDR LVDS and an internal reference that does not require external decoupling
capacitors, have been used to achieve significant savings in pin-count. This results in a compact 7 mm x 7 mm
48 pin QFN package.
The device can be put in an external reference mode, where the VCM pin behaves as the external reference
input. For applications where power is important, ADS556X offers power down modes and automatic power
scaling at lower sample rates.
It is specified over the industrial temperature range (-40°C to +85°C).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS5560
ADS5562
SLWS207–MAY 2008....................................................................................................................................................................................................... www.ti.com
CLKP
CLKM
CLKOUTP
CLKOUTM
CLOCKGEN
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
INP
INM
Digital
Encoder
and
Sample
and
Hold
16-Bit ADC
D6_D7_P
D6_D7_M
Serializer
D8_D9_P
D8_D9_M
D10_D11_P
D10_D11_M
Control
Interface
VCM
Reference
D12_D13_P
D12_D13_M
D14_D15_P
D14_D15_M
OVR
ADS556x
LVDS INTERFACE
B0095-05
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA
ADS5562
QFN-48
RGZ
RGZ
–40°C to 85°C
–40°C to 85°C
AZ5562
AZ5560
ADS5562IRGZT
ADS5562IRGZR
ADS5560IRGZT
ADS5560IRGZR
Tape and Reel,
small
Tape and Reel,
large
ADS5560
QFN-48
Tape and Reel,
small
Tape and Reel,
large
(1) θJA = 25.41 °C/W (0 LFM Air Flow), θJC = 16.5 °C/W when used with 2 oz. copper trace and the thermal pad is soldered directly to a
JEDEC standard four layer 3 in. x 3 in. (7.62 cm x 7.62 cm) PCB. Thermal pad is 5.2 x 5.2 mm. Please see mechanical drawings in the
back of the datasheet for details.
2
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ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
V
AVDD
DRVDD Supply voltage range
Voltage between AGND and DRGND
Supply voltage range
–0.3 V to 3.9
–0.3 V to 3.9
V
-0.3 to 0.3
V
Voltage between AVDD to DRVDD
-0.3 to 3.3
V
Voltage applied to VCM pin (in external reference mode)
Voltage applied to analog input pins
-0.3 to 1.8
V
–0.3 V to minimum (3.6, AVDD + 0.3 V)
V
TA
Operating free-air temperature range
–40 to 85
125
°C
°C
°C
°C
Tjmax
TSTG
Operating junction temperature range
Storage temperature range
–65 to 150
220
Lead temperature 1,6 mm (1/16") from the case for 10 seconds
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX UNIT
SUPPLIES AND REFERENCES
AVDD Analog supply voltage
3
3
3.3
3.3
3.6
3.6
V
V
DRVDD Digital supply voltage
ANALOG INPUTS
Differential input voltage range (with default fine gain=1 dB)
3.56
VPP
V
Input common-mode voltage
1.5 ±0.1
Voltage applied on VCM in external reference mode
1.5
V
±0.05
CLOCK INPUT
Sample rate
DEFAULT SPEED mode
> 30
1
80
30
40
30
MSP
S
ADS5562
ADS5560
(1)
LOW SPEED mode
MSP
S
DEFAULT SPEED mode
LOW SPEED mode
> 30
1
MSP
S
MSP
S
Sine wave, LVPECL,
LVDS, LVCMOS
Supported clock waveform formats
Clock amplitude, ac-coupled, differential (VCLKP - VCLKM
)
0.4
VPP
pF
Clock duty cycle
45%
50%
55%
DIGITAL OUTPUTS
CL
Maximum external load capacitance from each output pin to DRGND (LVDS and CMOS
modes)
5
RL
Differential external load resistance between the LVDS output pairs (LVDS mode)
Operating free-air temperature
100
Ω
-40
85
°C
(1) See Low sampling frequency operation in application section for details.
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ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling rate = Max Rated, sine wave input clock, 1.5 VPP clock
amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, DDR LVDS interface, default fine
gain (1dB).
Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V, sampling
rate = Max Rated, unless otherwise noted.
ADS5562
TYP
ADS5560
TYP
TEST
CONDITIONS
PARAMETER
UNIT
MIN
MAX
MIN
MAX
RESOLUTION
ANALOG INPUT
Differential input voltage
16
16
bits
VPP
pF
3.56
5
3.56
5
(1)
range
Differential input
capacitance
Analog input bandwidth
300
6.6
300
6.6
MHz
Analog input common
µA/MSPS
mode current (per input pin)
VCM
Common mode output
voltage
Internal reference
mode
1.5
±4
1.5
±4
V
VCM output current
capability
Internal reference
mode
mA
DC ACCURACY
No Missing Codes
0 dB gain
Assured
0.5
Assured
0.5
DNL
INL
Differential non-linearity
Integral non-linearity
Offset error
-0.95
-8.5
-25
3
-0.95
-8.5
-25
3
LSB
LSB
±3
8.5
25
±3
8.5
25
±10
±10
mV
Offset error temperature
coefficient
0.005
0.005
mV/°C
Variation of offset error
across AVDD supply
1.5
1.5
±1
mV/V
%FS
There are two sources of gain error: i) internal reference inaccuracy and ii) channel gain
error
EGREF
ECHAN
Gain error due to internal
reference inaccuracy alone
-2.5
±1
2.5
-2.5
2.5
2.5
Channel gain error alone
-2.5
± 1
2.5
-2.5
± 1
%FS
Channel gain error
0.01
0.01
Δ%/°C
temperature coefficient
POWER SUPPLY
IAVDD
Analog supply current
210
52
250
160
44
190
mA
mA
LVDS mode
IO = 3.5 mA, RL
100 Ω
=
Digital supply current
CL = 5 pF
IDRVDD
CMOS mode
FIN = 3 MHz
60
37
mA
Total power
LVDS mode
865
155
1100
150
674
135
810
150
mW
mW
Standby power
STANDBY mode
with clock running
Clock stop power
125
125
mW
(1) The full-scale voltage range is a function of the fine gain settings. See Table 23.
4
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ELECTRICAL CHARACTERISTICS (Continued)
Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling rate = Max Rated, sine wave input clock, 1.5 VPP clock
amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, DDR LVDS interface, 0 dB fine
(1)
gain
.
Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V, sampling
rate = Max Rated, default fine gain (1dB), unless otherwise noted.
ADS5562
ADS5560
Fs = 80 MSPS
Fs = 40 MSPS
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
AC CHARACTERISTICS
FIN = 3 MHz
84
84.3
84
FIN = 10 MHz
FIN = 25 MHz
FIN = 30 MHz
FIN = 3 MHz
FIN = 10 MHz
FIN = 25 MHz
FIN = 30 MHz
79
83.8
83.2
82.8
81.7
81.4
80.7
80.4
1.42
80.5
80.5
79.5
79
80
LVDS
interface
dBFS
82.5
81.8
83.5
83.1
81.8
81.6
1.42
83.2
83
SNR
Signal to noise
ratio
77
78
CMOS
interface
dBFS
LSB
RMS output noise Inputs tied to common-mode
FIN = 3 MHz
FIN = 10 MHz
FIN = 25 MHz
FIN = 30 MHz
FIN = 3 MHz
FIN = 10 MHz
FIN = 25 MHz
FIN = 30 MHz
75
76
75
LVDS
interface
dBFS
79
SINAD
Signal to noise and
distortion ratio
77
80.5
80.2
79.3
77.9
82
73.5
81.4
79.3
78
CMOS
interface
dBFS
bits
ENOB
Effective number
of bits
LVDS
interface
FIN = 10 MHz
12.2
77
13.1
12.4
78
13.5
FIN = 3 MHz
FIN = 10 MHz
FIN = 25 MHz
FIN = 30 MHz
FIN = 3 MHz
FIN = 10 MHz
FIN = 25 MHz
FIN = 30 MHz
85
85
83
80
90
89
88
88
90
88
83
79
94
92
90
88
SFDR
Spurious free
dynamic range
dBc
77
78
HD2
Second harmonic
dBc
(1) Note that after reset, the device is initialized to 1 dB fine gain setting. For SFDR and SNR performance across fine gains, see Typical
Characteristics section.
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ELECTRICAL CHARACTERISTICS (Continued)
Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling rate = Max Rated, sine wave input clock, 1.5 VPP clock
amplitude, 50% clock duty cycle, –1 dBFS differential analog input, default fine gain (1dB),internal reference mode, DDR
LVDS interface 0 dB fine gain(1)
.
Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V, sampling
rate = Max Rated, default fine gain (1dB), unless otherwise noted.
ADS5562
TYP
85
ADS5560
TYP
90
PARAMETER
TEST CONDITIONS
FIN = 3 MHz
UNIT
MIN
MAX
MIN
MAX
FIN = 10 MHz
FIN = 25 MHz
FIN = 30 MHz
FIN = 3 MHz
FIN = 10 MHz
FIN = 25 MHz
FIN = 30 MHz
FIN = 3 MHz
FIN = 10 MHz
FIN = 25 MHz
FIN = 30 MHz
77
85
78
88
HD3
Third harmonic
dBc
83
83
80
79
104
102
100
100
84
104
102
101
101
88
Worst harmonic
other than HD2,
HD3
dBc
THD
Total harmonic
distortion
75.5
83
76.5
86
dBc
82
81
80
78
IMD
Two-tone
intermodulation
distortion
FIN1 = 5 MHz, FIN2 = 10 MHz
each tone -7 dBFS
92
1
98
1
dBFS
Voltage overload
recovery time
Recovery to 1% for 6-dB
overload
clock
cycles
(1) Note that after reset, the device is initialized to 1 dB fine gain setting. For SFDR and SNR performance across fine gains, see Typical
Characteristics section.
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DIGITAL CHARACTERISTICS
DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0
or 1, AVDD = 3.0V to 3.6V, IO = 3.5 mA, RL = 100 Ω(1)(2)
PARAMETER
DIGITAL INPUTS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
Input capacitance
2.4
V
0.8
V
33
-33
4
µA
µA
pF
DIGITAL OUTPUTS – CMOS MODE
High-level output voltage
Low-level output voltage
Output capacitance
DRVDD
V
V
0
4
Capacitance inside the device from each output pin to
ground
pF
DIGITAL OUTPUTS – LVDS MODE
VODH High-level output voltage
VODL Low-level output voltage
+350
-350
1.2
mV
mV
V
VOCM Output common-mode
voltage
Output capacitance
Capacitance inside the device from each output pin to
ground
4
pF
(1) All LVDS and CMOS specifications are characterized, but not tested at production.
(2) IO refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair.
Dn_Dn + 1_P
Dn_Dn+1_P
Logic 0
VODL = –350 mV*
Logic 1
VODH = 350 mV*
Dn_Dn+1_M
Dn_Dn + 1_M
VOCM
V
GND
GND
* With external 100-W termination
T0334-01
Figure 1. LVDS Output Voltage Levels
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TIMING CHARACTERISTICS – LVDS AND CMOS MODES(1)
Typical values are at 25°C, AVDD = 3.3 V, DRVDD = 3.0 to 3.6V, Sampling frequency = 80 MSPS, sine wave input clock,
(3)
50% clock duty cycle, 1.5 VPP clock amplitude, CL = 5 pF(2) , no internal termination, IO = 3.5 mA, RL = 100 Ω
Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.0 to 3.6V,
unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
1.2
90
MAX
UNIT
ns
ta
tj
Aperture delay
0.5
2
Sampling frequency = 80 MSPS
fs rms
fs rms
µs
Aperture jitter
Sampling frequency = 40 MSPS
Time to data stable (4) after coming out of STANDBY mode
135
60
200
Wake-up time
Latency
Time to valid data after stopping and restarting the input clock
80
µs
Clock
cycles
16
DDR LVDS MODE(5)
LVDS bit clock duty
47%
50%
53%
12.5
cycle
tsu
th
Data setup time(6)
Data hold time(6)
Data valid(7) to zero-crossing of CLKOUTP
Zero-crossing of CLKOUTP to data becoming invalid(7)
2.0
2.0
9.5
3.0
3.0
11
ns
ns
ns
tPDI
Clock propagation delay Input clock rising edge cross-over to output clock rising edge
cross-over
tr
Data rise time
Rise time measured from –100 mV to 100 mV
Fall time measured from 100 mV to –100 mV
Rise time measured from –100 mV to 100 mV
Fall time measured from 100 mV to –100 mV
Time to data valid after OE becomes active
0.15
0.15
0.15
0.15
0.22
0.22
0.22
0.22
700
0.3
0.3
0.3
0.3
ns
ns
ns
ns
ns
tf
Data fall time
tr
Output clock rise time
Output clock fall time
tf
tOE
Output enable (OE) to
data delay
PARALLEL CMOS MODE
CMOS output clock duty
50%
cycle
tsu
th
Data setup time
Data hold time
Data valid(8) to 50% of CLKOUT rising edge
6.5
2.0
6.3
8.0
3.0
7.8
ns
ns
ns
(8)
50% of CLKOUT rising edge to data becoming invalid
tPDI
Clock propagation delay Input clock rising edge cross-over to 50% of CLKOUT rising
edge
9.3
tr
Data rise time
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
Time to data valid after OE becomes active
1.0
1.0
0.7
1.2
1.5
1.5
1.0
1.5
200
2.0
2.0
1.2
1.8
ns
ns
ns
ns
ns
tf
Data fall time
tr
Output clock rise time
Output clock fall time
tf
tOE
Output enable (OE) to
data delay
(1) Timing parameters are ensured by design and characterization and not tested in production.
(2) CL is the effective external single-ended load capacitance between each output pin and ground.
(3) Io refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair.
(4) Data stable is defined as the point at which the SNR is within 2dB of its normal value.
(5) Measurements are done with a transmission line of 100 Ω characteristic impedance between the device and the load.
(6) Setup and hold time specifications take into account the effect of jitter on the output data and clock.
(7) Data valid refers to logic high of +100 mV and logic low of -100 mV.
(8) Data valid refers to logic high of 2.6 V and logic low of 0.66 V.
8
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Table 1. Timing Characteristics at lower sampling frequencies
Sampling
Frequency,
MSPS
tsu,Setup time, ns
tho,Hold time, ns
tPDI,Clock propagation delay, ns
DDR LVDS
65
2.7
5
3.7
6
2.7
5
3.7
6
11.5
16.5
30.5
13
18
32
14.5
19.5
33.5
40
20
8
11
8
11
Parallel CMOS
65
40
20
8
9.5
3
4
7
8
5
8.5
9.5
10
11
15
14
14
15.5
6.5
6.5
7.5
10.5
N+19
N+18
N+4
N+3
N+17
N+2
Sample
N
N+1
N+16
Input
Signal
ta
CLKP
Input
Clock
CLKM
CLKOUTM
CLKOUTP
tsu
th
tPDI
16 Clock Cycles
DDR
LVDS
Output Data
DXP, DXM
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
N–16
N–15
N–14
N–13
N–12
N–1
N
N+1
N+2
E – Even Bits D0,D2,D4,D6,D8,D10,D12,D14
O – Odd Bits D1,D3,D5,D7,D9,D11,D13,D15
tPDI
CLKOUT
tsu
Parallel
CMOS
16 Clock Cycles
th
Output Data
D0–D15
N–16
N–15
N–14
N–13
N–12
N–1
N
N+1
N+2
T0105-08
Figure 2. Latency
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CLKM
Input
Clock
CLKP
tPDI
CLKOUTP
Output
Clock
CLKOUTM
th
tsu
tsu
th
Dn(1)
Dn+1(2)
Output
Data Pair
Dn_Dn+1_P,
Dn_Dn+1_M
(1)Dn – Bits D0, D2, D4, D6, D8, D10, D12, D14
(2)Dn+1 – Bits D1, D3, D5, D7, D9, D11, D13, D15
T0106-06
Figure 3. LVDS Mode Timing
CLKM
Input
Clock
CLKP
tPDI
Output
CLKOUT
Clock
th
tsu
Dn(1)
Output
Data
Dn
(1)Dn – Bits D0–D15
T0107-04
Figure 4. CMOS Mode Timing
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DEVICE PROGRAMMING MODES
ADS5562 offers flexibility with several programmable features that are easily configured.
The device can be configured independently using either parallel interface control or serial interface
programming.
In addition, the device supports a third configuration mode, where both the parallel interface and the serial control
registers are used. In this mode, the priority between the parallel and serial interfaces is determined by a priority
table (Table 3). If this additional level of flexibility is not required, the user can select either the serial interface
programming or the parallel interface control.
USING PARALLEL INTERFACE CONTROL ONLY
To control the device using parallel interface, keep RESET tied to high (DRVDD). Pins DFS, MODE, SEN,
SCLK, and SDATA are used to directly control certain modes of the ADC. The device is configured by
connecting the parallel pins to the correct voltage levels (as described in Table 4 to Table 8). There is no need to
apply reset.
In this mode, SEN, SCLK, and SDATA function as parallel interface control pins. Frequently used functions are
controlled in this mode—standby, selection between LVDS/CMOS output format, internal/external reference,
two's complement/offset binary output format, and position of the output clock edge.
Table 2 has a description of the modes controlled by the parallel pins.
Table 2. Parallel Pin Definition
PIN
DFS
CONTROL MODES
DATA FORMAT and the LVDS/CMOS output interface
MODE
SEN
Internal or external reference
CLKOUT edge programmability
SCLK
SDATA
LOW SPEED mode control for low sampling frequencies (≤ 30 MSPS)
STANDBY mode – Global (ADC, internal references and output buffers are powered down)
USING SERIAL INTERFACE PROGRAMMING ONLY
To program using the serial interface, the internal registers must first be reset to their default values, and the
RESET pin must be kept low. In this mode, SEN, SDATA, and SCLK function as serial interface pins and are
used to access the internal registers of ADC. The registers are reset either by applying a pulse on the RESET
pin, or by a high setting on the <RST> bit (D1 in register 0x6C). The serial interface section describes the
register programming and register reset in more detail.
Since the parallel pins DFS and MODE are not used in this mode, they must be tied to ground.
USING BOTH SERIAL INTERFACE AND PARALLEL CONTROLS
For increased flexibility, a combination of serial interface registers and parallel pin controls (DFS, MODE) can
also be used to configure the device.
The serial registers must first be reset to their default values and the RESET pin must be kept low. In this mode,
SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC.
The registers are reset either by applying a pulse on RESET pin or by a high setting on the <RST> bit (D1 in
register 0x6C). The serial interface section describes the register programming and register reset in more detail.
The parallel interface control pins DFS and MODE are used and their function is determined by the appropriate
voltage levels as described in Table 7 and Table 8. The voltage levels are derived by using a resistor string as
illustrated in Figure 5. Since some functions are controlled using both the parallel pins and serial registers, the
priority between the two is determined by a priority table (Table 3).
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Table 3. Priority Between Parallel Pins and Serial Registers
PIN
FUNCTIONS SUPPORTED
PRIORITY
When using the serial interface, bit <REF> (register 0x6D, bit D4) controls this mode, ONLY
if the MODE pin is tied low.
MODE
Internal/External reference
When using the serial interface, bit <DF> (register 0x63, bit D3) controls this mode, ONLY if
the DFS pin is tied low.
DATA FORMAT
LVDS/CMOS
DFS
When using the serial interface, bit <ODI> (register 0x6C, bits D3-D4) controls LVDS/CMOS
selection independent of the state of DFS pin
DRVDD
(5/8) DRVDD
3R
(5/8) DRVDD
GND
DRVDD
2R
3R
(3/8) DRVDD
(3/8) DRVDD
To Parallel Pin
GND
S0321-02
Figure 5. Simple Scheme to Configure Parallel Pins
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DESCRIPTION OF PARALLEL PINS
Table 4. SCLK Control Pin
SCLK
0
DESCRIPTION
DEFAULT SPEED mode - Use for sampling frequencies > 30 MSPS.
LOW SPEED mode Enabled - Use for sampling frequencies ≤ 30 MSPS.
DRVDD
Table 5. SDATA Control Pin
SDATA
0
DESCRIPTION
Normal operation (Default)
DRVDD
STANDBY. This is a global power down, where ADC, internal references and the output buffers are powered down.
Table 6. SEN Control Pin
SEN
With CMOS interface
0
CLKOUT Rising edge later by (3/36)Ts
CLKOUT Falling edge later by (3/36)Ts
(3/8)DRVDD
(5/8)DRVDD
DRVDD
CLKOUT Rising edge later by (5/36)Ts
CLKOUT Falling edge later by (5/36)Ts
CLKOUT Rising edge earlier by (3/36)Ts
CLKOUT Falling edge earlier by (3/36)Ts
Default CLKOUT position
With LVDS interface
0
CLKOUT Rising edge later by (7/36)Ts
CLKOUT Falling edge later by (6/36)Ts
(3/8)DRVDD
(5/8)DRVDD
DRVDD
CLKOUT Rising edge later by (7/36)Ts
CLKOUT Falling edge later by (6/36)Ts
CLKOUT Rising edge later by (3/36)Ts
CLKOUT Falling edge later by (3/36)Ts
Default CLKOUT position
Table 7. DFS Control Pin
DFS
0
DESCRIPTION
2's complement data and DDR LVDS output (Default)
2's complement data and parallel CMOS output
Offset binary data and parallel CMOS output
(3/8)DRVDD
(5/8)DRVDD
DRVDD
Offset binary data and DDR LVDS output
Table 8. MODE Control Pin
MODE
0
DESCRIPTION
Internal reference
External reference
External reference
Internal reference
(3/8)AVDD
(5/8)AVDD
AVDD
SERIAL INTERFACE
The ADC has a set of internal registers, which can be accessed through the serial interface formed by pins SEN
(Serial interface Enable), SCLK (Serial Interface Clock), SDATA (Serial Interface Data) and RESET. After device
power-up, the internal registers must be reset to their default values by applying a high-going pulse on RESET
(of width greater than 10 ns).
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Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge
of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge
when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data is loaded in
multiples of 16-bit words within a single active SEN pulse.
The first 8 bits form the register address and the remaining 8 bits form the register data. The interface can work
with SCLK frequency from 20 MHz down to very low speeds (few Hertz) and also with non-50% SCLK duty
cycle.
REGISTER INITIALIZATION
After power-up, the internal registers must be reset to their default values. This is done in one of two ways:
1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10 ns) as
shown in Figure 6.
OR
2. By applying software reset. Using the serial interface, set the <RST> bit (D1 in register 0x6C) to high. This
initializes the internal registers to their default values and then self-resets the <RST> bit to low. In this case
the RESET pin is kept low.
Register Address
Register Data
SDATA
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
t(DH)
D1
D0
t(SCLK)
t(DSU)
SCLK
t(SLOADH)
t(SLOADS)
SEN
RESET
Figure 6. Serial Interface Timing Diagram
SERIAL INTERFACE TIMING CHARACTERISTICS
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V (unless otherwise noted)
MIN
> DC
25
TYP
MAX
20
UNIT
MHz
ns
fSCLK
tSLOADS
tSLOADH
tDSU
SCLK frequency
SEN to SCLK setup time
SCLK to SEN hold time
SDATA setup time
SDATA hold time
25
ns
25
ns
tDH
25
ns
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RESET TIMING
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
5
TYP
MAX
UNIT
ms
ns
t1
t2
Power-on delay
Delay from power-up of AVDD and DRVDD to RESET pulse active
10
Reset pulse width
Pulse width of active RESET signal
1
µs
t3
Register write delay
Power-up time
Delay from RESET disable to SEN active
25
ns
tPO
Delay from power-up of AVDD and DRVDD to output stable
6.5
ms
Power Supply
AVDD, DRVDD
t1
RESET
t2
t3
SEN
NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset.
For parallel interface operation, RESET has to be tied permanently HIGH.
Figure 7. Reset Timing Diagram
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SERIAL REGISTER MAP
Table 9 gives a summary of all the modes that can be programmed through the serial interface.
Table 9. Summary of Functions Supported by Serial Interface(1)(2)
REGISTER
ADDRESS
IN HEX
REGISTER FUNCTIONS
D4 D3
A7 - A0
D7
D6
D5
D2
D1
D0
<LF NOISE
SUPPRESSION>
5D
<CLKOUT POSN>
OUTPUT CLOCK POSITION PROGRAMMABILITY
62
<LOW SPEED>
ENABLE LOW
SAMPLING
FREQUENCY
OPERATION
<STBY>
GLOBAL
POWER
DOWN
<DF>
DATA FORMAT -
2's COMP or
63
OFFSET BINARY
<TEST PATTERN> – ALL 0S, ALL 1s,
TOGGLE, RAMP, CUSTOM PATTERN
65
68
<GAIN>
FINE GAIN 0dB to 6dB, in 1dB steps
69
6A
<CUSTOM A> CUSTOM PATTERN (D7 TO D0)
<CUSTOM B> CUSTOM PATTERN (D15 TO D8)
<ODI> OUTPUT DATA INTERFACE
DDR LVDS or PARALLEL CMOS
6C
<REF>
INTERNAL or
EXTERNAL
REFERENCE
6D
<RST>
SOFTWARE
RESET
6E
<DATA TERM>
INTERNAL TERMINATION – DATA
OUTPUTS
<LVDS CURR>
LVDS CURRENT
PROGRAMMABILITY
<CLKOUT TERM>
INTERNAL TERMINATION – OUTPUT CLOCK
7E
7F
<CURR DOUBLE>
LVDS CURRENT DOUBLE
(1) The unused bits in each register (shown by blank cells in above table) must be programmed as ‘0’.
(2) Multiple functions in a register can be programmed in a single write operation.
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DESCRIPTION OF SERIAL REGISTERS
Each register function is explained in detail below.
Table 10.
A7 - A0 (hex)
D7
D6
D5
D4
D3
D2
D1
D0
<LF NOISE
SUPPRESSION>
5D
D0
0
<LF NOISE SUPPRESSION> Low frequency noise suppression
Disable low frequency noise suppression
1
Enable low frequency noise suppression
Table 11.
A7 - A0 (hex)
D7
D6
D5
D4
D3
D2
<CLKOUT POSN>
OUTPUT CLOCK POSITION PROGRAMMABILITY
D1
D0
62
D4 - D0
<CLKOUT POSN> Output Clock Position Programmability
00000
Register value after reset (corresponds to default CLKOUT position)
Setup/hold timings with this clock position are specified in the timing
characteristics table.
00001
Default CLKOUT position.
Setup/hold timings with this clock position are specified in the timing
characteristics table.
XX011
XX101
XX111
01XX1
10XX1
11XX1
CMOS - Rising edge earlier by (3/36) Ts
LVDS - Falling edge later by (3/36) Ts
CMOS - Rising edge later by (3/36) Ts
LVDS - Falling edge later by (6/36) Ts
CMOS - Rising edge later by (5/36) Ts
LVDS - Falling edge later by (6/36) Ts
CMOS - Falling edge earlier by (3/36) Ts
LVDS - Rising edge later by (3/36) Ts
CMOS - Falling edge later by (3/36) Ts
LVDS - Rising edge later by (7/36) Ts
CMOS - Falling edge later by (5/36) Ts
LVDS - Rising edge later by (7/36) Ts
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Table 12.
A7 - A0 (hex)
D7
D6
D5
D4
D3
D2
D1
D0
<DF>
DATA
FORMAT
2's COMP or
OFFSET
BINARY
<LOW SPEED>
ENABLE LOW
SAMPLING
FREQUENCY
OPERATION
<STBY>
GLOBAL
POWER
DOWN
63
D3
0
<DF> Output Data Format
2's complement
1
Offset binary
D0
0
<LOW SPEED> Low Sampling Frequency Operation
DEFAULT SPEED mode (for Fs > 30 MSPS)
LOW SPEED mode eabled (for Fs ≤ 30 MSPS)
1
D7
0
<STBY> Global STANDBY
Normal operation
1
Global power down (includes ADC, internal references and output buffers)
Table 13.
A7 - A0 (hex)
D7
D6
D5
D4
D3
D2
D1
D0
<TEST PATTERNS> — ALL 0S, ALL 1s,
TOGGLE, RAMP, CUSTOM PATTERN
65
D7 - D5
000
<TEST PATTERN> Outputs selected test pattern on data lines
Normal operation
All 0s
001
010
All 1s
011
Toggle pattern - alternate 1s and 0s on each data output and across data
outputs
100
101
111
Ramp pattern - Output data ramps from 0x0000 to 0xFFFF by one code
every clock cycle
Custom pattern - Outputs the custom pattern in CUSTOM PATTERN
registers A and B
Unused
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Table 14.
A7 - A0 (hex)
D7
D6
D5
D4
D3
D2
D1
D0
68
<GAIN> FINE GAIN 0 dB to 6 dB, in 1 dB steps
D3 - D0
0XXX
1000
1001
1010
1011
1100
1101
1110
<GAIN> Programmable Fine Gain
1 dB
0 dB
1 dB, default register value after reset
2 dB
3 dB
4 dB
5 dB
6 dB
Table 15.
A7 - A0 (hex)
D7
D6
D5
D4
D3
D2
D1
D0
69
6A
<CUSTOM A> CUSTOM PATTERN (D7 TO D0)
<CUSTOM B> CUSTOM PATTERN (D15 TO D8)
Reg 69
Reg 6A
D7 - D0
Program bits D7 to D0 of custom pattern
Program bits D15 to D8 of custom pattern
D15 - D8
Table 16.
A7 - A0 (hex)
D7
D6
D5
D4
D3
D2
D1
D0
<ODI> OUTPUT DATA
INTERFACE - DDR LVDS OR
PARALLEL CMOS
6C
D4 - D3
<ODI> Output Interface
00
default after reset, state of DFS pin determines
interface type. See Table 7.
01
11
DDR LVDS outputs, independent of state of DFS
pin.
Parallel CMOS outputs, independent of state of
DFS pin.
Table 17.
A7 - A0
D7
D6
D5
D4
D3
D2
D1
D0
<REF>
6D
INTERNAL or EXTERNAL
REFERENCE
D4
0
<REF> Reference
Internal reference
1
External reference mode, force voltage on VCM to set reference.
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Table 18.
A7 - A0
D7
D6
D5
D4
D3
D2
D1
D0
<RST> SOFTWARE
6E
RESET
D0
<RST> Software resets the ADC
1
Resets all registers to default values
Table 19.
A7 - A0
D7
D6
D5
D4
D3
D2
D1
D0
<LVDS CURR> LVDS
CURRENT
PROGRAMMABILITY
<DATA TERM> INTERNAL TERMINATION –
<CLKOUT TERM> INTERNAL
TERMINATION – OUTPUT CLOCK
7E
DATA OUTPUTS
D1 - D0
00
<LVDS CURR> LVDS Buffer Current Programmability
3.5 mA, default
2.5 mA
01
10
4.5 mA
11
1.75 mA
D4 - D2
000
<CLKOUT TERM> LVDS Buffer Internal Termination
No internal termination
001
325
200
125
170
120
100
75
010
011
100
101
110
111
D7 - D5
000
<DATA TERM> LVDS Buffer Internal Termination
No internal termination
001
325
200
125
170
120
100
75
010
011
100
101
110
111
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Table 20.
A7 - A0
D7
D6
D5
D4
D3
D2
D1
D0
<CURR DOUBLE> LVDS
CURRENT DOUBLE
7F
D7 - D6
00
<CURR DOUBLE> LVDS Buffer Internal Termination
Value specified by <LVDS CURR>
2x data, 2x clockout currents
01
10
1x data, 2x clockout currents
11
2x data, 4x clockout currents
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PIN CONFIGURATION (LVDS MODE)
ADS556x
RGZ PACKAGE
(TOP VIEW)
1
36
35
34
33
32
31
30
29
28
27
26
25
DRGND
DRVDD
OVR
DRGND
DRVDD
D2_D3_P
D2_D3_M
D0_D1_P
D0_D1_M
RESET
SCLK
2
Thermal Pad
3
4
CLKOUTM
CLKOUTP
DFS
5
6
7
OE
8
AVDD
9
AGND
CLKP
SDATA
SEN
10
11
12
CLKM
AVDD
AGND
AGND
P0023-09
Figure 8. LVDS Mode Pinout
Table 21. PIN ASSIGNMENTS – LVDS Mode
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
PIN NAME
AVDD
DESCRIPTION
Analog power supply
Analog ground
I
8, 18, 20,
22, 24, 26
6
AGND
I
9, 12, 14, 17,
19, 25
6
CLKP, CLKM
INP, INM
VCM
Differential clock input
Differential analog input
I
I
10, 11
15, 16
13
2
2
1
Internal reference mode – Common-mode voltage output.
External reference mode – Reference input. The voltage forced on this
pin sets the internal reference.
I/O
RESET
Serial interface reset input.
I
30
1
When using the serial interface, the user should apply a high-going
pulse on this pin to reset the internal registers.
When the serial interface is not used, the user should tie RESET
permanently high. (SCLK, SDATA and SEN can be used as parallel
pin controls).
The pin has an internal 100-kΩ pull-down resistor to DRGND.
22
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Table 21. PIN ASSIGNMENTS – LVDS Mode (continued)
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
PIN NAME
SCLK
DESCRIPTION
This pin functions as serial interface clock input when RESET is low.
It functions as LOW SPEED MODE control when RESET is tied high.
See Table 4 for detailed information.
I
29
1
The pin has an internal 100-kΩ pull-down resistor to DRGND.
SDATA
SEN
This pin functions as serial interface data input when RESET is low.
It functions as STANDBY control pin when RESET is tied high.
I
28
1
See Table 5 for detailed information.
The pin has an internal 100-kΩ pull-down resistor to DRGND.
This pin functions as serial interface enable input when RESET is low.
It functions as CLKOUT edge programmability when RESET is tied
high. See Table 6 for detailed information.
I
27
1
The pin has an internal 100-kΩ pull-up resistor to DRVDD.
OE
Output buffer enable input, active high.
The pin has an internal 100-kΩ pull-up resistor to DRVDD.
I
I
7
6
1
1
DFS
Data Format Select input.
This pin sets the DATA FORMAT (Twos complement or Offset binary)
and the LVDS/CMOS output mode type. See Table 7 for detailed
information.
The pin has an internal 100-kΩ pull-down resistor to DRGND.
MODE
Mode select input.
I
23
1
This pin selects the Internal or External reference mode. See Table 8
for detailed information.
The pin has an internal 100-kΩ pull-down resistor to AGND.
CLKOUTP
CLKOUTM
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
D6_D7_P
D6_D7_M
D8_D9_P
D8_D9_M
D10_D11_P
D10_D11_M
D12_D13_P
D12_D13_M
D14_D15_P
D14_D15_M
OVR
Differential output clock, true
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
5
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
Differential output clock, complement
Differential output data D0 and D1 multiplexed, true
Differential output data D0 and D1 multiplexed, complement.
Differential output data D2 and D3 multiplexed, true
Differential output data D2 and D3 multiplexed, complement
Differential output data D4 and D5 multiplexed, true
Differential output data D4 and D5 multiplexed, complement
Differential output data D6 and D7 multiplexed, true
Differential output data D6 and D7 multiplexed, complement
Differential output data D8 and D9 multiplexed, true
Differential output data D8 and D9 multiplexed, complement
Differential output data D10 and D11 multiplexed, true
Differential output data D10 and D11 multiplexed, complement
Differential output data D12 and D13 multiplexed, true
Differential output data D12 and D13 multiplexed, complement
Differential output data D14 and D15 multiplexed, true
Differential output data D14 and D15 multiplexed, complement
Out-of-range indicator, CMOS level signal
32
31
34
33
38
37
40
39
42
41
44
43
46
45
48
47
3
DRVDD
Digital and output buffer supply
2, 35
1, 36
DRGND
Digital and output buffer ground
I
PAD
Connect the PAD to the ground plane. See in application section.
Do not connect
NC
-
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PIN CONFIGURATION (CMOS MODE)
ADS556x
RGZ PACKAGE
(TOP VIEW)
1
36
35
34
33
32
31
30
29
28
27
26
25
DRGND
DRVDD
OVR
DRGND
DRVDD
D3
2
Thermal Pad
3
4
UNUSED
CLKOUT
DFS
D2
5
D1
6
D0
7
OE
RESET
SCLK
SDATA
SEN
8
AVDD
AGND
CLKP
9
10
11
12
CLKM
AGND
AVDD
AGND
P0023-10
Figure 9. CMOS Mode Pinout
Table 22. PIN ASSIGNMENTS – CMOS Mode
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
PIN NAME
AVDD
DESCRIPTION
Analog power supply
Analog ground
I
8, 18, 20,
22, 24, 26
6
AGND
I
9, 12, 14, 17,
19, 25
6
CLKP, CLKM
INP, INM
VCM
Differential clock input
Differential analog input
I
I
10, 11
15, 16
13
2
2
1
Internal reference mode – Common-mode voltage output.
External reference mode – Reference input. The voltage forced on this pin
sets the internal references.
I/O
RESET
Serial interface reset input.
I
30
1
When using the serial interface, the user should apply a high-going pulse on
this pin to reset the internal registers.
When the serial interface is not used, the user should tie RESET
permanently high. (SCLK, SDATA and SEN can be used as parallel pin
controls).
The pin has an internal 100-kΩ pull-down resistor to DRGND.
SCLK
This pin functions as serial interface clock input when RESET is low.
It functions as LOW SPEED MODE control when RESET is tied high. See
Table 4 for detailed information.
I
29
1
The pin has an internal 100-kΩ pull-down resistor to DRGND.
24
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Table 22. PIN ASSIGNMENTS – CMOS Mode (continued)
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
PIN NAME
SDATA
DESCRIPTION
This pin functions as serial interface data input when RESET is low.
It functions as STANDBY control pin when RESET is tied high.
I
28
1
See Table 5 for detailed information.
The pin has an internal 100-kΩ pull-down resistor to DRGND.
SEN
This pin functions as serial interface enable input when RESET is low.
It functions as CLKOUT edge programmability when RESET is tied high. See
Table 6 for detailed information.
I
27
1
The pin has an internal 100-kΩ pull-up resistor to DRVDD.
OE
Output buffer enable input, active high.
The pin has an internal 100-kΩ pull-up resistor to DRVDD.
I
I
7
6
1
1
DFS
Data Format Select input.
This pin sets the DATA FORMAT (Twos complement or Offset binary) and
the LVDS/CMOS output mode type. See Table 7 for detailed information.
The pin has an internal 100-kΩ pull-down resistor to DRGND.
MODE
Mode select input.
I
23
1
This pin selects the Internal or External reference mode. See Table 8 for
detailed information.
The pin has an internal 100-kΩ pull-down resistor to AGND.
CLKOUT
D0
CMOS output clock
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
5
31
32
33
34
37
38
39
40
41
42
43
44
45
46
47
48
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
CMOS output data D0
D1
CMOS output data D1
D2
CMOS output data D2
D3
CMOS output data D3
D4
CMOS output data D4
D5
CMOS output data D5
D6
CMOS output data D6
D7
CMOS output data D7
D8
CMOS output data D8
D9
CMOS output data D9
D10
D11
D12
D13
D14
D15
OVR
DRVDD
DRGND
UNUSED
PAD
NC
CMOS output data D10
CMOS output data D11
CMOS output data D12
CMOS output data D13
CMOS output data D14
CMOS output data D15
Out-of-range indicator, CMOS level signal
Digital and output buffer supply
Digital and output buffer ground
Unused pin in CMOS mode
Connect the PAD to the ground plane. See in application section.
Do not connect
2, 35
1, 36
4
I
-
-
21
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TYPICAL CHARACTERISTICS
Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = Max Rated, sine wave input clock, 1.5 VPP clock
amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, DDR LVDS interface, default fine
gain (1dB), (unless otherwise noted)
ADS5562 - 80MSPS
FFT for 5 MHz, -1dBFS Input Signal
FFT for 20 MHz, -1dBFS Input Signal
0
−20
0
−20
SFDR = 88.88 dBc
SINAD = 81.4 dBFS
SNR = 82.86 dBFS
THD = 85.87 dBc
SFDR = 91.54 dBc
SINAD = 81.53 dBFS
SNR = 82.64 dBFS
THD = 87.02 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−140
−160
−180
−100
−120
−140
−160
−180
0
10
20
30
40
0
10
20
30
40
f − Frequency − MHz
f − Frequency − MHz
G001
G002
Figure 10.
Figure 11.
FFT for 5 MHz, -80dBFS Input Signal (Small signal)
Inter-modulation Distortion
0
−20
0
−20
F1 = 5.01 MHz, –7 dBFS
A
= −80 dBFS
IN
F2 = 10.1 MHz, –7 dBFS
F1 + 2F2 = –92.1 dBFS
2F2 − F1 = –92.4 dBFS
2F1 + F2 = –94.2 dBFS
2F1 − F2 = –95.5 dBFS
3F1 = –99 dBFS
SFDR = 21.9 dBc
SINAD = 84.3 dBFS
SNR = 84.3 dBFS
THD = 33 dBc
−40
−40
−60
−60
3F2 = −102 dBFS
−80
−80
Worst Spur = −103.5 dBFS
−100
−120
−140
−160
−180
−100
−120
−140
−160
−180
0
10
20
30
40
0
10
20
30
40
f − Frequency − MHz
f − Frequency − MHz
G004
G003
Figure 12.
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = Max Rated, sine wave input clock, 1.5 VPP clock
amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, DDR LVDS interface, default fine
gain (1dB), (unless otherwise noted)
SNR vs Fin, 0 dB gain
SFDR vs Fin
86
85
84
83
82
81
80
79
78
96
92
88
84
80
76
LVDS
CMOS
0
5
10
15
20
25
30
0
5
10
15
20
25
30
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G006
G007
Figure 14.
Figure 15.
SFDR Across Fine Gain
SNR Across Fine Gain
Input adjusted to get −1dBFS input
0 dB
98
96
94
92
90
88
86
84
82
80
78
87
86
85
84
83
82
81
80
79
78
77
Input adjusted to get −1dBFS input
2 dB
3 dB
4 dB
2 dB
3 dB
1 dB
5 dB
6 dB
0 dB
1 dB
4 dB
5
5 dB
10
6 dB
15
0
5
10
15
20
25
30
0
20
25
30
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G009
G010
Figure 16.
Performance vs AVDD Supply
Figure 17.
Performance vs DRVDD Supply
96
94
92
90
88
86
84
82
80
90
92
90
88
86
84
82
80
78
76
90
f
= 5.01 MHz
f
= 5.01 MHz
IN
IN
89
88
87
86
85
84
83
82
89
88
87
86
85
84
83
82
DRV = 3.3 V
DD
AV = 3.3 V
DD
SFDR
SFDR
SNR
3.3
SNR
3.3
3.0
3.1
3.2
3.4
3.5
3.6
3.0
3.1
3.2
3.4
3.5
3.6
AV − Supply Voltage − V
DD
DRV − Supply Voltage − V
DD
G013
G014
Figure 18.
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = Max Rated, sine wave input clock, 1.5 VPP clock
amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, DDR LVDS interface, default fine
gain (1dB), (unless otherwise noted)
Performance vs Temperature
Performance vs Input Amplitude, 0 dB gain
92
90
88
86
84
82
80
88
87
86
85
84
83
82
120
110
100
90
91
f
IN
= 10.1 MHz
SFDR (dBFS)
89
87
85
83
81
79
77
75
SFDR
SNR (dBFS)
80
70
SFDR (dBc)
SNR
60
50
f
IN
= 5.01 MHz
−10
40
−60
−40
−20
0
20
40
60
80
−50
−40
−30
−20
0
T − Temperature − °C
Input Amplitude − dBFS
G015
G016
G018
G020
Figure 20.
Figure 21.
Performance vs Clock Amplitude
Performance vs Clock Duty Cycle
94
92
90
88
86
84
82
80
78
88
87
86
85
84
83
82
81
80
96
92
88
84
80
76
72
87
86
85
84
83
82
81
f
= 5.01 MHz
SFDR
SNR
50
f
= 10.1 MHz
IN
IN
SFDR
SNR
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
35
40
45
55
60
65
Input Clock Duty Cycle − %
Input Clock Amplitude − V
PP
G017
Figure 22.
Figure 23.
Output Noise Histogram
Performance in External Reference Mode
90
88
86
84
82
80
87
86
85
84
83
82
40
35
30
25
20
15
10
5
f
IN
= 5.01 MHz
RMS (LSB) = 1.424
External Reference Mode
SFDR
SNR
0
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70
V
VCM
− VCM Voltage − V
Output Code
G019
Figure 24.
Figure 25.
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TYPICAL CHARACTERISTICS (continued)
Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = Max Rated, sine wave input clock, 1.5 VPP clock
amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, DDR LVDS interface, default fine
gain (1dB), (unless otherwise noted)
ADS5560 - 40MSPS
FFT for 5 MHz, -1dBFS Input Signal
FFT for 20 MHz, -1dBFS Input Signal
0
−20
0
−20
SFDR = 92.7 dBc
SINAD = 82.5 dBFS
SNR = 83.2 dBFS
THD = 90 dBc
SFDR = 83.43 dBc
SINAD = 80.2 dBFS
SNR = 82.9 dBFS
THD = 82.55 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−140
−160
−180
−100
−120
−140
−160
−180
0
5
10
15
20
0
5
10
15
20
f − Frequency − MHz
f − Frequency − MHz
G022
G023
Figure 26.
Figure 27.
FFT for 5 MHz, -80dBFS Input Signal
Inter-modulation Distortion
0
−20
0
−20
F1 = 10.1 MHz, –7 dBFS
A
= −80 dBFS
IN
F2 = 5.01 MHz, –7 dBFS
F2 − 2F1 = –98.1 dBFS
2F2 − F1 = –101.7 dBFS
2F2 + F1 = –102.7 dBFS
2F1 + F2 = –106 dBFS
3F2 = –104.7 dBFS
SFDR = 31.1 dBc
SINAD = 84.7 dBFS
SNR = 84.8 dBFS
THD = 29.1 dBc
−40
−40
−60
−60
3F1 = −105.4 dBFS
−80
−80
Worst Spur = −101.7 dBFS
−100
−120
−140
−160
−180
−100
−120
−140
−160
−180
0
5
10
15
20
0
5
10
15
20
f − Frequency − MHz
f − Frequency − MHz
G024
G025
Figure 28.
Figure 29.
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TYPICAL CHARACTERISTICS (continued)
Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = Max Rated, sine wave input clock, 1.5 VPP clock
amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, DDR LVDS interface, default fine
gain (1dB), (unless otherwise noted)
SNR vs Fin, 0 dB gain
SFDR vs Fin
86
85
84
83
82
81
80
79
78
96
92
88
84
80
76
LVDS
CMOS
0
5
10
15
20
25
30
0
5
10
15
20
25
30
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G027
G028
Figure 30.
Figure 31.
SFDR Across Fine Gain
SNR Across Fine Gain
100
98
96
94
92
90
88
86
84
82
80
87
86
85
84
83
82
81
80
79
78
77
Input adjusted to get −1dBFS input
2 dB
Input adjusted to get −1dBFS input
2 dB
0 dB
3 dB
3 dB
6 dB
1 dB
5 dB
4 dB
0 dB
1 dB
4 dB
5
5 dB
10
6 dB
15
0
5
10
15
20
25
30
0
20
25
30
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G030
G031
Figure 32.
Performance vs AVDD Supply
Figure 33.
Performance vs DRVDD Supply
98
90
100
98
96
94
92
90
88
86
84
90
f
= 5.01 MHz
f
= 5.01 MHz
IN
IN
96
94
92
90
88
86
84
82
89
88
87
86
85
84
83
82
89
88
87
86
85
84
83
82
DRV = 3.3 V
DD
AV = 3.3 V
DD
SFDR
SFDR
SNR
3.3
SNR
3.3
3.0
3.1
3.2
3.4
3.5
3.6
3.0
3.1
3.2
3.4
3.5
3.6
AV − Supply Voltage − V
DD
DRV − Supply Voltage − V
DD
G034
G035
Figure 34.
Figure 35.
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TYPICAL CHARACTERISTICS (continued)
Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = Max Rated, sine wave input clock, 1.5 VPP clock
amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, DDR LVDS interface, default fine
gain (1dB), (unless otherwise noted)
Performance vs Temperature
Performance vs Input Amplitude, 0 dB gain
98
96
94
92
90
88
86
88
87
86
85
84
83
82
120
110
100
90
91
89
87
85
83
81
79
77
75
f
IN
= 10.1 MHz
SFDR (dBFS)
SFDR
SNR (dBFS)
SFDR (dBc)
80
70
SNR
60
50
f
IN
= 5.01 MHz
−10
40
−60
−40
−20
0
20
40
60
80
−50
−40
−30
−20
0
T − Temperature − °C
Input Amplitude − dBFS
G036
G037
G039
G041
Figure 36.
Figure 37.
Performance vs Clock Amplitude
Performance vs Clock Duty Cycle
94
92
90
88
86
84
82
80
78
88
87
86
85
84
83
82
81
80
100
96
92
88
84
80
76
86
84
82
80
78
76
74
f
= 5.01 MHz
f
= 10.1 MHz
IN
SFDR
SNR
IN
SFDR
SNR
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
35
40
45
50
55
60
65
Input Clock Amplitude − V
Input Clock Duty Cycle − %
PP
G038
Figure 38.
Figure 39.
Output Noise Histogram
Performance in External Reference Mode
92
90
88
86
84
82
87
86
85
84
83
82
40
35
30
25
20
15
10
5
f
IN
= 5.01 MHz
RMS (LSB) = 1.429
External Reference Mode
SFDR
SNR
0
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70
V
VCM
− VCM Voltage − V
Output Code
G040
Figure 40.
Figure 41.
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TYPICAL CHARACTERISTICS (continued)
Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = Max Rated, sine wave input clock, 1.5 VPP clock
amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, DDR LVDS interface, default fine
gain (1dB), (unless otherwise noted)
Valid Up to Max Clock Rate (ADS5562 or ADS5560)
CMRR vs Common-Mode Frequency
100
90
80
70
60
50
40
30
20
10
0
0
20
40
60
80
100
f
IN
− Input Frequency − MHz
G043
Figure 42.
Power Dissipation vs Sampling Frequency
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
CMOS, No-Load Capacitance
CMOS, 5-pF Load Capacitance
CMOS, 10-pF Load Capacitance
LVDS
25
40
50
65
80
f
S
− Sampling Frequency − MSPS
G044
Figure 43.
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TYPICAL CHARACTERISTICS (continued)
Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = Max Rated, sine wave input clock, 1.5 VPP clock
amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, DDR LVDS interface, default fine
gain (1dB), (unless otherwise noted)
SFDR Contour, 0 dB Gain
80
84
84
84
70
82
84
84
84
84
60
86
86
88
50
40
30
88
82
90
84
90
88
92
86
82
5
10
15
fIN - Input Frequency - MHz
20
25
30
94
80
82
84
86
88
90
92
SFDR - dBc
M0049-04
Figure 44.
SNR Contour, 0 dB Gain
80
70
60
50
40
30
83
83.5
84
83.5
82.5
83
84
82
82.5
83.5
84
82
83
81.5
5
10
15
fIN - Input Frequency - MHz
20
25
30
81
81.5
82
82.5
83
83.5
84
84.5
SNR - dBFS
M0048-04
Figure 45.
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APPLICATION INFORMATION
THEORY OF OPERATION
ADS556X is a high performance 16-bit A/D converter family with sampling rates up to 80 MSPS. It is based on
switched capacitor technology and runs off a single 3.3-V supply. Once the signal is captured by the input
sample and hold, the input sample is sequentially converted by a series of small resolution stages. At every clock
edge, the sample propagates through the pipeline resulting in a data latency of 16 clock cycles. The output is
available as 16-bit data, in DDR LVDS or parallel CMOS and coded in either offset binary or binary 2’s
complement format.
Analog Input Circuit
The analog input consists of a switched-capacitor based differential sample and hold architecture, shown in
Figure 46.
This differential topology results in good ac-performance even for high input frequencies at high sampling rates.
The INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V (VCM). For a
full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM + 0.9 V and VCM –
0.9 V, resulting in a 3.6-VPP differential input swing.
Sampling
Switch
Lpkg
» 1 nH
Sampling
Capacitor
INP
Ron
10 W
10 W
Csamp
6 pF
Cp4
1 pF
Cbond
» 1 pF
Cp2
0.5 pF
Cp3
2 pF
Resr
100 W
Cp1
2 pF
Ron
10 W
Lpkg
» 1 nH
Cp4
1 pF
Csamp
6 pF
Ron
10 W
10 W
INM
Sampling
Capacitor
Cbond
» 1 pF
Cp2
0.5 pF
Cp3
2 pF
Resr
100 W
Sampling
Switch
S0322-02
Figure 46. Input Stage
Drive Circuit Recommendations
For optimum performance, the analog inputs have to be driven differentially. This improves the common-mode
noise immunity and even order harmonic rejection. A resistor in series with each input pin (about 15 Ω) is
recommended to damp out ringing caused by package parasitics. It is also necessary to present low impedance
(< 50 Ω) for the common mode switching currents. This can be achieved by using two resistors from each input
terminated to the common mode voltage (VCM).
Note that the device includes an internal R-C filter from each input to ground. The purpose of this filter is to
absorb the glitches caused by the opening and closing of the sampling capacitors. The filtering of the glitches
can be improved further using an external R-C-R filter.
In addition to the above, the drive circuit may have to be designed to provide a low insertion loss over the
desired frequency range and matched impedance to the source. While doing this, the ADC input impedance
must be considered. Figure 47 and Figure 48 show the impedance (Zin = Rin || Cin) looking into the ADC input
pins.
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100
10
1
0.1
0.01
0
100
200
300
400
500
f − Frequency − MHz
G045
Figure 47. ADC Analog Input Resistance (Rin) Across Frequency
10
8
6
4
2
0
0
100
200
300
400
500
f − Frequency − MHz
G046
Figure 48. ADC Analog Input Capacitance (Cin) Across Frequency
Example Driving Circuit
An example input configuration using RF transformers is shown in Figure 49. Here, an external R-C-R filter using
22pF has been used. Together with the series inductor (39nH), this combination forms a filter and absorbs the
sampling glitches. Due to the relatively large capacitor (22pF) in the R-C-R and the 15 ohms resistors in series
with each input pin, this drive circuit has low bandwidth and is suited for low input frequencies.
Note that the drive circuit has been terminated by 50 ohms near the ADC side. The termination is accomplished
by a 25 ohms resistor from each input to the 1.5V common-mode (VCM) from the device. This allows the analog
inputs to be biased around the required common-mode voltage.
The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order
harmonic performance. Connecting two identical RF transformers back to back helps minimize this mismatch and
good performance is obtained for high frequency input signals. An additional termination resistor pair may be
required between the two transformers (enclosed by the dashed lines in Figure 49). The centre point of this
termination is connected to ground to improve the balance between the P and M sides. The values of the
terminations between the transformers and on the secondary side have to be chosen to get an effective 50 ohms
(in the case of 50 ohms source impedance).
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ADS556x
39 nH
0.1 mF
0.1 mF
15 W
INP
50 W
0.1 mF
25 W
25 W
50 W
22 pF
50 W
50 W
INM
15 W
0.1 mF
1:1
1:1
39 nH
VCM
S0329-01
Figure 49. Drive Circuit Using RF transformers
Input Common-Mode
To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1-µF low-inductance capacitor
connected to ground. The VCM pin is designed to directly drive the ADC inputs. Each input pin of the ADC sinks
a common-mode current in the order of 6uA/MSPS(about 1mA at 80 MSPS) from the external drive circuit.
Reference
ADS556X has built-in internal reference that does not require external components. Design schemes are used to
linearize the converter load seen by the reference; this and the integration of the requisite reference capacitors
on-chip eliminates the need for external decoupling capacitors. The full-scale input range of the converter can be
controlled in the external reference mode as explained below. The internal or external reference modes can be
selected by controlling the MODE pin 23 (see Table 8 for details) or by programming the serial interface register
bit <REF>.
Internal Reference
When the device is in internal reference mode, the REFP and REFM voltages are generated internally.
Common-mode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analog
input pins.
External Reference
When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on the
VCM pin is buffered and gained internally, generating the REFP and REFM voltages. The differential input
voltage corresponding to full-scale is given by Equation 1. In this mode, the 1.5 V common-mode voltage to bias
the input pins has to be generated externally.
Full-scale differential input voltage, pp = (Voltage forced on VCM pin)´ 2.67´G
where G = 10-(Fine gain in dB/20)
(1)
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INTREF
Internal
Reference
VCM
INTREF
EXTREF
REFM
REFP
ADS556x
S0165-08
Figure 50. Reference Section
Programmable Fine Gain
ADS556x has programmable fine gain from 0 dB to 6dB in steps of 1 dB. The corresponding full-scale input
range varies from 3.6VPP down to 2VPP. The fine gain is useful, when lower full-scale input ranges are used to
get SFDR improvement (See Figure 15 and Figure 31). This is accompanied by corresponding degradation in
SNR (see Figure 16 and Figure 32). The gain can be programmed using the register bits GAIN (Table 14).
After reset, the device is initialized to 1 dB fine gain.
Table 23. Full-scale Input Range Across Gains
Gain, dB
Corresponding full-scale input range, Vpp
(1)
0
3.56
1, default after reset
3.56
3.20
2.85
2.55
2.27
2.00
2
3
4
5
6
(1) Note that with 0 dB gain, the full-scale input range continues to be 3.56Vpp. This means that the output code range will be 58409 LSBs
(or 1dB below 65536).
Low Frequency Noise Suppression
The low-frequency noise suppression mode is specifically useful in applications where good noise performance is
desired in the low frequency band of dc to 1 MHz. Setting this mode shifts the low-frequency noise of the
ADS556x to approximately (Fs/2), thereby moving the noise floor around dc to a much lower value. Register bit
<LF NOISE SUPPRESSION> enables this mode. As Figure 52 shows, when the mode is enabled, the noise floor
from dc-1 MHz improves significantly. The low frequency noise components get shifted to the region around Fs/2
(Figure 53).
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0
−20
−40
−60
−80
−100
−120
−140
0
5
10
15
20
25
30
35
40
f − Frequency − MHz
G047
Figure 51. Spectrum with LF Noise Suppression Enabled (Fs=80 MSPS)
0
−20
−40
−60
LF Noise Suppression Enabled
−80
LF Noise Suppression Disabled
−100
−120
−140
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
f − Frequency − MHz
G048
Figure 52. Zoomed Spectrum (dc to 1 MHz) with LF Noise Suppression Enabled (Fs=80 MSPS)
0
−20
−40
−60
−80
LF Noise Suppression Disabled
LF Noise Suppression Enabled
−100
−120
−140
39.0 39.1 39.2 39.3 39.4 39.5 39.6 39.7 39.8 39.9 40.0
f − Frequency − MHz
G049
Figure 53. Zoomed Spectrum (39 to 40 MHz) with LF Noise Suppression Enabled (Fs=80 MSPS)
Low Sampling Frequency Operation
For best performance at high sampling frequencies, ADS556X uses a clock generator circuit to derive internal
timing for the ADC. The clock generator operates from 80 MSPS down to 30 MSPS in the DEFAULT SPEED
mode. The ADC enters this mode after applying reset (with serial interface configuration) or by tying SCLK pin to
low (with parallel configuration).
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For low sampling frequencies (below 30 MSPS), the ADC must be put in the LOW SPEED mode. This mode can
be entered by
•
•
setting the register bit <LOW SPEED> (Table 12) through the serial interface, OR
tying the SCLK pin to high (see Table 4) using the parallel configuration.
Clock Input
ADS556X clock input can be driven with either a differential clock signal or a single-ended clock input, with little
or no difference in performance between both configurations. The common-mode voltage of the clock inputs is
set to VCM using internal 5-kΩ resistors that connect CLKP and CLKM to VCM, as shown in Figure 54.
VCM
VCM
5 kW
5 kW
CLKP
CLKM
ADS556x
S0166-05
Figure 54. Clock Inputs
For the best performance, it is recommended to drive the clock inputs differentially, reducing susceptibility to
common-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with
0.1-µF capacitors, as shown in Figure 55.
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0.1 mF
CLKP
Differential Sine-Wave
or Square Wave
0.1 mF
CLKM
ADS556x
S0167-08
Figure 55. Differential Clock Drive
When driven with a single-ended CMOS clock input, connect CLKM to ground with a 0.1-µF capacitor and CLKP
with a 0.1-µF capacitor to the clock source, as shown in Figure 56.
0.1 mF
Square or Sine-Wave
Input
CLKP
0.1 mF
CLKM
ADS556x
S0168-12
Figure 56. Single-Ended Clock Drive
For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass
filtering of the clock source can help reduce the effect of jitter. There is little change in performance with a
non-50% duty cycle clock input.
Power Down
ADS556X has three power-down modes – global STANDBY, output buffer disabled, and input clock stopped.
Global STANDBY
This mode can be initiated by controlling SDATA or by setting the register bit <STBY> through the serial
interface. In this mode, the A/D converter, reference block and the output buffers are powered down resulting in
reduced total power dissipation of about 155 mW. The wake-up time from global power down to valid data is
typically 60 µs.
Output Buffer Disable
The output buffers can be disabled using OE pin in both the LVDS and CMOS modes. With the buffers disabled,
the digital outputs are three-stated. The wake-up time from this mode to data becoming valid in normal mode is
typically 700 ns in LVDS mode and 200 ns in CMOS mode.
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Input Clock Stop
The converter enters this mode when the input clock frequency falls below 1 MSPS. The power dissipation is
about 125 mW and the wake-up time from this mode to data becoming valid in normal mode is typically 80 µs.
Power Supply Sequence
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are
separated inside the device. Externally, they can be driven from separate supplies or from a single supply.
Output Interface
ADS556X provides 16-bit data, an output clock synchronized with the data and an out-of-range indicator that
goes high when the output reaches the full-scale limits. In addition, output enable control (OE) is provided to
power down the output buffers and put the outputs in high-impedance state.
Two output interface options are available – Double Data Rate (DDR) LVDS and parallel CMOS. They can be
selected using the DFS or the serial interface register bit <ODI> (see Table 7).
DDR LVDS Outputs
In this mode, the 16 data bits and the output clock are put out using LVDS (Low Voltage Differential Signal)
levels. Two successive data bits are multiplexed and output on each LVDS differential pair as shown in
Figure 57. So, there are 8 LVDS output pairs for the data bits and 1 LVDS output pair for the output clock.
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Pins
CLKOUTP
Output Clock
CLKOUTM
D0_D1_P
Data Bits D0. D1
D0_D1_M
D2_D3_P
Data Bits D2, D3
D2_D3_M
D4_D5_P
Data Bits D4, D5
D4_D5_M
D6_D7_P
Data Bits D6, D7
D6_D7_M
D8_D9_P
Data Bits D8, D9
D8_D9_M
D10_D11_P
Data Bits D10, D11
D10_D11_M
D12_D13_P
Data Bits D12, D13
D12_D13_M
D14_D15_P
Data Bits D14, D15
D14_D15_M
OVR
Out-of-Range Indicator
ADS556x
S0169-03
Figure 57. DDR LVDS Outputs
Even data bits (D0, D2...D14) are output at the falling edge of CLKOUTP and the odd data bits (D1, D3...D15)
are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP have to be used to
capture all the data bits (see Figure 58).
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CLKOUTP
CLKOUTM
D0_D1_P,
D0_D1_M
D0
D2
D1
D3
D0
D2
D1
D3
D2_D3_P,
D2_D3_M
D4_D5_P,
D4_D5_M
D4
D5
D4
D5
D6_D7_P,
D6_D7_M
D6
D7
D6
D7
D8_D9_P,
D8_D9_M
D8
D9
D8
D9
D10_D11_P,
D10_D11_M
D10
D12
D14
D11
D13
D15
D10
D12
D14
D11
D13
D15
D12_D13_P,
D12_D13_M
D14_D15_P,
D14_D15_M
Sample N
Sample N+1
T0110-04
Figure 58. DDR LVDS Interface
LVDS Buffer Current Programmability
The default LVDS buffer output current is 3.5 mA. When terminated by 100 Ω, this results in logic HIGH of +350
mV and logic LOW of -350 mV. The LVDS buffer currents can also be programmed to 2.5 mA, 4.5 mA, and 1.95
mA using the serial interface. In addition, there exists a current double mode, where this current is doubled for
the data and output clock buffers.
Both the buffer current programming and the current double mode can be done separately for the data buffers
and the output clock buffer (register bits <LVDS CURR>).
LVDS Buffer Internal Termination
An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially
terminated inside the device. These termination resistances are available – 325, 200, and 175 Ω (nominal with
±20% variation). Any combination of these three terminations can be programmed; the effective termination will
be the parallel combination of the selected resistances. This results in eight effective terminations from open (no
termination) to 75 Ω.
The internal termination helps to absorb any reflections coming from the receiver end, improving the signal
integrity. With 100 Ω internal and 100 Ω external termination, the voltage swing at the receiver end will be halved
(compared to no internal termination). The terminations can be controlled using register bits <DATA TERM> and
<CLKOUT TERM>.
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The voltage swing can be restored by using the LVDS current double mode (register bit <CURR DOUBLE>).
Parallel CMOS
In this mode, the digital data and output clock are put out as 3.3-V CMOS voltage levels. Each data bit and the
output clock is available on a separate pin in parallel. By default, the data outputs are valid during the rising edge
of the output clock. The output clock is CLKOUT.
Output Clock Position Programmability
In both the LVDS and CMOS modes, the output clock can be moved around its default position. This can be
done using SEN pin (as described in Table 6) or using the serial interface register bits <CLKOUT POSN>
(Table 11).
Output Data Format
Two output data formats are supported – 2s complement and offset binary. They can be selected using DFS pin
or the serial interface register bit <DFS> ( see Table 9). In the event of an input voltage overdrive, the digital
outputs go to the appropriate full scale level. For a positive overdrive, the output code is 0xFFFF in offset binary
output format, and 0x7FFF in 2s complement output format. For a negative input overdrive, the output code is
0x0000 in offset binary output format and 0x8000 in 2s complement output format.
Board Design Considerations
Grounding
A single ground plane is sufficient to give good performance, provided the analog, digital and clock sections of
the board are cleanly partitioned. See the EVM User Guide (SLWU028) for details on layout and grounding.
Supply de-coupling
As ADS556X already includes internal decoupling, minimal external decoupling can be used without loss in
performance. Note that decoupling capacitors can help to filter external power supply noise, so the optimum
number of capacitors would depend on the actual application. The decoupling capacitors should be placed very
close to the converter supply pins. It is recommended to use separate supplies for the analog and digital supply
pins to isolate digital switching noise from sensitive analog circuitry. In case only a single 3.3V supply is
available, it should be routed first to AVDD. It can then be tapped and isolated with a ferrite bead (or inductor)
with decoupling capacitor, before being routed to DRVDD.
Exposed thermal pad
It is necessary to solder the exposed pad at the bottom of the package to a ground plane for best thermal
performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and QFN/SON
PCB Attachment (SLUA271).
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low
frequency value.
Aperture Delay
The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling
occurs.
Aperture Jitter
The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle
The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width)
to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential
sine-wave clock results in a 50% duty cycle.
Maximum Sample Rate
The maximum conversion rate at which certified operation is given. All parametric testing is performed at this
sampling rate unless otherwise noted.
Minimum Sample Rate
The minimum conversion rate at which the ADC functions.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the
deviation of any single step from this ideal value, measured in units of LSBs
Integral Nonlinearity (INL)
The INL is the deviation of the ADC’s transfer function from a best fit line determined by a least squares curve fit
of that transfer function, measured in units of LSBs.
Gain Error
The gain error is the deviation of the ADC’s actual input full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale range.
Offset Error
The offset error is the difference, given in number of LSBs, between the ADC’s actual average idle channel
output code and the ideal average idle channel output code. This quantity is often mapped into mV.
Temperature Drift
The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree
Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation of the parameter
across the TMIN to TMAX range by the difference TMAX–TMIN
.
Signal-to-Noise Ratio
SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc
and the first nine harmonics.
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P
P
s
SNR + 10Log10
N
(2)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components
including noise (PN) and distortion (PD), but excluding dc.
P
s
SINAD + 10Log10
P
) P
N
D
(3)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Effective Number of Bits (ENOB)
The ENOB is a measure of a converter’s performance as compared to the theoretical limit based on quantization
noise.
SINAD * 1.76
ENOB +
6.02
(4)
(5)
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD).
P
P
s
THD + 10Log10
N
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR)
The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic).
SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion
IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral
component at either frequency 2f1–f2 or 2f2–f1. IMD3 is either given in units of dBc (dB to carrier) when the
absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the
fundamental is extrapolated to the converter’s full-scale range.
Voltage Overload Recovery
The number of clock cycles taken to recover to less than 1% error for a 6-dB overload on the analog inputs.
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PACKAGE OPTION ADDENDUM
www.ti.com
13-May-2008
PACKAGING INFORMATION
Orderable Device
ADS5560IRGZR
ADS5560IRGZT
ADS5562IRGZR
ADS5562IRGZT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFN
RGZ
48
48
48
48
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
QFN
QFN
QFN
RGZ
RGZ
RGZ
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-May-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
ADS5560IRGZR
ADS5560IRGZT
ADS5562IRGZR
ADS5562IRGZT
QFN
QFN
QFN
QFN
RGZ
RGZ
RGZ
RGZ
48
48
48
48
2500
250
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
1.5
1.5
1.5
1.5
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
Q2
Q2
Q2
Q2
2500
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-May-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS5560IRGZR
ADS5560IRGZT
ADS5562IRGZR
ADS5562IRGZT
QFN
QFN
QFN
QFN
RGZ
RGZ
RGZ
RGZ
48
48
48
48
2500
250
333.2
333.2
333.2
333.2
345.9
345.9
345.9
345.9
28.6
28.6
28.6
28.6
2500
250
Pack Materials-Page 2
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相关型号：
ADS5560IRGZTG4
1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL/PARALLEL ACCESS, PQCC48, 7 X 7 MM, GREEN, PLASTIC, VQFN-48
TI
ADS5562IRGZRG4
1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL/PARALLEL ACCESS, PQCC48, 7 X 7 MM, GREEN, PLASTIC, VQFN-48
TI
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