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ADS58J63

ZHCSDU3A –JUNE 2015–REVISED JUNE 2015

ADS58J63 四通道、14 位、500MSPS 电信接收器

1 特性

3 说明

1

•

四通道

ADS58J63 是一款低功耗、高带宽、14 位、

500MSPS、四通道电信接收器。 ADS58J63 支持

14 位分辨率

JESD204B 串行接口，每个通道上具有 1 条信道，数

据传输速率高达 10Gbps。经缓冲的模拟输入可在较

宽频率范围内提供统一输入阻抗，并最大程度地降低采

样和保持毛刺脉冲能量。 ADS58J63 以超低功耗在宽

输入频率范围内提供出色的无杂散动态范围 (SFDR)。

数字信号处理模块包含复混频器，后接低通滤波器。低

通滤波器具有 2 倍抽取率和 4 倍抽取率两个选项，支

持高达 200MHz 的接收器带宽。此外，ADS58J63 在

突发模式下还支持 14 位、500MSPS 输出，因此适用

于 DPD 观测接收器。

最大时钟速率：500MSPS

输入带宽 (3dB)：900MHz

片上抖动

具有高阻抗输入的模拟输入缓冲器

输出选项：

–

Rx：2 倍抽取率和 4 倍抽取率（低通滤波器）

200MHz 复带宽或 100MHz 实带宽支持

DPD FB：突发模式，14 位输出

•

1.9 V_PP差分满量程输入

JESD204B 接口：

–

支持子类 1

JESD204B 接口减少了接口线路数，从而实现高系统

集成度。内部锁相环 (PLL) 会将传入的模数转换器

(ADC) 采样时钟加倍，以获得串行化各通道的 14 位数

据时所使用的位时钟。

每个 ADC 一条信道，速率高达 10Gsps

专用于通道对的 SYNC 引脚

•

支持多芯片同步

72 引脚超薄型四方扁平无引线 (VQFN) 封装

(10mm × 10mm)

器件信息⁽¹⁾

器件型号

ADS58J63

封装

封装尺寸（标称值）

•

主要技术规格：

VQFN (72)

10.00mm x 10.00mm

–

功耗：每通道 675mW

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

频谱性能（未抽取）

–

f_IN= 190MHz 中频 (IF)（–1dBFS 时）：

简化框图

–

信噪比 (SNR)：70.4dBFS

噪声频谱密度 (NSD)：–154.4dBFS/Hz

Digital Block

2x

14bit

ADC

Interleaving

Correction

INAP/M

INBP/M

DAP/M

C{ꢀ4

无杂散动态范围

(SFDR)：86dBc（HD2，HD3），

95dBFS（非 HD2，HD3）

4x

2x

JESD204B

Digital Block

Interleaving

Correction

Y*C{ꢀ16

14bit

ADC

C{ꢀ8

DBP/M

Burst Mode

TRIGAB

–

f_IN= 370 MHz IF（–3dBFS 时）：

TRIGCD

TRDYAB

TRDYCD

–

SNR：68.5dBFS

SYSREFP/M

CLKINP/M

NSD：–152.5dBFS/Hz

PLL

x10/x20

SYNCbAB

SYNCbCD

SFDR：81dBc（HD2，HD3），

86dBFS（非 HD2，HD3）

Burst Mode

Digital Block

Interleaving

Correction

14bit

ADC

INCP/M

INDP/M

DCP/M

DDP/M

2x

C{ꢀ4

JESD204B

Digital Block

Interleaving

Correction

4x

2x

2 应用

14bit

ADC

Y*C{ꢀ16

C{ꢀ8

•

多载波 GSM 蜂窝基础设施基站

多载波多模式蜂窝基础设施基站

电信接收器

Configuration

Registers

电信数字预失真 (DPD) 观测接收器

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBAS717

ADS58J63

ZHCSDU3A –JUNE 2015–REVISED JUNE 2015

www.ti.com.cn

7.2 Functional Block Diagram ....................................... 21

7.3 Feature Description................................................. 22

7.4 Device Functional Modes........................................ 23

7.5 Programming .......................................................... 34

7.6 Register Maps......................................................... 45

Application and Implementation ........................ 71

8.1 Application Information............................................ 71

8.2 Typical Application .................................................. 75

Power Supply Recommendations...................... 76

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 6

6.6 AC Performance ...................................................... 7

6.7 Digital Characteristics ............................................. 10

6.8 Timing Characteristics............................................. 11

6.9 Typical Characteristics: 14-Bit Burst Mode............. 12

6.10 Typical Characteristics: Mode 2............................ 19

6.11 Typical Characteristics: Mode 0............................ 20

Detailed Description ............................................ 21

7.1 Overview ................................................................. 21

8

9

10 Layout................................................................... 77

10.1 Layout Guidelines ................................................. 77

10.2 Layout Example .................................................... 77

11 器件和文档支持 ..................................................... 78

11.1 社区资源................................................................ 78

11.2 商标....................................................................... 78

11.3 静电放电警告......................................................... 78

11.4 Glossary................................................................ 78

12 机械、封装和可订购信息....................................... 78

7

4 修订历史记录

Changes from Original (June 2015) to Revision A

Page

•

已从“产品预览”更改为“量产”数据表......................................................................................................................................... 1

2

ADS58J63

www.ti.com.cn

ZHCSDU3A –JUNE 2015–REVISED JUNE 2015

5 Pin Configuration and Functions

RMP Package

VQFN-72

Top View

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

TRDYCD

TRIGCD

DGND

1

2

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

TRDYAB

TRIGAB

DGND

IOVDD

PDN

3

IOVDD

4

5

SDIN

SCLK

6

RES

7

SEN

RESET

DVDD

AVDD

AVDD3V

AVDD

INAP

DVDD

8

9

AVDD

AVDD3V

SDOUT

AVDD

ADS58J63

10

11

12

13

14

15

16

17

18

GND PAD (backside)

INDP

INDM

INAM

AVDD

AVDD3V

AVDD

INBM

AVDD3V

AVDD

INCM

35

36

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

3

ADS58J63

ZHCSDU3A –JUNE 2015–REVISED JUNE 2015

www.ti.com.cn

Pin Functions

I/O

DESCRIPTION

NAME

INPUT/REFERENCE

INAP/M

NUMBER

42, 41

36, 37

19, 18

13, 14

I

Differential analog input for channel A

Differential analog input for channel B

Differential analog input for channel C

Differential analog input for channel D

INBP/M

INCP/M

INDP/M

CLOCK/SYNC

CLKINP/M

SYSREFP/M

CONTROL/SERIAL

RESET

27, 28

33, 34

I

Differential clock input for ADC

External sync input

48

6

I

Hardware reset. Active high. This pin has an internal 150-kΩ pull-down resistor.

Serial interface clock input

SCLK

SDIN

5

I

Serial interface data input.

SEN

7

I

Serial interface enable

SDOUT

11

50

49

22, 23

O

Serial interface data output.

PDN

I/O Power down. Can be configured via SPI register setting.

RES

–

Reserve Pin. Connect to GND

No connect

NC

Trigger ready output for burst mode for channel A,B. Can be configured via SPI to TRDY signal

for all four channels in burst mode. Can be left open if not used.

TRDYAB

TRIGAB

TRDYCD

TRIGCD

54

53

1

O

I

Manual burst mode trigger input channel A,B. Can be configured via SPI to manual trigger input

signal for all four channels in burst mode. Can be connected to GND if not used.

Trigger ready output for burst mode for channel C,D. Can be configured via SPI to TRDY signal

for all four channels in burst mode. Can be left open if not used.

O

I

Manual burst mode trigger input channel C,D. Can be configured via SPI to manual trigger input

signal for all four channels in burst mode. Can be connected to GND if not used.

2

DATA INTERFACE

DAP/M

58, 59

61, 62

66, 65

69, 68

O

JESD204B Serial data output for channel A

JESD204B Serial data output for channel B

JESD204B Serial data output for channel C

JESD204B Serial data output for channel D

DBP/M

DCP/M

DDP/M

Synchronization input for JESD204B port channel A,B. Can be configured via SPI to SYNCb

signal for all four channels. Needs external termination.

SYNCbABP/M

55, 56

72, 71

I

Synchronization input for JESD204B port channel C,D. Can be configured via SPI to SYNCb

signal for all four channels. Needs external termination.

SYNCbCDP/M

POWER SUPPLY

10, 16, 24, 31,

39, 45

AVDD3V

I

Analog 3 V for analog buffer

Analog 1.9-V power supply

9, 12, 15, 17,

20, 25, 30, 35,

38, 40, 43, 44,

46

AVDD

DVDD

IOVDD

AGND

DGND

8, 47

I

Digital 1.9-V power supply

Digital 1.15-V power supply for the JESD204B transmitter

Analog ground

4, 51, 57, 64,

70

21, 26, 29, 32

3, 52, 60, 63,

67

Digital ground

4

ADS58J63

www.ti.com.cn

ZHCSDU3A –JUNE 2015–REVISED JUNE 2015

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–0.2

–0.3

MAX

UNIT

V

AVDD3V

3.6

AVDD

Supply voltage range:

DVDD

2.1

V

2.1

V

IOVDD

Voltage between AGND and DGND

INA/BP, INA/BM, INC/DP, INC/DM

CLKINP, CLKINM

1.4

0.3

V

3

V

AVDD + 0.3

V

Voltage applied to input pins

SYSREFP, SYSREFM, TRIGAB, TRIGCD

V

SCLK, SEN, SDIN, RESET, SPI_MODE,

SYNCbABP/M, SYNCbCDP/M, PDN

–0.2

–65

2

V

Storage temperature, T_stg

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

V_(ESD)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±1

kV

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

2.85

1.8

NOM

3

MAX

3.6

2

UNIT

V

AVDD3V

AVDD

1.9

1.15

1.9

V

Supply voltage range:

Analog inputs:

DVDD

1.8

2

V

IOVDD

1.1

1.2

V

Differential input voltage range

Input common-mode voltage

V_PP

V

VCM ± 0.025

250

Input clock frequency, device clock frequency

Sine wave, ac-coupled

500

MHz

V_PP

1.5

1.6

Input clock amplitude differential

(V_CLKP– V_CLKM

Clock inputs:

LVPECL, ac-coupled

LVDS, ac-coupled

)

0.7

Input device clock duty cycle, default after reset

Operating free-air, T_A

Operating junction, T_J

45%

–40

50%

55%

85

ºC

Temperature:

105⁽²⁾

125

(1) SYSREF needs to be applied for the device bring up.

(2) Prolonged use above this junction temperature can increase the device failure-in-time (FIT) rate.

5

ADS58J63

ZHCSDU3A –JUNE 2015–REVISED JUNE 2015

www.ti.com.cn

6.4 Thermal Information

ADS58J63

THERMAL METRIC⁽¹⁾

RMP (VQFNP)

UNIT

72 PINS

22.3

5.1

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

R_θJC(top)

R_θJB

2.4

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

ψ_JB

2.3

R_θJC(bot)

0.4

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC Sampling Frequency = 500

Msps, 50% clock duty cycle, AVDD3V = 3 V, AVDD/DVDD = 1.9 V, IOVDD = 1.15 V, –1 -dBFS differential input for IF ≤ 250

MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.

PARAMETER

ADC Sampling Rate

TEST CONDITIONS

MIN

TYP

MAX

UNIT

500 MSPS

Bits

Resolution

POWER SUPPLY

AVDD3V

AVDD

14

2.85

1.8

3

1.9

3.6

2

V

DVDD

1.8

1.9

2

V

IOVDD

1.1

1.15

340

365

190

184

1.2

V

I_AVDD3V

I_AVDD

3-V analog supply current

mA

1.9-V analog supply current

2x Decimation (4 ch)

I_DVDD

I_IOVDD

Pdis

1.9-V digital supply current

370-MHz, full-scale

input on all four

channels

Burst Mode (4 ch)

1.15-V SERDES supply

current

533

mA

2x Decimation (4 ch)

Burst Mode (4 ch)

2.68

2.67

W

Total power dissipation

Global power-down power

dissipation

250

mW

ANALOG INPUTS

Differential input full-scale

1.9

V_PP

V

voltage

VCM ±

0.025

Input common-mode voltage

Diffrential input resistance

Differential input capacitance

Analog input bandwidth (3 dB)

at f_IN=370MHz

0.5

2.5

kΩ

pF

900

MHz

6

ADS58J63

www.ti.com.cn

ZHCSDU3A –JUNE 2015–REVISED JUNE 2015

Electrical Characteristics (continued)

Typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC Sampling Frequency = 500

Msps, 50% clock duty cycle, AVDD3V = 3 V, AVDD/DVDD = 1.9 V, IOVDD = 1.15 V, –1 -dBFS differential input for IF ≤ 250

MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ISOLATION

f_IN= 10 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 270 MHz

f_IN= 370 MHz

f_IN= 470 MHz

f_IN= 10 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 270 MHz

f_IN= 370 MHz

f_IN= 470 MHz

105

104

96

dBFS

Isolation between near

channels

(CHA and CHB are near to

each other.

CHC and CHD are near to

each other)

97

93

85

Crosstalk

(1)

110

107

96

Isolation between far channels

(for CHA and CHB, CHC and

CHD are far channels)

97

95

94

CLOCK INPUT

Internal clock biasing

CLKINP and CLKINM pins are connected to

internal biasing voltage through 400 Ω

1.15

V

(1) Crosstalk is measured with a –1-dBFS input signal on aggressor channel and no input on the victim channel.

6.6 AC Performance

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX UNIT

14-Bit Burst Mode

(DDC Mode 8)

Decimate-by-2 Filter

(DDC Mode 2)

f_IN= 10 MHz

70.8

70.5

69.5

74.1

74

f_IN= 70 MHz

A_IN= – 1 dBFS

A_IN= – 3 dBFS

73.2

73.6

72.6

72

f_IN= 190 MHz

65.6

64.6

70.3

69

SNR

Signal-to-noise ratio

dBFS

f_IN= 300 MHz

f_IN= 350 MHz

f_IN= 370 MHz

f_IN= 470 MHz

f_IN= 10 MHz

f_IN= 70 MHz

68.7

68.4

67.5

154.8

154.5

153.5

70.7

154.8

154.5

153.5

154.3

153.0

152.7

152.4

151.5

A_IN= – 1 dBFS

A_IN= – 3 dBFS

f_IN= 190 MHz

149.5 154.3

153

dBFS/

Hz

NSD

Noise spectral density

f_IN= 300 MHz

f_IN= 350 MHz

f_IN= 370 MHz

f_IN= 470 MHz

152.7

148.5 152.4

151.5

7

ADS58J63

ZHCSDU3A –JUNE 2015–REVISED JUNE 2015

www.ti.com.cn

MAX UNIT

AC Performance (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

f_IN= 10 MHz

MIN

TYP

70.7

70.4

69.4

70.2

68.9

68.6

68.2

66.9

89

MAX

MIN

TYP

73.9

73.1

73.5

72.5

71.7

f_IN= 70 MHz

A_IN= – 1 dBFS

A_IN= – 3 dBFS

f_IN= 190 MHz

Signal-to-noise and

distortion ratio

SINAD

SFDR

HD2

dBFS

dBc

f_IN= 300 MHz

f_IN= 350 MHz

f_IN= 370 MHz

f_IN= 470 MHz

f_IN= 10 MHz

f_IN= 70 MHz

69.7

88

87

95

A_IN= – 1 dBFS

A_IN= – 3 dBFS

86

97

f_IN= 190 MHz

78

75

88

96

Spurious-free dynamic

range

f_IN= 300 MHz

f_IN= 350 MHz

f_IN= 370 MHz

f_IN= 470 MHz

f_IN= 10 MHz

f_IN= 70 MHz

82

94

82

81

73

74

91

89

94

103

101

97

A_IN= – 1 dBFS

A_IN= – 3 dBFS

86

f_IN= 190 MHz

78

75

88

Second harmonic

distortion

f_IN= 300 MHz

f_IN= 350 MHz

f_IN= 370 MHz

f_IN= 470 MHz

f_IN= 10 MHz

f_IN= 70 MHz

82

81

73

74

88

93

87

99

A_IN= – 1 dBFS

A_IN= – 3 dBFS

98

100

98

f_IN= 190 MHz

78

75

97

HD3

Third harmonic distortion

f_IN= 300 MHz

f_IN= 350 MHz

f_IN= 370 MHz

f_IN= 470 MHz

f_IN= 10 MHz

f_IN= 70 MHz

95

100

96

90

85

83

98

95

97

96

94

A_IN= – 1 dBFS

A_IN= – 3 dBFS

93

f_IN= 190 MHz

Non

HD2,

HD3

Spurious-free dynamic

range (excluding HD2,

HD3)

87

80

93

f_IN= 300 MHz

f_IN= 350 MHz

f_IN= 370 MHz

f_IN= 470 MHz

92

91

90

87

93

8

ADS58J63

www.ti.com.cn

ZHCSDU3A –JUNE 2015–REVISED JUNE 2015

AC Performance (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

f_IN= 10 MHz

MIN

TYP

88

85

86

81

79

78

72

MAX

MIN

TYP

86

MAX UNIT

f_IN= 70 MHz

92

A_IN= – 1 dBFS

A_IN= – 3 dBFS

92

f_IN= 190 MHz

91

THD

Total harmonic distortion

dBc

f_IN= 300 MHz

f_IN= 350 MHz

f_IN= 370 MHz

f_IN= 470 MHz

89

82

73

f_IN= 185 MHz, f_IN

190 MHz

=

A_IN= – 7 dBFS

89

82

77

Third-tone intermodulation f_IN= 365 MHz, f_IN

IMD3

dBFS

distortion

370 MHz

f_IN= 465 MHz, f_IN

470 MHz

9

ADS58J63

ZHCSDU3A –JUNE 2015–REVISED JUNE 2015

www.ti.com.cn

6.7 Digital Characteristics

Typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 500

MSPS, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input,

unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, PDN)⁽¹⁾

V_IH

V_IL

High-level input voltage

Low-level input voltage

All digital inputs support 1.2-V and 1.8-V logic levels

0.8

V

All digital inputs support 1.2-V and 1.8-V logic levels

0.4

V

SEN

0

100

50

µA

I_IH

High-level input current

Low-level input current

RESET, SCLK, SDIN, PDN

SEN

I_IL

RESET, SCLK, SDIN, PDN

0

DIGITAL INPUTS (SYSREFP, SYSREFM, SYNCbABM, SYNCbABP, SYNCbCDM, SYNCbCDP)

V_D

Differential Input Voltage

0.35

0.45

1.3

1.4

V

V_{(CM_DIG)}

Common-mode voltage for SYSREF

DIGITAL OUTPUTS (SDOUT, PDN)

DVDD –

0.1

V_OH

V_OL

High-level output voltage

Low-level output voltage

DVDD

V

0.1

DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM)⁽²⁾

V_OD

V_OC

Output differential voltage

With default swing setting.

700

450

mV_PP

mV

Output common-mode voltage

Transmitter pins shorted to any voltage between

–0.25 V and 1.45 V

Transmitter short-circuit current

Single-ended output impedance

Output capacitance

–100

100

mA

Ω

z_os

50

2

Output capacitance inside the device,

from either output to ground

pF

(1) The RESET, SCLK, SDATA, and PDN pins have a 20-kΩ (typical) internal pulldown resistor to ground, and the SEN pin has a 20-kΩ

(typical) pull up resistor to IOVDD.

(2) 50-Ω, single-ended external termination to IOVDD.

10

ADS58J63

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6.8 Timing Characteristics

Typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 500

MSPS, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input,

unless otherwise noted.

MIN

TYP

MAX

UNITS

SAMPLE TIMING CHARACTERISTICS

Aperture delay

0.75

1.6

ns

ps

Aperture delay matching between two channels on the same device

±70

±270

135

Aperture delay matching between two devices at the same temperature and supply voltage

Aperture jitter

ps

f_Srms

µs

Wake-up time to valid data after coming out of global power-down

150

Input

Clock

Cycles

Data Latency⁽¹⁾

ADC sample to digital output

ADC sample to OVR bit

77

Input

Clock

Cycles

OVR Latency

44

4

Input clock rising edge cross-over to output clock rising edge

cross-over

t_PDI

Clock propagation delay

ns

t_{SU_SYSREF}Setup time for SYSREF, referenced to input clock rising edge

t_{H_SYSREF}Hold time for SYSREF, referenced to input clock rising edge

300

100

900

ps

JESD OUTPUT INTERFACE TIMING CHARACTERISTICS

Unit interval

100

2.5

400

10

ps

Gbps

ps

Serial output data rate

Total jitter for BER of 1E-15 and lane rate = 10 Gbps

Random jitter for BER of 1E-15 and lane rate = 10 Gbps

Deterministic jitter for BER of 1E-15 and lane rate = 10 Gbps

26

0.75

12

ps rms

ps, pk-pk

Data rise time, data fall time: rise and fall times measured from 20% to 80%, differential output

waveform, 2.5 Gbps ≤ bit rate ≤ 10 Gbps

t_R, t_F

35

ps

(1) Overall ADC Latency = Data Latency + t_PDI

N+1

N+2

N

SAMPLE

T_PD

Data Latency: 77 Clock Cycles

CLKINP

CLKINM

DAP/M

DBP/M

DCP/M

DDP/M

D

20

D

1

D

20

SAMPLE N-1

SAMPLE N

SAMPLE N+1

Figure 1. Latency Timing Diagram

11

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6.9 Typical Characteristics: 14-Bit Burst Mode

Typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC Sampling Frequency = 500

Msps, 14-bit Resolution, No Decimation Filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15

V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.

0

-20

0

-20

-40

-60

-80

-100

-120

-100

-120

0

50

100

150

200

250

0

50

100

150

200

250

Input Frequency (MHz)

D001

D002

F_IN= 10 MHz , A_IN= –1 dBFS

F_IN= 140 MHz , A_IN= –1 dBFS

SNR = 71 dBFS, SFDR = 89 dBc, SFDR = 89 dBc (Non23)

SNR = 70 dBFS, SFDR = 88 dBc, SFDR = 91 dBc (Non23)

Figure 2. FFT for 10-MHz Input Signal

Figure 3. FFT for 140-MHz Input Signal

0

-20

-40

-20

-40

-60

-80

-100

-120

-100

-120

0

50

100

150

200

250

0

50

100

150

200

250

Input Frequency (MHz)

D003

D004

F_IN= 190 MHz , A_IN= –1 dBFS

F_IN= 230 MHz , A_IN= –1 dBFS

SNR = 69.4 dBFS, SFDR = 88 dBc, SFDR = 96 dBc (Non23)

SNR = 69.4 dBFS, SFDR = 85 dBc, SFDR = 96 dBc (Non23)

Figure 4. FFT for 190-MHz Input Signal

Figure 5. FFT for 230-MHz Input Signal

0

-20

-40

-20

-40

-60

-80

-100

-120

-100

-120

0

50

100

150

200

250

0

50

100

150

200

250

Input Frequency (MHz)

D005

D006

F_IN= 300 MHz , A_IN= - 3 dBFS

F_IN= 370 MHz , A_IN= - 3 dBFS

SNR = 69.4 dBFS, SFDR = 80 dBc, SFDR = 95 dBc (Non23)

SNR = 68.4 dBFS, SFDR = 84 dBc, SFDR = 86 dBc (Non23)

Figure 6. FFT for 300-MHz Input Signal

Figure 7. FFT for 370-MHz Input Signal

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Typical Characteristics: 14-Bit Burst Mode (continued)

Typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC Sampling Frequency = 500

Msps, 14-bit Resolution, No Decimation Filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15

V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.

0

-20

-40

-60

-80

-100

-120

-100

-120

0

50

100

150

200

250

0

50

100

150

200

250

Input Frequency (MHz)

D007

D008

F_IN= 470 MHz , A_IN= - 3 dBFS

SNR = 67.4 dBFS, SFDR = 73 dBc, SFDR = 80 dBc (Non23)

F_IN1= 185 MHz, F_IN2= 190 MHz, IMD = 89 dBFS

Each tone at -7 dBFS

Figure 8. FFT for 470-MHz Input Signal

Figure 9. FFT for Two-Tone Input Signal

0

-20

-40

-20

-40

-60

-80

-100

-120

-100

-120

0

50

100

150

200

250

0

50

100

150

200

250

Input Frequency (MHz)

D009

D010

F_IN1= 185 MHz, F_IN2= 190 MHz, IMD = 103 dBFS

Each tone at -36 dBFS

F_IN1= 370 MHz, F_IN2= 365 MHz, IMD = 81.7 dBFS

Each tone at -7 dBFS

Figure 10. FFT for Two-Tone Input Signal

Figure 11. FFT for Two-Tone Input Signal

0

-20

-40

-60

-80

-20

-40

-60

-80

-100

-120

0

50

100

150

200

250

0

50

100

150

200

250

Input Frequency (MHz)

D011

D012

F_IN1= 370 MHz, F_IN2= 365 MHz, IMD = 102 dBFS

Each tone at -36 dBFS

F_IN1= 470 MHz, F_IN2= 465 MHz, IMD = 76.7 dBFS

Each tone at -7 dBFS

Figure 12. FFT for Two-Tone Input Signal

Figure 13. FFT for Two-Tone Input Signal

13

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Typical Characteristics: 14-Bit Burst Mode (continued)

Typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC Sampling Frequency = 500

Msps, 14-bit Resolution, No Decimation Filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15

V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.

0

-88

-90

-20

-92

-40

-94

-60

-96

-98

-80

-100

-102

-104

-100

-120

0

50

100

150

200

250

-35

-31

-27

-23

-19

-15

-11

-7

Input Frequency (MHz)

Each Tone Amplitude (dBFS)

D013

D014

F_IN1= 470 MHz, F_IN2= 465 MHz, IMD = 98.8 dBFS

Each tone at -36 dBFS

F_IN1= 185 MHz, F_IN2= 190 MHz

Figure 14. FFT for Two-Tone Input Signal

Figure 15. Intermodulation Distortion Vs Input Amplitude

-80

-74

-84

-88

-80

-86

-92

-96

-98

-100

-104

-35

-31

-27

-23

-19

-15

-11

-7

-35

-31

-27

-23

-19

-15

-11

-7

Each Tone Amplitude (dBFS)

D015

D016

F_IN1= 365 MHz, F_IN2= 370 MHz

F_IN1= 465 MHz, F_IN2= 470 MHz

Figure 16. Intermodulation Distortion Vs Input Amplitude

Figure 17. Intermodulation Distortion Vs Input Amplitude

96

Ain = -1 dBFS

Ain = -3 dBFS

92

93

90

87

84

81

78

88

84

80

76

72

0

40 80 120 160 200 240 280 320 360 400 440 480

Input Frequency (MHz)

0

40 80 120 160 200 240 280 320 360 400 440 480

Input Frequency (MHz)

D017

D018

Figure 18. Spurious-Free Dynamic Range vs Input

Frequency

Figure 19. IL Spur Vs Input Frequency

14

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Typical Characteristics: 14-Bit Burst Mode (continued)

Typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC Sampling Frequency = 500

Msps, 14-bit Resolution, No Decimation Filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15

V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.

71.5

70.5

69.5

68.5

67.5

66.5

72

71.2

70.4

69.6

68.8

68

AIN = -1 dBFS

AIN = -3 dBFS

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.95 V

AVDD = 2 V

0

40 80 120 160 200 240 280 320 360 400 440 480

Input Frequency (MHz)

-40

-15

10

35

60

85

Temperature (°C)

D019

D020

F_IN= 190 MHz, A_IN= – 1 dBFS

Figure 20. Signal-to-Noise Ratio vs Input Frequency

Figure 21. Signal-to-Noise Ratio vs AVDD Supply and

Temperature

93

72

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.95 V

AVDD = 2 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.95 V

AVDD = 2 V

71

70

69

68

67

66

91

89

87

85

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D021

D022

F_IN= 190 MHz, A_IN= – 1 dBFS

F_IN= 370 MHz, A_IN= – 3 dBFS

Figure 22. Spurious-Free Dynamic Range vs AVDD Supply

and Temperature

Figure 23. Signal-to-Noise Ratio vs AVDD Supply and

Temperature

84

71.4

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.95 V

AVDD = 2 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.95 V

DVDD = 2 V

71

70.6

70.2

69.8

69.4

83

82

81

80

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D023

D024

F_IN= 370 MHz, A_IN= – 3 dBFS

F_IN= 190 MHz, A_IN= – 1 dBFS

Figure 24. Spurious-Free Dynamic Range vs AVDD Supply

and Temperature

Figure 25. Signal-to-Noise Ratio vs DVDD Supply and

Temperature

15

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ZHCSDU3A –JUNE 2015–REVISED JUNE 2015

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Typical Characteristics: 14-Bit Burst Mode (continued)

Typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC Sampling Frequency = 500

Msps, 14-bit Resolution, No Decimation Filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15

V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.

92

91

90

89

88

87

86

71

70

69

68

67

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.95 V

DVDD = 2 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.95 V

DVDD = 2 V

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D025

D026

F_IN= 190 MHz, A_IN= – 1 dBFS

F_IN= 370 MHz, A_IN= – 3 dBFS

Figure 26. Spurious-Free Dynamic Range vs DVDD Supply

and Temperature

Figure 27. Signal-to-Noise Ratio vs DVDD Supply and

Temperature

72.2

84

AVDD3V = 2.85 V

AVDD3V = 3 V

AVDD3V = 3.1 V

AVDD3V = 3.2 V

AVDD3V = 3.3 V

AVDD3V = 3.4 V

AVDD3V = 3.5 V

AVDD3V = 3.6 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.95 V

DVDD = 2 V

71.7

71.2

70.7

70.2

69.7

69.2

83

82

81

80

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D027

D028

F_IN= 370 MHz, A_IN= – 3 dBFS

F_IN= 190 MHz, A_IN= – 1 dBFS

Figure 28. Spurious-Free Dynamic Range vs DVDD Supply

and Temperature

Figure 29. Signal-to-Noise Ratio vs AVDD3V Supply and

Temperature

92

73

AVDD3V = 2.85 V

AVDD3V = 3 V

AVDD3V = 3.1 V

AVDD3V = 3.2 V

AVDD3V = 3.3 V

AVDD3V = 3.4 V

AVDD3V = 3.5 V

AVDD3V = 3.6 V

AVDD3V = 2.85 V

AVDD3V = 3 V

AVDD3V = 3.1 V

AVDD3V = 3.2 V

AVDD3V = 3.3 V

AVDD3V = 3.4 V

AVDD3V = 3.5 V

AVDD3V = 3.6 V

91

90

89

88

87

86

72

71

70

69

68

67

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D029

D030

F_IN= 190 MHz, A_IN= – 1 dBFS

F_IN= 370 MHz, A_IN= – 3 dBFS

Figure 30. Spurious-Free Dynamic Range vs AVDD3V

Supply and Temperature

Figure 31. Signal-to-Noise Ratio vs AVDD3V Supply and

Temperature

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Typical Characteristics: 14-Bit Burst Mode (continued)

Typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC Sampling Frequency = 500

Msps, 14-bit Resolution, No Decimation Filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15

V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.

74

72

70

68

66

64

150

125

100

75

84

83

82

81

80

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

AVDD3V = 2.85 V

AVDD3V = 3 V

AVDD3V = 3.1 V

AVDD3V = 3.2 V

AVDD3V = 3.3 V

AVDD3V = 3.4 V

AVDD3V = 3.5 V

AVDD3V = 3.6 V

50

25

-40

-15

10

35

60

85

-70

-60

-50

-40

-30

-20

-10

0

Temperature (°C)

Amplitude (dBFS)

D031

D032

F_IN= 370 MHz, A_IN= – 3 dBFS

F_IN= 190 MHz

Figure 32. Spurious-Free Dynamic Range vs AVDD3V

Supply and Temperature

Figure 33. Performance vs Amplitude

75

73

71

69

67

65

110

74

180

150

120

90

SNR

SFDR

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

72.5

71

100

90

69.5

68

80

60

70

66.5

30

65

0

60

-70

-60

-50

-40

-30

-20

-10

0

0.2

0.6

1

1.4

1.8

2.2

Amplitude (dBFS)

Differential Clock Amplitude (Vpp)

D033

D034

F_IN= 370 MHz

F_IN= 190 MHz, A_IN= – 1 dBFS

Figure 34. Performance vs Amplitude

Figure 35. Performance vs Clock Amplitude

75

72

69

66

63

60

125

100

75

50

25

0

73

95

SNR

SFDR

SNR

SFDR

72

71

70

69

68

90

85

80

75

70

0.2

0.6

1

1.4

1.8

2.2

30

35

40

45

50

55

60

65

70

Differential Clock Amplitude (Vpp)

Input Clock Duty Cycle (%)

D035

D036

F_IN= 370 MHz, A_IN= – 3 dBFS

Figure 36. Performance vs Clock Amplitude

F_IN= 190 MHz, A_IN= – 1 dBFS

Figure 37. Performance vs Clock Duty Cycle

17

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Typical Characteristics: 14-Bit Burst Mode (continued)

Typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC Sampling Frequency = 500

Msps, 14-bit Resolution, No Decimation Filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15

V, –1-dBFS differential input for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.

0

72

71

70

69

68

67

66

65

90

87

84

81

78

75

72

69

SNR

SFDR

-20

-40

-60

-80

-100

-120

30

35

40

45

50

55

60

65

70

0

50

100

150

200

250

Input Clock Duty Cycle (%)

Input Frequency (MHz)

D037

D038

F_IN= 370 MHz, A_IN= – 3 dBFS

F_IN= 190 MHz , A_IN= –1 dBFS

SFDR = 49 dBc, f_PSRR= 5 MHz, A_PSRR= 50 mVPP

Figure 39. Power-Supply Rejection Ratio FFT for test signal

on AVDD Supply

Figure 38. Performance vs Clock Duty Cycle

-10

-15

-20

-25

-30

-35

-40

-45

-50

-55

0

PSRR with 50-mVPP Signal on AVDD

PSRR with 50-mVPP Signal on AVDD3V

-20

-40

-60

-80

-100

-120

0

50

100

150

200

250

300

0

50

100

150

200

250

Frequency of Signal on Supply (MHz)

Input Frequency (MHz)

D039

D040

F_IN= 190 MHz, A_IN= – 1 dBFS

F_IN= 190 MHz , A_IN= – 1 dBFS

SFDR = 81 , f_CMRR= 5 MHz, A_CMRR= 50 mVPP

Figure 41. Common-Mode Rejection Ratio FFT

Figure 40. Power-Supply Rejection Ratio vs Supplies

4

3.2

2.4

1.6

0.8

0

-20

AVDD_Power (W)

DVDD_Power (W)

AVDD3V_Power (W)

IOVDD_Power (W)

TotalPower (W)

-25

-30

-35

-40

-45

-50

-55

-60

0

50

100

150

200

250

300

250

300

350

400

450

500

Frequency of Input Common-Mode Signal (MHz)

Sampling Speed (MSPS)

D041

D042

F_IN= 190 MHz, A_IN= – 1dBFS

50-mVPP test-Signal on input common mode

Figure 42. Common-Mode Rejection Ratio

Figure 43. Power vs Chip Clock

18

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6.10 Typical Characteristics: Mode 2

Low pass or high pass decimation-by-2 filter selected as per input frequency. Typical values are at T_A= 25°C, full

temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC Sampling Frequency = 500 Msps, 14-bit Resolution, No

Decimation Filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input

for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.

0

-20

0

-20

-40

-60

-80

-100

-120

-100

-120

0

25

50

75

100

125

0

25

50

75

100

125

Input Frequency (MHz)

D043

D044

F_IN= 100 MHz , A_IN= – 1 dBFS

F_IN= 150 MHz , A_IN= – 1 dBFS

SNR = 74.1 dBFS, SFDR = 98 dBc, SFDR = 100 dBc (Non23)

SNR = 73.8 dBFS, SFDR = 99 dBc, SFDR = 99 dBc (Non23)

Figure 44. FFT for 100-MHz Input Signal

Figure 45. FFT for 150-MHz Input Signal

0

-20

-40

-20

-40

-60

-80

-100

-120

-100

-120

0

25

50

75

100

125

0

25

50

75

100

125

Input Frequency (MHz)

D045

F_IN= 185 MHz , A_IN= – 1 dBFS

F_IN= 230 MHz , A_IN= – 1 dBFS

SNR = 73.2 dBFS, SFDR = 98 dBc, SFDR = 98 dBc (Non23)

SNR = 72.4 dBFS, SFDR = 91 dBc, SFDR = 98 dBc (Non23)

Figure 46. FFT for 185-MHz Input Signal

Figure 47. FFT for 230-MHz Input Signal

19

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ZHCSDU3A –JUNE 2015–REVISED JUNE 2015

www.ti.com.cn

6.11 Typical Characteristics: Mode 0

Low-pass decimation-by-2 filter selected, Complex FFT plotted,mixer frequency 125 MHz. Typical values are at T_A= 25°C,

full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC Sampling Frequency = 500 Msps, 14-bit Resolution, No

Decimation Filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input

for IF ≤ 250 MHz, and –3-dBFS differential input for IF > 250 MHz, unless otherwise noted.

0

-20

0

-20

-40

-60

-80

-100

-120

-125

-75

-25

25

75

125

-125

-75

-25

25

75

125

Input Frequency (MHz)

D047

D048

F_IN= 270 MHz , A_IN= – 3 dBFS

F_IN= 370 MHz , A_IN= – 3 dBFS

SNR = 69.5 dBFS, SFDR = 83 dBc, SFDR = 87 dBc (Non23)

SNR = 68.1 dBFS, SFDR = 82 dBc, SFDR = 82 dBc (Non23)

Figure 48. FFT for 270-MHz Input Signal

Figure 49. FFT for 370-MHz Input Signal

0

-20

-40

-60

-80

-100

-120

-125

-75

-25

25

75

125

Input Frequency (MHz)

D049

F_IN= 470 MHz , A_IN= – 3 dBFS

SNR = 66.3 dBFS, SFDR = 75 dBc, SFDR = 75 dBc (Non23)

Figure 50. FFT for 470-MHz Input Signal

20

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7 Detailed Description

7.1 Overview

The ADS58J63 is a low power, wide bandwidth 14-bit 500 MSPS quad channel telecom receiver IC. It supports

the JESD204B serial interface with data rates up to 10 Gbps supporting 1 lane per channel. The buffered analog

input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch

energy. The ADS58J63 provides excellent spurious-free dynamic range (SFDR) over a large input frequency

range with very low power consumption. Its digital block includes a 2x and 4x decimation low pass filter with FS/4

and k×FS/16 mixers to support a receive bandwidth up to 200 MHz and a output burst mode for use as DPD

observation receiver.

The JESD204B interface reduces the number of interface lines allowing high system integration density. An

internal phase locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock which is used

to serialize the 14bit data from each channel.

7.2 Functional Block Diagram

Digital Block

Interleaving

Correction

2x

14bit

ADC

INAP/M

INBP/M

DAP/M

C{ꢀ4

4x

2x

JESD204B

Digital Block

Interleaving

Correction

Y*C{ꢀ16

14bit

ADC

C{ꢀ8

DBP/M

Burst Mode

TRIGAB

TRIGCD

TRDYAB

TRDYCD

SYSREFP/M

CLKINP/M

PLL

x10/x20

SYNCbAB

SYNCbCD

Burst Mode

Digital Block

Interleaving

Correction

14bit

ADC

INCP/M

INDP/M

DCP/M

DDP/M

2x

C{ꢀ4

JESD204B

4x

2x

Digital Block

Interleaving

Correction

14bit

ADC

Y*C{ꢀ16

C{ꢀ8

Configuration

Registers

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7.3 Feature Description

7.3.1 Analog Inputs

The ADS58J63 analog signal inputs are designed to be driven differentially. The analog input pins have internal

analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high

impedance input across a very wide frequency range to the external driving source which enables great flexibility

in the external analog filter design as well as excellent 50 Ω matching for RF applications. The buffer also helps

to isolate the external driving circuit from the internal switching currents of the sampling circuit which results in a

more constant SFDR performance across input frequencies.

The common-mode voltage of the signal inputs is internally biased to 1.9 V using 600-Ω resistors which allows

for AC coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM +

0.475 V) and (VCM – 0.475 V), resulting in a 1.9-Vpp (default) differential input swing. The input sampling circuit

has a 3-dB bandwidth that extends up to 900 MHz.

7.3.2 Recommended Input Circuitry

In order to achieve optimum AC performance the following circuitry is recommended at the analog inputs.

Ç1

Ç2

0.1uC

10 Ω

Lbxt

0.1uC

25 Ω

0.1uC

win

/in

3.3 pF

25 Ω

Lbxa

1:1

10 Ω

1:1

0.1uC

5evice

Figure 51. Analog Input Driving Circuit

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7.4 Device Functional Modes

7.4.1 Digital Features

The ADS58J63 supports decimation by 2 and 4 and burst mode output. The 4 channels can be configured as

pairs (A and B and C and D) to either burst or decimation mode (must be same decimation mode for all 4

channels).

Table 1. Overview of Operating Modes

MAX

OUTPUT

RATE

OPERATING

MODE

DIGITAL

MIXER

BANDWIDTH BANDWIDTH

OUTPUT

FORMAT

DESCRIPTION

DECIMATION

AT 491Msps

AT 368Msps

0

2

4

5

6

7

8

±FS/4

–

2

4

2

–

200 MHz

100 MHz

200 MHz

100 MHz

245.76 MHz

150 MHz

75 MHz

Complex

Real

250 Msps

125 Msps

500 Msps

N×Fs/16

–

75 MHz

Real

Decimation

Burst Mode

150 MHz

75 MHz

Complex

Real

75 MHz

184.32 MHz

Real

Figure 52 shows signal processing in Digital Down-Conversion (DDC) Block in ADS58J63.

L dꢀtꢀ

Filter

N

weꢀl dꢀtꢀ

0

2

4

5

6

7

8

L[

9

n

g

i

cos(2‹nf_mix2/f_{)

sin(2‹nf_mix2/f_{)

cos(2‹nf_mix1/f_{)

ꢃ00a{ꢄ{

dꢀtꢀ, x(n)

ꢁI x

2

Üpscꢀled

Ço W9{5

9ncoder

n

e

ùero-

pꢀdded

dꢀtꢀ

sin(2‹nf_mix1/f_{)

N

Filter

v dꢀtꢀ

14-bit

Burst Mode

14/ꢂ-bit .urst aode dꢀtꢀ

aode

{election

Figure 52. Digital Down-Conversion (DDC) Block

Table 2 shows characteristics of different blocks of DDC signal processing blocks active in different modes.

Table 2. Features of DDC Block in Different Modes

Mode

fmix1

f_S/4

Filter and Decimation

fmix 2

not used

f_S/8

Output

0

2

4

5

6

LPF cut off freq at f_S/4, decimation by 2

LPF or HPF cut off at f_S/4, decimation by 2

LPF cutoff at f_S/8, decimation by 2

LPF cutoff at f_S/8, decimation by 4

I, Q data at 250 MSPS each is given out

Straight 250 MSPS data is given out

Real data at 250 MSPS is given out

I, Q data at 250 MSPS each is given out

I, Q data at 125 MSPS each is given out

not used

k f_S/16

not used

Real data is up-scaled, zero-padded and given out

at 500 MSPS

7

8

k f_S/16

LPF cutoff at f_S8, decimation by 2

not used

f_S/8

not used

Straight 500 MSPS Burst mode data is given out

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7.4.2 Mode 0 – Decimation by 2 with IQ Outputs for up to 220 MHz of IQ Bandwidth

In this configuration, the DDC block includes a fixed frequency ±Fs/4 complex digital mixer preceding the digital

filter – so the IQ passband is ± ~110 MHz (3 dB) centered at Fs/4. Mixing with +FS/4 inverts the spectrum. The

stop band attenuation is approximately 90 dB and the passband flatness is ±0.1 dB. Figure 53 shows mixing

operation in DDC Mode 0.

± Fs/4

500 Msps

IQ: 500 Msps

14-bit

ADC

IQ: 250 Msps

2x

FS/4

FS/2

FS/4

Figure 53. Mixing in Mode 0

Table 3. Filter Specification Details – Mode 0

CORNERS

LOW PASS

0.204 × Fs

0.211 × Fs

0.216 × Fs

0.226 × Fs

–0.1 dB

–0.5 dB

–1 dB

–3 dB

20

0

0.5

0

-20

-40

-60

-80

-100

-120

-0.5

-1

-1.5

-2

-2.5

-3

0

0.1

0.2

0.3

0.4

0.5

0

0.05

0.1

0.15

0.2

0.25

Frequency Response

D052

D053

Figure 54. Frequency Response of Filter in Mode 0

Figure 55. Zoomed view of Frequency Response

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7.4.3 Mode 2 – Decimation by 2 for up to 110 MHz of Real Bandwidth

In this configuration, the DDC block only includes a 2x decimation filter (high pass or low pass) with real outputs.

The passband is ~110 MHz (3 dB). Figure 56 shows filtering operation in DDC Mode 2.

500 Msps

14-bit

250 Msps

2x

ADC

FS/4

FS/2

FS/4

Figure 56. Filtering in Mode 2

Table 4. Filter Specification Details – Mode 2

CORNERS

–0.1 dB

–0.5 dB

–1 dB

LOW PASS

0.204 × Fs

0.211 × Fs

0.216 × Fs

0.226 × Fs

HIGH PASS

0.296 × Fs

0.290 × Fs

0.284 × Fs

0.274 × Fs

–3 dB

20

0

0.5

0

-20

-40

-60

-80

-100

-120

-0.5

-1

-1.5

-2

-2.5

-3

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Frequency Response

0

0.05

0.1

0.15

0.2

0.25

Frequency Response

D056

D057

Figure 57. Frequency Response for Decimate-by-2 Low

Pass and High Pass Filter (in Mode 2)

Figure 58. Zoomed View of Frequency Response

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7.4.4 Mode 4/7 – Decimation by 2 with Real Outputs for up to 110 MHz of Bandwidth

In this configuration, the DDC block includes a selectable N×Fs/16 complex digital mixer (N from –8 to +7)

preceding the decimation by 2 digital filter also with an IQ passband of ± ~55 MHz (3 dB) centered at N×Fs/16. A

positive value for N inverts the spectrum. In addition a Fs/8 complex digital mixer is added after the decimation

filter transforming the output back to real format while centering the output spectrum within the Nyquist zone.

In addition the ADS58J63 supports a 0-pad feature where a sample with value = 0 gets added after each

sample. In that way the output data rate gets interpolated to 500 Msps (real) with a 2^ndimage inverted at Fs/2-

Fin.

The stop band attenuation is approximately 90 dB for in-band aliases from negative frequencies and ~55 dB for

out of band aliases. The passband flatness is ±0.1 dB.

FS/8

2^ndImage

N*Fs/16

Fs/8

Real: 500 Msps

Real: 250 Msps

0 Pad

500 Msps

IQ: 500 Msps

IQ: 250 Msps

14-bit

ADC

2x

FS/4

FS/2

Example:

N= -4

FS/8

FS/4

FS/2

0

FS/8

FS/4

Figure 59. Mixing and Filtering in Mode 4/7

Table 5. Filter Specification Details – Mode 4/7

CORNERS

–0.1 dB

–0.5 dB

–1 dB

LOW PASS

0.102 × Fs

0.105 × Fs

0.108 × Fs

0.113 × Fs

–3 dB

0.5

0

20

0

-0.5

-1

-20

-40

-60

-80

-100

-120

-1.5

-2

-2.5

-3

0

0.05

0.1

0.15

0.2

0.25

0

0.05

0.1

0.15

0.2

0.25

Frequency Response

D050

D051

Figure 60. Frequency Response for Decimate-by-2 Low-

Pass Filter (in Mode 4 and Mode 7)

Figure 61. Zoomed View of Frequency Response

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7.4.5 Mode 5 – Decimation by 2 with IQ Outputs for up to 110 MHz of IQ Bandwidth

In this configuration, the DDC block includes a selectable N×Fs/16 complex digital mixer (N from –8 to +7)

preceding the decimation by 2 digital filter – so the IQ passband is ± ~55 MHz (3 dB) centered at N×Fs/16. A

positive value for N inverts the spectrum.

The stop band attenuation is approximately 90 dB for in-band aliases from negative frequencies. The passband

flatness is ±0.1 dB.

N*Fs/16

500 Msps

IQ: 500 Msps

14-bit

ADC

IQ: 250 Msps

2x

Example:

N= -4

FS/4

FS/2

FS/8

FS/4

Figure 62. Mixing and Filtering in Mode 5

Table 6. Filter Specification Details – Mode 5

CORNERS

LOW PASS

0.102 × Fs

0.105 × Fs

0.108 × Fs

0.113 × Fs

–0.1 dB

–0.5 dB

–1 dB

–3 dB

0.5

0

20

0

-0.5

-1

-20

-40

-60

-80

-100

-120

-1.5

-2

-2.5

-3

0

0.05

0.1

0.15

0.2

0.25

0

0.05

0.1

0.15

0.2

0.25

Frequency Response

D050

D051

Figure 63. Frequency Response for Decimate-by-2 Low-

Pass Filter (in Mode 5)

Figure 64. Zoomed View of Frequency Response

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7.4.6 Mode 6 – Decimation by 4 with IQ Outputs for up to 110 MHz of IQ Bandwidth

In this configuration, the DDC block includes a selectable n×Fs/16 complex digital mixer (n from –8 to +7)

preceding the decimation by 4 digital filter – so the IQ passband is ± ~55 MHz (3 dB) centered at n×Fs/16. A

positive value for N inverts the spectrum. The decimaiton by 4 filter is a cascade of two decimation by 2 filters

with frequency response shown in Figure 66.

The stop band attenuation is approximately 90 dB for in-band aliases from negative frequencies and ~55 dB for

out of band aliases. The passband flatness is ±0.1 dB.

N*Fs/16

500 Msps

IQ: 500 Msps

14-bit

ADC

IQ: 250 Msps

IQ: 125 Msps

2x

Example:

N= -6

3FS/8

FS/4

FS/2

FS/8

FS/4

Figure 65. Mixing and Filtering in Mode 6

Table 7. Filter Specification Details – Mode 6

CORNERS

–0.1 dB

–0.5 dB

–1 dB

LOW PASS

0.102 × Fs

0.105 × Fs

0.108 × Fs

0.113 × Fs

–3 dB

0.5

0

20

0

-0.5

-1

-20

-40

-60

-80

-100

-120

-1.5

-2

-2.5

-3

0

0.05

0.1

0.15

0.2

0.25

0

0.05

0.1

0.15

0.2

0.25

Frequency Response

D050

D051

Figure 66. Frequency Response for Decimate-by-2 Low-

Pass Filter (in Mode 6)

Figure 67. Zoomed View of Frequency Response

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7.4.7 Mode 8 – Burst Mode

In burst mode the output data is alternated between low resolution (L, 9-bit) and high resolution (H, 14-bit)

output. The burst mode can be configured via SPI register writes independently for channel A/B and channel

C/D.

The high resolution output is 14 bit and the number (#) of high and low resolution samples is set with two user

programmable counters – one for high resolution (HC) and one for low resolution (LC). There is one counter pair

(HC, LC) for channel A/B and one pair for channel C/D. The internal logic checks if the maximum duty cycle is

exceeded and if necessary resets the counters to its default values.

Each output cycle starts with a low resolution and the counter values can be reconfigured for the next cycle

during prior to the start of the next cycle.

Enable

Burst Mode

New cycle

starts again

L times out

DA

DB

DC

DD

L

H

L

H

Update Counter Values

HRES

14-bit high resolution

9-bit low resolution

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

OVR HR

13 12 11 10

16-bit data going into 8b/10b encoder

Figure 68. Timing Diagram for 14-bit Burst Mode (DDC Mode 8)

The counter values for high and low resolution can be programmed to:

High resolution counter (HC): 1 to 2²⁵

Low resolution counter (LC); 1 to 2²⁸

The output duty cycle limit is illustrated in Table 8.

Table 8. Output Duty Cycle Limit

MAXIMUM ALLOWED DUTY CYCLE

(high : low resolution output)

DEFAULT VALUE

HC

DEFAULT VALUE

LC

HIGH RESOLUTION

OUTPUT

LOW RESOLUTION

OUTPUT

14 bit

9 bit

1/3

1

3

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7.4.8 Trigger Input

The burst mode can be operated in auto trigger or manual trigger mode. In manual trigger mode the TRIGGER

input (TRIGAB, TRIGCD) is used to release the high resolution data (HC) burst after the low resolution data

counter LC has timed out. In auto trigger mode the high resolution data is released immediately after completion

of the last low resolution sample.

Using SPI control the ADS58J63 can be configured to use TRIGAB or TRIGCD as the manual trigger input.

7.4.9 Manual Trigger Mode

Upon enabling manual trigger mode, the ADS58J63 starts transmission of low resolution data. As soon as the LC

counter is finished, the manual trigger is unlocked, the trigger ready flag (TRDY) is raised and the high resolution

output H can be triggered. Once the low resolution counter LC is finished, the next high resolution output or burst

mode sequence can be triggered again. The HRES flag is embedded in the JESD204B output data stream. The

counter values can be updated until a new burst mode cycles starts with transmission of low resolution samples.

Example of burst mode with manual trigger:

Enable

Burst Mode

LC times out

Ready for trigger

Trigger Event

New cycle

starts again

DA

DB

DC

DD

L

H

L

H

Update Counter Values

TRDYAB/CD

TRIGAB/CD

HRES

14 bit high resolution

9 bit low resolution

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

OVR HR

13 12 11 10

16 bit data going into 8b/10b encoder

Figure 69. Timing Diagram for Manual Trigger Mode

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7.4.10 Auto Trigger Mode

Upon enabling auto trigger mode, the ADS58J63 starts transmission of low resolution data. As soon as the low

resolution samples counter (LC) is finished, the ADS58J63 immediately begins transmitting the high resolution

output H. The HRES flag can also be embedded in the JESD204B output data stream. The counter values can

be updated until a new burst mode cycles starts with transmission of low resolution samples. Any input on the

trigger input pins is ignored.

Example of burst mode with automatic trigger:

Enable

Burst Mode

New cycle

starts again

LC times out

DA

DB

DC

DD

L

H

L

H

Update Counter Values

HRES

14-bit high resolution

9-bit low resolution

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

OVR HR

13 12 11 10

16-bit data going into 8b/10b encoder

Figure 70. Timing Diagram for Auto Trigger Mode

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7.4.11 Over-range Indication

The ADS58J63 provides a fast over-range indication (FOVR) which can be presented in the digital output data

stream via SPI configuration. When the FOVR indication is embedded in the output data stream, it replaces the

LSB (normal 0) of the 16 bit going to the 8b/10b encoder.

One threshold is set per channel pair A/B and C/D.

14-bit data output

0/

OVR

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

16-bit data going into 8b/10b encoder

Figure 71. Timing Diagram for FOVR

The fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and it gets

presented after just 44 input clock cycles enabling a quicker reaction to an overrange event.

The input voltage level at which the overload is detected is referred to as the threshold. It is programmable using

the FOVR THRESHOLD bits.

The input voltage level at which fast OVR is triggered is:

Full-scale × [the decimal value of the FOVR Threshold bits] / 255)

The default threshold is E3h (227) which corresponds to a threshold of –1 dBFS.

In terms of full scale input, the fast OVR threshold can be calculated as shown in Equation 1:

20 × log (<FOVR Threshold>/255).

(1)

Following is an example register write to set the FOVR threshold for all 4 channels:

Table 9. Register Sequence for FOVR Configuration

ADDRESS

11h

DATA

80h

20h

FFh

68h

00h

01h

03h

01h

00h

COMMENT

Go to Master page

59h

Enable FOVR

11h

Go to ADC page

5Fh

Set FOVR threshold for chCD to 255

4004h

4003h

60ABh

60ADh

6000h

Go to main digital page

Enable bit D0 overwrite

Select FOVR to replace bit D0

Issue and clear digital reset

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7.4.12 Power-Down Mode

The ADS58J63 provides a highly-configurable power-down mode. Power-down can be enabled using the PDN

pin or SPI register writes.

A power-down mask can be configured, which allows a trade-off between wake-up time and power consumption

in power-down mode. Two independent power-down masks can be configured: MASK 1 and MASK 2 as shown

in Table 10. See the master page registers in Table 15 for further details.

Table 10. Register Address for Power-Down Modes

REGISTER

ADDRESS

REGISTER DATA

COMMENT

A[7:0] (Hex)

MASTER PAGE (80h)

20

7

6

5

4

3

2

1

0

PDN ADC CHAB

PDN ADC CHCD

MASK 1

21

23

24

PDN BUFFER CHCD

PDN BUFFER CHAB

0

PDN ADC CHAB

PDN ADC CHCD

MASK 2

CONFIG

PDN BUFFER CHCD

PDN BUFFER CHAB

0

GLOBAL

PDN

OVERRIDE

PDN PIN

PDN MASK

26

0

SEL

MASK

SYSREF

53

55

0

PDN MASK

To save power, the device can be put in complete power down by using the GLOBAL PDN register bit. However,

when JESD link must remain up while putting the device in power down, the ADC and analog buffer can be

powered down by using the PDN ADC CHx and PDN BUFFER CHx register bits after enabling the PDN MASK

register bit. The PDN MASK SEL register bit can be used to select between MASK 1 or MASK 2. Table 11

shows power consumption for different combinations of the GLOBAL PDN, PDN ADC CHx, and PDN BUFF CHx

register bits.

Table 11. Power Consumption in Different Power-Down Settings

TOTAL

IAVDD3V

(mA)

IAVDD

(mA)

IDVDD

(mA)

IIOVDD

(mA)

POWER

(W)

REGISTER BIT

Default

COMMENT

After reset, with a full-scale input signal to

both channels

0.340

0.002

0.365

0.006

0.184

0.012

0.533

0.181

2.675

0.247

The device is in complete power-down

state

GBL PDN = 1

GBL PDN = 0,

PDN ADC CHx = 1

(x = AB or CD)

The ADCs of one pair of channels are

powered down

0.277

0.266

0.225

0.361

0.123

0.187

0.496

0.527

2.063

2.445

GBL PDN = 0,

PDN BUFF CHx = 1

(x = AB or CD)

The input buffers of one pair of channels

iarepowered down

GBL PDN = 0,

PDN ADC CHx = 1,

PDN BUFF CHx = 1

(x = AB or CD)

The ADCs and input buffers of one pair of

channels are powered down

0.200

0.060

0.224

0.080

0.126

0.060

0.492

0.448

1.830

0.960

GBL PDN = 0,

PDN ADC CHx = 1,

PDN BUFF CHx = 1

(x = AB and CD)

The ADCs and input buffers of all channels

are powered down

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7.5 Programming

7.5.1 Device Configuration

The ADS58J63 can be configured using a serial programming interface, as described below. In addition, the

device has one dedicated parallel pin (PDN) for controlling the power down modes. The ADS58J63 supports a

24-bit (16-bit address, 8-bit data) SPI operation and uses paging (see detailed register map info) to access all

register bits.

7.5.1.1 Details of Serial Interface

The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial

interface enable), SCLK (serial interface clock) and SDIN (serial interface data) pins. Serial shift of bits into the

device is enabled when SEN is low. Serial data on SDIN are latched at every SCLK rising edge when SEN is

active (low). The interface can work with SCLK frequencies from 5 MHz down to very low speeds (of a few hertz)

and also with non-50% SCLK duty cycle.

Register Address[11:0]

Register Data[7:0]

SDIN

R/W

M

P

CH

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

t_DH

D0

t_SCLK

t_DSU

SCLK

SEN

t_SLOADS

t_SLOADH

RESET

Figure 72. Serial Interface Timing Diagram

Table 12. Programing Details of Serial Interface

SPI BITS

DESCRIPTION

OPTIONS

0 = SPI write

1 = SPI read back

R/W

Read/write bit

0 = Analog SPI bank (Master and ADC page)

1 = JDigital SPI bank (Main Digital, Analog JESD, and

Digital JESD pages)

M

SPI bank access

JESD page selection bit

0 = Page access

1 = Register access

P

0 = Channel AB

1 = Channel CD

By default, both channels are being addressed.

SPI access for a specific channel of the digital SPI

bank

CH

ADDR [11:0]

DATA [7:0]

SPI address bits

SPI data bits

—

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7.5.1.2 Serial Register Write: Analog Bank

The analog SPI bank contains of two pages (the master and ADC page). The internal register of the ADS58J63

analog SPI bank can be programmed by:

1. Drive the SEN pin low.

2. Initiate a serial interface cycle specifying the page address of the register whose content must be written.

–

Master page: write address 0011h with 80h.

ADC page: write address 0011h with 0Fh.

3. Write the register content as shown in Figure 73. When a page is selected, multiple writes into the same

page can be done.

Register Address[11:0]

Register Data[7:0]

0

SDIN

SCLK

R/W

M

P

CH A11 A10

A9

A8

A7 A6 A5 A4

A3

A2

A1

A0

D7

D6

D5 D4 D3 D2

D1

D0

SEN

RESET

Figure 73. Serial Register Write Timing Diagram

7.5.1.3 Serial Register Readout: Analog Bank

The content from one of the two analog banks can be read out by:

1. Drive the SEN pin low.

2. Select the page address of the register whose content must be read.

–

Master page: write address 0011h with 80h.

ADC page: write address 0011h with 0Fh.

3. Set the R/W bit to 1 and write the address to be read back.

4. Read back the register content on the SDOUT pin, as shown in Figure 74. When a page is selected, multiple

read backs from the same page can be done.

Register Address[11:0]

Register Data[7:0] = XX

1

0

SDIN

SCLK

R/W

M

P

CH

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SEN

RESET

SDOUT

D7

D6

D5

D4

D3

D2

D1

D0

SDOUT[7:0]

Figure 74. Serial Register Read Timing Diagram

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7.5.1.4 JESD Bank SPI Page Selection

The JESD SPI bank contains four pages (main digital, interleaving engine, digital, and analog JESD pages). The

individual pages can be selected by:

1. Drive the SEN pin low.

2. Set the M bit to 1 and specify the page with two register writes. Note that the P bit must be set to 0, as

shown in Figure 75.

–

Write address 4003h with 00h (LSB byte of page address).

Write address 4004h with the MSB byte of the page address.

–

For Main digital page: write address 4004h with 68h.

For Digital JESD page: write address 4004h with 69h.

For Analog JESD page: write address 4004h with 6Ah.

For Interleaving engine page: write address 4004h with 61h.

Register Address[11:0]

Register Data[7:0]

D5 D4 D3 D2

0

1

0

SDIN

R/W

M

P

CH A11 A10 A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D1

D0

SCLK

SEN

RESET

Figure 75. SPI Page Selection

7.5.1.5 Serial Register Write: Analog Bank

The analog SPI bank contains two pages (Master and ADC page). The internal register of the ADS58J63 analog

SPI bank can be programmed following these steps:

1. Drive the SEN pin low.

2. Initiate a serial interface cycle specifying the page address of the register whose content has to be written

–

Master page: write address 11h with 80h

ADC page: write address 11h with 0Fh

3. Write register content. Once a page is selected, multiple writes into the same page can be done.

Register Address[11:0]

Register Data[7:0]

0

1

0

SDIN

SCLK

R/W

M

P

CH A11 A10

A9

A8

A7 A6 A5 A4

A3

A2

A1

A0

D7

D6

D5 D4 D3 D2

D1

D0

SEN

RESET

Figure 76. Serial Register Write Timing Diagram

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7.5.1.6 Serial Register Readout: Analog Bank

SPI read out of content in one of the two analog banks can be accomplished with the following steps:

1. Drive the SEN pin low.

2. Select the page address of the register which content has to be read.

–

Master page: write Address = 11h with 80h

ADC page: write Address 11h with 0Fh.

3. Set the R/W bit to '1' and write the address to be read back.

4. Read back register content on the SDOUT pin. Once a page is selected, multiple read backs from the same

page can be done.

Register Address[11:0]

Register Data[7:0] = XX

1

0

SDIN

SCLK

R/W

M

P

CH A11 A10 A9

A8

A7 A6 A5 A4

A3

A2

A1

A0

D7

D6

D5 D4 D3 D2

D1

D0

SEN

RESET

SDOUT

D7

D6

D5

D4

D3

D2

D1

D0

SDOUT[7:0]

Figure 77. Serial Register Read Timing Diagram

7.5.1.7 Digital Bank SPI Page Selection

The Digital SPI bank contains five pages (Main digital, Interleaving Engine, Decimation filter, JESD digital, and

JESD analog). The individual pages can be selected following these steps:

1. Drive the SEN pin low.

2. Set the M bit to ‘1’ and specify the page with two register writes (Note: P bit set to 0)

–

Write address 4003h with 00h (LSB byte of page address)

Write address 4004h MSB byte of page address

spacer

–

Main digital page: write Address = 4004h with 68h (default)

Digital JESD page: write Address = 4004h with 69h

Analog JESD page: write Address = 4004h with 6Ah

Interleaving Engine page: write Address = 4004h with 61h

Decimation Filter page: write Address = 4004h with 61h and 4003h with 41h

Register Address <11:0>

Register Data <7:0>

D5 D4 D3 D2

0

1

0

SDIN

SCLK

R/W

M

P

CH A11 A10 A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D1

D0

SEN

RESET

Figure 78. SPI Timing Diagram for Digital Bank Page Selection

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7.5.1.8 Serial Register Write – Digital Bank

The ADS58J63 is a quad channel device and the JESD204B portion is configured individually for 2 channel (A/B

and C/D) using the CH bit. Note the P bit needs to be set to 1 for register writes.

1. Drive the SEN pin low.

2. Select the digital bank page (Note: M bit = 1, P bit = 0)

–

Write address 4003h with 00h

Main digital page: write Address = 4004h with 68h (default)

Digital JESD page: write Address = 4004h with 69h

Analog JESD page: write Address = 4004h with 6Ah

Interleaving Engine page: write Address = 4004h with 61h

Decimation Filter page: write Address = 4004h with 61h and 4003h with 41h

3. Set M and P bit to 1 and select ChAB (CH=0) or ChCD (CH=1) and write register content. Once a page is

selected, multiple writes into the same page can be done.

By default, register writes are applied to both channel pairs (broadcast mode). To disable broadcast mode

and enable individual channel writes, write address 4005h with 01h (default is 00h).

Register Address <11:0>

Register Data <7:0>

0

1

0

SDIN

SCLK

R/W

M

P

CH A11 A10 A9

A8

A7 A6 A5 A4

A3

A2

A1

A0

D7

D6

D5 D4 D3 D2

D1

D0

SEN

RESET

Figure 79. Serial Register Write Timing Diagram

7.5.1.9 Individual Channel Programming

By default, register writes are applied to both channels. To enable individual channel writes, write address 4005h

with 01h (default is 00h).

7.5.1.10 Serial Register Readout – Digital Bank

SPI read out of content in one of the three digital banks can be accomplished with the following steps:

1. Drive the SEN pin low.

2. Select the digital bank page (Note: M bit = 1, P bit = 0)

–

Write address 4003h with 00h

Main digital page: write Address = 4004h with 68h

Digital JESD page: write Address = 4004h with 69h

Analog JESD page: write Address = 4004h with 6Ah

Interleaving Engine page: write Address = 4004h with 61h

Decimation Filter page: write Address = 4004h with 61h and 4003h with 41h

3. Set the R/W bit, M and P bit to '1' and select ChAB) or ChCD and write the address to be read back.

4. Read back register content on the SDOUT pin. Once a page is selected, multiple read backs from the same

page can be done.

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Register Address <11:0>

A7 A6 A5 A4

Register Data <7:0> = XX

1

0

SDIN

SCLK

R/W

M

P

CH A11 A10 A9

A8

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SEN

RESET

SDOUT

D7

D6

D5

D4

D3

D2

D1

D0

SDOUT <7:0>

Figure 80. Serial Register Read Timing Diagram

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7.5.2 JESD204B Interface

The ADS58J63 supports device subclass 1 with a maximum output data rate of 10 Gbps for each serial

transmitter.

An external SYSREF signal is used to align all internal clock phases and the local multi frame clock to a specific

sampling clock edge. This allows synchronization of multiple devices in a system and minimizes timing and

alignment uncertainty. The ADS58J63 supports single (for all 4 JESD links) or dual (for channel A/B and C/D)

SYNCb inputs and can be configured via SPI.

JESD204B Block

Transport Layer

Link Layer

Frame Data

Mapping

8b/10b

encoding

Scrambler

1+x¹⁴+x¹⁵

DX

Comma characters

Initial lane alignment

Test Patterns

SYNCb

Figure 81. JESD Interface Block Diagram

Depending on the ADC sampling rate, the JESD204B output interface can be operated with 1 lane per channel.

The JESD204B setup and configuration of the frame assembly parameters is handled via SPI interface.

The JESD204B transmitter block consists of the transport layer, the data scrambler and the link layer. The

transport layer maps the ADC output data into the selected JESD204B frame data format and manages if the

ADC output data or test patterns are being transmitted. The link layer performs the 8b/10b data encoding as well

as the synchronization and initial lane alignment using the SYNC input signal. Optionally data from the transport

layer can be scrambled.

SYSREFSYNCbAB

JESD204B

JESD

204B

INA

DA

JESD204B

JESD

204B

INB

DB

JESD204B

JESD

204B

INC

DC

JESD204B

JESD

204B

IND

DD

Sample

Clock

SYNCbCD

Figure 82. JESD204B Transmitter Block

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7.5.2.1 JESD204B Initial Lane Alignment (ILA)

The initial lane alignment process is started by the receiving device by de-asserting the SYNCb signal. Upon

detecting a logic low on the SYNC input pins, the ADS58J63 starts transmitting comma (K28.5) characters to

establish code group synchronization.

Once synchronization is completed the receiving device re-asserts the SYNCb signal and the ADS58J63 starts

the initial lane alignment sequence with the next local multi frame clock boundary. The ADS58J63 transmits 4

multi-frames each containing K frames (K is SPI programmable). Each of the multi-frames contains the frame

start and end symbols and the 2^ndmulti-frame also contains the JESD204 link configuration data.

{ò{w9C

[aC/ /lock

[aC/ .oundꢁry

aulti

Crꢁme

{òb/ꢀ

Çrꢁnsmit 5ꢁtꢁ

xxx

Y28ꢂꢃ

/ode Droup

{ynchronizꢁtion

Figure 83. ILA Sequence

Y28ꢂꢃ

Lnitiꢁl [ꢁne

!lignment

L[!

5!Ç!

5ꢁtꢁ Çrꢁnsmission

5!Ç!

7.5.2.2 JESD204B Frame Assembly

The JESD204B standard defines the following parameters:

•

L is the number of lanes per link.

M is the number of converters per device.

F is the number of octets per frame clock period.

S is the number of samples per frame.

Table 13 lists the available JESD204B formats and valid ranges for the ADS58J63. The ranges are limited by the

Serdes line rate and the maximum ADC sample frequency.

Table 13. Available JESD204B Formats and Valid Ranges for the ADS58J63

JESD

MODE

(69h, 01h) (6Ah, 01h6)

JESD PLL

MODE

MAX ADC

OUTPUT

RATE (Msps)

MAX f_SERDES

(Gbps)

OPERATING

MODE

OUTPUT

FORMAT

L

M

F

S

DIGITAL MODE

4

2

4

2

4

8

4

8

4

2

4

8

2

1

0,5

2,4

6

2x Decimation

4x Decimation

Complex

Real

40 x

20 x

40 x

80 x

20 x

40 x

20 x

40 x

20 x

40 x

250

125

500

10.0

5.0

Real

10.0

5.0

Complex

Real

6

10.0

7

2x Decimation with

‘0-Pad’

4

2

1

8

Burst Mode

Real

20 x

40 x

500

10.0

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The detailed frame assembly is shown in Table 14.

Table 14. Detailed Frame Assembly

LMFS = 4841

LMFS = 4421

LMFS = 4421 (0-Pad)

DA

DB

DC

DD

AI0[15:8]

BI0[15:8]

CI0[15:8]

DI0[15:8]

AI0[7:0] AQ0[15:8 AQ0[7:0]

]

A0[15:8]

B0[15:8]

C0[15:8]

D0[15:8]

A0[7:0]

A1[15:8]

B1[15:8]

C1[15:8]

D1[15:8]

A1[7:0]

B1[7:0]

C1[7:0]

D1[7:0]

A0[15:8]

B0[15:8]

C0[15:8]

D0[15:8]

A0[7:0]

B0[7:0]

C0[7:0]

D0[7:0]

0000

BI0[7:0] BQ0[15:8 BQ0[7:0]

]

B0[7:0]

C0[7:0]

D0[7:0]

0000

CI0[7:0] CQ0[15:8 CQ0[7:0]

]

0000

DI0[7:0] DQ0[15:8 DQ0[7:0]

]

0000

LMFS = 2441

LMFS = 2881

DB

DC

A0[15:8]

C0[15:8]

A0[7:0]

C0[7:0]

B0[15:8]

D0[15:8]

B0[7:0]

D0[7:0]

AI0[15:8]

CI0[15:8]

AI0[7:0] AQ0[15:8] AQ0[7:0] BI0[15:8]

CI0[7:0] CQ0[15:8] CQ0[7:0] DI0[15:8]

BI0[7:0] BQ0[15:8] BQ0[7:0]

DI0[7:0] DQ0[15:8] DQ0[7:0]

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7.5.2.3 JESD Output Switch

The ADS58J63 provides a digital cross point switch in the JESD204B block which allows internal routing of any

output of the 2 ADCs within one channel pair to any of the 2 JESD204B serial transmitters in order to ease layout

constraints. The cross point switch routing is configured via SPI (address 21h in JESD digital page).

JESD SWITCH

ADCA

ADCB

DAP/M

DBP/M

JESD SWITCH

ADCC

ADCD

DCP/M

DDP/M

Figure 84. Switching the Output Lanes

7.5.2.3.1 Serdes Transmitter Interface

Each of the 10 Gbps serdes transmitter outputs requires AC coupling between transmitter and receiver. The

differential pair should be terminated with 100 Ω as close to the receiving device as possible to avoid unwanted

reflections and signal degradation.

0.1 uF

DA/B/C/DP

R _t= Z _O

Transmission Line

VCM

Receiver

Zo

R _t= Z _O

DA/B/C/DM

0.1 uF

Figure 85. Serdes Transmitter Connection to Receiver

7.5.2.3.2 SYNCb Interface

The ADS58J63 supports single (either SYNCb input controls all 4 JESD204B links) or dual (1 SYNCb input

controls 2 JESD204B lanes (DA/DB and DC/DD) SYNCb control. When using single SYNCb control, the unused

input should be connected to differential logic low (SYNCbxxP = 0 V, SYNCbxxM = IOVDD).

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7.5.2.3.3 Eye Diagram

Figure 86 to Figure 89 show the serial output eye diagrams of the ADS58J63 at 5 Gbps and 10 Gbps with default

and increased output voltage swing against the JESD204B mask.

Figure 86. Eye at 5-Gbps Bit Rate with

Default Output Swing

Figure 87. Eye at 5-Gbps Bit Rate with

Increased Output Swing

Figure 89. Eye at 10-Gbps Bit Rate with

Increased Output Swing

Figure 88. Eye at 10-Gbps Bit Rate with

Default Output Swing

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7.6.2 Example Register Writes

Global Power Down

ADDRESS

11h

DATA

COMMENT

80h

Set Master Page

00h26

Set Global Power Down

Change decimation mode 0 (default) to mode 4 adjusting both the LMFS configuration (LMFS = 4841 to 4421) as

well as serial output data rate (10 Gbps to 5 Gbps).

ADDRESS

4004h

4003h

6000h

6001h

4004h

6016h

4004h

4003h

6000h

DATA

69h

00h

40h

01h

6Ah

00h

61h

41h

CCh

COMMENT

Select digital JESD page

Enables JESD mode overwrite

Select digital to 20x mode

Select analog JESD page

Set serdes PLL to 20x mode

Select decimation filter page

Select mode 4

Digital mixer for chAB set to –4 (FS/4)

6002h

0Ch

Digital mixer for chCD set to –4 (FS/4)

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7.6.3 Register Descriptions

7.6.3.1 Register 0h (offset = 0h) [reset = 0h]

Figure 91. Register 0h

A7-A0 in Hex

7

6

5

4

3

2

1

0

RESET

0

RESET

LEGEND: W = Write only; -n = value after reset

Table 16. Register 0h Field Description

Bit⁽¹⁾

Name

Type

Reset

Description

0 = Normal operation

1 = Internal software reset, clears back to 0

D7

RESET

R/W

0

0 = Normal operation

1 = Internal software reset, clears back to 0

D0

RESET

R/W

0

(1) Both bits (D7, D0) must be set simultaneously to exercise reset

7.6.3.2 Register 3h/4h (offset = 3h/4h) [reset = 0h]

Figure 92. Register 3h/4h

A7-A0 in Hex

7

6

5

4

3

2

1

0

3

4

JESD BANK PAGE SEL [7:0]

JESD BANK PAGE SEL [16:8]

LEGEND: W = Write only; -n = value after reset

Table 17. Register 3h/4h Field Description

Bit

Name

Type

Reset

Description

Program these bits to access desired page in JESD Bank

6100h = Interleaving Engine Page selected

6141h = Decimation Filter Page Selected

6800h = Main Digital Page Selected

D7 - D0 JESD BANK PAGE SEL

R/W

0

6900h = JESD Digtial Page selected

6A00h = JESD Analog Page selected

7.6.3.3 Register 5h (offset = 5h) [reset = 0h]

Figure 93. Register 5h

A7-A0 in Hex

7

6

5

4

3

2

1

0

DIS

BROADCAST

5

0

LEGEND: W = Write only; -n = value after reset

Table 18. Register 5h Field Description

Bit

Name

Type

Reset

Description

0 = Normal operation. Channel A and B are programmed as a pair. Channel

C and D are programmed as a pair.

D0

DIS BROADCAST

R/W

0

1 = channel A and B can be individually programmed based on bit 'CH'.

Similarly channel C and D can be individually programmed based on bit

'CH'.

7.6.3.4 Register 11h (offset = 11h) [reset = 0h]

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Figure 94. Register 11h

A7-A0 in Hex

7

6

5

4

3

2

1

0

11

ANALOG PAGE SELECTION [7:0]

LEGEND: R/W = Read/Write; -n = value after reset

Table 19. Register 11h Field Descriptions

Bit

Name

Type

Reset

Description

Register page (only one page at a time can be addressed).

Master page = 80h

ANALOG PAGE

SELECTION [7:0]

ADC page = 0Fh

D7-D0

R/W

0

The 5 digital pages (Main digital, Interleaving Engine, Analog JESD, Digital

JESD, and Decimation filter) are selected via the M bit. See Serial Interface

Read/Write section for more details.

7.6.3.5 Master Page (80h)

7.6.3.5.1 Register 20h (address = 20h) [reset = 0h] , Master Page (080h)

Figure 95. Register 20h

A7-A0 in Hex

7

6

5

4

3

2

1

0

PDN ADC CHAB

R/W-0h

PDN ADC CHCD

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 20. Registers 20h Field Descriptions

Bit

Field

Type

Reset

Description

7-4

PDN ADC CHAB

R/W

0h

There are two power-down masks that are controlled via the

PDN mask register bit in address 55h. The power-down mask 1

or mask 2 are selected via register bit 5 in address 26h.

Power-down mask 1: addresses 20h and 21h.

3-0

PDN ADC CHCD

R/W

0h

Power-down mask 2: addresses 23h and 24h.

See Power-Down Mode for details.

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7.6.3.5.2 Register 21h (address = 21h) [reset = 0h] , Master Page (080h)

Figure 96. Register 21h

A7-A0 in Hex

7

6

5

4

3

0

2

0

1

0

PDN BUFFER CHCD

R/W-0h

PDN BUFFER CHAB

R/W-0h

W-0h

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 21. Register 21h Field Descriptions

Bit

7-6

5-4

Field

Type

R/W

Reset

0h

Description

PDN BUFFER CHCD

PDN BUFFER CHAB

There are two power-down masks that are controlled via the

PDN mask register bit in address 55h. The power-down mask 1

or mask 2 are selected via register address 26h, bit 5.

Power-down mask 1: addresses 20h and 21h.

0h

3

0

W

0h

Power-down mask 2: addresses 23h and 24h.

See Power-Down Mode for details.

2-0

Must write 0.

7.6.3.5.3 Register 23h (address = 23h), Master Page (080h)

Figure 97. Register 23h

A7-A0 in Hex

7

6

5

4

3

2

1

0

PDN BUFFER CHAB

PDN BUFFER CHCD

R/W-0h R/W-0h

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

R/W-0h

W-0h

Table 22. Register 23h Field Descriptions

Bit

Field

Type

Reset

Description

7-4

PDN ADC CHAB

R/W

0h

There are two power-down masks that are controlled via the

PDN mask register bit in address 55h. The power-down mask 1

or mask 2 are selected via register bit 5 in address 26h.

Power-down mask 1: addresses 20h and 21h.

3-0

PDN ADC CHCD

R/W

0h

Power-down mask 2: addresses 23h and 24h.

See Power-Down Mode for details.

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7.6.3.5.4 Register 24h (address = 24h) [reset = 0h] , Master Page (080h)

Figure 98. Register 24h

A7-A0 in Hex

7

6

5

4

3

0

2

0

1

0

PDN BUFFER CHCD

R/W-0h

PDN BUFFER CHAB

R/W-0h

W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 23. Register 24h Field Descriptions

Bit

7-6

5-4

Field

Type

R/W

Reset

0h

Description

PDN BUFFER CHCD

PDN BUFFER CHAB

There are two power-down masks that are controlled via the

PDN mask register bit in address 55h. The power-down mask 1

or mask 2 are selected via register address 26h, bit 5.

Power-down mask 1: addresses 20h and 21h.

0h

3

0

W

0h

Power-down mask 2: addresses 23h and 24h.

See Power-Down Mode for details.

2-0

Must write 0.

7.6.3.5.5 Register 26h (address = 26h), Master Page (080h)

Figure 99. Register 26h

A7-A0 in Hex

7

6

5

4

3

2

0

1

0

GLOBAL

PDN

OVERRIDE

PDN PIN

PDN MASK

SEL

0

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 24. Register 26h Field Descriptions

Bit

Field

Type

Reset

Description

Bit 6 (OVERRIDE PDN PIN) must be set before this bit can be

programmed.

0 = Normal operation

7

GLOBAL PDN

R/W

0h

1 = Global power-down via the SPI

This bit ignores the power-down pin control.

0 = Normal operation

6

OVERRIDE PDN PIN

R/W

0h

1 = Ignores inputs on the power-down pin

This bit selects power-down mask 1 or mask 2.

0 = Power-down mask 1

1 = Power-down mask 2

5

PDN MASK SEL

0

R/W

0h

4-0

Must write 0

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7.6.3.5.6 Register 3Ah (address = 3Ah) [reset = 0h] , Master Page (80h)

Figure 100. Register 3Ah

A7-A0 in Hex

7

6

5

4

3

2

1

0

MASTER PAGE (80h)

3Ah

0

BUFFER

CURR

0

INCREASE

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 25. Register 3Ah Field Descriptions

Bit

Name

Type

Reset

Description

7, [5-0]

0

W

0h

Must write 0

0 = normal operation

BUFFER CURR

INCREASE

1 = Increases AVDD3V current by 30 mA., improves HD3, helpful for second

Nyquist application. Ensure that regiset bit INPUT BUF CUR EN is also set to

1.

6

R/W

0h

7.6.3.5.7 Register 39h (address = 39h) [reset = 0h] , Master Page (80h)

Figure 101. Register 39h

A7-A0 in Hex

7

6

5

4

3

2

1

0

MASTER PAGE (80h)

39h

ALWAYS WRITE 1

0

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 26. Register 39h Field Descriptions

Bit

Name

Type

R/W

W

Reset

0h

Description

[7:5]

[5-0]

ALWAYS WRITE 1

0

Always set these bits to 11.

Must write 0

0h

7.6.3.5.8 Register 53h (address = 53h) [reset = 0h] , Master Page (80h)

Figure 102. Register 53h Register

A7-A0 in Hex

7

6

5

4

3

2

1

0

MASTER PAGE (80h)

53h

CLK DIV

MASK

0

SYSREF

LEGEND: R/W = Read/Write; -n = value after reset

Table 27. Register 53h Field Descriptions

Bit

Name

Type

Reset

Description

Configures input clock divider

0 = Divide by 4

7

CLK DIV

R/W

0

1= Divide by 2 (must be enabled for proper operation of ADS58J63)

0 = normal operation

1 = ignores SYSREF input

6

MASK SYSREF

R/W

0

53

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7.6.3.5.9 Register 55h (address = 55h) [reset = 0h] , Master Page (80h)

Figure 103. Register 55h

A7-A0 in Hex

7

6

5

4

3

2

1

0

MASTER PAGE (80h)

PDN MASK

55h

0

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 28. Register 55h Field Descriptions

Bit

Name

Type

Reset

Description

4

PDN MASK

R/W

0

Power down via register bit

0 = normal operation

1 = power down enabled powering down internal blocks specified in the

selected power down mask

7.6.3.5.10 Register 56h (address = 56h) [reset = 0h] , Master Page (80h)

Figure 104. Register 56h

A7-A0 in Hex

7

6

5

4

3

2

1

0

MASTER PAGE (80h)

56h

0

INPUT BUFF

CURR EN

0

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 29. Register 56h Field Descriptions

Bit

Name

Type

Reset

Description

3

INPUT BUFF CURR EN R/W

0

0 = normal operation

1 = Increases AVDD3V current by 30 mA., improves HD3, helpful for

second Nyquist application. Ensure that regiset bit BUFFER CURR

INCREASE is also set to 1.

7.6.3.5.11 Register 59h (address = 59h) [reset = 0h] , Master Page (80h)

Figure 105. Register 59h

A7-A0 in Hex

7

6

5

4

3

2

1

0

MASTER PAGE (80h)

39h

0

ALWAYS

WRITE 1

0

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 30. Register 59h Field Descriptions

Bit

Name

Type

Reset

Description

5

ALWAYS WRITE 1

R/W

0h

Always set these bits to 1.

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7.6.3.6 ADC Page (0Fh)

7.6.3.6.1 Register 5Fh (address = 5Fh) [reset = 0h] , ADC Page (0Fh)

Figure 106. Register 5Fh

A7-A0 in Hex

7

6

5

4

3

2

1

0

ADC Page (0Fh)

5Fh

FOVR CHCD THRESH

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 31. Register 5Fh Field Descriptions

Bit

Name

Type

Reset

Description

Controls the location of FAST OVR threshold for channel C and D. Refer to

Over-range Indication.

D [7:0]

FOVR CHCD THRESH

R/W

0h

7.6.3.6.2 Register 60h (address = 60h) [reset = 0h] , ADC Page (0Fh)

Figure 107. Register 60h

A7-A0 in Hex

7

6

5

4

3

2

1

0

ADC Page (0Fh)

60Fh

0

PULSE BIT

CHC

0

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 32. Register 60h Field Descriptions

Bit

Name

Type

Reset

Description

Pulse ⁽¹⁾this bit to improve HD3 for 2nd Nyquist frequiencies (f_IN> 250 MHz)

for channel C.

4

PULSE BIT CHC

R/W

0h

Before pulsing this bit, register bit HD3 NYQ2 CHCD must be set to 1.

(1) Pulsing = Set the bit to 1 and then reset to 0.

7.6.3.6.3 Register 60h (address = 61h) [reset = 0h], ADC Page (0Fh)

Figure 108. Register 61h

A7-A0 in Hex

7

6

5

4

3

2

1

0

ADC Page (0Fh)

61Fh

0

HD3 NYQ2

CHCD

0

PULSE BIT

CHD

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 33. Register 61h Field Descriptions

Bit

Name

Type

Reset

Description

Se this bit to improve HD3 for 2nd Nyquist frequiencies (f_IN> 250 MHz) for

channel C and D. Once this bit is set, it is required to pulse the PULSE BIT

CHx register bits to see the improvement in corresponding channels.

4

HD3 NYQ2 CHCD

R/W

0h

Pulse ⁽¹⁾this bit to improve HD3 for 2nd Nyquist frequiencies (f_IN> 250 MHz)

for channel D.

0

PULSE BIT CHD

R/W

0h

Before pulsing this bit, register bit HD3 NYQ2 CHCD must be set to 1.

(1) Pulsing = Set the bit to 1 and then reset to 0.

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7.6.3.6.4 Register 6Ch (address = 6Ch) [reset = 0h], ADC Page (0Fh)

Figure 109. Register 6Ch

A7-A0 in Hex

7

6

5

4

3

2

1

0

ADC Page (0Fh)

6Ch

0

PULSE BIT

CHA

0

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 34. Register 6Ch Field Descriptions

Bit

Name

Type

Reset

Description

Pulse ⁽¹⁾this bit to improve HD3 for 2nd Nyquist frequiencies (f_IN> 250 MHz)

for channel A.

4

PULSE BIT CHA

R/W

0h

Before pulsing this bit, register bit HD3 NYQ2 CHCAB must be set to 1.

(1) Pulsing = Set the bit to 1 and then reset to 0.

7.6.3.6.5 Register 6Dh (address = 6Dh) [reset = 0h], ADC Page (0Fh)

Figure 110. Register 6Dh

A7-A0 in Hex

7

6

5

4

3

2

1

0

ADC Page (0Fh)

6Dh

0

HD3 NYQ2

CHAB

0

PULSE BIT

CHB

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 35. Register 6Dh Field Descriptions

Bit

Name

Type

Reset

Description

Se this bit to improve HD3 for 2nd Nyquist frequiencies (f_IN> 250 MHz) for

channel A and B. Once this bit is set, it is required to pulse the PULSE BIT

CHx register bits to see the improvement in corresponding channels.

4

HD3 NYQ2 CHAB

R/W

0h

Pulse ⁽¹⁾this bit to improve HD3 for 2nd Nyquist frequiencies (f_IN> 250 MHz)

for channel B.

0

PULSE BIT CHB

R/W

0h

Before pulsing this bit, register bit HD3 NYQ2 CHAB must be set to 1.

(1) Pulsing = Set the bit to 1 and then reset to 0.

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7.6.3.6.6 Register 74h(address = 74h) [reset = 0h], ADC Page (0Fh)

Figure 111. Register 74h

A7-A0 in Hex

D7

D6

D5

D4

D3

D2

D1

D0

ADC Page (0Fh)

74

TEST PATTERN ON CHANNEL

0

LEGEND: R/W = Read/Write; -n = value after reset

Table 36. Register 74h Field Descriptions

Bit

Field

Type

Reset

Description

Test pattern output on channel A and B

0000 Normal Operation using ADC output data

0001 Outputs all 0s

0010 Outputs all 1s

0011 Outputs toggle pattern: Output data are an alternating sequence of

101010101010 and 010101010101

TEST PATTERN ON

CHANNEL

0100 Output digital ramp: output data increments by one LSB every clock

cycle from code 0 to 16384

D7-D4

R/W

0000

0110 Single pattern: output data is custom pattern 1 (75h and 76h)

0111 Double pattern: output data alternates between custom patter 1 and

custom pattern 2

1000 Deskew pattern: output data is 2AAAh

1001 SYNC pattern: output data is 3FFFh

See ADC Test Pattern for more details.

7.6.3.6.7 Register 75h/76h/77h/78h (address = 75h/76h/77h/78h) [reset = 0h], ADC Page (0Fh)

Figure 112. Register 75h/76h/77h/78h

A7-A0 in Hex

D7

D6

D5

D4

D3

D2

D1

D0

ADC Page (0Fh)

75

76

77

78

CUSTOM PATTERN 1[13:6]

CUSTOM PATTERN 1[ 5:0]

CUSTOM PATTERN 2[13:6]

CUSTOM PATTERN 2[ 5:0]

0

LEGEND: R/78W = Read/Write; -n = value after reset

Table 37. Register 75h/76h/77h/78h Field Descriptions

Bit

Name

Type

Reset

Description

7-0

CUSTOM PATTERN

R/W

0

Address 75/76/77/78

Sets the custom pattern (13:6, 5:0) for all channels.

See ADC Test Pattern for more details.

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7.6.3.7 Interleaving Engine Page (6100h)

7.6.3.7.1 Register 18h (address = 18h) [reset = 0h], Interleaving Engine Page (6100h)

Figure 113. Register 18h

A7-A0 in hex

D7

D6

D5

D4

D3

D2

D1

D0

INTERLEAVING ENGINE PAGE (6100h)

18

0

IL BYPASS

LEGEND: R/W = Read/Write; -n = value after reset

Table 38. Register 18h Field Descriptions

Bit

Name

Type

Reset

Description

Allows bypassing of the interleaving correction. To be used when ADC

test patterns are enabled.

00 = interleaving correction enabled

D1-D0

IL BYPASS

R/W

00

11= interleaving correction bypassed

7.6.3.7.2 Register 68h (address = 68h) [reset = 0h], Interleaving Engine Page (6100h)

Figure 114. Register 68h

A7-A0 in hex

D7

D6

D5

D4

D3

D2

D1

D0

INTERLEAVING ENGINE PAGE (6100h)

68

0

DC CORR DIS

0

LEGEND: R/W = Read/Write; -n = value after reset

Table 39. Register 68h Field Descriptions

Bit

Name

Type

Reset

Description

Enables DC offset correction loop.

00 = DC offset correction enabled

11 = DC offset correction disabled

Others = Do not use

D2

DC CORR DIS

R/W

0

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7.6.3.8 Decimation Filter Page (6141h) Registers

7.6.3.8.1 Register 0h (address = 0h) [reset = 0h]

Figure 115. Register 0h

A7-A0 in hex

D7

D6

D5

DECIMATION FILTER PAGE (6141h)

CHB/C FINE MIX

D4

D3

D2

D1

DDC MODE

D0

0

LEGEND: R/W = Read/Write; -n = value after reset

Table 40. 0h Field Descriptions

Bit

Field

Type Reset Description

Selects fine mixing frequency for N × f_S/16 mixer where N is a 2's complement number

varynig from -8 to 7.

0000 = N is 0

0001 = N is 1

0010 = N is 2

...

D7-D4 CHB/C FINE MIX

R/W

0000

0111 = N is 7

1000 = N is -8

...

1111 = N is -1

Selects the DDC Mode for all channels

SETTING

000

MODE

DESCRIPTION

f_S/4 mixing with decimation by 2, complex output

N/A

0

–

2

–

4

5

6

001

010

Decimation by 2, high or low pass filter, real output

N/A

011

100

Decimation by 2, N × f_S/16 mixer, real output

Decimation by 2, N × f_S/16 mixer, complex output

D3-D0 DDC MODE

R/W

0h

101

Decimation by 4, N × f_S/16 mixer, complex output.

Ensure that register bits DDC MODE 6 EN [3:1 ] are

also set to '111'.

110

111

1000

7

8

–

Decimation by 2, N × f_S/16 mixer, insert 0, real output

14-bit burst mode selected.

Others

Do not use

59

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7.6.3.8.2 Register 1h (address = 1h) [reset = 0h]

Figure 116. Register 1h

A7-A0 in hex

D7

D6

D5

D4

D3

D2

D1

D0

DECIMATION FILTER PAGE (6141h)

1

0

DDC MODE6

EN1

ALWAYS

WRITE 1

CHB/C HPF

EN

CHB/C

COARSE MIX

LEGEND: R/W = Read/Write; -n = value after reset

Table 41. Register 1h Field Descriptions

Bit

Name

Type

Reset

Description

D7-D4

0

W

0

Set this bit aong with register bits DDC MODE6 EN2 and DDC

MODE6 EN3 for proper operation of Mode 6.

0 = Default

D3

DDC MODE6 EN1

R/W

0

1 = Use for proper operation of DDC Mode 6.

D2

D1

ALWAYS WRITE 1

CHB/C HPF EN

R/W

0

Always write this bit to 1.

Enables high pass filter for DDC Mode 2 for channel B and C.

0 = Low pass filter enabled

1 = High pass filter enabled

Selects f_S/4 mixer phase for DDC Mode 0 for channel B and C.

D0

CHB/C COARSE MIX

R/W

0

0 = Mix with +f_S/4

1 = Mix with –f_S/4

7.6.3.8.3 Register 2h (address = 2h) [reset = 0h]

Figure 117. Register 2h

A7-A0 in hex

D7

D6

D5

D4

D3

D2

D1

D0

DECIMATION FILTER PAGE (6141h)

2

0

CHA/D HPF

EN

CHA/D

COARSE

MIX

CHA/D FINE MIX

LEGEND: R/W = Read/Write; -n = value after reset

Table 42. 2h Field Descriptions

Bit

Name

Type

Reset

Description

D7-D6

0

CHA/D HPF EN

Enables high pass filter for DDC Mode 2 for channel A and D.

0 = Low pass filter enabled

1 = High pass filter enabled

D5

D4

R/W

0

CHA/D COARSE MIX

Selects f_S/4 mixer phase for DDC Mode 0 for channel A and D.

0 = Mix with +f_S/4

1 = Mix with –f_S/4

Selects fine mixing frequency for N × f_S/16 mixer where N is a

2's complement number varynig from -8 to 7.

0000 = N is 0

0001 = N is 1

0010 = N is 2

...

D3-D0

CHA/D FINE MIX

R/W

0000

0111 = N is 7

1000 = N is -8

...

1111 = N is -1

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7.6.3.9 Main Digital Page (6800h) Registers

7.6.3.9.1 Register 0h (address = 0h) [reset = 0h], Main Digital Page (6800h)

Figure 118. Register 0h

A7-A0 in hex

D7

D6

D5

D4

D3

D2

D1

D0

MAIN DIGITAL PAGE (6800h)

0

IL RESET

LEGEND: R/W = Read/Write; -n = value after reset

Table 43. Register 0h Field Descriptions

Bit

Name

Type

Reset

Description

Resets the interleaving engine. This bit is not a self-clearing bit

and must be pulsed⁽¹⁾

.

Any register bit in Main Digital Page (6800h) takes effect only

after this bit is pulsed. Also, note that pulsing this bit clears

registers in interleaving page (6100h).

D0

IL RESET

R/W

0

0 = normal operation

0 → 1 → 0 = interleaving engine reset.

(1) Pulsing = Set the bit to 1 and then reset to 0.

7.6.3.9.2 Register 42h(address = 42h) [reset = 0h], Main Digital Page (6800h)

Figure 119. Register 42h

A7-A0 in hex

D7

D6

D5

D4

D3

D2

D1

D0

MAIN DIGITAL PAGE (6800h)

42

0

NYQUIST ZONE

LEGEND: R/W = Read/Write; -n = value after reset

Table 44. Register 42h Field Descriptions

Bit

Name

Type

Reset

Description

Provide Nyquist zone information to IL engine. Ensure that register bit CTRL

NYQUIST is set to 1.

000 = 1^stNyquist zone (input frequencies between 0 to f_S/2)

001 = 2^ndNyquist zone (input frequencies between f_S/2 to f_S)

010 = 3^rdNyquist zone (input frequencies between f_Sto 3f_S/2)

...

NYQUIST

ZONE

D2-D0

R/W

000

111 = 8^thNyquist zone (input frequencies between 7f_S/2 to 4f_S)

7.6.3.9.3 Register 4Eh (address = 4Eh) [reset = 0h], Main Digital Page (6800h)

Figure 120. Register 4Eh

A7-A0 in hex

D7

D6

D5

D4

D3

D2

D1

D0

MAIN DIGITAL PAGE (6800h)

4E

CTRL

0

NYQUIST

LEGEND: R/W = Read/Write; -n = value after reset

Table 45. Register 4Eh Field Descriptions

Bit

Name

Type

Reset

Description

Enables Nyquist zone control using register bits NYQUIST ZONE.

0 = Selection disabled

D7

CTRL NYQUIST R/W

0

1 = Selection enabled

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7.6.3.9.4 Register ABh (address = ABh) [reset = 0h], Main Digital Page (6800h)

Figure 121. Register ABh

A7-A0 in hex

D7

D6

D5

D4

D3

D2

D1

D0

MAIN DIGITAL PAGE (68h)

AB

0

OVR EN

LEGEND: R/W = Read/Write; -n = value after reset

Table 46. Register ABh Field Descriptions

Bit

Field

Type

Reset

Description

Set this bit to enable register bit OVR ON LSB.

0 = normal operation

D0

OVR EN

R/W

0

1 = OVR ON LSB enabled

7.6.3.9.5 Register ADh (address = ADh) [reset = 0h], Main Digital Page (6800h)

Figure 122. Register ADh

A7-A0 in hex

D7

D6

D5

D4

D3

D2

D1

D0

MAIN DIGITAL PAGE (68h)

AD

0

OVR ON LSB

LEGEND: R/W = Read/Write; -n = value after reset

Table 47. Register ADh Field Descriptions

Bit

Field

Type

Reset

Description

Set this bit to bring OVR on two LSBs of 16-bit output. Ensure that register bit OVR

EN is set to 1

0000 = Bits D0 and D1 of 16-bit data are noise bits

0011 = OVR comes on bit D0 of 16-bit data

D0

OVR EN

R/W

0

1100 = OVR comes on bit D1 of 16-bit data

1111 = OVR comes on both D0 and D1 bits of 16-bit data

7.6.3.9.6 Register F7h (address = F7h) [reset = 0h], Main Digital Page (68h)

Figure 123. Register F7h

A7-A0 in hex

D7

D6

D5

D4

D3

D2

D1

D0

MAIN DIGITAL PAGE (68h)

F7

0

DIG RESET

LEGEND: R/W = Read/Write; -n = value after reset

Table 48. Register F7h Field Descriptions

Bit

Field

Type

Reset

Description

Self clearing reset for the digital block. Does not include the interleaving correction.

D0

DIG RESET

R/W

0

0 = normal operation

1 = digital reset

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7.6.3.10 JESD Digital Page (6900h) Registers

7.6.3.10.1 Register 0h (address = 0h) [reset = 0h], JESD Digital Page (6900h)

Figure 124. Register 0h

A7-A0 in hex

D7

D6

D5

JESD DIGITAL PAGE (6900h)

JESD MODE DDC MODE6 TESTMODE

EN EN2 EN

LEGEND: R/W = Read/Write; -n = value after reset

D4

D3

D2

D1

D0

0

CTRL K

0

LANE ALIGN

FRAME

ALIGN

TX LINK DIS

Table 49. Register 0h Field Descriptions

Bit

Name

Type

Reset

Description

Enable bit for a number of frames per multi frame.

0 = Default is 5 frames per multi frame

D7

CTRL K

R/W

0

1 = Frames per multi frame can be set in register 06h

Allows changing the JESD MODE setting in register 01h (D1-D0)

0 = Disabled

1 = Enables changing the JESD MODE setting

JESD MODE

EN

D6

D5

R/W

0

Set this bit aong with register bits DDC MODE6 EN1 and DDC MODE6 EN3 for

proper operation of Mode 6.

0 = Default

DDC MODE6

EN2

1 = Use for proper operation of DDC Mode 6.

This bit generates the long transport layer test pattern mode, as per section 5.1.6.3 of

the JESD204B specification.

0 = Test mode disabled

1 = Test mode enabled

D4

D2

D1

D0

TESTMODE EN R/W

0

This bit inserts the lane alignment character (K28.3) for the receiver to align to lane

boundary, as per section 5.3.3.5 of the JESD204B specification.

0 = Normal operation

LANE ALIGN

R/W

1 = Inserts lane alignment characters

This bit inserts the lane alignment character (K28.7) for the receiver to align to lane

boundary, as per section 5.3.3.5 of the JESD204B specification.

0 = Normal operation

FRAME ALIGN R/W

1 = Inserts frame alignment characters

This bit disables sending the initial link alignment (ILA) sequence when SYNC is de-

asserted.

0 = Normal operation

1 = ILA disabled

TX LINK DIS

R/W

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7.6.3.10.2 Register 1h (address = 1h) [reset = 0h], JESD Digital Page (6900h)

Figure 125. Register 1h

A7-A0 in hex

D7

D6

D5

D4

D3

D2

D1

D0

JESD MODE

JESD DIGITAL PAGE (6900h)

1

SYNC REG

SYNC REG SYNCB SEL

EN AB/CD

0

DDC MODE6

EN3

0

LEGEND: R/W = Read/Write; -n = value after reset

Table 50. Register 1h Field Descriptions

Bit

Name

Type

Reset

Description

SYNC Register (Bit D6 must be enabled)

0 = Normal operation

D7

SYNC REG

R/W

0

1 = ADC output data are replaced with K28.5 characters.

Enables bit for SYNC operation

0 = Normal operation

1 = ADC output data over-write enabled

D6

D5

SYNC REG EN R/W

0

Selects which SYNCb input controls the JESD interface. Needs to be configured for

SYNCB SEL

R/W

chAB and chCD

0 = SYLNCbAB

1 = SYNCbCD

AB/CD

Set this bit aong with register bits DDC MODE6 EN1 and DDC MODE6 EN2 for

proper operation of Mode 6.

0 = Default

DDC MODE6

R/W

D5

0

EN3

1 = Use for proper operation of DDC Mode 6.

Selects number of serial JESD output lanes per ADC. Also need to set the JESD

MODE EN (00h) and JESD PLL MODE register (JESD ANALOG page, register 16h)

accordingly.

01 = 20x mode

10 = 40x mode

11 = 80x mode

All others = Not used

D1-D0

JESD MODE

R/W

7.6.3.10.3 Register 2h (address = 2h) [reset = 0h], JESD Digital Page (6900h)

Figure 126. Register 2h

A7-A0 in hex

D7

D6

D5

D4

D3

D2

D1

D0

JESD DIGITAL PAGE (6900h)

2

LINK LAYER TESTMODE

LINK LAYER LMFC MASK

0

RPAT

RESET

LEGEND: R/W = Read/Write; -n = value after reset

Table 51. Register 2h Field Descriptions

Bit

Name

Type

Reset

Description

These bits generate a pattern according to clause 5.3.3.8.2 of

the JESD204B document.

000 = Normal ADC data

001 = D21.5 (high-frequency jitter pattern)

010 = K28.5 (mixed-frequency jitter pattern)

011 = Repeat initial lane alignment (generates a K28.5 character

and continuously repeats lane alignment sequences)

100 = 12 octet RPAT jitter pattern

D7-D5

LINK LAYER TESTMODE

R/W

000

This bit changes the running disparity in the modified RPAT

pattern test mode (only when the link layer test mode = 100).

0 = Normal operation

D4

D3

LINK LAYER RPAT

LMFC MASK RESET

R/W

0

1 = Changes disparity

0 = Default

1 = Resets LMFC mask

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7.6.3.10.4 Register 3h (address = 3h) [reset = 0h], JESD Digital Page (6900h)

Figure 127. Register 3h

A7-A0 in hex

D7

D6

D5

D4

D3

D2

D1

D0

JESD DIGITAL PAGE (69h)

3

FORCE

LMFC

LMFC COUNT INIT

RELEASE ILANE SEQ

COUNT

LEGEND: R/W = Read/Write; -n = value after reset

Table 52. 3h Field Descriptions

Bit

Name

Type

Reset

Description

Force LMFC count.

0 = Normal operation

1 = Enables using a different starting value for the LMFC

counter

D7

FORCE LMFC COUNT

R/W

0

SYSREF coming to the digital block will reset the LMFC count to

0 and K28.5 will stop coming when the LMFC count reaches 31.

The initial value to which LMFC count resets to can be set using

LMFC COUNT INIT. This way the Rx can get synchronized early

since it will get the LANE ALIGNMENT SEQUENCE early.

Register bit FORCE LMFC COUNT must be enabled.

D6-D2

D1-D0

LMFC COUNT INIT

R/W

00000

Delays the generation of lane alignment sequence by 0, 1, 2, or

3 multi frames after code group synchronization.

00 = 0

01 = 1

10 = 2

11 = 3

RELEASE ILANE SEQ

00

7.6.3.10.5 Register 5h (address = 5h) [reset = 0h], JESD Digital Page (6900h)

Figure 128. Register 5h

A7-A0 in hex

D7

D6

D5

D4

D3

D2

D1

D0

JESD DIGITAL PAGE (69h)

5h

SCRAMBLE

EN

0

LEGEND: R/W = Read/Write; -n = value after reset

Table 53. 5h Field Descriptions

Bit

Name

Type

Reset

Description

Scramble enable bit in the JESD204B interface.

0 = Scrambling disabled

D7

SCRAMBLE EN

R/W

1 = Scrambling enabled

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7.6.3.10.6 Register 6h (address = 6h) [reset = 0h], JESD Digital Page (6900h)

Figure 129. Register 6h

A7-A0 in hex

D7

D6

D5

D4

D3

D2

D1

D0

JESD DIGITAL PAGE (69h)

6

0

FRAMES PER MULTI FRAME (K)

LEGEND: R/W = Read/Write; -n = value after reset

Table 54. 6h Field Descriptions

Bit

Name

Type

Reset

Description

D7-D5

FRAMES PER MULTI

FRAME (K)

set the number of multi frames.

Actual K is the value in hex + 1 (that is, 0Fh is K = 16).

D4-D0

R/W

00000

7.6.3.10.7 Register 17h (address = 17h) [reset = 0h], JESD Digital Page (6900h)

Figure 130. Register 17h

A7-A0 in hex

D7

D6

D5

D4

D3

D2

D1

D0

JESD DIGITAL PAGE (69h)

17

HIRES FLAG ON LSB

0

TRIG SET

AB/CD

AUTO TRIG

EN

0

RATIO

INVALID

0

LEGEND: R/W = Read/Write; -n = value after reset

Table 55. 17h Field Descriptions

Bit

Name

Type

Reset

Description

Applicable only in 14-bit Burst mode. Program two LSBs of 16-bit data as flag

for 14-bit high resolution samples. Flag is '1' when the sample belongs to 14-

bit resolution.

D7 - D6 HIRES FLAG ON LSB

R/W

0

00 = LSB Bits D0 and D1 of 16-bit data noise bits.

01 = Bit D0 carries high-resolution flag.

10 = Bit D1 carries high-resolution flag.

11 = Both bits D0 and D1 carry high-resolution flag.

TRIG SET AB/CD

D4

Determines if triggerAB or triggerCD pin is used for burst mode. Needs to be

configured individually for chAB and chCD with paging.

0 = uses TRIGGERAB pin

R/W

0

1 = uses TRIGGERCD pin

Enables automatic trigger in burst mode (ignores TRIGGERAB/CD inputs)

0 = auto trigger disabled

1= auto trigger enabled

D3

D1

AUTO TRIG EN

RATIO INVALID

R/W

0

Alarm flag when duty cycle ratio between high and low resolution counter is

set incorrectly.

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7.6.3.10.8 Register 19h/1Ah/1Bh/1Ch (address = 19h/1Ah/1Bh/1Ch) [reset = 0h], JESD Digital Page (6900h)

Figure 131. Register 19h/1Ah/1Bh/1Ch

A7-A0 in hex

D7

D6

D5

D4

D3

D2

D1

D0

JESD DIGITAL PAGE (69h)

19

1A

1B

1C

0

LC[27:24]

LC[23:16]

LC[15:8]

LC[7:0]

Table 56. 19h/1Ah/1Bh/1Ch Field Descriptions

Bit

Name

LC [xx:xx]

Type

Reset

Description

Sets the low resolution counter value. While programming LC[27:0], first

program LC[7:0], then LC[15:8], then LC[23:16], and then LC[27:24] in the

same order.

D7-D0

R/W

0

7.6.3.10.8.1 Register 1Dh/1Eh/1Fh/20h (address = 1Dh/1Eh/1Fh/20h) [reset = 0h], JESD Digital Page (6900h)

Figure 132. Register 1Dh/1Eh/1Fh/20h

A7-A0 in hex

D7

D6

D5

D4

D3

D2

D1

D0

JESD DIGITAL PAGE (69h)

1D

1E

1F

20

0

HC[27:24]

HC[23:16]

HC[15:8]

HC[7:0]

Table 57. 1Dh/1Eh/1Fh/20h Field Descriptions

Bit

Name

HC [xx:xx]

Type

Reset

Description

Sets the high resolution counter value. While programming HC[27:0], first

program HC[7:0], then HC[15:8], then HC[23:16], and then HC[27:24] in

the same order.

D7-D0

R/W

0

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7.6.3.10.8.2 Register 21h (address = 21h) [reset = 0h], JESD Digital Page (6900h)

Figure 133. Register 21h

A7-A0 in hex

D7

D6

D5

D4

D3

D2

D1

D0

JESD DIGITAL PAGE (69h)

21

OUTPUT CHA MUX SEL

OUTPUT CHB MUX SEL

OUTPUT CHC MUX SEL

OUTPUT CHD MUX SEL

LEGEND: R/W = Read/Write; -n = value after reset

Table 58. 21h Field Descriptions

Bit

Name

Type

Reset

Description

Serdes lane swap with chB

00 = ChA is output on lane DA

10 = ChA is output on lane DB

01/11 = Do not use

D7-D6

OUTPUT CHA MUX SEL

R/W

00

Serdes lane swap with chA

00 = ChB is output on lane DB

10 = ChB is output on lane DA

01/11 = Do not use

D5-D4

D3-D2

D1-D0

OUTPUT CHB MUX SEL

OUTPUT CHC MUX SEL

OUTPUT CHD MUX SEL

R/W

00

Serdes lane swap with chD

00 = ChC is output on lane DC

10 = ChC is output on lane DD

01/11 = Do not use

Serdes lane swap with chC

00 = ChD is output on lane DD

10 = ChD is output on lane DC

01/11 = Do not use

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7.6.3.10.8.3 Register 22h (address = 22h) [reset = 0h], JESD Digital Page (6900h)

Figure 134. Register 22h

A7-A0 in hex

D7

D6

D5

JESD DIGITAL PAGE (6900h)

OUT CHA

INV

D4

D3

D2

D1

D0

22

0

OUT CHB

INV

OUT CHC

INV

OUT CHD INV

LEGEND: R/W = Read/Write; -n = value after reset

Table 59. 22h Field Descriptions

Bit

Name

Type

Reset

Description

D7-D4

0

Polarity inversion of JESD output of chA

0 = normal operation

1 = output polarity inverted

D3

D2

D1

D0

OUT CHA INV

OUT CHB INV

OUT CHC INV

OUT CHD INV

R/W

0

Polarity inversion of JESD output of chB

0 = normal operation

1 = output polarity inverted

Polarity inversion of JESD output of chC

0 = normal operation

1 = output polarity inverted

Polarity inversion of JESD output of chD

0 = normal operation

1 = output polarity inverted

7.6.3.11 JESD Analog Page (6A00h) Register

7.6.3.11.1 Register 12h/13h (address 12h/13h) [reset = 0h], JESD Analog Page (6Ah)

Figure 135. Register 12h/13h

A7-A0 in hex

D7

D6

D5

D4

D3

D2

D1

D0

JESD ANALOG PAGE (6A00h)

SEL EMP LANE DA/DD

12

13

0

SEL EMP LANE DB/DC

LEGEND: R/W = Read/Write; -n = value after reset

Table 60. 12h/13h Field Descriptions

Bit

Name

Type

Reset

Description

Selects the amount of de-emphasis for the JESD output transmitter. The

de-emphasis value in dB is measured as the ratio between the peak

value after the signal transition to the settled value of the voltage in one

bit period.

0 = 0 dB

1 = –1 dB

3 = –2 dB

SEL EMP LANE DA/DD

SEL EMP LANE DB/DC

D7-D2

R/W

000000

7 = –4.1 dB

15 = –6.2 dB

31 = –8.2 dB

63 = –11.5 dB

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7.6.3.11.2 16h (address = 16h) [reset = 0h], JESD Analog Page (6A00h)

Figure 136. Register 16h

A7-A0 in hex

D7

D6

D5

D4

D3

D2

D1

D0

JESD ANALOG PAGE (6A00h)

16

0

JESD PLL MODE

LEGEND: R/W = Read/Write; -n = value after reset

Table 61. 16h Field Descriptions

Bit

Name

Type

Reset

Description

D7-D1

Selects the JESD PLL multiplication factor

0 = 20x mode

D0

JESD PLL MODE

R/W

0

1 = 40x mode

7.6.3.11.3 Register 1Bh (address = 1Bh) [reset = 0h], JESD Analog Page (6Ah)

Figure 137. Register 1Bh

A7-A0 in hex

D7

D6

D5

D4

D3

D2

D1

D0

JESD ANALOG PAGE (6Ah)

1B

JESD SWING

0

LEGEND: R/W = Read/Write; -n = value after reset

Table 62. 1Bh Field Descriptions

Bit

Name

Type

Reset Description

Programs SERDES output swing

0 = 860 mVPP

1 = 810 mVPP

2 = 770 mVPP

D7-D5

D4-D3

JESD SWING

R/W

000

3 = 745 mVPP

4 = 960 mVPP

5 = 930 mVPP

6 = 905 mVPP

7 = 880 mVPP

0

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Start-Up Sequence

The following steps are recommended as the power up sequence with the ADS58J63 in 2x complex decimation

mode (DDC Mode 0) with LMFS = 4841 (shown in Table 63).

Table 63. Recommended Power-Up Sequence

REGISTER

ADDRESS

REGISTE

R DATA

STEP

DESCRIPTION

COMMENT

1

Supply all supply voltages. There is no

required power supply sequence for the 1.15-

V supply, 1.9-V supply and 3-V supply, and

these may be supplied in any order.

—

2

Pulse a hardware reset (low to high to low) on

pin 48.

—

Alternatively it can be reset with:

Analog reset and Digital reset

00h

81h

68h

00h

01h

4004h

4003h

4002h

4001h

60F7h

3

4

5

Set input clock divider

11h

53h

80h

Select master page

Set clock divider to /2

Reset interleaving correction engine. Register

access default into page 68h

6000h

01h

00h

Channel AB (and channel CD since device

is in broadcast mode)

Default registers for JESD analog page

4003h

4004h

6016h

00h

6Ah

02h

Select JESD analog page

m

PLL mode 40x for Channel AB and CD

6

Default registers for JESD digital page

4003h

4004h

6000h

6006h

00h

69h

80h

0Fh

Select JESD digital page

m

Set CTRL K for channel AB and CD

Set K to 16

7

8

Enable single SYNCb input (SYNCAB)

4005h

7001h

01h

22h

Disable broadcast mode

Use SYNCAB for channel C/D

Pulse SYNCb (pin 55/56) from low to high to

transmit data from k28.5 sync mode

—

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8.1.2 Hardware Reset

Power Supplies

t₁

RESET

t₂

t₃

SEN

Figure 138. Hardware Reset Timing Diagram

Table 64. Timing Requirements for Figure 138

MIN

1

TYP MAX

UNIT

ms

ns

t₁

t₂

t₃

Power-on delay

Delay from power up to active high RESET pulse

Active high RESET pulse duration

Reset pulse duration

Register write delay

10

Delay from RESET disable to SEN active

100

ns

8.1.3 SNR and Clock Jitter

The signal to noise ratio of the ADC is limited by three different factors: the quantization noise is typically not

noticeable in pipeline converters and is 84 dB for a 14-bit ADC. The thermal noise limits the SNR at low input

frequencies while the clock jitter sets the SNR for higher input frequencies.

(2)

The SNR limitation resulting from sample clock jitter can be calculated following:

(3)

The total clock jitter (T_Jitter) has two components – the internal aperture jitter (120 fs for ADS58J63) which is set

by the noise of the clock input buffer and the external clock jitter. It can be calculated as following:

(4)

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass

filters at the clock input while a faster clock slew rate also improves the ADC aperture jitter.

The ADS58J63 has a thermal noise of approximately 72 dBFS and an internal aperture jitter of 120 fs.

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8.1.4 ADC Test Pattern

The ADS58J63 provides several different options to output test patterns instead of the actual output data of the

ADC in order to simplify bring up of the JESD204B digital interface link. The output data path is shown in

Figure 139

!5/ {ection

Çransport [ayer

[ink [ayer

ꢀIò [ayer

DDC

Data Mapping

Frame

Construction

ADC

8b/10b

Interleaving

Correction

Burst

Mode

encoding

Scrambler

1+x¹⁴+x¹⁵

Serializer

ADC Test

Pattern

JESD204B Long

Transport Layer

Test Pattern

JESD204B

Link Layer

Test Pattern

Figure 139. ADC Test Pattern

8.1.4.1 ADC Section

The ADC test pattern replaces the actual output data of the ADC. The following test patterns are available in

register 74h. In order to get the test pattern output propoerly, the interleaving correction needs to be disabled

(6100h, address 18h) and burst mode enabled (DDC disabled).

Burst mode only supports LMFS = 4421 (DDC Modes have different configurations) and test pattern switches

between 9-bit (low resolution) and 14-bit (high resolution) output. See Table 65

Table 65. ADC Test Pattern Settings

Bit

Name

Default

Description

Test pattern output on channel A and B

0000 Normal Operation using ADC output data

0001 Outputs all 0s

0010 Outputs all 1s

0011 Outputs toggle pattern: Output data are an

alternating sequence of 101010101010 and

010101010101

D7-D4

TEST PATTERN

0000

0100 Output digital ramp: output data increments by

one LSB every clock cycle from code 0 to 16384

0110 Single pattern: output data is custom pattern 1

(75h and 76h)

0111 Double pattern: output data alternates between

custom patter 1 and custom pattern 2

1000 Deskew pattern: output data is 2AAAh

1001 SYNC pattern: output data is 3FFFh

8.1.4.2 Transport Layer Pattern

The Transport Layer maps the ADC output data into 8bit octets and constructs the JESD204B frames using the

LMFS parameters. Tail bits or ‘0’s are added when needed. Alternatively the JESD204B long transport layer test

pattern can be substituted as shown in Table 66 .

Table 66. Transport Layer Test-mode

Bit

Name

Default

Description

Generates long transport layer test pattern mode

according to clause 5.1.6.3 of JESD204B specification

0 = test mode disabled

D4

TESTMODE EN

0

1 = test mode enabled

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8.1.4.3 Link Layer Pattern

The Link Layer contains the scrambler and the 8b/10b encoding of any data passed on from the Transport Layer.

Additionally it also handles the initial lane alignment sequence which can be manually restarted. The Link Layer

test patterns are intended for testing the quality of the link (jitter testing etec). The test patterns do not pass

through the 8b/10b encoder and contain the options shown in Table 67.

Table 67. Link Layer Test-mode

Bit

Name

Default

Description

Generates pattern according to clause 5.3.3.8.2 of the

JESD204B document

000 normal ADC data

001 D21.5 (high frequency jitter pattern)

010 K28.5 (mixed frequency jitter pattern)

011 Repeat initial lane alignment (generates K28.5

character and repeat lane alignment sequences

continuously)

D7-D5

LINK LAYER TESTMODE

000

100 12 octet RPAT jitter pattern

Furthermore a 2¹⁵PRBS can be enabled by setting up a custom test pattern (AAAA) in the ADC section and

running that through the 8b/10b encoder with scrambling enabled.

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8.2 Typical Application

The ADS58J63 is designed for wideband receiver applications demanding excellent dynamic range over a large

input frequency range. A typical schematic for an AC coupled dual receiver (dual FPGA with dual SYNC) is

shown below.

DVDD

5 ꢀ

10 kꢀ

25 ꢀ

3.3 pF

0.1 uF

GND

Driver

SPI Master

25 ꢀ

5 ꢀ

GND

IOVDD GND

0.1 uF

GND

0.1 uF

AVDD

0.1 uF

DVDD

AVDD3V

AVDD

AVDD3V

5 ꢀ

25 ꢀ

3.3 pF

25 ꢀ

0.1 uF

100 ꢀ Differential

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

GND

INCP

SYNCbCDP

SYNCbCDM

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

50 ꢀ

Vterm=1.2 V

AVDD

AGND

AVDD

0.1 uF

GND

IOVDD

FPGA

IOVDD

DDP

10 nF

GND

10 nF

NC

DDM

GND

0.1 uF

AVDD3V

AVDD

DGND

DCP

GND

AVDD

0.1 uF

GND

DCM

AGND

10 nF

IOVDD

0.1 uF

GND

IOVDD

DGND

DBM

CLKINP

CLKINM

AGND

100 ꢀ

ADS58J63

GND

0.1 uF

AVDD

GND PAD (backside)

Low Jitter

Clock

Generator

DBP

AVDD

DGND

DAM

AVDD3V

AGND

AVDD3V

0.1 uF

GND

10 nF

GND

DAP

SYSREFP

100 ꢀ

IOVDD

10 nF

IOVDD

SYNCbABM

SYNCbABP

SYSREFM

AVDD

GND

50 ꢀ

Vterm=1.2 V

5 ꢀ

INBP

FPGA

25 ꢀ

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

0.1 uF

100 ꢀ Differential

0.1 uF

GND

3.3 pF

Driver

25 ꢀ

5 ꢀ

AVDD3V

AVDD

DVDD

AVDD

AVDD3V

0.1 uF

GND

0.1 uF

IOVDD

0.1 uF

GND

5 ꢀ

25 ꢀ

0.1 uF

GND

3.3 pF

25 ꢀ

GND = AGND + DGND connected in Layout

25 ꢀ

NOTE: GND = AGND and DGND connected in the PCB layout.

Figure 140. Application Diagram ADS58J63

8.2.1 Design Requirements

By using the simple drive circuit of Figure 140 (when AMP drives ADC) or Figure 51 (when transformers drive

ADC), uniform performance can be obtained over a wide frequency range. The buffers present at the analog

inputs of the device help isolate the external drive source from the switching currents of the sampling circuit.

8.2.2 Detailed Design Procedure

For optimum performance, the analog inputs must be driven differentially. This architecture improves the

common-mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with

each input pin is recommended to damp out ringing caused by package parasitics, as shown in Figure 140.

75

ADS58J63

ZHCSDU3A –JUNE 2015–REVISED JUNE 2015

www.ti.com.cn

Typical Application (continued)

8.2.3 Application Curves

Figure 141 and Figure 142 show the typical performance at 190 MHz and 230 MHz, respectively.

0

-20

0

-20

-40

-60

-80

-100

-120

-100

-120

0

50

100

150

200

250

0

50

100

150

200

250

Input Frequency (MHz)

D003

D004

F_IN= 190 MHz , A_IN= –1 dBFS

F_IN= 230 MHz , A_IN= –1 dBFS

SNR = 69.4 dBFS, SFDR = 88 dBc, SFDR = 96 dBc (Non23)

SNR = 69.4 dBFS, SFDR = 85 dBc, SFDR = 96 dBc (Non23)

Figure 141. FFT for 190-MHz Input Signal

Figure 142. FFT for 230-MHz Input Signal

9 Power Supply Recommendations

The device requires a 1.9-V nominal supply for DVDD, a 1.9-V nominal supply for AVDD, and a 3-V nominal

supply for AVDD3V. There is no specific sequence for power-supply requirements during device power-up.

AVDD, DVDD, and AVDD3V can power-up in any order.

76

ADS58J63

www.ti.com.cn

ZHCSDU3A –JUNE 2015–REVISED JUNE 2015

10 Layout

10.1 Layout Guidelines

The device evaluation module (EVM) layout can be used as a reference layout to obtain the best performance. A

layout diagram of the EVM top layer is provided in Figure 143. Complete layout of EVM is available at

ADS58J63's EVM folder. Some important points to remember during board layout are:

•

Analog inputs are located on opposite sides of the device pinout to ensure minimum crosstalk on the package

level. To minimize crosstalk onboard, the analog inputs must exit the pinout in opposite directions, as shown

in the reference layout of Figure 143 as much as possible.

In the device pinout, the sampling clock is located on a side perpendicular to the analog inputs in order to

minimize coupling between them. This configuration is also maintained on the reference layout of Figure 143

as much as possible.

Keep digital outputs away from the analog inputs. When these digital outputs exit the pinout, the digital output

traces must not be kept parallel to the analog input traces because this configuration can result in coupling

from the digital outputs to the analog inputs and degrade performance. All digital output traces to the receiver

[such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)] must be

matched in length to avoid skew among outputs.

•

At each power-supply pin (AVDD, DVDD, or AVDDD3V), keep a 0.1-µF decoupling capacitor close to the

device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF

capacitors can be kept close to the supply source.

10.2 Layout Example

Figure 143. ADS58J63 EVM Layout

77

ADS58J63

ZHCSDU3A –JUNE 2015–REVISED JUNE 2015

www.ti.com.cn

11 器件和文档支持

11.1 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.2 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.3 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不

对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

78

PACKAGE MATERIALS INFORMATION

www.ti.com

31-Aug-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADS58J63IRMPR

VQFN

RMP

72

1500

330.0

24.4

10.25 10.25 2.25

16.0

24.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

31-Aug-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VQFN RMP 72

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 43.0

ADS58J63IRMPR

1500

Pack Materials-Page 2

PACKAGE OUTLINE

RMP0072A

VQFN - 0.9 mm max height

SCALE 1.700

VQFN

10.1

9.9

A

B

PIN 1 ID

10.1

9.9

0.9 MAX

0.05

0.00

C

SEATING PLANE

0.08 C

(0.2)

4X (45 X0.42)

19

36

18

37

SYMM

4X

8.5

8.5 0.1

PIN 1 ID

(R0.2)

1

54

0.30

0.18

72X

72

55

68X 0.5

SYMM

0.5

0.3

0.1

C B

A

72X

0.05

C

4221047/B 02/2014

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RMP0072A

VQFN - 0.9 mm max height

VQFN

(

8.5)

SYMM

72X (0.6)

SEE DETAILS

55

72

1

54

72X (0.24)

(0.25) TYP

SYMM

(9.8)

(1.315) TYP

68X (0.5)

(

0.2) TYP

VIA

37

18

19

36

(1.315) TYP

(9.8)

LAND PATTERN EXAMPLE

SCALE:8X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4221047/B 02/2014

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON PCB application report

in literature No. SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RMP0072A

VQFN - 0.9 mm max height

VQFN

(9.8)

72X (0.6)

(1.315) TYP

72

55

1

54

72X (0.24)

(1.315)

TYP

(0.25) TYP

SYMM

(9.8)

(1.315)

TYP

68X (0.5)

METAL

TYP

37

18

(

0.2) TYP

VIA

19

36

36X ( 1.115)

(1.315) TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

62% PRINTED SOLDER COVERAGE BY AREA

SCALE:8X

4221047/B 02/2014

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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型号：	ADS58J63IRMPR
厂家：	TEXAS INSTRUMENTS
描述：	四通道 14 位 500Msps 电信接收器 IC \| RMP \| 72 \| -40 to 85 电信
文件：	总86页 (文件大小：6240K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS58J63IRMPR [TI]

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