ADS58J64 [TI]
四通道、14 位、1GSPS 电信接收器和反馈 IC;型号: | ADS58J64 |
厂家: | TEXAS INSTRUMENTS |
描述: | 四通道、14 位、1GSPS 电信接收器和反馈 IC 电信 |
文件: | 总89页 (文件大小:11286K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ADS58J64
ZHCSFY7B –JANUARY 2017 –REVISED DECEMBER 2021
ADS58J64 四通道、14 位、1GSPS 电信接收器
1 特性
3 说明
• 四通道
• 14 位分辨率
ADS58J64 是一款低功耗、高带宽、14 位、1GSPS、
四通道电信接收器。ADS58J64 支持 JESD204B 串行
接口,每个通道上具有 1 条信道,数据传输速率高达
10Gbps。经缓冲的模拟输入可在较宽频率范围内提供
统一输入阻抗,并最大程度地降低采样和保持毛刺脉冲
能量。ADS58J64 以超低功耗在宽输入频率范围内提
供出色的无杂散动态范围 (SFDR)。数字信号处理模块
包含复混频器,后接低通滤波器。低通滤波器具有 2
倍抽取率和 4 倍抽取率两个选项,支持高达 200MHz
的接收器带宽。此外,ADS58J64 在突发模式下还支
持 14 位、500MSPS 输出,因此适用于数字预失真
(DPD) 观测接收器。
• 最大采样率:1GSPS
• 最大输出采样率:500MSPS
• 具有高阻抗输入的模拟输入缓冲器
• 3dB 输入带宽:1GHz
• 输出选项:
– Rx:低通滤波器具有
2 倍抽取率和4 倍抽取率两个选项
– 支持200MHz 复带宽或100MHz 实带宽
– DPD FB:2 倍抽取率,14 位突发模式输出
• 1.1 VPP 差分满量程输入
• JESD204B 接口:
JESD204B 接口减少了接口线路数,从而提升系统集
成度。内部锁相环 (PLL) 会将传入的模数转换器
(ADC) 采样时钟加倍,以获得串行化各通道的 14 位数
据时使用的位时钟。
– 支持子类1
– 每个ADC 一条信道,速率高达10Gsps
– 专用于通道对的SYNC 引脚
• 支持多芯片同步
• 72 引脚超薄型四方扁平无引线(VQFN) 封装
(10mm × 10mm)
器件信息(1)
封装尺寸(标称值)
器件型号
ADS58J64
封装
• 功率耗散:625 mW/通道
• 频谱性能
VQFN (72)
10.00mm x 10.00mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
(突发模式,高分辨率):
– fIN = 190MHz 中频(IF)(–1dBFS 时):
2x Decimation
High Pass/
Low Pass
N
14-bit
ADC
• SNR:69dBFS
• NSD:-153dBFS/Hz
• SFDR:86dBc(HD2,HD3),
95dBFS(非HD2,HD3)
– fIN = 370 MHz IF(–3dBFS 时):
INAP, INAM
INBP. INAM
DAP, DAM
NCO
JESD204B
14-bit
ADC
2x Decimation
High Pass/
Low Pass
DBP, DBM
TRIGAB
Burst Mode
TRIGCD
TRDYAB
TRDYCD
SYSREFP, SYSREFM
CLKINP, CLKINM
• SNR:68.5dBFS
CLK
DIV
/2, /4
PLL
x10/x20
SYNCbAB
SYNCbCD
• NSD:-152.5dBFS/Hz
• SFDR:80dBc(HD2,HD3),
86dBFS(非HD2,HD3)
2x Decimation
High Pass/
Low Pass
Burst Mode
N
14-bit
ADC
INCP, INCM
INDP, INDM
DCP, DCM
DDP, DDM
JESD204B
NCO
2x Decimation
High Pass/
Low Pass
14-bit
ADC
2 应用
Configuration
Registers
• 多载波GSM 蜂窝基础设施基站
• 多载波多模蜂窝基础设施基站
• 电信接收器
• 电信数字预失真(DPD) 观测接收器
简化版方框图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SBAS807
ADS58J64
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ZHCSFY7B –JANUARY 2017 –REVISED DECEMBER 2021
Table of Contents
7.3 Feature Description...................................................22
7.4 Device Functional Modes..........................................23
7.5 Programming............................................................ 33
7.6 Register Maps...........................................................40
8 Application and Implementation..................................67
8.1 Application Information............................................. 67
8.2 Typical Application.................................................... 74
9 Power Supply Recommendations................................75
10 Layout...........................................................................76
10.1 Layout Guidelines................................................... 76
10.2 Layout Example...................................................... 76
11 Device and Documentation Support..........................77
11.1 接收文档更新通知................................................... 77
11.2 支持资源..................................................................77
11.3 Trademarks............................................................. 77
11.4 Electrostatic Discharge Caution..............................77
11.5 术语表..................................................................... 77
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................7
6.6 AC Performance......................................................... 8
6.7 Digital Characteristics............................................... 11
6.8 Timing Characteristics...............................................12
6.9 Typical Characteristics: 14-Bit Burst Mode............... 13
6.10 Typical Characteristics: Mode 2..............................19
6.11 Typical Characteristics: Mode 0.............................. 20
7 Detailed Description......................................................21
7.1 Overview...................................................................21
7.2 Functional Block Diagram.........................................21
Information.................................................................... 78
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision A (January 2017) to Revision B (December 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Added RHH (VQFN) package option..................................................................................................................3
• Changed description for GAINWORD ............................................................................................................. 63
• Added the text Also need to enable OVR_ON_LSB bit in DIGTOP page to register 3 and 1 of Register 27h in
CHX page......................................................................................................................................................... 63
Changes from Revision * (January 2017) to Revision A (January 2017)
Page
• 在第三个特性要点中将动词采样更改为名词采样............................................................................................. 1
• 将带宽:250MHz 更改为采样率500MSPS(在第四个特性要点中)................................................................1
• 向特性部分添加了3dB 输入带宽要点...............................................................................................................1
• Changed plot and SNR and SFDR conditions of Figure 9 ...............................................................................13
• Added for loading trims to description of bit 1 in Register 64h Field Descriptions ...........................................45
• Changed select to set in description of bits 7-0 in Register 8Dh Field Descriptions and Register 8Eh Field
Descriptions .....................................................................................................................................................45
• Changed select to set in description of bits 7-0 in Register 8Fh Field Descriptions and Register 90h Field
Descriptions .....................................................................................................................................................46
• Added Others: Do not use to Description column of Register 71h Field Descriptions and Register 72h Field
Descriptions .....................................................................................................................................................50
• Changed Others: Do not use to Description column of Register 93h Field Descriptions and Register 94h Field
Descriptions .....................................................................................................................................................51
• Added Valid only when CTRL_LID = 1 to description of bits 7-4 in Register 2Dh Field Descriptions ..............58
• Changed Description column of Register 41h Field Descriptions ....................................................................62
• Changed 1 : to 3 : and added Others: Do not use to Description column of Register 42h Field Descriptions ....
62
• Changed description of bits 7-0 in Register 07h Field Descriptions ................................................................ 66
• Changed description of bits 7-0 in Register 08h Field Descriptions ................................................................ 66
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5 Pin Configuration and Functions
TRDYCD
TRIGCD
DGND
DVDD
SDIN
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
TRDYAB
TRIGAB
DGND
DVDD
PDN
2
3
4
5
SCLK
6
RES
SEN
7
RESET
DVDD
AVDD
AVDD19
AVDD
AVDD
INAP
DVDD
AVDD
AVDD19
SDOUT
AVDD
INDP
8
9
Thermal
Pad
10
11
12
13
14
15
16
17
18
INDM
INAM
AVDD
AVDD19
AVDD
INCM
AVDD
AVDD19
AVDD
INBM
Not to scale
图5-1. RMP or RHH Package 72-Pin VQFN Top View
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
INPUT, REFERENCE
INAM
INAP
INBM
INBP
INCM
INCP
41
42
37
36
18
19
I
I
I
Differential analog input pin for channel A, internal bias via a 2-kΩresistor to VCM
Differential analog input pin for channel B, internal bias via a 2-kΩresistor to VCM
Differential analog input pin for channel C, internal bias via a 2-kΩresistor to VCM
INPUT, REFERENCE (continued)
INDM
14
13
I
Differential analog input pin for channel D, internal bias via a 2-kΩresistor to VCM
INDP
CLOCK, SYNC
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表5-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
CLKINM
NO.
28
I
I
Differential clock input pin for the ADC with internal 100-Ωdifferential termination, requires external ac coupling
CLKINP
27
SYSREFM
SYSREFP
34
External SYSREF input, requires dc coupling and external termination
33
CONTROL, SERIAL
NC
22, 23
50
No connection
—
Power down. This pin can be configured via an SPI register setting. This pin has an internal 10-kΩpulldown
resistor.
PDN
I/O
RES
49
48
6
Reserved pin, connect to GND
—
RESET
SCLK
SDIN
I
Hardware reset; active high. This pin has an internal 10-kΩpulldown resistor.
Serial interface clock input. This pin has an internal 10-kΩpulldown resistor.
Serial interface data input. This pin has an internal 10-kΩpulldown resistor.
1.8-V logic serial interface data output
I
I
5
SDOUT
SEN
11
7
O
I
Serial interface enable. This pin has an internal 10-kΩpullup resistor to DVDD.
Trigger-ready output for burst mode for channels A and B. This pin can be configured via SPI to a TRDY signal for
all four channels in burst mode, and can be left open if not used.
TRDYAB
TRDYCD
54
1
O
O
Trigger-ready output for burst mode for channels C and D. This pin can be configured via SPI to a TRDY signal for
all four channels in burst mode, and can be left open if not used.
Manual burst mode trigger input for channels A and B. This pin can be configured via SPI to a manual trigger input
signal for all four channels in burst mode, and can be connected to GND if not used. This pin has an internal 10-
kΩpulldown resistor.
TRIGAB
TRIGCD
53
2
I
I
Manual burst mode trigger input for channels C and D. This pin can be configured via SPI to a manual trigger input
signal for all four channels in burst mode, and can be connected to GND if not used. This pin has an internal 10-
kΩpulldown resistor.
DATA INTERFACE
DAM
59
58
62
61
65
66
68
69
56
55
71
72
O
O
O
O
I
JESD204B serial data output pin for channel A
JESD204B serial data output pin for channel B
JESD204B serial data output pin for channel C
JESD204B serial data output pin for channel D
DAP
DBM
DBP
DCM
DCP
DDM
DDP
SYNCbABM
SYNCbABP
SYNCbCDM
SYNCbCDP
POWER SUPPLY
Synchronization input pin for JESD204B port channels A and B. This pin can be configured via SPI to a SYNCb
signal for all four channels. This pin has an internal differential termination of 100 Ω.
Synchronization input pin for JESD204B port channels C and D. This pin can be configured via SPI to a SYNCb
signal for all four channels. This pin has an internal differential termination of 100 Ω..
I
AGND
21, 26, 29, 32
I
I
Analog ground
9, 12, 15, 17, 20,
25, 30, 35, 38,
40, 43, 44, 46
AVDD
Analog 1.15-V power supply
10, 16, 24, 31,
39, 45
AVDD19
DGND
I
I
Analog 1.9-V supply for analog buffer
Digital ground
3, 52, 60, 63, 67
4, 8, 47,51, 57,
64, 70
DVDD
I
Digital 1.15-V power supply
Connect to GND
Thermal pad
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
AVDD19
2.1
1.4
–0.3
–0.3
–0.3
–0.2
–0.3
–0.3
–0.3
–0.3
AVDD
Supply voltage
DVDD
1.4
IOVDD
Voltage between AGND and DGND
INAP, INBP, INAM, INBM, INCP, INDP, INCM, INDM
CLKINP, CLKINM
1.4
0.3
V
2.1
AVDD + 0.3
AVDD + 0.3
Voltage applied to input pins
V
SYSREFP, SYSREFM, TRIGAB, TRIGCD
SCLK, SEN, SDIN, RESET, SYNCbABP,
SYNCbABM, SYNCbCDP, SYNCbCDM, PDN
AVDD19 + 0.3
150
–0.2
–65
Storage temperature, Tstg
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.8
1.1
1.1
1.1
NOM
1.9
MAX
UNIT
AVDD19
2
1.2
1.2
1.2
AVDD
Supply voltage range
DVDD
1.15
1.15
1.15
1.1
V
IOVDD
Differential input voltage range
Analog inputs
VPP
V
Input common-mode voltage (VCM)
1.3
Input clock frequency, device clock frequency
400
1000
MHz
VPP
Input clock amplitude differential
(VCLKP –VCLKM
Sine wave, ac-coupled
1.5
1.6
)
Clock inputs
Temperature
LVPECL, ac-coupled
LVDS, ac-coupled
0.7
Input device clock duty cycle, default after reset
Operating free-air, TA
45%
50%
55%
100(3)
125(1)
–40
Operating junction, TJ
105
°C
Specified maximum, measured at the device footprint thermal pad
on the printed circuit board, TP-MAX
104.5(2)
(1) Prolonged use above this junction temperature can increase the device failure-in-time (FIT) rate.
(2) The recommended maximum temperature at the PCB footprint thermal pad assumes the junction-to-package bottom thermal
resistance, RθJC(bot) = 0.2°C/W, the thermal resistance of the device thermal pad connection to the PCB footprint is negligible, and the
device power consumption is 2.5 W.
(3) Assumes system thermal design meets the TJ specification.
6.4 Thermal Information
ADS58J64
THERMAL METRIC(1)
RMP (VQFNP)
72 PINS
RHH (VQFN)
72 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance (2)
Junction-to-case (top) thermal resistance (3)
Junction-to-board thermal resistance (3)
22.3
5.1
2.4
0.1
2.3
0.2
18.1
5.8
4.5
0.2
4.4
0.3
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-top characterization parameter (4)
Junction-to-board characterization parameter (5)
Junction-to-case (bottom) thermal resistance (6)
ψJT
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board,
as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is
extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
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6.5 Electrical Characteristics
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +100°C, input clock frequency =
1 GHz, mode 8: 2x decimation with burst mode output, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –1-
dBFS differential input, and fIN = 190 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
GENERAL
ADC sampling rate
Resolution
1
GSPS
Bits
14
POWER SUPPLY
AVDD19 1.9-V analog supply
1.85
1.1
1.9
1.15
1.15
618
415
1.95
1.2
V
V
AVDD
DVDD
IAVDD19
IAVDD
1.15-V analog supply
1.15-V digital supply
1.1
1.2
V
1.9-V analog supply current
1.15-V analog supply current
100-MHz, full-scale input on all four channels
100-MHz, full-scale input on all four channels
mA
mA
Mode 8, 100 MHz, full-scale input on all four
channels
629
730
674
703
2.37
2.49
2.42
2.46
120
Mode 3, 100 MHz, full-scale input on all four
channels
IDVDD
1.15-V digital supply current
mA
Mode 0 and 2, 100 MHz, full-scale input on all four
channels
Mode 1, 4, 6, and 7, 100 MHz, full-scale input on
all four channels
Mode 8, 100 MHz, full-scale input on all four
channels
Mode 3, 100 MHz, full-scale input on all four
channels
Pdis
Total power dissipation
W
Mode 0 and 2, 100 MHz, full-scale input on all four
channels
Mode 1, 4, 6, and 7, 100 MHz, full-scale input on
all four channels
Global power-down power
dissipation
Full-scale input on all four channels
mW
VPP
ANALOG INPUTS
Differential input full-scale
1.1
voltage
Input common-mode voltage
Differential input resistance
Differential input capacitance
Analog input bandwidth (3 dB)
1.3
4
V
At fIN = dc
kΩ
pF
2.5
1000
MHz
ISOLATION
fIN = 10 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 270 MHz
fIN = 370 MHz
fIN = 470 MHz
75
75
74
72
71
70
Crosstalk(1) isolation between
near channels
(channels A and B are near to
each other, channels C and D
are near to each other)
dBFS
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typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +100°C, input clock frequency =
1 GHz, mode 8: 2x decimation with burst mode output, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –1-
dBFS differential input, and fIN = 190 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
110
110
110
110
110
110
MAX UNIT
fIN = 10 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 270 MHz
fIN = 370 MHz
fIN = 470 MHz
Crosstalk(1) isolation between
far channels
(channels A and B are far from
channels C and D)
dBFS
CLOCK INPUT
Internal clock biasing
CLKINP and CLKINM pins are connected to the
internal biasing voltage through a 5-kΩresistor
0.7
V
(1) Crosstalk is measured with a –1-dBFS input signal on aggressor channel and no input on the victim channel.
6.6 AC Performance
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +100°C, input clock frequency =
1 GHz, mode 8: 2x decimation with burst mode output, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –1-
dBFS differential input, and fIN = 190 MHz (unless otherwise noted)
MIN
TYP
MAX
MIN
TYP
MAX
PARAMETER
TEST CONDITIONS
UNIT
14-BIT BURST MODE
(DDC Mode 8)
DECIMATE-BY-4
(DDC Mode 2)
69.9
69.6
69.2
72.2
71.8
71.8
71
fIN = 10 MHz, AIN = –1 dBFS
fIN = 70 MHz, AIN = –1 dBFS
fIN = 190 MHz, AIN = –1 dBFS
fIN = 190 MHz, AIN = –3 dBFS
fIN = 300 MHz, AIN = –3 dBFS
fIN = 370 MHz, AIN = –3 dBFS
fIN = 470 MHz, AIN = –3 dBFS
fIN = 10 MHz, AIN = –1 dBFS
fIN = 70 MHz, AIN = –1 dBFS
fIN = 190 MHz, AIN = –1 dBFS
fIN = 190 MHz, AIN = –3 dBFS
fIN = 300 MHz, AIN = –3 dBFS
fIN = 370 MHz, AIN = –3 dBFS
fIN = 470 MHz, AIN = –3 dBFS
fIN = 10 MHz, AIN = –1 dBFS
fIN = 70 MHz, AIN = –1 dBFS
fIN = 190 MHz, AIN = –1 dBFS
fIN = 190 MHz, AIN = –3 dBFS
fIN = 300 MHz, AIN = –3 dBFS
66.5
69.6
69.3
SNR
Signal-to-noise ratio
dBFS
71.7
71.3
69.8
68.7
68.4
–153.9
–153.6
–153.2
–153.2
–152.8
–152.7
–153.2
–152.7
–152.2
–151
83
NSD
Noise spectral density
dBFS/Hz
–150.5 –153.6
–152.8
–152.5
–151.5
83
81
100
87
100
78
88
79
82
98
Spurious-free dynamic
range
SFDR(1)
dBc
98
70
fIN = 370 MHz, AIN = –3 dBFS,
input clock frequency = 983.04 MHz
78
76
fIN = 470 MHz, AIN = –3 dBFS
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typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +100°C, input clock frequency =
1 GHz, mode 8: 2x decimation with burst mode output, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –1-
dBFS differential input, and fIN = 190 MHz (unless otherwise noted)
MIN
TYP
MAX
MIN
TYP
MAX
PARAMETER
TEST CONDITIONS
UNIT
14-BIT BURST MODE
(DDC Mode 8)
DECIMATE-BY-4
(DDC Mode 2)
68.5
68.5
68.2
68.5
68.9
68
70.6
70.6
72.2
73
fIN = 10 MHz, AIN = –1 dBFS
fIN = 70 MHz, AIN = –1 dBFS
fIN = 190 MHz, AIN = –1 dBFS
fIN = 190 MHz, AIN = –3 dBFS
fIN = 300 MHz, AIN = –3 dBFS
fIN = 370 MHz, AIN = –3 dBFS
fIN = 470 MHz, AIN = –3 dBFS
Signal-to-noise and
distortion ratio
SINAD
dBFS
72.3
68.2
69
68
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typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +100°C, input clock frequency =
1 GHz, mode 8: 2x decimation with burst mode output, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –1-
dBFS differential input, and fIN = 190 MHz (unless otherwise noted)
MIN
TYP
MAX
MIN
TYP
MAX
PARAMETER
TEST CONDITIONS
UNIT
14-BIT BURST MODE
(DDC Mode 8)
DECIMATE-BY-4
(DDC Mode 2)
fIN = 10 MHz, AIN = –1 dBFS
fIN = 70 MHz, AIN = –1 dBFS
fIN = 190 MHz, AIN = –1 dBFS
fIN = 190 MHz, AIN = –3 dBFS
fIN = 300 MHz, AIN = –3 dBFS
–83
–82
–85
–90
–100
–98
Second-order harmonic
distortion
–78
–86
–82
–82
–100
–100
–69
HD2(1)
dBc
fIN = 370 MHz, AIN = –3 dBFS
input clock frequency = 983.04 MHz
fIN = 470 MHz, AIN = –3 dBFS
fIN = 10 MHz, AIN = –1 dBFS
fIN = 70 MHz, AIN = –1 dBFS
fIN = 190 MHz, AIN = –1 dBFS
fIN = 190 MHz, AIN = –3 dBFS
fIN = 300 MHz, AIN = –3 dBFS
fIN = 370 MHz, AIN = –3 dBFS
fIN = 470 MHz, AIN = –3 dBFS
fIN = 10 MHz, AIN = –1 dBFS
fIN = 70 MHz, AIN = –1 dBFS
fIN = 190 MHz, AIN = –1 dBFS
fIN = 190 MHz, AIN = –3 dBFS
fIN = 300 MHz, AIN = –3 dBFS
fIN = 370 MHz, AIN = –3 dBFS
fIN = 470 MHz, AIN = –3 dBFS
fIN = 10 MHz, AIN = –1 dBFS
fIN = 70 MHz, AIN = –1 dBFS
fIN = 190 MHz, AIN = –1 dBFS
fIN = 190 MHz, AIN = –3 dBFS
fIN = 300 MHz, AIN = –3 dBFS
fIN = 370 MHz, AIN = –3 dBFS
fIN = 470 MHz, AIN = –3 dBFS
–100
–83
–81
–92
–92
–90
–90
–80
95
–94
–85
–100
–100
–100
–100
–100
–79
Third-order harmonic
distortion
HD3(1)
dBc
–78
–100
–92
95
95
–100
–98
Spurious-free dynamic
range (excluding HD2,
HD3)
Non
HD2, HD3
87
95
dBFS
95
–100
–100
–100
–83
95
93
–81
–79
–83
–85
–81
–76
–82
–90
–100
–100
–100
–100
–68
THD(1)
Total harmonic distortion
dBc
–80
f1 = 185 MHz, f2 = 190 MHz,
–87
AIN = –10 dBFS
f1 = 365 MHz, f2 = 370 MHz,
AIN = –10 dBFS
Two-tone, third-order
intermodulation distortion
–90
–85
–94
–85
IMD3
dBFS
f1 = 465 MHz, f2 = 470 MHz,
AIN = –10 dBFS
(1) Harmonic distortion performance can be significantly improved by using the frequency planning explained in the 节8.1.3 section.
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6.7 Digital Characteristics
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +100°C, input clock frequency =
1 GHz, mode 8: 2x decimation with burst mode output, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –1-
dBFS differential input, and fIN = 190 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, PDN, TRIGAB, TRIGCD)(1)
VIH
VIL
High-level input voltage
Low-level input voltage
All digital inputs support 1.2-V and 1.8-V logic levels
All digital inputs support 1.2-V and 1.8-V logic levels
SEN
0.8
V
V
0.4
0
50
50
0
IIH
High-level input current
µA
RESET, SCLK, SDIN, PDN, TRIGAB, TRIGCD
SEN
IIL
Low-level input current
Input capacitance
µA
pF
RESET, SCLK, SDIN, PDN, TRIGAB, TRIGCD
4
DIGITAL INPUTS
SYSREFP, SYSREFM
0.35
0.35
0.9
0.45
0.55
1.3
VD
Differential input voltage
V
V
SYNCbABM, SYNCbABP, SYNCbCDM,
SYNCbCDP
SYSREFP, SYSREFM
1.2
1.2
1.4
V(CM_DIG)
Common-mode voltage for SYSREF
SYNCbABM, SYNCbABP, SYNCbCDM,
SYNCbCDP
DIGITAL OUTPUTS (SDOUT, TRDYAB, TRDYCD)
VOH
High-level output voltage
100-µA current
100-µA current
V
V
AVDD19 –0.2
VOL
Low-level output voltage
0.2
DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM)(2)
VOD
VOC
Output differential voltage
With default swing setting
700
450
mVPP
mV
Output common-mode voltage
Transmitter pins shorted to any voltage between –
0.25 V and 1.45 V
Transmitter short-circuit current
Single-ended output impedance
Output capacitance
100
mA
–100
zos
50
2
Ω
Output capacitance inside the device,
from either output to ground
pF
(1) The RESET, SCLK, SDIN, and PDN pins have a 20-kΩ(typical) internal pulldown resistor to ground, and the SEN pin has a 20-kΩ
(typical) pullup resistor to IOVDD.
(2) 50-Ω, single-ended external termination to IOVDD.
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6.8 Timing Characteristics
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +100°C, input clock frequency =
1 GHz, mode 8: 2x decimation with burst mode output, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –1-
dBFS differential input, and fIN = 190 MHz (unless otherwise noted)
MIN
TYP
MAX
UNITS
SAMPLE TIMING CHARACTERISTICS
Aperture delay
0.55
0.92
ns
ps
Aperture delay matching between two channels on the same device
±100
±100
Aperture delay matching between two devices at the same temperature and supply
voltage
ps
Aperture jitter
100
10
fS rms
ms
Global power-down
Wake-up time
Pin power-down (fast power-down)
5
µs
Data latency: ADC
sample to digital
output
Burst mode
116
Input clock
cycles
DDC mode 0
204
tSU_SYSREF Setup time for SYSREF, referenced to input clock rising edge
tH_SYSREF Hold time for SYSREF, referenced to input clock rising edge
JESD OUTPUT INTERFACE TIMING CHARACTERISTICS
Unit interval
350
100
900
10
ps
ps
100
ps
Gbps
ps
Serial output data rate
Total jitter for BER of 1E-15 and lane rate = 10 Gbps
Random jitter for BER of 1E-15 and lane rate = 10 Gbps
Deterministic jitter for BER of 1E-15 and lane rate = 10 Gbps
24
0.95
8.8
ps rms
ps, pk-pk
Data rise time, data fall time: rise and fall times measured from 20% to 80%,
differential output waveform, 2.5 Gbps ≤bit rate ≤10 Gbps
tR, tF
35
ps
N+1
N+2
N
Sample
tPD
Data Latency: 116 Clock Cycles
CLKINP
CLKINM
DAP, DAM
DBP, DBM
DCP, DCM
DDP, DDM
D20
D1
D20
Sample N-1
Sample N
Sample N+1
图6-1. Latency Timing Diagram in Burst Mode
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6.9 Typical Characteristics: 14-Bit Burst Mode
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +100°C, device sampling frequency =
1 GSPS, mode 8: 2x decimation with burst mode output, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –
1-dBFS differential input, and fIN = 190 MHz (unless otherwise noted)
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
50
100
150
200
250
0
50
100 150
Input Frequency (MHz)
200
250
Input Frequency (MHz)
D001
D002
fIN = 100 MHz, AIN = –1 dBFS, SNR = 69.57 dBFS, SFDR =
fIN = 190 MHz, AIN = –1 dBFS, SNR = 69.23 dBFS, SFDR =
85.23 dBc, SFDR = 102.09 dBc (non 23)
86.83 dBc, SFDR = 91.23 dBc (non 23)
图6-2. FFT for 100-MHz Input Signal
图6-3. FFT for 190-MHz Input Signal
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
50
100 150
Input Frequency (MHz)
200
250
0
50
100 150
Input Frequency (MHz)
200
250
D003
D004
fIN = 190 MHz, AIN = –3 dBFS, SNR = 69.60 dBFS, SFDR =
fIN = 190 MHz, AIN = –10 dBFS, SNR = 70.05 dBFS, SFDR =
88.45 dBc, SFDR = 99.78 dBc (non 23)
93.27 dBc, SFDR = 97.26 dBc (non 23)
图6-4. FFT for 190-MHz Input Signal
图6-5. FFT for 190-MHz Input Signal
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
50
100 150
Input Frequency (MHz)
200
250
0
50
100 150
Input Frequency (dBFS)
200
250
D005
D006
fIN = 190 MHz, AIN = –20 dBFS, SNR = 70.23 dBFS, SFDR =
fIN = 230 MHz, AIN = –1 dBFS, SNR = 69.17 dBFS, SFDR =
81.71 dBc, SFDR = 81.71 dBc (non 23)
85.29 dBc, SFDR = 89.30 dBc (non 23)
图6-6. FFT for 190-MHz Input Signal
图6-7. FFT for 230-MHz Input Signal
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6.9 Typical Characteristics: 14-Bit Burst Mode (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +100°C, device sampling frequency =
1 GSPS, mode 8: 2x decimation with burst mode output, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –
1-dBFS differential input, and fIN = 190 MHz (unless otherwise noted)
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
50
100 150
Input Frequency (MHz)
200
250
0
50
100 150
Input Frequency (MHz)
200
250
D007
D008
fIN = 270 MHz, AIN = –3 dBFS, SNR = 69.27 dBFS, SFDR =
fIN = 370 MHz, AIN = –3 dBFS, SNR = 68.36 dBFS, SFDR =
82.98 dBc, SFDR = 95.4 dBc (non 23)
81.37 dBc, SFDR = 97.28 dBc (non 23)
图6-8. FFT for 270-MHz Input Signal
图6-9. FFT for 370-MHz Input Signal
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
50
100 150
Input Frequency (MHz)
200
250
0
50
100 150
Input Frequency (MHz)
200
250
D009
D010
fIN1 = 160 MHz, fIN2 = 170 MHz, IMD = 102.68 dBFS, each
fIN = 470 MHz, AIN = –3 dBFS, SNR = 68.21 dBFS, SFDR =
79.85 dBc, SFDR = 99.12 dBc (non 23)
tone at –7 dBFS
图6-10. FFT for 470-MHz Input Signal
图6-11. FFT for Two-Tone Input Signal
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
50
100
150
200
250
0
50
100 150
Input Frequency (MHz)
200
250
Input Frequency (MHz)
D011
D012
fIN1 = 160 MHz, fIN2 = 170 MHz, IMD = 103.44 dBFS, each
fIN1 = 340 MHz, fIN2 = 350 MHz, IMD = 84.34 dBFS, each tone
tone at –10 dBFS
at –7 dBFS
图6-12. FFT for Two-Tone Input Signal
图6-13. FFT for Two-Tone Input Signal
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6.9 Typical Characteristics: 14-Bit Burst Mode (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +100°C, device sampling frequency =
1 GSPS, mode 8: 2x decimation with burst mode output, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –
1-dBFS differential input, and fIN = 190 MHz (unless otherwise noted)
0
-20
70.5
70
AIN = -3 dBFS
AIN = -1 dBFS
-40
69.5
69
-60
68.5
68
-80
-100
-120
-140
67.5
67
0
50
100
150
200
250
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
Input Frequency (MHz)
D014
D013
图6-15. SNR vs Input Frequency
fIN1 = 340 MHz, fIN2 = 350 MHz, IMD = 95.08 dBFS, each tone
at –10 dBFS
图6-14. FFT for Two-Tone Input Signal
102
98
96
94
92
90
88
86
84
82
80
78
76
74
AIN = -3 dBFS
AIN = -1 dBFS
96
90
84
78
72
AIN = -3 dBFS
AIN = -1 dBFS
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
D015
D016
图6-16. HD3 vs Input Frequency
图6-17. HD2 vs Input Frequency
71
70.5
70
106
100
94
Temperature = -40 èC
Temperature = 25 èC
Temperature = 105 èC
Temperature = -40 èC
Temperature = 25 èC
Temperature = 105 èC
69.5
69
88
68.5
68
82
67.5
76
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
D017
D018
图6-18. SNR vs Input Frequency and Temperature
图6-19. HD3 vs Input Frequency and Temperature
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6.9 Typical Characteristics: 14-Bit Burst Mode (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +100°C, device sampling frequency =
1 GSPS, mode 8: 2x decimation with burst mode output, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –
1-dBFS differential input, and fIN = 190 MHz (unless otherwise noted)
110
102
94
70.5
Temperature = -40 èC
Temperature = 25 èC
Temperature = 105 èC
AVDD19 = 1.8 V
AVDD19 = 1.9 V
AVDD19 = 2 V
70
69.5
69
86
78
68.5
68
70
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
D019
D020
图6-20. HD2 vs Input Frequency and Temperature
图6-21. SNR vs Input Frequency and AVDD19 Supply
100
70.5
AVDD19 = 1.8 V
AVDD19 = 1.9 V
AVDD19 = 2 V
AVDD = 1.1 V
AVDD = 1.15 V
AVDD = 1.2 V
95
70
90
85
80
75
69.5
69
68.5
68
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
D021
D022
图6-22. HD3 vs Input Frequency and AVDD19 Supply
图6-23. SNR vs Input Frequency and AVDD Supply
105
70.2
AVDD = 1.1 V
AVDD = 1.15 V
AVDD = 1.2 V
DVDD = 1.1 V
DVDD = 1.15 V
DVDD = 1.2 V
70
99
69.8
69.6
69.4
69.2
69
93
87
81
75
68.8
68.6
68.4
68.2
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
D023
D024
图6-24. HD3 vs Input Frequency and AVDD Supply
图6-25. SNR vs Input Frequency and DVDD Supply
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6.9 Typical Characteristics: 14-Bit Burst Mode (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +100°C, device sampling frequency =
1 GSPS, mode 8: 2x decimation with burst mode output, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –
1-dBFS differential input, and fIN = 190 MHz (unless otherwise noted)
100
95
90
85
80
75
71.5
150
120
90
60
30
0
DVDD = 1.1 V
DVDD = 1.15 V
DVDD = 1.2 V
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
71
70.5
70
69.5
69
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
-70
-60
-50
-40 -30
Amplitude (dBFS)
-20
-10
0
D025
D026
图6-26. HD3 vs Input Frequency and DVDD Supply
fIN = 190 MHz
图6-27. Performance vs Input Signal Amplitude
72.5
150
-80
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
71.5
70.5
69.5
68.5
67.5
120
90
60
30
0
-88
-96
-104
-112
-120
-70
-60
-50
-40 -30
Amplitude (dBFS)
-20
-10
0
-35
-31
-27
Each Tone Amplitude (dBFS)
-23
-19
-15
-11
-7
D027
D028
fIN = 370 MHz
fIN1 = 160 MHz, fIN2 = 170 MHz
图6-28. Performance vs Input Signal Amplitude
图6-29. IMD vs Input Amplitude
-80
0
-20
-40
-88
-96
-60
-80
-104
-112
-120
-100
-120
-140
0
50
100
150
200
250
-35
-31
-27
-23
-19
-15
Intermodulation Distortion (dBFS)
-11
-7
Input Frequency (MHz)
D029
D030
fIN1 = 340 MHz, fIN2 = 350 MHz
fIN = 190 MHz, AIN = –1 dBFS, fNoise = 5 MHz, ANoise = 50
mVPP, SFDR = 73.5 dBFS
图6-30. IMD vs Input Amplitude
图6-31. Power-Supply Rejection Ratio FFT for 50-mV Noise on
AVDD Supply
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6.9 Typical Characteristics: 14-Bit Burst Mode (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +100°C, device sampling frequency =
1 GSPS, mode 8: 2x decimation with burst mode output, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –
1-dBFS differential input, and fIN = 190 MHz (unless otherwise noted)
-10
-20
-30
-40
-50
-60
0
-20
PSRR with 50-mVPP Signal on AVDD
PSRR with 50-mVPP Signal on AVDD19
-40
-60
-80
-100
-120
-140
0
50
100
150
200
250
0
10
20
30
40
Frequency of Signal on Supply (MHz)
50
60
Input Frequency (MHz)
D031
D032
fIN = 190 MHz, AIN = –1 dBFS, fNoise = 5 MHz, ANoise = 50
fIN = 190 MHz, AIN = –1 dBFS, fNoise = 5 MHz, ANoise = 50
mVPP
mVPP, SFDR = 63.12 dBFS
图6-32. PSRR vs Power Supplies
图6-33. Common-Mode Rejection Ratio FFT
-15
4
AVDD19_Power (W)
AVDD_Power (W)
DVDD_Power (W)
-25
-35
-45
-55
-65
3.2
Total Power (W)
2.4
1.6
0.8
0
0
20
40
60
Frequency of Input Common-Mode Signal (MHz)
80
100
250
300
350 400
Sampling Speed (MSPS)
450
500
D033
D034
图6-35. Power Consumption vs Input Clock Rate
fIN = 190 MHz, AIN = –1 dBFS, fNoise = 5 MHz, ANoise = 50
mVPP
图6-34. CMRR vs Noise Frequency
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6.10 Typical Characteristics: Mode 2
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +100°C, device sampling frequency =
1 GSPS, mode 8: 2x decimation with burst mode output, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –
1-dBFS differential input, and fIN = 190 MHz (unless otherwise noted)
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
25
50
75
100
125
0
25
50
75
100
125
Input Frequency (MHz)
Input Frequency (MHz)
D036
D035
fIN = 190 MHz, AIN= –1 dBFS, SNR = 72.37 dBFS, SFDR =
fIN = 150 MHz, AIN= –1 dBFS, SNR = 72.85 dBFS, SFDR =
99.95 dBc, SFDR = 100.76 dBc (non 23)
84.41 dBc, SFDR = 100.99 dBc (non 23)
图6-37. FFT for 190-MHz Input Signal
图6-36. FFT for 150-MHz Input Signal
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
25
50
75
100
125
0
25
50
75
100
125
Input Frequency (MHz)
Input Frequency (MHz)
D037
D038
fIN = 300 MHz, AIN= –3 dBFS, SNR = 72.3 dBFS, SFDR =
fIN = 350 MHz, AIN= –3 dBFS, SNR = 72.02 dBFS, SFDR =
100.31 dBc, SFDR = 100.75 dBc (non 23)
79.23 dBc, SFDR = 96.42 dBc (non 23)
图6-38. FFT for 300-MHz Input Signal
图6-39. FFT for 350-MHz Input Signal
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6.11 Typical Characteristics: Mode 0
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +85°C, device sampling frequency =
1 GSPS, mode 8: 2x decimation with burst mode output, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –
1-dBFS differential input, and fIN = 190 MHz (unless otherwise noted)
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
-125
-75
-25
25
75
125
-125
-75
-25
25
75
125
Input Frequency (MHz)
Input Frequency (MHz)
D039
D040
fIN = 100 MHz, AIN= –1 dBFS, SNR = 70.16 dBFS, SFDR =
fIN = 170 MHz, AIN= –1 dBFS, SNR = 69.35 dBFS, SFDR =
84.95 dBc, SFDR = 95.41 dBc (non 23)
86.46 dBc, SFDR = 89.27 dBc (non 23)
图6-40. FFT for 100-MHz Input Signal
图6-41. FFT for 170-MHz Input Signal
0
-20
-40
-60
-80
-100
-120
-140
-125
-75
-25
25
75
125
Input Frequency (MHz)
D041
fIN = 220 MHz, AIN= –1 dBFS, SNR = 69.27 dBFS, SFDR = 87.66 dBc, SFDR = 91.04 dBc (non 23)
图6-42. FFT for 220-MHz Input Signal
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7 Detailed Description
7.1 Overview
The ADS58J64 is a quad-channel device with a complex digital down-converter (DDC) and digital decimation to
allow flexible signal processing to suit different usage cases. Each channel is composed of two interleaved
analog-to-digital converters (ADCs) sampling at half the input clock rate. The 2x interleaved data are decimated
by 2 to provide a processing gain of 3 dB. The decimation filter can be configured as low pass (default) or high
pass. The half-rate (with regards to the input clock) data are available on the output, in burst mode (DDC mode =
8) as a stream of high (14-bit) and low (9-bit) resolution samples. Burst mode can be enabled by device
programming along with other options (such as the number of high- and low-resolution samples, and trigger
mode as either automatic or pin-controlled). In default mode, the device operates in DDC mode 0, where the
input is mixed with a constant frequency of –fS / 4 and is given out as complex IQ. The different operational
modes modes of the ADS58J64 are listed in 表7-1.
7.2 Functional Block Diagram
2x Decimation
High Pass/
Low Pass
N
14-bit
ADC
INAP, INAM
INBP. INAM
DAP, DAM
NCO
JESD204B
2x Decimation
High Pass/
Low Pass
14-bit
ADC
DBP, DBM
TRIGAB
Burst Mode
TRIGCD
TRDYAB
TRDYCD
SYSREFP, SYSREFM
CLKINP, CLKINM
CLK
DIV
/2, /4
PLL
x10/x20
SYNCbAB
SYNCbCD
2x Decimation
High Pass/
Low Pass
Burst Mode
N
14-bit
ADC
INCP, INCM
INDP, INDM
DCP, DCM
DDP, DDM
JESD204B
NCO
2x Decimation
High Pass/
Low Pass
14-bit
ADC
Configuration
Registers
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7.3 Feature Description
7.3.1 Analog Inputs
The ADS58J64 analog signal inputs are designed to be driven differentially. The analog input pins have internal
analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high-
impedance input across a very wide frequency range to the external driving source that enables great flexibility
in the external analog filter design as well as excellent 50-Ω matching for RF applications. The buffer also helps
isolate the external driving circuit from the internal switching currents of the sampling circuit, resulting in a more
constant SFDR performance across input frequencies. The common-mode voltage of the signal inputs is
internally biased to 1.3 V using 2-kΩ resistors to allow for ac-coupling of the input drive network. Each input pin
(INP, INM) must swing symmetrically between (VCM + 0.275 V) and (VCM – 0.275 V), resulting in a 1.1-VPP
(default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 1000 MHz.
7.3.2 Recommended Input Circuit
In order to achieve optimum ac performance, the following circuitry (shown in 图 7-1) is recommended at the
analog inputs.
T1
T2
0.1 mF
10 W
INxP
0.1 mF
25 W
25 W
0.1 mF
RIN
CIN
INxM
1:1
10 W
1:1
0.1 mF
TI Device
Copyright © 2017, Texas Instruments Incorporated
图7-1. Analog Input Driving Circuit
7.3.3 Clock Input
The clock inputs of the ADS58J64 supports LVDS and LVPECL standards. The CLKP, CLKM inputs have an
internal termination of 100 Ω. The clock inputs must be ac-coupled because the input pins are self-biased to a
common-mode voltage of 0.7 V, as shown in 图7-2 and 图7-3.
0.1 mF
0.1 mF
ADS58J64
ADS58J64
Z0
CLKP
Z0
CLKP
150 Ω
Internal termination
of 100 ꢀ
Typical LVPECL
Clock Input
Internal termination
of 100 ꢀ
Typical LVDS
Clock Input
Z0
CLKM
Z0
0.1 mF
150 Ω
CLKM
0.1 mF
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Copyright © 2017, Texas Instruments Incorporated
图7-2. LVPECL Clock Driving Circuit
图7-3. LVDS Clock Driving Circuit
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7.4 Device Functional Modes
7.4.1 Digital Features
The ADS58J64 has two stages of digital decimation filters, as shown in 图 7-4. The first stage is mandatory and
decimates by 2, and can be configured as either a low-pass or high-pass filter. The second stage decimation
supports real to complex quadrature demodulation and decimation by 2 or 4. After decimation, the complex
signal can be converter back to a real signal through digital quadrate modulation at a frequency of fOUT / 4,
where fOUT is the sample frequency after decimation.
Optionally, a burst mode output can be used to output the decimate-by-2 data directly.
The four channels can be configured as pairs (A, B and C, D) to either burst or decimation mode. If all four
channels are in decimation mode, then the decimation setting must be the same decimation for all four channels.
All modes of operation and the maximum bandwidth provided at a sample rate of 491.52 MSPS and
368.64 MSPS are listed in 表 7-1. The first stage decimation filter prior to the 16-bit numerically controlled
oscillator (NCO) is a noise suppression filter with 45% pass-band bandwidth relative to the input sample rate,
less than 0.2-dB ripple, and approximately 40-dB stop-band attenuation. This filter is only used to reduce the
ADC output rate from 1 GSPS to 500 MSPS prior to the second stage decimation filter or burst mode. Some
analog filtering of other Nyquist zones after the first stage decimation filter is expected to be required.
The second stage filter has a pass-band bandwidth of 81.4% relative to the output sample rate, supporting a
200-MHz bandwidth with a 245.76-MSPS complex output rate.
fOUT / 4
Real Output
Filter
16-Bit
NCO
IQ 125 MSPS
IQ Output
JESD204B
Block
2
Filter
2
Filter
2
IQ 250 MSPS
fS = 1 GSPS
500 MSPS
IQ 500 MSPS
Real or IQ Output
ADC
图7-4. ADS58J64 Channel (1 of 4) Block Diagram
表7-1. ADS58J64 Operating Modes
BANDWIDTH
AT 368.64
MSPS
OPERATING
MODE
1ST STAGE
DECIMATION
DIGITAL
MIXER
2ND STAGE
DECIMATION
BANDWIDTH AT
491.52 MSPS
OUTPUT
MIXER
OUTPUT
FORMAT
MAX OUTPUT
RATE
DESCRIPTION
0
1
2
2
±fS / 4
2
2
200 MHz
200 MHz
150 MHz
150 MHz
Complex
Complex
250 MSPS
250 MSPS
—
—
16-bit NCO
100 MHz (LP, LP or HP, HP),
75 MHz (HP, LP or LP, HP)
75 MHz,
56.25 MHz
2
2
2
Real
250 MSPS
—
—
3
4
5
6
2
16-bit NCO
16-bit NCO
Reserved
Bypass
200 MHz
100 MHz
Reserved
100 MHz
150 MHz
75 MHz
fOUT / 4
fOUT / 4
Reserved
—
Real
Real
500 MSPS
250 MSPS
Reserved
125 MSPS
Decimation
2
Reserved
2
2
Reserved
4
Reserved
75 MHz
Reserved
Complex
16-bit NCO
Real with zero
insertion
7
8
2
16-bit NCO
2
100 MHz
223 MHz
75 MHz
fOUT / 4
500 MSPS
500 MSPS
Burst mode
167 MHz
Real
—
—
—
—
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7.4.1.1 Numerically Controlled Oscillators (NCOs) and Mixers
The ADS58J64 is equipped with a complex numerically-controlled oscillator. The oscillator generates a complex
exponential sequence: x[n] = ejωn. The frequency (ω) is specified by the 16-bit register setting. The complex
exponential sequence is multiplied by the real input from the ADC to mix the desired carrier down to 0 Hz.
The NCO frequency setting is set by the 16-bit register value, NCO_FREQ[n]:
NCO Frequency [n]ì fS
fNCO
=
216
(1)
7.4.1.2 Decimation Filter
The ADS58J64 has two decimation filters (decimate-by-2) in the data path. The first stage of the decimation filter
is non-programmable and is used in all functional modes. The second stage of decimation, available in DDC
mode 2 and 6, can be used to obtain noise and linearity improvement for low bandwidth applications.
7.4.1.2.1 Stage-1 Filter
The first stage filter is used for decimation of the 2x interleaved data from fCLK to fCLK / 2. The frequency
response and pass-band ripple of the first stage decimation filter are shown in 图7-5 and 图7-6, respectively.
0
-5
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
-10
-15
-20
-25
-30
-35
-40
-45
0
50 100 150 200 250 300 350 400 450 500 550
Frequency (MHz)
0
50 100 150 200 250 300 350 400 450 500 550
Frequency (MHz)
D043
D042
Input clock rate = 1 GHz
Input clock rate = 1 GHz
图7-6. Decimation Filter Pass-Band Ripple vs
图7-5. Decimation Filter Response vs Frequency
Frequency
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7.4.1.2.2 Stage-2 Filter
The second stage filter is used for decimating the data from a sample rate of fCLK / 2 to fCLK / 4. The frequency
response and pass-band ripple of the second stage filter are shown in 图7-7 and 图7-8, respectively.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
0
25 50 75 100 125 150 175 200 225 250 275
Frequency (MHz)
0
25 50 75 100 125 150 175 200 225 250 275
Frequency (MHz)
D044
D045
Input clock rate (fCLK) = 1 GHz
Input clock rate (fCLK) = 1 GHz
图7-7. Decimation Filter Response vs Frequency
图7-8. Decimation Filter Pass-Band Ripple vs
Frequency
7.4.1.3 Mode 0: Decimate-by-4 With IQ Outputs and fS / 4 Mixer
In mode 0, the DDC block includes a fixed frequency ±fS / 4 complex digital mixer preceding the second stage
decimation filters. The IQ passband is approximately ±100 MHz centered at fS / 8 or 3fS / 8, as shown in 图7-9.
fS / 4
Filter
2
Filter
2
IQ 250 MSPS
fS = 1 GSPS
500 MSPS
IQ 500 MSPS
JESD204B
Block
ADC
40 dBc
90 dBc
-fS / 2 -fS / 4
fS / 4 fS / 2
-fS / 4 -fS / 8
fS / 8 fS / 4
40 dBc
-fS / 8
fS / 8
fS / 2
500 MHz
0
fS / 4
图7-9. Operating Mode 0
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7.4.1.4 Mode 1: Decimate-by-4 With IQ Outputs and 16-Bit NCO
In mode 1, the DDC block includes a 16-bit frequency resolution complex digital mixer preceding the second
stage decimation filters, as shown in 图7-10.
16-Bit
NCO
Filter
2
Filter
2
IQ 250 MSPS
fS = 1 GSPS
500 MSPS
IQ 500 MSPS
JESD204B
Block
ADC
40 dBc
90 dBc
-fS / 2 -fS / 4
fS / 4 fS / 2
-fS / 4 -fS / 8
fS / 8 fS / 4
40 dBc
-fS / 8
fS / 8
fS / 2
500 MHz
0
fS / 4
图7-10. Operating Mode 1
7.4.1.5 Mode 2: Decimate-by-4 With Real Output
In mode 2, the DDC block cascades two decimate-by-2 filters. Each filter can be configured as low pass (LP) or
high pass (HP) to allow down conversion of different frequency ranges, as shown in 表 7-2. The LP, HP and HP,
LP output spectra are inverted as shown in 图7-11.
Filter
2
Filter
2
Real 250 MSPS
fS = 1 GSPS
500 MSPS
JESD204B
Block
ADC
40 dBc
90 dBc
-fS / 2 -fS / 4
fS / 4 fS / 2
-fS / 4 -fS / 8
fS / 8 fS / 4
图7-11. Operating in Mode 2
表7-2. ADS58J64 Operating Mode 2 Down-Converted Frequency Ranges
BANDWIDTH WITH
CLOCK RATE OF
737.28 MHz
1ST STAGE
FILTER
2ND STAGE
FILTER
FREQUENCY RANGE WITH
CLOCK RATE OF 983.04 MHz
BANDWIDTH WITH CLOCK
RATE OF 983.04 MHz
FREQUENCY RANGE WITH
CLOCK RATE OF 737.28 MHz
LP
LP
HP
HP
LP
HP
LP
HP
100 MHz
73 MHz
73 MHz
100 MHz
75 MHz
54.75 MHz
54.75 MHz
75 MHz
0 MHz–100 MHz
150 MHz–223 MHz
0 MHz–75 MHz
112.5 MHz–167.25 MHz
201.39 MHz–256.14 MHz
293.64 MHz–368.64 MHz
268.52 MHz–341.52 MHz
391.52 MHz–491.52 MHz
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7.4.1.6 Mode 3: Decimate-by-2 Real Output With Frequency Shift
In mode 3, the DDC block includes a 16-bit complex NCO digital mixer followed by a fS / 4 mixer with a real
output to center the band at fS / 4. The NCO must be set to a value different from ±fS / 4, or else the samples are
zeroed as shown in 图7-12.
16-Bit
fOUT / 4
NCO
Filter
fS = 1 GSPS
500 MSPS
IQ 500 MSPS
Real Output
JESD204B
Block
ADC
2
Filter
40 dBc
-fS / 2 -fS / 4
fS / 4 fS / 2
图7-12. Operating Mode 3
7.4.1.7 Mode 4: Decimate-by-4 With Real Output
In mode 4, the DDC block includes a 16-bit complex NCO digital mixer preceding the second stage decimation
filter. The signal is then mixed with fOUT / 4 to generate a real output, as shown in 图 7-13. The bandwidth
available in this mode is 100 MHz.
16-Bit
fOUT / 4
NCO
Filter
2
Filter
2
fS = 1 GSPS
500 MSPS
IQ 500 MSPS
IQ 250 MSPS
Real Output
JESD204B
Block
ADC
40 dBc
90 dBc
-fS / 2 -fS / 4
fS / 4 fS / 2
-fS / 4 -fS / 8
fS / 8 fS / 4
图7-13. Operating Mode 4
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7.4.1.8 Mode 6: Decimate-by-4 With IQ Outputs for up to 110 MHz of IQ Bandwidth
In mode 6, the DDC block includes a 16-bit complex NCO digital mixer preceding a second stage with a
decimate-by-4 complex, generating a complex output at fS / 8 as shown in 图7-14.
16-Bit
NCO
Filter
2
Filter
2
Filter
2
IQ 125 MSPS
fS = 1 GSPS
500 MSPS
IQ 500 MSPS
IQ 250 MSPS
JESD204B
Block
ADC
40 dBc
90 dBc
90 dBc
-fS / 2 -fS / 4
fS / 4 fS / 2
-fS / 4 -fS / 8
-fS / 4 -fS / 8
fS / 8 fS / 4
fS / 8 fS / 4
40 dBc
-fS / 8
fS / 8
fS / 16
fS / 2
0
-fS / 16
fS / 4
500 MHz
图7-14. Operating Mode 6
7.4.1.9 Mode 7: Decimate-by-4 With Real Output and Zero Stuffing
In mode 7, the DDC block includes a 16-bit complex NCO digital mixer preceding the second stage decimation
filter. The signal is then mixed with fOUT / 4 to generate a real output that is then doubled in sample rate by zero
stuffing every other sample, as shown in 图7-15. The bandwidth available in this mode is 100 MHz.
16-Bit
fOUT / 4
NCO
Filter
2
Zero Stuff
2
Filter
2
fS = 1 GSPS
500 MSPS
IQ 500 MSPS
IQ 250 MSPS
500 MSPS
250 MSPS
JESD204B
Block
ADC
40 dBc
90 dBc
-fS / 2 -fS / 4
fS / 4 fS / 2
-fS / 4 -fS / 8
fS / 8 fS / 4
图7-15. Operating Mode 7
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7.4.1.10 Mode 8: Burst Mode
In burst mode, the decimate-by-2 data are output alternating between low resolution (L, 9-bit) and high resolution
(H, 14-bit) output. The burst mode can be configured via SPI register writes independently for channels A, B and
channels C, D. The high-resolution output is 14 bits and the number of high- and low-resolution samples is set
with two user-programmable counters: one for high resolution (HC) and one for low resolution (LC). There is one
counter pair (HC, LC) for channels A, B and one pair for channels C, D. The internal logic checks if the maximum
duty cycle is exceeded and, if necessary, resets the counters to default values. Each output cycle starts with a
low resolution and the counter values can be reconfigured for the next cycle prior to the start of the next cycle.
The number of high-resolution samples is equal to two times the high-resolution count (HC). Similarly, the
number of low-resolution samples is equal to two times the low-resolution count (LC).
An example of burst mode with mode 8 is shown in 图7-16.
Enable
Burst Mode
New Cycle
Starts Again
2LC Times Out
DA
DB
DC
DD
2HC
2HC
2LC
2LC
Update Counter Values
HRES
14-Bit Low Resolution
9-Bit Low Resolution
HRES
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OVR
16-Bit Data Going Into 8b, 10b Encoder
图7-16. Burst Mode
The counter values for high and low resolution can be programmed to:
High-resolution counter (HC): 1 to 225
Low-resolution counter (LC): 1 to 228
The output duty cycle limit is shown in 表7-3.
表7-3. Output Duty Cycle Limit
HIGH-RESOLUTION LOW-RESOLUTION
MAXIMUM-ALLOWED DUTY CYCLE
(High:Low Resolution Output)
DEFAULT VALUE
(HC)
DEFAULT VALUE
(LC)
OUTPUT
OUTPUT
14 bits
9 bits
1:3
1
3
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7.4.1.11 Trigger Input
Burst mode can be operated in auto trigger or manual trigger mode. In manual trigger mode, the TRIGGER input
(TRIGAB, TRIGCD) is used to release the high-resolution data (HC) burst after the low-resolution data counter
(LC) times out. In auto trigger mode, the high-resolution data are released immediately after completion of the
last low-resolution sample.
Using SPI control the ADS58J64 can be configured to use TRIGAB or TRIGCD as the manual trigger input.
7.4.1.12 Manual Trigger Mode
Burst mode can be operated in auto trigger or manual trigger mode. In manual trigger mode, the TRIGGER input
(TRIGAB, TRIGCD) is used to release the high-resolution data (HC) burst after the low-resolution data counter
(LC) times out. In auto trigger mode, the high-resolution data are released immediately after completion of the
last low-resolution sample. Using SPI control, the ADS58J64 can be configured to use TRIGAB or TRIGCD as
the manual trigger input.
An example of burst mode with a manual trigger is shown in 图7-17.
New Cycle
Starts Again
Enable
Burst Mode
LC Times Out,
Ready for Trigger
Trigger Event
DA
DB
DC
DD
2HC
2HC
2LC
2LC
Update Counter Values
TRDYAB,
TRDYCD
TRIGAB,
TRIGCD
HRES
14-Bit High Resolution
9-Bit Low Resolution
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
HRES
D0
OVR
16-Bit Data Going Into 8b, 10b Encoder
图7-17. Timing Diagram for Manual Trigger Mode
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7.4.1.13 Auto Trigger Mode
When auto trigger mode is enabled, the ADS58J64 starts transmission of low-resolution data. As soon as the
low-resolution samples counter (LC) is finished, the ADS58J64 immediately begins transmitting the high-
resolution output (H). The HRES flag can also be embedded in the JESD204B output data stream. The counter
values can be updated until a new burst mode cycle starts with transmission of low-resolution samples. Any
input on the trigger input pins is ignored.
An example of burst mode with an automatic trigger is shown in 图7-18.
Enable
Burst Mode
New Cycle
Starts Again
2LC Times Out
DA
DB
DC
DD
2HC
2HC
2LC
2LC
Update Counter Values
HRES
14-Bit Low Resolution
9-Bit Low Resolution
HRES
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OVR
16-Bit Data Going Into 8b, 10b Encoder
图7-18. Timing Diagram for Auto Trigger Mode
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7.4.1.14 Overrange Indication
The ADS58J64 provides a fast overrange indication that can be presented in the digital output data stream via
SPI configuration. When the FOVR indication is embedded in the output data stream, this indication replaces the
LSB (D0) of the 16 bits going to the 8b, 10b encode, as shown in 图7-19.
14-bit data output
D0/
OVR
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
16-bit data going into 8b/10b encoder
图7-19. Timing Diagram for FOVR
The fast overrange feature of the ADS58J64 is configured using an upper (FOVRHi) and a lower (FOVRLo) 8-bit
threshold that are compared against the partial ADC output of the initial pipeline stages. 图 7-20 shows the
FOVR high and FOVR low thresholds.
The two thresholds are configured via the SPI register where a setting of 136 maps to the maximum ADC code
for a high FOVR, and a setting of 8 maps to the minimum ADC code for a low FOVR.
18000
16000
FOVR Hi
14000
12000
10000
8000
6000
FOVR Lo
4000
2000
0
图7-20. FOVR High and FOVR Low Thresholds
The FOVR threshold from a full-scale input based on the ADC code can be calculated by 方程式2:
FOVR High or FOVR Low - 72
FOVR (dBFS) = 20log
64
(2)
Therefore, a threshold of –0.5 dBFS from full-scale can be set with:
• FOVR high = 132 (27h, 84h)
• FOVR low = 12 (28h, 0Ch)
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7.5 Programming
7.5.1 JESD204B Interface
The ADS58J64 supports device subclass 1 with a maximum output data rate of 10 Gbps for each serial
transmitter.
An external SYSREF signal is used to align all internal clock phases and the local multi-frame clock to a specific
sampling clock edge, as shown in 图7-21. A common SYSREF signal allows synchronization of multiple devices
in a system and minimizes timing and alignment uncertainty. The ADS58J64 supports single (for all four JESD
links) or dual (for channel A, B and C, D) SYNCb inputs and can be configured via SPI.
SYSREF
SYNCbAB
JESD
204B
JESD204B
DA
INA
INB
INC
IND
JESD
204B
JESD204B
DB
JESD
204B
JESD204B
DC
JESD
204B
JESD204B
DD
Sample Clock
SYNCbCD
图7-21. JESD204B Transmitter Block
Depending on the ADC sampling rate, the JESD204B output interface can be operated with one lane per
channel. The JESD204B setup and configuration of the frame assembly parameters is handled via the SPI
interface.
The JESD204B transmitter block consists of the transport layer, the data scrambler, and the link layer, as shown
in 图 7-22. The transport layer maps the ADC output data into the selected JESD204B frame data format and
manages if the ADC output data or test patterns are being transmitted. The link layer performs the 8b, 10b data
encoding as well as the synchronization and initial lane alignment using the SYNC input signal. Optionally, data
from the transport layer can be scrambled.
JESD204B Block
Transport Layer
Link Layer
Frame Data
Mapping
8b, 10b
Encoding
Scrambler
1+x14+x15
DX
Comma Characters
Initial Lane Alignment
Test Patterns
SYNCb
图7-22. JESD Interface Block Diagram
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7.5.2 JESD204B Initial Lane Alignment (ILA)
The initial lane alignment process is started by the receiving device by deasserting the SYNCb signal. When a
logic low is detected on the SYNC input pins, the ADS58J64 starts transmitting comma (K28.5) characters to
establish code group synchronization, as shown in 图7-23.
When synchronization is complete, the receiving device reasserts the SYNCb signal and the ADS58J64 starts
the initial lane alignment sequence with the next local multi-frame clock boundary. The ADS58J64 transmits four
multi-frames, each containing K frames (K is SPI programmable). Each of the multi-frames contains the frame
start and end symbols and the second multi-frame also contains the JESD204 link configuration data.
SYSREF
LMFC Clock
LMFC Boundary
Multi
Frame
SYNCb
Transmit Data
xxx
K28.5
K28.5
ILA
ILA
DATA
DATA
Code Group
Synchronization
Initial Lane Alignment
Data Transmission
图7-23. ILA Sequence
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7.5.3 JESD204B Frame Assembly
The JESD204B standard defines the following parameters:
• L is the number of lanes per link
• M is the number of converters per device
• F is the number of octets per frame clock period
• S is the number of samples per frame
表 7-4 lists the available JESD204B formats and valid ranges for the ADS58J64. The ranges are limited by the
SerDes line rate and the maximum ADC sample frequency.
表7-4. Available JESD204B Formats and Valid Ranges for the ADS58J64
MAX ADC
OUTPUT
RATE (MSPS)
OPERATING
MODE
DIGITAL
MODE
OUTPUT
FORMAT
JESD PLL
MODE
MAX fSerDes
(Gbps)
JESD PLL REGISTER
CONFIGURATION
L
M
F
S
JESD MODE
4
4
8
4
4
2
1
1
0, 1
2, 4
2x decimation
2x decimation
Complex
Real
40x
20x
40x
20x
250
250
10.0
5.0
—
CTRL_SER_MODE = 1,
SerDes_MODE = 1
2
4
4
8
4
4
1
1
2, 4
6
2x decimation
4x decimation
Real
40x
40x
40x
20x
250
125
10.0
5.0
—
—
Complex
CTRL_SER_MODE = 1,
SerDes_MODE = 3
2
8
8
1
6
4x decimation
Complex
80x
40x
125
10.0
2x decimation
with 0-pad
4
4
4
4
2
2
1
1
7
Real
Real
20x
20x
40x
40x
500
500
10.0
10.0
—
—
3, 8
Burst mode
The detailed frame assembly for various LMFS settings are shown in 表7-5 and 表7-6.
表7-5. Detailed Frame Assembly for Four-Lane Modes (Mode 0, 1, 3, 6, 7, and 8)
OUTPUT
LANE
LMFS = 4841
LMFS = 4421
LMFS = 4421 (0-Pad)
DA
DB
DC
DD
AI0[15:8]
BI0[15:8]
CI0[15:8]
DI0[15:8]
AI0[7:0]
AQ0[15:8] AQ0[7:0]
BQ0[15:8] BQ0[7:0]
CQ0[15:8] CQ0[7:0]
DQ0[15:8] DQ0[7:0]
A0[15:8]
B0[15:8]
C0[15:8]
D0[15:8]
A0[7:0]
A1[15:8]
B1[15:8]
C1[15:8]
D1[15:8]
A1[7:0]
B1[7:0]
C1[7:0]
D1[7:0]
A0[15:8]
B0[15:8]
C0[15:8]
D0[15:8]
A0[7:0]
B0[7:0]
C0[7:0]
D0[7:0]
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
BI0[7:0]
CI0[7:0]
DI0[7:0]
B0[7:0]
C0[7:0]
D0[7:0]
表7-6. Detailed Frame Assembly for Two-Lane Modes (Mode 2 and 4)
OUTPUT
LANE
LMFS = 2441
LMFS = 2881
DB
DC
A0[15:8]
C0[15:8]
A0[7:0]
C0[7:0]
B0[15:8]
D0[15:8]
B0[7:0]
D0[7:0]
AI0[15:8]
CI0[15:8]
AI0[7:0]
CI0[7:0]
AQ0[15:8]
CQ0[15:8]
AQ0[7:0]
CQ0[7:0]
BI0[15:8]
DI0[15:8]
BI0[7:0]
DI0[7:0]
BQ0[15:8]
DQ0[15:8]
BQ0[7:0]
DQ0[7:0]
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7.5.4 JESD Output Switch
The ADS58J64 provides a digital cross-point switch in the JESD204B block that allows internal routing of any
output of the two ADCs within one channel pair to any of the two JESD204B serial transmitters in order to ease
layout constraints, as shown in 图 7-24. The cross-point switch routing is configured via SPI (address 41h in the
SERDES_XX digital page).
JESD Switch
DAP,
ADCA
DAM
DBP,
ADCB
DBM
JESD Switch
DCP,
ADCC
DCM
DDP,
ADCD
DDM
图7-24. Switching the Output Lanes
7.5.4.1 SerDes Transmitter Interface
Each of the 10-Gbps SerDes transmitter outputs require ac-coupling between the transmitter and receiver, as
shown in 图 7-25. Terminate the differential pair with 100 Ωas close to the receiving device as possible to avoid
unwanted reflections and signal degradation.
0.1 mF
DAP, DAB,
DAC, DAP
Rt = ZO
Transmission Line,
VCM
Receiver
Zo
Rt = ZO
DAM, DAB,
DAC, DAM
0.1 mF
图7-25. SerDes Transmitter Connection to Receiver
7.5.4.2 SYNCb Interface
The ADS58J64 supports single (where either the SYNCb input controls all four JESD204B links) or dual (where
one SYNCb input controls two JESD204B lanes: DA, DB and DC, DD) SYNCb control. When using the single
SYNCb control, connect the unused input to a differential logic low (SYNCbxxP = 0 V, SYNCbxxM = DVDD).
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7.5.4.3 Eye Diagram
图 7-26 to 图 7-29 show the serial output eye diagrams of the ADS58J64 at 7.5 Gbps and 10 Gbps with default
and increased output voltage swing against the JESD204B mask.
图7-27. Eye at 7.5-Gbps Bit Rate with Default
图7-26. Eye at 10-Gbps Bit Rate with Default
Output Swing
Output Swing
图7-28. Eye at 10-Gbps Bit Rate with Increased
图7-29. Eye at 7.5-Gbps Bit Rate with Increased
Output Swing
Output Swing
7.5.5 Device Configuration
The ADS58J64 can be configured using a serial programming interface, as described in the 节 7.6 section. In
addition, the device has one dedicated parallel pin (PDN) for controlling the power-down modes. The ADS58J64
supports a 24-bit (16-bit address, 8-bit data) SPI operation and uses paging to access all register bits.
7.5.5.1 Details of the Serial Interface
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), SDIN (serial data input data), and SDOUT (serial data output)
pins. Serially shifting bits into the device is enabled when SEN is low. SDIN serial data are latched at every
SCLK rising edge when SEN is active (low). Data can be loaded in multiples of 24-bit words within a single
active SEN pulse. The first 16 bits form the register address and the remaining eight bits are the register data.
The interface can work with SCLK frequencies from 10 MHz down to very low speeds (of a few hertz) and also
with a non-50% SCLK duty cycle.
7.5.5.1.1 Register Initialization
After power-up, the internal registers must be initialized to the default values. This initialization can be
accomplished in one hardware reset by applying a high pulse on the RESET pin.
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7.5.5.2 Serial Register Write
The internal registers of the ADS58J64 can be programmed (as shown in 图7-30) by:
1. Driving the SEN pin low
2. Setting the R/W bit = 0
3. Initiating a serial interface cycle specifying the address of the register (A[14:0]) whose content must be
written
4. Writing the 8-bit data that is latched in on the SCLK rising edge
The ADS58J64 has several different register pages (page selection in address 11h, 12h). Specify the register
page before writing to the desired address. The register page only must be set one time for continuous writes to
the same page.
During the write operation, the SDOUT pin is in a high-impedance mode and must float.
Register Address (14:0)
Register Data (7:0)
SDIN
R/W
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
tDH
tSCLK
tDSU
SCLK
tSLOADS
tSLOADH
SEN
RESET
图7-30. Serial Interface Write Timing Diagram
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7.5.5.3 Serial Read
A typical 4-wire serial register readout is shown in 图 7-31. In the default 4-pin configuration, the SDIN pin is the
data output from the ADS58J64 during the data transfer cycle when SDOUT is in a high-impedance state. The
internal registers of the ADS58J64 can be read out by:
1. Driving the SEN pin low
2. Setting the R/W bit to 1 to enable read back
3. Specifying the address of the register (A[14:0]) whose content must be read back
4. The device outputs the contents (D[7:0]) of the selected register on the SDOUT pin (pin 51)
5. The external controller can latch the contents at the SCLK rising edge
Read contents of register 11h containing 04h.
Register Address (15:0) = 11h
Register Data (7:0) = XX (don‘t care)
1
SDIN
R/W
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SEN
SDOUT functions as a serial readout (R/W = 1).
0
0
0
0
0
1
0
0
SDOUT
图7-31. Serial Interface 4-Wire Read Timing Diagram
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7.6 Register Maps
7.6.1 Register Map
The ADS58J64 registers are organized on different pages depending on their internal functions. The pages are
accessed by selecting the page in the master pages 11h–13h. The page selection must only be written one time
for a continuous update of registers for that page.
There are six different SPI banks (shown in 图7-32) that group together different functions:
• GLOBAL: contains controls for accessing other SPI banks
• DIGTOP: top-level digital functions
• ANALOG: registers controlling power-down and analog functions
• SERDES_XX: registers controlling JESD204B functions
• CHX: registers controlling channel-specific functions, including DDC
• ADCXX: register page for one of the eight interleaved ADCs
Global SPI Interface
SPI_ADC_
A1, A2, B1, B2
SPI_DIGTOP
SPI_ANALOG
SPI_ADC_
C1, C2, D1, D2
SPI_CH_A, B
SPI_SERDES_AB
SPI_SERDES_CD
SPI_CH_C, D
A1
A2
C1
C2
Channel C
Channel A
Top Digital
and
Analog Functions
SERDES AB
SERDES CD
A3
A4
D1
D2
Channel D
Channel B
图7-32. SPI Register Block Diagram
表7-7. Serial Interface Register Map
ADDRESS (Hex)
7
6
5
4
3
2
1
0
GLOBAL PAGE
00h
WRITE_1
0
0
0
0
0
0
SW_RESET
04h
VERSION_ID
11h
SPI_D2
SPI_D1
SPI_SerDes_CD
0
SPI_C2
SPI_SerDes_AB
0
SPI_C1
SPI_B2
SPI_CHC
0
SPI_B1
SPI_CHB
0
SPI_A2
SPI_CHA
0
SPI_A1
12h
0
0
SPI_CHD
0
SPI_DIGTOP
SPI_ANALOG
13h
DIGTOP PAGE
64h
8Dh
8Eh
8Fh
90h
0
0
0
0
0
0
FS_375_500
0
CUSTOMPATTERN1[7:0]
CUSTOMPATTERN1[15:8]
CUSTOMPATTERN2[7:0]
CUSTOMPATTERN2[15:8]
TESTPATTERNEN TESTPATTERNEN TESTPATTERNEN TESTPATTERNEN
TESTPATTERNSELECT
91h
ABh
ACh
ADh
AEh
CHD
CHC
CHB
CHA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SPECIALMODE0
SPECIALMODE1
DDCMODEAB
DDCMODECD
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表7-7. Serial Interface Register Map (continued)
ADDRESS (Hex)
7
6
5
4
3
2
1
0
B7h
0
0
0
0
0
0
0
LOADTRIMS
ANALOG PAGE
6Ah
0
0
0
0
0
0
0
0
0
0
0
DIS_SYSREF
0
0
0
6Fh
JESD_SWING
71h
EMP_LANE_B[5:4]
EMP_LANE_D[5:4]
EMP_LANE_A
EMP_LANE_C
72h
0
0
EMP_LANE_B[3:0]
93h
94h
0
0
0
0
0
0
0
0
0
0
EMP_LANE_D[3:0]
9Bh
0
SYSREF_PDN
0
0
0
0
9Dh
PDN_CHA
PDN_CHB
0
PDN_CHD
PDN_CHC
0
0
9Eh
0
0
0
0
0
0
PDN_SYNCAB
0
0
0
0
0
0
0
PDN_GLOBAL
FAST_PDN
0
9Fh
AFh
0
0
PIN_PDN_MODE
PDN_SYNCCD
SERDES_XX PAGE
CTRL_SER_MOD
E
CTRL_K
0
TRANS_TEST_EN
0
0
0
LANE_ALIGN
FRAME_ALIGN
TX_ILA_DIS
20h
21h
22h
SYNCB_SEL_AB_
CD
SYNC_REQ
OPT_SYNC_REQ
0
0
SerDes_MODE
LMFC_MASK_RE
SET
LINK_LAYER_TESTMODE_SEL
FORCE_LMFC_C
RPAT_SET_DISP
0
0
LMFC_CNT_INIT
0
RELEASE_ILANE_REQ
23h
25h
26h
28h
2Dh
36h
OUNT
SCR_EN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
K_NO_OF_FRAMES_PER_MULTIFRAME
0
0
CTRL_LID
0
0
LID1
LID2
PRBS_MODE
0
0
0
0
SERDES_XX PAGE (continued)
LSB1_HR_FLAG_ LSB0_HR_FLAG_
TRIG_SEL_AB_C
D
LOAD_RES
0
AUTO_TRIG_EN
0
RATIO_INVALID
0
37h
EN
EN
39h
0
0
0
LOWRESCOUNT[27:24]
3Ah
LOWRESCOUNT[23:16]
3Bh
LOWRESCOUNT[15:8]
LOWRESCOUNT[7:0]
0
3Ch
3Dh
0
0
0
0
0
HIGHRESCOUNT[27:24]
3Eh
HIGHRESCOUNT[23:16]
HIGHRESCOUNT[15:8]
HIGHRESCOUNT[7:0]
3Fh
40h
41h
LANE_BONA
LANE_AONB
42h
0
0
INVERT_AC
INVERT_BD
GAINWORD
CHX PAGE
26h
0
0
0
0
0
0
0
0
27h
OVR_ENABLE
OVR_FAST_SEL
OVR_LSB1
0
0
0
OVR_LSB0
0
0
NYQUIST_SELEC
0
0
0
0
0
0
0
0
2Dh
T
NYQ_SEL_MODE
02
0
FS4_SIGN
NYQ_SEL
78h
7Ah
NCO_WORD[15:8]
NCO_WORD[7:0]
7Bh
7Eh
0
0
0
0
0
0
0
0
MODE467_GAIN
MODE0_GAIN
MODE13_GAIN
ADCXX PAGE
07h
FAST_OVR_THRESHOLD_HIGH
FAST_OVR_THRESHOLD_LOW
08h
D5h
0
CAL_EN
0
0
0
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7.6.1.1 Register Description
7.6.1.1.1 GLOBAL Page Register Description
7.6.1.1.1.1 Register 00h (address = 00h) [reset = 0h], GLOBAL Page
图7-29. Register 0h
7
6
0
5
0
4
3
2
0
1
0
0
WRITE_1
R/W-0h
0
0
SW_RESET
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-8. Register 00h Field Descriptions
Bit
7
Field
Type
R/W
R/W
R/W
Reset
Description
WRITE_1
0
0h
Always write 1
6-1
0
0h
Must read or write 0
This bit rests the device.
SW_RESET
0h
7.6.1.1.1.2 Register 04h (address = 04h) [reset = 0h], GLOBAL Page
图7-30. Register 4h
7
6
5
4
3
2
1
0
VERSION_ID
R-0h
LEGEND: R = Read only; -n = value after reset
表7-9. Register 04h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
VERSION_ID
R
0h
16 : PG 1.0
32 : PG 2.0
48 : PG3.0
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7.6.1.1.1.3 Register 11h (address = 11h) [reset = 0h], GLOBAL Page
图7-31. Register 11h
7
6
5
4
3
2
1
0
SPI_D2
R/W-0h
SPI_D1
R/W-0h
SPI_C2
R/W-0h
SPI_C1
R/W-0h
SPI_B2
R/W-0h
SPI_B1
R/W-0h
SPI_A2
R/W-0h
SPI_A1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-10. Register 11h Field Descriptions
Bit
Field
Type
Reset
Description
7
SPI_D2
R/W
0h
This bit selects the ADC D2 SPI.
0 : ADC D2 SPI is disabled
1 : ADC D2 SPI is enabled
6
5
4
3
2
1
0
SPI_D1
SPI_C2
SPI_C1
SPI_B2
SPI_B1
SPI_A2
SPI_A1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
This bit selects the ADC D1 SPI.
0 : ADC D1 SPI is disabled
1 : ADC D1 SPI is enabled
This bit selects the ADC C2 SPI
0 : ADC C2 SPI is disabled
1 : ADC C2 SPI is enabled
This bit selects the ADC C1 SPI.
0 : ADC C1 SPI is disabled
1 : ADC C1 SPI is enabled
This bit selects the ADC B2 SPI.
0 : ADC B2 SPI is disabled
1 : ADC B2 SPI is enabled
This bit selects the ADC B1 SPI.
0 : ADC B1 SPI is disabled
1 : ADC B1 SPI is enabled
This bit selects the ADC A2 SPI.
0 : ADC A2 SPI is disabled
1 : ADC A2 SPI is enabled
This bit selects the ADC A1 SPI.
0 : ADC A1 SPI is disabled
1 : ADC A1 SPI is enabled
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7.6.1.1.1.4 Register 12h (address = 12h) [reset = 0h], GLOBAL Page
图7-32. Register 12h
7
0
6
5
4
3
2
1
0
SPI_SerDes_CD
R/W-0h
SPI_SerDes_AB
R/W-0h
SPI_CHD
R/W-0h
SPI_CHC
R/W-0h
SPI_CHB
R/W-0h
SPI_CHA
R/W-0h
SPI_DIGTOP
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-11. Register 12h Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
Description
0
0h
Must read or write 0
6
SPI_SerDes_CD
0h
This bit selects the channel CD SerDes SPI.
0 : Channel CD SerDes SPI is disabled
1 : Channel CD SerDes SPI is enabled
5
4
3
2
1
0
SPI_SerDes_AB
SPI_CHD
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
This bit selects the channel AB SerDes SPI.
0 : Channel AB SerDes is disabled
1 : Channel AB SerDes is enabled
This bit selects the channel D SPI.
0 : Channel D SPI is disabled
1 : Channel D SPI is enabled
SPI_CHC
This bit selects the channel C SPI.
0 : Channel C SPI is disabled
1 : Channel C SPI is enabled
SPI_CHB
This bit selects the channel B SPI.
0 : Channel B SPI is disabled
1 : Channel B SPI is enabled
SPI_CHA
This bit selects the channel A SPI.
0 : Channel A SPI is disabled
1 : Channel A SPI is enabled
SPI_DIGTOP
This bit selects the DIGTOP SPI.
0 : DIGTOP SPI is disabled
1 : DIGTOP SPI is enabled
7.6.1.1.1.5 Register 13h (address = 13h) [reset = 0h], GLOBAL Page
图7-33. Register 13h
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
SPI_ANALOG
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-12. Register 13h Field Descriptions
Bit
7-1
0
Field
Type
R/W
R/W
Reset
Description
0
0h
Must read or write 0
SPI_ANALOG
0h
This bit selects the analog SPI.
0 : Analog SPI is disabled
1 : Analog SPI is disabled
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7.6.1.1.2 DIGTOP Page Register Description
7.6.1.1.2.1 Register 64h (address = 64h) [reset = 0h], DIGTOP Page
图7-34. Register 64h
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
FS_375_500
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-13. Register 64h Field Descriptions
Bit
7-2
1
Field
Type
R/W
R/W
Reset
Description
0
0h
Must read or write 0
FS_375_500
0h
This bit selects the clock rate for loading trims..
0 : 375 MSPS
1 : 500 MSPS
0
0
R/W
0h
Must read or write 0
7.6.1.1.2.2 Register 8Dh (address = 8Dh) [reset = 0h], DIGTOP Page
图7-35. Register 8Dh
7
6
5
4
3
2
1
0
CUSTOMPATTERN1[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-14. Register 8Dh Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CUSTOMPATTERN1[7:0]
R/W
0h
These bits set the custom pattern 1 that is used when the test
pattern is enabled and set to a single or dual test pattern.
7.6.1.1.2.3 Register 8Eh (address = 8Eh) [reset = 0h], DIGTOP Page
图7-36. Register 8Eh
7
6
5
4
3
2
1
0
CUSTOMPATTERN1[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-15. Register 8Eh Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CUSTOMPATTERN1[15:8]
R/W
0h
These bits set the custom pattern 1 that is used when the test
pattern is enabled and set to a single or dual test pattern.
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7.6.1.1.2.4 Register 8Fh (address = 8Fh) [reset = 0h], DIGTOP Page
图7-37. Register 8Fh
7
6
5
4
3
2
1
0
CUSTOMPATTERN2[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-16. Register 8Fh Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CUSTOMPATTERN2[7:0]
R/W
0h
These bits set the custom pattern 2 that is used when the test
pattern select is set to dual pattern mode.
7.6.1.1.2.5 Register 90h (address = 90h) [reset = 0h], DIGTOP Page
图7-38. Register 90h
7
6
5
4
3
2
1
0
CUSTOMPATTERN2[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-17. Register 90h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CUSTOMPATTERN2[15:8]
R/W
0h
These bits set the custom pattern 2 that is used when the test
pattern select is set to dual pattern mode.
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7.6.1.1.2.6 Register 91h (address = 91h) [reset = 0h], DIGTOP Page
图7-39. Register 91h
7
6
5
4
3
2
1
0
TESTPATTERNSELECT
R/W-0h
TESTPATTERNENCHD TESTPATTERNENCHC TESTPATTERNENCHB TESTPATTERNENCHA
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-18. Register 91h Field Descriptions
Bit
Field
Type
Reset
Description
7-4
TESTPATTERNSELECT
R/W
0h
These bits select the test pattern on the output when the test
pattern is enabled for a suitable channel.
0 : Default
1 : All zeros
2 : All ones
3 : Toggle pattern
4 : Ramp pattern
6 : Custom pattern 1
7 : Toggle between custom pattern 1 and custom pattern 2
8 : Deskew pattern (0xAAAA)
3
2
1
0
TESTPATTERNENCHD
TESTPATTERNENCHC
TESTPATTERNENCHB
TESTPATTERNENCHA
R/W
R/W
R/W
R/W
0h
0h
0h
0h
This bit enables the channel D test pattern.
0 : Default data on channel D
1 : Enable test pattern on channel D
This bit enables the channel C test pattern.
0 : Default data on channel C
1 : Enable test pattern on channel C
This bit enables the channel B test pattern.
0 : Default data on channel B
1 : Enable test pattern on channel B
This bit enables the channel A test pattern.
0 : Default data on channel A
1 : Enable test pattern on channel A
7.6.1.1.2.7 Register ABh (address = ABh) [reset = 0h], DIGTOP Page
图7-40. Register ABh
7
0
6
0
5
0
4
0
3
2
0
1
0
0
0
SPECIALMODE0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-19. Register ABh Field Descriptions
Bit
7-1
0
Field
Type
R/W
R/W
Reset
Description
0
0h
Must read or write 0
Always write 1
SPECIALMODE0
0h
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7.6.1.1.2.8 Register ACh (address = ACh) [reset = 0h], DIGTOP Page
图7-41. Register ACh
7
0
6
0
5
0
4
0
3
2
0
1
0
0
0
SPECIALMODE1
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-20. Register ACh Field Descriptions
Bit
7-1
0
Field
Type
R/W
R/W
Reset
Description
0
0h
Must read or write 0
Always write 1
SPECIALMODE1
0h
7.6.1.1.2.9 Register ADh (address = ADh) [reset = 0h], DIGTOP Page
图7-42. Register ADh
7
0
6
0
5
0
4
3
2
1
0
0
DDCMODEAB
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-21. Register ADh Field Descriptions
Bit
7-4
3-0
Field
Type
R/W
R/W
Reset
Description
0
0h
Must read or write 0
DDCMODEAB
0h
These bits select the DDC mode for channel AB.
0 : Mode 0
1 : Mode 1
2 : Mode 2
3 : Mode 3
4 : Mode 4
6 : Mode 6
7 : Mode 7
8 : Mode 8
7.6.1.1.2.10 Register AEh (address = AEh) [reset = 0h], DIGTOP Page
图7-43. Register AEh
7
0
6
0
5
0
4
3
2
1
0
0
DDCMODECD
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-22. Register AEh Field Descriptions
Bit
7-4
3-0
Field
Type
R/W
R/W
Reset
Description
0
0h
Must read or write 0
DDCMODECD
0h
These bits select the DDC mode for channel CD.
0 : Mode 0
1 : Mode 1
2 : Mode 2
3 : Mode 3
4 : Mode 4
6 : Mode 6
7 : Mode 7
8 : Mode 8
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ZHCSFY7B –JANUARY 2017 –REVISED DECEMBER 2021
7.6.1.1.2.11 Register B7h (address = B7h) [reset = 0h], DIGTOP Page
图7-44. Register B7h
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
LOADTRIMS
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-23. Register B7h Field Descriptions
Bit
7-1
0
Field
Type
R/W
R/W
Reset
Description
0
0h
Must read or write 0
This bit load trims the device.
LOADTRIMS
0h
7.6.1.1.3 ANALOG Page Register Description
7.6.1.1.3.1 Register 6Ah (address = 6Ah) [reset = 0h], ANALOG Page
图7-45. Register 6Ah
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
DIS_SYSREF
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-24. Register 6Ah Field Descriptions
Bit
7-2
1
Field
Type
R/W
R/W
Reset
Description
0
0h
Must read or write 0
DIS_SYSREF
0h
This bit masks the SYSREF input.
0 : SYSREF input is not masked
1 : SYSREF input is masked
0
0
R/W
0h
Must read or write 0
7.6.1.1.3.2 Register 6Fh (address = 6Fh) [reset = 0h], ANALOG Page
图7-46. Register 6Fh
7
0
6
5
4
3
2
0
1
0
0
0
JESD_SWING
R/W-0h
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-25. Register 6Fh Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
Description
0
0h
Must read or write 0
6-4
JESD_SWING
0h
These bits control the JESD swing.
0 : 860 mVPP
1 : 810 mVPP
2 : 770 mVPP
3 : 745 mVPP
4 : 960 mVPP
5 : 930 mVPP
6 : 905 mVPP
7 : 880 mVPP
3-0
0
R/W
0h
Must read or write 0
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7.6.1.1.3.3 Register 71h (address = 71h) [reset = 0h], ANALOG Page
图7-47. Register 71h
7
6
5
4
3
2
1
0
EMP_LANE_B[5:4]
R/W-0h
EMP_LANE_A
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-26. Register 71h Field Descriptions
Bit
Field
Type
Reset
Description
7-6
EMP_LANE_B[5:4]
R/W
0h
De-emphasis for lane B.
These bits select the amount of de-emphasis for the JESD
output transmitter. The de-emphasis value in decibels (dB) is
measured as the ratio between the peak value after the signal
transition to the settled value of the voltage in one bit period.
0 : 0 dB
1 : –1 dB
3 : –2 dB
7 : –4.1 dB
15 : –6.2 dB
31 : –8.2 dB
63 : –11.5 dB
Others: Do not use
5-0
EMP_LANE_A
R/W
0h
De-emphasis for lane A.
These bits select the amount of de-emphasis for the JESD
output transmitter. The de-emphasis value in dB is measured as
the ratio between the peak value after the signal transition to the
settled value of the voltage in one bit period.
0 : 0 dB
1 : –1 dB
3 : –2 dB
7 : –4.1 dB
15 : –6.2 dB
31 : –8.2 dB
63 : –11.5 dB
Others: Do not use
7.6.1.1.3.4 Register 72h (address = 72h) [reset = 0h], ANALOG Page
图7-48. Register 72h
7
0
6
0
5
0
4
3
2
1
0
0
EMP_LANE_B[3:0]
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-27. Register 72h Field Descriptions
Bit
Field
Type
Reset
Description
7-4
0
R/W
0h
Must read or write 0
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表7-27. Register 72h Field Descriptions (continued)
Bit
Field
EMP_LANE_B[3:0]
Type
Reset
Description
3-0
R/W
0h
De-emphasis for lane B.
These bits select the amount of de-emphasis for the JESD
output transmitter. The de-emphasis value in dB is measured as
the ratio between the peak value after the signal transition to the
settled value of the voltage in one bit period.
0 : 0 dB
1 : –1 dB
3 : –2 dB
7 : –4.1 dB
15 : –6.2 dB
31 : –8.2 dB
63 : –11.5 dB
Others: Do not use
7.6.1.1.3.5 Register 93h (address = 93h) [reset = 0h], ANALOG Page
图7-49. Register 93h
7
6
5
4
3
2
1
0
EMP_LANE_D[5:4]
R/W-0h
EMP_LANE_C
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-28. Register 93h Field Descriptions
Bit
Field
Type
Reset
Description
7-6
EMP_LANE_D[5:4]
R/W
0h
De-emphasis for lane D.
These bits select the amount of de-emphasis for the JESD
output transmitter. The de-emphasis value in dB is measured as
the ratio between the peak value after the signal transition to the
settled value of the voltage in one bit period.
0 : 0 dB
1 : –1 dB
3 : –2 dB
7 : –4.1 dB
15 : –6.2 dB
31 : –8.2 dB
63 : –11.5 dB
Others: Do not use
5-0
EMP_LANE_C
R/W
0h
De-emphasis for lane C.
These bits select the amount of de-emphasis for the JESD
output transmitter. The de-emphasis value in dB is measured as
the ratio between the peak value after the signal transition to the
settled value of the voltage in one bit period.
0 : 0 dB
1 : –1 dB
3 : –2 dB
7 : –4.1 dB
15 : –6.2 dB
31 : –8.2 dB
63 : –11.5 dB
Others: Do not use
7.6.1.1.3.6 Register 94h (address = 94h) [reset = 0h], ANALOG Page
图7-50. Register 94h
7
0
6
0
5
0
4
3
2
1
0
0
EMP_LANE_D[3:0]
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
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LEGEND: R/W = Read/Write; -n = value after reset
表7-29. Register 94h Field Descriptions
Bit
7-4
3-0
Field
Type
R/W
R/W
Reset
Description
0
0h
Must read or write 0
De-emphasis for lane D.
EMP_LANE_D[3:0]
0h
These bits select the amount of de-emphasis for the JESD
output transmitter. The de-emphasis value in dB is measured as
the ratio between the peak value after the signal transition to the
settled value of the voltage in one bit period.
0 : 0 dB
1 : –1 dB
3 : –2 dB
7 : –4.1 dB
15 : –6.2 dB
31 : –8.2 dB
63 : –11.5 dB
Others: Do not use
7.6.1.1.3.7 Register 9Bh (address = 9Bh) [reset = 0h], ANALOG Page
图7-51. Register 9Bh
7
0
6
0
5
0
4
3
2
0
1
0
0
0
SYSREF_PDN
R/W-0h
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-30. Register 9Bh Field Descriptions
Bit
7-5
4
Field
Type
R/W
R/W
Reset
Description
0
0h
Must read or write 0
SYSREF_PDN
0h
This bit powers down the SYSREF buffer.
0 : SYSREF buffer is powered up
1 : SYSREF buffer is powered down
3-0
0
R/W
0h
Must read or write 0
7.6.1.1.3.8 Register 9Dh (address = 9Dh) [reset = 0h], ANALOG Page
图7-52. Register 9Dh
7
6
5
0
4
3
2
1
0
0
0
PDN_CHA
R/W-0h
PDN_CHB
R/W-0h
0
PDN_CHD
R/W-0h
PDN_CHC
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-31. Register 9Dh Field Descriptions
Bit
Field
Type
Reset
Description
7
PDN_CHA
R/W
0h
This bit powers down channel A.
0 : Normal operation
1 : Channel A is powered down
6
PDN_CHB
R/W
0h
This bit powers down channel B.
0 : Normal operation
1 : Channel B is powered down
5-4
3
0
R/W
R/W
0h
0h
Must read or write 0
PDN_CHD
This bit powers down channel D.
0 : Normal operation
1 : Channel D is powered down
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表7-31. Register 9Dh Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
PDN_CHC
R/W
0h
This bit powers down channel C.
0 : Normal operation
1 : Channel C is powered down
1-0
0
R/W
0h
Must read or write 0
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7.6.1.1.3.9 Register 9Eh (address = 9Eh) [reset = 0h], ANALOG Page
图7-53. Register 9Eh
7
0
6
0
5
0
4
3
2
0
1
0
0
PDN_SYNCAB
R/W-0h
0
PDN_GLOBAL
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-32. Register 9Eh Field Descriptions
Bit
7-5
4
Field
Type
R/W
R/W
Reset
Description
0
0h
Must read or write 0
PDN_SYNCAB
0h
This bit controls the STNCAB buffer power-down.
0 : SYNCAB buffer is powered up
1 : SYNCAB buffer is powered down
3-1
0
0
R/W
R/W
0h
0h
Must read or write 0
PDN_GLOBAL
This bit controls the global power-down.
0 : Global power-up
1 : Global power-down
7.6.1.1.3.10 Register 9Fh (address = 9Fh) [reset = 0h], ANALOG Page
图7-54. Register 9Fh
7
0
6
0
5
0
4
0
3
2
1
0
0
0
PIN_PDN_MODE
R/W-0h
FAST_PDN
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-33. Register 9Fh Field Descriptions
Bit
7-2
1
Field
Type
R/W
R/W
Reset
Description
0
0h
Must read or write 0
PIN_PDN_MODE
0h
This bit selects the pin power-down mode.
0 : PDN pin is configured to fast power-down
1 : PDN pin is configured to global power-down
0
FAST_PDN
R/W
0h
This bit controls the fast power-down.
0 : Device powered up
1 : Fast power down
7.6.1.1.3.11 Register AFh (address = AFh) [reset = 0h], ANALOG Page
图7-55. Register AFh
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
PDN_SYNCCD
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-34. Register AFh Field Descriptions
Bit
7-2
1
Field
Type
R/W
R/W
Reset
Description
0
0h
Must read or write 0
PDN_SYNCCD
0h
This bit controls the SYNCCD buffer power-down.
0 : SYNCCD buffer is powered up
1 : SYNCCD buffer is powered down
0
0
R/W
0h
Must read or write 0
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7.6.1.1.4 SERDES_XX Page Register Description
7.6.1.1.4.1 Register 20h (address = 20h) [reset = 0h], SERDES_XX Page
图7-56. Register 20h
7
6
5
0
4
3
2
1
0
CTRL_SER_
MODE
TRANS_TEST_
EN
CTRL_K
R/W-0h
0
LANE_ALIGN FRAME_ALIGN TX_ILA_DIS
R/W-0h R/W-0h R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-35. Register 20h Field Descriptions
Bit
Field
Type
Reset
Description
7
CTRL_K
R/W
0h
This bit is the enable bit for programming the number of frames
per multi-frame.
0 : Default: 5 frames per multi-frame
1 : Frames per multi-frame can be programmed using register
26h
6
CTRL_SER_MODE
R/W
0h
This bit allows the SerDes_MODE setting in register 21h (bits
1-0) to be changed.
0 : Disabled
1 : Enables SerDes_MODE setting
5
4
0
R/W
R/W
0h
0h
Must read or write 0
TRANS_TEST_EN
This bit generates the long transport layer test pattern mode, as
per section 5.1.6.3 of the JESD204B specification.
0 : Test mode is disabled
1 : Test mode is enabled
3
2
0
R/W
R/W
0h
0h
Must read or write 0
LANE_ALIGN
This bit inserts the lane alignment character (K28.3) for the
receiver to align to the lane boundary, as per section 5.3.3.5 of
the JESD204B specification.
0 : Normal operation
1 : Inserts lane alignment characters
1
0
FRAME_ALIGN
TX_ILA_DIS
R/W
R/W
0h
0h
This bit inserts the lane alignment character (K28.7) for the
receiver to align to the lane boundary, as per section 5.3.3.5 of
the JESD204B specification.
0 : Normal operation
1 : Inserts frame alignment characters
This bit disables sending the initial link alignment (ILA)
sequence when SYNC is deasserted.
0 = Normal operation
1 = Disables ILA
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7.6.1.1.4.2 Register 21h (address = 21h) [reset = 0h], SERDES_XX Page
图7-57. Register 21h
7
6
5
4
3
0
2
0
1
0
SYNC_REQ
R/W-0h
OPT_SYNC_REQ
R/W-0h
SYNCB_SEL_AB_CD
R/W-0h
0
SerDes_MODE
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-36. Register 21h Field Descriptions
Bit
Field
Type
Reset
Description
7
SYNC_REQ
R/W
0h
This bit controlls the SYNC register (bit 6 must be enabled).
0 : Normal operation
1 : ADC output data are replaced with K28.5 characters
6
5
OPT_SYNC_REQ
R/W
R/W
0h
0h
This bit enables SYNC operation.
0 : Normal operation
1 : Enables SYNC from the SYNC_REQ register bit
SYNCB_SEL_AB_CD
This bit selects which SYNCb input controls the JESD interface.
0 : Use the SYNCbAB, SYNCbCD pins
1 : When set in the SerDes AB SPI, SYNCbCD is used for the
SerDes AB and CD. When set in the SerDes CD SPI, SYNCbAB
is used for the SerDes AB and CD
4-2
1-0
0
R/W
R/W
0h
0h
Must read or write 0
SerDes_MODE
These bits set the JESD output parameters. The
CTRL_SER_MODE bit (register 20h, bit 6) must also be set to
control these bits. These bits are auto configured for modes 0, 1,
3, and 7, but must be configured for modes 2, 4, and 6.
7.6.1.1.4.3 Register 22h (address = 22h) [reset = 0h], SERDES_XX Page
图7-58. Register 22h
7
6
5
4
3
2
0
1
0
0
0
LINK_LAYER_TESTMODE_SEL
R/W-0h
RPAT_SET_DISP
R/W-0h
LMFC_MASK_RESET
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-37. Register 22h Field Descriptions
Bit
Field
Type
Reset
Description
7-5
LINK_LAYER_TESTMODE_SEL
R/W
0h
These bits generate a pattern as per section 5.3.3.8.2 of the
JESD204B document.
0 : Normal ADC data
1 : D21.5 (high-frequency jitter pattern)
2 : K28.5 (mixed-frequency jitter pattern)
3 : Repeat the initial lane alignment (generates a K28.5
character and continuously repeats lane alignment sequences)
4 : 12-octet RPAT jitter pattern
6 : PRBS pattern (PRBS7, 15, 23, 31). Use PRBS_MODE
(register 36h, bits 7-6) to select the PRBS pattern.
4
RPAT_SET_DISP
R/W
0h
This bit changes the running disparity in the modified RPAT
pattern test mode (only when the link layer test mode = 100).
0 : Normal operation
1 : Changes disparity
3
LMFC_MASK_RESET
0
R/W
R/W
0h
0h
0 : Default
1 : Resets the LMFC mask
2-0
Must read or write 0
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7.6.1.1.4.4 Register 23h (address = 23h) [reset = 0h], SERDES_XX Page
图7-59. Register 23h
7
6
5
4
3
2
1
0
FORCE_LMFC_COUNT
R/W-0h
LMFC_CNT_INIT
R/W-0h
RELEASE_ILANE_REQ
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-38. Register 23h Field Descriptions
Bit
Field
Type
Reset
Description
7
FORCE_LMFC_COUNT
R/W
0h
This bit forces an LMFC count.
0 : Normal Operation
1 : Enables using a different starting value for the LMFC counter
6-2
1-0
LMFC_CNT_INIT
R/W
R/W
0h
0h
These bits set the initial value to which the LMFC count resets.
The FORCE_LMFC_COUNT register bit must be enabled.
RELEASE_ILANE_REQ
These bits delay the generation of the lane alignment sequence
by 0, 1, 2, or 3 multi-frames after the code group
synchronization.
0 : 0 multi-frames
1 : 1 multi-frame
2 : 2 multi-frames
3 : 3 multi-frames
7.6.1.1.4.5 Register 25h (address = 25h) [reset = 0h], SERDES_XX Page
图7-60. Register 25h
7
6
0
5
0
4
3
2
0
1
0
0
0
SCR_EN
R/W-0h
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-39. Register 25h Field Descriptions
Bit
Field
Type
Reset
Description
7
SCR_EN
R/W
0h
This bit is the scramble enable bit in the JESD204B interface.
0 : Scrambling is disabled
1 : Scrambling is enabled
6-0
0
R/W
0h
Must read or write 0
7.6.1.1.4.6 Register 26h (address = 26h) [reset = 0h], SERDES_XX Page
图7-61. Register 26h
7
0
6
0
5
0
4
3
2
1
0
K_NO_OF_FRAMES_PER_MULTIFRAME
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-40. Register 26h Field Descriptions
Bit
7-5
4-0
Field
Type
R/W
R/W
Reset
Description
0
0h
Must read or write 0
K_NO_OF_FRAMES_PER_MULTIFRAME
0h
These bits set the number of frames per multi-frame.
The K value used is set value + 1 (for example, if the set
value is 0xF, then K = 16).
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7.6.1.1.4.7 Register 28h (address = 28h) [reset = 0h], SERDES_XX Page
图7-62. Register 28h
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
CTRL_LID
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-41. Register 28h Field Descriptions
Bit
7-4
3
Field
Type
R/W
R/W
Reset
Description
0
0h
Must read or write 0
CTRL_LID
0h
This bit is the enable bit to program the lane ID (LID).
0 : Default LID
1 : Enable LID programming
2-0
0
R/W
0h
Must read or write 0
7.6.1.1.4.8 Register 2Dh (address = 2Dh) [reset = 0h], SERDES_XX Page
图7-63. Register 2Dh
7
6
5
4
3
2
1
0
LID1
LID2
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-42. Register 2Dh Field Descriptions
Bit
Field
Type
Reset
Description
7-4
LID1
R/W
0h
Lane ID for channels A, C. Select SerDes AB for channel A and
SerDes CD for channel C.
Valid only when CTRL_LID = 1.
3-0
LID2
R/W
0h
Lane ID for channels B, D. Select SerDes AB for channel B and
SerDes CD for channel D.
7.6.1.1.4.9 Register 36h (address = 36h) [reset = 0h], SERDES_XX Page
图7-64. Register 36h
7
6
5
0
4
3
2
0
1
0
0
0
PRBS_MODE
R-0h
0
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-43. Register 36h Field Descriptions
Bit
Field
Type
Reset
Description
7-6
PRBS_MODE
R
0h
These bits select the PRBS polynomial in the PRBS pattern
mode.
0 : PRBS7
1 : PRBS15
2 : PRBS23
3 : PRBS31
5-0
0
R/W
0h
Must read or write 0
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7.6.1.1.4.10 Register 37h (address = 37h) [reset = 0h], SERDES_XX Page
图7-65. Register 37h
7
6
5
4
3
2
0
1
0
0
LSB1_HR_
FLAG_EN
LSB0_HR_
FLAG_EN
TRIG_SEL_AB AUTO_TRIG_
RATIO_
INVALID
LOAD_RES
R/W-0h
_CD
EN
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表7-44. Register 37h Field Descriptions
Bit
Field
Type
Reset
Description
7
LSB1_HR_FLAG_EN
R/W
0h
This bit enables the HiRes flag on LSB1.
0 : LSB1 is stuck to 0
1 : LSB1 carries the high-resolution flag
6
5
4
LSB0_HR_FLAG_EN
LOAD_RES
R/W
R/W
R/W
0h
0h
0h
This bit enables the HiRes flag on LSB0.
0 : LSB0 is stuck to 0
1 : LSB0 carries the high-resolution flag
This bit enables loading of high- or low-resolution values.
0 : High- and low-resolution values are not updated
1 : High- and low-resolution values are updated
TRIG_SEL_AB_CD
This bit determines if the TRIGAB or TRIGCD pin is used for
burst mode; must be configured individually for channel AB and
channel CD with paging.
0 : Uses the TRIGAB, TRIGCD pin separately
1 : Uses the TRIGCD pin when set for the SerDes AB SPI; uses
the TRIGAB pin when set for the SerDes CD SPI
3
AUTO_TRIG_EN
R/W
0h
This bit enables an automatic trigger in burst mode (ignores the
TRIGAB, TRIGCD inputs).
0 : Disable auto trigger; trigger is accepted from the pin
1 : Enable auto trigger; pin trigger is ignored
2
1
0
R/W
R
0h
0h
Must read or write 0
RATIO_INVALID
This bit generates an alarm flag when the duty cycle ratio
between the high- and low-resolution counter is set incorrectly.
0 : LowRes, HighRes ratio is valid (≥3)
1 : LowRes, HighRes ratio is valid (< 3)
0
0
R/W
0h
Must read or write 0
7.6.1.1.4.11 Register 39h (address = 39h) [reset = 0h], SERDES_XX Page
图7-66. Register 39h
7
0
6
0
5
0
4
3
2
1
0
0
LOWRESCOUNT[27:24]
R-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表7-45. Register 39h Field Descriptions
Bit
7-4
3-0
Field
Type
R/W
R
Reset
Description
0
0h
Must read or write 0
LOWRESCOUNT[27:24]
0h
28-bit, low-resoluton sample count.
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7.6.1.1.4.12 Register 3Ah (address = 3Ah) [reset = 0h], SERDES_XX Page
图7-67. Register 3Ah
7
6
5
4
3
2
1
1
1
1
0
LOWRESCOUNT[23:16]
R-0h
LEGEND: R = Read only; -n = value after reset
表7-46. Register 3Ah Field Descriptions
Bit
Field
Type
Reset
Description
7-0
LOWRESCOUNT[23:16]
R
0h
28-bit, low-resoluton sample count.
7.6.1.1.4.13 Register 3Bh (address = 3Bh) [reset = 0h], SERDES_XX Page
图7-68. Register 3Bh
7
6
5
4
3
2
0
0
0
LOWRESCOUNT[15:8]
R-0h
LEGEND: R = Read only; -n = value after reset
表7-47. Register 3Bh Field Descriptions
Bit
Field
Type
Reset
Description
7-0
LOWRESCOUNT[15:8]
R
0h
28-bit, low-resoluton sample count.
7.6.1.1.4.14 Register 3Ch (address = 3Ch) [reset = 0h], SERDES_XX Page
图7-69. Register 3Ch
7
6
5
4
3
2
LOWRESCOUNT[7:0]
R-0h
LEGEND: R = Read only; -n = value after reset
表7-48. Register 3Ch Field Descriptions
Bit
Field
Type
Reset
Description
7-0
LOWRESCOUNT[7:0]
R
0h
28-bit, low-resoluton sample count.
7.6.1.1.4.15 Register 3Dh (address = 3Dh) [reset = 0h], SERDES_XX Page
图7-70. Register 3Dh
7
0
6
0
5
0
4
3
2
0
HIGHRESCOUNT[27:24]
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-49. Register 3Dh Field Descriptions
Bit
7-4
3-0
Field
Type
R/W
R/W
Reset
Description
0
0h
Must read or write 0
HIGHRESCOUNT[27:24]
0h
28-bit, high-resoluton sample count.
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7.6.1.1.4.16 Register 3Eh (address = 3Eh) [reset = 0h], SERDES_XX Page
图7-71. Register 3Eh
7
6
5
4
3
2
1
1
1
0
0
0
HIGHRESCOUNT[23:16]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-50. Register 3Eh Field Descriptions
Bit
Field
Type
Reset
Description
7-0
HIGHRESCOUNT[23:16]
R/W
0h
28-bit, high-resoluton sample count.
7.6.1.1.4.17 Register 3Fh (address = 3Fh) [reset = 0h], SERDES_XX Page
图7-72. Register 3Fh
7
6
5
4
3
2
HIGHRESCOUNT[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-51. Register 3Fh Field Descriptions
Bit
Field
Type
Reset
Description
7-0
HIGHRESCOUNT[15:8]
R/W
0h
28-bit, high-resoluton sample count.
7.6.1.1.4.18 Register 40h (address = 40h) [reset = 0h], SERDES_XX Page
图7-73. Register 40h
7
6
5
4
3
2
HIGHRESCOUNT[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-52. Register 40h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
HIGHRESCOUNT[7:0]
R/W
0h
28-bit, high-resoluton sample count.
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7.6.1.1.4.19 Register 41h (address = 41h) [reset = 0h], SERDES_XX Page
图7-74. Register 41h
7
6
5
4
3
2
1
0
LANE_BONA
R/W-0h
LANE_AONB
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-53. Register 41h Field Descriptions
Bit
Field
Type
Reset
Description
7-4
LANE_BONA
R/W
0h
These bits enable lane swap.
0 : Default
10 : Channel B on lane A; for SerDes CD, channel D on lane C
Others: Do not use
3-0
LANE_AONB
R/W
0h
These bits enable lane swap.
0 : Default
10 : Channel A on lane B; for SerDes CD, Channel C on lane D
Others: Do not use
7.6.1.1.4.20 Register 42h (address = 42h) [reset = 0h], SERDES_XX Page
图7-75. Register 42h
7
0
6
0
5
0
4
3
2
1
0
0
INVERT_AC
R/W-0h
INVERT_BD
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-54. Register 42h Field Descriptions
Bit
7-4
3-2
Field
Type
R/W
R/W
Reset
Description
0
0h
Must read or write 0
INVERT_AC
0h
These bits invert lanes A and C.
0 : No inversion
3 : Data inversion on lane A, C
Others: Do not use
1-0
INVERT_BD
R/W
0h
These bits invert lanes B and D.
0 : No inversion
3 : Data inversion on lane B, D
Others: Do not use
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7.6.1.1.5 CHX Page Register Description
7.6.1.1.5.1 Register 26h (address = 26h) [reset = 0h], CHX Page
图7-76. Register 26h
7
0
6
0
5
0
4
3
2
0
1
0
0
0
GAINWORD
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-55. Register 26h Field Descriptions
Bit
7-2
1-0
Field
Type
R/W
R/W
Reset
Description
0
0h
Must read or write 0
GAINWORD
0h
These bits control the channel A gain word.
0 : 0 dB
1 : 1 dB
2 : 2 dB
3 : 3 dB
7.6.1.1.5.2 Register 27h (address = 27h) [reset = 0h], CHX Page
图7-77. Register 27h
7
6
5
0
4
3
2
0
1
0
OVR_ENABLE
R/W-0h
OVR_FAST_SEL
R/W-0h
0
OVR_LSB1
R/W-0h
OVR_LSB0
R/W-0h
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-56. Register 27h Field Descriptions
Bit
Field
Type
Reset
Description
7
OVR_ENABLE
R/W
0h
This bit enables or disables the OVR on the JESD lanes.
0 : Disables OVR
1 : Enables OVR
6
OVR_FAST_SEL
R/W
0h
This bit selects the fast or delay-matched OVR
0 : Delay-matched OVR
1 : Fast OVR
5-4
3
0
R/W
R/W
0h
0h
Must read or write 0
OVR_LSB1
This bit selects either data or OVR on LSB1.
0 : Data selected
1 : OVR or FOVR selected
2
1
0
R/W
R/W
0h
0h
Must read or write 0
OVR_LSB0
This bit selects either data or OVR on LSB0.
0 : Data selected
1 : OVR or FOVR selected
0
0
R/W
0h
Must read or write 0
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7.6.1.1.5.3 Register 2Dh (address = 2Dh) [reset = 0h], CHX Page
图7-78. Register 2Dh
7
0
6
0
5
0
4
0
3
2
0
1
0
0
0
NYQUIST_SELECT
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-57. Register 2Dh Field Descriptions
Bit
7-2
1
Field
Type
R/W
R/W
Reset
Description
0
0h
Must read or write 0
NYQUIST_SELECT
0h
This bit selects the Nyquist zone of operation for trim loading.
0 : Nyquist 1
1 : Nyquist 2
0
0
R/W
0h
Must read or write 0
7.6.1.1.5.4 Register 78h (address = 78h) [reset = 0h], CHX Page
图7-79. Register 78h
7
0
6
0
5
0
4
0
3
2
1
0
0
FS4_SIGN
R/W-0h
NYQ_SEL_MODE02
R/W-0h
NYQ_SEL
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-58. Register 78h Field Descriptions
Bit
7-3
2
Field
Type
R/W
R/W
Reset
Description
0
0h
Must read or write 0
FS4_SIGN
0h
This bit controls the sign of mixing in mode 0.
0 : Centered at –fS / 4
1 : Centered at fS / 4
1
0
NYQ_SEL_MODE02
NYQ_SEL
R/W
R/W
0h
0h
This bit selects the pass band of the decimation filter in mode 2.
0 : Low pass
1 : High pass
This bit selects the pass band of the filter before the DDC.
0 : LPF (0 –fS / 2)
1 : HPF (0 –fS / 2)
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7.6.1.1.5.5 Register 7Ah (address = 7Ah) [reset = 0h], CHX Page
图7-80. Register 7Ah
7
6
5
4
3
2
1
0
NCO_WORD[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-59. Register 7Ah Field Descriptions
Bit
Field
Type
Reset
Description
7-0
NCO_WORD[15:8]
R/W
0h
These bits set the NCO frequency word.
0 : 0 × fS / 216
1 : 1 × fS / 216
2 : 2 × fS / 216
3 : 3 × fS / 216
5 : 5 × fS / 216
6 : 6 × fS / 216
…
65535 : 65535 × fS / 216
7.6.1.1.5.6 Register 7Bh (address = 7Bh) [reset = 0h], CHX Page
图7-81. Register 7Bh
7
6
5
4
3
2
1
0
NCO_WORD[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-60. Register 7Bh Field Descriptions
Bit
Field
Type
Reset
Description
7-0
NCO_WORD[7:0]
R/W
0h
These bits set the NCO frequency word.
0 : 0 × fS / 216
1 : 1 × fS / 216
2 : 2 × fS / 216
3 : 3 × fS / 216
5 : 5 × fS / 216
6 : 6 × fS / 216
…
65535 : 65535 × fS / 216
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7.6.1.1.5.7 Register 7Eh (address = 7Eh) [reset = 3h], CHX Page
图7-82. Register 7Eh
7
0
6
0
5
0
4
0
3
2
1
0
0
MODE467_GAIN
R/W-0h
MODE0_GAIN
R/W-1h
MODE13_GAIN
R/W-1h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-61. Register 7Eh Field Descriptions
Bit
7-3
2
Field
Type
R/W
R/W
Reset
Description
0
0h
Must read or write 0
MODE467_GAIN
0h
This bit sets the mixer loss compensation for modes 4, 6, and 7.
0 : No gain
1 : 6-dB gain
1
0
MODE0_GAIN
MODE13_GAIN
R/W
R/W
1h
1h
This bit sets the mixer loss compensation for mode 0.
0 : No gain
1 : 6-dB gain
This bit sets the mixer loss compensation for modes 1 and 3.
0 : No gain
1 : 6-dB gain
7.6.1.1.6 ADCXX Page Register Description
7.6.1.1.6.1 Register 07h (address = 07h) [reset = FFh], ADCXX Page
图7-83. Register 7h
7
6
5
4
3
2
1
0
FAST_OVR_THRESHOLD_HIGH
R/W-FFh
LEGEND: R/W = Read/Write; -n = value after reset
表7-62. Register 07h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
FAST_OVR_THRESHOLD_HIGH
R/W
FFh
Fast OVR threshold high; see the 节7.4.1.14 section for
programming.
7.6.1.1.6.2 Register 08h (address = 08h) [reset = 0h], ADCXX Page
图7-84. Register 8h
7
6
5
4
3
2
1
0
FAST_OVR_THRESHOLD_LOW
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-63. Register 08h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
FAST_OVR_THRESHOLD_LOW
R/W
0h
Fast OVR threshold low; see the 节7.4.1.14 section for
programming.
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7.6.1.1.6.3 Register D5h (address = D5h) [reset = 0h], ADCXX Page
图7-85. Register D5h
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
CAL_EN
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
表7-64. Register D5h Field Descriptions
Bit
7-4
3
Field
0
Type
R/W
R/W
Reset
Description
0h
Must read or write 0
CAL_EN
0h
This bit is the enable calibration bit. This bit must be toggled
during the startup sequence.
0 : Disables calibration
1 : Enables calibration
2-0
0
R/W
0h
Must read or write 0
8 Application and Implementation
8.1 Application Information
8.1.1 Start-Up Sequence
表 8-1 lists the recommended start-up sequence for a 500-MSPS, Nyquist 2 operation with DDC mode 0
enabled.
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表8-1. Recommended Start-Up Sequence for 500-MSPS, Nyquist 2, DDC Mode 0 Operation
REGISTER
ADDRESS
REGISTER
DATA
STEP
DESCRIPTION
COMMENT
1
2
Provide a 1.15-V power supply (AVDD, DVDD, IOVDD)
Provide a 1.9-V power supply (AVDD19)
—
—
—
—
—
A 1.15-V supply must be supplied first for
proper operation.
Provide a clock to CLKINM, CLKINP and a SYSREF signal to
SYSREFM, SYSREFP
SYSREF must be established before SPI
programming.
3
—
—
—
—
Pulse a reset (low to high to low) via a hardware reset (pin 50),
wait 100 µs
4
5
Hardware reset loads all trim register settings.
Issue a software reset to initialize the registers
00h
11h
12h
13h
ABh
ACh
64h
11h
12h
13h
26h
20h
11h
12h
13h
D5h
81h
00h
01h
00h
01h
01h
02h
00h
60h
00h
0Fh
80h
FFh
00h
00h
08h
—
Select the DIGTOP page.
Set the high SNR mode for channels AB and CD, select trims
for 500-MSPS operation
6
7
Set the high SNR mode for channel A and B.
Set the high SNR mode for channel C and D.
Select trims for 500-MSPS operation.
Select the SerDes_AB and SerDes_CD
pages.
Set up the SerDes configuration
Set the K value to 16 frames per multi-frame.
Enable the K value from register 26h.
Select the ADC_A1, ADC_A2, ADC_B1,
ADC_B2, ADC_C1, ADC_C2, ADC_D1, and
ADC_D2 pages.
Enable ADC calibration.
ADC calibration time.
Disable ADC calibration.
8
ADC calibration
Wait 2 ms
D5h
2Ah
CFh
11h
12h
13h
2Dh
11h
12h
13h
8Ch
B7h
B7h
11h
12h
13h
6Ah
00h
00h
50h
00h
1Eh
00h
02h
00h
01h
00h
02h
01h
00h
00h
00h
01h
02h
Internal trims.
Select the channel A, channel B, channel C,
and channel D pages.
9
Select trims for the second Nyquist
Select trims for the second Nyquist.
Select the DIGTOP page.
10
11
Load linearity trims
Load linearity trims.
Select the ANALOG page.
Disable SYSREF.
Disable SYSREF
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表 8-2 shows the recommended start-up sequence for a 375-MSPS, Nyquist 2 operation with DDC mode 0
enabled.
表8-2. Recommended Start-Up Sequence for 375-MSPS, Nyquist 2, DDC Mode 0 Operation
REGISTER
ADDRESS
REGISTER
DATA
STEP
DESCRIPTION
COMMENT
1
2
Provide a 1.15-V power supply (AVDD, DVDD, IOVDD)
Provide a 1.9-V power supply (AVDD19)
—
—
—
—
—
A 1.15-V supply must be supplied first for
proper operation.
Provide a clock to CLKINM, CLKINP and a SYSREF signal to
SYSREFM, SYSREFP
SYSREF must be established before SPI
programming.
3
—
—
—
—
Pulse a reset (low to high to low) via a hardware reset (pin 50),
wait 100 µs
4
5
Hardware reset loads all trim register settings.
Issue a software reset to initialize registers
00h
11h
12h
13h
ABh
ACh
11h
12h
13h
26h
20h
11h
12h
13h
D5h
81h
00h
01h
00h
01h
01h
00h
60h
00h
0Fh
80h
FFh
00h
00h
08h
—
Select the DIGTOP page.
6
7
Set the high SNR mode for channels AB and CD
Set the high SNR mode for channel A and B.
Set the high SNR mode for channel C and D.
Select the SerDes_AB and SerDes_CD
pages.
Set up the SerDes configuration
Set the K value to 16 frames per multi-frame.
Enable the K value from register 26h.
Select the ADC_A1, ADC_A2, ADC_B1,
ADC_B2, ADC_C1, ADC_C2, ADC_D1, and
ADC_D2 pages.
Enable ADC calibration.
ADC calibration time.
Disable ADC calibration.
8
ADC calibration
Wait 2 ms
D5h
2Ah
CFh
11h
12h
13h
2Dh
11h
12h
13h
8Ch
B7h
B7h
11h
12h
13h
6Ah
00h
00h
50h
00h
1Eh
00h
02h
00h
01h
00h
02h
01h
00h
00h
00h
01h
02h
Internal trims.
Select the channel A, channel B, channel C,
and channel D pages.
9
Select trims for the second Nyquist.
Select trims for the second Nyquist.
Select the DIGTOP page.
10
11
Load linearity trims
Load linearity trims.
Select the ANALOG page.
Disable SYSREF.
Disable SYSREF
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8.1.2 Hardware Reset
Timing information for the hardware reset is shown in 图8-1.
Power Supplies
t1
RESET
t2
t3
SEN
图8-1. Hardware Reset Timing Diagram
表8-3. Timing Requirements for 图8-1
MIN
1
TYP MAX UNIT
t1
t2
t3
Power-on delay from power-up to active high RESET pulse
ms
ns
µs
Reset pulse duration: active high RESET pulse duration
Register write delay from RESET disable to SEN active
10
100
8.1.3 Frequency Planning
The ADS58J64 uses an architecture where the ADCs are 2x interleaved followed by a digital decimation by 2.
The 2x interleaved and decimation architecture comes with a unique advantage of improved linearity resulting
from frequency planning. Frequency planning refers to choosing the clock frequency and signal band
appropriately such that the harmonic distortion components, resulting from the analog front-end (LNA, PGA), can
be made to fall outside the decimation filter pass band. In absence of the 2x interleave and decimation
architecture, these components alias back in band and limit the performance of the signal chain. For example,
for fCLK = 983.04 MHz and fIN = 184.32 MHz:
Second-order harmonic distortion (HD2) = 2 × 184.32 = 368.64 MHz
Pass band of the 2x decimation filter = 0 MHz to 245.76 MHz (0 to fCLK / 4)
The second-order harmonic performance improves by the stop-band attenuation of the filter (approximately
40 dBc) because the second-order harmonic frequency is outside the pass band of the decimation filter.
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图 8-2 shows the harmonic components (HD2–HD5) that fall in the decimation pass band for the input clock
rate (fCLK) of the 983.04-MHz and 100-MHz signal band around the center frequency of 184.32 MHz.
275
225
175
125
1
2
3 4
Signal Harmonic
5
6
D046
fCLK = 983.04 MHz, signal band = 134.32 MHz to 234.32 MHz
图8-2. In-Band Harmonics for a Frequency Planned System
As shown in 图 8-2, both HD2 and HD3 are completely out of band. HD4 and HD5 fall in the decimation pass
band for some frequencies of the input signal band.
Through proper frequency planning, the specifications of the ADC antialias filter can be relaxed.
8.1.4 SNR and Clock Jitter
The signal-to-noise ratio of the ADC is limited by three different factors (as shown in 方程式 3): the quantization
noise is typically not noticeable in pipeline converters and is 84 dB for a 14-bit ADC. The thermal noise limits the
SNR at low input frequencies and the clock jitter sets the SNR for higher input frequencies.
(3)
The SNR limitation resulting from sample clock jitter can be calculated by 方程式4:
(4)
The total clock jitter (TJitter) has two components: the internal aperture jitter (100 fs for the ADS58J64) that is set
by the noise of the clock input buffer and the external clock jitter. TJitter can be calculated by 方程式5:
(5)
External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-
pass filters at the clock input; a faster clock slew rate also improves the ADC aperture jitter.
The ADS58J64 has a thermal noise of approximately 70 dBFS and an internal aperture jitter of 100 fs.
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8.1.5 ADC Test Pattern
The ADS58J64 provides several different options to output test patterns instead of the actual output data of the
ADC in order to simplify debugging of the JESD204B digital interface link. The output data path is shown in 图
8-3.
ADC Section
Transport Layer
Link Layer
PHY Layer
DDC
ADC
Data Mapping
Frame Construction
8b/10b
Encoding
Interleaving
Correction
Burst
Mode
Scrambler
1+x14+x15
Serializer
ADC Test
Pattern
JESD204B Long
Transport Layer
Test Pattern
JESD204B
Link Layer
Test Pattern
图8-3. ADC Test Pattern
8.1.5.1 ADC Section
The ADC test pattern replaces the actual output data of the ADC. These test patterns can be programmed using
register 91h of the DIGTOP page. The supported test patterns are shown in 表8-4.
表8-4. ADC Test Pattern Settings
BIT
NAME
DEFAULT
DESCRIPTION
These bits select the test pattern on the output when the test pattern
is enabled for a suitable channel.
0 : Default
1 : All zeros
2 : All ones
3 : Toggle pattern
7-4
TESTPATTERNSELECT
0000
4 : Ramp pattern
6 : Custom pattern 1
7 : Toggles between custom pattern 1 and custom pattern 2
8 : Deskew pattern (AAAAh)
8.1.5.2 Transport Layer Pattern
The transport layer maps the ADC output data into 8-bit octets and constructs the JESD204B frames using the
LMFS parameters. Tail bits or 0s are added when needed. Alternatively, the JESD204B long transport layer test
pattern can be substituted by programming register 20h, as shown in 表8-5.
表8-5. Transport Layer Test Mode
BIT
NAME
DEFAULT
DESCRIPTION
This bit generates the long transport layer test pattern mode
according to clause 5.1.6.3 of the JESD204B specification.
0 = Test mode disabled
4
TRANS_TEST_EN
0
1 = Test mode enabled
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8.1.5.3 Link Layer Pattern
The link layer contains the scrambler and the 8b, 10b encoding of any data passed on from the transport layer.
Additionally, the link layer also handles the initial lane alignment sequence that can be manually restarted. The
link layer test patterns are intended for testing the quality of the link (jitter testing and so forth). The test patterns
do not pass through the 8b, 10b encoder. These test patterns can be used by programming register 22h of the
SERDES_XX page. 表8-6 shows the supported programming options.
表8-6. Link Layer Test Mode
BIT
NAME
DEFAULT
DESCRIPTION
These bits generate a pattern according to clause 5.3.3.8.2 of the
JESD204B document.
0 : Normal ADC data
1 : D21.5 (high-frequency jitter pattern)
2 : K28.5 (mixed-frequency jitter pattern)
3 : Repeats initial lane alignment (generates a K28.5 character and
continuously repeats lane alignment sequences)
4 : 12-octet RPAT jitter pattern
7-5
LINK_LAYER_TESTMODE_SEL
000
6 : PRBS pattern (PRBS7,15,23,31); use PRBS mode (register 36h)
to select the PRBS pattern
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8.2 Typical Application
The ADS58J64 is designed for wideband receiver applications demanding excellent dynamic range over a large
input frequency range. A typical schematic for an ac-coupled dual receiver [dual field-programmable gate array
(FPGA) with a dual SYNC] is shown in 图8-4.
DVDD
5 ꢀ
10 kꢀ
25 ꢀ
25 ꢀ
25 ꢀ
3.3 pF
0.1 uF
0.1 uF
GND
Driver
SPI Master
25 ꢀ
5 ꢀ
GND
DVDD
0.1 uF
GND
0.1 uF
GND
0.1 uF
AVDD
0.1 uF
DVDD
AVDD19
AVDD
5 ꢀ
AVDD19
25 ꢀ
25 ꢀ
25 ꢀ
3.3 pF
25 ꢀ
0.1 uF
0.1 uF
100 ꢀ Differential
Driver
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
5 ꢀ
GND
INCP
SYNCbCDP
SYNCbCDM
19
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
50 ꢀ
50 ꢀ
Vterm=1.2 V
AVDD
AGND
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
AVDD
FPGA
0.1 uF
GND
DVDD
10 nF
GND
DVDD
DDP
10 nF
NC
NC
DDM
GND
0.1 uF
AVDD19
AVDD
DGND
DCP
AVDD19
10 nF
GND
AVDD
0.1 uF
DCM
AGND
GND
10 nF
DVDD
0.1 uF
GND
DVDD
DGND
DBM
CLKINP
CLKINM
AGND
100 ꢀ
ADS58J64
GND PAD (backside)
GND
0.1 uF
AVDD
DBP
Low Jitter
Clock
Generator
AVDD
DGND
DAM
AVDD19
AGND
10 nF
AVDD19
0.1 uF
GND
GND
DAP
SYSREFP
100 ꢀ
DVDD
DVDD
SYNCbABM
SYNCbABP
SYSREFM
AVDD
10 nF
10 nF
GND
Vterm=1.2 V
AVDD
50 ꢀ
50 ꢀ
5 ꢀ
FPGA
INBP
25 ꢀ
25 ꢀ
25 ꢀ
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
0.1 uF
0.1 uF
GND
100 ꢀ Differential
3.3 pF
Driver
25 ꢀ
5 ꢀ
AVDD19
DVDD
0.1 uF
AVDD
AVDD
AVDD19
0.1 uF
GND
GND
0.1 uF
GND
DVDD
GND
5 ꢀ
25 ꢀ
25 ꢀ
3.3 pF
25 ꢀ
0.1 uF
0.1 uF
GND
Driver
25 ꢀ
5 ꢀ
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NOTE: GND = AGND and DGND are connected in the PCB layout.
图8-4. Application Diagram for the ADS58J64
8.2.1 Design Requirements
By using the simple drive circuit of 图8-4 (when the amplifier drives the ADC) or 图7-1 (when transformers drive
the ADC), uniform performance can be obtained over a wide frequency range. The buffers present at the analog
inputs of the device help isolate the external drive source from the switching currents of the sampling circuit.
8.2.2 Detailed Design Procedure
For optimum performance, the analog inputs must be driven differentially. This architecture improves the
common-mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with
each input pin is recommended to damp out ringing caused by package parasitics, as shown in 图8-4.
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8.2.3 Application Curves
图8-5 and 图8-6 show the typical performance at 190 MHz and 230 MHz, respectively.
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
50
100 150
Input Frequency (MHz)
200
250
0
50
100 150
Input Frequency (dBFS)
200
250
D002
D006
fIN = 190 MHz, AIN = –1 dBFS, SNR = 69.4 dBFS, SFDR =
fIN = 230 MHz, AIN = –1 dBFS, SNR = 69.4 dBFS, SFDR =
88 dBc, SFDR = 96 dBc (non 23)
85 dBc, SFDR = 96 dBc (non 23)
图8-5. FFT for 190-MHz Input Signal
图8-6. FFT for 230-MHz Input Signal
9 Power Supply Recommendations
The device requires a 1.15-V nominal supply for DVDD, a 1.15-V nominal supply for AVDD, and a 1.9-V nominal
supply for AVDD19. AVDD and DVDD are recommended to be powered up the before AVDD19 supply for
reliable loading of factory trims.
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10 Layout
10.1 Layout Guidelines
The device evaluation module (EVM) layout can be used as a reference layout to obtain the best performance. A
layout diagram of the EVM top layer is provided in 图 10-1. A complete layout of the EVM is available at the
ADS58J64 EVM folder. Some important points to remember during board layout are:
• Analog inputs are located on opposite sides of the device pinout to ensure minimum crosstalk on the package
level. To minimize crosstalk onboard, the analog inputs must exit the pinout in opposite directions, as shown
in the reference layout of 图10-1 as much as possible.
• In the device pinout, the sampling clock is located on a side perpendicular to the analog inputs in order to
minimize coupling between them. This configuration is also maintained on the reference layout of 图10-1 as
much as possible.
• Keep digital outputs away from the analog inputs. When these digital outputs exit the pinout, the digital output
traces must not be kept parallel to the analog input traces because this configuration can result in coupling
from the digital outputs to the analog inputs and degrade performance. All digital output traces to the receiver
[such as an FPGA or an application-specific integrated circuit (ASIC)] must be matched in length to avoid
skew among outputs.
• At each power-supply pin (AVDD, DVDD, or AVDD19), keep a 0.1-µF decoupling capacitor close to the
device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF
capacitors can be kept close to the supply source.
10.2 Layout Example
Sampling Clock
Analog Input
Routing
Routing
GND
(Thermal Pad)
ADS58J6x
SERDES output
Routing
图10-1. ADS58J64EVM Layout
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11 Device and Documentation Support
11.1 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS58J64IRMPR
ADS58J64IRMPT
ADS58J64IRRHR
ADS58J64IRRHT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
RMP
RMP
RRH
RRH
72
72
72
72
1500 RoHS & Green
250 RoHS & Green
1500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
AZ58J64
NIPDAU
NIPDAU
NIPDAU
AZ58J64
AZ58J64
AZ58J64
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Dec-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS58J64IRMPR
ADS58J64IRRHR
VQFN
VQFN
RMP
RRH
72
72
1500
1500
330.0
330.0
24.4
24.4
10.25 10.25 2.25
10.25 10.25 2.25
16.0
16.0
24.0
24.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS58J64IRMPR
ADS58J64IRRHR
VQFN
VQFN
RMP
RRH
72
72
1500
1500
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
RMP0072A
VQFN - 0.9 mm max height
SCALE 1.700
VQFN
10.1
9.9
A
B
PIN 1 ID
10.1
9.9
0.9 MAX
0.05
0.00
C
SEATING PLANE
0.08 C
(0.2)
4X (45 X0.42)
19
36
18
37
SYMM
4X
8.5
8.5 0.1
PIN 1 ID
(R0.2)
1
54
0.30
0.18
72X
72
55
68X 0.5
SYMM
0.5
0.3
0.1
C B
A
72X
0.05
C
4221047/B 02/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RMP0072A
VQFN - 0.9 mm max height
VQFN
(
8.5)
SYMM
72X (0.6)
SEE DETAILS
55
72
1
54
72X (0.24)
(0.25) TYP
SYMM
(9.8)
(1.315) TYP
68X (0.5)
(
0.2) TYP
VIA
37
18
19
36
(1.315) TYP
(9.8)
LAND PATTERN EXAMPLE
SCALE:8X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4221047/B 02/2014
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON PCB application report
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RMP0072A
VQFN - 0.9 mm max height
VQFN
(9.8)
72X (0.6)
(1.315) TYP
72
55
1
54
72X (0.24)
(1.315)
TYP
(0.25) TYP
SYMM
(9.8)
(1.315)
TYP
68X (0.5)
METAL
TYP
37
18
(
0.2) TYP
VIA
19
36
36X ( 1.115)
(1.315) TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
62% PRINTED SOLDER COVERAGE BY AREA
SCALE:8X
4221047/B 02/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
RRH0072A
VQFN - 1 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
10.1
9.9
A
B
PIN 1 INDEX AREA
10.1
9.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2X 8.5
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
19
36
18
37
SYMM
73
2X 8.5
8.5 0.1
1
54
0.3
0.2
68X 0.5
PIN 1 ID
72
55
72X
0.5
0.3
0.1
C A B
72X
0.05
4224461/A 08/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RRH0072A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
8.5)
SEE SOLDER MASK
DETAIL
SYMM
55
72
72X (0.6)
72X (0.25)
1
54
68X (0.5)
(4) TYP
(R0.05) TYP
(1.14) TYP
(0.57) TYP
(
0.2) TYP
VIA
SYMM
73
(9.8)
18
37
19
36
(0.57) TYP
(1.14)
TYP
(4) TYP
(9.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224461/A 08/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RRH0072A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.42)
(1.14) TYP
72
55
72X (0.6)
72X (0.25)
1
54
68X (0.5)
(1.14)
TYP
(R0.05) TYP
(3.42)
73
(9.8)
SYMM
49X (0.94)
37
18
19
36
SYMM
49X (0.94)
(9.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 73
60% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4224461/A 08/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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