ADS6122IRHBTG4 [TI]
12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS; 12位， 125/105/80/65 MSPS的DDR LVDS / CMOS输出的ADC
| 型号： | ADS6122IRHBTG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS |
| 文件： | 总67页 (文件大小：2167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER 2007–REVISED MARCH 2008
12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
1
FEATURES
DESCRIPTION
•
•
•
Maximum Sample Rate: 125 MSPS
12-Bit Resolution with No Missing Codes
ADS6125/ADS6124/ADS6123/ADS6122 (ADS612X)
is a family of 12-bit A/D converters with sampling
frequencies up to 125 MSPS. It combines high
3.5 dB Coarse Gain and up to 6 dB
Programmable Fine Gain for SNR/SFDR
Trade-Off
performance and low power consumption in
a
compact 32 QFN package. Using an internal high
bandwidth sample and hold and a low jitter clock
buffer helps to achieve high SNR and high SFDR
even at high input frequencies.
•
•
Parallel CMOS and Double Data Rate (DDR)
LVDS Output Options
Supports Sine, LVCMOS, LVPECL, LVDS Clock
Inputs and Clock Amplitude Down to 400 mVPP
It features coarse and fine gain options that are used
to improve SFDR performance at lower full-scale
analog input ranges.
•
•
Clock Duty Cycle Stabilizer
Internal Reference with Support for External
Reference
The digital data outputs are either parallel CMOS or
DDR LVDS (Double Data Rate). Several features
exist to ease data capture such as — controls for
output clock position and output buffer drive strength,
and LVDS current and internal termination
programmability.
•
•
No External Decoupling Required for
References
Programmable Output Clock Position and
Drive Strength to Ease Data Capture
•
•
•
3.3 V Analog and 1.8 V to 3.3 V Digital Supply
32-QFN Package (5 mm × 5 mm)
The output interface type, gain, and other functions
are programmed using a 3-wire serial interface.
Alternatively, some of these functions are configured
using dedicated parallel pins so that the device
comes up in the desired state after power-up.
Pin Compatible 12-Bit Family (ADS612X)
APPLICATIONS
•
•
•
•
•
•
•
•
Wireless Communications Infrastructure
Software Defined Radio
Power Amplifier Linearization
802.16d/e
Test and Measurement Instrumentation
High Definition Video
ADS612X includes internal references, while
eliminating the traditional reference pins and
associated external decoupling. External reference
mode is also supported.
The devices are specified over the industrial
temperature range (–40°C to 85°C).
Medical Imaging
Radar Systems
ADS612X Performance Summary
ADS6125
90
ADS6124
91
ADS6123
93
ADS6122
95
Fin = 10 MHz (0 dB gain)
Fin = 170 MHz (3.5 dB gain)
Fin = 10 MHz (0 dB gain)
Fin = 170 MHz (3.5 dB gain)
Power, mW
SFDR, dBc
78
82
83
84
71.1
67.6
417
71.3
69.1
374
71.5
69.2
318
71.6
69.8
285
SINAD, dBFS
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER 2007–REVISED MARCH 2008
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
CLKP
CLKOUTP
CLKOUTM
CLOCK
GEN
CLKM
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
Digital
Encoder
and
INP
INM
12-Bit
ADC
D6_D7_P
D6_D7_M
SHA
Serializer
D8_D9_P
D8_D9_M
D10_D11_P
D10_D11_M
Control
Interface
VCM
Reference
ADS612X
LVDS MODE
ADS61XX FAMILY
125 MSPS
105 MSPS
80 MSPS
65 MSPS
ADS614X
14 Bits
ADS6145
ADS6144
ADS6143
ADS6142
ADS612X
12 Bits
ADS6125
ADS6124
ADS6123
ADS6122
2
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Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER 2007–REVISED MARCH 2008
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
PRODUCT
TRANSPORT MEDIA
ADS6125IRHBT
ADS6125IRHBR
ADS6124IRHBT
ADS6124IRHBR
ADS6123IRHBT
ADS6123IRHBR
ADS6122IRHBT
ADS6122IRHBR
Tape and Reel, small
Tape and Reel, large
Tape and Reel, small
Tape and Reel, large
Tape and Reel, small
Tape and Reel, large
Tape and Reel, small
Tape and Reel, large
ADS6125
ADS6124
ADS6123
ADS6122
QFN-32(2)
QFN-32(2)
QFN-32(2)
QFN-32(2)
RHB
RHB
RHB
RHB
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
AZ6125
AZ6124
AZ6123
AZ6122
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θJA = 34 °C/W (0 LFM air flow),
θJC = 30 °C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in × 3 in (7.62 cm ×
7.62 cm) PCB.
ABSOLUTE MAXIMUM RATINGS(1)
VALUE
–0.3 to 3.9
UNIT
V
Supply voltage range, AVDD
VI
Supply voltage range, DRVDD
–0.3 to 3.9
V
Voltage between AGND and DRGND
Voltage between AVDD to DRVDD
–0.3 to 0.3
V
–0.3 to 3.3
V
Voltage applied to VCM pin (in external reference mode)
Voltage applied to analog input pins, INP and INM
Voltage applied to analog input pins, CLKP and CLKM
Operating free-air temperature range
Operating junction temperature range
Storage temperature range
–0.3 to 2
V
–0.3 to minimum ( 3.6, AVDD + 0.3)
–0.3 to (AVDD + 0.3)
–40 to 85
V
V
TA
°C
°C
°C
TJ
125
Tstg
–65 to 150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Copyright © 2007–2008, Texas Instruments Incorporated
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ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER 2007–REVISED MARCH 2008
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage
3
3.3
3.6
V
CMOS Interface
LVDS Interface
1.65 1.8 to 3.3
3.6
3.6
V
V
(1)
DRVDD Output buffer supply voltage
3
3.3
ANALOG INPUTS
Differential input voltage range
Input common-mode voltage
2
1.5 ± 0.1
1.5
Vpp
V
VIC
Voltage applied on VCM in external reference mode
CLOCK INPUT
1.45
1.55
V
ADS6125
1
1
125
105
80
ADS6124
FS
Input clock sample rate
MSPS
ADS6123
1
ADS6122
1
65
Sine wave, ac-Coupled
LVPECL, ac-Coupled
LVDS, ac-Coupled
LVCMOS, ac-Coupled
0.4
1.5
± 0.8
± 0.35
3.3
Input clock amplitude differential
(VCLKP – VCLKM
Vpp
)
Input Clock duty cycle
DIGITAL OUTPUTS
35%
50%
65%
For CLOAD ≤ 5 pF and DRVDD ≥ 2.2
V
DEFAULT
strength
For CLOAD > 5 pF and DRVDD ≥ 2.2
V
MAXIMUM
strength
(2)
Output buffer drive strength
MAXIMUM
strength
For DRVDD < 2.2 V
CMOS Interface, maximum buffer
strength
10
Maximum external load capacitance from each LVDS Interface, without internal
5
CLOAD
pF
output pin to DRGND
termination
LVDS Interface, with internal
termination
10
RLOAD
TA
Differential load resistance (external) between the LVDS output pairs
Operating free-air temperature
100
Ω
-40
85
°C
(1) For easy migration to next generation, higher sampling speed devices (> 125 MSPS), use 1.8V DRVDD supply.
(2) See Output Buffer Strength Programmability in application section
4
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Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER 2007–REVISED MARCH 2008
ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
DRVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input, internal
reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted.
ADS6125
ADS6124
ADS6123
ADS6122
FS = 125 MSPS
FS = 105 MSPS
FS = 80 MSPS
FS = 65 MSPS
PARAMETER
UNIT
MIN
TYP MAX
MIN
TYP MAX
MIN
TYP MAX
MIN
TYP MAX
RESOLUTION
12
12
12
12
Bits
ANALOG INPUT
Differential input voltage range
2
2
2
2
VPP
Differential input resistance (at dc)
see Figure 91
> 1
> 1
> 1
> 1
MΩ
Differential input capacitance
see Figure 92
7
450
180
7
450
151
7
450
114
7
450
92
pF
MHz
µA
Analog input bandwidth
Analog input common mode current
(per input pin of each ADC)
REFERENCE VOLTAGES
VREFB
VREFT
ΔVREF
Internal reference bottom voltage
Internal reference top voltage
1
2
1
2
1
2
1
2
V
V
Internal reference error
(VREFT–VREFB)
-20
-10
± 5
1.5
20
10
-20
-10
± 5
1.5
20
10
-20
-10
± 5
1.5
20
10
-20
-10
± 5
1.5
20
10
mV
V
VCM
Common mode output voltage
DC ACCURACY
No missing codes
Specified
± 2
Specified
± 2
Specified
± 2
Specified
± 2
EO
Offset error
mV
Offset error temperature coefficient
0.05
0.05
0.05
0.05
mV/°C
There are two sources of gain error – internal reference inaccuracy and channel gain error
Gain error due to internal reference
EGREF
-1
0.25
1
-1
0.25
1
-1
-1
0.25
±0.3
1
1
-1
-1
0.25
±0.3
1
1
% FS
% FS
Δ%/°C
inaccuracy alone, (ΔVREF /2) %
EGCHAN
Gain error of channel alone(1)
-1
±0.3
1
-1
±0.3
1
Channel gain error temperature
coefficient
0.005
0.005
0.005
0.005
DNL
INL
Differential nonlinearity
Integral nonlinearity
-0.75 ± 0.6
2
2
-0.75 ± 0.6
2
2
-0.75 ± 0.5
2
2
-0.75 ± 0.5
2
2
LSB
LSB
-2
± 1
123
6.1
-2
± 1
110
5.4
-2
± 1
-2
± 1
POWER SUPPLY
IAVDD
Analog supply current
94
84
mA
mA
Digital supply current, CMOS
interface
DRVDD = 1.8 V
IDRVDD
4.5
4.0
(2)
No load capacitance, FIN= 2 MHZ
Digital supply current, LVDS interface
DRVDD = 3.3 V
IDRVDD
42
42
42
42
mA
With 100 Ω external termination
Total power, CMOS
417
30
625
60
374
30
525
60
318
30
440
60
285
30
400
60
mW
mW
Global power down
(1) This is specified by design and characterization; it is not tested in production.
(2) In CMOS mode, the DRVDD current scales with the sampling frequency and the load capacitance on output pins (see Figure 84).
Copyright © 2007–2008, Texas Instruments Incorporated
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ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER 2007–REVISED MARCH 2008
ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
DRVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input, internal
reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted.
ADS6125
ADS6124
ADS6123
ADS6122
FS = 125 MSPS
FS = 105 MSPS
FS = 80 MSPS
FS = 65 MSPS
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP MAX
MIN
TYP MAX
MIN
TYP MAX
MIN
TYP MAX
DYNAMIC AC CHARACTERISTICS
Fin = 10 MHz
71.3
71.1
70.9
69.5
71.4
71.1
71
71.6
71.4
71.3
70.3
71.7
71.5
71.5
70.6
Fin = 50 MHz
68.5
68.5
68
69
Fin = 70 MHz
68.5
68.5
68
69
SNR
Signal to noise
ratio, CMOS
0 dB Gain
70
Fin = 170
MHz
dBFS
3.5 dB Coarse
gain
68.7
68.6
67.9
69.4
69.2
68.6
69.7
69.6
69.1
69.9
69.9
69.4
0 dB Gain
Fin = 230
MHz
3.5 dB Coarse
gain
Fin = 10 MHz
Fin = 50 MHz
Fin = 70 MHz
71.5
71.4
71.3
70.3
71.5
71.3
71.3
70.3
71.8
71.5
71.5
70.6
71.8
71.6
71.6
70.7
69
69
SNR
Signal to noise
ratio, LVDS
0 dB Gain
Fin = 170
MHz
dBFS
3.5 dB Coarse
gain
69.8
69.6
69
69.8
69.6
69
70.1
70
70.1
70.1
69.6
0 dB Gain
Fin = 230
MHz
3.5 dB Coarse
gain
69.5
Fin = 10 MHz
Fin = 50 MHz
Fin = 70 MHz
71.1
70.3
70.4
67.7
71.3
70.7
70.9
69.5
71.5
71.3
70.9
69.6
71.6
71.4
71.4
70.2
68.5
68.5
SINAD
Signal to noise
and distortion
ratio
0 dB Gain
Fin = 170
MHz
dBFS
3.5 dB Coarse
gain
67.6
66.6
66.3
69.1
68
69.2
68.9
68.6
69.8
69.1
69
CMOS
0 dB Gain
Fin = 230
MHz
3.5 dB Coarse
gain
68
Fin = 10 MHz
Fin = 50 MHz
Fin = 70 MHz
71.5
70.6
71
71.5
70.7
71
71.7
71.4
71.1
70.1
71.7
71.5
71.5
70.3
SINAD
Signal to noise
and distortion
ratio
0 dB Gain
69.1
69.7
Fin = 170
MHz
dBFS
3.5 dB Coarse
gain
69.3
68.2
68.3
11.4
69.5
68.1
68.3
69.9
69.4
69.2
70
69.1
69.1
LVDS
0 dB Gain
Fin = 230
MHz
3.5 dB Coarse
gain
ENOB
Effective
number of bits
Fin = 50 MHz
Fin = 70 MHz
11
76
11 11.55
Bits
11
76
11.5
11 11.56
Fin = 10 MHz
Fin = 50 MHz
Fin = 70 MHz
90
80
84
76
91
83
84
80
93
95
89
79
89
84
81
79
86
82
SFDR
Spurious free
dynamic range
0 dB Gain
Fin = 170
MHz
dBc
3.5 dB Coarse
gain
78
75
76
82
77
79
83
79
81
84
79
82
0 dB Gain
Fin = 230
MHz
3.5 dB Coarse
gain
6
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ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER 2007–REVISED MARCH 2008
ELECTRICAL CHARACTERISTICS (continued)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
DRVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input, internal
reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted.
ADS6125
ADS6124
ADS6123
ADS6122
FS = 125 MSPS
FS = 105 MSPS
FS = 80 MSPS
FS = 65 MSPS
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP MAX
MIN
TYP MAX
MIN
TYP MAX
MIN
TYP MAX
Fin = 10 MHz
88.5
79.5
82
90
82.5
83
91.5
88
93
88
85
80
Fin = 50 MHz
Fin = 70 MHz
73
76
76
76
79
79
73
76
76
83
76
79
79
THD
0 dB Gain
73.5
79
78
Fin = 170
MHz
Total harmonic
distortion
dBc
3.5 dB Coarse
gain
75
71.5
72.5
81
75.5
77.5
79
76
78
82
76
0 dB Gain
Fin = 230
MHz
3.5 dB Coarse
gain
78.5
Fin = 10 MHz
Fin = 50 MHz
Fin = 70 MHz
96
95
91
81
96
96
92
83
97
96
93
83
98
96
93
86
HD2
0 dB Gain
Second
harmonic
distortion
Fin = 170
MHz
dBc
3.5 dB Coarse
gain
82
75
76
84
79
81
84
80
81
87
79
81
0 dB Gain
Fin = 230
MHz
3.5 dB Coarse
gain
Fin = 10 MHz
Fin = 50 MHz
Fin = 70 MHz
90
80
84
76
91
83
84
80
93
89
84
81
95
89
86
82
HD3
0 dB Gain
Fin = 170
MHz
Third harmonic
distortion
dBc
3.5 dB Coarse
gain
78
75
76
82
77
79
83
79
81
84
79
82
0 dB Gain
Fin = 230
MHz
3.5 dB Coarse
gain
Fin = 10 MHz
Fin = 50 MHz
Fin = 70 MHz
93
92
91
94
90
90
96
93
92
97
96
95
Worst spur
(Other than
HD2, HD3)
dBc
Fin = 170
MHz
90
90
89
88
89
89
91
90
Fin = 230
MHz
IMD
2-Tone
F1 = 185 MHz, F2 = 190 MHz
83
1
82
1
84
1
88
1
dBFS
intermodulation Each tone at -7 dBFS
distortion
Recovery to within 1% (of final
value) for 6-dB overload with sine
wave input
Input overload
recovery
clock
cycles
PSRR
AC Power
supply rejection supply
ratio
For 100 mVpp signal on AVDD
35
35
35
35
dBc
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SLAS560A–OCTOBER 2007–REVISED MARCH 2008
DIGITAL CHARACTERISTICS(1)
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1 AVDD = 3.3 V
ADS6125/ADS6124
ADS6123/ADS6122
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DIGITAL INPUTS
(2)
PDN, SCLK, SEN & SDATA
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
Input capacitance
2.4
V
0.8
V
33
–33
4
µA
µA
pF
DIGITAL OUTPUTS
CMOS INTERFACE, DRVDD = 1.8 to 3.3 V
High-level output voltage
Low-level output voltage
DRVDD
0
V
V
Output capacitance inside the device, from
each output to ground
Output capacitance
2
pF
DIGITAL OUTPUTS
LVDS INTERFACE, DRVDD = 3.3 V, IO = 3.5 mA, RL = 100 Ω
(3)
High-level output voltage
1375
1025
350
mV
mV
mV
mV
Low-level output voltage
Output differential voltage, |VOD
|
225
VOS Output offset voltage, single-ended
Common-mode voltage of OUTP, OUTM
1200
Output capacitance inside the device, from
either output to ground
Output capacitance
2
pF
(1) All LVDS and CMOS specifications are characterized, but not tested at production.
(2) SCLK & SEN function as digital input pins when they are used for serial interface programming. When used as parallel control pins,
analog voltage needs to be applied as per Table 1 & Table 2.
(3) IO Refers to the LVDS buffer current setting, RL is the differential load resistance between the LVDS output pair.
8
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ADS6123, ADS6122
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SLAS560A–OCTOBER 2007–REVISED MARCH 2008
TIMING CHARACTERISTICS – LVDS AND CMOS MODES(1)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF(2), IO = 3.5
mA, RL = 100 Ω (3), no internal termination, unless otherwise noted.
For timings at lower sampling frequencies, see section Output Timings in the APPLICATION INFORMATION of this data
sheet.
ADS6125
ADS6124
ADS6123
ADS6122
FS = 125 MSPS
FS = 105 MSPS
FS = 80 MSPS
FS = 65 MSPS
PARAMETER
TEST CONDITIONS
UNIT
MIN
0.7
TYP MAX
MIN
TYP MAX
MIN
TYP MAX
MIN
TYP MAX
Aperture
delay
ta
tj
1.5
150
15
2.5
0.7
1.5
150
15
2.5
0.7
1.5
150
15
2.5
0.7
1.5
150
15
2.5
ns
fs rms
µs
Aperture
jitter
From global power
down
50
50
50
50
Wake-up
time
From standby
15
50
15
50
15
50
15
50
µs
(to valid
data)
From output CMOS
100
200
100
200
100
200
100
200
ns
buffer
LVDS
200
9
500
200
9
500
200
9
500
200
9
500
ns
disable
clock
cycles
Latency
DDR LVDS MODE(4), DRVDD = 3.3 V
Data valid (6) to
zero-cross of
CLKOUTP
Data setup
time(5)
tsu
1.7
0.7
2.3
1.7
2.5
0.7
3.1
1.7
3.9
0.7
4.5
1.7
5.4
0.7
6.0
1.7
ns
ns
Zero-cross of
Data hold
time(5)
th
CLKOUTP to data
becoming invalid(6)
Input clock rising edge
zero-cross to output
clock rising edge
zero-cross
Clock
propagation
delay
tPDI
4.3
5.8
7.3
4.3
5.8
7.3
4.3
5.8
7.3
4.3
5.8
7.3
ns
Duty cycle of
LVDS bit
clock duty
cycle
differential clock,
(CLKOUTP-
CLKOUTM)
40%
47%
55%
40%
47%
55%
40%
47%
55%
40%
47%
55%
10 ≤ Fs ≤ 125 MSPS
Rise time measured
from –50 mV to 50 mV
Fall time measured
from 50 mV to –50 mV
1 ≤ Fs ≤ 125 MSPS
Data rise
time,
Data fall
time
tr
tf
70
70
100
100
170
170
70
70
100
100
170
170
70
70
100
100
170
170
70
70
100
100
170
170
ps
ps
Rise time measured
from –50 mV to 50 mV
Fall time measured
from 50 mV to –50 mV
1 ≤ Fs ≤ 125 MSPS
tCLKRI Output clock
rise time,
tCLKFA Output clock
SE
fall time
LL
(7)
PARALLEL CMOS MODE, DRVDD = 2.5 V to 3.3 V, default output buffer drive strength
Data setup
time(5)
Data valid(8) to 50% of
CLKOUT rising edge
tsu
2.9
1.3
4.4
2.7
3.6
2.1
5.1
3.5
5.1
3.6
6.6
5.0
6.5
5.1
8.0
6.5
ns
ns
50% of CLKOUT
Rising edge to data
becoming invalid(8)
Data hold
time(5)
th
Clock
Input clock rising edge
tPDI
propagation zero-cross to 50% of
delay CLKOUT rising edge
5
6.5
7.9
5
6.5
7.9
5
6.5
7.9
5
6.5
7.9
ns
(1) Timing parameters are specified by design and characterization and not tested in production.
(2) CL is the Effective external single-ended load capacitance between each output pin and ground.
(3) IO Refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair.
(4) Measurements are done with a transmission line of 100 Ω characteristic impedance between the device and the load.
(5) Setup and hold time specifications take into account the effect of jitter on the output data and clock.
(6) Data valid refers to logic high of +100 mV and logic low of –100 mV.
(7) For DRVDD < 2.2V, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT). See
Parallel CMOS interface in application section.
(8) Data valid refers to logic high of 2V (1.7V) and logic low of 0.8 V (0.7V) for DRVDD = 3.3V (2.5V).
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SLAS560A–OCTOBER 2007–REVISED MARCH 2008
TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued)
For timings at lower sampling frequencies, see section Output Timings in the APPLICATION INFORMATION of this data
sheet.
ADS6125
ADS6124
ADS6123
ADS6122
FS = 125 MSPS
FS = 105 MSPS
FS = 80 MSPS
FS = 65 MSPS
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP MAX
MIN
TYP MAX
MIN
TYP MAX
MIN
TYP MAX
Duty cycle of output
clock (CLKOUT)
10 ≤ Fs ≤ 125 MSPS
Output clock
duty cycle
45%
0.8
50%
1.5
55%
2.4
45%
0.8
50%
1.5
55%
2.4
45%
0.8
50%
1.5
55%
2.4
45%
0.8
50%
1.5
55%
2.4
Rise time measured
from 20% to 80% of
DRVDD
Fall time measured
from 80% to 20% of
DRVDD
Data rise
time,
Data fall
time
tr
tf
ns
ns
1 ≤ Fs ≤ 125 MSPS
Rise time measured
from 20% to 80% of
DRVDD
Fall time measured
from 80% to 20% of
DRVDD
tCLKRI Output clock
rise time,
SE
0.8
1.5
2.4
0.8
1.5
2.4
0.8
1.5
2.4
0.8
1.5
2.4
tCLKFA Output clock
fall time
LL
1 ≤ Fs ≤ 125 MSPS
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N+12
N+11
N+4
N+3
N+10
N+2
Sample
N
N+1
N+9
Input
Signal
ta
CLKP
Input
Clock
CLKM
CLKOUTM
CLKOUTP
tsu
th
tPDI
9 Clock Cycles
DDR
LVDS
Output Data
DXP, DXM
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
E – Even Bits D0,D2,D4,D6,D8,D10
O – Odd Bits D1,D3,D5,D7,D9,D11
N–9
N–8
N–7
N–6
N–5
N–1
N
N+1
N+2
tPDI
CLKOUT
tsu
Parallel
CMOS
9 Clock Cycles
th
Output Data
D0–D11
N–9
N–8
N–7
N–6
N–5
N–1
N
N+1
N+2
Figure 1. Latency
CLKM
Input
Clock
CLKP
CLKM
CLKP
Input
Clock
tPDI
tPDI
CLKOUTM
Output
Clock
Output
Clock
CLKOUTP
CLKOUT
th
tsu
th
tsu
th
tsu
Dn(1)
Dn+1(2)
Output
Data Pair
Dn_Dn+1_P,
Dn_Dn+1_M
Dn(1)
Output
Data
Dn
(1)Dn – Bits D0, D2, D4, D6, D8, D10
(2)Dn+1 – Bits D1, D3, D5, D7, D9, D11
(1)Dn – Bits D0–D11
Figure 3. CMOS Mode Timing
Figure 2. LVDS Mode Timing
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SLAS560A–OCTOBER 2007–REVISED MARCH 2008
DEVICE PROGRAMMING MODES
ADS612X has several features that can be easily configured using either parallel interface control or serial
interface programming.
USING SERIAL INTERFACE PROGRAMMING ONLY
To program using the serial interface, the internal registers must first be reset to their default values, and the
RESET pin must be kept low. In this mode, SEN, SDATA, and SCLK function as serial interface pins and are
used to access the internal registers of ADC. The registers are reset either by applying a pulse on the RESET
pin, or by a high setting on the <RST> bit (D4 in register 0x00). The Serial Interface section describes register
programming and register reset in more detail.
USING PARALLEL INTERFACE CONTROL ONLY
To control the device using parallel interface, keep RESET tied to high (AVDD). Now, SEN, SCLK, SDATA and
PDN function as parallel interface control pins. These pins can be used to directly control certain modes of the
ADC by connecting them to the correct voltage levels (as described in Table 1 to Table 3). There is no need to
apply a reset pulse.
Frequently used functions are controlled in this mode — standby, selection between LVDS/CMOS output format,
internal/external reference and 2s complement/straight binary output format. Table 1,Table 2, and Table 3
describe the modes controlled by the parallel pins.
AVDD
(5/8) AVDD
3R
(5/8) AVDD
GND
AVDD
2R
3R
(3/8) AVDD
(3/8) AVDD
To Parallel Pin
(SCLK, SDATA, SEN)
GND
Figure 4. Simple Scheme to Configure Parallel Pins
DESCRIPTION OF PARALLEL PINS
Table 1. SCLK Control Pin
SCLK
0
DESCRIPTION
Internal reference and 0 dB gain (Full-scale = 2 VPP
)
(3/8) AVDD
(5/8) AVDD
AVDD
External reference and 0 dB gain (Full-scale = 2 VPP)
External reference and 3.5 dB coarse gain (Full-scale = 1.34 VPP
Internal reference and 3.5 dB coarse gain (Full-scale = 1.34 VPP
)
)
Table 2. SEN Control Pin
SEN
0
DESCRIPTION
2s Complement format and DDR LVDS interface
(3/8) AVDD
(5/8) AVDD
AVDD
Straight binary format and DDR LVDS interface
Straight binary and parallel CMOS interface
2s Complement format and parallel CMOS interface
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Table 3. SDATA, PDN Control Pins
SDATA
Low
PDN
DESCRIPTION
Low
Normal operation
Low
High (AVDD) Standby - only the ADC is powered down
Low Output buffers are powered down, fast wake-up time
High (AVDD) Global power down. ADC, internal reference and output buffers are powered down, slow wake-up time
High (AVDD)
High (AVDD)
SERIAL INTERFACE
The ADC has a set of internal registers, which can be accessed through the serial interface formed by pins SEN
(Serial interface Enable), SCLK (Serial Interface Clock), SDATA (Serial Interface Data) and RESET. After device
power-up, the internal registers must be reset to their default values by applying a high-going pulse on RESET
(of width greater than 10 ns).
Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge
of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge
when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data is loaded in
multiples of 16-bit words within a single active SEN pulse.
The first 5 bits form the register address and the remaining 11 bits form the register data.
The interface can work with SCLK frequency from 20 MHz down to very low speeds (few Hertz) and also with
non-50% SCLK duty cycle.
REGISTER ADDRESS
REGISTER DATA
A4
A3
A2
A1
A0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDATA
t
t
DH
DSU
t
SCLK
SCLK
SEN
t
SLOADH
t
SLOADS
RESET
Figure 5. Serial Interface Timing Diagram
REGISTER INITIALIZATION
After power-up, the internal registers must be reset to their default values. This is done in one of two ways:
1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10 ns) as
shown in Figure 5.
OR
2. By applying software reset. Using the serial interface, set the <RST> bit (D4 in register 0x00) to high. This
initializes the internal registers to their default values and then self-resets the <RST> bit to low. In this case
the RESET pin is kept low.
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SERIAL INTERFACE TIMING
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V (unless otherwise noted)
MIN TYP MAX
> DC 20
UNIT
MHz
fSCLK
tSLOADS
tSLOADH
tDSU
SCLK Frequency = 1/tSCLK
SEN to SCLK Setup time
SCLK to SEN Hold time
SDATA Setup time
25
25
25
25
ns
ns
ns
ns
tDH
SDATA Hold time
RESET TIMING
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V (unless otherwise noted)
PARAMETER
Power-on delay
Reset pulse width
Register write delay
Power-up time
TEST CONDITIONS
MIN
5
TYP
MAX
UNIT
ms
ns
t1
Delay from power-up of AVDD and DRVDD to RESET pulse active
Pulse width of active RESET signal
t2
10
25
t3
Delay from RESET disable to SEN active
ns
tPO
Delay from power-up of AVDD and DRVDD to output stable
6.5
ms
Power Supply
AVDD, DRVDD
t1
RESET
t2
t3
SEN
NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset.
For parallel interface operation, RESET has to be tied permanently HIGH.
Figure 6. Reset Timing Diagram
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SERIAL REGISTER MAP
Table 4 provides a summary of all the modes that can be programmed through the serial interface.
Table 4. Summary of Functions Supported by Serial Interface(1)(2)
REGISTER
ADDRESS
IN HEX
REGISTER FUNCTIONS
A4 - A0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
<PDN
OBUF>
Output
buffers
powered
down
<PDN
CLKOUT>
Output
clock buffer
powered
down
<LVDS
CMOS>
LVDS or
<REF>
Internal or
external
<COARSE
GAIN>
<RST>
Software
Reset
<STBY>
ADC Power
down
00
0
0
0
0
Coarse gain CMOS output
interface
Reference
<DATAOUT <CLKOUT
<CLKOUT
POSN>
Output Clock
position
POSN>
Output data
position
EDGE>
Output
Clock edge
control
04
09
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
control
control
Bit-wise or
Byte-wise
control
0
0
0
0
<DATA
FORMAT>
2s
complement
or straight
binary
0A
<TEST PATTERNS>
0
0
0
0
0
0
0
0
<CUSTOM LOW>
Custom Pattern lower 7bits
0B
0C
0
<FINE GAIN>
Fine Gain 0 to 6dB
<CUSTOM HIGH>
0
0
0
Custom Pattern upper 5 bits
<CURRENT
DOUBLE>
LVDS current double
LVDS Termination
LVDS Internal Termination control for output data and clock
<LVDS CURRENT>
LVDS Current control
0E
0F
0
0
<DRIVE STRENGTH>
CMOS output buffer drive strength control
0
0
0
0
0
0
(1) The unused bits in each register (shown by blank cells in above table) must be programmed as ‘0’.
(2) Multiple functions in a register can be programmed in a single write operation.
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DESCRIPTION OF SERIAL REGISTERS
Each register function is explained in detail below.
Table 5.
A4–A0
(hex)
D10
D9
D8
D7
0
D6
0
D5
D4
D3
0
D2
D1
0
D0
00
<PDN OBUF>
Output buffers
powered down Coarse gain
<COARSE
GAIN>
<LVDS CMOS>
LVDS or CMOS
output interface
<REF>
Internal or
external
<RST>
Software
Reset
<PDN CLKOUT>
Output clock
buffer powered
down
<STBY>
ADC Power
down
reference
D0
0
<STBY> Power down modes
Normal operation
1
Device enters standby mode where only ADC is powered down.
D2
0
<PDN CLKOUT> Power down modes
Output clock is active (on CLKOUT) pin
1
Output clock buffer is powered down and becomes tri-stated. Data outputs are unaffected.
D4
<RST>
1
Software reset applied - resets all internal registers and the bit self-clears to 0.
D5
0
<REF> Reference selection
Internal reference enabled
External reference enabled
1
D8
0
<LVDS CMOS> Output Interface selection
Parallel CMOS interface
1
DDR LVDS interface
D9
0
<COARSE GAIN> Gain programming
0 dB Coarse gain
1
3.5 dB Coarse gain
D10
0
<PDN OBUF> Power down modes
Output data and clock buffers enabled
Output data and clock buffers disabled
1
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Table 6.
A4–A0
(hex)
D10
D9
D8
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
04
<DATAOUT POSN>
Output data position Output Clock edge
control control
<CLKOUT EDGE>
<CLKOUT POSN>
Output Clock
position control
D8
<CLKOUT POSN> Output clock position control
0
Default output clock position after reset. The setup/hold timings for this clock position are specified
in the timing specifications table.
1
Output clock shifted (delayed) by 400 ps
D9
0
<CLKOUT EDGE>
Use rising edge to capture data
Use falling edge to capture data
1
D10
0
<DATAOUT_POSN>
Default position (after reset)
1
Data transition delayed by half clock cycle with respect to default position
Table 7.
A4–A0
(hex)
D10
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
09
Bit-wise or
Byte-wise control
D10
Bit-wise or byte-wise selection (DDR LVDS mode only)
0
Bit-wise sequence - Even data bits (D0, D2, D4..D12) are output at rising edge of CLKOUTP and
odd data bits (D1, D3, D5..D13) at falling edge of CLKOUTP
1
Byte-wise sequence - Lower 7 data bits (D0-D7) are output at rising edge of CLKOUTP and upper
7 data bits (D8-D13) at falling edge of CLKOUTP
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Table 8.
A4–A0
D10
D9
0
D8
D7
D6
D5
D4
0
D3
0
D2
0
D1
0
D0
(hex)
0A
<DF>
0
<TEST PATTERNS>
0
2s complement or straight binary
D7-D5
000
001
010
011
100
101
110
111
Test Patterns
Normal operation - <D13:D0> = ADC output
All zeros - <D13:D0> = 0x0000
All ones - <D13:D0> = 0x3FFF
Toggle pattern - <D13:D0> toggles between 0x2AAA and 0x1555
Digital ramp - <D13:D0> increments from 0x0000 to 0x3FFF by one code every cycle
Custom pattern - <D13:D0> = contents of CUSTOM PATTERN registers
Unused
Unused
D10
0
<DATA FORMAT>
2s Complement
Straight binary
1
Table 9.
A4–A0
(hex)
D10
D9
D8
D7
D6
D5
D4
D3
0
D2
0
D1
D0
0
0B
<CUSTOM LOW>
0
Lower 7bits of custom pattern
Table 10.
A4–A0
(hex)
D10
D9
D8
D7
0
D6
0
D5
0
D4
D3
D2
D1
D0
0C
<FINE GAIN>
<CUSTOM HIGH>
Fine Gain 0 to 6dB
Upper 5 bits of custom pattern
Reg 0B
D10-D4
<CUSTOM LOW> - Specifies lower 7 bits of custom pattern
<CUSTOM HIGH> - Specifies upper 5 bits of custom pattern
Reg 0C
D4-D0
D10-D8
000
<FINE GAIN> Gain programming
0 dB Gain
001
1 dB Gain
010
2 dB Gain
011
3 dB Gain
100
4 dB Gain
101
5 dB Gain
110
6 dB Gain
111
Unused
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Table 11.
A4–A0
(hex)
D10
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0E
<LVDS TERMINATION>
LVDS Internal Termination control for output data and clock
<LVDS
<CURRENT
DOUBLE>
LVDS current
double
CURRENT>
LVDS Current
control
D1-D0
<CURRENT DOUBLE> LVDS current programming
LVDS Data buffer current control
D0
0
Default current, set by <LVDS_CURR>
2x LVDS Current set by <LVDS_CURR>
1
D1
0
LVDS Clock buffer current control
Default current, set by <LVDS_CURR>
2x LVDS Current set by <LVDS_CURR>
1
D3-D2
00
<LVDS CURRENT> LVDS current programming
3.5 mA
2.5 mA
4.5 mA
1.75 mA
01
10
11
D9-D4
D9-D7
000
LVDS internal termination
<DATA TERM> Internal termination for LVDS output data bits
No internal termination
001
300 Ω
185 Ω
115 Ω
150 Ω
100 Ω
80 Ω
010
011
100
101
110
111
65 Ω
D6-D4
000
001
010
011
100
101
110
111
<CLKOUT TERM> Internal termination for LVDS output clock
No internal termination
300 Ω
185 Ω
115 Ω
150 Ω
100 Ω
80 Ω
65 Ω
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Table 12.
A4–A0
(hex)
D10
0
D9
0
D8
0
D7
D6
D5
D4
D3
0
D2
0
D1
D0
0
0F
<DRIVE STRENGTH>
CMOS output buffer drive strength control
0
D7-D4
<DRIVE STRENGTH> Output buffer drive strength controls
WEAKER than default drive
0101
0000
1111
1010
DEFAULT drive strength
STRONGER than default drive strength (recommended for load capacitances > 5 pF)
MAXIMUM drive strength (recommended for load capacitances > 5 pF)
Do not use
Other
combinations
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ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER 2007–REVISED MARCH 2008
PIN CONFIGURATION (CMOS MODE)
RHB PACKAGE
(TOP VIEW)
D5
D4
D3
D2
D1
1
2
3
4
5
6
7
8
24
23
22
21
20
DRVDD
RESET
SCLK
Bottom Pad Connected
To DRGND
SDATA
SEN
AGND
CLKP
CLKM
19 D0
18
17
NC
NC
Figure 7. CMOS Mode Pinout
Table 13. Pin Assignments – CMOS Mode
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
PIN NAME
DESCRIPTION
AVDD
AGND
Analog power supply
Analog ground
I
I
I
I
13, 15
6, 9, 12
7, 8
2
3
2
2
CLKP, CLKM Differential clock input
INP, INM
Differential analog input
10, 11
Internal reference mode – common-mode voltage output.
External reference mode – reference input. The voltage forced on this pin sets the
internal references.
VCM
I/O
14
1
Serial interface RESET input.
When using the serial interface mode, the user MUST initialize internal registers
through hardware RESET by applying a high-going pulse on this pin, or by using
the software reset option. See the SERIAL INTERFACE section.
In parallel interface mode, the user has to tie the RESET pin permanently HIGH.
(SCLK, SDATA and SEN are used as parallel pin controls in this mode)
The pin has an internal 100-kΩ pull-down resistor.
RESET
I
2
1
This pin functions as serial interface clock input when RESET is low.
When RESET is tied high, it controls the coarse gain and internal/external reference
selection. Tie SCLK to low for internal reference and 0 dB gain and high for
internal reference and 3.5 dB gain. See Table 1.
SCLK
I
I
3
4
1
1
The pin has an internal 100-kΩ pull-down resistor.
This pin functions as serial interface data input when RESET is low. It controls
various power down modes along with PDN pin when RESET is tied high.
SDATA
See Table 3 for detailed information.
The pin has an internal 100 kΩ pull-down resistor.
This pin functions as serial interface enable input when RESET is low. When
RESET is high, it controls output interface type and data formats. See Table 2 for
detailed information.
SEN
PDN
I
I
5
1
1
The pin has an internal 100-kΩ pull-up resistor to DRVDD.
Global power down control pin
16
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SLAS560A–OCTOBER 2007–REVISED MARCH 2008
Table 13. Pin Assignments – CMOS Mode (continued)
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
PIN NAME
DESCRIPTION
CLKOUT
D0
CMOS Output clock
O
O
O
O
O
O
O
O
O
O
O
O
O
O
26
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CMOS Output data D0
CMOS Output data D1
CMOS Output data D2
CMOS Output data D3
CMOS Output data D4
CMOS Output data D5
CMOS Output data D6
CMOS Output data D7
CMOS Output data D8
CMOS Output data D9
CMOS Output data D10
CMOS Output data D11
19
D1
20
D2
21
D3
22
D4
23
D5
24
D6
27
D7
28
D8
29
D9
30
D10
D11
31
32
Indicates over-voltage on analog inputs (for differential input greater than full-scale),
CMOS level
25
OVR
DRVDD
Digital supply
I
I
1
1
1
Digital ground.
PAD
DRGND
NC
Connect the pad to the ground plane. See Board Design Considerations in
application information section.
Do not connect
17,18
2
22
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SLAS560A–OCTOBER 2007–REVISED MARCH 2008
PIN CONFIGURATION (LVDS MODE)
RHB PACKAGE
(TOP VIEW)
D4_D5_P
D4_D5_M
D2_D3_P
D2_D3_M
D0_D1_P
1
2
3
4
5
6
7
8
24
23
22
21
20
DRVDD
RESET
SCLK
Bottom Pad Connected
To DRGND
SDATA
SEN
AGND
CLKP
CLKM
19 D0_D1_M
18
17
NC
NC
Figure 8. LVDS Mode Pinout
Table 14. Pin Assignments – LVDS Mode
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
PIN NAME
DESCRIPTION
AVDD
Analog power supply
Analog ground
I
I
I
I
13, 15
6, 9, 12
7, 8
2
3
2
2
AGND
CLKP, CLKM
INP, INM
Differential clock input
Differential analog input
10, 11
Internal reference mode – common-mode voltage output.
External reference mode – reference input. The voltage forced on this pin sets the
internal references.
VCM
I/O
14
1
Serial interface RESET input.
When using the serial interface mode, the user MUST initialize internal registers
through hardware RESET by applying a high-going pulse on this pin, or by using the
software reset option. See the SERIAL INTERFACE section.
In parallel interface mode, the user has to tie the RESET pin permanently HIGH.
(SCLK, SDATA and SEN are used as parallel pin controls in this mode)
The pin has an internal 100-kΩ pull-down resistor.
RESET
I
2
1
This pin functions as serial interface clock input when RESET is low.
When RESET is tied high, it controls the coarse gain and internal/external reference
selection. Tie SCLK to low for internal reference and 0 dB gain and high for internal
reference and 3.5 dB gain. See Table 1.
SCLK
I
I
3
4
1
1
The pin has an internal 100-kΩ pull-down resistor.
This pin functions as serial interface data input when RESET is low. It controls
various power down modes along with PDN pin when RESET is tied high.
SDATA
See Table 3 for detailed information.
The pin has an internal 100 kΩ pull-down resistor.
This pin functions as serial interface enable input when RESET is low. When RESET
is high, it controls output interface type and data formats. See Table 2 for detailed
information. The pin has an internal 100-kΩ pull-up resistor to DRVDD.
SEN
PDN
I
I
5
1
1
Global power down control pin
16
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SLAS560A–OCTOBER 2007–REVISED MARCH 2008
Table 14. Pin Assignments – LVDS Mode (continued)
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
PIN NAME
DESCRIPTION
CLKOUTP
CLKOUTM
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
D6_D7_P
D6_D7_M
D8_D9_P
D8_D9_M
D10_D11_P
D10_D11_M
DRVDD
Differential output clock, true
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
26
25
20
19
22
21
24
23
28
27
30
29
32
31
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Differential output clock, complement
Differential output data D0 and D1 multiplexed, true
Differential output data D0 and D1 multiplexed, complement.
Differential output data D2 and D3 multiplexed, true
Differential output data D2 and D3 multiplexed, complement
Differential output data D4 and D5 multiplexed, true
Differential output data D4 and D5 multiplexed, complement
Differential output data D6 and D7 multiplexed, true
Differential output data D6 and D7 multiplexed, complement
Differential output data D8 and D9 multiplexed, true
Differential output data D8 and D9 multiplexed, complement
Differential output data D10 and D11 multiplexed, true
Differential output data D10 and D11 multiplexed, complement
Digital supply
Digital ground.
I
PAD
DRGND
NC
Connect the pad to the ground plane. See Board Design Considerations in application
information section.
Do not connect
17,18
2
24
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SLAS560A–OCTOBER 2007–REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6125 (FS= 125 MSPS)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
FFT for 20 MHz INPUT SIGNAL
FFT for 70 MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 92 dBc
SFDR = 84.2 dBc
SINAD = 71.3 dBFS
SNR = 71.5 dBFS
THD = 87.9 dBc
SINAD = 70.6 dBFS
SNR = 71 dBFS
THD = 82.7 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−140
−160
−100
−120
−140
−160
0
0
0
10
20
30
40
50
60
0
10
20
30
40
50
60
f − Frequency − MHz
f − Frequency − MHz
G001
G002
Figure 9.
Figure 10.
FFT for 230 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
−20
0
SFDR = 74.1 dBc
SINAD = 66.5 dBFS
SNR = 68.6 dBFS
THD = 71.4 dBc
f
f
1 = 190.1 MHz, –7 dBFS
2 = 185.3 MHz, –7 dBFS
2-Tone IMD = –83.6 dBFS
SFDR = –81.3 dBFS
IN
IN
−20
−40
−40
−60
−60
−80
−80
−100
−120
−140
−160
−100
−120
−140
−160
10
20
30
40
50
60
0
10
20
30
40
50
60
f − Frequency − MHz
f − Frequency − MHz
G003
G004
Figure 11.
Figure 12.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
92
88
84
80
76
72
68
64
76
74
72
70
68
66
64
62
Gain = 0 dB
Gain = 3.5 dB
Gain = 0 dB
Gain = 3.5 dB
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G005
G006
Figure 13.
Figure 14.
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SLAS560A–OCTOBER 2007–REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6125 (FS= 125 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
SFDR vs INPUT FREQUENCY (LVDS interface)
SNR vs INPUT FREQUENCY (LVDS interface)
92
88
84
80
76
72
68
64
76
74
72
70
68
66
64
62
Gain = 3.5 dB
Gain = 0 dB
Gain = 3.5 dB
Gain = 0 dB
0
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G007
G008
Figure 15.
Figure 16.
SFDR vs INPUT FREQUENCY ACROSS GAINS
SINAD vs INPUT FREQUENCY ACROSS GAINS
95
90
85
80
75
70
65
60
76
74
72
70
68
66
64
62
60
Input adjusted to get −1dBFS input
Input adjusted to get −1dBFS input
0 dB
1 dB
3 dB
5 dB
2 dB
6 dB
4 dB
0 dB
3 dB
1 dB
2 dB
4 dB
6 dB
5 dB
0
100
200
300
400
500
0
100
200
300
400
500
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G009
G010
Figure 17.
Figure 18.
PERFORMANCE vs AVDD
PERFORMANCE vs DRVDD
96
94
92
90
88
86
73
88
86
84
82
80
78
76
74
72
78
f
= 10.1 MHz
f
= 70.1 MHz
IN
IN
77
76
75
74
73
72
71
70
AV = 3.3 V
DRV = 3.3 V
DD
DD
SFDR
72
71
70
69
68
SNR
SFDR
SNR
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
DRV − Supply Voltage − V
DD
AV − Supply Voltage − V
DD
G012
G011
Figure 19.
Figure 20.
26
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ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER 2007–REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6125 (FS= 125 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
PERFORMANCE vs TEMPERATURE
PERFORMANCE vs INPUT AMPLITUDE
94
92
90
88
86
84
74
73
72
71
70
69
110
100
90
90
85
80
75
70
65
60
55
50
SFDR (dBFS)
SFDR
SNR (dBFS)
80
70
SNR
60
SFDR (dBc)
50
40
f
IN
= 10.1 MHz
f
= 10.1 MHz
−10
IN
30
−60
−40
−20
0
20
40
60
80
−50
−40
−30
−20
0
T − Temperature − °C
Input Amplitude − dBFS
G013
G014
Figure 21.
Figure 22.
PERFORMANCE vs CLOCK AMPLITUDE
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
92
90
88
86
84
82
80
78
76
72.0
71.5
71.0
70.5
70.0
69.5
69.0
68.5
68.0
92
91
90
89
88
87
86
85
84
72.0
f
IN
= 20.1 MHz
71.5
71.0
70.5
70.0
69.5
69.0
68.5
68.0
SFDR
SNR
SNR
SFDR
f
IN
= 10.1 MHz
0.5
1.0
1.5
2.0
2.5
3.0
30
35
40
45
50
55
60
65
70
Input Clock Amplitude − V
Input Clock Duty Cycle − %
PP
G015
G016
Figure 23.
Figure 24.
OUTPUT NOISE HISTOGRAM
(INPUTS TIED TO COMMON-MODE)
PERFORMANCE IN EXTERNAL REFERENCE MODE
60
93
91
89
87
85
83
76
f
IN
= 20.1 MHz
RMS (LSB) = 0.497
External Reference Mode
50
40
30
20
10
0
74
72
70
68
66
SNR
SFDR
2048 2049 2050 2051 2052 2053 2054 2055 2056 2057
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70
V
VCM
− VCM Voltage − V
Output Code
G017
G018
Figure 25.
Figure 26.
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SLAS560A–OCTOBER 2007–REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6124 (FS= 105 MSPS)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
FFT for 20 MHz INPUT SIGNAL
FFT for 80 MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 88.2 dBc
SFDR = 84.8 dBc
SINAD = 71.3 dBFS
SNR = 71.5 dBFS
THD = 87.1 dBc
SINAD = 70.8 dBFS
SNR = 71.1 dBFS
THD = 82.9 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−140
−160
−100
−120
−140
−160
0
0
0
10
20
30
40
50
0
10
20
30
40
50
f − Frequency − MHz
f − Frequency − MHz
G019
G020
Figure 27.
Figure 28.
FFT for 230 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
−20
0
SFDR = 74.9 dBc
SINAD = 65.8 dBFS
SNR = 67.1 dBFS
THD = 73.3 dBc
f
f
1 = 190.1 MHz, –7 dBFS
2 = 185.3 MHz, –7 dBFS
IN
IN
−20
−40
2-Tone IMD = –82.4 dBFS
SFDR = –87.8 dBFS
−40
−60
−60
−80
−80
−100
−120
−140
−160
−100
−120
−140
−160
10
20
30
40
50
0
10
20
30
40
50
f − Frequency − MHz
f − Frequency − MHz
G021
G022
Figure 29.
Figure 30.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
96
92
88
84
80
76
72
68
64
60
76
74
72
70
68
66
64
62
Gain = 3.5 dB
Gain = 0 dB
Gain = 0 dB
Gain = 3.5 dB
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G023
G024
Figure 31.
Figure 32.
28
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SLAS560A–OCTOBER 2007–REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6124 (FS= 105 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
SFDR vs INPUT FREQUENCY (LVDS interface)
SNR vs INPUT FREQUENCY (LVDS interface)
96
92
88
84
80
76
72
68
64
60
76
74
72
70
68
66
64
62
Gain = 0 dB
Gain = 3.5 dB
Gain = 3.5 dB
Gain = 0 dB
0
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G025
G026
Figure 33.
Figure 34.
SFDR vs INPUT FREQUENCY ACROSS GAINS
SINAD vs INPUT FREQUENCY ACROSS GAINS
95
90
85
80
75
70
65
60
76
74
72
70
68
66
64
62
60
Input adjusted to get −1dBFS input
Input adjusted to get −1dBFS input
0 dB
1 dB
6 dB
5 dB
2 dB
0 dB
4 dB
1 dB
4 dB
3 dB
2 dB
300
5 dB
6 dB
300
3 dB
400
0
100
200
500
0
100
200
400
500
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G027
G028
Figure 35.
Figure 36.
PERFORMANCE vs AVDD
PERFORMANCE vs DRVDD
98
96
94
92
90
88
86
84
77
92
90
88
86
84
82
80
78
76
78
77
76
75
74
73
72
71
70
f
= 10.1 MHz
f
= 70.1 MHz
IN
IN
76
75
74
73
72
71
70
AV = 3.3 V
DD
DRV = 3.3 V
DD
SFDR
SFDR
SNR
SNR
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
DRV − Supply Voltage − V
DD
AV − Supply Voltage − V
DD
G030
G029
Figure 37.
Figure 38.
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ADS6123, ADS6122
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SLAS560A–OCTOBER 2007–REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6124 (FS= 105 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
PERFORMANCE vs TEMPERATURE
PERFORMANCE vs INPUT AMPLITUDE
96
94
92
90
88
86
75
74
73
72
71
70
110
100
90
90
85
80
75
70
65
60
55
50
SFDR (dBFS)
SFDR
SNR (dBFS)
80
70
60
SNR
SFDR (dBc)
50
40
f
IN
= 10.1 MHz
f
= 20.1 MHz
−10
IN
30
−60
−50
−40
−30
−20
0
−40
−20
0
20
40
60
80
Input Amplitude − dBFS
T − Temperature − °C
G032
G031
Figure 39.
Figure 40.
PERFORMANCE vs CLOCK AMPLITUDE
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
92
90
88
86
84
82
80
78
76
72.0
71.5
71.0
70.5
70.0
69.5
69.0
68.5
68.0
96
94
92
90
88
86
84
82
80
72.0
SNR
f
IN
= 10.1 MHz
71.5
71.0
70.5
70.0
69.5
69.0
68.5
68.0
SFDR
SFDR
SNR
f
IN
= 20.1 MHz
0.5
1.0
1.5
2.0
2.5
3.0
30
35
40
45
50
55
60
65
70
Input Clock Amplitude − V
Input Clock Duty Cycle − %
PP
G033
G034
Figure 41.
Figure 42.
PERFORMANCE IN EXTERNAL REFERENCE MODE
96
94
92
90
88
86
76
f
= 20.1 MHz
IN
External Reference Mode
74
72
70
68
66
SNR
SFDR
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70
V
VCM
− VCM Voltage − V
G036
Figure 43.
30
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SLAS560A–OCTOBER 2007–REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6123 (FS= 80 MSPS)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
FFT for 20 MHz INPUT SIGNAL
FFT for 70 MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 89.34 dBc
SFDR = 83.43 dBc
SINAD = 71.57 dBFS
SNR = 71.74 dBFS
THD = 86.63 dBc
SINAD = 71.03 dBFS
SNR = 71.49 dBFS
THD = 82.65 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−140
−160
−100
−120
−140
−160
0
0
0
10
20
30
40
0
10
20
30
40
f − Frequency − MHz
f − Frequency − MHz
G037
G038
Figure 44.
Figure 45.
FFT for 230 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
−20
0
SFDR = 81.4 dBc
f
f
1 = 190.1 MHz, –7 dBFS
2 = 185.3 MHz, –7 dBFS
2-Tone IMD = –84.1 dBFS
SFDR = –89.5 dBFS
IN
SINAD = 69 dBFS
SNR = 69.7 dBFS
THD = 78 dBc
IN
−20
−40
−40
−60
−60
−80
−80
−100
−120
−140
−160
−100
−120
−140
−160
10
20
30
40
0
10
20
30
40
f − Frequency − MHz
f − Frequency − MHz
G039
G040
Figure 46.
Figure 47.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
100
96
92
88
84
80
76
72
68
64
60
76
74
72
70
68
66
64
62
Gain = 3.5 dB
Gain = 0 dB
Gain = 0 dB
Gain = 3.5 dB
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G041
G042
Figure 48.
Figure 49.
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TYPICAL CHARACTERISTICS - ADS6123 (FS= 80 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
SFDR vs INPUT FREQUENCY (LVDS interface)
SNR vs INPUT FREQUENCY (LVDS interface)
100
96
92
88
84
80
76
72
68
64
60
76
74
72
70
68
66
64
62
Gain = 3.5 dB
Gain = 0 dB
Gain = 3.5 dB
Gain = 0 dB
0
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G043
G044
Figure 50.
Figure 51.
SFDR vs INPUT FREQUENCY ACROSS GAINS
SINAD vs INPUT FREQUENCY ACROSS GAINS
95
90
85
80
75
70
65
60
74
72
70
68
66
64
62
60
58
Input adjusted to get −1dBFS input
3 dB
Input adjusted to get −1dBFS input
0 dB
1 dB
2 dB
3 dB
2 dB
6 dB
5 dB
0 dB
4 dB
1 dB
4 dB
5 dB
6 dB
0
100
200
300
400
500
0
100
200
300
400
500
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G045
G046
Figure 52.
Figure 53.
PERFORMANCE vs AVDD
PERFORMANCE vs DRVDD
102
100
98
74
88
78
f
= 10.1 MHz
f
= 70.1 MHz
IN
IN
86
84
82
80
78
76
74
72
77
76
75
74
73
72
71
70
73
72
71
70
69
68
67
AV = 3.3 V
SFDR
DRV = 3.3 V
DD
DD
SNR
96
94
SFDR
92
SNR
90
88
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
DRV − Supply Voltage − V
DD
AV − Supply Voltage − V
DD
G048
G047
Figure 54.
Figure 55.
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TYPICAL CHARACTERISTICS - ADS6123 (FS= 80 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
PERFORMANCE vs TEMPERATURE
PERFORMANCE vs INPUT AMPLITUDE
99
97
95
93
91
89
74
73
72
71
70
69
110
100
90
90
85
80
75
70
65
60
55
50
SFDR
SFDR (dBFS)
SNR (dBFS)
80
SNR
70
60
50
SFDR (dBc)
−50
40
f
IN
= 10.1 MHz
f
IN
= 20 MHz
−10 0
30
−60
−40
−20
0
20
40
60
80
−40
−30
−20
T − Temperature − °C
Input Amplitude − dBFS
G049
G050
Figure 56.
Figure 57.
PERFORMANCE vs CLOCK AMPLITUDE
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
94
92
90
88
86
84
82
80
78
72.0
71.5
71.0
70.5
70.0
69.5
69.0
68.5
68.0
98
96
94
92
90
88
86
84
82
72.0
f
IN
= 10.1 MHz
71.5
71.0
70.5
70.0
69.5
69.0
68.5
68.0
SFDR
SNR
SNR
SFDR
f
IN
= 20.1 MHz
30
35
40
45
50
55
60
65
70
0.5
1.0
1.5
2.0
2.5
3.0
Input Clock Duty Cycle − %
Input Clock Amplitude − V
PP
G052
G051
Figure 58.
Figure 59.
PERFORMANCE IN EXTERNAL REFERENCE MODE
92
90
88
86
84
82
78
f
= 20.1 MHz
IN
External Reference Mode
76
74
72
70
68
SFDR
SNR
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70
V
VCM
− VCM Voltage − V
G054
Figure 60.
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TYPICAL CHARACTERISTICS - ADS6122 (FS= 65 MSPS)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
FFT for 20 MHz INPUT SIGNAL
FFT for 90 MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 91.8 dBc
SFDR = 83 dBc
SINAD = 71.1 dBFS
SNR = 71.8 dBFS
THD = 89.8 dBc
SINAD = 71.1 dBFS
SNR = 71.6 dBFS
THD = 82.3 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−140
−160
−100
−120
−140
−160
0
0
0
10
20
30
0
10
20
30
f − Frequency − MHz
f − Frequency − MHz
G055
G056
Figure 61.
Figure 62.
FFT for 230 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
−20
0
SFDR = 82.8 dBc
f
f
1 = 190.1 MHz, –7 dBFS
2 = 185.3 MHz, –7 dBFS
2-Tone IMD = –88.5 dBFS
SFDR = –91.9 dBFS
IN
SINAD = 69.5 dBFS
SNR = 70.1 dBFS
THD = 79.6 dBc
IN
−20
−40
−40
−60
−60
−80
−80
−100
−120
−140
−160
−100
−120
−140
−160
10
20
30
0
10
20
30
f − Frequency − MHz
f − Frequency − MHz
G057
G058
Figure 63.
Figure 64.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
100
96
92
88
84
80
76
72
68
64
60
76
74
72
70
68
66
64
62
Gain = 3.5 dB
Gain = 0 dB
Gain = 3.5 dB
Gain = 0 dB
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G059
G060
Figure 65.
Figure 66.
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SLAS560A–OCTOBER 2007–REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6122 (FS= 65 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
SFDR vs INPUT FREQUENCY (LVDS interface)
SNR vs INPUT FREQUENCY (LVDS interface)
100
96
92
88
84
80
76
72
68
64
60
76
74
72
70
68
66
64
62
Gain = 3.5 dB
Gain = 0 dB
Gain = 3.5 dB
Gain = 0 dB
0
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G061
G062
Figure 67.
Figure 68.
SFDR vs INPUT FREQUENCY ACROSS GAINS
SINAD vs INPUT FREQUENCY ACROSS GAINS
95
90
85
80
75
70
65
60
76
74
72
70
68
66
64
62
60
Input adjusted to get −1dBFS input
Input adjusted to get −1dBFS input
0 dB
2 dB
1 dB
3 dB
6 dB
1 dB
2 dB
0 dB
5 dB
3 dB
6 dB
300
5 dB
4 dB
4 dB
0
100
200
300
400
500
0
100
200
400
500
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G063
G064
Figure 69.
Figure 70.
PERFORMANCE vs AVDD
PERFORMANCE vs DRVDD
106
104
102
100
98
75
96
77
f
= 10.1 MHz
f
= 70.1 MHz
IN
IN
94
92
90
88
86
84
82
80
76
75
74
73
72
71
70
69
74
73
72
71
70
69
68
AV = 3.3 V
DRV = 3.3 V
DD
DD
SFDR
SNR
SNR
SFDR
96
94
92
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
DRV − Supply Voltage − V
DD
AV − Supply Voltage − V
DD
G066
G065
Figure 71.
Figure 72.
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SLAS560A–OCTOBER 2007–REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6122 (FS= 65 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
PERFORMANCE vs TEMPERATURE
PERFORMANCE vs INPUT AMPLITUDE
98
96
94
92
90
88
86
76
75
74
73
72
71
70
110
100
90
90
85
80
75
70
65
60
55
50
f
IN
= 10.1 MHz
SFDR (dBFS)
SFDR
SNR (dBFS)
80
70
60
SNR
SFDR (dBc)
50
40
f
= 20.1 MHz
−10
IN
30
−60
−50
−40
−30
−20
0
−40
−20
0
20
40
60
80
Input Amplitude − dBFS
T − Temperature − °C
G068
G067
Figure 73.
Figure 74.
PERFORMANCE vs CLOCK AMPLITUDE
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
96
94
92
90
88
86
84
82
80
72.0
71.5
71.0
70.5
70.0
69.5
69.0
68.5
68.0
96
94
92
90
88
86
84
82
80
72.0
SFDR
71.5
71.0
70.5
70.0
69.5
69.0
68.5
68.0
SNR
SNR
SFDR
f
IN
= 10.1 MHz
f
IN
= 20.1 MHz
0.5
1.0
1.5
2.0
2.5
3.0
30
35
40
45
50
55
60
65
70
Input Clock Amplitude − V
Input Clock Duty Cycle − %
PP
G069
G070
Figure 75.
Figure 76.
PERFORMANCE IN EXTERNAL REFERENCE MODE
95
93
91
89
87
85
78
f
= 20.1 MHz
IN
External Reference Mode
76
74
72
70
68
SFDR
SNR
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70
V
VCM
− VCM Voltage − V
G072
Figure 77.
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SLAS560A–OCTOBER 2007–REVISED MARCH 2008
TYPICAL CHARACTERISTICS - LOW SAMPLING FREQUENCIES
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty
cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted)
FS = 40 MSPS
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
100
96
92
88
84
80
76
72
68
64
60
76
74
72
70
68
66
64
62
Gain = 0 dB
Gain = 3.5 dB
Gain = 3.5 dB
Gain = 0 dB
0
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G073
G074
Figure 78.
Figure 79.
FS = 25 MSPS
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
100
90
80
70
60
50
76
74
72
70
68
66
64
62
Gain = 3.5 dB
Gain = 0 dB
Gain = 0 dB
Gain = 3.5 dB
0
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G075
G076
Figure 80.
Figure 81.
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SLAS560A–OCTOBER 2007–REVISED MARCH 2008
COMMON PLOTS
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty
cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted)
POWER DISSIPATION vs
SAMPLING FREQUENCY (DDR LVDS and CMOS)
COMMON-MODE REJECTION RATIO vs FREQUENCY
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
f
C
= 2.5 MHz
= 5 pF
IN
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
L
LVDS
CMOS
75
0
25
50
100
125
0
50
100
150
200
250
300
f
S
− Sampling Frequency − MSPS
f − Frequency − MHz
G078
G077
Figure 82.
Figure 83.
DRVDD current vs
SAMPLING FREQUENCY across load capacitance (CMOS)
30
1.8 V, No Load
25
1.8 V, 5 pF
20
15
10
5
3.3 V, No Load
3.3 V, 5 pF
3.3 V, 10 pF
0
0
25
50
75
100
125
f
S
− Sampling Frequency − MSPS
G079
Figure 84.
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SLAS560A–OCTOBER 2007–REVISED MARCH 2008
Contour Plots Across Input and Sampling Frequencies
125
120
90
75
84
72
66
84
78
87
84
69
81
110
100
90
84
63
66
75
81
87
84
72
78
90
90
87
80
60
69
87
81
70
63
78
60
75
84
50
90
93
69
72
66
40
78
60
75
81
84
63
30
25
10
50
100
150
200
250
300
350
400
450
500
fIN - Input Frequency - MHz
60
65
70
75
80
85
90
95
SFDR - dBc
M0049-15
Figure 85. SFDR Contour (No gain, FS = 2 VPP
)
125
120
84
87
84
75
87
78
87
81
110
100
90
69
87
72
66
90
75
78
81
81
90
87
80
90
87
90
84
69
70
93
66
72
75
93
60
78
50
90
90
40
87
84
93
78
63
72
81
69
93
75
30
25
10
50
100
150
200
250
300
350
400
450
500
fIN - Input Frequency - MHz
60
65
70
75
80
85
90
95
SFDR - dBc
M0049-16
Figure 86. SFDR Contour (with 3.5 dB Coarse gain, FS = 1.34 VPP
)
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SLAS560A–OCTOBER 2007–REVISED MARCH 2008
Contour Plots Across Input and Sampling Frequencies (continued)
Figure 87. SNR Contour (No gain, FS = 2 VPP
)
Figure 88. SNR Contour (with 3.5 dB Coarse gain, FS = 1.34 VPP
)
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SLAS560A–OCTOBER 2007–REVISED MARCH 2008
APPLICATION INFORMATION
THEORY OF OPERATION
ADS612X is a family of low power 12-bit pipeline ADC in a CMOS process up to 125 MSPS sampling frequency.
It is based on switched capacitor technology and runs off a single 3.3-V supply. The conversion process is
initiated by a rising edge of the external input clock. Once the signal is captured by the input sample and hold,
the input sample is sequentially converted by a series of lower resolution stages, with the outputs combined in a
digital correction logic block. At every clock edge, the sample propagates through the pipeline resulting in a data
latency of 9 clock cycles. The output is available as 12-bit data, in DDR LVDS or CMOS and coded in either
straight offset binary or binary 2s complement format.
ANALOG INPUT
The analog input consists of a switched-capacitor based differential sample and hold architecture, shown in
Figure 89.
This differential topology results in good ac-performance even for high input frequencies at high sampling rates.
The INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V available on VCM
pin. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM + 0.5 V
and VCM – 0.5 V, resulting in a 2-VPP differential input swing. The maximum swing is determined by the internal
reference voltages REFP (2.5 V nominal) and REFM (0.5 V, nominal).
Sampling
Switch
Lpkg
»1 nH
Sampling
Capacitor
RCR Filter
INP
Ron
15 W
25 W
Csamp
4.0 pF
Cbond
»1 pF
Cpar2
1 pF
50 W
3.2 pF
50 W
Resr
200 W
Ron
10 W
Cpar1
0.8 pF
Lpkg
»1 nH
Csamp
4.0 pF
Ron
15 W
25 W
INM
Sampling
Capacitor
Cbond
»1 pF
Cpar2
1 pF
Resr
200 W
Sampling
Switch
Figure 89. Input Stage
The input sampling circuit has a high 3-dB bandwidth that extends up to 450 MHz (measured from the input pins
to the voltage across the sampling capacitors).
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1
0
−1
−2
−3
−4
−5
−6
−7
0
100
200
300
400
500
600
f
IN
− Input Frequency − MHz
G080
Figure 90. ADC Analog Input Bandwidth
Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This improves the common-mode
noise immunity and even order harmonic rejection.
A 5-Ω resistor in series with each input pin is recommended to damp out ringing caused by the package
parasitics. It is also necessary to present low impedance (< 50 Ω) for the common mode switching currents. For
example, this is achieved by using two resistors from each input terminated to the common mode voltage (VCM).
In addition to the above, the drive circuit may have to be designed to provide a low insertion loss over the
desired frequency range and matched impedance to the source. While doing this, the ADC input impedance
must be considered. Over a wide frequency range, the input impedance can be approximated by a parallel
combination of Rin and Cin (Zin = Rin || Cin).
100
10
1
0.1
0.01
0
100
200
300
400
500
600
f − Frequency − MHz
G083
Figure 91. ADC Input Resistance, Rin
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9
8
7
6
5
4
3
2
1
0
0
100
200
300
400
500
600
f − Frequency − MHz
G084
Figure 92. ADC Input Capacitance, Cin
Using RF-Transformer Based Drive Circuits
Figure 93 shows a configuration using a single 1:1 turns ratio transformer (for example, Coilcraft WBC1-1) that
can be used for low input frequencies (about 100 MHz).
The single-ended signal is fed to the primary winding of the RF transformer. The transformer is terminated on the
secondary side. Putting the termination on the secondary side helps to shield the kickbacks caused by the
sampling circuit from the RF transformer’s leakage inductances. The termination is accomplished by two resistors
connected in series, with the center point connected to the 1.5 V common mode (VCM pin). The value of the
termination resistors (connected to common mode) has to be low (< 100 Ω) to provide a low-impedance path for
the ADC common-mode switching current.
TF_ADC
0.1
mF
5 W
INP
25 W
25 W
0.1
mF
5 W
INM
1 :1
VCM
Figure 93. Single Transformer Drive Circuit
At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results
in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps
minimize this mismatch, and good performance is obtained for high frequency input signals. Figure 94 shows an
example using two transformers (Coilcraft WBC1-1). An additional termination resistor pair (enclosed within the
shaded box in Figure 94) may be required between the two transformers to improve the balance between the P
and M sides. The center point of this termination must be connected to ground.
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5 W
0 .1
mF
INP
50 W
50 W
50 W
50 W
0 .1
mF
5 W
INM
1:1
1:1
VCM
Figure 94. Two Transformer Drive Circuit
Using Differential Amplifier Drive Circuits
Figure 95 shows a drive circuit using a differential amplifier (TI's THS4509) to convert a single-ended input to
differential output that can be interface to the ADC analog input pins. In addition to the single-ended to differential
conversion, the amplifier also provides gain (10 dB in Figure 95). RFIL helps to isolate the amplifier outputs from
the switching input of the ADC. Together with CFIL it also forms a low-pass filter that band-limits the noise (and
signal) at the ADC input. As the amplifier output is ac-coupled, the common-mode voltage of the ADC input pins
is set using two 200 Ω resistors connected to VCM.
The amplifier output can also be dc-coupled. Using the output common-mode control of the THS4509, the ADC
input pins can be biased to 1.5 V. In this case, use +4 V and -1 V supplies for the THS4509 so that its output
common-mode voltage (1.5 V) is at mid-supply.
RF
+VS
0.1 mF
RFIL
500 W
5 W
0.1 mF 10 mF
0.1 mF
INP
RS
RG
CFIL
200 W
0.1 mF
RT
CM THS4509
RG
200 W
5 W
CFIL
RFIL
INM
0.1 mF
500 W
RS || RT
VCM ADS612x
0.1 mF
–VS
0.1 mF 10 mF
0.1 mF
RF
Figure 95. Drive Circuit Using the THS4509
See the EVM User Guide (SLWU028) for more information.
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Input Common-Mode
To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1-µF low-inductance capacitor
connected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADC
sinks a common-mode current in the order of 180 µA (at 125 MSPS). Equation 1 describes the dependency of
the common-mode current and the sampling frequency.
Fs
180 mA x
125 MSPS
(1)
Equation 1 helps to design the output capability and impedance of the CM driving circuit.
REFERENCE
ADS612X has built-in internal references REFP and REFM, requiring no external components. Design schemes
are used to linearize the converter load seen by the references; this and the integration of the requisite reference
capacitors on-chip eliminates the need for external decoupling. The full-scale input range of the converter is
controlled in the external reference mode as explained below. The internal or external reference modes can be
selected by programming the serial interface register bit <REF> (seeTable 5).
INTREF
VCM
INTERNAL
REFERENCE
1 kW
4 kW
INTREF
EXTREF
REFM
REFP
Figure 96. Reference Section
Internal Reference
When the device is in internal reference mode, the REFP and REFM voltages are generated internally.
Common-mode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analog
input pins.
External Reference
When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on the
VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential
input voltage corresponding to full-scale is given by Equation 2.
Full−scale differential input pp + (Voltage forced on VCM) 1.33
(2)
In this mode, the 1.5 V common-mode voltage to bias the input pins has to be generated externally. There is no
change in performance compared to internal reference mode.
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COARSE GAIN and PROGRAMMABLE FINE GAIN
ADS612X includes gain settings that can be used to get improved SFDR performance (compared to 0 dB gain
mode). The gain settings are 3.5 dB coarse gain and programmable fine gain from 0 dB to 6 dB. For each gain
setting, the analog input full-scale range scales proportionally, as shown in Table 15.
The coarse gain is a fixed setting of 3.5 dB and is designed to improve SFDR with little degradation in SNR (as
seen in Figure 13 and Figure 14). The fine gain is programmable in 1 dB steps from 0 to 6 dB. With fine gain
also, SFDR improvement is achieved, but at the expense of SNR (there is about 1 dB SNR degradation for every
1 dB of fine gain).
So, the fine gain can be used to trade-off between SFDR and SNR. The coarse gain makes it possible to get
best SFDR but without losing SNR significantly. At high input frequencies, the gains are especially useful as the
SFDR improvement is significant with marginal degradation in SINAD. The gains can be programmed using the
register bits <COARSE GAIN> (see Table 5) and <FINE GAIN> (see Table 10). Note that the default gain after
reset is 0 dB.
Table 15. Full-Scale Range Across Gains
GAIN, dB
TYPE
FULL-SCALE RANGE, VPP
0
3.5
1
Default after reset
Coarse setting (fixed)
2.00
1.34
1.78
1.59
1.42
1.26
1.12
1.00
2
3
Fine gain (programmable)
4
5
6
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CLOCK INPUT
The clock inputs of the ADS612X can be driven differentially (SINE, LVPECL or LVDS) or single-ended
(LVCMOS), with little or no difference in performance between configurations. The common-mode voltage of the
clock inputs is set to VCM using internal 5-kΩ resistors as shown in Figure 97. This allows the use of
transformer-coupled drive circuits for sine wave clock, or ac-coupling for LVPECL, LVDS clock sources
(Figure 99 and Figure 100).
For best performance, it is recommended to drive the clock inputs differentially, reducing susceptibility to
common-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with
0.1-µF capacitors, as shown in Figure 99. A single-ended CMOS clock can be ac-coupled to the CLKP input,
with CLKM connected to ground with a 0.1-µF capacitor, as shown in Figure 100.
For high input frequency sampling, the use a clock source with very low jitter is recommended. Bandpass filtering
of the clock source can help reduce the effect of jitter. There is no change in performance with a non-50% duty
cycle clock input. Figure 24 shows the performance of the ADC versus clock duty cycle.
Clock Buffer
Lpkg
» 1 nH
10 W
CLKP
Cbond
» 1 pF
Ceq
Ceq
5 kW
Resr
» 100 W
VCM
6 pF
5 kW
Lpkg
» 1 nH
10 W
CLKM
Cbond
» 1 pF
Resr
» 100 W
Ceq » 1 to 3 pF, equivalent input capacitance of clock buffer
Figure 97. Internal Clock Buffer
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1000
900
800
700
600
500
400
300
200
100
0
0
25
50
75
100
125
Clock Frequency − MHz
G082
Figure 98. Clock Buffer Input Impedance
0.1 mF
CLKP
Differential Sine-Wave
or PECL or LVDS
Clock Input
0.1 mF
CLKM
ADS612x
Figure 99. Differential Clock Driving Circuit
0.1 mF
CMOS Clock Input
CLKP
0.1 mF
CLKM
ADS612x
Figure 100. Single-Ended Clock Driving Circuit
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POWER DOWN MODES
ADS612X has four power-down modes – global power down, standby, output buffer disable and input clock
stopped. These modes can be set using the serial interface or using the parallel interface (pins SDATA and
PDN).
Table 16. Power Down Modes
POWER DOWN
MODES
PARALLEL INTERFACE
SERIAL INTERFACE
REGISTER BIT
(Table 5)
TOTAL POWER,
mW
WAKE-UP TIME
(to valid data)
SDATA
PDN
Normal operation
Standby
Low
Low
<PDN OBUF>=0 and
<STBY>=0
417
72
-
Low
High
High
High
Low
High
<PDN OBUF>=0 and
<STBY>=1
Slow (50 µs)
Fast (200 ns)
Slow (50 µs)
Output buffer disable
Global power down
<PDN OBUF>=1 and
<STBY>=0
408
30
<PDN OBUF>=1 and
<STBY>=1
Global Powerdown
In this mode, the A/D converter, internal references and the output buffers are powered down and the total power
dissipation reduces to about 30 mW. The output buffers are in high impedance state. The wake-up time from the
global power down to output data becoming valid in the normal mode is maximum 50 µs. Note that after coming
out of global power down, optimum performance will be achieved after the internal reference voltages have
stabilized (about 1 ms).
Standby
Here, only the A/D converter is powered down and the total power dissipation is about 72 mW. The wake-up time
from standby to output data becoming valid is maximum 50 µs.
Output Buffer Disable
The data output buffers can be disabled, reducing the total power to about 408 mW. With the buffers disabled,
the outputs are in high impedance state. The wake-up time from this mode to data becoming valid in normal
mode is maximum 500 ns in LVDS mode and 200 ns in CMOS mode.
Input Clock Stop
The converter enters this mode when the input clock frequency falls below 1 MSPS. The power dissipation is
about 120 mW, and the wake-up time from this mode to data becoming valid in normal mode is maximum 50 µs.
Power Supply Sequence
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are
separated inside the device. Externally, they can be driven from separate supplies or from a single supply.
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DIGITAL OUTPUT INTERFACE
ADS612X outputs 12 data bits together with an output clock. The output interface are either parallel CMOS or
DDR LVDS voltage levels and can be selected using serial register bit <LVDS CMOS> or parallel pin SEN.
Parallel CMOS Interface
In the CMOS mode, the output buffer supply (DRVDD) can be operated over a wide range from 1.8 V to 3.3 V
(typical). Each data bit is output on separate pin as CMOS voltage level, every clock cycle.
For DRVDD ≥ 2.2 V, it is recommended to use the CMOS output clock (CLKOUT) to latch data in the receiving
chip. The rising edge of CLKOUT can be used to latch data in the receiver, even at the highest sampling speed
(125 MSPS). It is recommended to minimize the load capacitance seen by data and clock output pins by using
short traces to the receiver. Also, match the output data and clock traces to minimize the skew between them.
For DRVDD < 2.2 V, it is recommended to use external clock (for example, input clock delayed to get desired
setup/hold times).
Output Clock Position Programmability
There exists an option to shift (delay) the output clock position so that the setup time increases by 400 ps
(typical, with respect to the default timings specified). This may be useful if the receiver needs more setup time,
especially at high sampling frequencies. This can be programmed using the serial interface register bit
<CLKOUT_POSN> (see Table 6).
Output Buffer Strength Programmability
Switching noise (caused by CMOS output data transitions) can couple into the analog inputs during the instant of
sampling and degrade the SNR. The coupling and SNR degradation increases as the output buffer drive is made
stronger. To minimize this, the ADS612X CMOS output buffers are designed with controlled drive strength to get
best SNR. The default drive strength also ensures wide data stable window for load capacitances upto 5 pF and
DRVDD supply voltage ≥ 2.2 V.
To ensure wide data stable window for load capacitance > 5 pF, there is an option to increase the drive strength
using the serial interface (<DRIVE STRENGTH>, see Table 12). Note that for DRVDD supply voltage < 2.2 V, it
is recommended to use maximum drive strength (for any value of load capacitance).
CMOS Mode Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock
cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined
by the average number of output bits switching, which is a function of the sampling frequency and the nature of
the analog input signal.
Digital current due to CMOS output switching = CL × DRVDD x (N x FAVG
)
where CL = load capacitance, N × FAVG = average number of output bits switching
Figure 84 shows the current with various load capacitances across sampling frequencies at 2 MHz analog input
frequency.
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Pins
OVR
CLKOUT
D0
D1
D2
D3
D4
D5
D6
D7
D8
12 bit ADC data
D9
D10
D11
ADS612X
Figure 101. CMOS Output buffers
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DDR LVDS Interface
The LVDS interface works only with 3.3 V DRVDD supply. In this mode, the 12 data bits and the output clock are
available as LVDS (Low Voltage Differential Signal) levels. Two successive data bits are multiplexed and output
on each LVDS differential pair every clock cycle (DDR - Double Data Rate, see Figure 102 ). So, there are 7
LVDS output pairs for the 12 data bits and 1 LVDS output pair for the output clock.
LVDS Buffer Current Programmability
The default LVDS buffer output current is 3.5 mA. When terminated by 100 Ω, this results in a 350-mV
single-ended voltage swing (700-mVPP differential swing). The LVDS buffer currents can also be programmed to
2.5 mA, 4.5 mA, and 1.75 mA (register bits <LVDS CURRENT>, see Table 11). In addition, there is a current
double mode, where this current is doubled for the data and output clock buffers (register bits <CURRENT
DOUBLE>, see Table 11).
Pins
CLKOUTP
Output Clock
CLKOUTM
D0_D1_P
Data bits D0, D1
D0_D1_M
D2_D3_P
Data bits D2, D3
D2_D3_M
D4_D5_P
Data bits D4, D5
D4_D5_M
12-Bit ADC Data
D6_D7_P
Data bits D6, D7
D6_D7_M
D8_D9_P
Data bits D8, D9
D8_D9_M
D10_D11_P
Data bits D10, D11
D10_D11_M
ADS612x
Figure 102. DDR LVDS Outputs
Even data bits D0, D2, D4, D6, D8, D10, and D12 are output at the rising edge of CLKOUTP and the odd data
bits D1, D3, D5, D7, D9, D11, and D13 are output at the falling edge of CLKOUTP. Both the rising and falling
edges of CLKOUTP must be used to capture all the 12 data bits (see Figure 103).
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CLKOUTM
CLKOUTP
D0_D1_P,
D0_D1_M
D0
D2
D1
D3
D5
D7
D9
D11
D0
D2
D1
D3
D5
D7
D9
D2_D3_P,
D2_D3_M
D4_D5_P,
D4_D5_M
D4
D4
D6_D7_P,
D6_D7_M
D6
D6
D8_D9_P,
D8_D9_M
D8
D8
D10_D11_P,
D10_D11_M
D10
D10
D11
Sample N
Sample N+1
Figure 103. DDR LVDS Interface
LVDS Buffer Internal Termination
An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially
terminated inside the device. The termination resistances available are – 300 Ω, 185 Ω, and 150 Ω (nominal with
±20% variation). Any combination of these three terminations can be programmed; the effective termination is
the parallel combination of the selected resistances. This results in eight effective terminations from open (no
termination) to 65 Ω.
The internal termination helps to absorb any reflections coming from the receiver end, improving the signal
integrity. With 100 Ω internal and 100 Ω external termination, the voltage swing at the receiver end is halved
(compared to no internal termination). The voltage swing can be restored by using the LVDS current double
mode. Figure 104 and Figure 105 compare the LVDS eye diagrams without and with internal termination (100 Ω).
With internal termination, the eye looks clean even with 10 pF load capacitance (from each outpin to ground).
The terminations is programmed using register bits <DATA TERM> and <CLKOUT TERM> (see Table 11).
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Figure 104. LVDS Eye Diagram - No Internal Termination
5-pF Load Capacitance
Figure 105. LVDS Eye Diagram with 100-Ω Internal
Termination
Blue Trace - Output Clock (CLKOUT)
Pink Trace - Output Data
10-pF Load Capacitance
Blue Trace - Output Clock (CLKOUT)
Pink Trace - Output Data
Output Data Format
Two output data formats are supported – 2s complement and offset binary. They can be selected using the
parallel control pin SEN or the serial interface register bit <DATA FORMAT> (see Table 8).
Output Timings
The following table lists the timings at lower sampling frequencies.
(1)(2)
Table 17. Timing Characteristics at Lower Sampling Frequencies
tsu DATA SETUP TIME, ns
MIN TYP MAX
CMOS INTERFACE, DRVDD = 2.5 V to 3.3 V
th DATA HOLD TIME, ns
TYP
tPDI CLOCK PROPAGATION DELAY, ns
Fs, MSPS
MIN
MAX
MIN
TYP
MAX
40
20
10
11.3
23
12.8
25
10
21
46
11.2
23
5
6.5
7.9
48
50
48
DDR LVDS INTERFACE, DRVDD = 3.3 V
40
20
10
10.2
22
10.8
23
0.7
0.7
0.7
1.7
1.7
1.7
4.3
4.5
4.5
5.8
6.5
6.5
7.3
8.5
8.5
47
48
(1) Timing parameters are specified by design and characterization and not tested in production.
(2) Timings are specified with default output buffer drive strength and CL= 5 pF
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BOARD DESIGN CONSIDERATIONS
Grounding
A single ground plane is sufficient to give good performance, provided the analog, digital and clock sections of
the board are cleanly partitioned. See the EVM User Guide (SLWU028) for details on layout and grounding.
Supply Decoupling
As ADS612X already includes internal decoupling, minimal external decoupling can be used without loss in
performance. Note that decoupling capacitors can help to filter external power supply noise, so the optimum
number of capacitors would depend on the actual application. The decoupling capacitors should be placed very
close to the converter supply pins.
It is recommended to use separate supplies for the analog and digital supply pins to isolate digital switching
noise from sensitive analog circuitry. In case only a single 3.3-V supply is available, it should be routed first to
AVDD. It can then be tapped and isolated with a ferrite bead (or inductor) with decoupling capacitor, before being
routed to DRVDD.
Exposed Thermal Pad
It is necessary to solder the exposed pad at the bottom of the package to a ground plane for best thermal
performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and QFN/SON
PCB Attachment (SLUA271).
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low
frequency value.
Aperture Delay
The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling
occurs.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle
The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width)
to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential
sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate
The maximum sampling rate at which certified operation is given. All parametric testing is performed at this
sampling rate unless otherwise noted.
Minimum Conversion Rate
The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the
deviation of any single step from this ideal value, measured in units of LSBs
Integral Nonlinearity (INL)
The INL is the deviation of the ADC’s transfer function from a best fit line determined by a least squares curve fit
of that transfer function, measured in units of LSBs.
Gain Error
The gain error is the deviation of the ADC’s actual input full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale range.
Offset Error
The offset error is the difference, given in number of LSBs, between the ADC’s actual average idle channel
output code and the ideal average idle channel output code. This quantity is often mapped into mV.
Temperature Drift
The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree
Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation of the parameter
across the TMIN to TMAX range by the difference TMAX–TMIN
.
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SLAS560A–OCTOBER 2007–REVISED MARCH 2008
Signal-to-Noise Ratio
SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc
and the first nine harmonics.
P
P
s
SNR + 10Log10
N
(4)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components
including noise (PN) and distortion (PD), but excluding dc.
P
s
SINAD + 10Log10
P
) P
N
D
(5)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Effective Number of Bits (ENOB)
The ENOB is a measure of a converter’s performance as compared to the theoretical limit based on quantization
noise.
SINAD * 1.76
ENOB +
6.02
(6)
(7)
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD).
P
P
s
THD + 10Log10
N
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR)
The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic).
SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion
IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral
component at either frequency 2f1–f2 or 2f2–f1. IMD3 is either given in units of dBc (dB to carrier) when the
absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the
fundamental is extrapolated to the converter’s full-scale range.
DC Power Supply Rejection Ratio (DC PSRR)
The DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The DC PSRR is
typically given in units of mV/V.
Copyright © 2007–2008, Texas Instruments Incorporated
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ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER 2007–REVISED MARCH 2008
AC Power Supply Rejection Ratio (AC PSRR)
AC PSRR is the measure of rejection of variations in the supply voltage of the ADC. If ΔVSUP is the change in the
supply voltage and ΔVOUT is the resultant change in the ADC output code (referred to the input), then
DVOUT
PSRR = 20Log10
(Expressed in dBc)
DVSUP
(8)
Common Mode Rejection Ratio (CMRR)
CMRR is the measure of rejection of variations in the input common-mode voltage of the ADC. If ΔVcm is the
change in the input common-mode voltage and ΔVOUT is the resultant change in the ADC output code (referred
to the input), then
DVOUT
10
CMRR = 20Log
(Expressed in dBc)
DVCM
(9)
Voltage Overload Recovery
The number of clock cycles taken to recover to less than 1% error for a 6-dB overload on the analog inputs. A
6-dBFS sine wave at Nyquist frequency is used as the test stimulus.
58
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Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER 2007–REVISED MARCH 2008
REVISION HISTORY
Changes from Original (October 2007) to Revision A .................................................................................................... Page
•
•
•
Changed DDR LVDS output data sequence in Figure 1..................................................................................................... 11
Changed pin configuration (CMOS mode) information........................................................................................................ 21
Changed pin configuration (LVDS mode) information ......................................................................................................... 23
Copyright © 2007–2008, Texas Instruments Incorporated
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Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122
PACKAGE OPTION ADDENDUM
www.ti.com
4-Dec-2007
PACKAGING INFORMATION
Orderable Device
ADS6122IRHBR
ADS6122IRHBRG4
ADS6122IRHBT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFN
RHB
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
3000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
RHB
RHB
RHB
RHB
RHB
RHB
RHB
RHB
RHB
RHB
RHB
RHB
RHB
RHB
RHB
3000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
ADS6122IRHBTG4
ADS6123IRHBR
ADS6123IRHBRG4
ADS6123IRHBT
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
ADS6123IRHBTG4
ADS6124IRHBR
ADS6124IRHBRG4
ADS6124IRHBT
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
ADS6124IRHBTG4
ADS6125IRHBR
ADS6125IRHBRG4
ADS6125IRHBT
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
ADS6125IRHBTG4
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Dec-2007
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
ADS6122IRHBR
ADS6122IRHBT
ADS6123IRHBR
ADS6123IRHBT
ADS6124IRHBR
ADS6124IRHBT
ADS6125IRHBR
ADS6125IRHBT
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
RHB
RHB
RHB
RHB
RHB
RHB
RHB
RHB
32
32
32
32
32
32
32
32
3000
250
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS6122IRHBR
ADS6122IRHBT
ADS6123IRHBR
ADS6123IRHBT
ADS6124IRHBR
ADS6124IRHBT
ADS6125IRHBR
ADS6125IRHBT
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
RHB
RHB
RHB
RHB
RHB
RHB
RHB
RHB
32
32
32
32
32
32
32
32
3000
250
340.5
340.5
340.5
340.5
340.5
340.5
340.5
340.5
333.0
333.0
338.1
338.1
338.1
338.1
338.1
338.1
20.6
20.6
20.6
20.6
20.6
20.6
20.6
20.6
3000
250
3000
250
3000
250
Pack Materials-Page 2
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