ADS61JB46_技术文档

ADS61JB46

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SBAS611B –SEPTEMBER 2013–REVISED OCTOBER 2013

14-Bit, Input-Buffered, 160-MSPS, Analog-to-Digital Converter

with JESD204A Output Interface

Check for Samples: ADS61JB46

1

FEATURES

APPLICATIONS

2

•

Output Interface:

•

Wireless Base-Station Infrastructures

Test and Measurement Instrumentation

–

Single-Lane and Dual-Lane Interfaces

Maximum Data Rate: 3.125 Gbps

DESCRIPTION

Meets JEDEC JESD204A Specification

The ADS61JB46 is a high-performance, low-power,

single-channel, analog-to-digital converter with an

integrated JESD204A output interface. Available in a

6-mm × 6-mm QFN package, with both single-lane

and dual-lane output modes, the device offers an

unprecedented level of compactness. The output

interface is compatible to the JESD204A standard,

with an additional mode (as per the IEEE standard

802.3-2002 part 3, clause 36.2.4.12) to interface

seamlessly to the TI TLK family of SERDES

transceivers. Equally impressive is the inclusion of an

on-chip analog input buffer, providing isolation

between the sample-and-hold switches and higher

and more consistent input impedance.

CML Outputs with Current Programmable

from 2 mA to 32 mA

•

Power Dissipation:

–

583 mW at 160 MSPS in Dual-Lane Mode

Power Scales Down with Clock Rate

•

Input Interface: Buffered Analog Inputs

SNR at 185-MHz IF: –72.7 dBFS

Analog Input Dynamic Range: 2 V_PP

Reference Support:

External and Internal (Trimmed)

•

Supply:

–

Analog and Digital: 1.8 V

Input Buffer: 3.3 V

The device is specified over the industrial

temperature range (–40°C to +85°C).

•

Programmable Digital Gain: 0 dB to 6 dB

Output: Straight Offset Binary or

Twos Complement

•

Package: 6-mm × 6-mm QFN-40

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADS61JB46

SBAS611B –SEPTEMBER 2013–REVISED OCTOBER 2013

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

VALUE

–0.3 to +2.2

UNIT

V

AVDD

DRVDD

IOVDD

–0.3 to +2.2

V

Supply voltage range

–0.3 to +2.2

V

AVDD_3V

–0.3 to +3.9

V

Voltage between AGND and DRGND

Voltage applied to:

–0.3 to +0.3

V

External VCM pin

Analog input pins

Digital input pins

Clock input pins⁽²⁾

–0.3 to +2.2

V

–0.3 to min (3, AVDD_3V + 0.3)

–0.3 to AVDD + 0.3

–40 to +85

V

Operating free-air temperature range, T_A

Junction temperature

°C

+105

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP, CLKM is less than |0.3 V|).

This setting prevents the electrostatic discharge (ESD) protection diodes at the clock input pins from turning on.

THERMAL INFORMATION

ADS61JB46

THERMAL METRIC⁽¹⁾

UNITS

RHA (QFN)

θ_JA

Junction-to-ambient thermal resistance

30.7

17

θ_JCtop

θ_JB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

5.7

0.2

5.7

1

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

θ_JCbot

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

2

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RECOMMENDED OPERATING CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLIES, ANALOG INPUTS, AND REFERENCE VOLTAGES

AVDD

Analog supply voltage

1.7

3.0

1.8

1.9

3.6

V

DRVDD

IOVDD

Digital supply voltage

1.8

CML buffer supply voltage

1.8

V

AVDD_3V

Analog buffer supply voltage

Differential input voltage range

Input common-mode voltage

VCM (output), internal reference mode⁽¹⁾

VCM (input), external reference mode

3.3

V

2

VCM ± 0.05

1.95

V_PP

V

1.4

V

CLOCK INPUT

In JESD204A single-lane mode

15.625

31.25

0.2

156.3

160

MSPS

V_PP

Input clock rate

In JESD204A dual-lane mode

Sine wave, ac-coupled

LVPECL, ac-coupled

LVDS, ac-coupled

3.0

1.6

0.7

V_PP

Input clock amplitude

differential (V_CLKP– V_CLKM

V_PP

)

CMOS, single-ended, ac-

coupled

1.5

V

Input clock duty cycle

Output data rate

35%

50%

65%

DIGITAL OUTPUTS

20x (sample

rate)

In single-lane mode

In dual-lane mode

312.5

3125

1600

Mbps

10x (sample

rate)

C_LOAD

R_LOAD

T_A

Maximum external load capacitance from each pin to DRGND

External termination from each output pin to IOVDD

Operating free-air temperature

5

pF

Ω

50

–40

+85

°C

(1) Typical VCM reduces to 1.85 V after HIGH_SFDR_MODE (register address 02h) is written.

Table 1. HIGH_SFDR_MODE Summary

MODE

DESCRIPTION

Write register 02h, value 71h, to obtain best HD3 for input frequencies between 150 MHz to 250 MHz.

HIGH_SFDR_MODE

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ELECTRICAL CHARACTERISTICS

Typical values are at +25°C, minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX

+85°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, clock frequency = 160 MSPS, 10x mode, 50%

=

clock duty cycle, –1-dBFS differential analog input, internal reference mode, and CML buffer current setting = 16 mA, unless

otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

REFERENCE VOLTAGES (Internal)

VCM analog input common-mode voltage (output)

1.95

2.5

V

VCM output current

(resulting in a VCM change of ±50 mV)

mA

REFERENCE VOLTAGES (External)

VCM reference voltage (input)

ANALOG INPUT

1.4 ± 0.1

V

Differential input voltage range

Differential input capacitance

Analog input bandwidth

2.0

V_PP

pF

3

480

MHz

V

Analog input common-mode range

VCM ± 0.05

Analog input common-mode current

(per input pin)

1.6

µA

DC ACCURACY

E_O

Offset error

–20

20

mV

%FS

mV/°C

dB

E_GREF

E_GCHAN

Gain error due to internal reference inaccuracy alone

Gain error of channel alone

–2.5

2.5

5

0.006

> 30

Gain error temperature coefficient

AC power-supply rejection ratio

PSRR

50-mV_PPsignal on AVDD supply

POWER-DOWN MODES

Complete power-down mode

10

230

115

±0.6

±2

mW

LSB

Fast recovery power-down mode

Power with no clock

DNL

INL

Differential nonlinearity

Integral nonlinearity

–0.95

±4.5

POWER-SUPPLY CURRENTS

I_AVDD

AVDD current

132

42

160

55

mA

mW

I_{AVDD_3V}

I_DRVDD

I_IOVDD

AVDD_3V current

DRVDD current

79

100

40

IOVDD current (in 10x mode)

31

Total power

583

700

DYNAMIC PERFORMANCE⁽¹⁾⁽²⁾

f_IN= 10 MHz

f_IN= 185 MHz

f_IN= 10 MHz

f_IN= 185 MHz

f_IN= 10 MHz

f_IN= 185 MHz

f_IN= 10 MHz

f_IN= 185 MHz

f_IN= 10 MHz

f_IN= 185 MHz

f_IN= 10 MHz

f_IN= 185 MHz

75

77

dBc

SFDR

SNR

Spurious-free dynamic range

71.5

69.2

75

dBFS

dBc

Signal-to-noise ratio

72.7

72.1

71.5

75

SINAD

HD3

Signal-to-noise and distortion ratio

Third-order harmonic distortion

Second-order harmonic distortion

Worst spur (excluding HD2, HD3)

71.5

81

77

dBc

90

dBc

HD2

81

dBc

95

dBc

90

dBc

(1) HIGH_SFDR_MODE is enabled.

(2) f_S= 156.25 MSPS, 20x mode.

4

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DIGITAL CHARACTERISTICS

The dc specifications refer to the condition where the digital outputs do not switch, but are permanently at a valid logic level

'0' or '1'.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS

V_IH

V_IL

High-level input voltage

Low-level input voltage

1.2

V

0.6

V

SEN

0

10

0

μA

I_IH

High-level input current

Low-level input current

SCLK, SDATA, RESET, PDN, PDN_ANA

SEN

I_IL

SCLK, SDATA, RESET, PDN, PDN_ANA

DIGITAL OUTPUTS (SDOUT)

V_OH

V_OL

High-level output voltage

Low-level output voltage

DRVDD – 0.1

DRVDD

0

V

0.1

1.9

CML OUTPUTS (50-Ω single-ended external termination to IOVDD)

IOVDD supply range

1.7

1.8

IOVDD

V

High-level output voltage

Low-level output voltage

IOVDD – 0.4

0.4

|VOD|

V_OCM

Output differential voltage

Output common-mode voltage

IOVDD – 0.2

Transmitter terminals shorted to any voltage

between –0.25 V and 1.45 V

Transmitter short-circuit current

–90

625

50

mA

Single-ended output impedance

Unit interval

50

Ω

UI

T_J

3200

Total jitter

0.35

175

p-pUI

t_RISE

t_FALL

,

Rise time,

Fall time

5-pF, single-ended load capacitance to ground

ps

WAKE-UP TIMING CHARACTERISTICS

PARAMETER

TEST CONDITIONS

MIN

TYP

50

10

5

MAX

UNIT

μs

Time to valid data after coming out of complete power-down mode

Time to valid data after coming out of fast-recovery power-down mode

Time to valid data after coming out of software power-down mode

Time to valid data after stopping and restarting the input clock

μs

t_WAKE

Wake-up time

μs

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PARAMETRIC MEASUREMENT INFORMATION

JESD204A OUTPUT INTERFACE

The 14-bit analog-to-digital converter (ADC) output is padded with four zeros on the LSB side to form a 16-bit

output. Two 8B10B codes are formed; one from the eight MSBs and the other from the six LSBs and the two

padded zeros, as shown in Figure 1.

ADCOUT[13:6]

ADCOUT[5:0], 0, 0

8B10B Code 1

MSB Octet

8B10B Code 2

LSB Octet

Figure 1. ADC Output Mapping to Two 8B10B Codes

The two octets can be either transmitted on the same lane (single-lane interface, Figure 2) or on two lanes (dual-

lane interface, Figure 3). By default, the device operates in single-lane interface.

Conversion Clock

(CLKP - CLKM)

CML Output Lane 1

(ADC_OUTP0 - ADC_OUTM0)

Dx.y

(ADC Data N, MSB Octet)

Dx.y

(ADC Data N, LSB Octet)

Dx.y

(ADC Data N+1, MSB Octet)

Dx.y

(ADC Data N+1, LSB Octet)

Figure 2. Single-Lane Interface Timing Diagram

Conversion Clock

(CLKP - CLKM)

CML Output Lane 1

(ADC_OUTP0 - ADC_OUTM0)

Dx.y

(ADC Data N, MSB Octet)

Dx.y

(ADC Data N+1, MSB Octet)

Dx.y

(ADC Data N+2, MSB Octet)

Dx.y

(ADC Data N+3, MSB Octet)

CML Output Lane 2

(ADC_OUTP1 - ADC_OUTM1)

Dx.y

(ADC Data N, LSB Octet)

Dx.y

(ADC Data N+1, LSB Octet)

Dx.y

(ADC Data N+2, LSB Octet)

Dx.y

(ADC Data N+3, LSB Octet)

Figure 3. Dual-Lane Interface Timing Diagram

6

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PARAMETRIC MEASUREMENT INFORMATION (continued)

A detailed dual-lane mode timing diagram is shown in Figure 4.

N+4

N+22

N+21

N+3

N+2

N+1

N+20

Sample

N

Input

Signal

t_A

CLKP

Input

Clock

CLKM

20 Clock Cycles⁽¹⁾

t_PDI

CML Output

Data Lane 1

N-21

N-20

N-19

N-18

N-17

N-1

N

N+1

N+2

CML Output

Data Lane 2

(1) These clock cycles comprise the ADC latency. At higher sampling frequencies, t_PDI> 1 clock cycle and overall latency = ADC latency + 1.

Figure 4. Dual-Lane Mode Timing Diagram

PARAMETER

30 MSPS

560

40 MSPS

560

60 MSPS

560

160 MSPS

560

UNIT

ps

T_A

T_J

Aperture delay

Aperture jitter (RMS)

Latency

125

f_S

20

Clocks

ns

t_PDI

Data propagation delay

33.3

26.2

18.9

15.3

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The receiver issues a synchronization request through the SYNC~P, SYNC~M pins whenever the frame

boundary of the output data stream must be synchronized to. Figure 5 shows how the transmission switches

from normal data (D) to code group synchronization symbols K28.5 symbols during and after a synchronization

request.

N+9

N+8

N+7

N+6

N+5

N+4

N+3

N+2

N+1

Sample

N

Input

Signal

CLKP

CLKM

Input

Clock

t_CLK-INT

Internal Clock

for Latching SYNC~

(CLK_INT)

t_SYNC-SU

t_SYNC-H

SYNC~ Input

(SYNC~P) - (SYNC~M)

t_SYNC-PDI

SYNC~ Active Latency = 9 Clock Cycles

CML Output

Data Lane 1

N-21

N-20

N-13

N-19

N-18

K28.5

N-12

N-17

N-16

N-14

N-15

CML Output

Data Lane 2

N-20

N-19

N-18

Figure 5. SYNC~ Active Timing Diagram

Table 2. SYNC~ Falling Edge Timing at 160 MSPS

PARAMETER

DESCRIPTION

TYP

UNIT

Delay from the input clock rising edge to the internal clock (CLK_INT)

rising edge used to latch the SYNC~ falling edge

t_CLK-INT

10.5

2

ns

t_SYNC-SU

SYNC~ active edge setup time

SYNC~ active edge hold time

SYNC~ active latency

Minimum delay required from SYNC~ falling edge to CLK_INT rising

edge

t_SYNC-H

Minimum delay required from CLK_INT rising edge to SYNC~ falling

edge

2

9

ns

clocks

ns

Number of clocks for K28.5 to appear at the output after a SYNC~

request

t_SYNC-PDI

SYNC~ data propagation delay

Similar to data propagation delay

15.3

8

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N+9

N+8

N+7

N+6

N+5

N+4

N+3

N+2

N+1

Sample

N

Input

Signal

CLKP

CLKM

Input

Clock

t_CLK-INT

Internal Clock

for Latching SYNC

(CLK_INT)

t_SYNCZ-SU

t_SYNCZ-H

SYNC~ Input

(SYNC~P) - (SYNC~M)

SYNC~ De-Active Latency = 8 Clock Cycles

t_SYNCZ-PDI

CML Output

Data Lane 1

K28.5

N-11

K28.5

N-12

K28.5

CML Output

Data Lane 2

Figure 6. SYNC~ De-Active Timing Diagram

Table 3. SYNC~ Rising Edge Timing at 160 MSPS

PARAMETER

DESCRIPTION

TYP

UNIT

Delay from input clock rising edge to the internal clock (CLK_INT)

rising edge used to latch the SYNC~ rising edge

10.5

ns

t_CLK-INT

t_SYNCZ-SU

SYNC~ active edge setup time

SYNC~ active edge hold time

SYNC~ de-active latency

Minimum delay required from SYNC~ rising edge to CLK_INT rising

edge

2

ns

t_SYNCZ-H

Minimum delay required from CLK_INT rising edge to SYNC~ rising

edge

ns

Number of clocks for normal data to appear at the output after a

SYNC~ de-activate request

8

Clocks

ns

t_SYNCZ-PDI

SYNC~ de-active data

propagation delay

Similar to data propagation delay

15.3

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4-LEVEL CONTROL

The DFS_EXTREF and MODE pins function as 4-level control pins in the device, as described in Table 4 and

Table 5. A simple scheme to generate a 4-level voltage is shown in Figure 7.

AVDD

(5/8) AVDD

3R

(5/8) AVDD

2R

AVDD

GND

(3/8) AVDD

3R

To Parallel Pin

(3/8) AVDD

GND

Figure 7. Simple Scheme to Configure 4-Level Control Pins

Table 4. DFS_EXTREF Pin (Pin 3)

DFS_EXTREF

DESCRIPTION

0

EXTREF = 0, DFS = 0

EXTREF = 1, DFS = 0

EXTREF = 1, DFS = 1

EXTREF = 0, DFS = 1

+150 mV / 0 mV

(3/8) AVDD

±150 mV

(5/8) AVDD

±150 mV

AVDD

0 mV / –150 mV

Key:

0 = Internal reference mode,

1 = External reference mode

EXTREF:

DFS:

0 = Twos complement output,

1 = Offset binary output

10

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PIN CONFIGURATION

RHA PACKAGE

QFN-40

(Top View)

40 39 38 37 36 35 34 33 32 31

SYNC~M

SYNC~P

DFS_EXTREF

PDN_ANA

AVDD

1

2

30

29

28

27

26

25

24

23

22

21

DRVDD

DRGND

3

SDOUT_TEST1

DRVDD

4

5

RESET

Thermal Pad

AGND

6

SCLK_SERF0_SCR

SDATA_TEST0

SEN_FALIGN_IDLE

AVDD

CLKP

7

CLKM

8

AGND

9

VCM

10

PDN

11 12 13 14 15 16 17 18 19 20

NOTE: The thermal pad is connected to DRGND.

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PIN FUNCTIONS

DESCRIPTION

NAME

ADC_OUTM0

ADC_OUTM1

ADC_OUTP0

ADC_OUTP1

AGND

NO.

34

CML output lane 1, negative output

31

CML output lane 2, negative output

CML output lane 1, positive output

CML output lane 2, positive output

35

32

5, 6, 9, 11, 14, 16, Analog ground

AVDD

15, 18, 22

Analog supply, 1.8 V

AVDD_3V

CLKM

17

8

Analog supply for input buffer, 3.3 V

Conversion clock, negative input

Conversion clock, positive input

CLKP

7

DETECT3

DETECT2

DETECT1

DETECT0

DFS_EXTREF

DRGND

DRVDD

36

37

38

39

3

Signal level-detect output pins in 1.8-V CMOS logic level.

These pins can be used to either output a 4-bit ADC code with low latency or to output a 16-level RMS power

estimate.

4-level analog control for data format selection and internal and external reference mode

Digital ground

29

27, 30

20

13

12

33

19

40

21

Digital supply, 1.8 V

FAVDD

Fuse supply, connect externally to AVDD, 1.8 V

Analog input, Negative

INM

INP

Analog input, Positive

IOVDD

CML buffer supply, 1.7 V to 1.9 V

MODE

4-level control for selecting the serial and parallel interface modes

Over-range output in 1.8-V CMOS logic levels.

Full chip power-down (also referred to as complete power-down mode)

OVR

PDN

Analog section power-down; JESD interface is still active. This mode is referred to as fast-recovery power-down

mode.

PDN_ANA

RESET

4

Serial interface RESET input. When using the serial interface mode, the internal registers must be initialized

through a hardware RESET by applying a high pulse on this pin or by using the S_RESET register bit; refer to the

Serial Interface section.

In parallel interface mode, the RESET pin must be permanently tied high. In this mode, the SEN_FALIGN_IDLE,

SCLK_SERF0_SCR, and SDATA_TEST0 pins function as parallel pins with their functionality described in

Table 6, Table 7, and Table 8, respectively.

26

Serial clock input in serial interface mode. In parallel interface mode, this pin provides a 4-level control for all

JESD modes (single-lane, dual-lane, and scrambling modes).

SCLK_SERF0_SCR

25

SDATA_TEST0

SDOUT_TEST1

24

28

Serial data input in serial interface mode. In parallel interface mode, this pin provides a JESD test mode.

Serial data out in serial interface mode. In parallel interface mode, this pin provides a JESD test mode.

Serial enable input in serial interface mode. In parallel interface mode, this pin provides a 4-level control for JESD

modes.

SEN_FALIGN_IDLE

23

SYNC~M

SYNC~P

VCM

1

2

JESD synchronization request, negative input

JESD synchronization request, positive input

10

Common-mode output for setting the input common-mode. 1.95 V, reference input in external reference mode.

12

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FUNCTIONAL BLOCK DIAGRAM

CLOCKGEN

PLL

10X, 20X

CML

Outputs

ADC_OUTP[0]

ADC_OUTM[0]

INP

INM

JESD204A

Digital

Buffer

14-Bit ADC

ADC_OUTP[1]

ADC_OUTM[1]

Signal Level

Detect

OVR

DETECT[3:0]

Control

Interface

VCM

Reference

CMOS

Outputs

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TYPICAL CHARACTERISTICS

At +25°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, f_S= 153.6 MSPS, sine-wave input clock,

1.5-V_PPdifferential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 16-mA CML current, and 32k-

point FFT, unless otherwise noted. Note that after reset, the device is in 0-dB gain mode.

0

SFDR = 74.8 dBc

SNR = 75.0 dBFS

SINAD = 72.3 dBFS

THD = 74.7 dBc

SFDR Non HD2, HD3

= 94.6 dBc

SFDR = 74.0 dBc

SNR = 74.8 dBFS

SINAD = 71.8 dBFS

THD = 73.7 dBc

SFDR Non HD2, HD3

= 97.0 dBc

−20

−40

−60

−80

−100

−120

−100

−120

0

10

20

30

40

50

60

70 76.8

0

10

20

30

40

50

60

70 76.8

Frequency (MHz)

G001

G002

Figure 8. AMPLITUDE vs FREQUENCY

(20-MHz IF)

Figure 9. AMPLITUDE vs FREQUENCY

(70-MHz IF)

0

−20

0

−20

SFDR = 81.1 dBc

SNR = 72.9 dBFS

SINAD = 72.2 dBFS

THD = 79.9 dBc

SFDR Non HD2, HD3

= 89.87 dBc

SFDR = 67.8 dBc

SNR = 71.0 dBFS

SINAD = 65.5 dBFS

THD = 65.9 dBc

SFDR Non HD2, HD3

= 83.44 dBc

−40

−60

−80

−100

−120

−100

−120

0

10

20

30

40

50

60

70 76.8

0

10

20

30

40

50

60

70 76.8

Frequency (MHz)

G003

G004

Figure 10. AMPLITUDE vs FREQUENCY

(190-MHz IF)

Figure 11. AMPLITUDE vs FREQUENCY

(300-MHz IF)

14

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TYPICAL CHARACTERISTICS (continued)

At +25°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, f_S= 153.6 MSPS, sine-wave input clock,

1.5-V_PPdifferential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 16-mA CML current, and 32k-

point FFT, unless otherwise noted. Note that after reset, the device is in 0-dB gain mode.

0

Each Tone at

−10

−7 dBFS Amplitude

f_IN1= 190 MHz

f_IN2= 185 MHz

−36 dBFS Amplitude

f_IN1= 190 MHz

f_IN2= 185 MHz

−20

IMD3 = 79.9 dBFS

IMD3 = 106.9 dBFS

−30

−40

−50

−60

−70

−80

−90

−100

−110

−120

−100

−110

−120

0

10

20

30

40

50

60

70 76.8

0

10

20

30

40

50

60

70 76.8

Frequency (MHz)

G005

G006

Figure 12. AMPLITUDE vs FREQUENCY

(Two-Tone Input Signal)

Figure 13. AMPLITUDE vs FREQUENCY

(Two-Tone Input Signal)

95

90

85

80

75

70

65

60

55

50

100

98

96

94

92

90

88

86

84

82

80

Digital gain = 0 dB

Digital gain = 2 dB

Digital gain = 6 dB

Digital gain = 0 dB

Digital gain = 2 dB

Digital gain = 6 dB

0

50 100 150 200 250 300 350 400 450 500

Input Frequency (MHz)

0

50 100 150 200 250 300 350 400 450 500

Input Frequency (MHz)

G007

G008

Figure 14. SPURIOUS-FREE DYNAMIC RANGE vs

INPUT FREQUENCY

Figure 15. SPURIOUS-FREE DYNAMIC RANGE

(NON HD2, HD3) vs INPUT FREQUENCY

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TYPICAL CHARACTERISTICS (continued)

At +25°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, f_S= 153.6 MSPS, sine-wave input clock,

1.5-V_PPdifferential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 16-mA CML current, and 32k-

point FFT, unless otherwise noted. Note that after reset, the device is in 0-dB gain mode.

78.5

130

120

110

100

90

76

75

74

73

72

71

70

69

68

67

66

65

Input Frequency = 40MHz

SNR(dBFS)

SFDR(dBc)

SFDR(dBFS)

Digital gain = 0 dB

Digital gain = 2 dB

Digital gain = 6 dB

78

77.5

77

76.5

76

80

75.5

75

70

60

74.5

74

50

40

73.5

73

30

20

72.5

10

−80

−70

−60

−50

−40

−30

−20

−10

0

Amplitude (dBFS)

0

50 100 150 200 250 300 350 400 450 500

Input Frequency (MHz)

G010

G009

Figure 16. SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY

Figure 17. PERFORMANCE ACROSS INPUT AMPLITUDE

105

77

20 MHz

70 MHz

150 MHz

220 MHz

270 MHz

300 MHz

400 MHz

500 MHz

20 MHz

70 MHz

150 MHz

220 MHz

270 MHz

300 MHz

400 MHz

500 MHz

76

75

74

73

72

71

70

69

68

67

66

65

100

95

90

85

80

75

70

65

60

55

50

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

Digital Gain (dB)

G011

G012

Figure 18. SPURIOUS-FREE DYNAMIC RANGE

vs DIGITAL GAIN

Figure 19. SIGNAL-TO-NOISE RATIO vs DIGITAL GAIN

16

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TYPICAL CHARACTERISTICS (continued)

At +25°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, f_S= 153.6 MSPS, sine-wave input clock,

1.5-V_PPdifferential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 16-mA CML current, and 32k-

point FFT, unless otherwise noted. Note that after reset, the device is in 0-dB gain mode.

78

76

74

72

70

68

66

64

62

60

58

56

90

88

86

84

82

80

78

76

74

72

70

20 MHz

70 MHz

150 MHz

220 MHz

270 MHz

300 MHz

400 MHz

500 MHz

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.95 V

Input Frequency = 190 MHz

−15 10

Temperature (°C)

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

−40

35

60

85

Digital Gain (dB)

G013

G014

Figure 20. SIGNAL-TO-NOISE AND DISTORTION RATIO

vs DIGITAL GAIN

Figure 21. SPURIOUS-FREE DYNAMIC RANGE

vs AVDD SUPPLY AND TEMPERATURE

73.9

88

87

86

85

84

83

82

81

80

79

78

77

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.95 V

AVDD_3V = 3 V

AVDD_3V = 3.1 V

AVDD_3V = 3.2 V

AVDD_3V = 3.3 V

AVDD_3V = 3.4 V

AVDD_3V = 3.5 V

AVDD_3V = 3.6 V

73.7

73.5

73.3

73.1

72.9

72.7

72.5

72.3

72.1

Input Frequency = 190 MHz

−15 10

Temperature (°C)

Input Frequency = 190 MHz

−15 10

Temperature (°C)

−40

35

60

85

−40

35

60

85

G015

G016

Figure 22. SIGNAL-TO-NOISE RATIO vs

AVDD SUPPLY AND TEMPERATURE

Figure 23. SPURIOUS-FREE DYNAMIC RANGE vs

AVDD_3V SUPPLY AND TEMPERATURE

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TYPICAL CHARACTERISTICS (continued)

At +25°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, f_S= 153.6 MSPS, sine-wave input clock,

1.5-V_PPdifferential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 16-mA CML current, and 32k-

point FFT, unless otherwise noted. Note that after reset, the device is in 0-dB gain mode.

73.8

73.6

73.4

73.2

73

89

88

87

86

85

84

83

82

81

80

79

78

77

AVDD_3V = 3 V

AVDD_3V = 3.1 V

AVDD_3V = 3.2 V

AVDD_3V = 3.3 V

AVDD_3V = 3.4 V

AVDD_3V = 3.5 V

AVDD_3V = 3.6 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.95 V

72.8

72.6

72.4

72.2

Input Frequency = 190 MHz

−15 10

Temperature (°C)

Input Frequency = 190 MHz

−15 10

Temperature (°C)

−40

35

60

85

−40

35

60

85

G017

G018

Figure 24. SIGNAL-TO-NOISE RATIO vs

AVDD_3V SUPPLY AND TEMPERATURE

Figure 25. SPURIOUS-FREE DYNAMIC RANGE vs

DRVDD SUPPLY AND TEMPERATURE

78

77.5

77

82

73.8

73.6

73.4

73.2

73

Input Frequency = 40MHz

SNR

SFDR

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.95 V

79

76

73

70

67

64

61

58

55

76.5

76

75.5

75

72.8

72.6

72.4

72.2

74.5

74

73.5

Input Frequency = 190 MHz

−15 10

Temperature (°C)

1.85

1.88

1.91

1.94

1.97

2

Input Common−Mode Voltage (V)

−40

35

60

85

G020

G001

Figure 26. SIGNAL-TO-NOISE RATIO vs

DRVDD SUPPLY AND TEMPERATURE

Figure 27. PERFORMANCE vs

INPUT COMMON-MODE VOLTAGE

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TYPICAL CHARACTERISTICS (continued)

At +25°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, f_S= 153.6 MSPS, sine-wave input clock,

1.5-V_PPdifferential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 16-mA CML current, and 32k-

point FFT, unless otherwise noted. Note that after reset, the device is in 0-dB gain mode.

76

75

74

73

72

71

70

69

68

67

66

93

90

87

84

81

78

75

72

69

66

63

78.5

80

78

76

74

72

70

68

66

64

62

60

Input Frequency = 190MHz

SNR

SFDR

Input Frequency = 40 MHz

SNR

SFDR

78

77.5

77

76.5

76

75.5

75

74.5

74

73.5

1.85

1.88

1.91

1.94

1.97

2

1.2 1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7

Input Common−Mode Voltage (V)

External Reference Voltage (V)

G021

G022

Figure 28. PERFORMANCE vs

INPUT COMMON-MODE VOLTAGE

Figure 29. PERFORMANCE vs

EXTERNAL REFERENCE VOLTAGE

76

75.5

75

90

88

86

84

82

80

78

76

74

72

70

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

90

88

86

84

82

80

78

76

74

72

70

68

66

64

62

60

Input Frequency = 190 MHz

SNR

SFDR

Input Frequency = 190MHz

SNR

SFDR

74.5

74

73.5

73

72.5

72

71.5

71

1.2 1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7

0.1 0.4 0.7

1

1.3 1.6 1.9 2.2 2.5 2.8 3.1 3.4

External Reference Voltage (V)

Differential Clock Amplitude (Vpp)

G023

G024

Figure 30. PERFORMANCE vs

EXTERNAL REFERENCE VOLTAGE

Figure 31. PERFORMANCE vs

DIFFERENTIAL CLOCK AMPLITUDE

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TYPICAL CHARACTERISTICS (continued)

At +25°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, f_S= 153.6 MSPS, sine-wave input clock,

1.5-V_PPdifferential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 16-mA CML current, and 32k-

point FFT, unless otherwise noted. Note that after reset, the device is in 0-dB gain mode.

77.5

78

45

40

35

30

25

20

15

10

5

Input Frequency = 20MHz

SNR

THD

77

77.5

77

76.5

76

76.5

76

75.5

75

75.5

75

74.5

74

74.5

74

73.5

73

73.5

73

72.5

20

30

40

50

60

70

80

0

Input Clock Duty Cycle (%)

G025

Output Codes (LSB)

G026

Figure 32. PERFORMANCE vs

INPUT CLOCK DUTY CYCLE

Figure 33. OUTPUT CODES HISTOGRAM WITH IDLE

CHANNEL INPUT

0

f_IN= 20 MHz

SFDR = 75 dBc

f_PSRR= 10 MHz

50 − mV_PP

Amplitude(f_IN) = −1 dBFS

Amplitude(f_PSRR) = −104 dBFS

Amplitude(f_IN+ f_PSRR) = −96 dBFS

Amplitude(f_IN− f_PSRR) = −98 dBFS

SFDR = 74 dBc

f_CM= 10 MHz

50 − mV_PP

Amplitude(f_IN) = −1 dBFS

Amplitude(f_CM) = −94.6 dBFS

Amplitude(f_IN+ f_CM) = −88 dBFS

Amplitude(f_IN− f_CM) = −89 dBFS

−20

−40

−20

−40

−60

−80

−100

−120

−100

−120

0

15

30

45

60

75

0

15

30

45

60

75

Frequency (MHz)

G054

G055

Figure 34. POWER-SUPPLY REJECTION RATIO SPECTRUM

FOR AVDD SUPPLY

Figure 35. COMMON-MODE REJECTION RATIO SPECTRUM

FOR AVDD SUPPLY

20

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TYPICAL CHARACTERISTICS (continued)

At +25°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, f_S= 153.6 MSPS, sine-wave input clock,

1.5-V_PPdifferential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 16-mA CML current, and 32k-

point FFT, unless otherwise noted. Note that after reset, the device is in 0-dB gain mode.

0.66

0.33

Total Power

AVDD Power

AVDD_3V Power

DRVDD Power

IOVDD Power

0.3

0.6

0.27

0.24

0.21

0.18

0.15

0.12

0.09

0.06

0.03

0

0.54

0.48

0.42

0.36

0.3

0.24

0

20

40

60

80

100

120

140

160

0

20

40

60

80

100

120

140

160

Sampling Speed (MSPS)

G056

G057

Figure 36. TOTAL POWER vs SAMPLING SPEED

Figure 37. POWER BREAK-UP vs SAMPLING SPEED

0.1

IOVDD Power

Dual−Lane(10x Mode)

Single−Lane(20x Mode)

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0

20

40

60

80

100

120

140

160

Sampling Speed (MSPS)

G058

Figure 38. IOVDD POWER vs SAMPLING SPEED

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TYPICAL CHARACTERISTICS: CONTOUR

At +25°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, f_S= 153.6 MSPS, sine-wave input clock,

1.5-V_PPdifferential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 16-mA CML current, and 32k-

point FFT, unless otherwise noted. Note that after reset, the device is in 0-dB gain mode.

79

140

64

58

73

61

76

67

70

76

120

100

80

79

82

64

58

73

61

76

67

70

76

79

60

79

82

79

70

61

400

58

73

64

350

67

76

200

40

50

100

150

250

300

450

500

f_IN- Input Frequency - MHz

70

60

65

75

80

SFDR - dBc

M0049-33

Figure 39. SFDR ACROSS INPUT AND SAMPLING FREQUENCIES

140

120

100

80

77

81

85

73

89

77

81

85

73

89

81

89

60

77

89

85

81

77

250

69

40

50

100

150

200

300

350

400

450

500

f_IN- Input Frequency - MHz

80

70

75

85

SFDR - dBc

M0049-34

Figure 40. SFDR ACROSS INPUT AND SAMPLING FREQUENCIES (6-dB Gain)

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TYPICAL CHARACTERISTICS: CONTOUR (continued)

At +25°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, f_S= 153.6 MSPS, sine-wave input clock,

1.5-V_PPdifferential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 16-mA CML current, and 32k-

point FFT, unless otherwise noted. Note that after reset, the device is in 0-dB gain mode.

140

75

73

74

72

71

70

69

120

100

80

68

75

73

72

74

71

70

69

68

67

66

60

75

69

74

100

71

200

70

72

68

73

150

67

350

65

450

64

66

400

40

50

250

300

500

f_IN- Input Frequency - MHz

64

66

68

70

72

74

SNR - dBFS

M0048-33

Figure 41. SNR ACROSS INPUT AND SAMPLING FREQUENCIES

66

140

120

100

80

69

68

67

66

69

68

67

70

66

65

60

68

67

69

70

65

400

64

450

40

50

100

150

200

250

300

350

500

70

f_IN- Input Frequency - MHz

64

65

66

67

68

69

SNR - dBFS

M0048-34

Figure 42. SNR ACROSS INPUT AND SAMPLING FREQUENCIES (6-dB Gain)

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DEVICE CONFIGURATION

PARALLEL INTERFACE MODE

The device operates in parallel interface mode when a suitable voltage is applied on the MODE pin, as described

in Table 5. In parallel interface mode, the SEN, SDATA, SCLK, and SDOUT pins functionality differs from the

serial interface mode. In this mode, the SEN_FALIGN_IDLE and SCLK_SERF0_SCR pins turn into four level-

control pins for the JESD interface (as described in Table 6 and Table 7), whereas the SDATA_TEST0 and

SDOUT_TEST1 pins turn into 2-level control pins, as described in Table 8.

Table 5. MODE Pin (Pin 19)

MODE

DESCRIPTION

0

Serial interface mode.

+150 mV/–0 mV

Pins 23, 24, and 25 are configured as SEN, SDATA, SCLK. Pins 36, 37, 38, and 39 are configured to output either

an early-signal estimate or a signal power estimate (selection is based on register settings).

(3/8)AVDD

±150 mV

Do not use

(5/8)AVDD

±150 mV

Parallel interface mode.

Pins 23, 24 and 25 are configured as parallel input pins for controlling the JESD204A modes. Pins 36, 37, 38, and

39 always output an early-signal estimate.

AVDD

+0 mV/–150 mV

Do not use

Table 6. SEN_FALIGN_IDLE Pin, in Parallel Interface Mode (Pin 23)

SEN_FALIGN_IDLE

DESCRIPTION

0

FALIGN = 0, IDLE = 0

FALIGN = 1, IDLE = 0

FALIGN = 1, IDLE = 1

FALIGN = 0, IDLE = 1

+150 mV / 0 mV

(3/8) AVDD

±150 mV

(5/8) AVDD

±150 mV

AVDD

0 mV / –150 mV

Key:

When the last octet of the current frame is the same as the last octet of the previous frame, then FALIGN determines

whether the last octet of the current frame is transmitted as is, or if the last octet is replaced by a K28.7 control symbol.

0 = Last octet transmitted as is

FALIGN:

IDLE:

1 = Last octet is replaced with a K28.7 control symbol

IDLE determines the synchronization characters transmitted during and immediately after a SYNC event.

0 = The device transmits K28.5 as per the JESD204A specification

1 = The device alternately transmits K28.5 and D5.6/D16.2 characters as per the IEEE standard 802.3-2002 (part 3, clause

36.2.4.12). This setting is the case for both single- and dual-lane modes.

24

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Table 7. SCLK_SERF0_SCR Pin, in Parallel Interface Mode (Pin 25)

SCLK_SERF0_SCR

DESCRIPTION

0

SERF0 = 0, SCR = 0

SERF0 = 1, SCR = 0

SERF0 = 1, SCR = 1

SERF0 = 0, SCR = 1

+150 mV / 0 mV

(3/8) AVDD

±150 mV

(5/8) AVDD

±150 mV

AVDD

0 mV / –150 mV

Key:

SERF0: Output serialization factor.

0 = The device transmits two octets per frame (an entire ADC channel in a single lane) with an output serialization factor of 20

1 = The device transmits one octet per frame (one ADC channel over two lanes) with an output serialization factor of 10

0 = Scrambling disabled

1 = Scrambling enabled (as per JESD204A)

SCR:

Table 8. SDATA_TEST0 and SDOUT_TEST1 Pins, in Parallel Interface Mode (Pins 24 and 28)

TEST1

TEST0

MODE

Normal mode. JESD204A encoder input is ADC data.

0

1

0

1

0

1

JESD204A encoder input is B5B5. Output is a stream of D21.5 (alternating 1s and 0s).

JESD204A encoder input is FF00.

JESD204A encoder input is a pseudo random pattern 1 + X¹⁴+ X¹⁵(regardless of whether the scrambler

is enabled or not).

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SERIAL INTERFACE

The analog-to-digital converter (ADC) has a set of internal registers that can be accessed by the serial interface

formed by the serial interface enable (SEN), serial interface clock (SCLK), and serial interface data (SDATA)

pins. Serially shifting bits into the device is enabled when SEN is low. SDATA serial data are latched at every

SCLK falling edge when SEN is active (low). The serial data are loaded into the register at every 16th SCLK

falling edge when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data

can be loaded in multiples of 16-bit words within a single active SEN pulse.

The first eight bits form the register address and the remaining eight bits are the register data. The interface can

function with SCLK frequencies from 20 MHz down to very low speeds (of few Hertz) and also with a non-50%

SCLK duty cycle.

Register Initialization

After power-up, the internal registers must be initialized to the default values. This initialization can be

accomplished in one of two ways:

1. Either through a hardware reset by applying a high-going pulse on RESET pin (of widths greater than 10 ns),

as shown in Figure 43,

or

2. By applying a software reset. Using the serial interface, set the S_RESET bit (bit D1 in register 00h) high.

This setting initializes the internal registers to the default values and then self-resets the S_RESET bit low. In

this case, the RESET pin is kept low.

Register Address

Register Data

SDATA

SCLK

SEN

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

t_DH

t_SCLK

t_DSU

t_SLOADS

t_SLOADH

RESET

Figure 43. Serial Interface Timing Diagram

Table 9. Timing Characteristics for Figure 43⁽¹⁾

PARAMETER

MIN TYP

MAX UNIT

f_SCLK

t_SLOADS

t_SLOADH

t_DS

SCLK frequency (= 1/ t_SCLK

SEN to SCLK setup time

SCLK to SEN hold time

SDATA setup time

)

> DC

25

20

MHz

ns

25

ns

25

ns

t_DH

SDATA hold time

25

ns

(1) Typical values are at T_A= +25°C, minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX

+85°C, AVDD = 1.8 V, AVDD_3V = 3.3 V, DRVDD = 1.8 V, and IOVDD = 1.8 V, unless otherwise noted.

=

26

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Serial Register Readout

The device includes an option where the contents of the internal registers can be read back. This readback may

be useful as a diagnostic check to verify the serial interface communication between the external controller and

the ADC.

1. First, set the SERIAL_READOUT register bit = 1. This setting also disables any further register writes

(except for writes to the SERIAL_READOUT register bit).

2. Initiate a serial interface cycle specifying the address of the register (A[7:0]) whose content must be read.

3. The device outputs the contents (D[7:0]) of the selected register on the SDOUT_TEST1 pin.

4. The external controller latches the contents at the SCLK falling edge.

5. To enable register writes, reset the SERIAL_READOUT register bit = 0.

Reset Timing

Figure 44 shows a reset timing diagram.

Power Supply

(AVDD, DRVDD)

t₁

RESET

t₂

t₃

SEN

NOTE: A high-going pulse on the RESET pin is required for initialization through a hardware reset.

Figure 44. Reset Timing Diagram

Table 10. Timing Characteristics for Figure 44⁽¹⁾

PARAMETER

CONDITIONS

MIN TYP

MAX UNIT

t₁

t₂

t₃

Power-on delay

Delay from power-up of AVDD and DRVDD to RESET pulse active

1

ms

Reset pulse duration Pulse duration of the active RESET signal that resets the serial registers

Serial interface delay Delay from RESET disable to SEN active

10

100

ns

(1) Typical values are at T_A= +25°C and minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX

+85°C, unless otherwise noted.

=

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SERIAL INTERFACE REGISTER MAP

BIT LOCATION

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REGISTER BIT NAME

ADDRESS

DESCRIPTION

BIT

(Hex)

S_RESET

00

1

0

Software reset. This mode has the same function as a hardware reset.

0 = Serial interface write (default)

1 = Serial readout

SERIAL_READOUT

00

02

Set these bits to obtain the best HD3 when the input frequency is between 150 MHz to

250 MHz.

HIGH_SFDR_MODE

6:4, 0

This bit provides the override control mode for the DFS_EXTREF pin when controlling

the DFS select mode. This bit controls the DFS_EXTREF pin with the DFS_REG

register bit.

DFS_OVERRIDE

3C

7

0 = DFS functionality determined by DFS_EXTREF pin

1 = DFS functionality determined by DFS_REG pin

This bit is the register bit for DFS control.

0 = Output format is twos complement.

1 = Output format is offset binary. This setting takes effect when DFS_OVERRIDE is set

to ‘1’.

DFS_REG

6

CUSTOM_PAT[13:6]

CUSTOM_PAT[5:0]

3E

3F

7:0

7:2

Eight MSBs of the 14-bit custom pattern can be programmed.

Six LSBs of the 14-bit custom pattern can be programmed.

This bit is the override control for DFS_EXTREF pin when controlling the

internal/external reference select mode. This bit controls the DFS_EXTREF pin with the

INT_REF_REG register bit.

INT_REF_OVERRIDE

INT_REF_REG

44

3

2

0 = Internal/external reference mode is determined by the DFS_EXTREF pin

1 = Internal/external reference mode is determined by the INT_REF_REG

This bit is the register bit for internal/external reference mode control.

0 = Internal reference mode.

1 = External reference mode. This setting takes effect when INT_REF_OVERRIDE is

set to ‘1’.

S_PDN

44

45

6

Software power-down.

0-dB to 6-dB digital gain in 0.5-dB steps (default gain is 0 dB). Refer to the Fine-Gain

Control section for further details.

FINE_GAIN[3:0]

7:4

Digital gain bypass. Digital gain is enabled by default. When this bit set to '1', digital gain

(fine gain) is bypassed.

BYPASS_FINE_GAIN

45

These bits control the output test patterns.

000 = ADC output data bus is input to JESD204A encoder block

001 = ADC bus is replaced by the minimum code (00000000000000 in offset binary).

010 = ADC bus replaced by the maximum code (11111111111111 in offset binary).

100 = ADC bus replaced by a ramping code pattern that increments by 1 LSB every four

clocks (and folds back to the minimum code when the maximum code is reached).

ADC_TEST_PAT[2:0]

45

2:0

101 = ADC bus is replaced by custom patterns. The patterns are programmed by

registers 3E and 3F.

011, 110, 111 = Do not use

0 = Initial lane alignment sequence is not transmitted (default)

1 = Initial lane alignment sequence (as per JESD204A) is sent after the code group sync

in both single- and dual-lane interfaces

TXMIT_LINKDATA_EN

A0

0

Software Frame Align control.

This bit enables frame alignment monitoring.

When scrambling is enabled and this bit is ‘1’, this bit is encoded as K28.7 when the last

scrambled octet in a frame equals FC.

S_FALIGN bit control is similar to the FALIGN pin control.

S_FALIGN

1

When this bit is 0 = There is no replacement.

1 = When scrambling is off, if the last octet in the previous frame is the same as the last

octet in the current frame, then the last octet in the current frame is replaced with a

frame alignment symbol K28.7

Multiframe align control.

MFALIGN

A0

2

This bit functions similarly to S_FALIGN, but refers to multiframe instead.

The multiframe alignment symbol is K28.3.

28

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BIT LOCATION

REGISTER BIT NAME

DESCRIPTION

ADDRESS

(Hex)

BIT

By default, the last octet in the frame is derived from the data octet on the LSB side. The

occurrence of consecutive last octets may be rare because the LSB octets usually

switch more (frame-to-frame) than the MSB octets. This condition can lead to an

infrequent occurrence of frame alignment symbols. To increase the rate of consecutive

last octets (and thereby the rate of frame and multiframe alignment symbols), this bit can

be set to '1'.

FLIP_ADC_BUS

A0

3

Setting this bit to '1' flips the bit order of the ADC inputs (N bits) to the JESD204A logic.

Note that the two zeros padded at the end to cause the JESD204A logic input to remain

unchanged.

This bit enables the transmission of the test sequence mentioned in the JESD204A

document.

TESTMODE_EN

S_IDLE

A0

4

5

Software idle generation control.

Normally the output during code group synchronization is K28.5. When S_IDLE is set to

'1', the device output is a K28.5 comma followed by either a D5.6 or a D16.2 alignment

symbol. This configuration is as per IEEE standard 802.3-2002 (part 3, clause 36.2.4.12)

and enables compatibility with TI’s TLK family of devices.

This bit control is similar to the IDLE pin control (see Table 6).

S_TEST0

S_TEST1

CTRL_F

CTRL_K

S_SCR

A0

A1

A5

6

7

0

1

7

These two bit controls are similar to the TEST1 and TEST0 pin controls.

This bit enables writes into register A6h, bits 7:0.

This bit enables writes into register A7h, bits 4:0.

Software scrambling enable. This bit control is similar to the SCR pin control.

These bits control the number of octets per frame.

Default is set to 00000001 (2 – 1), which is two octets per frame (single-lane mode). For

a two-lane output (one octet per frame), set these bits to 00000000.

Note that in order to override default, CTRL_F must be set to '1'.

F[7:0]

A6

7:0

These bits control the number of frames per each multiframe (minus 1). Default depends

on value of bits F[7:0].

When F = 0 (10x mode), K = 16 (17 frames per multiframe)

When F = 1 (20x mode), K = 8 (nine frames per multiframe)

K[4:0]

A7

4:0

Note that to override the default value of bits K[4:0], CTRL_K must be set to '1'. When

CTRL_K is set to '1', the value programmed in bits A7[4:0] denotes the number of

frames per multiframe (minus 1). For example, to set the number of frames per

multiframe to 23, set CTRL_K = 1 and A7[4:0] = 10110.

CML buffer current select. Default (0000) is 16 mA.

CML_I[3:0]

B0

B4

3:0

3

Current is calculated as: 16 mA +16 mA × bit 3 – 8 mA × bit 2 – 4 mA × bit 1 – 2 mA ×

bit 0

This bit replaces the output of the 8b/10b coder (corresponding to the MSB octet) with a

10-bit word specified in the OUT_WORD_LANE1[9:0] bits.

FORCE_OUT_LANE1

OUT_WORD_LANE1[9:0]

FORCE_OUT_LANE2

B6

B7

7:0

7:6

These bits are a 10-bit word replacing the output of the 8b/10b coder when

FORCE_OUT_LANE1 is set to ‘1’.

This bit replaces the output of the 8b/10b coder (corresponding to the LSB octet) with a

10-bit word specified in the OUT_WORD_LANE2[9:0] bits.

B4

6

B8

B9

D6

7:4

7:2

0

These bits are a 10-bit word replacing the output of the 8b/10b coder when

FORCE_OUT_LANE2 is set to ‘1’.

OUT_WORD_LANE2[9:0]

EN_SIG_EST

This bit outputs a 4-bit ADC code with low latency on the DETECT[3:0] bits.

This bit outputs a 4-bit average power estimate of the input signal on the DETECT[3:0]

bits.

Power estimate is in dB scale in steps of approximately 1 dB. Refer to the Signal Power

Estimation section.

EN_PWR_EST

D6

5

These bits determine the number of samples to average for power estimation.

These bits are programmable from 1K to 16K.

SAMPLES_PWR_EST[2:0]

4:2

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REGISTER MODES

A brief summary of different register modes and respective locations in the digital processing flow of the

ADS61JB46 is shown in Figure 45 and Figure 46.

ADC Digital Block

(Data Format,

Digital Gain)

ADC

ADC Test

Pattern

Generator

To

Frame to

JESD Test

Pattern

Generator

FINE_GAIN[3:0]

DFS

Octet Conversion

JESD

Test Mode

Generator

ADC_TEST_PAT[2:0]

TEST0, TEST1

TESTMODE_EN

Figure 45. Register Modes Before Frame to Octet Conversion Block

MSB octet

TXMIT_LINKDATA_EN

SYNC~

To SERDES

SYNC~

Decoder

TX

Controller

ILAS

Generator

OUT_WORD_LANE1[9:0]

8B, 10B

Coder

FORCE_OUT_LANE1

Frame to

Octet

Stream

Alignment

Character

Generator

Scrambler

LSB octet

Conversion

To SERDES

OUT_WORD_LANE2[9:0]

FLIP_ADC_BUS

SCR

SCR, FALIGN, MALIGN

FORCE_OUT_LANE2

Figure 46. Register Modes After Frame to Octet Conversion Block

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INITIAL LANE ALIGNMENT SEQUENCE

By default, the initial lane alignment sequence is not transmitted. To enable transmission of the initial lane

alignment sequence, for the two settings of F, the mapping of the link configuration fields to octets of the

JESD204A specification is shown in Table 11.

Table 11. Link Configuration Fields Mapping to Octets

CONFIGURATION

MSB

6

5

4

3

2

1

LSB

OCTET NO.

F = 1 (20x Mode)

0

1

2

DID[7:0] = 00000000

X

BID[3:0] = 0000

LID[4:0] = 00000

L[4:0] = 00000

SCR[0], set

by S_SCR

3

X

4

5

F[7:0] = 00000001

X

K[4:0] = 01000 (or programmed value of A7[4:0] if CTRL_K = 1)

6

M[7:0] = 00000000

N[4:0] = 01101

7

CS[1:0] = 00

X

8

X

N'[4:0] = 01111

9

S[4:0] = 00000

10

11

12

13

HD[0] = 0

CF[4:0] = 00000

RES1[7:0], set to all 0s

RES2[7:0], set to all 0s

FCHK[7:0]

F = 0 (10x Mode)

0

1

2

DID[7:0] = 00000000

X

BID[3:0] = 0000

LID[4:0] = 00000 for lane 1 and 00001 for lane 2

SCR[0], set

by S_SCR

3

X

L[4:0] = 00001

4

5

F[7:0] = 00000000

K[4:0] = 10000 (or programmed value of A7[4:0] if CTRL_K = 1)

M[7:0] = 00000000

X

6

7

CS[1:0] = 00

X

N[4:0] = 01101

8

X

N'[4:0] = 01111

9

S[4:0] = 00000

10

11

12

13

HD[0] = 0

CF[4:0] = 00000

RES1[7:0], set to all 0s

RES2[7:0], set to all 0s

FCHK[7:0]

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APPLICATION INFORMATION

THEORY OF OPERATION

The ADS61JB46 is a buffered analog input, ultralow power ADC with maximum sampling rates up to 160 MSPS.

The conversion process is initiated by a rising edge of the external input clock and the analog input signal is also

sampled. The sampled signal is sequentially converted by a series of small-resolution stages, with the outputs

combined in a digital correction logic block. At every clock edge the sample propagates through the pipeline,

resulting in a data latency of 20 clock cycles. The output is available as 14-bit data, coded in either straight offset

binary or binary twos complement format, with a JESD207A interface in CML logic levels.

ANALOG INPUTS

The analog input pins have analog buffers (running off of the AVDD3V supply) that internally drive the differential

sampling circuit. As a result of the analog buffer, the input pins present high input impedance to the external

driving source (10-kΩ dc resistance and 3-pF input capacitance). The buffer helps isolate the external driving

source from the switching currents of the sampling circuit. This buffering makes driving buffered inputs easier

when compared to an ADC without the buffer.

The input common-mode is set internally using a 5-kΩ resistor from each input pin to 1.95 V, so the input signal

can be ac-coupled to the pins. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.5 V) and

(VCM – 0.5 V), resulting in a 2-V_PPdifferential input swing.

The input sampling circuit has a high 3-dB bandwidth that extends up to 450 MHz (measured from the input pins

to the sampled voltage). Figure 47 shows an equivalent circuit for the analog input.

LPIN1

1 nH (±0.± nHꢀ

ROUTE1

15 W (±ꢂ Wꢀ

INP_ADC

INP_PIN

5 pF (±0.5 pFꢀ

CBUF1

0.5 pF

CESD1

5000 W (±ꢁ00 Wꢀ

RVCM1

5 W (±± Wꢀ

RBUF1

0.5 pF

CPBUF1

5000 W (±ꢁ00 Wꢀ

RVCM±

LPIN±

1 nH (±0.± nHꢀ

ROUTE±

15 W (±ꢂ Wꢀ

INM_ADC

INM_PIN

5 pF (±0.5 pFꢀ

CBUF±

0.5 pF

CESD±

5 W (±± Wꢀ

RBUF±

0.5 pF

CPBUF±

Figure 47. Analog Input Equivalent Circuit

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DRIVE CIRCUIT REQUIREMENTS

For optimum performance, the analog inputs must be driven differentially. This technique improves the common-

mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω) in series with each input pin is

recommended to damp out ringing caused by package parasitics.

Figure 48 and Figure 49 show the differential impedance (Z_IN= R_IN|| C_IN) at the ADC input pins. The presence of

the analog input buffer results in an almost constant input capacitance up to 1 GHz.

INP

C_IN

R_IN

INM

Note that at frequency (f), the real part of input impedance (input resistance) = R_IN, the imaginary part of input impedance = 1 / (2 × πF ×

C_IN), and input capacitance = C_IN

.

Figure 48. Analog Input Equivalent Impedance Model

Frequency - MHz

Figure 49. R_INand C_INversus Frequency

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EXAMPLE DRIVING CIRCUITS

Two example driving circuit configurations are shown in Figure 50 and Figure 51, one optimized for low input

frequencies and the other for high input frequencies. The presence of internal analog buffers makes the

ADS61JB46 simple to drive by absorbing any ADC kick-back noise. The mismatch in the transformer parasitic

capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two

identical RF transformers back-to-back helps minimize this mismatch and good performance is obtained in the

input frequency range of interest.

The drive circuit for low input frequencies (< 200 MHz) in Figure 50 uses two back-to-back connected ADT1-1

transformers terminated by 50 Ω near the ADC side. An additional termination resistor pair may be required

between the two transformers to improve even-order harmonic performance, as shown in drive circuit for high

input frequencies (> 200 MHz) in Figure 51. The center point of this termination is connected to ground to

improve the balance between the P (positive) and M (negative) sides. The example circuit in Figure 51 uses two

back-to-back connected ADTL2-18 transformers with a 200-Ω termination between them and a secondary 100 Ω

at the second transformer to obtain an effective 50 Ω (for a 50-Ω source impedance). The ac-coupling capacitors

allow the analog inputs to self-bias around the required common-mode voltage.

0.1 mF

5 W

INP

25 W

0.1 mF

INM

5 W

1:1

Figure 50. Drive Circuit with Low Bandwidth (for Low Input Frequencies)

0.1 mF

5 W

INP

100 W

50 W

0.1 mF

100 W

INM

5 W

1:2

2:1

Figure 51. Drive Circuit with High Bandwidth (for High Input Frequencies)

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CLOCK INPUT

The ADS61JB46 clock inputs can be driven differentially by a sine, LVPECL, or LVDS source with little or no

difference in performance between them. The common-mode voltage of the clock inputs is set to 0.95 V using

internal 5-kΩ resistors, as shown in Figure 52. This setting allows the use of transformer-coupled drive circuits for

a sine-wave clock or ac-coupling for LVPECL and LVDS clock sources (see Figure 53, Figure 54, and

Figure 55). For best performance, the clock inputs must be driven differentially, thereby reducing susceptibility to

common-mode noise. TI recommends keeping the differential voltage between clock inputs less than 1.8 V_PPto

obtain best performance. For high input frequency sampling, TI recommends using a clock source with very low

jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in

performance with a non-50% duty cycle clock input.

Clock Buffer

L_PKG

~ 2 nH

20 Ω

CLKP

C_BOND

~ 1 pF

C_EQ

5 kΩ

R

ESR

~ 100 Ω

0.95V

5 kΩ

L

PKG

~ 2 nH

20 Ω

CLKM

C_BOND

~ 1 pF

R

ESR

~ 100 Ω

NOTE: C_EQis 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.

Figure 52. Internal Clock Buffer

0.1 μF

Z_o

0.1 μF

CLKP

Typical LVDS

Clock Input

Differential

Sine-Wave

Clock Input

100 Ω

R_T

Z_o

0.1 μF

CLKM

0.1 μF

CLKM

Figure 54. LVDS Clock Driving Circuit

Figure 53. Differential Sine-Wave Clock Driving

Circuit

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Z_o

0.1 μF

CLKP

150 Ω

Typical LVPECL

Clock Input

100 Ω

Z_o

0.1 μF

CLKM

150 Ω

Figure 55. LVPECL Clock Driving Circuit

FINE-GAIN CONTROL

The ADS61JB46 includes gain settings that can be used to obtain improved SFDR performance (compared to no

gain). The gain is programmable from 0 dB to 6 dB (in 0.5-dB steps). For each gain setting, the analog input full-

scale range scales proportionally, as shown in Table 12.

SFDR improvement is achieved at the expense of SNR; for each gain setting, SNR degrades approximately 0.5

dB. SNR degradation is reduced at high input frequencies. As a result, fine gain is very useful at high input

frequencies because SFDR improvement is significant with marginal degradation in SNR. Therefore, fine gain

can be used to trade-off between SFDR and SNR. Note that the default gain after reset is 0 dB.

Table 12. Full-Scale Range Across Gains

FINE_GAIN[3:0]

0000

GAIN (dB)

TYPE

FULL-SCALE (V_PP)

0

0.5

1

2.00

1.89

1.78

1.68

1.59

1.5

0001

0010

0011

1.5

2

0100

0101

2.5

3

Fine gain, programmable

(default after reset)

0110

1.42

1.34

1.26

1.19

1.12

1.06

1.00

0111

3.5

4

1000

1001

4.5

5

1010

1011

5.5

6

1100

1101

1110

Do not use

1111

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SIGNAL POWER ESTIMATION

The device includes a power estimation circuit that can be used to obtain a coarse power estimate (accurate to

within a dB) of the input signal averaged over a programmable number of samples. Enable the EN_PWR_EST

bit in order to make the power estimate available on the DETECT[3:0] pins. The states of the DETECT[3:0] bits

map to the input signal power as shown in Table 13.

Table 13. State of DETECT[3:0] Versus Input Signal Power

INPUT SIGNAL POWER

RANGE (dBFS)

INPUT SIGNAL POWER RANGE

(dBFS)

DETECT[3:0]

–Inf to –12.5

–12.5 to –11.5

–11.5 to –10.5

–10.5 to –9.5

–9.5 to –8.5

–8.5 to –7.5

–7.5 to –6.5

0001

0010

0011

0100

0101

0110

0111

–6.5 to –5.5

–5.5 to –4.5

–4.5 to –3.5

–3.5 to –2.5

–2.5 to –1.5

–1.5 to 0

1000

1001

1010

1011

1100

1101

1110

0 to +1

The number of samples used for computing the average power is set by SAMPLES_PWR_EST[2:0], as shown in

Table 14.

Table 14. Number of Samples Used for Power

Estimation

SAMPLES_PWR_EST[2:0]

NUMBER OF SAMPLES

000

001

010

011

100

1K

2K

4K

8K

16K

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DEFINITION OF SPECIFICATIONS

Analog Bandwidth: The analog input frequency at which the power of the fundamental is reduced by 3 dB with

respect to the low-frequency value.

Aperture Delay: The delay in time between the rising edge of the input sampling clock and the actual time at

which the sampling occurs. This delay is different across channels. The maximum variation is specified as

aperture delay variation (channel-to-channel).

Aperture Uncertainty (Jitter): The sample-to-sample variation in aperture delay.

Clock Pulse Duration and Duty Cycle: The duty cycle of a clock signal is the ratio of the time the clock signal

remains at a logic high (clock pulse duration) to the period of the clock signal. Duty cycle is typically expressed

as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle.

Maximum Conversion Rate: The maximum sampling rate at which certified operation is given. All parametric

testing is performed at this sampling rate unless otherwise noted.

Minimum Conversion Rate: The minimum sampling rate at which the ADC functions.

Differential Nonlinearity (DNL): An ideal ADC exhibits code transitions at analog input values spaced exactly 1

LSB apart. DNL is the deviation of any single step from this ideal value, measured in units of LSBs.

Integral Nonlinearity (INL): INL is the deviation of the ADC transfer function from a best-fit line determined by a

least-squares-curve fit of that transfer function, measured in units of LSBs.

Gain Error: Gain error is the deviation of the ADC actual input full-scale range from its ideal value. Gain error is

given as a percentage of the ideal input full-scale range. Gain error has two components: error resulting from

reference inaccuracy and error resulting from the channel. Both errors are specified independently as E_GREFand

E_GCHAN, respectively.

To a first-order approximation, the total gain error is E_TOTAL~ E_GREF+ E_GCHAN

.

For example, if E_TOTAL= ±0.5%, the full-scale input varies from (1 – 0.5 / 100) × FS_idealto (1 + 0.5 / 100) × FS_ideal

.

Offset Error: Offset error is the difference, given in number of LSBs, between the ADC actual average idle

channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts.

Temperature Drift: The temperature drift coefficient (with respect to gain and offset error) specifies the change

per degree Celsius of the parameter from T_MINto T_MAX. The coefficient is calculated by dividing the maximum

deviation of the parameter across the T_MINto T_MAXrange by the difference of T_MAX– T_MIN

.

Signal-to-Noise Ratio (SNR): SNR is the ratio of the power of the fundamental (P_S) to the noise floor power

(P_N), excluding the power at dc and the first nine harmonics.

P_S

SNR = 10Log¹⁰

P_N

(1)

SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the

reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-

scale range.

Signal-to-Noise and Distortion (SINAD): SINAD is the ratio of the power of the fundamental (P_S) to the power

of all other spectral components including noise (P_N) and distortion (P_D), but excluding dc.

P_S

SINAD = 10Log¹⁰

P_N+ P_D

(2)

SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the

reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-

scale range.

38

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SBAS611B –SEPTEMBER 2013–REVISED OCTOBER 2013

Effective Number of Bits (ENOB): ENOB is a measure of the converter performance as compared to the

theoretical limit based on quantization noise.

SINAD - 1.76

ENOB =

6.02

(3)

Total Harmonic Distortion (THD): THD is the ratio of the power of the fundamental (P_S) to the power of the first

nine harmonics (P_D).

P_S

THD = 10Log¹⁰

P_N

(4)

THD is typically given in units of dBc (dB to carrier).

Spurious-Free Dynamic Range (SFDR): SFDR is the ratio of the power of the fundamental to the highest other

spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).

Two-Tone Intermodulation Distortion (IMD3): IMD3 is the ratio of the power of the fundamental (at frequencies

f₁and f₂) to the power of the worst spectral component at either frequency (2f₁– f₂) or (2f₂– f₁). IMD3 is either

given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or

dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.

DC Power-Supply Rejection Ratio (DC PSRR): DC PSSR is the ratio of the change in offset error to a change

in analog supply voltage. DC PSRR is typically given in units of millivolts per volt.

AC Power-Supply Rejection Ratio (AC PSRR): AC PSRR is the measure of rejection of variations in the supply

voltage by the ADC. If ΔV_SUPis the change in supply voltage and ΔV_OUTis the resultant change of the ADC

output code (referred to the input), then:

DV_OUT

PSRR = 20Log¹⁰

(Expressed in dBc)

DV_SUP

(5)

Voltage Overload Recovery: The number of clock cycles taken to recover to less than 1% error after an

overload on the analog inputs. This overload recovery is tested by separately applying a sine-wave signal with a

6-dB positive and negative overload. The deviation of the first few samples after the overload (from the expected

values) is noted.

Common Mode Rejection Ratio (CMRR): CMRR is the measure of rejection of variation in the analog input

common-mode by the ADC. If ΔV_{CM_IN}is the change in the common-mode voltage of the input pins and ΔV_OUTis

the resultant change of the ADC output code (referred to the input), then:

DV_OUT

10

CMRR = 20Log

(Expressed in dBc)

DV_CM

(6)

Crosstalk (only for multichannel ADCs): Crosstalk is a measure of the internal coupling of a signal from

adjacent channel into the channel of interest. Crosstalk is specified separately for coupling from the immediate

neighboring channel (near-channel) and for coupling from a channel across the package (far-channel). Crosstalk

is usually measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of

the coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the

adjacent channel input. Crosstalk is typically expressed in dBc (dB to carrier).

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REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (October 2013) to Revision B

Page

•

Changed document status from Product Preview to Production Data ................................................................................. 1

Changed Power-Down Modes, Fast recovery power-down mode, DNL, and INL parameter specifications in

Electrical Characteristics table .............................................................................................................................................. 4

•

Changed Power-Supply Currents, I_IOVDDparameter name in Electrical Characteristics table .............................................. 4

Changed f_Svalue in footnote 2 of Electrical Characteristics table ........................................................................................ 4

Changed CML Outputs, IOVDD supply range parameter minimum specification in Digital Characteristics table ............... 5

Changed description of DETECT[3:0], OVR, and RESET pins in Pin Functions table ...................................................... 12

Changed DAC to ADC in functional block diagram ............................................................................................................ 13

Deleted Differential Nonlinearity (DNL) and Integrated Nonlinearity (INL) curves from Typical Characteristics ................ 19

Changed legend in Figure 38 ............................................................................................................................................. 21

Changed footnote 1 in Table 9 ........................................................................................................................................... 26

Changed Serial Register Readout section into two sections: Serial Register Readout and Reset Timing ........................ 27

Changed number of clock cycles for data latency in Theory of Operation section ............................................................ 32

Changed 2-pF input capacitance to 3-pF input capacitance in Analog Inputs section ....................................................... 32

Changes from Original (September 2013) to Revision A

Page

•

Changed data rate value in 1st Features bullet .................................................................................................................... 1

Changed dual-lane mode value in 2nd Features bullet ........................................................................................................ 1

Changed 4th and 5th Features bullets ................................................................................................................................. 1

Added Recommended Operating Conditions table and Table 1 .......................................................................................... 3

Added Electrical Characteristics tables ................................................................................................................................ 4

Added Parametric Measurement Information section ........................................................................................................... 6

Added Pin Configuration section ........................................................................................................................................ 11

Added Functional Block Diagram section ........................................................................................................................... 13

Added Typical Characteristics sections .............................................................................................................................. 14

Added Device Configuration section ................................................................................................................................... 24

Added Application Information section ............................................................................................................................... 32

40

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PACKAGE MATERIALS INFORMATION

www.ti.com

11-Oct-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADS61JB46IRHAR

ADS61JB46IRHAT

VQFN

RHA

40

2500

250

330.0

16.4

6.3

1.5

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Oct-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ADS61JB46IRHAR

ADS61JB46IRHAT

VQFN

RHA

40

2500

250

336.6

28.6

Pack Materials-Page 2

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型号：	ADS61JB46
厂家：	TEXAS INSTRUMENTS
描述：	14-Bit, Input-Buffered, 160-MSPS, Analog-to-Digital Converter with JESD204A Output Interface 14位，输入缓冲， 160 - MSPS ，模拟 - 数字转换器JESD204A输出接口转换器
文件：	总48页 (文件大小：1903K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS61JB46 [TI]

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