首页 |元器件品牌

ADS62P28 [TI]

Dual Channel 14-/12-Bit, 250-/210-MSPS ADC With DDR LVDS and Parallel CMOS Outputs; 双通道14位/ 12位， 250 / 210 - MSPS ADC，具有DDR LVDS和并行CMOS输出
ADS62P28
型号： ADS62P28
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

Dual Channel 14-/12-Bit, 250-/210-MSPS ADC With DDR LVDS and Parallel CMOS Outputs
双通道14位/ 12位， 250 / 210 - MSPS ADC，具有DDR LVDS和并行CMOS输出

双倍数据速率
文件： 总76页 (文件大小：2133K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
Dual Channel 14-/12-Bit, 250-/210-MSPS ADC With DDR LVDS and Parallel CMOS Outputs  
1
FEATURES  
•
•
Internal and External Reference Support  
64-QFN Package (9 mm × 9 mm)  
•
•
•
•
•
Maximum Sample Rate: 250 MSPS  
14-Bit Resolution – ADS62P49/ADS62P48  
12-Bit Resolution – ADS62P29/ADS62P28  
Total Power: 1.25 W at 250 MSPS  
ADS62PXX HIGH SPEED FAMILY  
250 MSPS  
ADS62P49  
ADS62P29  
210 MSPS  
ADS62P48  
ADS62P28  
200 MSPS  
14-Bit Family  
Double Data Rate (DDR) LVDS and Parallel  
CMOS Output Options  
12-Bit Family  
11-Bit Family  
ADS62C17  
•
Programmable Gain up to 6dB for SNR/SFDR  
Trade-Off  
•
•
•
DC Offset Correction  
90dB Cross-Talk  
Supports Input Clock Amplitude Down to 400  
mVPP Differential  
DESCRIPTION  
The ADS62Px9/x8 is a family of dual channel 14-bit and 12-bit A/D converters with sampling rates up to 250  
MSPS. It combines high dynamic performance and low power consumption in a compact 64 QFN package. This  
makes it well-suited for multi-carrier, wide band-width communications applications.  
The ADS62Px9/x8 has gain options that can be used to improve SFDR performance at lower full-scale input  
ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS  
(Double Data Rate) and parallel CMOS digital output interfaces are available.  
It includes internal references while the traditional reference pins and associated decoupling capacitors have  
been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified  
over the industrial temperature range (–40°C to 85°C).  
Performance Summary  
AT 170MHZ INPUT  
ADS62P49  
ADS62P48  
78  
ADS62P29  
ADS62P28  
78  
0 dB gain  
6 dB gain  
0 dB gain  
6 dB gain  
75  
82  
75  
82  
SFDR, dBc  
84  
84  
69.8  
66.5  
1
70.1  
68.3  
65.8  
1
68.7  
SINAD, dBFS  
66.3  
65.8  
Analog Power, W  
0.92  
0.92  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009, Texas Instruments Incorporated  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
LVDS INTERFACE  
DA0_P/M  
DA2_P/M  
DA4_P/M  
Digital  
and  
DDR  
INA_P  
INA_M  
Sample  
and  
Hold  
14-Bit  
ADC  
DA6_P/M  
DA8_P/M  
DA10_P/M  
DA12_P/M  
Serializer  
Output  
Clock  
Buffer  
CLKP  
CLKM  
CLOCKGEN  
CLKOUTP/M  
DB0_P/M  
DB2_P/M  
DB4_P/M  
Digital  
and  
DDR  
INB_P  
INB_M  
Sample  
and  
Hold  
14-Bit  
ADC  
DB6_P/M  
DB8_P/M  
DB10_P/M  
DB12_P/M  
Serializer  
VCM  
Reference  
Control Interface  
SDOUT  
ADS62P49/48  
B0349-01  
Figure 1. ADS62P49/48 Block Diagram  
2
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
LVDS INTERFACE  
DA0_P/M  
DA2_P/M  
DA4_P/M  
Digital  
and  
DDR  
INA_P  
INA_M  
Sample  
and  
Hold  
12-Bit  
ADC  
DA6_P/M  
DA8_P/M  
DA10_P/M  
Serializer  
Output  
Clock  
Buffer  
CLKP  
CLKM  
CLOCKGEN  
CLKOUTP/M  
DB0_P/M  
DB2_P/M  
DB4_P/M  
Digital  
and  
DDR  
INB_P  
INB_M  
Sample  
and  
Hold  
12-Bit  
ADC  
DB6_P/M  
DB8_P/M  
DB10_P/M  
Serializer  
VCM  
Reference  
Control Interface  
SDOUT  
ADS62P29/28  
B0350-01  
Figure 2. ADS62P29/28 Block Diagram  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
PACKAGE/ORDERING INFORMATION(1)  
SPECIFIED  
TEMPERATURE  
RANGE  
PACKAGE-  
LEAD  
PACKAGE  
DESIGNATOR  
ECO  
LEAD/BALL PACKAGE  
ORDERING  
NUMBER  
TRANSPORT  
MEDIA,QUANTITY  
PRODUCT  
PLAN(2)  
FINISH  
MARKING  
AZ62P49  
AZ62P48  
AZ62P29  
AZ62P28  
ADS62P49IRGCT,  
ADS62P49IRGCR  
ADS62P49  
ADS62P48  
ADS62P29  
ADS62P28  
Tape and Reel  
Tape and Reel  
ADS62P48IRGCT,  
ADS62P48IRGCR  
GREEN  
(RoHS and  
no Sb/Br)  
QFN-64  
RGC  
–40°C to 85°C  
Cu NiPdAu  
ADS62P29IRGCT,  
ADS62P29IRGCR  
ADS62P28IRGCT,  
ADS62P28IRGCR  
(1) For the most current product and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com. or  
(2) Eco Plan – The planned eco-friendly classification: Green (RoHS and no Sb/Br): TI defines “Green” to mean Pb-Free (RoHS compatible)  
and free of Bromine (Br) and Antimony (Sb) based flame retardants.  
ABSOLUTE MAXIMUM RATINGS(1)  
over operating free-air temperature range (unless otherwise noted)  
VALUE  
–0.3 V to 3.9  
UNIT  
V
Supply voltage range, AVDD  
Supply voltage range, DRVDD  
–0.3 V to 2.2  
V
Voltage between AGND and DRGND  
–0.3 to 0.3  
V
Voltage between AVDD to DRVDD (when AVDD leads DRVDD)  
Voltage between DRVDD to AVDD (when DRVDD leads AVDD)  
Voltage applied to external pin, VCM (in external reference mode)  
Voltage applied to analog input pins – INP_A, INM_A, INP_B, INM_B  
Voltage applied to input pins - CLKP, CLKM(2), RESET, SCLK, SDATA,  
SEN, CTRL1, CTRL2, CTRL3  
0 to 3.3  
V
–1.5 to 1.8  
V
–0.3 to 2.0  
V
–0.3V to minimum ( 3.6, AVDD + 0.3V )  
–0.3V to AVDD + 0.3V  
V
V
TA Operating free-air temperature range  
–40 to 85  
125  
°C  
°C  
°C  
kV  
TJ  
Operating junction temperature range  
Tstg Storage temperature range  
ESD, human body model  
–65 to 150  
2
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings  
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating  
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.  
(2) When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is < |0.3V|. This  
prevents the ESD protection diodes at the clock input pins from turning on.  
THERMAL CHARACTERISTICS(1)  
over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
(2)  
TEST CONDITIONS  
Soldered thermal pad, no airflow  
MIN  
TYP  
22  
MAX  
UNIT  
°C/W  
°C/W  
°C/W  
RθJA  
Soldered thermal pad, 200 LFM  
Bottom of package (thermal pad)  
15  
(3)  
RθJT  
0.57  
(1) With a JEDEC standard high-K board and 5x5 via array. See Exposed Pad in the Application Information.  
(2)  
(3)  
R
θJA is the thermal resistance from the junction to ambient.  
RθJT is the thermal resistance from the junction to the thermal pad.  
4
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
 
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
RECOMMENDED OPERATING CONDITIONS  
MIN  
TYP  
MAX UNIT  
SUPPLIES  
AVDD  
Analog supply voltage  
3.15  
1.7  
3.3  
1.8  
3.6  
1.9  
V
V
DRVDD Digital supply voltage  
ANALOG INPUTS  
Differential input voltage range  
2
1.5 ±0.1  
1.5±0.05  
500  
VPP  
V
Input common-mode voltage  
Voltage applied on CM in external reference mode  
Maximum analog input frequency with 2 Vpp input amplitude(1)  
Maximum analog input frequency with 1 Vpp input amplitude(1)  
V
MHz  
MHz  
800  
CLOCK INPUT  
Input clock sample rate  
Enable low speed mode(2)  
1
>100  
1
100  
250(3)  
100  
ADS62P49 / ADS62P29  
MSPS  
MSPS  
Low speed mode disabled (default mode after reset)  
Enable low speed mode  
ADS62P48 / ADS62P28  
Low speed mode disabled (default mode after reset)  
With multiplexed mode enabled(4)  
>100  
1
210  
65 MSPS  
Input clock amplitude differential (VCLKP–VCLKM  
)
Sine wave, ac-coupled  
LVPECL, ac-coupled  
0.2  
40%  
–40  
3
1.6  
VPP  
VPP  
VPP  
V
LVDS, ac-coupled  
0.7  
LVCMOS, single-ended, ac-coupled  
3.3  
Input clock duty cycle  
DIGITAL OUTPUTS  
50%  
60%  
CLOAD  
RLOAD  
TA  
Maximum external load capacitance from each output pin to DRGND  
Differential load resistance between the LVDS output pairs (LVDS mode)  
Operating free-air temperature  
5
pF  
Ω
100  
85  
°C  
(1) See the Theory of Operation section for information.  
(2) Use register bit <ENABLE LOW SPEED MODE>, refer to the Serial Register Map section for information.  
(3) With LVDS interface only; maximum recommended sample rate with CMOS interface is 210 MSPS.  
(4) See the Multiplexed Output Mode section for information.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
ELECTRICAL CHARACTERISTICS – ADS62P49/48 and ADS62P29/28  
Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8V, 50% clock duty cycle, –1dBFS differential analog input, internal  
reference mode (unless otherwise noted).  
Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.8V  
ADS62P49/ADS62P29  
250 MSPS  
ADS62P48/ADS62P28  
210 MSPS  
PARAMETER  
UNIT  
MIN  
TYP  
MAX  
MIN  
TYP  
MAX  
ANALOG INPUT  
Differential input voltage range (0 dB gain)  
Differential input resistance (at dc), See Figure 94  
Differential input capacitance, See Figure 95  
Analog input bandwidth (with 25Ω source impedance)  
Analog Input common mode current (per channel)  
Common mode output voltage  
2
> 1  
3.5  
700  
3.6  
1.5  
±4  
2
> 1  
3.5  
700  
3.6  
1.5  
±4  
Vpp  
MΩ  
pF  
MHz  
µA/MSPS  
V
VCM  
VCM  
Output current capability  
mA  
DC ACCURACY  
Offset error  
–20  
±2  
0.02  
0.5  
20  
–20  
±2  
0.02  
0.5  
20  
mV  
Temperature coefficient of offset error  
Variation of offset error with supply  
mV/ °C  
mV/V  
There are two sources of gain error – internal reference  
inaccuracy and channel gain error.  
EGREF  
Gain error due to internal reference inaccuracy alone  
Gain error of channel alone(1)  
–1  
–1  
±0.2  
±0.2  
1
1
–1  
–1  
±0.2  
±0.2  
1
1
% FS  
% FS  
EGCHAN  
Temperature coefficient of EGCHAN  
0.002  
0.002  
Δ% /°C  
Difference in gain errors between two channels  
within the same device  
–2  
–4  
2
4
–2  
–4  
2
4
Gain  
matching  
% FS  
(2)  
Difference in gain errors between two channels  
across two devices  
POWER SUPPLY  
IAVDD  
Analog supply current  
305  
133  
350  
175  
280  
122  
320  
165  
mA  
mA  
Output buffer supply current, LVDS interface with 100 Ω  
external termination  
IDRVDD  
Output buffer supply current, CMOS interface, Fin = 2MHz,  
No external load capacitance  
IDRVDD  
–
91  
mA  
(3)(4)  
Analog power  
1.01  
1.15  
0.92  
0.22  
45  
1.05  
0.3  
W
W
Digital power, LVDS interface  
Global power down  
0.24 0.315  
45 100  
100  
mW  
(1) This is specified by design and characterization; it is not tested in production.  
(2) For two channels within the same device, only the channel gain error matters, as the reference is common for both channels.  
(3) In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency and the  
supply voltage (see Figure 86 and CMOS interface power dissipation in application section).  
(4) The maximum DRVDD current with CMOS interface depends on the actual load capacitance on the digital output lines. Note that the  
maximum recommended load capacitance on each digital output line is 10 pF.  
6
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
 
 
 
 
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
ELECTRICAL CHARACTERISTICS – ADS62P49/48  
Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8V, 50% clock duty cycle, –1dBFS differential analog input, 0 dB gain,  
internal reference mode (unless otherwise noted).  
Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.8V  
ADS62P49  
250 MSPS  
ADS62P48  
210 MSPS  
PARAMETER  
TEST CONDITIONS  
Fin= 20 MHz  
UNIT  
MIN  
TYP  
73.4  
73  
MAX  
MIN  
TYP  
73.4  
73  
MAX  
Fin = 60 MHz  
Fin = 100 MHz  
SNR  
72  
72  
Signal to noise ratio,  
dBFS  
0 dB gain  
6 dB gain  
68  
71  
68  
71  
LVDS  
Fin = 170 MHz  
66.6  
69.8  
73.2  
72.7  
71.2  
69.8  
66.5  
69  
66.4  
69.7  
73  
Fin = 230 MHz  
Fin= 20 MHz  
Fin = 60 MHz  
Fin = 100 MHz  
72.8  
71.5  
70.1  
66.3  
68  
SINAD  
Signal to noise and distortion ratio,  
dBFS  
0 dB gain  
6 dB gain  
66.5  
66.5  
LVDS  
Fin = 170 MHz  
Fin = 230 MHz  
Fin = 170 MHz  
ENOB,  
11.3  
±0.6  
±2.5  
11.4  
±0.6  
±2.5  
LSB  
LSB  
LSB  
Effective number of bits  
DNL  
Fin = 170 MHz  
Fin = 170 MHz  
–0.95  
–5  
1.3 –0.95  
–5  
1.3  
5
Differential non-linearity  
INL  
5
Integrated non-linearity  
ELECTRICAL CHARACTERISTICS – ADS62P29/28  
Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8V, 50% clock duty cycle, –1dBFS differential analog input, 0 dB gain,  
internal reference mode (unless otherwise noted).  
Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.8V  
ADS62P29  
250 MSPS  
ADS62P28  
210 MSPS  
PARAMETER  
TEST CONDITIONS  
Fin= 20 MHz  
UNIT  
MIN  
TYP  
70.7  
70.5  
69.8  
69.4  
66  
MAX  
MIN  
TYP  
70.8  
70.6  
70  
MAX  
Fin = 60 MHz  
Fin = 100 MHz  
SNR  
Signal to noise ratio,  
dBFS  
0 dB gain  
6 dB gain  
66.5  
66.5  
69.4  
65.9  
68.4  
70.6  
70.5  
69.7  
68.7  
65.8  
67.1  
LVDS  
Fin = 170 MHz  
Fin = 230 MHz  
Fin= 20 MHz  
Fin = 60 MHz  
Fin = 100 MHz  
68.4  
70.6  
70.3  
69.3  
68.3  
65.9  
67.9  
SINAD  
Signal to noise and distortion ratio,  
dBFS  
0 dB gain  
6 dB gain  
66  
66  
LVDS  
Fin = 170 MHz  
Fin = 230 MHz  
Fin = 170 MHz  
ENOB,  
11  
±0.2  
±1  
11.1  
±0.2  
±1  
LSB  
LSB  
LSB  
Effective number of bits  
DNL  
–0.9  
–5  
1.3  
5
–0.9  
–5  
1.3  
5
Differential non-linearity  
INL  
Integrated non-linearity  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
7
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
 
 
 
 
 
 
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
ELECTRICAL CHARACTERISTICS – ADS62P49/48  
Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8V, 50% clock duty cycle, –1dBFS differential analog input, 0 dB gain,  
internal reference mode (unless otherwise noted).  
Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.8V  
ADS62P49/ADS62P29  
250 MSPS  
ADS62P48/ADS62P28  
210 MSPS  
PARAMETER  
TEST CONDITIONS  
Fin= 20 MHz  
UNIT  
MIN  
TYP  
89  
85  
78  
75  
77  
98  
95  
92  
90  
90  
93  
90  
90  
85  
85  
89  
85  
78  
75  
77  
87  
83.5  
77.5  
74  
75  
MAX  
MIN  
TYP  
85  
MAX  
Fin = 60 MHz  
Fin = 100 MHz  
Fin = 170 MHz  
Fin = 230 MHz  
Fin= 20 MHz  
85  
SFDR  
80  
dBc  
Spurious Free Dynamic Range  
71  
71  
77  
72  
98  
Fin = 60 MHz  
Fin = 100 MHz  
Fin = 170 MHz  
Fin = 230 MHz  
Fin= 20 MHz  
95  
SFDR  
Spurious Free Dynamic Range,  
excluding HD2,HD3  
92  
dBc  
dBc  
dBc  
dBc  
77  
71  
71  
70  
78  
71  
91  
90  
95  
Fin = 60 MHz  
Fin = 100 MHz  
Fin = 170 MHz  
Fin = 230 MHz  
Fin= 20 MHz  
94  
HD2  
90  
Second Harmonic Distortion  
88  
80  
85  
Fin = 60 MHz  
Fin = 100 MHz  
Fin = 170 MHz  
Fin = 230 MHz  
Fin= 20 MHz  
85  
HD3  
80  
Third Harmonic Distortion  
71  
77  
72  
83.5  
84.6  
79.7  
76.5  
71  
Fin = 60 MHz  
Fin = 100 MHz  
Fin = 170 MHz  
Fin = 230 MHz  
THD  
Total harmonic distortion  
70.5  
F1 = 46 MHz, F2 = 50 MHz,  
each tone at –7 dBFS  
87  
85  
90  
1
91  
84.5  
90  
IMD  
dBFS  
dB  
F1 = 185 MHz, F2 = 190  
MHz,  
each tone at –7 dBFS  
2-Tone Inter-modulation Distortion  
Up to 200-MHz cross-talk  
frequency  
Cross-talk  
Recovery to within 1% (of final  
value) for 6-dB overload with  
sine wave input  
Clock  
Cycles  
Input overload recovery  
1
PSRR  
For 100-mV pp signal on  
AVDD supply  
25  
25  
dB  
AC Power supply rejection ratio  
8
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
 
 
 
 
 
 
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
DIGITAL CHARACTERISTICS — ADS62Px9/x8  
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic  
level 0 or 1. AVDD = 3.3V, DRVDD = 1.8V  
ADS62P49/ADS62P48/  
ADS62P29/ADS62P28  
PARAMETER  
TEST CONDITIONS  
UNIT  
MIN  
TYP  
MAX  
DIGITAL INPUTS – CTRL1, CTRL2, CTRL3, RESET, SCLK, SDATA, SEN(1)  
High-level input voltage  
Low-level input voltage  
1.3  
V
V
All digital inputs support 1.8V and 3.3V  
CMOS logic levels.  
0.4  
SDATA, SCLK(2)  
SEN(3)  
16  
10  
0
High-level input current  
VHIGH = 3.3 V  
VLOW = 0 V  
µA  
SDATA, SCLK  
SEN  
Low-level input current  
Input capacitance  
µA  
–20  
4
pF  
DIGITAL OUTPUTS – CMOS INTERFACE (DA0-DA13, DB0-DB13, CLKOUT, SDOUT)  
High-level output voltage  
IOH = 1mA  
DRVDD  
–0.1  
DRVDD  
V
Low-level output voltage  
IOL = 1mA  
0
2
0.1  
V
Output capacitance (internal to device)  
DIGITAL OUTPUTS – LVDS INTERFACE  
VODH High-level output differential voltage  
VODL Low-level output differential voltage  
VOCM Output common-mode voltage  
pF  
With external 100 Ω termination.  
With external 100 Ω termination.  
275  
–425  
1
350  
–350  
1.15  
425  
–275  
1.4  
mV  
mV  
V
Capacitance inside the device from  
each output to ground  
Output Capacitance  
2
pF  
(1) SCLK, SDATA, SEN function as digital input pins in serial configuration mode.  
(2) SDATA, SCLK have internal 200 kΩ pull-down resistor  
(3) SEN has internal 100 kΩ pull-up resistor to AVDD. Since the pull-up is weak, SEN can also be driven by 1.8V or 3.3V CMOS buffers.  
DAnP/DBnP  
Dn_Dn+1_P  
Logic 0  
VODL = –350 mV(1)  
Logic 1  
VODH = 350 mV(1)  
Dn_Dn+1_M  
DAnM/DBnM  
VOCM  
V
GND  
GND  
T0334-02  
(1) With external 100-Ω termination  
Figure 3. LVDS Output Voltage Levels  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
9
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
TIMING REQUIREMENTS – LVDS AND CMOS MODES(1)  
Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 250 MSPS, sine wave input clock, 1.5 Vpp  
clock amplitude, CLOAD = 5pF(2) , RLOAD = 100Ω(3) , (unless otherwise noted).  
Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.7V to  
1.9V  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
1.2  
±50  
145  
1
MAX  
UNIT  
ns  
ta  
tj  
Aperture delay  
0.7  
1.7  
Aperture delay matching  
Aperture jitter  
Between two channels within the same device  
ps  
fs rms  
µs  
Time to valid data after coming out of STANDBY mode  
Time to valid data after coming out of global powerdown  
Time to valid data after stopping and restarting the input clock  
3
20  
50  
µs  
Wake-up time  
ADC latency(4)  
10  
Clock  
cycles  
Clock  
cycles  
22  
DDR LVDS MODE(5)  
tsu  
th  
Data setup time  
Data valid(6) to zero-crossing of CLKOUTP  
Zero-crossing of CLKOUTP to data becoming invalid(6)  
0.55  
0.55  
0.9  
ns  
ns  
Data hold time  
0.95  
tPDI  
Input clock falling edge cross-over to output clock rising edge  
cross-over  
100 MSPS ≤ Sampling frequency ≤ 250 MSPS  
Ts = 1/Sampling frequency  
tPDI = 0.69×Ts + tdelay  
Clock propagation delay  
tdelay  
4.2  
5.7  
7.2  
ns  
ps  
Difference in tdelay between two devices operating at same  
temperature and DRVDD supply voltage  
tdelay skew  
±500  
52%  
Duty cycle of differential clock, (CLKOUTP-CLKOUTM)  
100 MSPS ≤ Sampling frequency ≤ 250 MSPS  
LVDS bit clock duty cycle  
Rise time measured from –100mV to +100mV  
Fall time measured from +100mV to –100mV  
1MSPS ≤ Sampling frequency ≤ 250 MSPS  
tRISE  
tFALL  
,
Data rise time,  
Data fall time  
0.14  
ns  
Rise time measured from –100mV to +100mV  
Fall time measured from +100mV to –100mV  
1 MSPS ≤ Sampling frequency ≤ 250 MSPS  
tCLKRISE  
tCLKFALL  
,
Output clock rise time,  
Output clock fall time  
0.14  
100  
ns  
ns  
Output buffer enable to  
data delay  
tOE  
Time to valid data after output buffer becomes active  
PARALLEL CMOS MODE(7) at Fs = 210 MSPS  
tSTART  
tDV  
Input clock to data delay  
Data valid time  
Input clock falling edge cross-over to start of data valid(8)  
Time interval of valid data(8)  
2.5  
ns  
ns  
1.7  
2.7  
tPDI  
Input clock falling edge cross-over to output clock rising edge  
cross-over  
100 MSPS ≤ Sampling frequency ≤ 150 MSPS  
Ts = 1/Sampling frequency  
tPDI = 0.28 × Ts + tdelay  
Clock propagation delay  
Output clock duty cycle  
tdelay  
5.5  
7.0  
8.5  
ns  
Duty cycle of output clock, CLKOUT  
100 MSPS ≤ Sampling frequency ≤ 150 MSPS  
43%  
Rise time measured from 20% to 80% of DRVDD  
Fall time measured from 80% to 20% of DRVDD  
1 ≤ Sampling frequency ≤ 210 MSPS  
tRISE  
tFALL  
,
Data rise time,  
Data fall time  
1.2  
0.8  
ns  
ns  
Rise time measured from 20% to 80% of DRVDD  
Fall time measured from 80% to 20% of DRVDD  
1 ≤ Sampling frequency ≤ 150 MSPS  
tCLKRISE  
tCLKFALL  
,
Output clock rise time,  
Output clock fall time  
(1) Timing parameters are ensured by design and characterization and not tested in production  
(2) CLOAD is the effective external single-ended load capacitance between each output pin and ground  
(3) RLOAD is the differential load resistance between the LVDS output pair.  
(4) At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1.  
(5) Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load. Setup and hold  
time specifications take into account the effect of jitter on the output data and clock.  
(6) Data valid refers to LOGIC HIGH of +100.0mV and LOGIC LOW of –100.0mV.  
(7) For Fs> 150 MSPS, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT).  
(8) Data valid refers to LOGIC HIGH of 1.26V and LOGIC LOW of 0.54V.  
10  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
TIMING REQUIREMENTS – LVDS AND CMOS MODES (continued)  
Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 250 MSPS, sine wave input clock, 1.5 Vpp  
clock amplitude, CLOAD = 5pF , RLOAD = 100Ω , (unless otherwise noted).  
Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.7V to  
1.9V  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Output buffer enable (OE)  
to data delay  
tOE  
Time to valid data after output buffer becomes active  
100  
ns  
Table 1. LVDS Timings at Lower Sampling Frequencies  
Setup Time, ns  
Hold Time, ns  
Sampling Frequency, MSPS  
MIN  
0.75  
0.9  
TYP  
1.1  
MAX  
MIN  
0.75  
0.85  
1.1  
TYP  
1.15  
1.25  
1.5  
MAX  
210  
185  
153  
125  
1.25  
1.55  
2
1.15  
1.6  
1.45  
1.85  
< 100  
2
2
Enable LOW SPEED mode  
tPDI, ns  
TYP  
1 ≤ Fs ≤ 100  
Enable LOW SPEED mode  
MIN  
MAX  
12.6  
Table 2. CMOS Timings at Lower Sampling Frequencies  
Timings Specified With Respect to Input Clock  
Sampling Frequency, MSPS  
tSTART, ns  
TYP  
Data Valid time, ns  
MIN  
MAX  
2.5  
1.9  
0.9  
6
MIN  
1.7  
2
TYP  
2.7  
3
MAX  
210  
190  
170  
150  
2.7  
3.6  
3.7  
4.6  
Timings Specified With Respect to CLKOUT  
Sampling Frequency, MSPS  
Setup Time, ns  
Hold Time, ns  
MIN  
2.1  
2.8  
3.8  
5
TYP  
3.7  
4.4  
5.4  
MAX  
MIN  
0.35  
0.5  
TYP  
1.0  
1.2  
1.5  
MAX  
170  
150  
125  
0.8  
<100  
1.2  
Enable LOW SPEED mode  
tPDI, ns  
TYP  
9
1 ≤ Fs ≤ 100  
Enable LOW SPEED mode  
MIN  
MAX  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
11  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
N + 24  
N + 4  
N + 3  
N + 23  
N + 2  
Sample  
N
N + 1  
N + 22  
Input  
Signal  
ta  
CLKM  
CLKP  
Input  
Clock  
tPDI  
CLKOUTM  
CLKOUTP  
22 Clock Cycles  
DDR  
LVDS  
Output Data  
DXP, DXM  
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
E – Even Bits D0,D2,D4,...  
O – Odd Bits D1,D3,D5,...  
N – 22  
N – 21  
N – 20  
N – 19  
N – 1  
N
N + 1  
tPDI  
CLKOUT  
Parallel  
CMOS  
22 Clock Cycles  
Output Data  
D0–D13  
N – 22  
N – 21  
N – 20  
N – 19  
N – 18  
N – 1  
N
N + 1  
N + 2  
T0105-11  
Figure 4. Latency Diagram  
CLKP  
Input  
Clock  
CLKM  
tPDI  
CLKOUTM  
CLKOUTP  
Output  
Clock  
th  
tsu  
tsu  
th  
Dn(1)  
Dn+1(2)  
Output  
Data Pair  
DAnP/M  
DBnP/M  
T0106-08  
(1) Dn - Bits D0, D2, D4, ...  
(2) Dn + 1 - Bits d1, D3, D5, ...  
Figure 5. LVDS Interface Timing  
12  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
CLKP  
Input  
Clock  
CLKM  
tPDI  
Output  
CLKOUT  
Clock  
th  
tsu  
Output  
Data  
DAn, DBn  
Dn(1)  
CLKP  
CLKM  
Input  
Clock  
tSTART  
tDV  
Output  
Data  
DAn, DBn  
Dn(1)  
T0107-07  
(1) Dn - Bits D0, D1, D2, ... of Channel A and B  
Figure 6. CMOS Interface Timing  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
13  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
DEVICE CONFIGURATION  
ADS62Px9/x8 can be configured independently using either parallel interface control or serial interface  
programming.  
PARALLEL CONFIGURATION ONLY  
To put the device in parallel configuration mode, keep RESET tied to high (AVDD).  
Now, pins SEN, SCLK, CTRL1, CTRL2 and CTRL3 can be used to directly control certain modes of the ADC.  
The device can be easily configured by connecting the parallel pins to the correct voltage levels (as described in  
Table 3 to Table 6). There is no need to apply reset and SDATA pin can be connected to ground..  
In this mode, SEN and SCLK function as parallel interface control pins. Frequently used functions can be  
controlled in this mode – Power down modes, internal/external reference, selection between LVDS/CMOS  
interface and output data format.  
Table 3 has a brief description of the modes controlled by the four parallel pins.  
Table 3. Parallel Pin Definition  
PIN  
TYPE OF PIN  
CONTROLS MODES  
Coarse gain and internal/external  
reference  
SCLK  
Analog control pins (controlled by analog  
voltage levels, see Figure 8)  
LVDS/CMOS interface and output data  
format  
SEN  
CTRL1  
CTRL2  
CTRL3  
Digital control pins (controlled by digital logic Controls standby modes and MUX  
levels) mode.  
SERIAL INTERFACE CONFIGURATION ONLY  
To exercise this mode, first the serial registers have to be reset to their default values and RESET pin has to be  
kept low.  
SEN, SDATA and SCLK function as serial interface pins in this mode and can be used to access the internal  
registers of the ADC.  
The registers can be reset either by applying a pulse on RESET pin or by setting the <RESET> bit high. The  
serial interface section describes the register programming and register reset in more detail  
DETAILS OF PARALLEL CONFIGURATION ONLY  
The functions controlled by each parallel pin are described below. A simple way of configuring the parallel pins is  
shown in Figure 7.  
Table 4. SCLK CONTROL PIN  
VOLTAGE APPLIED ON SCLK  
DESCRIPTION  
0
Internal reference  
+200mV/-0mV  
(3/8)AVDD  
+/- 200mV  
External reference  
External reference  
Internal reference  
(5/8)2AVDD  
+/- 200mV  
AVDD  
+0mV/-200mV  
14  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
 
 
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
Table 5. SEN CONTROL PIN  
VOLTAGE APPLIED ON SEN  
DESCRIPTION  
0
Offset binary and DDR LVDS output  
+200mV/-0mV  
(3/8)AVDD  
+/- 200mV  
2’s complement format and DDR LVDS output  
2’s complement format and parallel CMOS output  
Offset binary and parallel CMOS output  
(5/8)AVDD  
+/- 200mV  
AVDD  
+0mV/-200mV  
Table 6. CTRL1, CTRL2 and CTRL3 PINS(1)  
CTRL1  
LOW  
LOW  
LOW  
LOW  
HIGH  
HIGH  
HIGH  
HIGH  
CTRL2  
LOW  
LOW  
HIGH  
HIGH  
LOW  
LOW  
HIGH  
HIGH  
CTRL3  
LOW  
HIGH  
LOW  
HIGH  
LOW  
HIGH  
LOW  
HIGH  
DESCRIPTION  
Normal operation  
Do not use, reserved for future  
Do not use, reserved for future  
Do not use, reserved for future  
Global power down  
Channel B standby  
Channel A standby  
MUX mode of operation, Channel A and B data is multiplexed and output on DA13 to DA0 pins.  
(1) See POWER DOWN in the APPLICATION INFORMATION section.  
AVDD  
(5/8) AVDD  
3R  
(5/8) AVDD  
GND  
AVDD  
2R  
(3/8) AVDD  
(3/8) AVDD  
3R  
To Parallel Pin  
GND  
S0321-01  
Figure 7. Simple Scheme to Configure Parallel Pins  
USING BOTH SERIAL INTERFACE AND PARALLEL CONTROLS  
For increased flexibility, a combination of serial interface registers and parallel pin controls (CTRL1 to CTRL3)  
can also be used to configure the device. To allow this, keep RESET low. The parallel interface control pins  
CTRL1 to CTRL3 are available. After power-up, the device is automatically configured as per the voltage settings  
on these pins (see Table 6). SEN, SDATA, and SCLK function as serial interface digital pins and are used to  
access the internal registers of ADC. The registers must first be reset to their default values either by applying a  
pulse on RESET pin or by setting bit <RST> = 1. After reset, the RESET pin must be kept low. The Serial  
Interface section describes register programming and register reset in more detail.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
15  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
 
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
SERIAL INTERFACE  
The ADC has a set of internal registers, which can be accessed by the serial interface formed by pins SEN  
(Serial interface Enable), SCLK (Serial Interface Clock) and SDATA (Serial Interface Data).  
Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge  
of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge  
when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be  
loaded in multiple of 16-bit words within a single active SEN pulse.  
The first 8 bits form the register address and the remaining 8 bits are the register data. The interface can work  
with SCLK frequency from 20 MHz down to very low speeds (few Hertz) and also with non-50% SCLK duty  
cycle.  
Register Initialization  
After power-up, the internal registers MUST be initialized to their default values. This can be done in one of two  
ways:  
1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10ns) as  
shown in Figure 8  
OR  
2. By applying software reset. Using the serial interface, set the <RESET> bit (D7 in register 0x00) to HIGH.  
This initializes internal registers to their default values and then self-resets the <RESET> bit to low. In this  
case the RESET pin is kept low.  
Register Address  
Register Data  
SDATA  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
D7  
D6  
D5  
D4  
D3  
D2  
t(DH)  
D1  
D0  
t(SCLK)  
t(DSU)  
SCLK  
t(SLOADH)  
t(SLOADS)  
SEN  
RESET  
T0109-01  
Figure 8. Serial Interface Timing  
16  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
 
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
SERIAL INTERFACE TIMING CHARACTERISTICS  
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V,  
DRVDD = 1.8V (unless otherwise noted).  
PARAMETER  
SCLK frequency (= 1/ tSCLK  
MIN  
> DC  
25  
TYP  
MAX  
UNIT  
MHz  
ns  
fSCLK  
tSLOADS  
tSLOADH  
tDS  
)
20  
SEN to SCLK setup time  
SCLK to SEN hold time  
SDATA setup time  
25  
ns  
25  
ns  
tDH  
SDATA hold time  
25  
ns  
Serial Register Readout  
The device includes an option where the contents of the internal registers can be read back. This may be useful  
as a diagnostic check to verify the serial interface communication between the external controller AND the ADC.  
a. First, set register bit <SERIAL READOUT> = 1. This also disables any further writes into the registers.  
b. Initiate a serial interface cycle specifying the address of the register (A7-A0) whose content has to be read.  
c. The device outputs the contents (D7-D0) of the selected register on the SDOUT pin (64).  
d. The external controller can latch the contents at the falling edge of SCLK.  
e. To enable register writes, reset register bit <SERIAL READOUT> = 0. SDOUT is a CMOS output pin; the readout functionality is  
available whether the ADC output data interface is LVDS or CMOS.  
When <SERIAL READOUT> is disabled, the SDOUT pin is forced low by the device (and not put in  
high-impedance). If serial readout is not used, the SDOUT pin has to be floated.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
17  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
A) Enable serial readout (<SERIAL READOUT> = 1)  
Register Address (A7:A0) = 0x00  
Register Data (D7:D0) = 0x01  
SDATA  
SCLK  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
SEN  
Pin SDOUT is NOT in high-impedance state; it is forced low by the device (<SERIAL READOUT> = 0)  
SDOUT  
B) Read contents of register 0x40. This register has been initialized with 0x0C (device is put in global power down mode)  
Register Address (A7:A0) = 0x40  
Register Data (D7:D0) = XX (Don't Care)  
SDATA  
SCLK  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
SEN  
0
0
0
0
1
1
0
0
SDOUT  
Pin SDOUT functions as serial readout (<SERIAL READOUT> = 1)  
T0386-02  
Figure 9. Serial Readout  
18  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
RESET TIMING (ONLY WHEN SERIAL INTERFACE IS USED)  
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C (unless otherwise  
noted).  
PARAMETER  
CONDITIONS  
MIN  
1
TYP  
MAX UNIT  
t1  
t2  
t3  
Power-on delay  
Delay from power-up of AVDD and DRVDD to RESET pulse active  
ms  
ns  
10  
Reset pulse width  
Pulse width of active RESET signal  
1(1)  
µs  
Register write delay  
Delay from RESET disable to SEN active  
100  
ns  
(1) The reset pulse is needed only when using the serial interface configuration. If the pulse width is greater than 1µsec, the device could  
enter the parallel configuration mode briefly and then return back to serial interface mode.  
Power Supply  
AVDD, DRVDD  
t1  
RESET  
t2  
t3  
SEN  
T0108-01  
NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset.  
For parallel interface operation, RESET has to be tied permanently HIGH.  
Figure 10. Reset Timing Diagram  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
19  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
SERIAL REGISTER MAP  
(1)  
Table 7. Summary of Functions Supported by Serial Interface  
REGISTER  
REGISTER FUNCTIONS  
ADDRESS  
A7–A0  
IN HEX  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
0
D0  
00  
<RESET>  
0
0
0
0
0
<SERIAL  
Software Reset  
READOUT>  
20  
0
0
0
0
0
<ENABLE  
LOW  
0
0
SPEED  
MODE>  
3F  
0
0
<REF>  
0
0
0
0
0
0
<STANDBY>  
0
0
Internal or external reference  
40  
41  
0
0
0
0
0
0
<POWER DOWN MODES>  
<LVDS CMOS>  
Output interface  
0
0
44  
50  
<CLKOUT EDGE CONTROL>  
0
0
0
0
<ENABLE INDIVIDUAL  
CHANNEL CONTROL>  
0
0
<DATA FORMAT>  
2s comp or offset binary  
51  
52  
53  
<CUSTOM PATTERN LOW>  
0
0
0
<CUSTOM PATTERN HIGH>  
<ENABLE OFFSET  
0
CORRECTION – CH A>  
55  
57  
<GAIN PROGRAMMABILITY – CH A>  
<OFFSET CORRECTION TIME  
CONSTANT – CH A>  
0 to 6 dB in 0.5 dB steps  
0
<FINE GAIN ADJUST – CH A>  
+0.001 dB to +0.134 dB, in 128 steps  
62  
63  
66  
0
0
0
0
0
0
0
0
<TEST PATTERNS – CH A>  
<OFFSET PEDESTAL – CH A>  
<ENABLE OFFSET  
0
0
0
0
0
0
CORRECTION – CH B>  
68  
6A  
<GAIN PROGRAMMABILITY – CH B>  
<OFFSET CORRECTION TIME  
CONSTANT – CH B>  
0 to 6 dB in 0.5 dB steps  
0
<FINE GAIN ADJUST – CH B>  
+0.001 dB to +0.134 dB, in 128 steps  
75  
76  
0
0
0
0
0
0
0
<TEST PATTERNS – CH B>  
<OFFSET PEDESTAL – CH B>  
(1) Multiple functions in a register can be programmed in a single write operation.  
20  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
DESCRIPTION OF SERIAL REGISTERS  
A7–A0 IN HEX  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
00  
<RESET>  
0
0
0
0
0
<SERIAL READOUT>  
Software Reset  
D7  
D0  
<RESET>  
1 Software reset applied – resets all internal registers and self-clears to 0.  
<SERIAL READOUT>  
0 Serial readout disabled. SDOUT is forced low by the device (and not put in high impedance state).  
1 Serial readout enabled, Pin SDOUT functions as serial data readout.  
A7–A0 IN HEX  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
20  
0
0
0
0
0
<ENABLE LOW SPEED MODE>  
0
0
D2  
<ENABLE LOW SPEED MODE>  
0
1
LOW SPEED mode disabled. Use for sampling frequency > 100 MSPS  
Enable LOW SPEED mode for sampling frequencies ≤ 100 MSPS.  
A7–A0 IN HEX  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
3F  
0
<REF>  
0
0
0
<STANDBY>  
0
D6-D5  
<REF> Internal or external reference selection  
01 Internal reference enabled  
11 External reference enabled  
<STANDBY>  
D1  
0
1
Normal operation  
Both ADC channels are put in standby. Internal references, output buffers are active. This results in  
quick wake-up time from standby.  
A7–A0 IN HEX  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
40  
0
0
0
0
POWER DOWN MODES  
D3-D0  
<POWER DOWN MODES>  
0000 Pins CTRL1, CTRL2, and CTRL3 determine power down modes.  
1000 Normal operation  
1001 Output buffer disabled for channel B  
1010 Output buffer disabled for channel A  
1011 Output buffer disabled for channel A and B  
1100 Global power down  
1101 Channel B standby  
1110 Channel A standby  
1111 Multiplexed mode, MUX- (only with CMOS interface)  
Channel A and B data is multiplexed and output on DA13 to DA0 pins.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
21  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
A7–A0 IN HEX  
41  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
<LVDS  
0
0
0
0
0
0
0
CMOS>  
D7  
<LVDS CMOS>  
0
1
Parallel CMOS interface  
DDR LVDS interface  
A7–A0 IN HEX  
44  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
<CLKOUT EDGE CONTROL>  
0
0
Output clock edge control  
LVDS interface  
D7-D5 <CLKOUT POSN> Output clock rising edge position  
000, 100 Default output clock position (refer to timing specification table)  
101  
110  
111  
Rising edge shifted by + (4/26)×Ts(1)  
Rising edge aligned with data transition  
Rising edge shifted by – (4/26)×Ts  
D4-D2  
<CLKOUT POSN> Output clock falling edge position  
000, 100 Default output clock position (refer to timing specification table)  
101  
110  
111  
Falling edge shifted by + (4/26)×Ts  
Falling edge shifted by – (6/26)×Ts  
Falling edge shifted by – (4/26)×Ts  
CMOS interface  
D7-D5  
<CLKOUT POSN> Output clock rising edge position  
000, 100 Default output clock position (refer to timing specification table)  
101  
110  
111  
Rising edge shifted by + (4/26)×Ts  
Rising edge shifted by – (6/26)×Ts  
Rising edge shifted by – (4/26)×Ts  
D4-D2  
<CLKOUT POSN> Output clock falling edge position  
000, 100 Default output clock position (refer to timing specification table)  
101  
110  
111  
Falling edge shifted by + (4/26)×Ts  
Falling edge shifted by – (6/26)×Ts  
Falling edge shifted by – (4/26)×Ts  
(1)Ts = 1 / sampling frequency  
22  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
A7–A0 IN HEX  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
50  
0
<ENABLE INDEPENDENT  
CHANNEL CONTROL>  
0
0
0
<DATA FORMAT>  
2s complement or offset binary  
0
D6  
<ENABLE INDEPENDENT CHANNEL CONTROL>  
0
1
Common control – both channels use common control settings for test patterns, offset correction,  
fine gain, gain correction and SNR Boost functions. These settings can be specified in a single set of  
registers.  
Independent control – both channels can be programmed with independent control settings for test  
patterns, offset correction and SNR Boost functions. Separate registers are available for each  
channel.  
D2-D1  
<DATA FORMAT>  
10 2s complement  
11 Offset binary  
A7–A0 IN HEX  
D7  
D6  
D5  
D4  
<Custom Pattern Low>  
<Custom Pattern High>  
D3  
D2  
D1  
D0  
51  
52  
0
0
D7-D0  
D5-D0  
<CUSTOM PATTERN LOW>  
8 lower bits of custom pattern available at the output instead of ADC data.  
<CUSTOM PATTERN HIGH>  
6 upper bits of custom pattern available at the output instead of ADC data  
Use this mode along with “Test Patterns” (register 0x62).  
A7–A0 IN HEX  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
53  
0
<ENABLE OFFSET CORRECTION – Common/Ch A> Offset  
0
0
0
0
0
0
correction enable  
D6  
<ENABLE OFFSET CORRECTION – Common/Ch A>  
Offset correction enable control for both channels (with common control) or for channel A only (with  
independent control).  
0
1
Offset correction disabled  
Offset correction enabled  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
23  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
A7–A0 IN HEX  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
55  
<GAIN – Common/Ch A>  
<OFFSET CORR TIME CONSTANT – Common/Ch A>  
Offset correction time constant  
D7-D4  
<GAIN – Common/Ch A>  
Gain control for both channels (with common control) or for channel A only (with independent  
control).  
0000 0 dB gain, default after reset  
0001 0.5 dB gain  
0010 1.0 dB gain  
0011 1.5 dB gain  
0100 2.0 dB gain  
0101 2.5 dB gain  
0110 3.0 dB gain  
0111 3.5 dB gain  
1000 4.0 dB gain  
1001 4.5 dB gain  
1010 5.0 dB gain  
1011 5.5 dB gain  
1100 6.0 dB gain  
D3-D0  
<OFFSET CORR TIME CONSTANT – Common/Ch A>  
Correction loop time constant in number of clock cycles.  
Applies to both channels (with common control) or for channel A only (with independent control).  
0000 256 k  
0001 512 k  
0010 1 M  
0011 2 M  
0100 4 M  
0101 8 M  
0110 16 M  
0111 32 M  
1000 64 M  
1001 128 M  
1010 256 M  
1011 512 M  
24  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
A7–A0 IN HEX  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
57  
0
<FINE GAIN ADJUST – Common/Ch A>  
+0.001 dB to +0.134 dB, in 128 steps  
Using the FINE GAIN ADJUST register bits, the channel gain can be trimmed in fine steps. The trim is only  
additive, has 128 steps and a range of 0.134dB. The relation between the FINE GAIN ADJUST bits and the  
trimmed channel gain is:  
Δ Channel gain = 20*log10[1 + (FINE GAIN ADJUST/8192)]  
Note that the total device gain = ADC gain + Δ Channel gain. The ADC gain is determined by register bits  
<GAIN PROGRAMMABILITY>  
A7–A0 IN HEX  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
62  
0
0
0
0
0
<TEST PATTERNS>  
D2-D0 <TEST PATTERNS> Test Patterns to verify data capture.  
Applies to both channels (with common control) or for channel A only (with independent control).  
000 Normal operation  
001 Outputs all zeros  
010 Outputs all ones  
011 Outputs toggle pattern  
In ADS62P49/48, output data <D13:D0> alternates between 01010101010101 and 10101010101010  
every clock cycle.  
In ADS62P29/28, output data <D11:D0> alternates between 010101010101 and 101010101010 every  
clock cycle.  
100 Outputs digital ramp  
In ADS62P49/48, output data increments by one LSB (14-bit) every clock cycle from code 0 to code  
16383  
In ADS62P29/28, output data increments by one LSB (12-bit) every 4th clock cycle from code 0 to  
code 4095  
101 Outputs custom pattern (use registers 0x51, 0x52 for setting the custom pattern)  
110 Unused  
111 Unused  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
25  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
A7–A0 IN HEX  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
63  
0
0
<OFFSET PEDESTAL – Common/Ch A>  
D5-D0  
<OFFSET PEDESTAL – Common/Ch A>  
When the offset correction is enabled, the final converged value (after the offset is corrected) will  
be the ideal ADC mid-code value (=8192 for P49/48, = 2048 for P29/28). A pedestal can be  
added to the final converged value by programming these bits. So, the final converged value will  
be = ideal mid-code + PEDESTAL.  
See "Offset Correction" in application section.  
Applies to both channels (with common control) or for channel A only (with independent control).  
011111 PEDESTAL = 31 LSB  
011110 PEDESTAL = 30 LSB  
011101 PEDESTAL = 29 LSB  
….  
000000 PEDESTAL = 0  
….  
111111 PEDESTAL = –1 LSB  
111110 PEDESTAL = –2 LSB  
….  
100000 PEDESTAL = –32 LSB  
A7–A0 IN HEX  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
66  
0
<ENABLE OFFSET CORRECTION – CH B> Offset  
0
0
0
0
0
0
correction enable  
D6  
<ENABLE OFFSET CORRECTION – CH B>  
Offset correction enable control for channel B (only with independent control).  
offset correction disabled  
0
1
offset correction enabled  
26  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
A7–A0 IN HEX  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
68  
<GAIN – CH B>  
<OFFSET CORR TIME CONSTANT – CH B>  
Offset correction time constant  
D7-D4  
<GAIN – CH B> Gain programmability to 0.5 dB steps.  
Applies to channel B (only with independent control).  
0000 0 dB gain, default after reset  
0001 0.5 dB gain  
0010 1.0 dB gain  
0011 1.5 dB gain  
0100 2.0 dB gain  
0101 2.5 dB gain  
0110 3.0 dB gain  
0111 3.5 dB gain  
1000 4.0 dB gain  
1001 4.5 dB gain  
1010 5.0 dB gain  
1011 5.5 dB gain  
1100 6.0 dB gain  
D3-D0  
OFFSET CORR TIME CONSTANT – CH B> Time constant of correction loop in number of clock  
cycles.  
Applies to channel B (only with independent control)  
0000 256 k  
0001 512 k  
0010 1 M  
0011 2 M  
0100 4 M  
0101 8 M  
0110 16 M  
0111 32 M  
1000 64 M  
1001 128 M  
1010 256 M  
1011 512 M  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
27  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
A7–A0 IN HEX  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
6A  
<FINE GAIN ADJUST – CH B>  
+0.001 dB to +0.134 dB, in 128 steps  
Using the FINE GAIN ADJUST register bits, the channel gain can be trimmed in fine steps. The trim is only  
additive, has 128 steps and a range of 0.134dB. The relation between the FINE GAIN ADJUST bits and the  
trimmed channel gain is:  
Δ Channel gain = 20*log10[1 + (FINE GAIN ADJUST/8192)]  
Note that the total device gain = ADC gain + Δ Channel gain. The ADC gain is determined by register bits  
<GAIN PROGRAMMABILITY>  
A7–A0 IN HEX  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
75  
0
0
0
<TEST PATTERNS – CH B>  
D2-D0  
<TEST PATTERNS> Test Patterns to verify data capture.  
Applies to channel B (only with independent control)  
000 Normal operation  
001 Outputs all zeros  
010 Outputs all ones  
011 Outputs toggle pattern  
In ADS62P49/48, output data <D13:D0> alternates between 01010101010101 and  
10101010101010 every clock cycle.  
In ADS62P29/28, output data <D11:D0> alternates between 010101010101 and 101010101010  
every clock cycle.  
100 Outputs digital ramp  
In ADS62P49/48, output data increments by one LSB (14-bit) every clock cycle from code 0 to  
code 16383  
In ADS62P29/28, output data increments by one LSB (12-bit) every 4th clock cycle from code 0 to  
code 4095  
101 Outputs custom pattern (use registers 0x51, 0x52 for setting the custom pattern)  
110 Unused  
111 Unused  
28  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
A7–A0 IN HEX  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
76  
0
0
<OFFSET PEDESTAL – Common/CH B>  
D5-D0  
<OFFSET PEDESTAL – Common/CH B>  
When the offset correction is enabled, the final converged value (after the offset is corrected) will  
be the ideal ADC mid-code value (=8192 for P49/48, = 2048 for P29/28). A pedestal can be  
added to the final converged value by programming these bits. So, the final converged value will  
be = ideal mid-code + PEDESTAL. See "Offset Correction" in application section.  
Applies to channel B (only with independent control).  
011111 PEDESTAL = 31 LSB  
011110 PEDESTAL = 30 LSB  
011101 PEDESTAL = 29 LSB  
….  
000000 PEDESTAL = 0  
….  
111111 PEDESTAL = –1 LSB  
111110 PEDESTAL = –2 LSB  
….  
100000 PEDESTAL = –32 LSB  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
29  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
DEVICE INFORMATION  
PIN CONFIGURATION (LVDS MODE) – ADS62P49/P48  
RGC Package  
(Top View)  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
DRVDD  
DB4M  
DB4P  
DRVDD  
DA6P  
2
3
DA6M  
DA4P  
4
DB6M  
DB6P  
5
DA4M  
DA2P  
6
DB8M  
DB8P  
7
DA2M  
DA0P  
8
DB10M  
DB10P  
DB12M  
DB12P  
RESET  
SCLK  
Thermal Pad  
(Connected to DRGND)  
9
DA0M  
DRGND  
DRVDD  
CTRL3  
CTRL2  
CTRL1  
AVDD  
AVDD  
10  
11  
12  
13  
14  
15  
16  
SDATA  
SEN  
AVDD  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
P0056-14  
Figure 11.  
30  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
 
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
PIN CONFIGURATION (LVDS MODE) – ADS62P29/P28  
RGC Package  
(Top View)  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
DRVDD  
DB2M  
DB2P  
DB4M  
DB4P  
DB6M  
DB6P  
DB8M  
DB8P  
DB10M  
DB10P  
RESET  
SCLK  
SDATA  
SEN  
DRVDD  
DA4P  
DA4M  
DA2P  
DA2M  
DA0P  
DA0M  
NC  
2
3
4
5
6
7
8
Thermal Pad  
(Connected to DRGND)  
9
NC  
10  
11  
12  
13  
14  
15  
16  
DRGND  
DRVDD  
CTRL3  
CTRL2  
CTRL1  
AVDD  
AVDD  
AVDD  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
P0056-15  
Figure 12.  
PIN ASSIGNMENTS (LVDS MODE) – ADS62P49/P48 and ADS62P29/P28  
PIN  
NO. OF  
PINS  
I/O  
DESCRIPTION  
NAME  
NO.  
AVDD  
16, 33, 34  
3
I
I
Analog power supply  
Analog ground  
17, 18, 21, 24,  
27, 28, 31, I32  
AGND  
8
CLKP, CLKM  
INP_A, INM_A  
INP_B, INM_B  
VCM  
25, 26  
29, 30  
19, 20  
23  
2
2
2
1
I
I
I
Differential clock input  
Differential analog input, Channel A  
Differential analog input, Channel B  
IO Internal reference mode – Common-mode voltage output.  
External reference mode – Reference input. The voltage forced on this pin sets the  
internal references.  
RESET  
12  
1
I
Serial interface RESET input.  
When using the serial interface mode, the user must initialize internal registers through  
hardware RESET by applying a high-going pulse on this pin or by using software reset  
option. Refer to Serial Interface section.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
31  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
 
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
PIN ASSIGNMENTS (LVDS MODE) – ADS62P49/P48 and ADS62P29/P28 (continued)  
PIN  
NO. OF  
PINS  
I/O  
DESCRIPTION  
NAME  
NO.  
In parallel interface mode, the user has to tie RESET pin permanently high. (SCLK and  
SEN are used as parallel control pins in this mode)  
The pin has an internal 100 kΩ pull-down resistor.  
SCLK  
13  
1
I
This pin functions as serial interface clock input when RESET is low.  
It controls selection of internal or external reference when RESET is tied high. See  
Table 4 for detailed information.  
The pin has an internal 100 kΩ pull-down resistor.  
SDATA  
SEN  
14  
15  
1
1
I
I
Serial interface data input.  
The pin has an internal 100KΩ pull-down resistor.  
It has no function in parallel interface mode and can be tied to ground.  
This pin functions as serial interface enable input when RESET is low.  
It controls selection of data format and interface type when RESET is tied high. See  
Table 5 for detailed information.  
The pin has an internal 100 kΩ pull-up resistor to DRVDD  
This pin functions as serial interface register readout, when the <SERIAL READOUT> bit  
is enabled.  
SDOUT  
64  
1
O
When <SERIAL READOUT> = 0, this pin forces logic LOW and is not 3-stated.  
CTRL1  
35  
36  
37  
57  
56  
1
1
1
1
1
2
2
2
2
2
I
CTRL2  
I
Digital control input pins. Together, they control various power down modes.  
CTRL3  
I
CLKOUTP  
CLKOUTM  
DA0P, DA0M  
DA2P, DA2M  
DA4P, DA4M  
DA6P, DA6M  
DA8P, DA8M  
O
O
O
O
O
O
O
Differential output clock, true  
Differential output clock, complement  
Differential output data pair, D0 and D1 multiplexed – Channel A  
Differential output data D2 and D3 multiplexed, true – Channel A  
Differential output data D4 and D5 multiplexed, true – Channel A  
Differential output data D6 and D7 multiplexed, true – Channel A  
Differential output data D8 and D9 multiplexed, true – Channel A  
DA10P,  
DA10M  
2
2
O
O
Differential output data D10 and D11 multiplexed, true – Channel A  
Differential output data D12 and D13 multiplexed, true – Channel A  
DA12P,  
DA12M  
Refer to  
Figure 11 and  
Figure 12  
DB0P, DB0M  
DB2P, DB2M  
DB4P, DB4M  
DB6P, DB6M  
DB8P, DB8M  
2
2
2
2
2
O
O
O
O
O
Differential output data pair, D0 and D1 multiplexed – Channel B  
Differential output data D2 and D3 multiplexed, true – Channel B  
Differential output data D4 and D5 multiplexed, true – Channel B  
Differential output data D6 and D7 multiplexed, true – Channel B  
Differential output data D8 and D9 multiplexed, true – Channel B  
DB10P,  
DB10M  
2
O
Differential output data D10 and D11 multiplexed, true – Channel B  
DB12P,  
DB12M  
2
4
4
O
I
Differential output data D12 and D13 multiplexed, true – Channel B  
Output buffer supply  
DRVDD  
1, 38, 48, 58  
39, 49, 59,  
PAD  
DRGND  
I
Output buffer ground  
Refer to  
Figure 11 and  
Figure 12  
NC  
Do not connect  
32  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
PIN CONFIGURATION (CMOS MODE) – ADS62P49/P48  
RGC Package  
(Top View)  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
DRVDD  
DB4  
DRVDD  
DA7  
2
3
DB5  
DA6  
4
DB6  
DA5  
5
DB7  
DA4  
6
DB8  
DA3  
7
DB9  
DA2  
8
DB10  
DB11  
DB12  
DB13  
RESET  
SCLK  
SDATA  
SEN  
DA1  
Thermal Pad  
(Connected to DRGND)  
9
DA0  
10  
11  
12  
13  
14  
15  
16  
DRGND  
DRVDD  
CTRL3  
CTRL2  
CTRL1  
AVDD  
AVDD  
AVDD  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
P0056-16  
Figure 13.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
33  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
 
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
PIN CONFIGURATION (CMOS MODE) – ADS62P29/P28  
RGC Package  
(Top View)  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
DRVDD  
DB2  
DRVDD  
DA5  
2
3
DB3  
DA4  
4
DB4  
DA3  
5
DB5  
DA2  
6
DB6  
DA1  
7
DB7  
DA0  
8
DB8  
NC  
Thermal Pad  
(Connected to DRGND)  
9
DB9  
NC  
10  
11  
12  
13  
14  
15  
16  
DB10  
DB11  
RESET  
SCLK  
SDATA  
SEN  
DRGND  
DRVDD  
CTRL3  
CTRL2  
CTRL1  
AVDD  
AVDD  
AVDD  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
P0056-17  
Figure 14.  
PIN ASSIGNMENTS (CMOS MODE) – ADS62P49/P48 and ADS62P29/P28  
PIN  
NO. OF  
PINS  
I/O  
DESCRIPTION  
NAME  
NO.  
AVDD  
16, 33, 34  
3
I
I
Analog power supply  
Analog ground  
17, 18, 21, 24,  
27, 28, 31, I32  
AGND  
8
CLKP, CLKM  
INP_A, INM_A  
INP_B, INM_B  
VCM  
25, 26  
29, 30  
19, 20  
23  
2
2
2
1
I
I
I
Differential clock input  
Differential analog input, Channel A  
Differential analog input, Channel B  
IO Internal reference mode – Common-mode voltage output.  
External reference mode – Reference input. The voltage forced on this pin sets the  
internal references.  
RESET  
12  
1
I
Serial interface RESET input.  
When using the serial interface mode, the user MUST initialize internal registers through  
hardware RESET by applying a high-going pulse on this pin or by using software reset  
option. Refer to SERIAL INTERFACE section.  
34  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
 
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
PIN ASSIGNMENTS (CMOS MODE) – ADS62P49/P48 and ADS62P29/P28 (continued)  
PIN  
NO. OF  
PINS  
I/O  
DESCRIPTION  
NAME  
NO.  
In parallel interface mode, the user has to tie RESET pin permanently high. (SDATA and  
SEN are used as parallel control pins in this mode)  
The pin has an internal 100 kΩ pull-down resistor.  
SCLK  
13  
1
I
This pin functions as serial interface clock input when RESET is low.  
It controls selection of internal or external reference when RESET is tied high. See  
Table 4 for detailed information.  
The pin has an internal 100-kΩ pull-down resistor.  
SDATA  
SEN  
14  
15  
1
1
I
I
Serial interface data input.  
The pin has an internal 100-kΩ pull-down resistor.  
It has no function in parallel interface mode and can be tied to ground.  
This pin functions as serial interface enable input when RESET is low.  
It controls selection of data format and interface type when RESET is tied high. See  
Table 5 for detailed information.  
The pin has an internal 100 kΩ pull-up resistor to DRVDD  
This pin functions as serial interface register readout, when the <SERIAL READOUT> bit  
is enabled.  
SDOUT  
64  
1
O
When <SERIAL READOUT> = 0, this pin forces logic LOW and is not 3-stated.  
CTRL1  
CTRL2  
CTRL3  
CLKOUT  
35  
36  
1
1
1
1
I
I
Digital control input pins. Together, they control various power down modes.  
37  
I
5
O
CMOS output clock  
Refer to  
DA0-DA13  
Figure 13 and  
Figure 14  
14  
O
Channel A ADC output data bits, CMOS levels  
DB0-DB13  
DRVDD  
14  
4
O
I
Channel B ADC output data bits, CMOS levels  
Output buffer supply  
1, 38, 48, 58  
39, 49, 59,  
PAD  
DRGND  
4
I
Output buffer ground  
Refer to  
Figure 13 and  
Figure 14  
NC  
Do not connect  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
35  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
 
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
TYPICAL CHARACTERISTICS – ADS62P49  
All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP  
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain,  
LVDS output interface, 32K point FFT (unless otherwise noted)  
FFT FOR 20 MHz INPUT SIGNAL  
FFT FOR 170 MHz INPUT SIGNAL  
0
−20  
0
−20  
SFDR = 89.5 dBc  
SFDR = 75 dBc  
SINAD = 73.1 dBFS  
SNR = 73.2 dBFS  
THD = 88.1 dBc  
SINAD = 69.5 dBFS  
SNR = 70.7 dBFS  
THD = 74.5 dBc  
−40  
−40  
−60  
−60  
−80  
−80  
−100  
−120  
−140  
−100  
−120  
−140  
0
0
0
25  
50  
75  
100  
125  
0
0
0
25  
50  
75  
100  
125  
f − Frequency − MHz  
f − Frequency − MHz  
G001  
G002  
Figure 15.  
Figure 16.  
FFT FOR 300 MHz INPUT SIGNAL  
FFT FOR 2-TONE INPUT SIGNAL  
0
−20  
0
−20  
SFDR = 76.5 dBc  
SINAD = 67.6 dBFS  
SNR = 68.6 dBFS  
THD = 73.6 dBc  
f
f
1 = 185 MHz, –7 dBFS  
2 = 190 MHz, –7 dBFS  
2-Tone IMD = –85 dBFS  
SFDR = 90.2 dBc  
IN  
IN  
−40  
−40  
−60  
−60  
−80  
−80  
−100  
−120  
−140  
−100  
−120  
−140  
25  
50  
75  
100  
125  
25  
50  
75  
100  
125  
f − Frequency − MHz  
f − Frequency − MHz  
G003  
G004  
Figure 17.  
Figure 18.  
FFT FOR 2-TONE INPUT SIGNAL  
SFDR vs INPUT FREQUENCY  
0
−20  
92  
88  
84  
80  
76  
72  
68  
64  
f
f
1 = 185 MHz, –36 dBFS  
2 = 190 MHz, –36 dBFS  
2-Tone IMD = –100 dBFS  
SFDR = 96.6 dBc  
IN  
IN  
−40  
−60  
−80  
−100  
−120  
−140  
25  
50  
75  
100  
125  
50 100 150 200 250 300 350 400 450 500  
f − Frequency − MHz  
f
IN  
− Input Frequency − MHz  
G005  
G006  
Figure 19.  
Figure 20.  
36  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
TYPICAL CHARACTERISTICS – ADS62P49 (continued)  
All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP  
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain,  
LVDS output interface, 32K point FFT (unless otherwise noted)  
SNR vs INPUT FREQUENCY  
SFDR vs INPUT FREQUENCY ACROSS GAIN  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
92  
90  
88  
86  
84  
82  
80  
78  
76  
74  
72  
Input adjusted to get −1dBFS input  
4 dB  
2 dB  
6 dB  
5 dB  
0 dB  
3 dB  
1 dB  
0
50 100 150 200 250 300 350 400 450 500  
0
50 100 150 200 250 300 350 400 450 500  
f
IN  
− Input Frequency − MHz  
f
IN  
− Input Frequency − MHz  
G007  
G008  
Figure 21.  
Figure 22.  
SINAD vs INPUT FREQUENCY ACROSS GAIN  
PERFORMANCE vs INPUT AMPLITUDE, SINGLE TONE  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
120  
100  
80  
60  
40  
20  
0
81  
SFDR (dBFS)  
0 dB  
79  
1 dB  
2 dB  
3 dB  
77  
SNR (dBFS)  
75  
73  
4 dB  
5 dB  
71  
SFDR (dBc)  
6 dB  
f
IN  
= 60 MHz  
69  
0
50 100 150 200 250 300 350 400 450 500  
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10  
0
f
IN  
− Input Frequency − MHz  
Input Amplitude − dBFS  
G009  
G010  
Figure 23.  
Figure 24.  
PERFORMANCE vs COMMON-MODE INPUT VOLTAGE  
SFDR vs AVDD SUPPLY VOLTAGE  
88  
88  
86  
84  
82  
80  
78  
80  
f
IN  
= 60 MHz  
DRV = 1.8 V  
= 60 MHz  
DD  
87  
86  
85  
84  
83  
82  
81  
80  
79  
78  
AV = 3.2 V  
DD  
f
IN  
SFDR  
78  
76  
74  
72  
70  
AV = 3.15 V  
DD  
AV = 3.3 V  
DD  
SNR  
AV = 3.6 V  
DD  
AV = 3.4 V  
DD  
AV = 3.5 V  
DD  
−40  
−20  
0
20  
40  
60  
80  
1.35  
1.40  
1.45  
1.50  
1.55  
1.60  
1.65  
1.70  
T
A
− Free-Air Temperature − °C  
V
IC  
− Common-Mode Input Voltage − V  
G012  
G011  
Figure 25.  
Figure 26.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
37  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
TYPICAL CHARACTERISTICS – ADS62P49 (continued)  
All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP  
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain,  
LVDS output interface, 32K point FFT (unless otherwise noted)  
SNR vs AVDD SUPPLY VOLTAGE  
AV = 3.2 V  
PERFORMANCE vs DRVDD SUPPLY VOLTAGE  
72.50  
72.25  
72.00  
71.75  
71.50  
71.25  
71.00  
86  
85  
84  
83  
82  
81  
80  
79  
78  
78  
AV = 3.3 V  
DD  
DD  
77  
76  
75  
74  
73  
72  
71  
70  
f
= 60 MHz  
IN  
AV = 3.4 V  
DD  
AV = 3.15 V  
DD  
SFDR  
SNR  
AV = 3.3 V  
DD  
AV = 3.6 V  
DD  
DRV = 1.8 V  
DD  
f
IN  
= 60 MHz  
AV = 3.5 V  
DD  
1.70  
1.74  
1.78  
1.82  
1.86  
1.90  
−40  
−20  
0
20  
40  
60  
80  
T
A
− Free-Air Temperature − °C  
DRV − Supply Voltage − V  
DD  
G013  
G014  
Figure 27.  
Figure 28.  
PERFORMANCE vs INPUT CLOCK AMPLITUDE  
PERFORMANCE vs INPUT CLOCK DUTY CYCLE  
90  
88  
86  
84  
82  
80  
78  
76  
78  
92  
90  
88  
86  
84  
82  
80  
78  
76  
78  
f
IN  
= 20 MHz  
f
IN  
= 60 MHz  
77  
76  
75  
74  
73  
72  
71  
70  
77  
76  
75  
74  
73  
72  
71  
70  
SFDR  
SFDR  
SNR  
SNR  
74  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
30  
35  
40  
45  
50  
55  
60  
65  
Input Clock Amplitude − V  
Input Clock Duty Cycle − %  
PP  
G015  
G016  
Figure 29.  
Figure 30.  
PERFORMANCE IN EXTERNAL REFERENCE MODE  
86  
84  
82  
80  
78  
76  
80  
f
= 60 MHz  
IN  
External Reference Mode  
78  
76  
74  
72  
70  
SFDR  
SNR  
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70  
V
VCM  
− VCM Voltage − V  
G017  
Figure 31.  
38  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
TYPICAL CHARACTERISTICS – ADS62P48  
All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP  
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain,  
LVDS output interface, 32K point FFT (unless otherwise noted)  
FFT FOR 20 MHz INPUT SIGNAL  
FFT FOR 170 MHz INPUT SIGNAL  
0
−20  
0
−20  
SFDR = 84.1 dBc  
SFDR = 77.4 dBc  
SINAD = 70.1 dBFS  
SNR = 70.9 dBFS  
THD = 77 dBc  
SINAD = 73.1 dBFS  
SNR = 73.4 dBFS  
THD = 83.5 dBc  
−40  
−40  
−60  
−60  
−80  
−80  
−100  
−120  
−140  
−100  
−120  
−140  
0
0
0
20  
40  
60  
80  
100  
0
0
0
20  
40  
60  
80  
100  
f − Frequency − MHz  
f − Frequency − MHz  
G018  
G020  
G022  
G019  
Figure 32.  
Figure 33.  
FFT FOR 300 MHz INPUT SIGNAL  
FFT FOR 2-TONE INPUT SIGNAL  
0
−20  
0
−20  
SFDR = 70.1 dBc  
f
f
1 = 185 MHz, –7 dBFS  
2 = 190 MHz, –7 dBFS  
IN  
SINAD = 66 dBFS  
SNR = 68.8 dBFS  
THD = 68.2 dBc  
IN  
2-Tone IMD = –84.7 dBFS  
SFDR = –97.2 dBc  
−40  
−40  
−60  
−60  
−80  
−80  
−100  
−120  
−140  
−100  
−120  
−140  
20  
40  
60  
80  
100  
20  
40  
60  
80  
100  
f − Frequency − MHz  
f − Frequency − MHz  
G021  
Figure 34.  
Figure 35.  
FFT FOR 2-TONE INPUT SIGNAL  
SFDR vs INPUT FREQUENCY  
0
−20  
92  
88  
84  
80  
76  
72  
68  
f
f
1 = 185 MHz, –36 dBFS  
2 = 190 MHz, –36 dBFS  
IN  
IN  
2-Tone IMD = –107.1 dBFS  
SFDR = –98.8 dBc  
−40  
−60  
−80  
−100  
−120  
−140  
20  
40  
60  
80  
100  
50 100 150 200 250 300 350 400 450 500  
f − Frequency − MHz  
f
IN  
− Input Frequency − MHz  
G023  
Figure 36.  
Figure 37.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
39  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
TYPICAL CHARACTERISTICS – ADS62P48 (continued)  
All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP  
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain,  
LVDS output interface, 32K point FFT (unless otherwise noted)  
SNR vs INPUT FREQUENCY  
SFDR vs INPUT FREQUENCY ACROSS GAIN  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
96  
92  
88  
84  
80  
76  
72  
68  
Input adjusted to get −1dBFS input  
5 dB  
4 dB  
6 dB  
0 dB  
3 dB  
2 dB  
50 100 150 200 250 300 350 400 450 500  
1 dB  
0
50 100 150 200 250 300 350 400 450 500  
0
f
IN  
− Input Frequency − MHz  
f
IN  
− Input Frequency − MHz  
G024  
G025  
Figure 38.  
Figure 39.  
SINAD vs INPUT FREQUENCY ACROSS GAIN  
PERFORMANCE vs INPUT AMPLITUDE, SINGLE TONE  
76  
74  
72  
70  
68  
66  
64  
62  
120  
100  
80  
60  
40  
20  
0
81  
Input adjusted to get −1dBFS input  
0 dB  
SFDR (dBFS)  
79  
1 dB  
2 dB  
77  
SNR (dBFS)  
75  
73  
3 dB  
4 dB  
71  
SFDR (dBc)  
5 dB  
6 dB  
f
IN  
= 60 MHz  
69  
0
50 100 150 200 250 300 350 400 450 500  
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10  
0
f
IN  
− Input Frequency − MHz  
Input Amplitude − dBFS  
G026  
G027  
Figure 40.  
Figure 41.  
PERFORMANCE vs COMMON-MODE INPUT VOLTAGE  
SFDR vs AVDD SUPPLY VOLTAGE  
90  
88  
86  
84  
82  
80  
78  
80  
f
IN  
= 60 MHz  
DRV = 1.8 V  
DD  
89  
88  
87  
86  
85  
84  
83  
82  
81  
80  
f
IN  
= 20 MHz  
78  
76  
74  
72  
70  
SFDR  
AV = 3.6 V  
DD  
AV = 3.3 V  
DD  
SNR  
AV = 3.15 V  
DD  
1.35  
1.40  
1.45  
1.50  
1.55  
1.60  
1.65  
1.70  
−40  
−20  
0
20  
40  
60  
80  
T
A
− Free-Air Temperature − °C  
V
IC  
− Common-Mode Input Voltage − V  
G029  
G028  
Figure 42.  
Figure 43.  
40  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
TYPICAL CHARACTERISTICS – ADS62P48 (continued)  
All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP  
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain,  
LVDS output interface, 32K point FFT (unless otherwise noted)  
SNR vs AVDD SUPPLY VOLTAGE  
PERFORMANCE vs DRVDD SUPPLY VOLTAGE  
86  
85  
84  
83  
82  
81  
80  
79  
78  
78  
74.00  
73.75  
73.50  
73.25  
73.00  
72.75  
72.50  
AV = 3.3 V  
DD  
DRV = 1.8 V  
DD  
77  
f
= 20 MHz  
f
IN  
= 20 MHz  
IN  
AV = 3.3 V  
DD  
SFDR  
SNR  
76  
75  
74  
73  
72  
71  
70  
AV = 3.15 V  
DD  
AV = 3.6 V  
DD  
1.70  
1.74  
1.78  
1.82  
1.86  
1.90  
−40  
−20  
0
20  
40  
60  
80  
T
A
− Free-Air Temperature − °C  
DRV − Supply Voltage − V  
DD  
G030  
G031  
Figure 44.  
Figure 45.  
PERFORMANCE vs INPUT CLOCK AMPLITUDE  
PERFORMANCE vs INPUT CLOCK DUTY CYCLE  
90  
88  
86  
84  
82  
80  
78  
76  
78  
94  
92  
90  
88  
86  
84  
82  
80  
78  
78  
f
IN  
= 20 MHz  
f
IN  
= 60 MHz  
77  
76  
75  
74  
73  
72  
71  
70  
77  
76  
75  
74  
73  
72  
71  
70  
SFDR  
SNR  
SFDR  
SNR  
74  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
30  
35  
40  
45  
50  
55  
60  
65  
Input Clock Amplitude − V  
Input Clock Duty Cycle − %  
PP  
G032  
G033  
Figure 46.  
Figure 47.  
PERFORMANCE IN EXTERNAL REFERENCE MODE  
90  
88  
86  
84  
82  
80  
80  
f
= 60 MHz  
IN  
External Reference Mode  
78  
76  
74  
72  
70  
SFDR  
SNR  
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70  
V
VCM  
− VCM Voltage − V  
G034  
Figure 48.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
41  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
TYPICAL CHARACTERISTICS – ADS62P29  
All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP  
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain,  
LVDS output interface, 32K point FFT (unless otherwise noted)  
FFT FOR 20 MHz INPUT SIGNAL  
FFT FOR 170 MHz INPUT SIGNAL  
0
−20  
0
−20  
SFDR = 87.8 dBc  
SFDR = 74.8 dBc  
SINAD = 70.8 dBFS  
SNR = 70.9 dBFS  
THD = 84.9 dBc  
SINAD = 68.4 dBFS  
SNR = 69.3 dBFS  
THD = 74.6 dBc  
−40  
−40  
−60  
−60  
−80  
−80  
−100  
−120  
−140  
−100  
−120  
−140  
0
0
0
25  
50  
75  
100  
125  
0
0
0
25  
50  
75  
100  
125  
f − Frequency − MHz  
f − Frequency − MHz  
G035  
G036  
Figure 49.  
Figure 50.  
FFT FOR 300 MHz INPUT SIGNAL  
FFT FOR 2-TONE INPUT SIGNAL  
0
−20  
0
−20  
SFDR = 76.4 dBc  
SINAD = 66.7 dBFS  
SNR = 67.5 dBFS  
THD = 73.5 dBc  
f
f
1 = 185 MHz, –7 dBFS  
2 = 190 MHz, –7 dBFS  
2-Tone IMD = –85.3 dBFS  
SFDR = –90.4 dBc  
IN  
IN  
−40  
−40  
−60  
−60  
−80  
−80  
−100  
−120  
−140  
−100  
−120  
−140  
25  
50  
75  
100  
125  
25  
50  
75  
100  
125  
f − Frequency − MHz  
f − Frequency − MHz  
G037  
G038  
Figure 51.  
Figure 52.  
FFT FOR 2-TONE INPUT SIGNAL  
SFDR vs INPUT FREQUENCY  
0
−20  
92  
88  
84  
80  
76  
72  
68  
f
f
1 = 185 MHz, –36 dBFS  
2 = 190 MHz, –36 dBFS  
2-Tone IMD = –102.9 dBFS  
SFDR = –96.3 dBc  
IN  
IN  
−40  
−60  
−80  
−100  
−120  
−140  
25  
50  
75  
100  
125  
50 100 150 200 250 300 350 400 450 500  
f − Frequency − MHz  
f
IN  
− Input Frequency − MHz  
G039  
G040  
Figure 53.  
Figure 54.  
42  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
TYPICAL CHARACTERISTICS – ADS62P29 (continued)  
All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP  
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain,  
LVDS output interface, 32K point FFT (unless otherwise noted)  
SNR vs INPUT FREQUENCY  
SFDR vs INPUT FREQUENCY ACROSS GAIN  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
92  
90  
88  
86  
84  
82  
80  
78  
76  
74  
72  
Input adjusted to get −1dBFS input  
4 dB  
2 dB  
6 dB  
5 dB  
3 dB  
0 dB  
1 dB  
0
50 100 150 200 250 300 350 400 450 500  
0
50 100 150 200 250 300 350 400 450 500  
f
IN  
− Input Frequency − MHz  
f
IN  
− Input Frequency − MHz  
G041  
G042  
Figure 55.  
Figure 56.  
SINAD vs INPUT FREQUENCY ACROSS GAIN  
Input adjusted to get −1dBFS input  
1 dB  
PERFORMANCE vs INPUT AMPLITUDE, SINGLE TONE  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
120  
100  
80  
60  
40  
20  
0
85  
0 dB  
SFDR (dBFS)  
80  
2 dB  
75  
SNR (dBFS)  
3 dB  
70  
65  
SFDR (dBc)  
4 dB  
5 dB  
60  
6 dB  
f
IN  
= 60 MHz  
−10 0  
55  
0
50 100 150 200 250 300 350 400 450 500  
−70  
−60  
−50  
−40  
−30  
−20  
f
IN  
− Input Frequency − MHz  
Input Amplitude − dBFS  
G043  
G044  
Figure 57.  
Figure 58.  
PERFORMANCE vs COMMON-MODE INPUT VOLTAGE  
SFDR vs AVDD SUPPLY VOLTAGE  
88  
87  
86  
85  
84  
83  
82  
81  
80  
79  
78  
88  
86  
84  
82  
80  
78  
78  
f
IN  
= 60 MHz  
DRV = 1.8 V  
= 60 MHz  
DD  
AV = 3.2 V  
DD  
f
IN  
SFDR  
76  
74  
72  
70  
68  
AV = 3.15 V  
DD  
AV = 3.3 V  
DD  
SNR  
AV = 3.6 V  
DD  
AV = 3.4 V  
DD  
AV = 3.5 V  
DD  
1.35  
1.40  
1.45  
1.50  
1.55  
1.60  
1.65  
1.70  
−40  
−20  
0
20  
40  
60  
80  
T
A
− Free-Air Temperature − °C  
V
IC  
− Common-Mode Input Voltage − V  
G046  
G045  
Figure 59.  
Figure 60.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
43  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
TYPICAL CHARACTERISTICS – ADS62P29 (continued)  
All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP  
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain,  
LVDS output interface, 32K point FFT (unless otherwise noted)  
SNR vs AVDD SUPPLY VOLTAGE  
PERFORMANCE vs DRVDD SUPPLY VOLTAGE  
70.50  
70.25  
70.00  
69.75  
69.50  
69.25  
69.00  
86  
85  
84  
83  
82  
81  
80  
79  
78  
76  
AV = 3.3 V  
DD  
AV = 3.15 V  
DD  
75  
74  
73  
72  
71  
70  
69  
68  
f
= 60 MHz  
IN  
AV = 3.3 V  
DD  
AV = 3.2 V  
DD  
SFDR  
SNR  
AV = 3.6 V  
DD  
AV = 3.5 V  
DD  
DRV = 1.8 V  
= 60 MHz  
DD  
AV = 3.4 V  
DD  
f
IN  
1.70  
1.74  
1.78  
1.82  
1.86  
1.90  
−40  
−20  
0
20  
40  
60  
80  
T
A
− Free-Air Temperature − °C  
DRV − Supply Voltage − V  
DD  
G047  
G048  
Figure 61.  
Figure 62.  
PERFORMANCE vs INPUT CLOCK AMPLITUDE  
PERFORMANCE vs INPUT CLOCK DUTY CYCLE  
90  
88  
86  
84  
82  
80  
78  
76  
76  
92  
90  
88  
86  
84  
82  
80  
78  
76  
76  
f
IN  
= 20 MHz  
f
IN  
= 60 MHz  
75  
74  
73  
72  
71  
70  
69  
68  
75  
74  
73  
72  
71  
70  
69  
68  
SFDR  
SFDR  
SNR  
SNR  
74  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
30  
35  
40  
45  
50  
55  
60  
65  
Input Clock Amplitude − V  
Input Clock Duty Cycle − %  
PP  
G049  
G050  
Figure 63.  
Figure 64.  
PERFORMANCE IN EXTERNAL REFERENCE MODE  
86  
84  
82  
80  
78  
76  
78  
f
= 60 MHz  
IN  
External Reference Mode  
76  
74  
72  
70  
68  
SFDR  
SNR  
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70  
V
VCM  
− VCM Voltage − V  
G051  
Figure 65.  
44  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
TYPICAL CHARACTERISTICS – ADS62P28  
All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP  
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain,  
LVDS output interface, 32K point FFT (unless otherwise noted)  
FFT FOR 20 MHz INPUT SIGNAL  
FFT FOR 170 MHz INPUT SIGNAL  
0
−20  
0
−20  
SFDR = 84 dBc  
SFDR = 77.6 dBc  
SINAD = 68.7 dBFS  
SNR = 69.2 dBFS  
THD = 77.2 dBc  
SINAD = 70.6 dBFS  
SNR = 70.8 dBFS  
THD = 83.4 dBc  
−40  
−40  
−60  
−60  
−80  
−80  
−100  
−120  
−140  
−100  
−120  
−140  
0
0
0
20  
40  
60  
80  
100  
0
0
0
20  
40  
60  
80  
100  
f − Frequency − MHz  
f − Frequency − MHz  
G052  
G054  
G056  
G053  
Figure 66.  
Figure 67.  
FFT FOR 300 MHz INPUT SIGNAL  
FFT FOR 2-TONE INPUT SIGNAL  
0
−20  
0
−20  
SFDR = 70.1 dBc  
f
f
1 = 185 MHz, –7 dBFS  
2 = 190 MHz, –7 dBFS  
IN  
SINAD = 65.4 dBFS  
SNR = 67.8 dBFS  
THD = 68.2 dBc  
IN  
2-Tone IMD = –84.8 dBFS  
SFDR = 97.5 dBc  
−40  
−40  
−60  
−60  
−80  
−80  
−100  
−120  
−140  
−100  
−120  
−140  
20  
40  
60  
80  
100  
20  
40  
60  
80  
100  
f − Frequency − MHz  
f − Frequency − MHz  
G055  
Figure 68.  
Figure 69.  
FFT FOR 2-TONE INPUT SIGNAL  
SFDR vs INPUT FREQUENCY  
0
−20  
92  
88  
84  
80  
76  
72  
68  
f
f
1 = 185 MHz, –36 dBFS  
2 = 190 MHz, –36 dBFS  
IN  
IN  
2-Tone IMD = –106.3 dBFS  
SFDR = 98.4 dBc  
−40  
−60  
−80  
−100  
−120  
−140  
20  
40  
60  
80  
100  
50 100 150 200 250 300 350 400 450 500  
f − Frequency − MHz  
f
IN  
− Input Frequency − MHz  
G057  
Figure 70.  
Figure 71.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
45  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
TYPICAL CHARACTERISTICS – ADS62P28 (continued)  
All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP  
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain,  
LVDS output interface, 32K point FFT (unless otherwise noted)  
SNR vs INPUT FREQUENCY  
SFDR vs INPUT FREQUENCY ACROSS GAIN  
72  
71  
70  
69  
68  
67  
66  
65  
64  
96  
93  
90  
87  
84  
81  
78  
75  
72  
69  
66  
Input adjusted to get −1dBFS input  
5 dB  
4 dB  
6 dB  
2 dB  
0 dB  
1 dB  
3 dB  
0
50 100 150 200 250 300 350 400 450 500  
0
50 100 150 200 250 300 350 400 450 500  
f
IN  
− Input Frequency − MHz  
f
IN  
− Input Frequency − MHz  
G058  
G059  
Figure 72.  
Figure 73.  
SINAD vs INPUT FREQUENCY ACROSS GAIN  
PERFORMANCE vs INPUT AMPLITUDE, SINGLE TONE  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
120  
100  
80  
60  
40  
20  
0
85  
Input adjusted to get −1dBFS input  
0 dB  
SFDR (dBFS)  
1 dB  
80  
75  
70  
SNR (dBFS)  
SFDR (dBc)  
65  
60  
55  
2 dB  
3 dB  
5 dB  
6 dB  
4 dB  
f
IN  
= 60 MHz  
0
50 100 150 200 250 300 350 400 450 500  
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10  
0
f
IN  
− Input Frequency − MHz  
Input Amplitude − dBFS  
G060  
G061  
Figure 74.  
Figure 75.  
PERFORMANCE vs COMMON-MODE INPUT VOLTAGE  
SFDR vs AVDD SUPPLY VOLTAGE  
88  
86  
84  
82  
80  
78  
78  
90  
f
IN  
= 60 MHz  
DRV = 1.8 V  
DD  
89  
88  
87  
86  
85  
84  
83  
82  
81  
80  
f
IN  
= 20 MHz  
SFDR  
76  
74  
72  
70  
68  
AV = 3.6 V  
DD  
SNR  
AV = 3.3 V  
DD  
AV = 3.15 V  
DD  
1.35  
1.40  
1.45  
1.50  
1.55  
1.60  
1.65  
1.70  
−40  
−20  
0
20  
40  
60  
80  
T − Free-Air Temperature − °C  
A
V
IC  
− Common-Mode Input Voltage − V  
G063  
G062  
Figure 76.  
Figure 77.  
46  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
TYPICAL CHARACTERISTICS – ADS62P28 (continued)  
All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP  
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain,  
LVDS output interface, 32K point FFT (unless otherwise noted)  
SNR vs AVDD SUPPLY VOLTAGE  
AV = 3.3 V  
PERFORMANCE vs DRVDD SUPPLY VOLTAGE  
86  
85  
84  
83  
82  
81  
80  
79  
78  
78  
71.00  
70.75  
70.50  
70.25  
70.00  
AV = 3.3 V  
DD  
DD  
77  
76  
75  
74  
73  
72  
71  
70  
f
= 20 MHz  
IN  
SFDR  
AV = 3.15 V  
DD  
AV = 3.6 V  
DD  
SNR  
DRV = 1.8 V  
DD  
f
IN  
= 20 MHz  
1.70  
1.74  
1.78  
1.82  
1.86  
1.90  
−40  
−20  
T
0
20  
40  
60  
80  
− Free-Air Temperature − °C  
DRV − Supply Voltage − V  
DD  
A
G064  
G065  
Figure 78.  
Figure 79.  
PERFORMANCE vs INPUT CLOCK AMPLITUDE  
PERFORMANCE vs INPUT CLOCK DUTY CYCLE  
96  
94  
92  
90  
88  
86  
84  
82  
80  
76  
90  
88  
86  
84  
82  
80  
78  
76  
76  
f
IN  
= 20 MHz  
f
IN  
= 60 MHz  
75  
74  
73  
72  
71  
70  
69  
68  
75  
74  
73  
72  
71  
70  
69  
68  
SFDR  
SFDR  
SNR  
SNR  
74  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
30  
35  
40  
45  
50  
55  
60  
65  
Input Clock Amplitude − V  
Input Clock Duty Cycle − %  
PP  
G066  
G067  
Figure 80.  
Figure 81.  
PERFORMANCE IN EXTERNAL REFERENCE MODE  
90  
88  
86  
84  
82  
80  
78  
f
= 60 MHz  
IN  
External Reference Mode  
SFDR  
76  
74  
72  
70  
68  
SNR  
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70  
V
VCM  
− VCM Voltage − V  
G068  
Figure 82.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
47  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
TYPICAL CHARACTERISTICS – COMMON PLOTS  
All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP  
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain,  
LVDS output interface, 32K point FFT (unless otherwise noted)  
CROSSTALK vs FREQUENCY  
CMRR vs FREQUENCY  
−76  
−80  
−84  
−88  
−92  
−96  
−100  
−30  
−35  
−40  
−45  
−50  
−55  
−60  
−65  
−70  
Signal amplitude on aggressor channel at −0.3 dBFS  
0
50  
100  
150  
200  
250  
300  
20  
70  
120  
170  
220  
270  
f − Frequency − MHz  
f − Frequency − MHz  
G070  
G069  
Figure 83.  
Figure 84.  
POWER DISSIPATION vs SAMPLING FREQUENCY  
DRVDD CURRENT vs SAMPLING FREQUENCY  
= 2.5 MHz  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
140  
120  
100  
80  
f
IN  
= 2.5 MHz  
f
IN  
LVDS  
LVDS  
60  
CMOS  
CMOS, No Load  
CMOS, 15 pF Load  
40  
20  
0
25  
50  
75  
100 125 150 175 200 225 250  
− Sampling Frequency − MSPS  
25  
50  
75  
100 125 150 175 200 225 250  
f − Sampling Frequency − MSPS  
S
f
S
G072  
G073  
Figure 85.  
Figure 86.  
48  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
 
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
TYPICAL CHARACTERISTICS – ADS62P49/48/29/28  
All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP  
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain,  
LVDS output interface, 32K point FFT (unless otherwise noted)  
SFDR CONTOUR, 0 dB GAIN, UP TO 500 MHz  
250  
76  
240  
80  
76  
76  
76  
220  
200  
180  
160  
140  
120  
100  
80  
84  
80  
76  
76  
84  
72  
80  
76  
88  
76  
80  
76  
72  
84  
72  
76  
88  
80  
92  
76  
400  
20  
50  
100  
150  
200  
250  
300  
350  
450  
500  
fIN - Input Frequency - MHz  
80 85  
70  
75  
90  
95  
SFDR - dBc  
M0049-17  
Figure 87.  
SFDR CONTOUR, 6 dB GAIN, UP TO 800 MHz  
250  
240  
85  
75  
79  
82  
88  
67  
220  
200  
180  
160  
140  
120  
100  
80  
71  
63  
79  
85  
82  
85  
75  
67  
79  
71  
88  
63  
79  
88  
82  
82  
85  
88  
75  
79  
88  
79  
79  
67  
71  
700  
91  
20  
100  
200  
300  
400  
500  
600  
85  
800  
fIN - Input Frequency - MHz  
60  
65  
70  
75  
80  
90  
SFDR - dBc  
M0049-18  
Figure 88.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
49  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
TYPICAL CHARACTERISTICS – ADS62P49/48  
All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP  
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain,  
LVDS output interface, 32K point FFT (unless otherwise noted)  
SNR CONTOUR, 0 dB GAIN, UP TO 500 MHz  
250  
69  
66  
67  
240  
220  
200  
180  
160  
140  
120  
100  
80  
72  
70  
73  
71  
68  
65  
69  
70  
67  
66  
71  
72  
73  
68  
69  
70  
71  
66  
67  
72  
73  
65  
68  
74  
20  
50  
100  
150  
200  
250  
300  
350  
400  
450  
500  
fIN - Input Frequency - MHz  
64  
66  
68  
70  
72  
74  
SNR - dBFS  
M0048-26  
Figure 89.  
SNR CONTOUR, 6 dB GAIN, UP TO 800 MHz  
250  
240  
62.5  
63  
63.5  
61  
62  
67  
66.5  
65.5  
64  
66  
64.5  
220  
200  
180  
160  
140  
120  
100  
80  
65  
61.5  
63  
62.5  
64.5  
64  
63.5  
67  
62  
65.5  
66.5  
65  
66  
63.5  
64  
63  
62.5  
65.5  
64.5  
62  
61.5  
67  
68  
66  
65  
66.5  
20  
50  
100  
150  
200  
250  
300  
350  
400  
450  
68  
500  
69  
fIN - Input Frequency - MHz  
60  
61  
62  
63  
64  
65  
66  
67  
SNR - dBFS  
M0048-27  
Figure 90.  
50  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
TYPICAL CHARACTERISTICS – ADS62P29/28  
All plots are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP  
differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain,  
LVDS output interface, 32K point FFT (unless otherwise noted)  
SNR CONTOUR, 0 dB GAIN, UP TO 500 MHz  
250  
240  
66  
65  
65.5  
64  
66.5  
67  
69  
68  
220  
200  
180  
160  
140  
120  
100  
80  
64.5  
70  
66  
68  
65.5  
65  
67  
66.5  
69  
70  
71  
67  
65  
65.5  
66  
69  
66.5  
68  
71  
70  
100  
64.5  
20  
50  
150  
200  
250  
300  
350  
400  
450  
500  
fIN - Input Frequency - MHz  
64  
65  
66  
67  
68  
69  
70  
71  
72  
SNR - dBFS  
M0048-28  
Figure 91.  
SNR CONTOUR, 6 dB GAIN, UP TO 800 MHz  
250  
240  
66  
64.5  
66.5  
65.5  
64  
65  
62  
63.5  
63  
61  
62.5  
220  
200  
180  
160  
140  
120  
100  
80  
61.5  
65  
65.5  
66  
64.5  
66.5  
64  
63  
62.5  
63.5  
62  
61.5  
65  
64  
64.5  
66.5  
65.5  
66  
67.5  
62.5  
61.5  
63.5  
63  
350  
62  
20  
50  
100  
150  
200  
250  
300  
400  
450  
500  
fIN - Input Frequency - MHz  
60  
61  
62  
63  
64  
65  
66  
67  
68  
SNR - dBFS  
M0048-29  
Figure 92.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
51  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
APPLICATION INFORMATION  
THEORY OF OPERATION  
The ADS62Px9/x8 is a family of high performance and low power dual channel 14-bit/12-bit A/D converters with  
sampling rates up to 250 MSPS.  
At every falling edge of the input clock, the analog input signal of each channel is sampled simultaneously. The  
sampled signal in each channel is converted by a pipeline of low resolution stages. In each stage, the sampled  
and held signal is converted by a high speed, low resolution flash sub-ADC. The difference (residue) between the  
stage input and its quantized equivalent is gained and propagates to the next stage.  
At every clock, each succeeding stage resolves the sampled input with greater accuracy. The digital outputs from  
all stages are combined in a digital correction logic block and processed digitally to create the final code, after a  
data latency of 22 clock cycles.  
The digital output is available as either DDR LVDS or parallel CMOS and coded in either straight offset binary or  
binary 2s complement format.  
The dynamic offset of the first stage sub-ADC limits the maximum analog input frequency to about 500MHz (with  
2V pp amplitude) and about 800MHz (with 1V pp amplitude).  
ANALOG INPUT  
The analog input consists of a switched-capacitor based differential sample and hold architecture. This  
differential topology results in very good AC performance even for high input frequencies at high sampling rates.  
The INP and INM pins have to be externally biased around a common-mode voltage of 1.5V, available on VCM  
pin. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM + 0.5V  
and VCM – 0.5V, resulting in a 2Vpp differential input swing.  
The input sampling circuit has a high 3-dB bandwidth that extends up to 700 MHz (measured from the input pins  
to the sampled voltage).  
Sampling  
Switch  
Sampling  
Capacitor  
RCR Filter  
Lpkg » 1 nH  
10 W  
INP  
Ron  
15 W  
Csamp  
2 pF  
Cbond  
» 1 pF  
Cpar2  
0.5 pF  
100 W  
Resr  
200 W  
3 pF  
Cpar1  
0.25 pF  
Ron  
10 W  
3 pF  
100 W  
Csamp  
2 pF  
Ron  
15 W  
Lpkg » 1 nH  
10 W  
INM  
Sampling  
Capacitor  
Cbond  
» 1 pF  
Cpar2  
0.5 pF  
Resr  
200 W  
Sampling  
Switch  
S0322-03  
Figure 93. Analog Input Circuit  
52  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
Drive Circuit Requirements  
For optimum performance, the analog inputs must be driven differentially. This improves the common-mode  
noise immunity and even order harmonic rejection. A 5-Ω to 15-Ω resistor in series with each input pin is  
recommended to damp out ringing caused by package parasitic.  
SFDR performance can be limited due to several reasons - the effect of sampling glitches (described below),  
non-linearity of the sampling circuit and non-linearity of the quantizer that follows the sampling circuit. Depending  
on the input frequency, sample rate and input amplitude, one of these plays a dominant part in limiting  
performance.  
At very high input frequencies (> about 300 MHz), SFDR is determined largely by the device’s sampling circuit  
non-linearity. At low input amplitudes, the quantizer non-linearity usually limits performance.  
Glitches are caused by the opening and closing of the sampling switches. The driving circuit should present a  
low source impedance to absorb these glitches. Otherwise, this could limit performance, mainly at low input  
frequencies (up to about 200 MHz). It is also necessary to present low impedance (< 50 Ω) for the common  
mode switching currents. This can be achieved by using two resistors from each input terminated to the common  
mode voltage (VCM).  
The device includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the  
sampling glitches inside the device itself. The cut-off frequency of the R-C filter involves a trade-off. A lower  
cut-off frequency (larger C) absorbs glitches better, but it reduces the input bandwidth. On the other hand, with a  
higher cut-off frequency (smaller C), bandwidth support is maximized. But now, the sampling glitches need to be  
supplied by the external drive circuit. This has limitations due to the presence of the package bond-wire  
inductance.  
In ADS62PXX, the R-C component values have been optimized while supporting high input bandwidth (up to 700  
MHz). However, in applications with input frequencies up to 200-300MHz, the filtering of the glitches can be  
improved further using an external R-C-R filter (as shown in Figure 96 and Figure 97).  
In addition to the above, the drive circuit may have to be designed to provide a low insertion loss over the  
desired frequency range and matched impedance to the source. While doing this, the ADC input impedance  
must be considered. Figure 94 and Figure 95 show the impedance (Zin = Rin || Cin) looking into the ADC input  
pins.  
100  
10  
1
0.1  
0.01  
0
100 200 300 400 500 600 700 800 900 1000  
f − Frequency − MHz  
G074  
Figure 94. ADC Analog Input Resistance (Rin) Across Frequency  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
53  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
 
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0
100 200 300 400 500 600 700 800 900 1000  
f − Frequency − MHz  
G075  
Figure 95. ADC Analog Input Capacitance (Cin) Across Frequency  
Driving Circuit  
Two example driving circuit configurations are shown in Figure 96 and Figure 97 one optimized for low bandwidth  
(low input frequencies) and the other one for high bandwidth to support higher input frequencies.  
In Figure 96, an external R-C-R filter using 22 pF has been used. Together with the series inductor (39 nH), this  
combination forms a filter and absorbs the sampling glitches. Due to the large capacitor (22 pF) in the R-C-R and  
the 15-Ω resistors in series with each input pin, the drive circuit has low bandwidth and supports low input  
frequencies (< 100MHz).  
To support higher input frequencies (up to about 300 MHz, see Figure 97), the capacitance used in the R-C-R is  
reduced to 3.3 pF and the series inductors are shorted out. Together with the lower series resistors (5 Ω), this  
drive circuit provides high bandwidth and supports high input frequencies. Transformers such as ADT1-1WT or  
ETC1-1-13 can be used up to 300MHz.  
Without the external R-C-R filter, the drive circuit has very high bandwidth and can support very high input  
frequencies (> 300MHz). For example, a transmission line transformer such as ADTL2-18 can be used (see  
Figure 98).  
Note that both the drive circuits have been terminated by 50 Ω near the ADC side. The termination is  
accomplished by a 25-Ω resistor from each input to the 1.5-V common-mode (VCM) from the device. This allows  
the analog inputs to be biased around the required common-mode voltage.  
The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order  
harmonic performance. Connecting two identical RF transformers back to back helps minimize this mismatch and  
good performance is obtained for high frequency input signals. An additional termination resistor pair may be  
required between the two transformers as shown in the figures. The center point of this termination is connected  
to ground to improve the balance between the P and M side. The values of the terminations between the  
transformers and on the secondary side have to be chosen to get an effective 50 Ω (in the case of 50-Ω source  
impedance).  
54  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
39 nH  
0.1 mF  
0.1 mF  
15 W  
INP  
50 W  
25 W  
25 W  
50 W  
0.1 mF  
22 pF  
50 W  
50 W  
INM  
15 W  
0.1 mF  
1:1  
1:1  
VCM  
39 nH  
S0396-01  
Figure 96. Drive Circuit With Low Bandwidth (for low input frequencies)  
0.1 mF  
0.1 mF  
5 W  
INP  
25 W  
25 W  
50 W  
0.1 mF  
3.3 pF  
50 W  
INM  
5 W  
0.1 mF  
1:1  
1:1  
VCM  
S0397-01  
Figure 97. Drive Circuit With High Bandwidth (for high input frequencies)  
0.1mF  
INP  
25 W  
0.1mF  
25 W  
T1  
T2  
INM  
0.1mF  
VCM  
Figure 98. Drive Circuit with Very High Bandwidth (> 300 MHz)  
All these examples show 1:1 transformers being used with a 50-Ω source. As explained in the “Drive Circuit  
Requirements”, this helps to present a low source impedance to absorb the sampling glitches. With a 1:4  
transformer, the source impedance will be 200 ohms. The higher impedance can lead to degradation in  
performance, compared to the case with 1:1 transformers.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
55  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
For applications where only a band of frequencies are used, the drive circuit can be tuned to present a low  
impedance for the sampling glitches. Figure 99shows an example with 1:4 transformer, tuned for a band around  
150 MHz.  
5 W  
INP  
25 W  
100 W  
0.1mF  
Differential  
input signal  
72 nH  
15 pF  
100 W  
25 W  
INM  
5 W  
1:4  
VCM  
Figure 99. Drive Circuit with 1:4 Transformer  
Input Common-Mode  
To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1µF low-inductance capacitor  
connected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADC  
sinks a common-mode current in the order of 3.6µA / MSPS (about 900µA at 250 MSPS).  
REFERENCE  
The ADS62Px9/x8 has built-in internal references REFP and REFM, requiring no external components. Design  
schemes are used to linearize the converter load seen by the references; this and the on-chip integration of the  
requisite reference capacitors eliminates the need for external decoupling. The full-scale input range of the  
converter can be controlled in the external reference mode as explained below. The internal or external reference  
modes can be selected by programming the serial interface register bit <REF>.  
56  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
 
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
INTREF  
Internal  
Reference  
VCM  
INTREF  
EXTREF  
REFM  
REFP  
S0165-09  
Figure 100. Reference Section  
Internal Reference  
When the device is in internal reference mode, the REFP and REFM voltages are generated internally.  
Common-mode voltage (1.5V nominal) is output on VCM pin, which can be used to externally bias the analog  
input pins.  
External Reference  
When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on the  
VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential  
input voltage corresponding to full-scale is given by the following:  
Full-scale differential input pp = (Voltage forced on VCM) × 1.33  
In this mode, the 1.5V common-mode voltage to bias the input pins has to be generated externally.  
CLOCK INPUT  
The ADS62Px9/x8 clock inputs can be driven differentially (sine, LVPECL or LVDS) or single-ended (LVCMOS),  
with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to  
VCM using internal 5-kΩ resistors as shown in Figure 101. This allows using transformer-coupled drive circuits  
for sine wave clock or ac-coupling for LVPECL, LVDS clock sources (Figure 102 and Figure 103).  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
57  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
Clock Buffer  
Lpkg  
» 2 nH  
20 W  
CLKP  
Cbond  
» 1 pF  
Ceq  
Ceq  
5 kW  
5 kW  
Resr  
» 100 W  
VCM  
2 pF  
Lpkg  
» 2 nH  
20 W  
CLKM  
Cbond  
» 1 pF  
Resr  
» 100 W  
Ceq » 1 to 3 pF, Equivalent Input Capacitance of Clock Buffer  
S0275-04  
Figure 101. Internal Clock Buffer  
Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin 11) connected to ground with a  
0.1-µF capacitor, as shown in Figure 103.  
For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode  
noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass  
filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a  
non-50% duty cycle clock input.  
0.1 mF  
0.1 mF  
CMOS Clock Input  
CLKP  
CLKP  
Differential Sine-Wave  
or PECL or LVDS Clock Input  
VCM  
0.1 mF  
0.1 mF  
CLKM  
CLKM  
S0168-14  
S0167-10  
Figure 102. Differential Clock Driving Circuit  
Figure 103. Single-Ended Clock Driving Circuit  
58  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
 
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
GAIN PROGRAMMABILITY  
The ADS62Px9/x8 includes gain settings that can be used to get improved SFDR performance (compared to no  
gain). The gain is programmable from 0dB to 6dB (in 0.5 dB steps). For each gain setting, the analog input  
full-scale range scales proportionally, as shown in Table 8.  
The SFDR improvement is achieved at the expense of SNR; for each 1dB gain step, the SNR degrades about  
1dB. The SNR degradation is less at high input frequencies. As a result, the gain is very useful at high input  
frequencies as the SFDR improvement is significant with marginal degradation in SNR.  
So, the gain can be used to trade-off between SFDR and SNR. Note that the default gain after reset is 0dB.  
Table 8. Full-Scale Range Across Gains  
GAIN, dB  
TYPE  
FULL-SCALE, Vpp  
0
1
2
3
4
5
6
Default after reset  
2 V  
1.78  
1.59  
1.42  
1.26  
1.12  
1.00  
Fine, programmable  
OFFSET CORRECTION  
The ADS62Px9/x8 has an internal offset correction algorithm that estimates and corrects dc offset up to ±10mV.  
The correction can be enabled using the serial register bit <ENABLE OFFSET CORRECTION>. Once enabled,  
the algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the  
correction loop is a function of the sampling clock frequency. The time constant can be controlled using register  
bits <OFFSET CORR TIME CONSTANT> as described in Table 9.  
After the offset is estimated, the correction can be frozen by setting <ENABLE OFFSET CORRECTION> back to  
0.  
Once frozen, the last estimated value is used for offset correction every clock cycle. The correction does not  
affect the phase of the signal. Note that offset correction is disabled by default after reset.  
Figure 104 shows the time response of the offset correction algorithm, after it is enabled.  
Table 9. Time Constant of Offset Correction Algorithm  
<OFFSET CORR TIME  
TIME CONSTANT (TCCLK),  
NUMBER OF CLOCK CYCLES  
TIME CONSTANT, sec  
(=TCCLK × 1/Fs)  
CONSTANT>  
D3-D0  
(1)  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
256 k  
512 k  
1 ms  
2 ms  
1 M  
4 ms  
2 M  
8 ms  
4 M  
17 ms  
33 ms  
67 ms  
134 ms  
268 ms  
536 ms  
1.1 s  
8 M  
16 M  
32 M  
64 M  
128 M  
256 M  
512 M  
RESERVED  
RESERVED  
2.2 s  
(1) Sampling frequency, Fs = 250 MSPS  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
59  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
 
 
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
Table 9. Time Constant of Offset Correction Algorithm (continued)  
<OFFSET CORR TIME  
TIME CONSTANT (TCCLK),  
NUMBER OF CLOCK CYCLES  
TIME CONSTANT, sec  
(=TCCLK × 1/Fs)  
CONSTANT>  
D3-D0  
(1)  
1110  
1111  
RESERVED  
RESERVED  
8200  
Offset Correction Enabled  
8195  
8190  
8185  
8180  
8175  
8170  
8165  
8160  
8155  
Output Data With  
Offset Corrected  
Offset  
Correction  
Disabled  
Output Data  
With 34 LSB  
Offset  
−2  
0
2
4
6
8
10 12 14 16 18 20  
t − Time − ms  
G076  
Figure 104. Time Response of Offset Correction  
POWER DOWN  
The ADS62Px9/x8 has two power down modes – global power down and individual channel standby. These can  
be set using either the serial register bits or using the control pins CTRL1 to CTRL3.  
CONFIGURE USING  
WAKE-UP  
POWER DOWN MODES  
PARALLEL  
TIME  
SERIAL INTERFACE  
CONTROL PINS  
Normal operation  
<POWER DOWN MODES> = 0000  
<POWER DOWN MODES> = 1001  
<POWER DOWN MODES> = 1010  
<POWER DOWN MODES> = 1011  
<POWER DOWN MODES> = 1100  
<POWER DOWN MODES> = 1101  
<POWER DOWN MODES> = 1110  
low  
low  
low  
low  
–
Output buffer disabled for channel B  
Output buffer disabled for channel A  
Output buffer disabled for channel A and B  
Global power down  
low  
low  
high  
low  
–
high  
high  
low  
–
–
low  
high  
low  
high  
high  
high  
high  
Slow (30 µs)  
Fast (1 µs)  
Fast (1 µs)  
–
Channel B standby  
low  
high  
low  
Channel A standby  
high  
high  
Multiplexed (MUX) mode – Output data of channel A <POWER DOWN MODES> = 1111  
high  
and B is multiplexed and available on DA13 to DA0  
pins.  
Global Power Down  
In this mode, the entire chip including both the A/D converters, internal reference and the output buffers are  
powered down resulting in reduced total power dissipation of about 45 mW. The output buffers are in high  
impedance state. The wake-up time from the global power down to data becoming valid in normal mode is  
typically 30µs.  
Channel Standby  
Here, each channel’s A/D converter can be powered down. The internal references are active, resulting in quick  
wake-up time of 1 µs. The total power dissipation in standby is about 475 mW.  
60  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
Input Clock Stop  
In addition to the above, the converter enters a low-power mode when the input clock frequency falls below 1  
MSPS. The power dissipation is about 275 mW.  
POWER SUPPLY SEQUENCE  
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are  
separated in the device. Externally, they can be driven from separate supplies or from a single supply.  
DIGITAL OUTPUT INFORMATION  
The ADS62Px9/x8 provides 14-bit/12-bit data and an output clock synchronized with the data.  
Output Interface  
Two output interface options are available – Double Data Rate (DDR) LVDS and parallel CMOS. They can be  
selected using the serial interface register bit <LVDS_CMOS> or using DFS pin in parallel configuration mode.  
DDR LVDS Outputs  
In this mode, the data bits and clock are output using LVDS (Low Voltage Differential Signal) levels. Two data  
bits are multiplexed and output on each LVDS differential pair.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
61  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
Pins  
CLKOUTP  
Output Clock  
CLKOUTM  
DB0_P  
Data Bits D0, D1  
DB0_M  
DB2_P  
Data Bits D2, D3  
DB2_M  
DB4_P  
Data Bits D4, D5  
DB4_M  
DB6_P  
DB6_M  
14-Bit ADC Channel-B Data  
Data Bits D6, D7  
Data Bits D8, D9  
Data Bits D10, D11  
Data Bits D12, D13  
DB8_P  
DB8_M  
DB10_P  
DB10_M  
DB12_P  
DB12_M  
LVDS Buffers  
ADS62P4x  
S0398-01  
Figure 105. LVDS Outputs  
Even data bits D0, D2, D4… are output at the rising edge of CLKOUTP and the odd data bits D1, D3, D5… are  
output at the falling edge of CLKOUTP. Both the rising and falling edges of CLKOUTP have to be used to  
capture all the data bits (SEE Figure 106).  
62  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
CLKOUTM  
CLKOUTP  
DA0, DB0  
DA2, DB2  
D0  
D2  
D1  
D3  
D0  
D2  
D1  
D3  
DA4, DB4  
D4  
D5  
D4  
D5  
DA6, DB6  
D6  
D7  
D6  
D7  
DA8, DB8  
D8  
D9  
D8  
D9  
DA10, DB10  
DA12, DB12  
D10  
D12  
D11  
D13  
D10  
D12  
D11  
D13  
Sample N  
Sample N + 1  
T0110-05  
Figure 106. DDR LVDS Interface  
LVDS Buffer  
The equivalent circuit of each LVDS output buffer is shown in Figure 107. The buffer is designed to present an  
output impedance of 100 Ω (Rout). The differential outputs can be terminated at the receive end by a 100-Ω  
termination.  
The buffer output impedance behaves like a source-side series termination. By absorbing reflections from the  
receiver end, it helps to improve signal integrity. Note that this internal termination cannot be disabled and its  
value cannot be changed.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
63  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
ADS62C18  
+
0.35 V  
OUTP  
–
External  
100-W Load  
+
–
OUTM  
Rout  
+
–
1.2 V  
–0.35 V  
Switch impedance is  
nominally 50 W (±10%)  
When the High switches are closed, OUTP = 1.375 V, OUTM = 1.025 V  
When the Low switches are closed, OUTP = 1.025 V, OUTM = 1.375 V  
When the High (or Low) switches are closed, Rout = 100 W  
S0374-03  
Figure 107. LVDS Buffer Equivalent Circuit  
Parallel CMOS Interface  
In CMOS mode, each data bit is output on a separate pin as a CMOS voltage level, every clock cycle. This mode  
is recommended only up to 210 MSPS, beyond which the CMOS data outputs do not have sufficient time to  
settle to valid logic levels.  
For sampling frequencies up to 150 MSPS, the rising edge of the output clock CLKOUT can be used to latch  
data in the receiver. The setup and hold timings of the output data with respect to CLKOUT are specified in the  
timing specification table up to 150 MSPS.  
For sampling frequencies above 150 MSPS, it is recommended to use an external clock to capture data. The  
delay from input clock to output data and the data valid times are specified up to 210 MSPS. These timings can  
be used to delay the input clock appropriately and use it to capture the data.  
When using the CMOS interface, it is important to minimize the load capacitance seen by data and clock output  
pins by using short traces on the board.  
64  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
Pins  
DB0  
DB1  
DB2  
·
·
·
·
·
·
14-Bit ADC Channel-B Data  
DB11  
DB12  
DB13  
SDOUT  
CLKOUT  
DA0  
DA1  
DA2  
·
·
·
·
·
·
14-Bit ADC Channel-A Data  
DA11  
DA12  
DA13  
LVDS Buffers  
ADS62P49/48/29/28  
S0399-01  
Figure 108. CMOS Outputs  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
65  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
CMOS Interface Power Dissipation  
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every  
output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock  
cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined  
by the average number of output bits switching, which is a function of the sampling frequency and the nature of  
the analog input signal.  
Digital current due to CMOS output switching = CL × DRVDD × (N × FAVG),  
where  
CL = load capacitance,  
N × FAVG = average number of output bits switching.  
Figure 86 shows the current with various load capacitances across sampling frequencies at 2.5-MHz analog  
input frequency  
Multiplexed Output Mode (only with CMOS interface)  
In this mode, the digital outputs of both the channels are multiplexed and output on a single bus (DA0-DA13  
pins). The channel B output pins (DB0-DB13) are 3-stated. Since the output data rate on the DA bus is  
effectively doubled, this mode is recommended only for low sampling frequencies (<65MSPS).  
This mode can be enabled using register bits <POWER DOWN MODES> or using the parallel pins CTRL1-3.  
Output Data Format  
Two output data formats are supported – 2s complement and offset binary. They can be selected using the serial  
interface register bit <DATA FORMAT> or controlling the DFS pin in parallel configuration mode.  
In the event of an input voltage overdrive, the digital outputs go to the appropriate full scale level. For a positive  
overdrive, the output code is 0x3FFF in offset binary output format, and 0x1FFF in 2s complement output format.  
For a negative input overdrive, the output code is 0x0000 in offset binary output format and 0x2000 in 2s  
complement output format.  
BOARD DESIGN CONSIDERATIONS  
Grounding  
A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of  
the board are cleanly partitioned. See the EVM User Guide (SLAU237) for details on layout and grounding.  
Supply Decoupling  
As ADS62Px9/x8 already includes internal decoupling, minimal external decoupling can be used without loss in  
performance. Note that decoupling capacitors can help filter external power supply noise, so the optimum  
number of capacitors would depend on the actual application. The decoupling capacitors should be placed very  
close to the converter supply pins.  
Exposed Pad  
In addition to providing a path for heat dissipation, the pad is also electrically connected to digital ground  
internally. So, it is necessary to solder the exposed pad to the ground plane for best thermal and electrical  
performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and QFN/SON  
PCB Attachment (SLUA271).  
66  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
DEFINITION OF SPECIFICATIONS  
Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with  
respect to the low frequency value.  
Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at  
which the sampling occurs. This delay will be different across channels. The maximum variation is specified as  
aperture delay variation (channel-channel).  
Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.  
Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains  
at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a  
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.  
Maximum Conversion Rate – The maximum sampling rate at which certified operation is given. All parametric  
testing is performed at this sampling rate unless otherwise noted.  
Minimum Conversion Rate – The minimum sampling rate at which the ADC functions.  
Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly  
1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.  
Integral Nonlinearity (INL) – The INL is the deviation of the ADC's transfer function from a best fit line  
determined by a least squares curve fit of that transfer function, measured in units of LSBs.  
Gain Error – Gain error is the deviation of the ADC's actual input full-scale range from its ideal value. The gain  
error is given as a percentage of the ideal input full-scale range. Gain error has two components: error due to  
reference inaccuracy and error due to the channel. Both these errors are specified independently as EGREF and  
EGCHAN  
To a first order approximation, the total gain error will be ETOTAL ~ EGREF + EGCHAN  
For example, if ETOTAL = ±0.5%, the full-scale input varies from (1-0.5/100) x FSideal to (1 + 0.5/100) x FSideal  
.
.
.
Offset Error – The offset error is the difference, given in number of LSBs, between the ADC's actual average  
idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV.  
Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the  
change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation  
of the parameter across the TMIN to TMAX range by the difference TMAX–TMIN  
.
Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN),  
excluding the power at DC and the first nine harmonics.  
PS  
SNR = 10Log10  
PN  
(1)  
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the  
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s  
full-scale range.  
Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power  
of all the other spectral components including noise (PN) and distortion (PD), but excluding dc.  
PS  
SINAD = 10Log10  
PN + PD  
(2)  
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the  
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's  
full-scale range.  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
67  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
SLAS635A–APRIL 2009–REVISED JUNE 2009............................................................................................................................................................. www.ti.com  
Effective Number of Bits (ENOB) – The ENOB is a measure of the converter performance as compared to the  
theoretical limit based on quantization noise.  
SINAD - 1.76  
ENOB =  
6.02  
(3)  
Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the  
first nine harmonics (PD).  
PS  
THD = 10Log10  
PN  
(4)  
THD is typically given in units of dBc (dB to carrier).  
Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other  
spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).  
Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1  
and f2) to the power of the worst spectral component at either frequency 2f1–f2 or 2f2–f1. IMD3 is either given in  
units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to  
full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range.  
DC Power Supply Rejection Ratio (DC PSRR) – The DC PSSR is the ratio of the change in offset error to a  
change in analog supply voltage. The DC PSRR is typically given in units of mV/V.  
AC Power Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the  
supply voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVout is the resultant change of the  
ADC output code (referred to the input), then  
DVOUT  
PSRR = 20Log10  
(Expressed in dBc)  
DVSUP  
(5)  
Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an  
overload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive and  
negative overload. The deviation of the first few samples after the overload (from their expected values) is noted.  
Common Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input  
common-mode by the ADC. If ΔVcm_in is the change in the common-mode voltage of the input pins and ΔVOUT  
is the resultant change of the ADC output code (referred to the input), then  
DVOUT  
10  
CMRR = 20Log  
(Expressed in dBc)  
DVCM  
(6)  
Cross-Talk (only for multi-channel ADC)– This is a measure of the internal coupling of a signal from adjacent  
channel into the channel of interest. It is specified separately for coupling from the immediate neighboring  
channel (near-channel) and for coupling from channel across the package (far-channel). It is usually measured  
by applying a full-scale signal in the adjacent channel. Cross-talk is the ratio of the power of the coupling signal  
(as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel  
input. It is typically expressed in dBc.  
68  
Submit Documentation Feedback  
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
ADS62P49 / ADS62P29  
ADS62P48 / ADS62P28  
www.ti.com............................................................................................................................................................. SLAS635A–APRIL 2009–REVISED JUNE 2009  
REVISION HISTORY  
Changes from Original (April 2009) to Revision A .......................................................................................................... Page  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Changed ADS62P48, ADS62P29, ADS62P28 from product preview to production data .................................................... 4  
Added Analog supply current max value of 320 mA ............................................................................................................. 6  
Added Output buffer supply current, LVDS interface max value of 165 mA ......................................................................... 6  
Added Analog power max value of 1.05 W ........................................................................................................................... 6  
Added Digital power, LVDS interface max value of 0.3 W .................................................................................................... 6  
Added SNR Signal to noise ratio,LVDS, Fin = 170 MHz, 0 dB gain min value of 68 dBFS.................................................. 7  
Added SINADSignal to noise and distortion ratio, LVDS, Fin = 170 MHz, 0 dB gain min value of 66.5 dBFS..................... 7  
Added SNR Signal to noise ratio,LVDS, Fin = 170 MHz, 0 dB gain min value of 66.5 dBFS............................................... 7  
Added SNR Signal to noise ratio,LVDS, Fin = 170 MHz, 0 dB gain min value of 66.5 dBFS............................................... 7  
Added SINADSignal to noise and distortion ratio, LVDS, Fin = 170 MHz, 0 dB gain min value of 66 dBFS........................ 7  
Added SINADSignal to noise and distortion ratio, LVDS, Fin = 170 MHz, 0 dB gain min value of 66 dBFS........................ 7  
Added DNL Differential non-linearity min value of –0.9 LSB................................................................................................. 7  
Added DNL Differential non-linearity max value of 1.3 LSB.................................................................................................. 7  
Added DNL Differential non-linearity min value of –0.9 LSB................................................................................................. 7  
Added DNL Differential non-linearity max value of 1.3 LSB.................................................................................................. 7  
Added INL Integrated non-linearity min value of –5 LSB ...................................................................................................... 7  
Added INL Integrated non-linearity max value of 5 LSB ....................................................................................................... 7  
Added INL Integrated non-linearity min value of –5 LSB ...................................................................................................... 7  
Added INL Integrated non-linearity max value of 5 LSB ....................................................................................................... 7  
Added SFDR Spurious Free Dynamic Range, Fin = 170 MHz min value of 71 dBc ........................................................... 8  
Added SFDRSpurious Free Dynamic Range, excluding HD2,HD3, Fin = 170 MHz min value of 78 dBc............................ 8  
Added HD2 Second Harmonic Distortion, Fin = 170 MHz min value of 71 dBc.................................................................... 8  
Added HD3 Third Harmonic Distortion, Fin = 170 MHz min value of 71 dBc........................................................................ 8  
Added THDTotal harmonic distortion, Fin = 170 MHz min value of 70.5 dBc....................................................................... 8  
Added IMD2-Tone Inter-modulation Distortion, F1 = 46 MHz, F2 = 50 MHz, each tone at –7 dBFS typ value of 91 dBFS 8  
Changed DB0-DB13 number of pins from 2 to 14............................................................................................................... 35  
Copyright © 2009, Texas Instruments Incorporated  
Submit Documentation Feedback  
69  
Product Folder Link(s): ADS62P49 / ADS62P29 ADS62P48 / ADS62P28  
PACKAGE OPTION ADDENDUM  
www.ti.com  
25-Jun-2009  
PACKAGING INFORMATION  
Orderable Device  
ADS62P28IRGCR  
ADS62P28IRGCT  
ADS62P29IRGCR  
ADS62P29IRGCT  
ADS62P48IRGCR  
ADS62P48IRGCT  
ADS62P49IRGCR  
ADS62P49IRGCT  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
VQFN  
RGC  
64  
64  
64  
64  
64  
64  
64  
64  
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
VQFN  
VQFN  
VQFN  
VQFN  
VQFN  
VQFN  
VQFN  
RGC  
RGC  
RGC  
RGC  
RGC  
RGC  
RGC  
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
23-Jun-2009  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) W1 (mm)  
(mm) (mm) Quadrant  
ADS62P28IRGCR  
ADS62P28IRGCT  
ADS62P29IRGCR  
ADS62P29IRGCT  
ADS62P48IRGCR  
ADS62P48IRGCT  
ADS62P49IRGCR  
ADS62P49IRGCT  
VQFN  
VQFN  
VQFN  
VQFN  
VQFN  
VQFN  
VQFN  
VQFN  
RGC  
RGC  
RGC  
RGC  
RGC  
RGC  
RGC  
RGC  
64  
64  
64  
64  
64  
64  
64  
64  
2000  
250  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
16.4  
16.4  
16.4  
16.4  
16.4  
16.4  
16.4  
16.4  
9.3  
9.3  
9.3  
9.3  
9.3  
9.3  
9.3  
9.3  
9.3  
9.3  
9.3  
9.3  
9.3  
9.3  
9.3  
9.3  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
16.0  
16.0  
16.0  
16.0  
16.0  
16.0  
16.0  
16.0  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
2000  
250  
2000  
250  
2000  
250  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
23-Jun-2009  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
ADS62P28IRGCR  
ADS62P28IRGCT  
ADS62P29IRGCR  
ADS62P29IRGCT  
ADS62P48IRGCR  
ADS62P48IRGCT  
ADS62P49IRGCR  
ADS62P49IRGCT  
VQFN  
VQFN  
VQFN  
VQFN  
VQFN  
VQFN  
VQFN  
VQFN  
RGC  
RGC  
RGC  
RGC  
RGC  
RGC  
RGC  
RGC  
64  
64  
64  
64  
64  
64  
64  
64  
2000  
250  
333.2  
333.2  
333.2  
333.2  
333.2  
333.2  
333.2  
333.2  
345.9  
345.9  
345.9  
345.9  
345.9  
345.9  
345.9  
345.9  
28.6  
28.6  
28.6  
28.6  
28.6  
28.6  
28.6  
28.6  
2000  
250  
2000  
250  
2000  
250  
Pack Materials-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,  
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should  
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are  
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard  
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where  
mandated by government requirements, testing of all parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and  
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide  
adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,  
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information  
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a  
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual  
property of the third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied  
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive  
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional  
restrictions.  
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all  
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not  
responsible or liable for any such statements.  
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably  
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing  
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and  
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products  
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be  
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in  
such safety-critical applications.  
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are  
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military  
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at  
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.  
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are  
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated  
products in automotive applications, TI will not be responsible for any failure to meet such requirements.  
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:  
Products  
Amplifiers  
Applications  
Audio  
Automotive  
Broadband  
Digital Control  
Medical  
Military  
Optical Networking  
Security  
amplifier.ti.com  
dataconverter.ti.com  
www.dlp.com  
www.ti.com/audio  
Data Converters  
DLP® Products  
DSP  
Clocks and Timers  
Interface  
www.ti.com/automotive  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/medical  
www.ti.com/military  
www.ti.com/opticalnetwork  
www.ti.com/security  
www.ti.com/telephony  
www.ti.com/video  
dsp.ti.com  
www.ti.com/clocks  
interface.ti.com  
logic.ti.com  
power.ti.com  
microcontroller.ti.com  
www.ti-rfid.com  
Logic  
Power Mgmt  
Microcontrollers  
RFID  
Telephony  
Video & Imaging  
Wireless  
RF/IF and ZigBee® Solutions www.ti.com/lprf  
www.ti.com/wireless  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2009, Texas Instruments Incorporated  

相关型号：

ADS62P28IRGC25

 Dual Channel 14-/12-Bit, 250-/210-MSPS ADC With DDR LVDS and Parallel CMOS Outputs
TI

ADS62P28IRGCR

 Dual Channel 14-/12-Bit, 250-/210-MSPS ADC With DDR LVDS and Parallel CMOS Outputs
TI

ADS62P28IRGCT

 Dual Channel 14-/12-Bit, 250-/210-MSPS ADC With DDR LVDS and Parallel CMOS Outputs
TI

ADS62P29

 Dual Channel 14-/12-Bit, 250-/210-MSPS ADC With DDR LVDS and Parallel CMOS Outputs
TI

ADS62P29IRGC25

 Dual Channel 14-/12-Bit, 250-/210-MSPS ADC With DDR LVDS and Parallel CMOS Outputs
TI

ADS62P29IRGCR

 Dual Channel 14-/12-Bit, 250-/210-MSPS ADC With DDR LVDS and Parallel CMOS Outputs
TI

ADS62P29IRGCT

 Dual Channel 14-/12-Bit, 250-/210-MSPS ADC With DDR LVDS and Parallel CMOS Outputs
TI

ADS62P42

 Dual Channel 14-Bit, 125/105/80/65 MSPS ADC with Parallel CMOS/DDR LVDS outputs
TI

ADS62P42IRGCR

 Dual Channel 14-Bit, 125/105/80/65 MSPS ADC with Parallel CMOS/DDR LVDS outputs
TI

ADS62P42IRGCRG4

 DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
TI

ADS62P42IRGCT

 Dual Channel 14-Bit, 125/105/80/65 MSPS ADC with Parallel CMOS/DDR LVDS outputs
TI

ADS62P42IRGCTG4

 DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
TI
©2020 ICPDF网 联系我们和版权申明