ADS62P44IRGCRG4 [TI]
DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS; 双通道， 14位， 125/105/80/65 MSPS的DDR LVDS / CMOS输出的ADC
| 型号： | ADS62P44IRGCRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS |
| 文件： | 总70页 (文件大小：1787K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com
SLAS561A–JULY 2007–REVISED FEBRUARY 2008
DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
1
FEATURES
DESCRIPTION
•
•
•
•
•
Maximum Sample Rate: 125 MSPS
14-Bit Resolution with No Missing Codes
95 dB Crosstalk
ADS62P4X is a dual channel 14-bit A/D converter
family with maximum sample rates up to 125 MSPS.
It combines high performance and low power
consumption in a compact 64 QFN package. Using
an internal sample and hold and low jitter clock
buffer, the ADC supports high SNR and high SFDR at
high input frequencies. It has coarse and fine gain
options that can be used to improve SFDR
performance at lower full-scale input ranges.
Parallel CMOS and DDR LVDS Output Options
3.5 dB Coarse Gain and Programmable Fine
Gain up to 6 dB for SNR/SFDR Trade-Off
•
Digital Processing Block with:
–
–
–
–
Offset Correction
Fine Gain Correction, in Steps of 0.05 dB
Decimation by 2/4/8
ADS62P4X includes a digital processing block that
consists of several useful and commonly used digital
functions such as ADC offset correction, fine gain
correction (in steps of 0.05 dB), decimation by 2,4,8
and in-built and custom programmable filters. By
default, the digital processing block is bypassed, and
its functions are disabled.
Built-in and Custom Programmable 24-Tap
Low-/High-/Band-Pass Filters
•
Supports Sine, LVPECL, LVDS and LVCMOS
Clocks and Amplitude Down to 400 mVPP
•
•
Clock Duty Cycle Stabilizer
Two output interface options exist – parallel CMOS
and DDR LVDS (Double Data Rate). ADS62P4X
includes internal references while traditional
reference pins and associated decoupling capacitors
have been eliminated. Nevertheless, the device can
also be driven with an external reference. The device
is specified over the industrial temperature range
(–40°C to 85°C).
Internal Reference; Supports External
Reference also
•
•
64-QFN Package (9mm × 9mm)
Pin Compatible 12-Bit Family (ADS62P2X)
APPLICATIONS
•
•
•
•
•
•
•
Wireless Communications Infrastructure
Software Defined Radio
Power Amplifier Linearization
802.16d/e
Medical Imaging
Radar Systems
Test and Measurement Instrumentation
ADS62P4X Performance Summary
ADS62P45
88
ADS62P44
ADS62P43
93
ADS62P42
94
Fin = 10 MHz (0 dB gain)
Fin = 190 MHz (3.5 dB gain)
Fin = 10 MHz (0 dB gain)
Fin = 190 MHz (3.5 dB gain)
92
86
SFDR, dBc
84
87
85
73.7
70.8
799
74.2
71
74.6
71.3
594
74.7
70.9
515
SINAD, dBFS
Analog Power, mW
710
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated
ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com
SLAS561A–JULY 2007–REVISED FEBRUARY 2008
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Digital Processing
DA0
Block
DA1
DA2
Channel A
DA3
DA4
Output
Buffers
DA5
DA6
DA7
DA8
DA9
INA_P
INA_M
Digital
Encoder
SHA
14-Bit ADC
14 Bit
14 Bit
Channel A
DA10
DA11
DA12
DA13
Output Clock
Buffer
CLKP
CLKM
CLOCKGEN
CLKOUT
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
Output
Buffers
14 Bit
14 Bit
INB_P
INB_M
Digital
Encoder
SHA
14-Bit ADC
Channel B
Digital Processing
Block
Channel B
VCM
Reference
Control Interface
CMOS Interface
B0286-01
ADS62PXX FAMILY
125 MSPS
105 MSPS
80 MSPS
65 MSPS
ADS62P4X
14 Bits
ADS62P45
ADS62P25
ADS62P44
ADS62P24
ADS62P43
ADS62P42
ADS62P22
ADS62P2X
12 Bits
ADS62P23
2
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Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42
ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com
SLAS561A–JULY 2007–REVISED FEBRUARY 2008
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
PRODUCT
ADS62P45IRGCT
ADS62P45IRGCR
ADS62P44IRGCT
ADS62P44IRGCR
ADS62P43IRGCT
ADS62P43IRGCR
ADS62P42IRGCT
ADS62P42IRGCR
Tape and Reel, 250
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 2500
Tape and Reel, 250
Tape and Reel, 2500
ADS62P45
ADS62P44
ADS62P43
ADS62P42
QFN-64(2)
QFN-64(2)
QFN-64(2)
QFN-64(2)
RGC
RGC
RGC
RGC
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
AZ62P45
AZ62P44
AZ62P43
AZ62P42
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θJA = 23.17 °C/W (0 LFM air flow),
θJC = 22.1 °C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in × 3 in (7.62 cm ×
7.62 cm) PCB.
ABSOLUTE MAXIMUM RATINGS(1)
VALUE
–0.3 to 3.9
UNIT
V
Supply voltage range, AVDD
VI
Supply voltage range, DRVDD
–0.3 to 3.9
V
Voltage between AGND and DRGND
Voltage between AVDD to DRVDD
–0.3 to 0.3
V
–0.3 to 3.3
V
Voltage applied to VCM pin (in external reference mode)
Voltage applied to analog input pins, INP and INM
Voltage applied to analog input pins, CLKP and CLKM
Operating free-air temperature range
Operating junction temperature range
Storage temperature range
–0.3 to 2
V
–0.3 to minimum ( 3.6, AVDD + 0.3)
–0.3 to (AVDD + 0.3)
–40 to 85
V
V
TA
°C
°C
°C
TJ
125
Tstg
–65 to 150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Copyright © 2007–2008, Texas Instruments Incorporated
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SLAS561A–JULY 2007–REVISED FEBRUARY 2008
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage
3
3.3
3.6
V
CMOS interface
LVDS interface
1.65 1.8 to 3.3
3.6
3.6
V
V
(1)
DRVDD Output buffer supply voltage
3
3.3
ANALOG INPUTS
Differential input voltage range
Input common-mode voltage
2
1.5 ± 0.1
1.5
Vpp
V
VIC
Voltage applied on VCM in external reference mode
CLOCK INPUT
1.45
1.55
V
ADS62P45
1
1
125
105
80
ADS62P44
Input clock sample rate, FS
MSPS
ADS62P43
1
ADS62P42
1
65
Sine wave, ac-coupled
LVPECL, ac-coupled
LVDS, ac-coupled
LVCMOS, ac-coupled
0.4
1.5
± 0.8
± 0.35
3.3
Input clock amplitude differential
(VCLKP – VCLKM
Vpp
)
Input clock duty cycle
DIGITAL OUTPUTS
35%
50%
65%
DEFAULT
strength
for CLOAD ≤ 5 pF and DRVDD ≥ 2.2 V
for CLOAD > 5 pF and DRVDD ≥ 2.2 V
for DRVDD < 2.2 V
MAXIMUM
strength
(2)
Output buffer drive strength
MAXIMUM
strength
CMOS interface, maximum buffer
strength
10
Maximum external load capacitance from each LVDS interface, without internal
5
CLOAD
pF
output pin to DRGND
termination
LVDS interface, with internal
termination
10
RLOAD
TA
Differential load resistance (external) between the LVDS output pairs
Operating free-air temperature
100
Ω
-40
85
°C
(1) For easy migration to the next generation, higher sampling speed devices (> 125 MSPS), use 1.8V DRVDD supply.
(2) See Output Buffer Strength Programmability in application section.
4
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SLAS561A–JULY 2007–REVISED FEBRUARY 2008
ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, AVDD = 3.3 V, DRVDD = 1.8 v to 3.3 V, maximum rated sampling frequency, 50% clock duty
cycle, –1 dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise
noted.
Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 3.3 V,
unless otherwise noted.
ADS62P45
ADS62P44
ADS62P43
ADS62P42
FS = 125 MSPS
FS = 105 MSPS
FS = 80 MSPS
FS = 65 MSPS
PARAMETER
UNIT
MIN
TYP MAX
MIN
TYP MAX MIN TYP MAX MIN
TYP MAX
RESOLUTION
14
14
14
14
Bits
ANALOG INPUT
Differential input voltage range
2
2
2
2
VPP
Differential input resistance (dc)
see Figure 82
> 1
> 1
> 1
> 1
MΩ
Differential input capacitance
see Figure 83
7
450
1.3
7
450
1.3
7
450
1.3
7
450
1.3
pF
Analog input bandwidth
MHz
Analog input common mode current (per
input pin of each ADC)
µA/MSP
S
REFERENCE VOLTAGES
VREFB Internal reference bottom voltage
VREFT Internal reference top voltage
1
2
1
2
1
2
1
2
V
V
VCM
Common mode output voltage
VCM output current capability
1.5
4
1.5
4
1.5
4
1.5
4
V
mA
DC ACCURACY
No missing codes
Specified
± 2
Specified
± 2
Specified
Specified
EO
Offset error
-10
10
-10
10 -10 ± 2
10 -10
± 2
10
mV
Offset error temperature coefficient
0.05
0.05
0.05
0.05
mV/°C
There are two sources of gain error – internal reference inaccuracy and channel gain error
Gain error due to internal reference
EGREF
-2
0.25
2
-2
0.25
2
1
-2 0.25
-1 ±0.3
2
1
-2
-1
0.25
±0.3
2
1
% FS
% FS
Δ%/°C
inaccuracy alone
EGCHAN Gain error of channel alone(1)
across devices & across channels within a
device.
-1
±0.3
1
-1
±0.3
0.00
5
Channel gain error temperature coefficient
0.005
0.005
0.005
-
±
0.5
-
DNL
INL
Differential nonlinearity
Integral nonlinearity
-0.95 ± 0.6
-5 ± 2.5
-0.95 ± 0.6
-5 ± 2.5
± 0.5
± 2
LSB
LSB
0.95
0.95
5
5
-5 ± 2
5
-5
5
POWER SUPPLY
IAVDD
Analog supply current
240
17
275
215
14
240
180
12
200
156
10
175
mA
mA
No external load
capacitance
Digital supply current,
CMOS interface
IDRVDD
DRVDD = 1.8 V
10-pF external
load capacitance
(2)
30
26
22
19
mA
Fin = 2 MHz
Digital supply current, LVDS interface
with 100-Ω external termination
IDRVDD
PAVDD
73
799
31
73
710
25
73
594
22
73
515
18
mA
mW
mW
Analog power dissipation
908
75
792
75
660
75
578
75
No external load
capacitance
Digital power dissipation,
PDRVDD CMOS interface
(3)
10-pF external
load capacitance
DRVDD = 1.8 V
54
50
47
50
40
50
34
50
mW
mW
Global powerdown
(1) This is specified by design and characterization; it is not tested in production.
(2) In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency and the
supply voltage (see Figure 79 and CMOS power dissipation in application section).
(3) The maximum DRVDD current depends on the actual load capacitance on the digital output lines. Note that the maximum
recommended load capacitance on each digital output line is 10 pF.
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ADS62P43, ADS62P42
www.ti.com
SLAS561A–JULY 2007–REVISED FEBRUARY 2008
ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8 V to 3.3 V, maximum rated sampling frequency, 50% clock duty
cycle, –1 dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise
noted.
Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 3.3 V,
unless otherwise noted.
ADS62P45
ADS62P44
ADS62P43
ADS62P42
FS = 125 MSPS
FS = 105 MSPS
FS = 80 MSPS
FS = 65 MSPS
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP MAX
MIN
TYP MAX
MIN
TYP MAX
MIN
TYP MAX
DYNAMIC AC CHARACTERISTICS
Fin = 10 MHz
74.2
73.9
73.6
72.3
74.5
74.2
74
74.8
74.4
73.9
72.5
74.8
74.5
74.1
72.2
Fin = 50 MHz
70
71
SNR
Fin = 70 MHz
Signal to noise
70
71
dBFS
LSB
ratio
0 dB gain
72.3
Fin = 190
MHz
3.5 dB coarse
gain
71
71.2
1.0
71.6
1.0
70.8
1.0
RMS Output
Noise
Inputs tied to common-mode
1.0
Fin = 10 MHz
Fin = 50 MHz
73.7
73.3
73.2
71.4
74.2
73.5
73.5
71.8
74.6
74.2
73.8
72
74.7
74.3
73.9
71.5
69
70
SINAD
Signal to noise Fin = 70 MHz
and distortion
69
70
dBFS
0 dB gain
ratio
Fin = 190
MHz
3.5 dB coarse
gain
70.8
11.9
71
71.3
12
70.9
ENOB
Effective
Number of Bits
Fin = 50 MHz
Fin = 70 MHz
11.2
76
11.3
78
Bits
dBc
11.2 11.95
11.3
79
12
Fin = 10 MHz
Fin = 50 MHz
Fin = 70 MHz
88
80
86
81
92
83
93
87
89
83
94
87
89
81
SFDR
Spurious Free
Dynamic Range
78
75
78
78
85
83
0 dB gain
Fin = 190
MHz
3.5 dB coarse
gain
84
86
87
85
Fin = 10 MHz
Fin = 50 MHz
Fin = 70 MHz
88
79
90
82
84
80
92
86
88
80
93
86
88
79
73
76
76
76
78
78
THD
Total Harmonic
Distortion
84.5
79
76
79
79
dBc
dBc
0 dB gain
Fin = 190
MHz
3.5 dB coarse
gain
81
82
82
82
Fin = 10 MHz
Fin = 50 MHz
Fin = 70 MHz
94
92
92
86
93
93
93
86
95
94
94
85
98
97
96
86
HD2
Second
Harmonic
Distortion
0 dB gain
Fin = 190
MHz
3.5 dB coarse
gain
88
88
88
89
Fin = 10 MHz
Fin = 50 MHz
Fin = 70 MHz
88
80
86
81
92
83
85
83
93
87
89
83
94
87
89
81
HD3
Third Harmonic
Distortion
dBc
dBc
0 dB gain
Fin = 190
MHz
3.5 dB coarse
gain
84
86
87
85
Fin = 10 MHz
Fin = 50 MHz
Fin = 70 MHz
Fin = 190 MHz
95
94
94
90
96
95
95
93
97
96
96
95
99
98
97
92
Worst Spur
(Other than
HD2, HD3)
6
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SLAS561A–JULY 2007–REVISED FEBRUARY 2008
ELECTRICAL CHARACTERISTICS (continued)
Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8 V to 3.3 V, maximum rated sampling frequency, 50% clock duty
cycle, –1 dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise
noted.
Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 3.3 V,
unless otherwise noted.
ADS62P45
ADS62P44
ADS62P43
ADS62P42
FS = 125 MSPS
FS = 105 MSPS
FS = 80 MSPS
FS = 65 MSPS
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP MAX
MIN
TYP MAX
MIN
TYP MAX
MIN
TYP MAX
IMD
2-Tone
F1 = 185 MHz, F2 = 190 MHz
88
87
92
92
dBFS
dB
Intermodulation each tone at -7 dBFS
Distortion
Crosstalk
Up to 100 MHz
95
1
95
1
95
1
95
1
Recovery to within 1% (of final
value) for 6-dB overload with sine
wave input
Input Overload
Recovery
clock
cycles
PSRR
AC Power
Supply
for 100 mVpp signal on AVDD
supply
35
35
35
35
dBc
Rejection Ratio
DIGITAL CHARACTERISTICS(1)
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1, AVDD = 3.0 V to 3.6 V.
ADS62P45/ADS62P44
ADS62P43/ADS62P42
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DIGITAL INPUTS
RESET, CTRL1, CTRL2, CTRL3, SCLK, SDATA & SEN
(2)
High-level input voltage
2.4
V
Low-level input voltage
0.8
V
High-level input current
33
–33
4
µA
µA
pF
Low-level input current
Input capacitance
DIGITAL OUTPUTS
CMOS INTERFACE, DRVDD = 1.65 V to 3.6 V
High-level output voltage
Low-level output voltage
DRVDD
0
V
V
Output capacitance inside the device, from
each output to ground
Output capacitance
2
pF
DIGITAL OUTPUTS
LVDS INTERFACE, DRVDD = 3.0 V to 3.6 V, IO = 3.5 mA, RL = 100 Ω
(3)
High-level output voltage
1375
1025
350
mV
mV
mV
mV
Low-level output voltage
Output differential voltage, |VOD
|
225
VOS Output offset voltage, single-ended
Common-mode voltage of OUTP, OUTM
1200
Output capacitance inside the device, from
either output to ground
Output capacitance
2
pF
(1) All LVDS and CMOS specifications are characterized, but not tested at production.
(2) SCLK & SEN function as digital input pins when they are used for serial interface programming. When used as parallel control pins,
analog voltage needs to be applied as per Table 2 & Table 3
(3) IO refers to the LVDS buffer current setting, RL is the differential load resistance between the LVDS output pair.
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SLAS561A–JULY 2007–REVISED FEBRUARY 2008
TIMING CHARACTERISTICS – LVDS AND CMOS MODES(1)
Typical values are specified at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock,
1.5 VPP clock amplitude, CL = 5 pF(2), IO = 3.5 mA, RL = 100 Ω(3), no internal termination, unless otherwise noted.
Min and max values are specified across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.0 V to 3.6 V,
unless otherwise specified.
ADS62P45
ADS62P44
ADS62P43
ADS62P42
FS = 125 MSPS
FS = 105 MSPS
FS = 80 MSPS
FS = 65 MSPS
PARAMETER
TEST CONDITIONS
UNIT
MIN
0.7
TYP MAX
MIN
TYP MAX
MIN
TYP MAX
MIN
TYP MAX
Aperture
delay
ta
1.5
2.5
0.7
1.5
2.5
0.7
1.5
2.5
0.7
1.5
2.5
ns
ps
Aperture
delay
channel-to-channel
within the same device
±80
±80
±80
±80
variation
Aperture
jitter
tj
150
15
150
15
150
15
150
15
fs rms
from global power
down
50
50
50
50
µs
Wake-up
time
from standby
15
50
15
50
15
50
15
50
µs
(to valid
data)
from output
buffer
disable
CMOS
LVDS
100
200
100
200
100
200
100
200
ns
200
14
500
200
14
500
200
14
500
200
14
500
ns
clock
cycles
default, after reset
with low latency mode
enabled
clock
cycles
Latency
10
15
10
15
10
15
10
15
with decimation filter
enabled
clock
cycles
DDR LVDS MODE(4), DRVDD = 3.0 V to 3.6 V
Data valid (6) to
zero-cross of
CLKOUTP
Data setup
tsu
0.6
1.0
1.5
2.3
1.0
1.0
2.3
2.3
2.4
1.0
3.8
2.3
3.8
1.0
5.2
2.3
ns
ns
time(5)
Zero-cross of
Data hold
time(5)
th
CLKOUTP to data
becoming invalid(6)
Input clock rising edge
zero-cross to output
clock rising edge
zero-cross
Clock
propagation
delay
tPDI
3.5
5.5
7.5
3.5
5.5
7.5
3.5
5.5
7.5
3.5
5.5
7.5
ns
Duty cycle of
LVDS bit
clock duty
cycle
differential clock,
(CLKOUTP-
CLKOUTM)
46%
50%
53%
46%
50%
53%
46%
50%
53%
46%
50%
53%
10 ≤ Fs ≤ 125 MSPS
Rise time measured
from –50 mV to 50 mV
Fall time measured
from 50 mV to –50 mV
1 ≤ Fs ≤ 125 MSPS
Data rise
time
Data fall
time
tr
tf
70
70
100
100
170
170
70
70
100
100
170
170
70
70
100
100
5.8
170
170
70
70
100
100
7.2
170
170
ps
ps
ns
Rise time measured
from –50 mV to 50 mV
Fall time measured
from 50 mV to –50 mV
1 ≤ Fs ≤ 125 MSPS
tCLKRI Output clock
rise time
tCLKFA Output clock
SE
fall time
LL
(7)
PARALLEL CMOS MODE, DRVDD = 2.5 V to 3.6 V, default output buffer drive strength
Data setup
time(5)
Data valid(8) to 50% of
CLKOUT rising edge
tsu
2.0
3.5
2.8
4.3
4.3
5.7
(1) Timing parameters are specified by design and characterization and not tested in production.
(2) CL is the effective external single-ended load capacitance between each output pin and ground.
(3) IO refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair.
(4) Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and the load.
(5) Setup and hold time specifications take into account the effect of jitter on the output data and clock.
(6) Data valid refers to logic high of +100 mV and logic low of –100 mV.
(7) For DRVDD < 2.2 V, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT). See
Parallel CMOS interface in application section.
(8) Data valid refers to logic high of 2 V (1.7 V) and logic low of 0.8 V (0.7 V) for DRVDD = 3.3 V (2.5 V).
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SLAS561A–JULY 2007–REVISED FEBRUARY 2008
TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued)
Typical values are specified at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock,
1.5 VPP clock amplitude, CL = 5 pF, IO = 3.5 mA, RL = 100 Ω, no internal termination, unless otherwise noted.
Min and max values are specified across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.0 V to 3.6 V,
unless otherwise specified.
ADS62P45
ADS62P44
ADS62P43
ADS62P42
FS = 125 MSPS
FS = 105 MSPS
FS = 80 MSPS
FS = 65 MSPS
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP MAX
MIN
TYP MAX
MIN
TYP MAX
MIN
TYP MAX
50% of CLKOUT rising
edge to data becoming
invalid(8)
Data hold
time(5)
th
2.0
3.5
2.7
5.8
4.2
7.3
4.2
5.8
5.7
7.3
5.6
5.8
7.1
7.3
ns
ns
Clock
Input clock rising edge
propagation zero-cross to 50% of
tPDI
5.8
7.3
8.8
8.8
8.8
8.8
delay
CLKOUT rising edge
Duty cycle of output
clock (CLKOUT)
10 ≤ Fs ≤ 125 MSPS
Output clock
duty cycle
45%
53%
1.8
60%
45%
53%
60%
45%
53%
60%
45%
53%
60%
Rise time measured
from 20% to 80% of
DRVDD
Fall time measured
from 80% to 20% of
DRVDD
Data rise
time
Data fall
time
tr
tf
1.0
1.0
2.5
2.5
1.0
1.0
1.8
1.8
2.5
2.5
1.0
1.0
1.8
1.8
2.5
2.5
1.0
1.0
1.8
1.8
2.5
2.5
ns
ns
1 ≤ Fs ≤ 125 MSPS
Rise time measured
from 20% to 80% of
DRVDD
Fall time measured
from 80% to 20% of
DRVDD
tCLKRI Output clock
rise time
tCLKFA Output clock
SE
1.8
fall time
LL
1 ≤ Fs ≤ 125 MSPS
Timing Characteristics at Lower Sampling Frequencies
Sampling
frequency,
MSPS
tPDI CLOCK PROPAGATION DELAY,
ns
tsu DATA SETUP TIME, ns
th DATA HOLD TIME, ns
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
CMOS INTERFACE, DRVDD = 2.5 V TO 3.6 V
40
20
10.5
23
12
10.3
23
11.8
24.5
5.8
7.3
8.8
24.5
LVDS INTERFACE, DRVDD = 3.0 V to 3.6 V
40
20
8.5
21
10
1
1
2.3
2.3
3.5
5.5
7.5
22.5
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SLAS561A–JULY 2007–REVISED FEBRUARY 2008
N+16
N+4
N+3
N+15
N+2
Sample
N
N+1
N+14
Input
Signal
ta
CLKM
CLKP
Input
Clock
CLKOUTM
CLKOUTP
tsu
th
tPDI
14 Clock Cycles(1)
DDR
LVDS
Output Data
DXP, DXM
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
E – Even Bits D0,D2,D4,D6,D8,D10,D12
O – Odd Bits D1,D3,D5,D7,D9,D11,D13
N–10
N–9
N–1
N
N+1
N+2
tPDI
CLKOUT
tsu
14 Clock Cycles(1)
N–10
Parallel
CMOS
th
Output Data
D0–D13
N–9
N–1
N
N+1
N+2
T0105-06
(1) Latency is 10 clock cycles in low-latency mode.
Figure 1. Latency
CLKM
Input
Clock
CLKP
CLKM
Input
Clock
CLKP
tPDI
tPDI
CLKOUTM
Output
Clock
Output
Clock
CLKOUT
CLKOUTP
th
tsu
th
tsu
th
tsu
Dn(1)
Dn+1(2)
Output
Data Pair
Dn_Dn+1_P,
Dn_Dn+1_M
Dn(1)
Output
Data
Dn
(1)Dn – Bits D0, D2, D4, D6, D8, D10, D12
(2)Dn+1 – Bits D1, D3, D5, D7, D9, D11, D13
(1)Dn – Bits D0 to D13
T0107-02
T0106-04
Figure 3. CMOS Mode Timing
Figure 2. LVDS Mode Timing
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SLAS561A–JULY 2007–REVISED FEBRUARY 2008
DEVICE CONFIGURATION
ADS62P4X can be configured independently using either parallel interface control or serial interface
programming.
USING PARALLEL INTERFACE CONTROL ONLY
To control the device using the parallel interface, keep RESET tied to high (AVDD). Pins SEN, SCLK, CTRL1,
CTRL2 and CTRL3 can be used to directly control certain modes of the ADC. After power-up, the device will
automatically get configured as per the parallel pin voltage settings (Table 2 to Table 4).
In this mode, SEN and SCLK function as parallel analog control pins, which can be configured using a simple
resistor divider (Figure 4). Table 1 has a brief description of the modes controlled by the parallel pins.
Table 1. Parallel Pin Definition
PIN
TYPE OF PIN
CONTROLS MODES
SCLK
Analog control pins
(controlled by analog
voltage levels, see )
Coarse Gain and internal/external reference
SEN
LVDS/CMOS interface and output data format
CTRL1
CTRL2
CTRL3
Digital control pins
(controlled by digital
logic levels)
Together control various powerdown modes and MUX mode.
USING SERIAL INTERFACE PROGRAMMING ONLY
To program the device using the serial interface, keep RESET low. Pins SEN, SDATA, and SCLK function as
serial interface digital pins and are used to access the internal registers of ADC. The registers must first be reset
to their default values either by applying a pulse on RESET pin or by setting bit <RST> = 1. After reset, the
RESET pin must be kept low.
The serial interface section describes the register programming and register reset in more detail. Since the
parallel pins (CTRL1, CTRL2, CTRL3) are not used in this mode, they must be tied to ground.
USING BOTH SERIAL INTERFACE and PARALLEL CONTROLS
For increased flexibility, a combination of serial interface registers and parallel pin controls (CTRL1 to CTRL3)
can also be used to configure the device. To allow this, keep RESET low.
The parallel interface control pins CTRL1 to CTRL3 are available. After power-up, the device will automatically
get configured as per the voltage settings on these pins (Table 4).
SEN, SDATA, and SCLK function as serial interface digital pins and are used to access the internal registers of
ADC. The registers must first be reset to their default values either by applying a pulse on RESET pin or by
setting bit <RST> = 1. After reset, the RESET pin must be kept low. The serial interface section describes the
register programming and register reset in more detail.
Since the power down modes can be controlled using both the parallel pins and serial registers, the priority
between the two is determined by <OVRD> bit. When <OVRD> bit = 0, pins CTRL1 to CTRL3 control the power
down modes. With <OVRD> = 1, register bits <POWER DOWN> control these modes, over-riding the pin
settings.
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DETAILS OF PARALLEL CONFIGURATION ONLY
The functions controlled by each parallel pin are described below. A simple way of configuring the parallel pins is
shown in Figure 4.
Table 2. SCLK (Analog Control Pin)
SCLK
0
DESCRIPTION
0dB gain and Internal reference
(3/8)AVDD
(5/8)2AVDD
AVDD
0dB gain and External reference
3.5dB Coarse gain and External reference
3.5dB Coarse gain and Internal reference
Table 3. SEN (Analog Control Pin)
SEN
0
DESCRIPTION
2s complement format and DDR LVDS output
Straight binary and DDR LVDS output
(3/8)AVDD
(5/8)AVDD
AVDD
Straight binary and parallel CMOS output
2s complement format and parallel CMOS output
Table 4. CTRL1, CTRL2 and CTRL3 (Digital Control Pins)
CTRL1
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
CTRL2
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
CTRL3
DESCRIPTION
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
Normal operation
Channel A output buffer disabled
Channel B output buffer disabled
Channel A and B output buffer disabled
Channel A and B powered down
Channel A standby
Channel B standby
MUX mode of operation (only with CMOS interface Channel A and B data is multiplexed and
output on DB10 to DB0 pins. See Multiplexed output mode for detailed description.
HIGH
HIGH
HIGH
AVDD
(5/8) AVDD
3R
(5/8) AVDD
GND
AVDD
2R
3R
(3/8) AVDD
(3/8) AVDD
To Parallel Pin
GND
S0321-01
Figure 4. Simple Scheme to Configure Parallel Pins
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SLAS561A–JULY 2007–REVISED FEBRUARY 2008
SERIAL INTERFACE
The ADC has a set of internal registers, which can be accessed by the serial interface formed by pins SEN
(Serial interface Enable), SCLK (Serial Interface Clock) and SDATA (Serial Interface Data).
Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge
of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge
when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be
loaded in multiple of 16-bit words within a single active SEN pulse.
The first 8 bits form the register address and the remaining 8 bits the register data. The interface can work with
SCLK frequency from 20 MHz down to low speeds (few Hertz), and also with a non-50% SCLK duty cycle.
Register Initialization
After power-up, the internal registers must be initialized to their default values. This can be done in one of two
ways:
1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10ns) as
shown in Figure 5.
OR
2. By applying software reset. Using the serial interface, set the <RST> bit to high. This initializes internal
registers to their default values and then self-resets the <RST> bit to low. In this case the RESET pin is kept
low.
SERIAL INTERFACE TIMING CHARACTERISTICS
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V,
DRVDD = 1.8 V to 3.3 V, unless otherwise noted.
PARAMETER
MIN
> DC
25
TYP
MAX
UNIT
MHz
ns
fSCLK
tSLOADS
tSLOADH
tDS
SCLK frequency
20
SEN to SCLK setup time
SCLK to SEN hold time
SDATA setup time
SDATA hold time
25
ns
25
ns
tDH
25
ns
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SLAS561A–JULY 2007–REVISED FEBRUARY 2008
Register Address
Register Data
SDATA
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
t(DH)
D1
D0
t(SCLK)
t(DSU)
SCLK
t(SLOADH)
t(SLOADS)
SEN
RESET
T0109-01
Figure 5. Serial Interface Timing
RESET TIMING
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, unless otherwise
noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Delay from power-up of AVDD and DRVDD to RESET pulse
active
t1
Power-on delay
5
ms
t2
Reset pulse width
Register write delay
Power-up time
Pulse width of active RESET signal
10
25
ns
ns
t3
Delay from RESET disable to SEN active
tPO
Delay from power-up of AVDD and DRVDD to output stable
7
ms
Power Supply
AVDD, DRVDD
t1
RESET
t2
t3
SEN
T0108-01
NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset.
For parallel interface operation, RESET has to be tied permanently HIGH.
Figure 6. Reset Timing Diagram
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SLAS561A–JULY 2007–REVISED FEBRUARY 2008
SERIAL REGISTER MAP
(1)
Table 5. Summary of Functions Supported by Serial Interface
REGISTER
ADDRESS
REGISTER FUNCTIONS
A7–A0 IN
HEX
D7
D6
D5
0
D4
0
D3
0
D2
0
D1
D0
0
<RST>
Software Reset
00
10
0
0
<CLKOUT
STRENGTH>
0
0
0
0
0
0
<LVDS CURRENT>
LVDS buffer current
programmability
<CURRENT DOUBLE>
LVDS buffer current double
<DATAOUT
STRENGTH>
11
0
0
<LVDS TERMINATION>
Internal termination programmability
12
13
0
0
0
0
0
<OFFSET FREEZE>
0
0
0
0
<OUTPUT
INTERFACE>
LVDS or CMOS
interface
<POWER DOWN MODES>
<OVRD>
Over-ride
bit
<REF>
Internal/External
reference
<COARSE GAIN>
3.5 dB gain
14
0
and
MUX mode
<DATA FORMAT>
2s complement or straight
binary
Bit/Byte wise
(LVDS only)
16
17
0
0
0
0
0
0
<TEST PATTERNS>
<FINE GAIN>
0
0 to 6 dB gain in 0.5 dB steps
18
19
<CUSTOM LOW> Lower 8 bits
<CUSTOM HIGH> Upper 6 bits
0
0
<OFFSET TC>
Offset correction time constant
<GAIN CORRECTION>
0 to 0.5 dB, steps of 0.05 dB
<LOW
LATENCY>
1A
<OFFSET
EN>
Offset
correction
enable
<FILTER COEFF
SELECT>
In-built or custom
coefficients
<FILTER Enable>
Enable digital filtering
<DECIMATION RATE>
Decimate by 2, 4, 8
<ODD TAP
Enable>
1B
0
0
<DECIMATION FILTER
FREQ BANDS>
1D
0
0
0
0
0
1E to 2F
<FILTER COEFFICIENTS> 12 coefficients, each 12 bit signed
(1) Multiple functions in a register can be programmed in a single write operation.
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DESCRIPTION OF SERIAL REGISTERS
Table 6.
A7–A0
(hex)
D7
D6
D5
D4
D3
D2
D1
D0
<RST>
Software Reset
00
0
0
0
0
0
0
0
D1
<RST>
1
Software reset applied – resets all internal registers and self-clears to 0.
Table 7.
A7–A0
(hex)
D7
D6
D5
D4
D3
D2
D1
D0
10
<CLKOUT STRENGTH>
0
0
0
0
0
0
D7–D6
01
<CLKOUT STRENGTH> Output clock buffer drive strength control
WEAKER than default drive
00
DEFAULT drive strength
11
10
STRONGER than default drive strength (recommended for load capacitances > 5 pF)
MAXIMUM drive strength (recommended for load capacitances > 5 pF)
Table 8.
A7–A0
(hex)
D7
D6
D5
D4
D3
D2
D1
D0
LVDS CURRENT> LVDS
buffer current
<CURRENT DOUBLE>
LVDS buffer current double
11
0
0
DATAOUT STRENGTH>
programmability
D1–D0
<DATAOUT STRENGTH> Output data buffer drive strength control
WEAKER than default drive
DEFAULT drive strength
STRONGER than default drive strength (recommended for load capacitances > 5 pF)
MAXIMUM drive strength (recommended for load capacitances > 5 pF)
01
00
11
10
D3–D2
00
01
10
11
<LVDS CURRENT> LVDS Current programmability
3.5 mA
2.5 mA
4.5 mA
1.75 mA
D5–D4
00
CURRENT DOUBLE> LVDS Current double control
Default current, set by <LVDS CURR>
01
10
11
LVDS clock buffer current is doubled, 2x <LVDS CURR>
LVDS data and clock buffers current are doubled, 2x <LVDS CURR>
Unused
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Table 9.
A7–A0
(hex)
D7
D6
D5
D4
D3
D2
D1
D0
12
0
0
<LVDS TERMINATION> Internal termination programmability
D5–D3
000
001
010
011
100
101
110
111
<LVDS DATA TERM> Internal termination control for data outputs
No internal termination
300 Ω
180 Ω
110 Ω
150 Ω
100 Ω
81 Ω
60 Ω
D2–D0
000
001
010
011
100
101
110
111
<LVDS CLK TERM> Internal termination control for clock output
No internal termination
300 Ω
180 Ω
110 Ω
150 Ω
100 Ω
81 Ω
60 Ω
Table 10.
A7–A0
(hex)
D7
D6
D5
D4
D3
D2
D1
D0
13
0
0
0
<OFFSET FREEZE>
0
0
0
0
D4
0
1
<OFFSET FREEZE> Offset correction becomes inactive and the last estimated offset value is used to cancel the offset
Offset correction active
Offset correction inactive
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Table 11.
A7–A0
(hex)
D7
D6
D5
D4
D3
D2
D1
D0
<OUTPUT
INTERFACE>
LVDS or CMOS
interface
<REF>
Internal / External
reference
<OVRD>
Over-ride bit
<COARSE GAIN>
<POWER DOWN
MODES>
14
0
3.5 dB gain
D2-D0
<POWER DOWN MODES>
Normal operation
Channel A output buffer disabled
Channel B output buffer disabled
Channel A and B output buffers disabled
Global power down
Channel A standby
000
001
010
011
100
101
110
111
Channel B standby
Multiplexed mode, MUX – (only with CMOS interface)
Channel A and B data is multiplexed and output on DA10 to DA0 pins.
D3
0
1
<REF> Reference mode
Internal reference enabled
External reference enabled
D4
0
<COARSE GAIN> Coarse gain control
0 dB coarse gain
1
3.5 dB coarse gain
D5
0
<OUTPUT INTERFACE> Output interface selection
Parallel CMOS data outputs
1
DDR LVDS data outputs
D7
<OVRD> Over-ride bit – the LVDS/CMOS selection, power down and MUX modes can also be controlled using parallel pins.
By setting <OVRD> = 1, register bits LVDS <CMOS> and <POWER DOWN MODES> will over-ride the settings of the parallel
pins.
0
1
Disable over-ride
Enable over-ride
Table 12.
A7–A0
(hex)
D7
D6
D5
D4
D3
D2
D1
D0
DATA FORMAT>
2s complement or straight binary
16
0
0
0
Bit / Byte wise (LVDS only)
<TEST PATTERNS>
D2–D0
000
001
010
011
100
101
110
111
<TEST PATTERNS> Test Patterns to verify capture
Normal ADC operation
Outputs all zeros
Outputs all ones
Outputs toggle pattern
Outputs digital ramp
Outputs custom pattern
Unused
Unused
D3
Bit-wise/Byte-wise selection (DDR LVDS mode ONLY)
0
Bit wise – Odd bits (D1, D3, D5, D7, D9) on CLKOUT rising edge and Even bits (D0, D2, D4, D6, D8, D10) on CLKOUT
falling edge
1
Byte wise – Lower 7 bits (D0-D6) at CLKOUT rising edge and Upper 4 bits (D7-D10) at CLKOUT falling edge
D4
0
<DATA FORMAT> Data format selection
2s complement
1
Straight binary
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SLAS561A–JULY 2007–REVISED FEBRUARY 2008
Table 13.
A7–A0
(hex)
D7
D6
D5
D4
D3
D2
D1
D0
17
0
0
0
0
<FINE GAIN> 0 to 6 dB gain in 0.5 dB steps
D2–D0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Others
<FINE GAIN> Gain programmability in 0.5 dB steps
0 dB gain, default after reset
0.5 dB gain
1.0 dB gain
1.5 dB gain
2.0 dB gain
2.5 dB gain
3.0 dB gain
3.5 dB gain
4.0 dB gain
4.5 dB gain
5.0 dB gain
5.5 dB gain
6.0 dB gain
Unused
Table 14.
A7–A0
(hex)
D7
D6
D5
D4
D3
D2
D1
D0
18
<CUSTOM LOW> Lower 8 bits
<CUSTOM HIGH> Upper 6 bits
19
0
0
D7-D0
<CUSTOM LOW>
8 lower bits of custom pattern available at the output instead of ADC data.
D5-D0
<CUSTOM HIGH>
6 upper bits of custom pattern available at the output instead of ADC data.
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SLAS561A–JULY 2007–REVISED FEBRUARY 2008
Table 15.
A7–A0
(hex)
D7
D6
D5
D4
D3
D2
D1
D0
<OFFSET TC>
Offset correction time constant
<GAIN CORRECTION>
0 to 0.5 dB, steps of 0.05 dB
1A
<LOW LATENCY>
D2–D0
<GAIN CORRECTION> Enables fine gain correction in steps of 0.05 dB (same correction applies to both channels)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
0 dB gain, default after reset
+0.5 dB gain
+0.10 dB gain
+0.15 dB gain
+0.20 dB gain
+0.25 dB gain
+0.30 dB gain
+0.35 dB gain
+0.40 dB gain
+0.45 dB gain
+0.5 dB gain
D6-D4
<OFFSET TC> Time constant of offset correction in number of clock cycles (seconds, for sampling frequency = 125
MSPS)
000
001
010
011
100
101
110
111
227 (1.1 s)
226 (0.55 s)
225 (0.27 s)
224 (0.13 s)
228 (2.15 s)
229 (4.3 s)
227 (1.1 s)
227 (1.1 s)
D7
0
<LOW LATENCY>
Default latency, 14 clock cycles
1
Low latency enabled, 10 clock cycles – Digital Processing Block is bypassed.
Table 16.
A7–A0
(hex)
D7
D6
D5
D4
D3
D2
D1
D0
<FILTER COEFF
SELECT>
In-built or custom
coefficients
<OFFSET Enable>
Offset correction
enable
<FILTER Enable>
Enable digital filtering
<DECIMATION RATE>
Decimate by 2,4,8
<ODD TAP
Enable>
1B
0
D2-D0
<DECIMATION RATE> Decimation filters
000
001
011
100
Decimate by 2 (pre-defined or user coefficients can be used)
Decimate by 4 (pre-defined or user coefficients can be used)
NO decimation (Pre-defined coefficients are disabled, only custom coefficients are available)
Decimate by 8 (Only custom coefficients are available)
D3
0
1
<ODD TAP ENABLE>
Even taps enabled (24 coefficients)
0 Odd taps enabled (23 coefficients)
D4
0
1
<FILTER ENABLE>
Digital filter bypassed
Digital filter enabled
D5
0
<FILTER COEFF SELECT>
Pre-defined coefficients are loaded in the filter
1
User-defined coefficients are loaded in the filter (coefficients have to be loaded in registers – to - )
D7
0
1
<OFFSET Enable>
Offset correction disabled
Offset correction enabled
20
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SLAS561A–JULY 2007–REVISED FEBRUARY 2008
Table 17.
A7–A0
(hex)
D7
D6
D5
D4
D3
D2
D1
D0
1D
0
0
0
0
0
0
<DECIMATION FILTER FREQ BANDS>
D1-D0
<DECIMATION FILTER FREQ BAND> Decimation filters
With decimate by 2, <DECIMATION RATE> = 000:
Low pass filter (–6 dB frequency at Fs/4)
High pass filter (–6 dB frequency at Fs/4)
Unused
00
01
10, 11
With decimate by 4, <DECIMATION RATE> = 001:
Low pass filter (-3 dB frequency at Fs/8)
Band pass filter (center frequency at 3Fs/16)
Band pass filter (center frequency at 5Fs/16)
High pass filter (-3 dB frequency at 3Fs/8)
00
01
10
11
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SLAS561A–JULY 2007–REVISED FEBRUARY 2008
PIN DESCRIPTION (CMOS INTERFACE)
RGC PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DRVDD
DB4
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DRVDD
DA7
2
DB5
3
DA6
DB6
4
DA5
DB7
5
DA4
DB8
6
DA3
DB9
7
DA2
DB10
DB11
DB12
DB13
RESET
SCLK
SDATA
SEN
8
DA1
PAD
(Connected to DRGND)
9
DA0
10
11
12
13
14
15
16
DRGND
DRVDD
CTRL3
CTRL2
CTRL1
AVDD
AVDD
AVDD
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P0056-09
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SLAS561A–JULY 2007–REVISED FEBRUARY 2008
Pin Assignments (CMOS INTERFACE)
NUMBER OF
PIN NAME
DESCRIPTION
PIN NUMBER
PINS
AVDD
Analog power supply
Analog ground
16, 33, 34
3
9
AGND
17, 18, 21, 22, 24,
27, 28, 31, 32
CLKP, CLKM
INP_A, INM_A
INP_B, INM_B
VCM
Differential input clock
25, 26
29, 30
19, 20
23
2
2
2
1
Differential input signal – channel A
Differential input signal – channel B
Internal reference mode – Common-mode voltage output.
External reference mode – Reference input. The voltage forced on this pin sets
the ADC internal references.
RESET
Serial interface RESET input.
12
1
In serial interface mode, the user must initialize internal registers through
hardware RESET by applying a high-going pulse on this pin or by using
software reset (refer to Serial Interface section).
In parallel interface mode, the user has to tie RESET pin permanently high.
(SCLK, SDATA and SEN are used as parallel pin controls in this mode) The pin
has an internal 100-kΩ pull-down resistor.
SCLK
This pin functions as serial interface clock input when RESET is low.
It functions as analog control pin when RESET is tied high and controls coarse
gain and internal/external reference selection. See Table 2 for details.
The pin has an internal pull-down resistor to ground.
13
1
SDATA
SEN
This pin functions as serial interface data input when RESET is low. The pin has
an internal pull-down resistor to ground.
14
15
1
1
This pin functions as serial interface enable input when RESET is low.
It functions as analog control pin when RESET is tied high and controls the
output interface (LVDS/CMOS) and data format selection. See Table 3 for
details.
The pin has an internal pull-up resistor to AVDD.
CTRL1
These are digital logic input pins. Together they control various power down and
multiplexed mode. see Table 4 for details
35
36
1
1
CTRL2
CTRL3
37
1
DA0 to DA13
DB0 to DB13
CLKOUT
DRVDD
Channel A 14-bit data outputs, CMOS
Channel B 14-bit data outputs, CMOS
CMOS Output clock
40-47, 50-55
60-63, 2-11
57
14
14
1
Digital supply
1, 38, 48, 58
4
DRGND
Digital ground
39, 49, 59, 64 and
PAD
4
PAD
NC
Digital ground. Solder the bottom pad to the digital ground on the board using
multiple vias for good electrical and thermal performance.
–
1
1
Do not connect
56
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SLAS561A–JULY 2007–REVISED FEBRUARY 2008
PIN DESCRIPTION (LVDS INTERFACE)
RGC PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DRVDD
DB4M
DB4P
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DRVDD
DA6P
2
3
DA6M
DA4P
DB6M
DB6P
4
5
DA4M
DA2P
DB8M
DB8P
6
7
DA2M
DA0P
DB10M
DB10P
DB12M
DB12P
RESET
SCLK
8
PAD
(Connected to DRGND)
9
DA0M
DRGND
DRVDD
CTRL3
CTRL2
CTRL1
AVDD
AVDD
10
11
12
13
14
15
16
SDATA
SEN
AVDD
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P0056-10
Pin Assignments (LVDS INTERFACE)
PIN
NUMBER
NUMBER OF
PINS
PIN NAME
AVDD
DESCRIPTION
Analog power supply
Analog ground
16, 33, 34
3
9
AGND
17, 18, 21,
22, 24, 27,
28, 31,32
CLKP, CLKM
INP_A, INM_A
INP_B, INM_B
VCM
Differential input clock
25, 26
29, 30
19, 20
23
2
2
2
1
Differential input signal – Channel A
Differential input signal – Channel B
Internal reference mode – Common-mode voltage output.
External reference mode – Reference input. The voltage forced on this pin sets the
ADC internal references.
RESET
Serial interface RESET input.
12
1
In serial interface mode, the user must initialize internal registers through hardware
RESET by applying a high-going pulse on this pin or by using software reset (refer to
Serial Interface section).
In parallel interface mode, the user has to tie RESET pin permanently high. (SCLK,
SDATA and SEN are used as parallel pin controls in this mode) The pin has an internal
100-kΩ pull-down resistor.
24
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SLAS561A–JULY 2007–REVISED FEBRUARY 2008
Pin Assignments (LVDS INTERFACE) (continued)
PIN
NUMBER
NUMBER OF
PINS
PIN NAME
DESCRIPTION
SCLK
This pin functions as serial interface clock input when RESET is low.
It functions as analog control pin when RESET is tied high and controls coarse gain
and internal/external reference selection. See Table 2 for details.
The pin has an internal pull-down resistor to ground.
13
1
SDATA
SEN
This pin functions as serial interface data input when RESET is low. The pin has an
internal pull-down resistor to ground.
14
15
1
1
This pin functions as serial interface enable input when RESET is low.
It functions as analog control pin when RESET is tied high and controls the output
interface (LVDS/CMOS) and data format selection. See Table 3 for details.
The pin has an internal pull-up resistor to AVDD.
CTRL1
CTRL2
CTRL3
DA0P
These are digital logic input pins. Together they control various power down and
multiplexed mode. See Table 4 for details.
35
36
37
41
40
43
42
45
44
47
46
51
50
53
52
55
54
57
56
61
60
63
62
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
Channel A Differential output data D0 and D1 multiplexed, true
Channel A Differential output data D0 and D1 multiplexed, complement
Channel A Differential output data D2 and D3 multiplexed, true
Channel A Differential output data D2 and D3 multiplexed, complement
Channel A Differential output data D4 and D5 multiplexed, true
Channel A Differential output data D4 and D5 multiplexed, complement
Channel A Differential output data D6 and D7 multiplexed, true
Channel A Differential output data D6 and D7 multiplexed, complement
Channel A Differential output data D8 and D9 multiplexed, true
Channel A Differential output data D8 and D9 multiplexed, complement
Channel A Differential output data D10 and D11 multiplexed, true
Channel A Differential output data D10 and D11 multiplexed, complement
Channel A Differential output data D12 and D13 multiplexed, true
Channel A Differential output data D12 and D13 multiplexed, complement
Differential output clock, true
DA0M
DA2P
DA2M
DA4P
DA4M
DA6P
DA6M
DA8P
DA8M
DA10P
DA10M
DA12P
DA12M
CLKOUTP
CLKOUTM
DB0P
Differential output clock, complement
Channel B Differential output data D0 and D1 multiplexed, true
Channel B Differential output data D0 and D1 multiplexed, complement
Channel B Differential output data D2 and D3 multiplexed, true
Channel B Differential output data D2 and D3 multiplexed, complement
Channel B Differential output data D4 and D5 multiplexed, true
Channel B Differential output data D4 and D5 multiplexed, complement
Channel B Differential output data D6 and D7 multiplexed, true
Channel B Differential output data D6 and D7 multiplexed, complement
Channel B Differential output data D8 and D9 multiplexed, true
Channel B Differential output data D8 and D9 multiplexed, complement
Channel B Differential output data D10 and D11 multiplexed, true
Channel B Differential output data D10 and D11 multiplexed, complement
Channel B Differential output data D12 and D13 multiplexed, true
Channel B Differential output data D12 and D13 multiplexed, complement
Digital supply
DB0M
DB2P
DB2M
DB4P
DB4M
DB6P
2
5
DB6M
DB8P
4
7
DB8M
DB10P
DB10M
DB12P
DB12M
DRVDD
6
9
8
11
10
1, 38, 48,
58
DRGND
PAD
Digital ground
39, 49, 59,
64 and PAD
4
1
Digital ground. Solder the bottom pad to the digital ground on the board using multiple
vias for good electrical and thermal performance.
–
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SLAS561A–JULY 2007–REVISED FEBRUARY 2008
TYPICAL CHARACTERISTICS - ADS62P45 (FS= 125 MSPS)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
FFT for 20 MHz INPUT SIGNAL
FFT for 70 MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 88.2 dBc
SFDR = 86.6 dBc
SINAD = 73.7 dBFS
SNR = 73.8 dBFS
THD = 88.2 dBc
SINAD = 73.4 dBFS
SNR = 73.7 dBFS
THD = 85.4 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−140
−160
−100
−120
−140
−160
0
0
0
10
20
30
40
50
60
0
10
20
30
40
50
60
f − Frequency − MHz
f − Frequency − MHz
G001
G002
Figure 7.
Figure 8.
FFT for 190 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
−20
0
SFDR = 78.9 dBc
f
f
1 = 190.1 MHz, –7 dBFS
2 = 185.3 MHz, –7 dBFS
2-Tone IMD = –89 dBFS
SFDR = –96 dBFS
IN
SINAD = 71.2 dBFS
SNR = 72.1 dBFS
THD = 77.3 dBc
IN
−20
−40
−40
−60
−60
−80
−80
−100
−120
−140
−160
−100
−120
−140
−160
10
20
30
40
50
60
0
10
20
30
40
50
60
f − Frequency − MHz
f − Frequency − MHz
G003
G004
Figure 9.
Figure 10.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
94
92
90
88
86
84
82
80
78
76
76
75
74
73
72
71
70
Gain = 3.5 dB
Gain = 0 dB
Gain = 3.5 dB
Gain = 0 dB
25
50
75
100
125
150
175
200
0
25
50
75
100
125
150
175
200
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G005
G006
Figure 11.
Figure 12.
26
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SLAS561A–JULY 2007–REVISED FEBRUARY 2008
TYPICAL CHARACTERISTICS - ADS62P45 (FS= 125 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
SFDR vs INPUT FREQUENCY (LVDS interface)
SFDR vs INPUT FREQUENCY ACROSS GAINS
94
92
90
88
86
84
82
80
78
76
96
94
92
90
88
86
84
82
80
78
Input adjusted to get −1dBFS input
Gain = 3.5 dB
3 dB
5 dB
2 dB
4 dB
Gain = 0 dB
1 dB
6 dB
0 dB
0
25
50
75
100
125
150
175
200
0
25
50
75
100
125
150
175
200
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G007
G009
Figure 13.
Figure 14.
SINAD vs INPUT FREQUENCY ACROSS GAINS
PERFORMANCE vs AVDD
75
74
73
72
71
70
69
68
67
66
65
90
89
88
87
86
85
84
83
82
80
79
78
77
76
75
74
73
72
0 dB
1 dB
f
IN
= 70.1 MHz
DRV = 3.31 V
2 dB
3 dB
DD
SFDR
SNR
5 dB
50
4 dB
25
6 dB
Input adjusted to get −1dBFS input
0
75
100
125
150
175
200
3.0
3.1
3.2
3.3
3.4
3.5
3.6
f
IN
− Input Frequency − MHz
AV − Supply Voltage − V
DD
G010
G011
Figure 15.
Figure 16.
PERFORMANCE vs DRVDD
PERFORMANCE vs TEMPERATURE
90
89
88
87
86
85
84
83
82
80
88
87
86
85
84
83
82
78
77
76
75
74
73
72
f
IN
= 70.1 MHz
AV = 3.31 V
DD
79
78
77
76
75
74
73
72
SFDR
SFDR
SNR
SNR
f
IN
= 70.1 MHz
−20
3.0
3.1
3.2
3.3
3.4
3.5
3.6
−40
0
20
40
60
80
DRV − Supply Voltage − V
DD
T − Temperature − °C
G012
G013
Figure 17.
Figure 18.
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ADS62P43, ADS62P42
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SLAS561A–JULY 2007–REVISED FEBRUARY 2008
TYPICAL CHARACTERISTICS - ADS62P45 (FS= 125 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
PERFORMANCE vs INPUT AMPLITUDE
PERFORMANCE vs CLOCK AMPLITUDE
110
100
90
90
85
80
75
70
65
60
55
50
94
92
90
88
86
84
82
80
78
80
79
78
77
76
75
74
73
72
f
IN
= 20.1 MHz
SFDR (dBFS)
SFDR
80
SNR (dBFS)
70
60
SNR
50
SFDR (dBc)
40
f
IN
= 20.1 MHz
−10
30
−60
−50
−40
−30
−20
0
0.5
1.0
1.5
2.0
2.5
3.0
Input Amplitude − dBFS
Input Clock Amplitude − V
PP
G014
G015
Figure 19.
Figure 20.
OUTPUT NOISE HISTOGRAM
(INPUTS TIED TO COMMON-MODE)
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
40
94
92
90
88
86
84
82
80
78
76
79
RMS = 1.033 LSB
f
IN
= 20.1 MHz
78
77
76
75
74
73
72
71
70
35
30
25
20
15
10
5
SFDR
SNR
0
8171 8172 8173 8174 8175 8176 8177 8178 8179 8180
30
35
40
45
50
55
60
65
70
Input Clock Duty Cycle − %
Output Code
G016
G017
Figure 21.
Figure 22.
PERFORMANCE IN EXTERNAL REFERENCE MODE
93
91
89
87
85
83
80
f
= 20.1 MHz
IN
External Reference Mode
78
76
74
72
70
SFDR
SNR
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70
V
VCM
− VCM Voltage − V
G018
Figure 23.
28
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ADS62P43, ADS62P42
www.ti.com
SLAS561A–JULY 2007–REVISED FEBRUARY 2008
TYPICAL CHARACTERISTICS - ADS62P44 (FS= 105 MSPS)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
FFT for 20 MHz INPUT SIGNAL
FFT for 70 MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 88.26 dBc
SFDR = 84.45 dBc
SINAD = 73.81 dBFS
SNR = 73.94 dBFS
THD = 88 dBc
SINAD = 73.45 dBFS
SNR = 73.8 dBFS
THD = 83.4 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−140
−160
−100
−120
−140
−160
0
0
0
10
20
30
40
50
0
10
20
30
40
50
f − Frequency − MHz
f − Frequency − MHz
G019
G020
Figure 24.
Figure 25.
FFT for 190 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
−20
0
SFDR = 82.36 dBc
f
f
1 = 190.1 MHz, –7 dBFS
2 = 185.3 MHz, –7 dBFS
IN
SINAD = 71.57 dBFS
SNR = 72.09 dBFS
THD = 80.05 dBc
IN
−20
−40
2-Tone IMD = –87 dBFS
SFDR = –90 dBFS
−40
−60
−60
−80
−80
−100
−120
−140
−160
−100
−120
−140
−160
10
20
30
40
50
0
10
20
30
40
50
f − Frequency − MHz
f − Frequency − MHz
G021
G022
Figure 26.
Figure 27.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
96
94
92
90
88
86
84
82
80
78
76
76
75
74
73
72
71
70
Gain = 3.5 dB
Gain = 0 dB
Gain = 3.5 dB
Gain = 0 dB
25
50
75
100
125
150
175
200
0
25
50
75
100
125
150
175
200
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G023
G024
Figure 28.
Figure 29.
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ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com
SLAS561A–JULY 2007–REVISED FEBRUARY 2008
TYPICAL CHARACTERISTICS - ADS62P44 (FS= 105 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
SFDR vs INPUT FREQUENCY (LVDS interface)
SFDR vs INPUT FREQUENCY ACROSS GAINS
96
94
92
90
88
86
84
82
80
78
76
96
94
92
90
88
86
84
82
80
78
Input adjusted to get −1dBFS input
2 dB
3 dB
Gain = 3.5 dB
5 dB
Gain = 0 dB
4 dB
6 dB
1 dB
0 dB
0
25
50
75
100
125
150
175
200
0
25
50
75
100
125
150
175
200
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G025
G027
Figure 30.
Figure 31.
SINAD vs INPUT FREQUENCY ACROSS GAINS
PERFORMANCE vs AVDD
88
87
86
85
84
83
82
81
80
80
79
78
77
76
75
74
73
72
76
75
74
73
72
71
70
69
68
67
66
Input adjusted to get −1dBFS input
0 dB
f
IN
= 70.1 MHz
DRV = 3.31 V
DD
1 dB
2 dB
3 dB
SFDR
SNR
4 dB
5 dB
6 dB
3.0
3.1
3.2
3.3
3.4
3.5
3.6
0
25
50
75
100
125
150
175
200
f
IN
− Input Frequency − MHz
AV − Supply Voltage − V
DD
G028
G029
Figure 32.
Figure 33.
PERFORMANCE vs DRVDD
PERFORMANCE vs TEMPERATURE
90
89
88
87
86
85
84
83
82
80
90
88
86
84
82
80
78
78
77
76
75
74
73
72
f
IN
= 70.1 MHz
AV = 3.31 V
DD
79
78
77
76
75
74
73
72
SFDR
SFDR
SNR
SNR
f
IN
= 70.1 MHz
−20
3.0
3.1
3.2
3.3
3.4
3.5
3.6
−40
0
20
40
60
80
DRV − Supply Voltage − V
DD
T − Temperature − °C
G030
G031
Figure 34.
Figure 35.
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Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42
ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com
SLAS561A–JULY 2007–REVISED FEBRUARY 2008
TYPICAL CHARACTERISTICS - ADS62P44 (FS= 105 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
PERFORMANCE vs INPUT AMPLITUDE
PERFORMANCE vs CLOCK AMPLITUDE
110
100
90
90
85
80
75
70
65
60
55
50
94
92
90
88
86
84
82
80
78
80
79
78
77
76
75
74
73
72
SFDR (dBFS)
f
IN
= 20.1 MHz
SFDR
80
SNR (dBFS)
70
60
SNR
50
SFDR (dBc)
40
f
IN
= 20.1 MHz
−10
30
−60
−50
−40
−30
−20
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Input Amplitude − dBFS
Input Clock Amplitude − V
PP
G032
G033
Figure 36.
Figure 37.
OUTPUT NOISE HISTOGRAM WITH
INPUTS TIED TO COMMON-MODE
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
94
92
90
88
86
84
82
80
78
76
79
40
35
30
25
20
15
10
5
f
= 20.1 MHz
RMS = 1.006 LSB
IN
78
77
76
75
74
73
72
71
70
SFDR
SNR
0
8171 8172 8173 8174 8175 8176 8177 8178 8179 8180
25
30
35
40
45
50
55
60
65
70
75
Input Clock Duty Cycle − %
G034
Output Code
G035
Figure 38.
Figure 39.
PERFORMANCE IN EXTERNAL REFERENCE MODE
96
92
88
84
80
76
80
78
SFDR
76
SNR
74
72
70
f
IN
= 20.1 MHz
External Reference Mode
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70
V
VCM
− VCM Voltage − V
G036
Figure 40.
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ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com
SLAS561A–JULY 2007–REVISED FEBRUARY 2008
TYPICAL CHARACTERISTICS - ADS62P43 (FS= 80 MSPS)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
FFT for 20 MHz INPUT SIGNAL
FFT for 70 MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 89 dBc
SFDR = 89.82 dBc
SINAD = 74.15 dBFS
SNR = 74.55 dBFS
THD = 83.74 dBc
SINAD = 74.02 dBFS
SNR = 74.13 dBFS
THD = 88.99 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−140
−160
−100
−120
−140
−160
0
0
0
10
20
30
40
0
10
20
30
40
f − Frequency − MHz
f − Frequency − MHz
G037
G038
Figure 41.
Figure 42.
FFT for 190 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
−20
0
SFDR = 84.34 dBc
f
f
1 = 190.1 MHz, –7 dBFS
2 = 185.3 MHz, –7 dBFS
2-Tone IMD = −93 dBFS
SFDR = −98 dBFS
IN
SINAD = 72.39 dBFS
SNR = 72.76 dBFS
THD = 82.19 dBc
IN
−20
−40
−40
−60
−60
−80
−80
−100
−120
−140
−160
−100
−120
−140
−160
10
20
30
40
0
10
20
30
40
f − Frequency − MHz
f − Frequency − MHz
G039
G040
Figure 43.
Figure 44.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
98
96
94
92
90
88
86
84
82
80
76
75
74
73
72
71
70
Gain = 0 dB
Gain = 3.5 dB
Gain = 3.5 dB
Gain = 0 dB
25
50
75
100
125
150
175
200
0
25
50
75
100
125
150
175
200
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G041
G042
Figure 45.
Figure 46.
32
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Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42
ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com
SLAS561A–JULY 2007–REVISED FEBRUARY 2008
TYPICAL CHARACTERISTICS - ADS62P43 (FS= 80 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
SFDR vs INPUT FREQUENCY (LVDS interface)
SFDR vs INPUT FREQUENCY ACROSS GAINS
98
96
94
92
90
88
86
84
82
80
98
96
94
92
90
88
86
84
82
80
Input adjusted to get −1dBFS input
4 dB
5 dB
3 dB
Gain = 3.5 dB
6 dB
50
Gain = 0 dB
1 dB
0 dB
100
2 dB
125
0
25
50
75
100
125
150
175
200
0
25
75
150
175
200
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G043
G045
Figure 47.
Figure 48.
SINAD vs INPUT FREQUENCY ACROSS GAINS
PERFORMANCE vs AVDD
91
90
89
88
87
86
85
84
83
80
79
78
77
76
75
74
73
72
76
75
74
73
72
71
70
69
68
67
66
f
IN
= 70.1 MHz
0 dB
1 dB
DRV = 3.3 V
DD
2 dB
3 dB
SFDR
SNR
4 dB
5 dB
6 dB
Input adjusted to get −1dBFS input
3.0
3.1
3.2
3.3
3.4
3.5
3.6
0
25
50
75 100 125 150 175
200
f
IN
− Input Frequency − MHz
AV − Supply Voltage − V
DD
G046
G047
Figure 49.
Figure 50.
PERFORMANCE vs DRVDD
PERFORMANCE vs TEMPERATURE
92
91
90
89
88
87
86
85
84
80
92
90
88
86
84
82
80
78
77
76
75
74
73
72
f
IN
= 70.1 MHz
AV = 3.31 V
DD
79
78
77
76
75
74
73
72
SFDR
SNR
SFDR
SNR
f
IN
= 70.1 MHz
3.0
3.1
3.2
3.3
3.4
3.5
3.6
−40
−20
0
20
40
60
80
DRV − Supply Voltage − V
DD
T − Temperature − °C
G048
G049
Figure 51.
Figure 52.
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ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com
SLAS561A–JULY 2007–REVISED FEBRUARY 2008
TYPICAL CHARACTERISTICS - ADS62P43 (FS= 80 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
PERFORMANCE vs INPUT AMPLITUDE
PERFORMANCE vs CLOCK AMPLITUDE
110
100
90
90
85
80
75
70
65
60
55
50
94
92
90
88
86
84
82
80
78
79
78
77
76
75
74
73
72
71
SFDR (dBFS)
f
IN
= 20.1 MHz
SFDR
SNR
80
SNR (dBFS)
70
60
50
SFDR (dBc)
40
f
IN
= 20.1 MHz
−10 0
30
−60
−50
−40
−30
−20
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Input Amplitude − dBFS
Input Clock Amplitude − V
PP
G050
G051
Figure 53.
Figure 54.
OUTPUT NOISE HISTOGRAM WITH
INPUTS TIED TO COMMON-MODE
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
94
92
90
88
86
84
82
80
78
76
79
40
35
30
25
20
15
10
5
f
= 20.1 MHz
RMS = 1.019 LSB
IN
78
77
76
75
74
73
72
71
70
SFDR
SNR
0
8174 8175 8176 8177 8178 8179 8180 8181 8182 8183
25
30
35
40
45
50
55
60
65
70
75
Input Clock Duty Cycle − %
G052
Output Code
G053
Figure 55.
Figure 56.
PERFORMANCE IN EXTERNAL REFERENCE MODE
92
90
88
86
84
80
f
= 20.1 MHz
IN
External Reference Mode
78
76
74
72
70
SFDR
SNR
82
1.35
1.40
1.45
1.50
1.55
1.60
1.65
V
VCM
− VCM Voltage − V
G054
Figure 57.
34
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ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com
SLAS561A–JULY 2007–REVISED FEBRUARY 2008
TYPICAL CHARACTERISTICS - ADS62P42 (FS= 65 MSPS)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
FFT for 20 MHz INPUT SIGNAL
FFT for 70 MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 88.5 dBc
SFDR = 88.18 dBc
SINAD = 74.35 dBFS
SNR = 74.56 dBFS
THD = 86.5 dBc
SINAD = 74.13 dBFS
SNR = 74.28 dBFS
THD = 87.89 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−140
−160
−100
−120
−140
−160
0
0
0
10
20
30
0
10
f − Frequency − MHz
Figure 59.
20
30
f − Frequency − MHz
G055
G056
Figure 58.
FFT for 190 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
−20
0
SFDR = 89.9 dBc
f
f
1 = 190.1 MHz, –7 dBFS
2 = 185.3 MHz, –7 dBFS
IN
SINAD = 71.51 dBFS
SNR = 71.88 dBFS
THD = 81.32 dBc
IN
−20
−40
2-Tone IMD = 92 dBFS
SFDR = 95 dBFS
−40
−60
−60
−80
−80
−100
−120
−140
−160
−100
−120
−140
−160
10
20
30
0
10
20
30
f − Frequency − MHz
f − Frequency − MHz
G057
G058
Figure 60.
SFDR vs INPUT FREQUENCY
Gain = 3.5 dB
Figure 61.
SNR vs INPUT FREQUENCY
96
94
92
90
88
86
84
82
80
78
76
76
75
74
73
72
71
70
Gain = 0 dB
Gain = 3.5 dB
Gain = 0 dB
25
50
75
100
125
150
175
200
0
25
50
75
100
125
150
175
200
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G059
G060
Figure 62.
Figure 63.
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Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42
ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com
SLAS561A–JULY 2007–REVISED FEBRUARY 2008
TYPICAL CHARACTERISTICS - ADS62P42 (FS= 65 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
SFDR vs INPUT FREQUENCY (LVDS interface)
SFDR vs INPUT FREQUENCY ACROSS GAINS
96
94
92
90
88
86
84
82
80
78
76
98
96
94
92
90
88
86
84
82
80
Input adjusted to get −1dBFS input
Gain = 3.5 dB
4 dB
5 dB
3 dB
6 dB
Gain = 0 dB
0 dB
2 dB
1 dB
0
25
50
75
100
125
150
175
200
0
25
50
75
100
125
150
175
200
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G061
G063
Figure 64.
Figure 65.
SINAD vs INPUT FREQUENCY ACROSS GAINS
PERFORMANCE vs AVDD
91
90
89
88
87
86
85
84
83
80
79
78
77
76
75
74
73
72
76
75
74
73
72
71
70
69
68
67
66
f
= 70.1 MHz
0 dB
1 dB
IN
DRV = 3.3 V
DD
2 dB
3 dB
SFDR
SNR
4 dB
6 dB
Input adjusted to get −1dBFS input
5 dB
3.0
3.1
3.2
3.3
3.4
3.5
3.6
0
25
50
75 100 125 150 175
200
f
IN
− Input Frequency − MHz
AV − Supply Voltage − V
DD
G064
G065
Figure 66.
Figure 67.
PERFORMANCE vs DRVDD
PERFORMANCE vs TEMPERATURE
93
92
91
90
89
88
87
86
85
80
92
90
88
86
84
82
80
78
77
76
75
74
73
72
f
IN
= 70.1 MHz
AV = 3.31 V
DD
79
78
77
76
75
74
73
72
SFDR
SFDR
SNR
SNR
f
IN
= 70.1 MHz
3.0
3.1
3.2
3.3
3.4
3.5
3.6
−40
−20
0
20
40
60
80
DRV − Supply Voltage − V
DD
T − Temperature − °C
G066
G067
Figure 68.
Figure 69.
36
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Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42
ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com
SLAS561A–JULY 2007–REVISED FEBRUARY 2008
TYPICAL CHARACTERISTICS - ADS62P42 (FS= 65 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
PERFORMANCE vs INPUT AMPLITUDE
PERFORMANCE vs CLOCK AMPLITUDE
110
100
90
90
85
80
75
70
65
60
55
50
94
92
90
88
86
84
82
80
78
77
76
75
74
73
72
71
70
69
SFDR
SFDR (dBFS)
SNR (dBFS)
80
SNR
70
60
50
SFDR (dBc)
40
f
IN
= 20.1 MHz
2.5 3.0
f
IN
= 20.1 MHz
−10
30
−60
−50
−40
−30
−20
0
0.0
0.5
1.0
1.5
2.0
Input Amplitude − dBFS
Input Clock Amplitude − V
PP
G068
G069
Figure 70.
Figure 71.
OUTPUT NOISE HISTOGRAM WITH
INPUTS TIED TO COMMON-MODE
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
100
98
96
94
92
90
88
86
84
82
79
40
f
= 20.1 MHz
RMS = 1.025 LSB
IN
78
77
76
75
74
73
72
71
70
35
30
25
20
15
10
5
SFDR
SNR
0
8175 8176 8177 8178 8179 8180 8181 8182 8183
25
30
35
40
45
50
55
60
65
70
75
Input Clock Duty Cycle − %
G070
Output Code
G071
Figure 72.
Figure 73.
PERFORMANCE IN EXTERNAL REFERENCE MODE
95
93
91
89
87
85
80
f
= 20.1 MHz
IN
External Reference Mode
78
76
74
72
70
SFDR
SNR
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70
V
VCM
− VCM Voltage − V
G072
Figure 74.
Copyright © 2007–2008, Texas Instruments Incorporated
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37
Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42
ADS62P45, ADS62P44
ADS62P43, ADS62P42
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SLAS561A–JULY 2007–REVISED FEBRUARY 2008
TYPICAL CHARACTERISTICS - LOW SAMPLING FREQUENCIES
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty
cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted)
FS = 25 MSPS
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
100
95
90
85
80
75
70
80
78
76
74
72
70
68
66
Gain = 3.5 dB
Gain = 0 dB
Gain = 0 dB
Gain = 3.5 dB
0
25
50
75
100
125
150
175
200
0
25
50
75
100
125
150
175
200
f
IN
− Input Frequency − MHz
f
IN
− Input Frequency − MHz
G075
G076
Figure 75.
Figure 76.
COMMON PLOTS
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty
cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted)
POWER DISSIPATION vs
SAMPLING FREQUENCY (DDR LVDS and CMOS)
COMMON-MODE REJECTION RATIO vs FREQUENCY
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
f
C
= 2.5 MHz
= 5 pF
IN
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
L
LVDS
CMOS
0
25
50
75
100
125
0
25
50
75
100
125
150
175
200
f
S
− Sampling Frequency − MSPS
f − Frequency − MHz
G078
G077
Figure 77.
Figure 78.
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COMMON PLOTS (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty
cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted)
DRVDD current (CMOS) vs
SAMPLING FREQUENCY
across load capacitance at 2 MHz input frequency
60
3.3 V, No Load
1.8 V, 5 pF
50
1.8 V, 10 pF
40
3.3 V, 5 pF
30
20
10
0
3.3 V, 10 pF
1.8 V, No Load
100 125
0
25
50
75
f
S
− Sampling Frequency − MSPS
G079
Figure 79.
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APPLICATION INFORMATION
THEORY OF OPERATION
ADS62P4X is a low power 14-bit dual channel pipeline ADC family fabricated in a CMOS process using switched
capacitor techniques.
The conversion process is initiated by a rising edge of the external input clock. Once the signal is captured by
the input sample and hold, the input sample is sequentially converted by a series of small resolution stages, with
the outputs combined in a digital correction logic block. At every clock edge the sample propagates through the
pipeline resulting in a data latency of 14 clock cycles. The output is available as 14-bit data, in DDR LVDS or
CMOS and coded in either straight offset binary or binary 2s complement format.
ANALOG INPUT
The analog input consists of a switched-capacitor based differential sample and hold architecture.
This differential topology results in very good AC performance even for high input frequencies at high sampling
rates. The INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V, available on
VCM pin. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM +
0.5 V and VCM – 0.5 V, resulting in a 2 VPP differential input swing. The maximum swing is determined by the
internal reference voltages REFP (2.5 V nominal) and REFM (0.5 V, nominal).
Sampling
Switch
Lpkg
» 2 nH
Sampling
Capacitor
RCR Filter
INP
Ron
15 W
25 W
Csamp
4 pF
Cbond
» 1 pF
Cpar2
1 pF
50 W
Resr
100 W
Cpar1
0.8 pF
Ron
10 W
3.2 pF
50 W
Lpkg
» 2 nH
Csamp
4 pF
Ron
15 W
25 W
INM
Sampling
Capacitor
Cbond
» 1 pF
Cpar2
1 pF
Resr
100 W
Sampling
Switch
S0322-01
Figure 80. Analog Input Equivalent Circuit
The input sampling circuit has a high 3-dB bandwidth that extends up to 450 MHz (measured from the input pins
to the sampled voltage).
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1
0
−1
−2
−3
−4
−5
−6
−7
0
100
200
300
400
500
600
f − Input Frequency − MHz
I
G080
Figure 81. ADC Analog Bandwidth
Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This improves the common-mode
noise immunity and even order harmonic rejection. A 5-Ω resistor in series with each input pin is recommended
to damp out ringing caused by the package parasitics.
It is also necessary to present low impedance (50 Ω) for the common mode switching currents. This can be
achieved by using two resistors from each input terminated to the common mode voltage (VCM).
In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency
range and matched impedance to the source. While doing this, the ADC input impedance must be considered.
Figure 82 and Figure 83 show the impedance (Zin = Rin || Cin) looking into the ADC input pins.
100
10
1
0.1
0.01
0
100
200
300
400
500
600
f − Frequency − MHz
G081
Figure 82. ADC Analog Input Resistance (Rin) Across Frequency
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9
8
7
6
5
4
3
2
1
0
0
100
200
300
400
500
600
f − Frequency − MHz
G082
Figure 83. ADC Analog Input Capacitance (Cin) Across Frequency
Using RF-Transformer Based Drive Circuits
Figure 84 shows a configuration using a single 1:1 turns ratio transformer (for example, Coilcraft WBC1-1) that
can be used for low input frequencies (about 100 MHz). The single-ended signal is fed to the primary winding of
the RF transformer. The transformer is terminated on the secondary side. Putting the termination on the
secondary side helps to shield the kickbacks caused by the sampling circuit from the RF transformer’s leakage
inductances. The termination is accomplished by two resistors connected in series, with the center point
connected to the 1.5-V common mode (VCM). The value of the termination resistors (connected to common
mode) has to be low ( <100 Ω) to provide a low-impedance path for the ADC common-mode switching currents.
ADS62P4x
0.1 mF
INP
25 W
0.1 mF
25 W
INM
1:1
VCM
S0163-03
Figure 84. Drive Circuit at Low Input Frequencies
At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results
in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps
minimize this mismatch, and good performance is obtained for high frequency input signals. Figure 85 shows an
example using two transformers (Coilcraft WBC1-1). An additional termination resistor pair (enclosed within the
shaded box) may be required between the two transformers to improve the balance between the P and M sides.
The center point of this termination must be connected to ground.
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ADS62P4x
0.1 mF
INP
50 W
50 W
0.1 mF
50 W
50 W
INM
1:1
1:1
VCM
S0164-05
Figure 85. Drive Circuit at High Input Frequencies
Using Differential Amplifier Drive Circuits
Figure 86 shows a drive circuit using a differential amplifier (TI's THS4509) to convert a single-ended input to
differential output that can be interface to the ADC analog input pins. In addition to the single-ended to differential
conversion, the amplifier also provides gain (10 dB). RFIL helps to isolate the amplifier outputs from the switching
input of the ADC. Together with CFIL it also forms a low-pass filter that band-limits the noise (and signal) at the
ADC input. As the amplifier output is ac-coupled, the common-mode voltage of the ADC input pins is set using
two 200-Ω resistors connected to VCM.
The amplifier output can also be dc-coupled. Using the output common-mode control of the THS4509, the ADC
input pins can be biased to 1.5 V. In this case, use +4-V and –1-V supplies for the THS4509 so that its output
common-mode voltage (1.5 V) is at mid-supply.
RF
+VS
ADS62P4x
0.1 mF
RFIL
500 W
5 W
0.1 mF 10 mF
0.1 mF
INP
RS
RG
CFIL
200 W
0.1 mF
RT
CM THS4509
RG
200 W
5 W
CFIL
RFIL
INM
0.1 mF
500 W
RS || RT
VCM
0.1 mF
–VS
0.1 mF 10 mF
0.1 mF
RF
S0259-02
Figure 86. Drive Circuit Using the THS4509
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Input Common-Mode
To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1-µF low-inductance capacitor
connected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADC
sinks a common-mode current in the order of 165 µA (at 125 MSPS). Equation 1 describes the dependency of
the common-mode current and the sampling frequency.
165 mA Fs
125 MSPS
(1)
This equation helps to design the output capability and impedance of the VCM driving circuit accordingly.
REFERENCE
ADS62P4X has built-in internal references REFP and REFM, requiring no external components. Design schemes
are used to linearize the converter load seen by the references; this and the on-chip integration of the requisite
reference capacitors eliminates the need for external decoupling. The full-scale input range of the converter can
be controlled in the external reference mode as explained below. The internal or external reference modes can
be selected by programming the serial interface register bit (REF).
INTREF
Internal
VCM
Reference
1 kW
INTREF
4 kW
EXTREF
REFM
REFP
ADS62P4x
S0165-05
Figure 87. Reference Section
Internal Reference
When the device is in internal reference mode, the REFP and REFM voltages are generated internally.
Common-mode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analog
input pins.
External Reference
When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on the
VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential
input voltage corresponding to full-scale is given in Equation 2.
Full-scale differential input pp = (Voltage forced on VCM) × 1.33
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In this mode, the 1.5-V common-mode voltage to bias the input pins has to be generated externally.
COARSE GAIN AND PROGRAMMABLE FINE GAIN
ADS62P4X includes gain settings that can be used to get improved SFDR performance (over 0dB gain mode).
For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 18.
The coarse gain is a fixed setting of 3.5 dB and is designed to improve SFDR with little degradation in SNR. The
fine gain is programmable in 0.5 dB steps from 0 to 6 dB; however the SFDR improvement is achieved at the
expense of SNR. So, the programmable fine gain makes it possible to trade-off between SFDR and SNR. The
coarse gain makes it possible to get best SFDR but without losing SNR significantly.
The gains can be programmed using the serial interface (bits COARSE GAIN and FINE GAIN). Note that the
default gain after reset is 0 dB.
Table 18. Full-Scale Range Across Gains
GAIN, dB
0
TYPE
FULL-SCALE, VPP
Default after reset
Coarse (fixed)
2V
3.5
1.34
1.89
1.78
1.68
1.59
1.50
1.42
1.34
1.26
1.19
1.12
1.06
1.00
0.5
1.0
1.5
2.0
2.5
3.0
Fine (programmable)
3.5
4.0
4.5
5.0
5.5
6.0
CLOCK INPUT
The clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS), with little or
no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using
internal 5-kΩ resistors as shown in Figure 88. This allows using transformer-coupled drive circuits for sine wave
clock or ac-coupling for LVPECL, LVDS clock sources (Figure 90 and Figure 91).
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Clock Buffer
Lpkg
» 2 nH
10 W
CLKP
Cbond
» 1 pF
Ceq
Ceq
5 kW
Resr
» 100 W
VCM
6 pF
5 kW
Lpkg
» 2 nH
10 W
CLKM
Cbond
» 1 pF
Resr
» 100 W
Ceq » 1 to 3 pF, equivalent input capacitance of clock buffer
S0275-02
Figure 88. Internal Clock Buffer
100k
10k
1k
100
10
5
25
45
65
85
105
125
f
S
− Sampling Frequency − MSPS
G083
Figure 89. Clock Input Impedance
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0.1 mF
CLKP
Differential Sine-Wave
or PECL or LVDS Clock Input
0.1 mF
CLKM
ADS62P4x
S0167-06
Figure 90. Differential Clock Driving Circuit
Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-µF
capacitor, as shown in Figure 91.
0.1 mF
CMOS Clock Input
CLKP
0.1 mF
CLKM
ADS62P4x
S0168-10
Figure 91. Single-Ended Clock Driving Circuit
For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode
noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass
filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a
non-50% duty cycle clock input.
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POWER DOWN
ADS62P4X has three powerdown modes – power down global, individual channel standby and individual channel
output buffer disable. These can be set using either the serial register bits or using the control pins CTRL1 to
CTRL3.
Table 19. Powerdown Modes
CONFIGURE USING
WAKE-UP
POWERDOWN MODES
SERIAL INTERFACE
PARALLEL CONTROL PINS
TIME
<POWER DOWN MODES>
CTRL1
low
CTRL2
low
CTRL3
low
Normal operation
000
001
010
011
100
101
110
—
Channel A output buffer disabled
Channel B output buffer disabled
Channel A and B output buffer disabled
Channel A and B powered down
Channel A standby
low
low
high
low
Fast (100 ns)
Fast (100 ns)
Fast (100 ns)
Slow (15 µS)
Fast (100 ns)
Fast (100 ns)
low
high
high
low
low
high
low
high
high
high
low
high
low
Channel B standby
high
Multiplexed (MUX) mode – Output data of
channel A and B is multiplexed and available
on DA13 to DA0 pins.
111
high
high
high
—
Power Down Global
In this mode, the entire chip including both the A/D converters, internal reference and the output buffers are
powered down resulting in reduced total power dissipation of about 50 mW. The output buffers are in high
impedance state. The wake-up time from the global power down to data becoming valid in normal mode is
typically 15 µs.
Channel Standby (Individual or Both Channels)
This mode allows the individual ADCs to be powered down. The internal references are active and this results in
fast wake-up time, about 100 ns. The total power dissipation in standby is about 482 mW.
Output Buffer Disable (Individual or Both Channels)
Each channel’s output buffer can be disabled and put in high impedance state -- wakeup time from this mode is
fast, about 100 ns.
Input Clock Stop
In addition to the above, the converter enters a low-power mode when the input clock frequency falls below 1
MSPS. The power dissipation is about 140 mW.
POWER SUPPLY SEQUENCE
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are
separated in the device. Externally, they can be driven from separate supplies or derived from a single supply.
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DIGITAL OUTPUT INFORMATION
ADS62P4X provides 14-bit data per channel and a common output clock synchronized with the data. The output
interface can be either parallel CMOS or DDR LVDS voltage levels and can be selected using serial register bit
<OUTPUT INTERFACE> or parallel pin SEN.
Parallel CMOS Interface
In the CMOS mode, the output buffer supply (DRVDD) can be operated over a wide range from 1.8 V to 3.3 V
(typical). Each data bit is output on separate pin as CMOS voltage level, every clock cycle (see Figure 92).
For DRVDD > 2.2 V, it is recommended to use the CMOS output clock (CLKOUT) to latch data in the receiving
chip. The rising edge of CLKOUT can be used to latch data in the receiver, even at the highest sampling speed.
It is recommended to minimize the load capacitance seen by data and clock output pins by using short traces to
the receiver. Also, match the output data and clock traces to minimize the skew between them.
For DRVDD < 2.2 V, it is recommended to use external clock (for example, input clock delayed to get desired
setup/hold times).
CMOS
Output Buffers
DA0
DA1
DA2
DA3
·
14-Bit Channel-A
Data
·
·
DA12
DA13
CLKOUT
DB0
DB1
DB2
DB3
·
14-Bit Channel-B
Data
·
·
DB12
DB13
B0287-01
Figure 92. CMOS Output Interface
Output Buffer Strength Programmability
Switching noise (caused by CMOS output data transitions) can couple into the analog inputs during the instant of
sampling and degrade the SNR. The coupling and SNR degradation increases as the output buffer drive is made
stronger. To minimize this, ADS62P4X CMOS output buffers are designed with controlled drive strength to get
best SNR. The default drive strength also ensures wide data stable window for load capacitances up to 5 pF and
DRVDD supply voltage >2.2 V.
To ensure wide data stable window for load capacitance > 5 pF, there exists option to increase the output data
and clock drive strengths using the serial interface ( DATAOUT STRENGTH and CLKOUT STRENGTH). Note
that for DRVDD supply voltage <2.2 V, it is recommended to use maximum drive strength (for any value of load
capacitance).
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CMOS Mode Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock
cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined
by the average number of output bits switching, which is a function of the sampling frequency and the nature of
the analog input signal.
Digital current due to CMOS output switching = CL × DRVDD × (N × FAVG),
where CL = load capacitance, N × FAVG = average number of output bits switching.
Figure 79 shows the current with various load capacitances across sampling frequencies at 2 MHz analog input
frequency.
DDR LVDS Interface
The LVDS interface works only with 3.3-V DRVDD supply. In this mode, the 11 data bits of each channel and a
common output clock are available as LVDS (Low Voltage Differential Signal) levels. Two successive data bits
are multiplexed and output on each LVDS differential pair every clock cycle (DDR – Double Data Rate,
Figure 94).
Pins
LVDS Buffers
DA0P
Data Bits D0, D1
DA0M
DA2P
Data Bits D2, D3
DA2M
14-Bit Channel-A
Data
·
·
·
·
·
·
DA12P
DA12M
Data Bits D12, D13
Output Clock
CLKOUTP
CLKOUTM
DB0P
DB0M
Data Bits D0, D1
Data Bits D2, D3
DB2P
DB2M
14-Bit Channel-B
Data
·
·
·
·
·
·
DB12P
DB12M
Data Bits D12, D13
B0288-01
Figure 93. DDR LVDS Outputs
Odd data bits D1, D3, D5, D7, D9 are output at the rising edge of CLKOUTP and even data bits D0, D2, D4, D6,
D8, D10 are output at the falling edge of CLKOUTP. Both the rising and falling edges of CLKOUTP have to be
used to capture all the data bits.
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CLKOUTM
CLKOUTP
DA0 (DB0)
DA2 (DB2)
DA4 (DB4)
DA6 (DB6)
DA8 (DB8)
DA10 (DB10)
DA12 (DB12)
D0
D2
D1
D3
D0
D2
D1
D3
D4
D5
D4
D5
D6
D7
D6
D7
D8
D9
D8
D9
D10
D12
D11
D13
D10
D12
D11
D13
Sample N
Sample N+1
T0110-02
Figure 94. DDR LVDS Interface
LVDS Buffer Current Programmability
The default LVDS buffer output current is 3.5 mA. When terminated by 100 Ω, this results in a 350-mV
single-ended voltage swing (700-mVPP differential swing). The LVDS buffer currents can also be programmed to
2.5 mA, 4.5 mA, and 1.75 mA (LVDS CURRENT). In addition, there exists a current double mode, where this
current is doubled for the data and output clock buffers (register bits CURRENT DOUBLE).
LVDS Buffer Internal Termination
An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially
terminated inside the device. The termination resistances available are –300 Ω, 185 Ω, and 150 Ω (nominal with
±20% variation). Any combination of these three terminations can be programmed; the effective termination is
the parallel combination of the selected resistances. This results in eight effective terminations from open (no
termination) to 60 Ω.
The internal termination helps to absorb any reflections coming from the receiver end, improving the signal
integrity. With 100 Ω internal and 100-Ω external termination, the voltage swing at the receiver end is halved
(compared to no internal termination). The voltage swing can be restored by using the LVDS current double
mode. Figure 95 and Figure 96 compare the LVDS eye diagrams without and with 100-Ω internal termination.
With internal termination, the eye looks clean even with 10-pF load capacitance (from each output pin to ground).
The terminations can be programmed using register bits (LVDS TERMINATION).
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Figure 95. LVDS Eye Diagram – No Internal Termination, External Termination = 100 Ω
Figure 96. LVDS Eye Diagram – with 100-Ω Internal Termination, External Termination = 100 Ω and LVDS
Current Double Mode Enabled
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Output Data Format
Two output data formats are supported – 2s complement and straight binary. They can be selected using the
serial interface register bit <DATA FORMAT> or controlling the SEN pin in parallel configuration mode.
In the event of an input voltage overdrive, the digital outputs go to the appropriate full scale level. For a positive
overdrive, the output code is 0x7FF in offset binary output format, and 0x3FF in 2s complement output format.
For a negative input overdrive, the output code is 0x000 in offset binary output format and 0x400 in 2s
complement output format.
Multiplexed Output mode
This mode is available only with CMOS interface. In this mode, the digital outputs of both the channels are
multiplexed and output on a single bus (DB0-DB10 pins), as per the timing diagram shown in Figure 97. The
channel A output pins (DA0-DA10) are three-stated. Since the output data rate on the DB bus is effectively
doubled, this mode is recommended only for low sampling frequencies (< 65 MSPS).
This mode can be enabled using register bits <POWER DOWN MODES> or using the parallel pins CTRL1 -3.
CLKOUT
DB0
DB1
DB2
DA0
DA1
DA2
DB0
DB1
DB2
DA0
DA1
DA2
DB0
DB1
DB2
DB13
DA13
DB13
DA13
DB13
Sample N
Sample N+1
T0297-01
Figure 97. Multiplexed Mode – Output Timing
Low Latency Mode
The default latency of ADS62P4X is 14 clock cycles. For applications, which cannot tolerate large latency,
ADS62P4X includes a special mode with 10 clock cycles latency. In the low latency condition, the Digital
Processing block is bypassed and its features (offset correction, fine gain, decimation filters) are not available.
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DETAILS OF DIGITAL PROCESSING BLOCK
CLIPPER
From
ADC
Output
14 Bits
14 Bits
14 Bits
14 Bits
14 Bits
To output buffers
LVDS or CMOS
24 TAP FILTER
Fine Gain
(0 to 6 dB
0.05 dB Steps)
Gain Correction
(0.05 dB Steps)
- LOW PASS
- HIGH PASS
- BAND PASS
DECIMATION
BY 2/4/8
14 Bits
0
OFFSET
ESTIMATION
BLOCK
Filter Select
Disable
Offset
Correction
Bypass
Filter
Bypass
Decimation
Freeze Offset
Correction
OFFSET
CORRECTION
GAIN
CORRECTION
DIGITAL
FILTER and DECIMATION
FINE GAIN
DIGITAL PROCESSING BLOCK
B0289-01
Figure 98. Digital Processing Block Diagram
Offset Correction
ADS62P4X has an internal offset correction algorithm that estimates and corrects dc offset up to ±10 mV. The
correction can be enabled using the serial register bit (OFFSET LOOP EN). Once enabled, the algorithm
estimates the channel offset and applies the correction every clock cycle. The time constant of the correction
loop is a function of the sampling clock frequency. The time constant can be controlled using register bits
(OFFSET LOOP TC) as described in Table 20.
Table 20. Time Constant of Offset Correction Algorithm
<OFFSET LOOP TC>
D6-D5-D4
TIME CONSTANT (TCCLK),
number of clock cycles
TIME CONSTANT, sec
(= TCCLK × 1/Fs)(1)
000
001
010
011
100
101
110
111
227
226
225
224
228
229
227
227
1.1
0.55
0.27
0.13
2.15
4.3
1.1
1.1
(1) Sampling frequency, Fs = 125 MSPS
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It is also possible to freeze the offset correction using the serial interface (<OFFSET LOOP FREEZE>). Once
frozen, the offset estimation becomes inactive and the last estimated value is used for correction every clock
cycle. Note that the offset correction is disabled by default after reset.
Figure 99 shows the time response of the offset correction algorithm, after it is enabled.
8260
8240
Device With
Offset Cancelled
8220
8200
8180
Offset Loop
Enabled Here
8160
Device With
Initial Offset
8140
8120
0
2
4
6
8
10
12
14
t − Time − s
G084
Figure 99. Time Response of Offset Correction
Gain Correction
ADS62P4X has ability to make fine corrections to the ADC channel gain. The corrections can be done in steps of
0.05 dB, up to a maximum of 0.5 dB, using the register bits (GAIN CORRECTION). Only positive corrections are
supported and the same correction applies to both the channels.
Table 21. Gain Correction Values
<GAIN CORRECTION>
D3-D2-D1-D0
AMOUNT OF CORRECTION,
dB
0000
0001
0
+0.05
+0.1
0010
0011
+0.15
+0.20
+0.25
+0.30
+0.35
+0.40
+0.45
+0.5
0100
0101
0110
0111
1000
1001
1010
Other combinations
Unused
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Decimation Filters
ADS62P4X includes option to decimate the ADC output data with in-built low pass, high pass or band pass
filters.
The decimation rate and type of filter can be selected using register bits (DECIMATION RATE) and
(DECIMATION FILTER TYPE). Decimation rates of 2, 4, or 8 are available and either low pass, high pass or
band pass filters can be selected (see Table 22). By default, the decimation filter is disabled – use register bit
<FILTER ENABLE> to enable it.
Table 22. Decimation Filter Modes
COMBINATION OF DECIMATION RATES AND FILTER TYPES
<DECIMATIO <FILTER
<DECIMATION
RATE>
N FILTER
FREQ
BAND>
COEFF
SELECT ENABLE>
>
<FILTER
DECIMATION
TYPE OF FILTER
Decimate by 2
Decimate by 4
In-built low-pass filter (pass band = 0 to Fs/4)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
1
0
1
0
1
0
0
0
0
0
0
1
1
1
1
1
1
In-built high-pass filter (pass band = Fs/4 to Fs/2)
In-built low-pass filter (pass band = 0 to Fs/8)
In-built 2nd band-pass filter (pass band = Fs/8 to Fs/4)
In-built 3rd band-pass filter (pass band = Fs/4 to 3Fs/8)
In-built last band-pass filter (pass band = 3Fs/8 to Fs/2)
Decimate by 2
Decimate by 4
Decimate by 8
No decimation
Custom filter (user programmable coefficients)
Custom filter (user programmable coefficients)
Custom filter (user programmable coefficients)
Custom filter (user programmable coefficients)
0
0
1
0
0
0
0
1
0
1
0
1
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
0
Decimation Filter Equation
The decimation filter is implemented as 24-tap FIR with symmetrical coefficients (each coefficient is 12-bit
signed). The filter equation is:
y(n) +
1
ǒ Ǔ
[h0 x(n) ) h1 x(n * 1) ) h2 x(n * 2) ) AAA ) h11 x(n * 11) ) h11 x(n * 12) ) AAA ) h1 x(n * 22) ) h0 x(n * 23)]
211
(3)
By setting the register bit <ODD TAP ENABLE> = 1, a 23-tap FIR is implemented:
y(n) +
1
ǒ Ǔx[h0 x(n) ) h1 x(n * 1) ) h2 x(n * 2) ) AAA ) h10 x(n * 10) ) h11 x(n * 11) ) h10 x(n * 12) ) AAA ) h1 x(n * 21) ) h0 x(n * 22)]
211
(4)
In the above equations,
h0, h1 …h11 are 12-bit signed representation of the coefficients,
x(n) is the input data sequence to the filter
y(n) is the filter output sequence
Pre-defined Coefficients
The in-built filter types (low pass, high pass, and band pass) use pre-defined coefficients. The frequency
response of the in-built filters is shown in Figure 100 and Figure 101.
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5
0
−5
Low Pass
High Pass
−10
−15
−20
−25
−30
−35
−40
−45
0.0
0.1
0.2
0.3
0.4
0.5
Normalized Frequency − f/f
S
G085
Figure 100. Decimate by 2 Filter Response
5
0
−5
−10
−15
−20
−25
−30
−35
−40
−45
Low Pass
High Pass
0.0
0.1
0.2
0.3
0.4
0.5
Normalized Frequency − f/f
S
G086
Figure 101. Decimate by 4 Filter Response
5
0
−5
−10
−15
−20
−25
−30
st
−35
−40
−45
1
Bandpass
0.3
nd
2
Bandpass
0.2
0.0
0.1
0.4
0.5
Normalized Frequency − f/f
S
G087
Figure 102. Decimate by 4 Band-Pass Response
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Table 23. Predefined Coefficients for Decimation by 2 Filters
COEFFICIENTS
DECIMATE BY 2
LOW-PASS FILTER
HIGH-PASS FILTER
h0
h1
23
-37
-6
-22
-65
-52
30
h2
h3
68
h4
-36
-61
35
66
h5
-35
-107
38
h6
h7
118
-100
-197
273
943
h8
202
-41
-644
1061
h9
h10
h11
Table 24. Predefined Coefficients for Decimation by 4 Filters
COEFFICIENTS
DECIMATE BY 4
LOW-PASS FILTER
1st BAND-PASS FILTER
2nd BAND-PASS FILTER
HIGH-PASS FILTER
h0
h1
-17
-50
71
-7
19
-34
-34
-101
43
32
-15
-95
22
h2
-47
127
73
h3
46
h4
24
58
-8
h5
-42
-100
-97
8
0
-28
-5
-81
106
-62
-97
310
-501
575
h6
86
h7
117
-190
-464
-113
526
-179
294
86
h8
h9
202
414
554
h10
h11
-563
352
Custom Filter Coefficients with Decimation
The filter coefficients can also be programmed by the user (custom). For custom coefficients, set the register bit
(FILTER COEFF SELECT) and load the coefficients (h0 to h11) in registers 1E to 2F using the serial interface
(Table 25) as:
Register content = 12-bit signed representation of [real coefficient value × 211]
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Custom Filter Coefficients without Decimation
The filter with custom coefficients can also be used with the decimation mode disabled. In this mode, the filter
implementation is 12-tap FIR:
y(n) +
1
ǒ Ǔx[h6 x(n) ) h7 x(n * 1) ) h8 x(n * 2) ) AAA ) h11 x(n * 5) ) h11 x(n * 6) ) AAA ) h7 x(n * 10) ) h6 x(n * 11)]
211
(5)
Table 25. Register Map of Custom Coefficients
A7–A0
D7
D6
D5
D4
D3
D2
D1
D0
(hex)
1E
1F
20
Coefficient h0 <7:0>
Coefficient h1 <3:0>
Coefficient h3 <3:0>
Coefficient h5 <3:0>
Coefficient h7 <3:0>
Coefficient h9 <3:0>
Coefficient h11 <3:0>
Coefficient h0 <11:8>
Coefficient h2 <11:8>
Coefficient h4 <11:8>
Coefficient h6 <11:8>
Coefficient h8 <11:8>
Coefficient h10 <11:8>
Coefficient h1 <11:4>
Coefficient h2 <7:0>
21
22
23
Coefficient h3 <11:4>
Coefficient h4 <7:0>
24
25
26
Coefficient h5 <11:4>
Coefficient h6 <7:0>
27
28
29
Coefficient h7 <11:4>
Coefficient h8 <7:0>
2A
2B
2C
2D
2E
2F
Coefficient h9 <11:4>
Coefficient h10 <7:0>
Coefficient h11 <11:4>
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BOARD DESIGN CONSIDERATIONS
Grounding
A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of
the board are cleanly partitioned. See the EVM User Guide (SLAU237) for details on layout and grounding.
Supply Decoupling
As the ADS62P4X already includes internal decoupling, minimal external decoupling can be used without loss in
performance. Note that decoupling capacitors can help filter external power supply noise, so the optimum
number of capacitors would depend on the actual application. The decoupling capacitors should be placed very
close to the converter supply pins.
It is recommended to use separate supplies for the analog and digital supply pins to isolate digital switching
noise from sensitive analog circuitry. In case only a single 3.3-V supply is available, it should be routed first to
AVDD. It can then be tapped and isolated with a ferrite bead (or inductor) with decoupling capacitor, before being
routed to DRVDD.
Exposed Thermal Pad
It is necessary to solder the exposed pad at the bottom of the package to a ground plane for best thermal
performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and QFN/SON
PCB Attachment (SLUA271).
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low frequency value.
Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs. This delay will be different across channels. The maximum variation is specified as
aperture delay variation (channel-channel).
Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains
at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate – The maximum sampling rate at which certified operation is given. All parametric
testing is performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate – The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly
1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL) – The INL is the deviation of the ADC's transfer function from a best fit line
determined by a least squares curve fit of that transfer function, measured in units of LSBs.
Gain Error – Gain error is the deviation of the ADC's actual input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input full-scale range. Gain error has two components: error due to
reference inaccuracy and error due to the channel. Both these errors are specified independently as EGREF and
EGCHAN
To a first order approximation, the total gain error will be ETOTAL ~ EGREF + EGCHAN
For example, if ETOTAL = ±0.5%, the full-scale input varies from (1-0.5/100)xFSideal to (1+0.5/100)xFSideal
.
.
.
Offset Error – The offset error is the difference, given in number of LSBs, between the ADC's actual average
idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV.
Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the
change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation
of the parameter across the TMIN to TMAX range by the difference TMAX–TMIN
.
Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN),
excluding the power at DC and the first nine harmonics.
P
P
s
SNR + 10Log10
N
(6)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power
of all the other spectral components including noise (PN) and distortion (PD), but excluding dc.
P
s
SINAD + 10Log10
P
) P
N
D
(7)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's
full-scale range.
Effective Number of Bits (ENOB) – The ENOB is a measure of a converter’s performance as compared to the
theoretical limit based on quantization noise.
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SINAD * 1.76
ENOB +
6.02
(8)
Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the
first nine harmonics (PD).
P
P
s
THD + 10Log10
N
(9)
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other
spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1
and f2) to the power of the worst spectral component at either frequency 2f1–f2 or 2f2–f1. IMD3 is either given in
units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to
full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range.
DC Power Supply Rejection Ratio (DC PSRR) – The DC PSSR is the ratio of the change in offset error to a
change in analog supply voltage. The DC PSRR is typically given in units of mV/V.
AC Power Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the
supply voltage by the ADC. If ΔVsup is the change in supply voltage and ΔVout is the resultant change of the
ADC output code (referred to the input), then
DVOUT
PSRR = 20Log10
(Expressed in dBc)
DVSUP
(10)
Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an
overload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive and
negative overload. The deviation of the first few samples after the overload (from their expected values) is noted.
Common Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input
common-mode by the ADC. If ΔVcm_in is the change in the common-mode voltage of the input pins and ΔVout
is the resultant change of the ADC output code (referred to the input), then
DVOUT
10
CMRR = 20Log
(Expressed in dBc)
DVCM
(11)
Cross-Talk (only for multi-channel ADC)– This is a measure of the internal coupling of a signal from adjacent
channel into the channel of interest. It is specified separately for coupling from the immediate neighboring
channel (near-channel) and for coupling from channel across the package (far-channel). It is usually measured
by applying a full-scale signal in the adjacent channel. Cross-talk is the ratio of the power of the coupling signal
(as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel
input. It is typically expressed in dBc.
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Mar-2008
PACKAGING INFORMATION
Orderable Device
ADS62P42IRGCR
ADS62P42IRGCRG4
ADS62P42IRGCT
ADS62P42IRGCTG4
ADS62P43IRGCR
ADS62P43IRGCRG4
ADS62P43IRGCT
ADS62P43IRGCTG4
ADS62P44IRGCR
ADS62P44IRGCRG4
ADS62P44IRGCT
ADS62P44IRGCTG4
ADS62P45IRGCR
ADS62P45IRGCRG4
ADS62P45IRGCT
ADS62P45IRGCTG4
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
VQFN
RGC
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Mar-2008
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jul-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
ADS62P42IRGCR
ADS62P42IRGCT
ADS62P43IRGCR
ADS62P43IRGCT
ADS62P44IRGCR
ADS62P44IRGCT
ADS62P45IRGCR
ADS62P45IRGCT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
64
64
64
64
64
64
64
64
2500
250
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
2500
250
2500
250
2500
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jul-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS62P42IRGCR
ADS62P42IRGCT
ADS62P43IRGCR
ADS62P43IRGCT
ADS62P44IRGCR
ADS62P44IRGCT
ADS62P45IRGCR
ADS62P45IRGCT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
64
64
64
64
64
64
64
64
2500
250
333.2
333.2
333.2
333.2
333.2
333.2
333.2
333.2
345.9
345.9
345.9
345.9
345.9
345.9
345.9
345.9
28.6
28.6
28.6
28.6
28.6
28.6
28.6
28.6
2500
250
2500
250
2500
250
Pack Materials-Page 2
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相关型号：
ADS62P48IRGC25
Dual Channel 14-/12-Bit, 250-/210-MSPS ADC With DDR LVDS and Parallel CMOS Outputs
TI
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