ADS7040 [TI]
超低功耗、超小尺寸 SAR ADC | 8 位 | 1MSPS | 单端;
| 型号： | ADS7040 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 超低功耗、超小尺寸 SAR ADC | 8 位 | 1MSPS | 单端 |
| 文件： | 总44页 (文件大小：1651K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS7040
ZHCSD01C –NOVEMBER 2014–REVISED DECEMBER 2015
ADS7040 超低功耗、超小尺寸、8 位、1MSPS、SAR ADC
1 特性
3 说明
1
•
业界第一款具有毫微瓦功耗的逐次逼近寄存器
(SAR) 模数转换器 (ADC)：
ADS7040 是一款 8 位、1MSPS、模数转换器
(ADC)。该器件支持较宽的模拟输入电压范围（1.65V
到 3.6V），并包含一个基于电容且内置采样保持电路
的逐次逼近寄存器 (SAR) ADC。串行外设接口 (SPI)
兼容串口由 CS 和 SCLK 信号控制。输入信号在 CS
下降沿进行采样，SCLK 用于转换和串行数据输出。此
器件支持宽范围的数字电源（1.65V 至 3.6V），可直
接连接到各类主机控制器。ADS7040 符合 JESD8-7A
标准的标称 DVDD 范围（1.65V 至
–
–
–
–
1MSPS 和 1.8V AVDD 时为 171µW
1MSPS 和 3V AVDD 时为 555µW
100kSPS 和 3V AVDD 时为 56µW
1kSPS 和 3V AVDD 时低于 1µW
•
业界最小的 SAR ADC：
采用 X2QFN-8 封装，封装尺寸为 2.25mm2
–
•
•
1MSPS 吞吐量且零延迟
1.95V）。
宽工作范围：
–
–
–
AVDD：1.65V 到 3.6V
ADS7040 采用 8 引脚微型引线 X2QFN 封装，额定工
作温度范围为 –40°C 至 125°C。此器件尺寸微小且功
耗极低，非常适合空间受限类电池供电 应用。
DVDD：1.65V 至 3.6V（与 AVDD 无关）
温度范围：-40°C 至 125°C
•
出色的性能：
器件信息(1)
–
–
8 位分辨率且无丟码 (NMC)
部件名称
封装
封装尺寸（标称值）
最大 ±0.5 最低有效位 (LSB) 的积分非线性
(INL)，最大 ±0.4 最低有效位 (LSB) 的差分非线
性 (DNL)
X2QFN (8)
1.50mm x 1.50mm
ADS7040
超薄小外形尺寸封装
(VSSOP)(8)
2.30mm x 2.00mm
–
–
49dB 的信噪比 (SNR)
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
-70dB 的总谐波失真 (THD)
•
•
•
•
单极输入范围：0V 至 AVDD
集成偏移校准
空白
空白
空白
串行外设接口 (SPI)™- 兼容串口：12MHz
符合 JESD8-7A 标准的数字 I/O
典型应用
2 应用
AVDD
AVDD used as
OPA_AVDD
•
•
•
•
•
•
•
•
•
低功耗数据采集
Reference for device
R
AVDD
+
电池供电类手持设备
液位传感器
超声波流量计
电机控制
AINP
+
VIN+
Device
œ
C
AINM
GND
OPA_AVSS
可穿戴健身器
便携式医疗设备
硬盘
RUG (8)
Actual Device Size
1.5 x 1.5 x 0.35(H) mm
血糖仪
注：ADS7040 比 0805（2012 公制）SMD
元件小。
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBAS676
ADS7040
ZHCSD01C –NOVEMBER 2014–REVISED DECEMBER 2015
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 19
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Applications ................................................ 22
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ..................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Timing Characteristics............................................... 7
6.7 Typical Characteristics.............................................. 8
Parameter Measurement Information ................ 13
7.1 Digital Voltage Levels ............................................. 13
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 15
9
10 Power-Supply Recommendations ..................... 30
10.1 AVDD and DVDD Supply Recommendations....... 30
10.2 Estimating Digital Power Consumption................. 30
10.3 Optimizing Power Consumed by the Device ........ 30
11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
11.2 Layout Example .................................................... 31
12 器件和文档支持 ..................................................... 32
12.1 文档支持................................................................ 32
12.2 社区资源................................................................ 32
12.3 商标....................................................................... 32
12.4 静电放电警告......................................................... 32
12.5 Glossary................................................................ 32
13 机械、封装和可订购信息....................................... 33
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (February 2015) to Revision C
Page
•
•
•
•
Updated Figure 1 ................................................................................................................................................................... 7
Changed Serial Interface section: changed last half of first paragraph, changed Figure 35 ............................................... 18
Changed Figure 38 .............................................................................................................................................................. 21
添加了社区资源部分 ............................................................................................................................................................. 32
Changes from Revision A (November 2014) to Revision B
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
已更改 宽工作电压范围 特性 要点：已将 AVDD 的值从 1.8V 改为 1.65V ............................................................................ 1
已更改 宽模拟输入电压范围下限至 1.65V（说明部分第 1 段） ............................................................................................. 1
Changed ESD Ratings table to latest standards ................................................................................................................... 5
Changed AVDD parameter minimum specification in Recommended Operating Conditions table to 1.65 V ....................... 5
Changed AVDD range in conditions of Electrical Characteristics table ................................................................................. 6
Changed INL and DNL parameter test conditions in Electrical Characteristics table ............................................................ 6
Changed maximum throughput rate parameter test conditions in Electrical Characteristics table ........................................ 6
Changed AVDD parameter minimum specification in Electrical Characteristics table........................................................... 6
Changed conditions for Timing Characteristics table: changed range of AVDD and added CLOAD condition........................ 7
Changed t D_CKDO parameter in Timing Characteristics table ................................................................................................ 7
Added fSCLK minimum specification to Timing Characteristics table ...................................................................................... 7
Changed titles of Figure 26 to Figure 30 ............................................................................................................................. 11
Changed Reference sub-section in Feature Description section ......................................................................................... 15
Changed range of second fCLK-CAL parameter description in Table 2 ................................................................................... 20
Changed range of second fCLK-CAL parameter description in Table 3 .................................................................................. 21
Changed Reference Circuit section in Application Information ............................................................................................ 24
Added last two sentences to AVDD and DVDD Supply Recommendations section .......................................................... 30
2
版权 © 2014–2015, Texas Instruments Incorporated
ADS7040
www.ti.com.cn
ZHCSD01C –NOVEMBER 2014–REVISED DECEMBER 2015
Changes from Original (November 2014) to Revision A
Page
•
已更改产品预览数据表............................................................................................................................................................ 1
Copyright © 2014–2015, Texas Instruments Incorporated
3
ADS7040
ZHCSD01C –NOVEMBER 2014–REVISED DECEMBER 2015
www.ti.com.cn
5 Pin Configuration and Functions
RUG Package
8-Pin X2QFN
Top View
DCU Package
8-Pin Leaded VSSOP
Top View
AINM
GND
1
2
3
4
8
7
6
5
DVDD
SCLK
SDO
CS
SDO
1
2
3
7
6
5
AINP
AVDD
GND
AVDD
AINP
AINM
SCLK
CS
DVDD
Pin Functions
PIN
NO.
NAME
AINM
RUG
DCU
I/O
DESCRIPTION
8
7
6
1
4
5
3
2
5
6
7
4
1
8
2
3
Analog input
Analog input
Supply
Analog signal input, negative
Analog signal input, positive
AINP
AVDD
CS
Analog power-supply input, also provides the reference voltage to the ADC
Digital input
Supply
Chip-select signal, active low
DVDD
GND
SCLK
SDO
Digital I/O supply voltage
Supply
Ground for power supply, all analog and digital signals are referred to this pin
Digital input
Digital output
Serial clock
Serial data out
4
Copyright © 2014–2015, Texas Instruments Incorporated
ADS7040
www.ti.com.cn
ZHCSD01C –NOVEMBER 2014–REVISED DECEMBER 2015
6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–60
MAX
3.9
UNIT
V
AVDD to GND
DVDD to GND
3.9
V
AINP to GND
AVDD + 0.3
0.3
V
AINM to GND
V
Digital input voltage to GND
Storage temperature, Tstg
DVDD + 0.3
150
V
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.65
1.65
–40
MAX
3.6
UNIT
AVDD
DVDD
TA
Analog supply voltage range
Digital supply voltage range
Operating free-air temperature
V
V
3.6
125
°C
6.4 Thermal Information
ADS7040
THERMAL METRIC(1)
RUG (X2QFN)
8 PINS
177.5
51.5
DCU (VSSOP)
8 PINS
235.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
79.8
76.7
117.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.0
8.9
ψJB
76.7
116.5
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2014–2015, Texas Instruments Incorporated
5
ADS7040
ZHCSD01C –NOVEMBER 2014–REVISED DECEMBER 2015
www.ti.com.cn
6.5 Electrical Characteristics
At TA = –40°C to 125°C, AVDD = 1.65 V to 3.6 V, DVDD = 1.65 V to 3.6 V, fSAMPLE = 1 MSPS, and VAINM = 0 V, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-scale input voltage span(1)
0
–0.1
–0.1
AVDD
AVDD + 0.1
0.1
V
V
AINP to GND
AINM to GND
Absolute input
voltage range
CS
Sampling capacitance
15
8
pF
SYSTEM PERFORMANCE
Resolution
Bits
Bits
LSB(2)
NMC
INL
No missing codes
8
–0.5
–0.4
Integral nonlinearity
Differential nonlinearity
Offset error
AVDD = 1.8 V to 3.6 V
±0.25
±0.2
±0.5
±25
0.5
0.4
DNL
EO
AVDD = 1.8 V to 3.6 V
LSB
LSB
dVOS/dT
EG
Offset error drift with temperature
Gain error
ppm/°C
%FS
±0.2
±25
Gain error drift with temperature
ppm/°C
SAMPLING DYNAMICS
tACQ Acquisition time
Maximum throughput rate
DYNAMIC CHARACTERISTICS
275
48.5
48.5
ns
12-MHz SCLK, AVDD = 1.65 V to 3.6 V
1
MHz
fIN = 2 kHz, AVDD = 3 V
fIN = 2 kHz, AVDD = 1.8 V
fIN = 2 kHz, AVDD = 3 V
fIN = 2 kHz, AVDD = 3 V
fIN = 2 kHz, AVDD = 1.8 V
fIN = 2 kHz, AVDD = 3 V
At –3 dB, AVDD = 3 V
49
49
SNR
Signal-to-noise ratio(3)
dB
dB
dB
THD
Total harmonic distortion(3)(4)
Signal-to-noise and distortion(3)
–70
49
SINAD
49
SFDR
BW(fp)
Spurious-free dynamic range(3)
Full-power bandwidth
75
dB
25
MHz
DIGITAL INPUT/OUTPUT (CMOS Logic Family)
VIH
VIL
High-level input voltage(5)
Low-level input voltage(5)
0.65 DVDD
DVDD + 0.3
0.35 DVDD
DVDD
V
V
–0.3
At Isource = 500 µA
At Isource = 2 mA
At Isink = 500 µA
At Isink = 2 mA
0.8 DVDD
VOH
High-level output voltage(5)
Low-level output voltage(5)
V
V
DVDD – 0.45
DVDD
0
0
0.2 DVDD
0.45
VOL
POWER-SUPPLY REQUIREMENTS
AVDD
DVDD
Analog supply voltage
1.65
1.65
3
3
3.6
3.6
185
23
V
V
Digital I/O supply voltage
At 1 MSPS with AVDD = 3 V
At 100 kSPS with AVDD = 3 V
At 1 MSPS with AVDD = 1.8 V
At 1 MSPS with AVDD = 3 V
At 100 kSPS with AVDD = 3 V
At 1 MSPS with AVDD = 1.8 V
IAVDD
Analog supply current
Power dissipation
µA
95
555
56
PD
µW
171
(1) Ideal input span; does not include gain or offset error.
(2) LSB means least significant bit.
(3) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale,
unless otherwise specified.
(4) Calculated on the first nine harmonics of the input frequency.
(5) Digital voltage levels comply with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V. See the Digital Voltage Levels section for
more details.
6
Copyright © 2014–2015, Texas Instruments Incorporated
ADS7040
www.ti.com.cn
ZHCSD01C –NOVEMBER 2014–REVISED DECEMBER 2015
6.6 Timing Characteristics
All specifications are at TA = –40°C to 125°C, AVDD = 1.65 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and CLOAD on SDO = 20 pF,
unless otherwise specified.
MIN
TYP
MAX
UNIT
TIMING SPECIFICATIONS
fTHROUGHPUT Throughput
tCYCLE
1
MSPS
µs
Cycle time
1
tCONV
Conversion time
8.5 × tSCLK + tSU_CSCK
10
ns
tDV_CSDO
Delay time: CS falling to data enable
ns
Delay time: SCLK falling to (next) data valid on DOUT,
AVDD = 1.8 V to 3.6 V
30
50
ns
tD_CKDO
Delay time: SCLK falling to (next) data valid on DOUT,
AVDD = 1.65 V to 1.8 V
ns
ns
tDZ_CSDO
Delay time: CS rising to DOUT going to 3-state
5
TIMING REQUIREMENTS
tACQ
Acquisition time
275
0.016
83.33
0.45
0.45
60
ns
MHz
ns
fSCLK
SCLK frequency
12
tSCLK
SCLK period
tPH_CK
tPL_CK
tPH_CS
tSU_CSCK
tD_CKCS
SCLK high time
0.55
0.55
tSCLK
tSCLK
ns
SCLK low time
CS high time
Setup time: CS falling to SCLK falling
Delay time: last SCLK falling to CS rising
15
ns
10
ns
Sample
N
Sample
N+1
tCYCLE
tCONV
tACQ
tPH_CS
CS
tSU_CSCK
tPL_CK
tD_CKCS
tSCLK
tPH_CK
1
2
3
4
5
6
7
8
9
10
SCLK
tD_CKDO
tDV_CSDO
tDZ_CSDO
D3
D2
D1
D5
D4
D0
0
0
D7
D6
SDO
Data for Sample N
Figure 1. Timing Diagram
Copyright © 2014–2015, Texas Instruments Incorporated
7
ADS7040
ZHCSD01C –NOVEMBER 2014–REVISED DECEMBER 2015
www.ti.com.cn
6.7 Typical Characteristics
At TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
0
œ20
0
œ20
œ40
œ40
œ60
œ60
œ80
œ80
œ100
œ120
œ140
œ100
œ120
œ140
0
100
200
300
400
500
0
100
200
300
400
500
C002
Input Frequency (kHz)
Input Frequency (kHz)
C001
SNR = 49.85 dB
THD = –68.69 dB
fIN = 2 kHz
SNR = 49.34 dB
THD = –63.31 dB
fIN = 250 kHz
Number of samples = 16384
Number of samples = 16384
Figure 2. Typical FFT
Figure 3. Typical FFT
52
50.5
49
52
50.5
49
SNR
SNR
SINAD
SINAD
47.5
46
47.5
46
44.5
43
44.5
43
41.5
41.5
40
40
26
59
92
125
2
33
64
95
126
157
188
219
250
œ40
œ7
Free-Air Temperature (oC)
Input Frequency (kHz)
C003
C004
fIN = 2 kHz
Figure 4. SNR and SINAD vs Free-Air Temperature
Figure 5. SNR and SINAD vs Input Frequency
52
œ65
œ67
œ69
œ71
œ73
œ75
SNR
50.5
49
SINAD
47.5
46
44.5
43
41.5
40
1.8
2.1
2.4
2.7
3
3.3
3.6
26
59
92
125
œ40
œ7
Reference Voltage (V)
Free-Air Temperature (oC)
C006
C005
Figure 6. SNR and SINAD vs Reference Voltage (AVDD)
Figure 7. THD vs Free-Air Temperature
8
Copyright © 2014–2015, Texas Instruments Incorporated
ADS7040
www.ti.com.cn
ZHCSD01C –NOVEMBER 2014–REVISED DECEMBER 2015
Typical Characteristics (continued)
At TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
œ65
œ70
œ75
œ80
œ85
œ60
œ63
œ66
œ69
œ72
œ75
1.8
2.1
2.4
2.7
3
3.3
3.6
0
50
100
150
200
250
C008
Reference Voltage (V)
Input Frequency (kHz)
C010
Figure 8. THD vs Input Frequency
Figure 9. THD vs Reference Voltage
80
78
76
74
72
70
80
77
74
71
68
65
26
59
92
125
0
50
100
150
200
250
œ40
œ7
Free-Air Temperature (oC)
Input Frequency (kHz)
C009
C007
Figure 10. SFDR vs Free-Air Temperature
Figure 11. SFDR vs Input Frequency
90
86
82
78
74
70
70000
60000
50000
40000
30000
20000
10000
0
1.8
2.1
2.4
2.7
3
3.3
3.6
128
129
C012
Reference Voltage (V)
Code
C011
Figure 12. SFDR vs Reference Voltage
Figure 13. DC Input Histogram
Copyright © 2014–2015, Texas Instruments Incorporated
9
ADS7040
ZHCSD01C –NOVEMBER 2014–REVISED DECEMBER 2015
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
2
1.5
1
0.5
Calibrated
0
0.5
0
-0.5
-1
Calibrated
-0.5
-1
-1.5
-2
Un-Calibrated
-1.5
-2
Un-Calibrated
26
59
92
125
1.8
1.8
0
2.1
2.4
2.7
3
3.3
3.6
œ40
œ7
Free-Air Temperature (oC)
Reference Voltage (V)
C013
C014
Figure 14. Offset vs Free-Air Temperature
Figure 15. Offset vs Reference Voltage
0.2
0.1
0
0.2
0.1
0
-0.1
-0.2
-0.1
-0.2
26
59
92
125
2.1
2.4
2.7
3
3.3
3.6
œ40
œ7
Free-Air Temperature (oC)
Reference Voltage (V)
C016
C015
Figure 16. Gain Error vs Free-Air Temperature
Figure 17. Gain Error vs Reference Voltage
0.5
0.3
0.5
0.3
0.1
0.1
-0.1
-0.3
-0.5
-0.1
-0.3
-0.5
0
64
128
192
256
64
128
192
256
C018
Code
Code
C017
AVDD = 3 V
AVDD = 3 V
Figure 18. Typical DNL
Figure 19. Typical INL
10
Copyright © 2014–2015, Texas Instruments Incorporated
ADS7040
www.ti.com.cn
ZHCSD01C –NOVEMBER 2014–REVISED DECEMBER 2015
Typical Characteristics (continued)
At TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
0.5
0.5
0.3
0.3
0.1
0.1
-0.1
-0.3
-0.5
-0.1
-0.3
-0.5
0
64
128
192
256
0
64
128
192
256
C020
Code
Code
C019
AVDD = 1.8 V
AVDD = 1.8 V
Figure 20. Typical INL
Figure 21. Typical INL
0.5
0.3
0.5
0.3
Maximum
Minimum
0.1
0.1
Maximum
Minimum
-0.1
-0.3
-0.1
-0.3
-0.5
-0.5
26
59
92
125
1.8
2.1
2.4
2.7
3
3.3
3.6
œ40
œ7
Free-Air Temperature (oC)
Reference Voltage (V)
C021
C022
Figure 22. DNL vs Free-Air Temperature
Figure 23. DNL vs Reference Voltage (AVDD)
0.5
0.3
0.5
0.3
Maximum
Minimum
Maximum
Minimum
0.1
0.1
-0.1
-0.3
-0.5
-0.1
-0.3
-0.5
26
59
92
125
1.8
2.1
2.4
2.7
3
3.3
3.6
œ40
œ7
Free-Air Temperature (oC)
C023
Reference Voltage (V)
C024
Figure 24. INL vs Free-Air Temperature
Figure 25. INL vs Reference Voltage (AVDD)
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS, unless otherwise noted.
185
180
175
170
165
180
150
120
90
60
30
0
26
59
92
125
0
200
400
600
800
1000
œ40
œ7
Free-Air Temperature (oC)
Throughput (Ksps)
C026
C025
AVDD = 3 V
Figure 27. AVDD Supply Current vs Throughput
Figure 26. AVDD Supply Current vs Free-Air Temperature
100
230
210
190
170
150
130
110
90
80
60
40
20
0
0
200
400
600
800
1000
1.8
2.1
2.4
2.7
3
3.3
3.6
C028
Throughput (Ksps)
Supply Voltage (V)
C027
AVDD = 1.8 V
Figure 28. AVDD Supply Current vs Throughput
Figure 29. AVDD Supply Current vs AVDD Voltage
70
60
50
40
30
20
10
0
0
25
50
75
100
125
Free-Air Temperature (oC)
C029
Figure 30. AVDD Static Current vs Free-Air Temperature
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7 Parameter Measurement Information
7.1 Digital Voltage Levels
The device complies with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V. Figure 31 shows voltage
levels for the digital input and output pins.
Digital Output
DVDD
VOH
DVDD-0.45V
SDO
0.45V
VOL
0V
ISource= 2 mA, ISink = 2 mA,
DVDD = 1.65 V to 1.95 V
Digital Inputs
DVDD + 0.3V
VIH
0.65DVDD
CS
SCLK
0.35DVDD
VIL
DVDD = 1.65 V to 1.95 V
-0.3V
Figure 31. Digital Voltage Levels as per the JESD8-7A Standard
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8 Detailed Description
8.1 Overview
The ADS7040 is an ultralow-power, ultra-small analog-to-digital converter (ADC) that supports a wide analog
input range. The analog input range for the device is defined by the AVDD supply voltage. The device samples
the input voltage across the AINP and AINM pins on the CS falling edge and starts the conversion. The clock
provided on the SCLK pin is used for conversion and data transfer. During conversions, both the AINP and AINM
pins are disconnected from the sampling circuit. After the conversion completes, the sampling capacitors are
reconnected across the AINP and AINM pins and the ADS7040 enters acquisition phase.
The device has an internal offset calibration. The offset calibration can be initiated by the user either on power-up
or during normal operation; see the Offset Calibration section for more details.
The device also provides a simple serial interface to the host controller and operates over a wide range of digital
power supplies. The ADS7040 requires only a 12-MHz SCLK for supporting a throughput of 1 MSPS. The digital
interface also complies with the JESD8-7A (normal range) standard. The Functional Block Diagram section
provides a block diagram of the device.
8.2 Functional Block Diagram
DVDD
AVDD
GND
Offset
Calibration
AINP
AINM
CS
SCLK
SDO
CDAC
Comparator
Serial
Interface
SAR
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8.3 Feature Description
8.3.1 Reference
The device uses the analog supply voltage (AVDD) as a reference, as shown in Figure 32. TI recommends
decoupling the AVDD pin with a 1-µF, low equivalent series resistance (ESR) ceramic capacitor. The minimum
capacitor value required for AVDD is 200 nF. The AVDD pin functions as a switched capacitor load to the source
powering AVDD. The decoupling capacitor provides the instantaneous charge required by the internal circuit and
helps in maintaining a stable dc voltage on the AVDD pin. TI recommends powering the AVDD pin with a low
output impedance and low-noise regulator (such as the TPS79101).
1µF
DVDD
AVDD
GND
Offset
Calibration
AINP
AINM
CS
SCLK
SDO
CDAC
Comparator
Serial
Interface
SAR
Figure 32. Reference for the Device
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Feature Description (continued)
8.3.2 Analog Input
The device supports single-ended analog inputs. The ADC samples the difference between AINP and AINM and
converts for this voltage. The device is capable of accepting a signal from –100 mV to 100 mV on the AINM input
and is useful in systems where the sensor or signal-conditioning block is far from the ADC. In such a scenario,
there can be a difference between the ground potential of the sensor or signal conditioner and the ADC ground.
In such cases, use separate wires to connect the ground of the sensor or signal conditioner to the AINM pin. The
AINP input is capable of accepting signals from 0 V to AVDD. Figure 33 represents the equivalent analog input
circuits for the sampling stage. The device has a low-pass filter followed by the sampling switch and sampling
capacitor. The sampling switch is represented by an Rs(typically 50 Ω) resistor in series with an ideal switch and
Cs (typically 15 pF) is the sampling capacitor. The ESD diodes are connected from both analog inputs to AVDD
and ground.
AVDD
50 ꢀ
Rs
AINP
CS
10 pF
AVDD
Rs
50 ꢀ
AINM
CS
Figure 33. Equivalent Input Circuit for the Sampling Stage
The analog input full-scale range (FSR) is equal to the reference voltage of the ADC. The reference voltage for
the device is equal to the analog supply voltage (AVDD). Thus, the device FSR can be determined by
Equation 1:
FSR = VREF = AVDD
(1)
8.3.3 ADC Transfer Function
The device output is in straight binary format. The device resolution for a single-ended input can be computed by
Equation 2:
1 LSB = VREF / 2N
where:
•
•
VREF = AVDD and
N = 8
(2)
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Feature Description (continued)
Figure 34 and Table 1 show the ideal transfer characteristics for the device.
PFSC
MC + 1
MC
NFSC+1
NFSC
VIN
V
REF
V
REF
VREF œ 1 LSB
+ 1LSB
1 LSB
2
2
Single-Ended Analog Input
(AINP œ AINM)
Figure 34. Ideal Transfer Characteristics
Table 1. Transfer Characteristics
INPUT VOLTAGE (AINP – AINM)
≤1 LSB
CODE
NFSC
DESCRIPTION
IDEAL OUTPUT CODE
Negative full-scale code
00
01
80
81
FF
1 LSB to 2 LSBs
NFSC + 1
MC
—
Mid code
(VREF / 2) to (VREF / 2) + 1 LSB
(VREF / 2) + 1 LSB to (VREF / 2) + 2 LSBs
≥ VREF – 1 LSB
MC + 1
PFSC
—
Positive full-scale code
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8.3.4 Serial Interface
The device supports a simple, SPI-compatible interface to the external host. The CS signal defines one
conversion and serial transfer frame. A frame starts with a CS falling edge and ends with a CS rising edge. The
SDO pin outputs the ADC conversion results. Figure 35 shows a detailed timing diagram for the serial interface.
A minimum delay of tSU_CSCK must elapse between the CS falling edge and the first SCLK falling edge. The
device uses the clock provided on the SCLK pin for conversion and data transfer. The conversion result is
available on the SDO pin with the first two bits set to 0, followed by 8 bits of the conversion result. The first zero
is launched on the SDO pin on the CS falling edge. Subsequent bits (starting with another 0 followed by the
conversion result) are launched on the SDO pin on subsequent SCLK falling edges. The SDO output remains
low after 10 SCLKs. A CS rising edge ends the frame and brings the serial data bus to 3-state. For acquisition of
the next sample, a minimum time of tACQ must be provided after the conversion of the current sample is
completed. For details on timing specifications, see the Timing Characteristics table.
The device initiates an offset calibration on the first CS falling edge after power-up and the SDO output remains
low during the first serial transfer frame after power-up. For further details, refer to the Offset Calibration section.
Sample
N+1
Sample
N
tCYCLE
tCONV
tACQ
tSU_CSCK
CS
1
0
2
3
4
5
6
7
8
9
10
SCLK
D4
D3
0
D6
D5
D2
D1
D0
D7
SDO
Data for Sample N
Figure 35. Serial Interface Timing Diagram
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8.4 Device Functional Modes
8.4.1 Offset Calibration
The ADS7040 includes a feature to calibrate the device internal offset. During offset calibration, the analog input
pins (AINP and AINM) are disconnected from the sampling stage. The device includes an internal offset
calibration register (OCR) that stores the offset calibration result. The OCR is an internal register and cannot be
accessed by the user through the serial interface. The OCR is reset to zero on power-up. Therefore, TI
recommends calibrating the offset on power-up to bring the offset within the specified limits. If the operating
temperature or analog supply voltage reflect a significant change, the offset can be recalibrated during normal
operation. Figure 36 shows the offset calibration process.
Normal Operation
With Uncalibarted
Data Capture(1)
offset
Device
Power Up
Data Capture(1)
Normal Operation
With Calibarted
offset
Calibration during Normal Operation(2)
(1) See the Timing Characteristics section for timing specifications.
(2) See the Offset Calibration During Normal Operation section for details.
(3) See the Offset Calibration on Power-Up section for details.
(4) The power recycle on the AVDD supply is required to reset the offset calibration and to bring the device to a power-up
state.
Figure 36. Offset Calibration
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Device Functional Modes (continued)
8.4.1.1 Offset Calibration on Power-Up
The device initiates offset calibration on the first CS falling edge after power-up and calibration completes if the
CS pin remains low for at least 16 SCLK falling edges after the first CS falling edge. The SDO output remains
low during calibration. The minimum acquisition time must be provided after calibration for acquiring the first
sample. If the device is not provided with at least 16 SCLKs during the first serial transfer frame after power-up,
the OCR is not updated. Table 2 provides the timing parameters for offset calibration on power-up.
For subsequent samples, the device adjusts the conversion results with the value stored in the OCR. The
conversion result adjusted with the value stored in OCR is provided by the device on the SDO output. Figure 37
shows the timing diagram for offset calibration on power-up.
Table 2. Offset Calibration on Power-Up
MIN
TYP
MAX
12
UNIT
MHz
MHz
ns
fCLK-CAL
fCLK-CAL
SCLK frequency for calibration for 1.8 V < AVDD < 3.6 V
SCLK frequency for calibration for 1.65 V < AVDD < 2.25 V
12
tPOWERUP-CAL Calibration time at power-up
15 tSCLK
275
tACQ
Acquisition time
ns
tPH_CS
tSU_CSCK
tD_CKCS
CS high time
tACQ
15
ns
Setup time: CS falling to SCLK falling
Delay time: last SCLK falling to CS rising
ns
10
ns
Start
Power-up
Calibration
Sample
#1
tPH_CS
tACQ
tPOWERUP-CAL
CS
tD_CKCS
tSU_CSCK
1
2
15
16
SCLK(fCLK-CAL
)
SDO
Figure 37. Offset Calibration on Power-Up Timing Diagram
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8.4.1.2 Offset Calibration During Normal Operation
Offset calibration can be done during normal device operation if at least 32 SCLK falling edges are provided in
one serial transfer frame. During the first 10 SCLKs, the device converts the sample acquired on the CS falling
edge and provides data on the SDO output. The device initiates the offset calibration on the 17th SCLK falling
edge and calibration completes on the 32nd SCLK falling edge. The SDO output remains low after the 10th
SCLK falling edge and SDO goes to 3-state after CS goes high. If the device is provided with less than 32
SCLKs during a serial transfer frame, the OCR is not updated. Table 3 provides the timing parameters for offset
calibration during normal operation.
For subsequent samples, the device adjusts the conversion results with the value stored in the OCR. The
conversion result adjusted with the value stored in the OCR is provided by the device on the SDO output.
Figure 38 shows the timing diagram for offset calibration during normal operation.
Table 3. Offset Calibration During Normal Operation
MIN
TYP
MAX
12
UNIT
MHz
MHz
ns
fCLK-CAL
fCLK-CAL
tCAL
SCLK frequency for calibration for 1.8 V < AVDD < 3.6 V
SCLK frequency for calibration for 1.65 V < AVDD < 2.25 V
Calibration time during normal operation
Acquisition time
12
15 tSCLK
275
tACQ
ns
tPH_CS
tSU_CSCK
tD_CKCS
CS high time
tACQ
15
ns
Setup time: CS falling to SCLK falling
Delay time: last SCLK falling to CS rising
ns
10
ns
Sample
N+1
Sample
N
tPH_CS
tACQ
tCONV
tCAL
CS
tSU_CSCK
tD_CKCS
16
18
32
1
0
2
3
4
9
10
17
31
SCLK(fCLK-CAL
)
0
D7
D6
D1
SDO
D0
Data for Sample N
Figure 38. Offset Calibration During Normal Operation Timing Diagram
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The two primary circuits required to maximize the performance of a high-precision, successive approximation
register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This
section details some general principles for designing the input driver circuit, reference driver circuit, and provides
some application circuits designed for the ADS7040.
9.2 Typical Applications
9.2.1 Single-Supply DAQ with the ADS7040
AVDD
AVDD
OPA314
AVDD
200 ꢀ
VIN+
+
AINP
AINM
+
Device
1.5 nF
œ
GND
Input Driver
Device: 8-Bit, 1-MSPS,
Single-Ended Input
Figure 39. DAQ Circuit: Single-Supply DAQ
9.2.1.1 Design Requirements
The goal of this application is to design a single-supply digital acquisition (DAQ) circuit based on the ADS7040
with SNR greater than 49 dB and THD less than –70 dB for input frequencies of 5 kHz at a throughput of
1 MSPS.
9.2.1.2 Detailed Design Procedure
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and an
antialiasing filter. Careful design of the front-end circuit is critical to meet the linearity and noise performance of a
high-precision ADC.
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Typical Applications (continued)
9.2.1.2.1 Antialiasing Filter
Converting analog-to-digital signals requires sampling an input signal at a rate greater than or equal to the
Nyquist rate. Any higher frequency content in the input signal beyond half the sampling frequency is digitized and
folded back into the low-frequency spectrum. This process is called aliasing. Therefore, an external, antialiasing
filter must be used to remove the harmonic content from the input signal before being sampled by the ADC. An
antialiasing filter is designed as a low-pass RC filter, for which the 3-dB bandwidth is optimized for noise,
response time, and throughput. For dc signals with fast transients (including multiplexed input signals), a high-
bandwidth filter is designed to allow accurately settling the signal at the ADC inputs during the small acquisition
time window. Figure 40 provides the equation for determining the bandwidth of the antialiasing filter.
AVDD
AVDD
RFLT
AINP
1
CFLT
f-3dB
=
Device
2p ì R ì C
FLT
FLT
AINM
GND
Figure 40. Antialiasing Filter
For ac signals, the filter bandwidth must be kept low to band limit the noise fed into the ADC input, thereby
increasing the signal-to-noise ratio (SNR) of the system. Besides filtering the noise from the front-end drive
circuitry, the RC filter also helps attenuate the sampling charge injection from the switched-capacitor input stage
of the ADC. A filter capacitor, CFLT, is connected across the ADC inputs. This capacitor helps reduce the
sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold
capacitors during the acquisition process. As a rule of thumb, the value of this capacitor is at least 20 times the
specified value of the ADC sampling capacitance. For this device, the input sampling capacitance is equal to
15 pF. Thus, the value of CFLT is greater than 300 pF. Select a COG- or NPO-type capacitor because these
capacitor types have a high-Q, low-temperature coefficient, and stable electrical characteristics under varying
voltages, frequency, and time.
Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of
the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a
result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance,
input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability
and distortion of the design.
The input amplifier bandwidth is typically much higher than the cutoff frequency of the antialiasing filter. Thus, TI
strongly recommends performing a SPICE simulation to confirm that the amplifier has more than 40° phase
margin with the selected filter. Simulation is critical because even with high-bandwidth amplifiers, some amplifiers
can require more bandwidth than others to drive similar filters.
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Typical Applications (continued)
9.2.1.2.2 Input Amplifier Selection
Selection criteria for the input amplifiers is highly dependent on the input signal type and the performance goals
of the data acquisition system. Some key amplifier specifications to consider when selecting an appropriate
amplifier to drive the inputs of the ADC are:
•
Small-signal bandwidth: Select the small-signal bandwidth of the input amplifiers to be high enough to settle
the input signal in the acquisition time of the ADC. Higher bandwidth reduces the closed-loop output
impedance of the amplifier, thus allowing the amplifier to more easily drive the low cutoff frequency RC filter
at the ADC inputs. Higher bandwidth also minimizes the harmonic distortion at higher input frequencies. In
order to maintain the overall stability of the input driver circuit, the select the amplifier bandwidth as described
in Equation 3.
1
GBW í 4ì
2ŒìRFLT ì
CFLT
where:
•
GBW = unity gain bandwidth
(3)
•
Noise: Noise contribution of the front-end amplifiers must be low enough to prevent any degradation in SNR
performance of the system. As a rule of thumb, to ensure that the noise performance of the data acquisition
system is not limited by the front-end circuit, keep the total noise contribution from the front-end circuit below
20% of the input-referred noise of the ADC. Noise from the input driver circuit is band limited by designing a
low cutoff frequency RC filter, as explained in Equation 4.
SNR(dB)
-
(
)
2
1
5
VREF
2 2
V1 f _AMP_PP
Œ
20
NG ì
+e2n_RMS ì ìf
Ç
ì
ì 10
-3dB
6.6
2
where:
•
•
•
•
V1/f_AMP_PP is the peak-to-peak flicker noise in µVRMS,
en_RMS is the amplifier broadband noise,
f–3dB is the –3-dB bandwidth of the RC filter, and
NG is the noise gain of the front-end circuit, which is equal to 1 in the buffer configuration.
(4)
•
Settling time: For dc signals with fast transients that are common in a multiplexed application, the input signal
must settle to the desired accuracy at the inputs of the ADC during the acquisition time window. This
condition is critical to maintain the overall linearity performance of the ADC. Typically, the amplifier data
sheets specify the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the
desired accuracy. Therefore, always verify the settling behavior of the input driver with TINA™-SPICE
simulations before selecting the amplifier.
The OPA314 is selected for this application for its rail-to-rail input and output swing, low-noise (14 nV/√Hz), and
low-power (150 µA) performance to support a single-supply data acquisition circuit.
9.2.1.2.3 Reference Circuit
The analog supply voltage of the device is also used as a voltage reference for conversion. TI recommends
decoupling the AVDD pin with a 1-µF, low-ESR ceramic capacitor. The minimum capacitor value required for
AVDD is 200 nF.
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Typical Applications (continued)
9.2.1.3 Application Curve
Figure 41 shows the FFT plot for the ADS7040 with a 5-kHz input frequency used for the circuit in Figure 39.
0
œ20
œ40
œ60
œ80
œ100
œ120
œ140
0
100
200
300
400
500
C031
Input Frequency (kHz)
SNR = 49.7 dB
THD = –70.5 dB
SINAD = 49.6 dB
Number of samples = 32768
Figure 41. Test Results for the ADS7040 and OPA314 for a 5-kHz Input
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Typical Applications (continued)
9.2.2 DAQ Circuit with the ADS7040 for Maximum SINAD
AVDD
OPA_AVDD
25 ꢀ
OPA835
AVDD
+
AINP
AINM
+
VIN+
œ
Device
1.5 nF
GND
OPA_AVSS
Device: 8-Bit, 1-MSPS,
Single-Ended Input
Input Driver
Figure 42. ADS7040 DAQ Circuit: Maximum SINAD for Input Frequencies up to 250 kHz
9.2.2.1 Design Requirements
The goal of this application is to design a data acquisition circuit based on the ADS7040 with SINAD greater than
49 dB for input frequencies up to 250 kHz.
9.2.2.2 Detailed Design Procedure
To achieve a SINAD of 49 dB, the operational amplifier must have high bandwidth in order to settle the input
signal within the acquisition time of the ADC. The operational amplifier must have low noise to keep the total
system noise below 20% of the input-referred noise of the ADC. For the application circuit shown in Figure 42,
the OPA835 is selected for its high bandwidth (56 MHz) and low noise (9.3 nV/√Hz).
For a step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation
results, and test results, refer to TI Precision Design TIPD168, Three 12-Bit Data Acquisition
Reference Designs Optimized for Low Power and Ultra-Small Form Factor (TIDU390).
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9.2.2.3 Application Curves
Figure 43 shows the FFT plot for the ADS7040 with a 2-kHz input frequency used for the circuit in Figure 42.
Figure 44 shows the FFT plot for the ADS7040 with a 250-kHz input frequency used for the circuit in Figure 42.
0
œ20
0
œ20
œ40
œ40
œ60
œ60
œ80
œ80
œ100
œ120
œ140
œ100
œ120
œ140
0
100
200
300
400
500
0
100
200
300
400
500
Input Frequency (kHz)
Input Frequency (kHz)
C002
C001
SNR = 49.85 dB
THD = –68.7 dB
SINAD = 49.8 dB
SNR = 49.9 dB
THD = –64.1 dB
SINAD = 49.7 dB
Number of samples = 32768
Number of samples = 32768
Figure 43. Test Results for the ADS7040 and OPA835 for a
2-kHz Input
Figure 44. Test Results for the ADS7040 and OPA835 for a
250-kHz Input
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9.2.3 8-Bit, 10-kSPS DAQ Circuit Optimized for DC Sensor Measurements
AVDD
Sensor
ROUT
AVDD
AINP
Device
+
AINM
CFLT
œ
GND
Figure 45. Interfacing the Device Directly with Sensors
In applications where the input is very slow moving and the overall system ENOB is not a critical parameter, a
DAQ circuit can be designed without the input driver for the ADC . This type of a use case is of particular interest
for applications in which the primary goal is to achieve the absolute lowest power possible. Typical applications
that fall into this category are low-power sensor applications (such as temperature, pressure, humidity, gas, and
chemical).
9.2.3.1 Design Requirements
For this design example, use the parameters listed in Table 4 as the input parameters.
Table 4. Design Parameters
DESIGN PARAMETER
Throughput
GOAL VALUE
10 kSPS
48.5 dB
65dB
SNR at 100 Hz
THD at 100 Hz
SINAD at 100 Hz
ENOB
48 dB
7.5
Power
10 µW
9.2.3.2 Detailed Design Procedure
The ADS7040 can be directly interfaced with sensors at lower throughputs without the need of an amplifier
buffer. The analog input source drive must be capable of driving the switched capacitor load of a SAR ADC and
settling the analog input signal within the acquisition time of the SAR ADC. However, the output impedance of
the sensor must be taken into account when interfacing a SAR ADC directly with sensors. Drive the analog input
of the SAR ADC with a low impedance source. The input signal requires more acquisition time to settle to the
desired accuracy because of the higher output impedance of the sensor. The simplified circuit for a sensor as a
voltage source with output impedance (ROUT) is shown in Figure 45.
The acquisition time of a SAR ADC (such as the ADS7040) can be increased by reducing throughput in the
following ways:
1. Reducing the SCLK frequency to reduce the throughput, or
2. Keeping the SCLK fixed at the highest permissible value (that is, 12 MHz for the device) and increasing the
CS high time.
28
Copyright © 2014–2015, Texas Instruments Incorporated
ADS7040
www.ti.com.cn
ZHCSD01C –NOVEMBER 2014–REVISED DECEMBER 2015
Table 5 lists the acquisition time for the above two cases for a throughput of 100 kSPS. Clearly, case 2 provides
more acquisition time for the input signal to settle.
Table 5. Acquisition Time with Different SCLK Frequencies
CONVERSION TIME
(= 8.5 × tSCLK + tSU_CSCK
ACQUISITION TIME
CASE
SCLK
tcycle
)
(= tcycle – tconv
)
1
2
1.2 MHz
12 MHz
10 µs
10 µs
7.233 µs
2.767 µs
0.7233 µs
9.2767 µs
For a step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation
results, and test results, refer to TI Precision Design TIPD168, Three 12-Bit Data Acquisition
Reference Designs Optimized for Low Power and Ultra-Small Form Factor (TIDU390).
9.2.3.3 Application Curve
When the output impedance of the sensor increases, the time required for the input signal to settle increases and
the performance of the SAR ADC starts degrading if the input signal does not settle within the acquisition time of
the ADC. The performance of the SAR ADC can be improved by reducing the throughput to provide enough time
for the input signal to settle. Figure 46 provides the results for ENOB achieved from the ADS7040 for case 2 at
different throughputs with different input impedances at the device input.
12
25 ꢀ and 1.5 nF
250 ꢀ and 1.5 nF
11
2.5 kꢀ and 1.5 nF
10 kꢀ and 1.5 nF
10
25 kꢀ and 1.5 nF
50 kꢀ and 1.5 nF
9
8
7
6
0
200
400
600
800
1000
C030
Sampling Rate (Ksps)
Figure 46. ENOB (Effective Number of Bits) Achieved from the ADS7040 at Different Throughputs
Table 6 shows the results and performance summary for this 12-bit, 10-kSPS DAQ circuit application.
Table 6. Results and Performance Summary for 8-Bit, 10-kSPS DAQ Circuit for DC Sensor
Measurements
DESIGN PARAMETER
Throughput
GOAL VALUE
10 kSPS
48.5 dB
65dB
ACHIEVED RESULT
10 kSPS
49.55 dB
70 dB
SNR at 100 Hz
THD at 100 Hz
SINAD at 100 Hz
ENOB
48dB
49.5 dB
7.5
7.93
Power
10 µW
6 µW
Copyright © 2014–2015, Texas Instruments Incorporated
29
ADS7040
ZHCSD01C –NOVEMBER 2014–REVISED DECEMBER 2015
www.ti.com.cn
10 Power-Supply Recommendations
10.1 AVDD and DVDD Supply Recommendations
The ADS7040 has two separate power supplies: AVDD and DVDD. The device operates on AVDD; DVDD is
used for the interface circuits. AVDD and DVDD can be independently set to any value within the permissible
ranges. The AVDD supply also defines the full-scale input range of the device. Always set the AVDD supply to
be greater than or equal to the maximum input signal to avoid saturation of codes. Decouple the AVDD and
DVDD pins individually with 1-µF ceramic decoupling capacitors, as shown in Figure 47. The minimum capacitor
value required for AVDD and DVDD is 200 nF and 20 nF, respectively. If both supplies are powered from the
same source, a minimum capacitor value of 220 nF is required for decoupling.
AVDD
AVDD
GND
1 mF
1 mF
DVDD
DVDD
Figure 47. Power-Supply Decoupling
10.2 Estimating Digital Power Consumption
The current consumption from the DVDD supply depends on the DVDD voltage, load capacitance on the SDO
line, and the output code. The load capacitance on the SDO line is charged by the current from the SDO pin on
every rising edge of the data output and is discharged on every falling edge of the data output. The current
consumed by the device from the DVDD supply can be calculated by Equation 5:
IDVDD = C × V × f
where:
•
•
•
C = Load capacitance on the SDO line,
V = DVDD supply voltage, and
f = Number of transitions on the SDO output.
(5)
The number of transitions on the SDO output depends on the output code, and thus changes with the analog
input. The maximum value of f occurs when data output on the SDO change on every SCLK. SDO changing on
every SCLK results in an output code of AAh or 55h. For an output code of AAh or 55h at a 1-MSPS throughput,
the frequency of transitions on the SDO output is 4MHz.
For the current consumption to remain at the lowest possible value, keep the DVDD supply at the lowest
permissible value and keep the capacitance on the SDO line as low as possible.
10.3 Optimizing Power Consumed by the Device
•
Keep the analog supply voltage (AVDD) as close as possible to the analog input voltage. Set AVDD to be
greater than or equal to the analog input voltage of the device.
•
•
•
Keep the digital supply voltage (DVDD) at the lowest permissible value.
Reduce the load capacitance on the SDO output.
Run the device at the optimum throughput. Power consumption reduces with throughput.
30
Copyright © 2014–2015, Texas Instruments Incorporated
ADS7040
www.ti.com.cn
ZHCSD01C –NOVEMBER 2014–REVISED DECEMBER 2015
11 Layout
11.1 Layout Guidelines
Figure 48 shows a board layout example for the ADS7040. Use a ground plane underneath the device and
partition the PCB into analog and digital sections. Avoid crossing digital lines with the analog signal path and
keep the analog input signals and the reference input signals away from noise sources. In Figure 48, the analog
input and reference signals are routed on the top and left side of the device and the digital connections are
routed on the bottom and right side of the device.
The power sources to the device must be clean and well-bypassed. Use 1-μF ceramic bypass capacitors in close
proximity to the analog (AVDD) and digital (DVDD) power-supply pins. Avoid placing vias between the AVDD and
DVDD pins and the bypass capacitors. Connect all ground pins to the ground plane using short, low-impedance
paths. The AVDD supply voltage for the ADS7040 also functions as a reference for the device. Place the
decoupling capacitor (CREF) for AVDD close to the device AVDD and GND pins and connect CREF to the device
pins with thick copper tracks, as shown in Figure 48.
The fly-wheel RC filters are placed close to the device. Among ceramic surface-mount capacitors, COG (NPO)
ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG (NPO) ceramic
capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes.
11.2 Layout Example
/
Lb
!ë55
Figure 48. Example Layout
版权 © 2014–2015, Texas Instruments Incorporated
31
ADS7040
ZHCSD01C –NOVEMBER 2014–REVISED DECEMBER 2015
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档ꢀ
相关文档如下：
•
•
•
•
《OPA314 数据表》（文献编号 SBOS563）
《OPA835 数据表》（文献编号 SLOS713）
《TPS79101 数据表》（文献编号 SLVS325）
《TIPD168 参考指南》（文献编号 TIDU390）
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
E2E is a trademark of Texas Instruments.
TINA is a trademark of Texas Instruments, Inc.
串行外设接口 (SPI) is a trademark of Motorola.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
32
版权 © 2014–2015, Texas Instruments Incorporated
ADS7040
www.ti.com.cn
ZHCSD01C –NOVEMBER 2014–REVISED DECEMBER 2015
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2014–2015, Texas Instruments Incorporated
33
ADS7040
ZHCSD01C –NOVEMBER 2014–REVISED DECEMBER 2015
www.ti.com.cn
PACKAGE OUTLINE
RUG0008A
X2QFN - 0.4 mm max height
SCALE 7.500
PLASTIC QUAD FLATPACK - NO LEAD
1.55
1.45
B
A
PIN 1 INDEX AREA
1.55
1.45
C
0.4 MAX
SEATING PLANE
0.05
0.00
0.08 C
SYMM
0.35
2X
(0.15)
TYP
0.25
0.45
0.35
2X
4
3
5
SYMM
2X
1
4X 0.5
0.25
0.15
2X
7
1
0.3
4X
8
0.2
0.1
0.05
PIN 1 ID
(45 X0.1)
C A
C
B
0.4
0.3
6X
4222060/A 05/14/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
34
版权 © 2014–2015, Texas Instruments Incorporated
ADS7040
www.ti.com.cn
ZHCSD01C –NOVEMBER 2014–REVISED DECEMBER 2015
EXAMPLE BOARD LAYOUT
RUG0008A
X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.3)
2X (0.6)
8
6X (0.55)
1
7
4X (0.25)
SYMM
(1.3)
4X (0.5)
2X (0.2)
3
5
(R0.05) TYP
4
SYMM
(1.35)
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL
UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4222060/A 05/14/2015
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
版权 © 2014–2015, Texas Instruments Incorporated
35
ADS7040
ZHCSD01C –NOVEMBER 2014–REVISED DECEMBER 2015
www.ti.com.cn
EXAMPLE STENCIL DESIGN
RUG0008A
X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.3)
2X (0.6)
8
6X (0.55)
1
7
4X (0.25)
SYMM
(1.3)
4X (0.5)
3
2X (0.2)
5
4
SYMM
(1.35)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICKNESS
SCALE:25X
4222060/A 05/14/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
36
版权 © 2014–2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS7040IDCUR
ADS7040IDCUT
ADS7040IRUGR
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
X2QFN
DCU
DCU
RUG
8
8
8
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
7040
7040
FT
NIPDAU
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS7040IDCUR
ADS7040IDCUT
ADS7040IRUGR
VSSOP
VSSOP
X2QFN
DCU
DCU
RUG
8
8
8
3000
250
180.0
180.0
180.0
8.4
8.4
8.4
2.25
2.25
1.6
3.35
3.35
1.6
1.05
1.05
0.66
4.0
4.0
4.0
8.0
8.0
8.0
Q3
Q3
Q2
3000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS7040IDCUR
ADS7040IDCUT
ADS7040IRUGR
VSSOP
VSSOP
X2QFN
DCU
DCU
RUG
8
8
8
3000
250
202.0
202.0
202.0
201.0
201.0
201.0
28.0
28.0
28.0
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DCU0008A
VSSOP - 0.9 mm max height
S
C
A
L
E
6
.
0
0
0
SMALL OUTLINE PACKAGE
3.2
3.0
TYP
C
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
6X 0.5
8
1
2X
2.1
1.9
1.5
NOTE 3
4
5
0.25
0.17
8X
2.4
2.2
B
0.08
C A B
NOTE 3
SEE DETAIL A
0.9
0.6
0.12
GAGE PLANE
0.1
0.0
0.35
0.20
0 -6
(0.13) TYP
A
30
DETAIL A
TYPICAL
4225266/A 09/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-187 variation CA.
www.ti.com
EXAMPLE BOARD LAYOUT
DCU0008A
VSSOP - 0.9 mm max height
SMALL OUTLINE PACKAGE
SEE SOLDER MASK
DETAILS
SYMM
8X (0.85)
(R0.05) TYP
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(3.1)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
OPENING
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4225266/A 09/2014
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCU0008A
VSSOP - 0.9 mm max height
SMALL OUTLINE PACKAGE
8X (0.85)
SYMM
(R0.05) TYP
8
1
8X (0.3)
SYMM
6X (0.5)
4
5
(3.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 25X
4225266/A 09/2014
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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