ADS7046IRUGR [TI]
12 位 3MSPS 单端输入小型低功耗 SAR ADC | RUG | 8 | -40 to 125;
| 型号： | ADS7046IRUGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12 位 3MSPS 单端输入小型低功耗 SAR ADC | RUG | 8 | -40 to 125 转换器 |
| 文件： | 总45页 (文件大小：1929K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS7046
ZHCSH50 –DECEMBER 2016
ADS7046 12 位，3 MSPS，单端输入，小型低功耗 SAR ADC
1 特性
3 说明
1
•
3 MSPS 吞吐量
封装尺寸小：
X2QFN-8 封装 (1.5mm × 1.5mm)
ADS7046 器件属于引脚对引脚兼容的高速低功耗、单
通道逐次逼近型寄存器 (SAR) 类型的模数转换器
(ADC) 系列。该器件系列包含多个分辨率、吞吐量和
模拟输入型号（有关器件列表，请参阅 表格1）。
•
–
•
•
单极输入范围：0V 至 AVDD
宽工作电压范围：
ADS7046 是一款 12 位 3 MSPS SAR ADC，支持0V
到 AVDD 范围内的单端输入，AVDD 的范围为2.35V
至 3.6V。
–
–
–
AVDD：2.35V 至 3.6V
DVDD：1.65V 至 3.6V（与 AVDD 无关）
温度范围：-40°C 至 +125°C
内部失调电压校准功能在整个 AVDD 和工作温度范围
内可保持优异的失调电压规格。
•
•
性能优异：
–
–
–
12 位 NMC DNL，±0.3-LSB INL
71.2dB SINAD（2kHz 时）
69.5dB SINAD（1MHz 时）
该器件支持由 CS 和 SCLK 信号控制的兼容 SPI 的串
行接口。输入信号通过 CS 下降沿进行采样，而 SCLK
用于转换和串行数据输出。该器件支持宽数字电源范围
（1.65V 至 3.6V），可直接连接到各种主机控制器。
ADS7046 的标称 DVDD 范围（1.65V 至 1.95V）符合
JESD8-7A 标准。
低功耗：
–
–
–
3.8mW（3 MSPS，3.3V AVDD 时）
115µW（100kSPS，3.3V AVDD 时）
67µW（100kSPS，2.5V AVDD 时）
•
•
•
集成失调电压校准
ADS7046 采用 8 引脚小型 X2QFN 封装，可以在广泛
的工业温度范围（–40°C 至 +125°C）内正常工作。该
器件体积小巧，功耗极低，非常适合需要高速高分辨率
数据采集的空间受限型 电池供电 应用。
与 SPI 兼容的串行接口：60MHz
符合 JESD8-7A 标准的数字 I/O
2 应用
器件信息(1)
•
•
•
•
•
•
•
•
光学编码器
部件名称
ADS7046
封装
封装尺寸（标称值）
声纳接收器
探鱼器
X2QFN (8)
1.50mm x 1.50mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
I/Q 解调器
光线路卡和模块
热成像摄像机
超声波流量计
手持无线电
典型应用
Simultaneous Sampling Circuit
Single ADC Circuit
Optical
SDO
+
SCLK
CS
ADC 1
ADC
HOST
SONAR
CS
SCLK
SDO
ADC 2
ADC Package Size
1.5 (L) x 1.5 (W) x 0.35 (H) mm
Votlage/
Current
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBAS785
ADS7046
ZHCSH50 –DECEMBER 2016
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 20
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Applications ................................................ 24
1
2
3
4
5
6
特性.......................................................................... 1
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 7
6.7 Switching Characteristics.......................................... 7
6.8 Typical Characteristics.............................................. 9
Parameter Measurement Information ................ 14
7.1 Digital Voltage Levels ............................................. 14
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 16
10 Power Supply Recommendations ..................... 31
10.1 AVDD and DVDD Supply Recommendations....... 31
10.2 Optimizing Power Consumed by the Device ........ 31
11 Layout................................................................... 32
11.1 Layout Guidelines ................................................. 32
11.2 Layout Example .................................................... 33
12 器件和文档支持 ..................................................... 34
12.1 器件支持................................................................ 34
12.2 文档支持................................................................ 34
12.3 接收文档更新通知 ................................................. 34
12.4 社区资源................................................................ 34
12.5 商标....................................................................... 34
12.6 静电放电警告......................................................... 34
12.7 Glossary................................................................ 35
13 机械、封装和可订购信息....................................... 36
7
8
4 修订历史记录
日期
修订版本
说明
2017 年 12 月
*
初始发行版
2
Copyright © 2016, Texas Instruments Incorporated
ADS7046
www.ti.com.cn
ZHCSH50 –DECEMBER 2016
5 Pin Configuration and Functions
RUG Package
8-Pin X2QFN
Top View
CS
SDO
1
2
3
7
6
5
AINP
AVDD
GND
SCLK
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
1
CS
Digital input
Digital output
Digital input
Supply
Chip-select signal, active low
Serial data out
2
3
4
5
6
7
8
SDO
SCLK
DVDD
GND
Serial clock
Digital I/O supply voltage
Supply
Ground for power supply, all analog and digital signals are referred to this pin
Analog power-supply input, also provides the reference voltage to the ADC
Analog signal input, positive
AVDD
AINP
AINM
Supply
Analog input
Analog input
Analog signal input, negative
Copyright © 2016, Texas Instruments Incorporated
3
ADS7046
ZHCSH50 –DECEMBER 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
–0.3
–0.3
–0.3
–0.3
–10
MAX
3.9
UNIT
V
AVDD to GND
DVDD to GND
3.9
V
AINP to GND
AVDD + 0.3
0.3
V
AINM to GND
V
Input current to any pin except supply pins
Digital input voltage to GND
Storage temperature, Tstg
10
mA
V
–0.3
–60
DVDD + 0.3
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.35
1.65
–40
NOM
3.3
MAX
UNIT
AVDD
DVDD
TA
Analog supply voltage range
Digital supply voltage range
Operating free-air temperature
3.6
3.6
V
V
1.8
25
125
°C
6.4 Thermal Information
ADS7046
THERMAL METRIC(1)
RUG (X2QFN)
UNIT
8 PINS
177.5
51.5
76.7
1
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
76.7
N/A
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2016, Texas Instruments Incorporated
ADS7046
www.ti.com.cn
ZHCSH50 –DECEMBER 2016
6.5 Electrical Characteristics
at AVDD = 3.3 V, DVDD = 1.65 V to 3.6 V, fsample = 3 MSPS, and VAINM = 0 V (unless otherwise noted); minimum and
maximum values for TA = –40°C to +125°C; typical values at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-scale input voltage
span(1)
0
AVDD
V
AINP to GND
–0.1
–0.1
AVDD + 0.1
0.1
Absolute input voltage
range
V
AINM to GND
CS
Sampling capacitance
16
12
pF
SYSTEM PERFORMANCE
Resolution
Bits
Bits
LSB(3)
NMC
INL(2)
DNL
No missing codes
12
–1
Integral nonlinearity
Differential nonlinearity
Offset error
±0.3
±0.15
±1
1
0.5
3
–0.5
–3
LSB
(2)
EO
After calibration(4)
LSB
Offset error drift with
temperature
dVOS/dT
1.75
±0.01
0.5
ppm/°C
%FS
(2)
EG
Gain error
–0.1
0.1
Gain error drift with
temperature
ppm/°C
SAMPLING DYNAMICS
tCONV Conversion time
tACQ
15 × tSCLK
ns
ns
Acquisition time
80
Maximum throughput
rate
fSAMPLE
60-MHz SCLK, AVDD = 2.35 V to 3.6 V
3
MHz
Aperture delay
3
ns
ps
Aperture jitter, RMS
12
DYNAMIC CHARACTERISTICS
AVDD = 3.3 V, fIN = 2 kHz
AVDD = 2.5 V, fIN = 2 kHz
fIN = 2 kHz
69
69
71.2
70.4
–86
–85
–84.5
71.1
70.9
70.8
90
SNR
Signal-to-noise ratio(5)
dB
dB
Total harmonic
distortion(5)(6)
THD
fIN = 500 kHz
fIN = 1000 kHz
fIN = 2 kHz
Signal-to-noise and
distortion(5)
SINAD
fIN = 500 kHz
dB
fIN = 1000 kHz
fIN = 2 kHz
Spurious-free dynamic
range(5)
SFDR
BW(fp)
fIN = 500 kHz
90
dB
fIN = 1000 kHz
At –3 dB
88
Full-power bandwidth
200
MHz
(1) Ideal input span; does not include gain or offset error.
(2) See Figure 31, Figure 29, and Figure 30 for statistical distribution data for INL, offset error, and gain error.
(3) LSB means least significant bit.
(4) See the OFFCAL State section for details.
(5) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale,
unless otherwise noted.
(6) Calculated on the first nine harmonics of the input frequency.
Copyright © 2016, Texas Instruments Incorporated
5
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ZHCSH50 –DECEMBER 2016
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Electrical Characteristics (continued)
at AVDD = 3.3 V, DVDD = 1.65 V to 3.6 V, fsample = 3 MSPS, and VAINM = 0 V (unless otherwise noted); minimum and
maximum values for TA = –40°C to +125°C; typical values at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT/OUTPUT (CMOS Logic Family)
High-level input
VIH
0.65 DVDD
–0.3
DVDD + 0.3
0.35 DVDD
V
V
voltage(7)
Low-level input
VIL
voltage(7)
At Isource = 500 µA
At Isource = 2 mA
0.8 DVDD
DVDD
DVDD
High-level output
voltage(7)
VOH
V
V
DVDD – 0.45
At Isink = 500 µA
At Isink = 2 mA
0
0
0.2 DVDD
0.45
Low-level output
voltage(7)
VOL
POWER-SUPPLY REQUIREMENTS
AVDD
DVDD
Analog supply voltage
2.35
1.65
3
3
3.6
3.6
V
V
Digital I/O supply
voltage
AVDD = 3.3 V, fSAMPLE = 3 MSPS
AVDD = 3.3 V, fSAMPLE = 100 kSPS
AVDD = 3.3 V, fSAMPLE = 10 kSPS
AVDD = 2.5 V, fSAMPLE = 3 MSPS
Static current with CS and SCLK high
1150
36
1300
45
IAVDD
Analog supply current
Digital supply current
5
µA
800
0.02
DVDD = 1.8 V, CSDO = 20 pF,
output code = AAAh(8)
650
IDVDD
µA
DVDD = 1.8 V, static current with CS and
SCLK high
0.01
(7) Digital voltage levels comply with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V; see the Parameter Measurement Information
section for details.
(8) See the Estimating Digital Power Consumption section for details.
6
Copyright © 2016, Texas Instruments Incorporated
ADS7046
www.ti.com.cn
ZHCSH50 –DECEMBER 2016
6.6 Timing Requirements
all specifications are at AVDD = 2.35 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and CLOAD-SDO = 20 pF (unless otherwise noted);
minimum and maximum values for TA = –40°C to +125°C; typical values at TA = 25°C
MIN
16.66
7
TYP
MAX
UNIT
ns
tCLK
Time period of SCLK
tsu_CSCK
tht_CKCS
tph_CK
tpl_CK
Setup time: CS falling edge to SCLK falling edge
Hold time: SCLK rising edge to CS rising edge
SCLK high time
ns
8
ns
0.45
0.45
15
0.55
0.55
tSCLK
tSCLK
ns
SCLK low time
tph_CS
CS high time
6.7 Switching Characteristics
all specifications are at AVDD = 2.35 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and CLOAD-SDO = 20 pF (unless otherwise noted);
minimum and maximum values for TA = –40°C to +125°C; typical values at TA = 25°C
PARAMETER
Cycle time
Conversion time
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ns
(1)
tCYCLE
tCONV
333
15 × tSCLK
ns
tden_CSDO Delay time: CS falling edge to data enable
6.5
10
ns
Delay time: SCLK rising edge to (next) data
valid on SDO
td_CKDO
ns
ns
ns
tht_CKDO
tdz_CSDO
SCLK rising edge to current data invalid
2.5
5.5
Delay time: CS rising edge to SDO going to
tri-state
(1) tCYCLE = 1 / fSAMPLE
.
Copyright © 2016, Texas Instruments Incorporated
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ZHCSH50 –DECEMBER 2016
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Sample
A+1
Sample
A
tACQ
tCYCLE
tph_CS
tCONV
CS
SCLK
SDO
1
2
3
13
14
15
0
D10
D0
0
0
D11
Data Output for Sample A-1
Figure 1. Serial Transfer Frame
tCLK
tph_CK
tpl_CK
CS
50%
SCLK
50%
td_CKDO
tsu_CSCK
tht_CKCS
SCLK
50%
SDO
50%
tht_CKDO
tden_CSDO
tdz_CSDO
SDO
Figure 2. Timing Specifications
8
Copyright © 2016, Texas Instruments Incorporated
ADS7046
www.ti.com.cn
ZHCSH50 –DECEMBER 2016
6.8 Typical Characteristics
at TA = 25°C, AVDD = 3.3 V, DVDD = 1.8 V, fIN = 2 kHz, and fsample = 3 MSPS (unless otherwise noted)
0
-50
0
-50
-100
-150
-200
-100
-150
-200
0
300
600
900
1200
1500
0
300
600
900
1200
1500
fIN, Input Frequency (kHz)
fIN, Input Frequency (kHz)
D001
D003
SNR = 71.5 dB, THD = –87.5 dB, ENOB = 11.6 bits
SNR = 70.1 dB, THD = –85.7 dB, fIN = 500 kHz
Figure 3. Typical FFT
Figure 4. Typical FFT
0
73
72
71
70
69
68
SNR
SINAD
-50
-100
-150
-200
0
300
600
900
1200
1500
-40
-7
26
59
92
125
fIN, Input Frequency (kHz)
Free-Air Temperature (èC)
D004
D005
SNR = 70.1dB, THD = –88.2 dB, fIN = 1000 kHz
Figure 5. Typical FFT
Figure 6. SNR and SINAD vs Temperature
73
72
71
70
69
68
75
73
71
69
67
65
SNR
SINAD
SNR
SINAD
0
200
400
600
800
1000
2.35
2.6
2.85
3.1
3.35
3.6
fIN, Input Frequency (kHz)
AVDD Voltage (V)
D006
D007
Figure 7. SNR and SINAD vs Input Frequency
Figure 8. SNR and SINAD vs Reference Voltage (AVDD)
Copyright © 2016, Texas Instruments Incorporated
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ZHCSH50 –DECEMBER 2016
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, DVDD = 1.8 V, fIN = 2 kHz, and fsample = 3 MSPS (unless otherwise noted)
-93
-91
-89
-87
-85
-83
-84
-86
-88
-90
-92
-94
-40
-7
26
59
92
125
0
200
400
600
800
1000
Free-Air Temperature (èC)
fIN, Input Frequency (kHz)
D008
D010
Figure 9. THD vs Temperature
Figure 10. THD vs Input Frequency
-84
-86
-88
-90
-92
-94
100
98
96
94
92
90
2.35
2.6
2.85
3.1
3.35
3.6
-40
-7
26
59
92
125
AVDD Voltage (V)
Free-Air Temperature (èC)
D012
D009
Figure 11. THD vs Reference Voltage (AVDD)
Figure 12. SFDR vs Temperature
94
92
90
88
86
84
100
97
94
91
88
85
0
200
400
600
800
1000
2.35
2.6
2.85
3.1
3.35
3.6
fIN, Input Frequency (kHz)
AVDD Voltage (V)
D011
D013
Figure 13. SFDR vs Input Frequency
Figure 14. SFDR vs Reference Voltage (AVDD)
10
Copyright © 2016, Texas Instruments Incorporated
ADS7046
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ZHCSH50 –DECEMBER 2016
Typical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, DVDD = 1.8 V, fIN = 2 kHz, and fsample = 3 MSPS (unless otherwise noted)
0.5
0.5
0.3
0.3
0.1
0.1
-0.1
-0.3
-0.5
-0.1
-0.3
-0.5
0
819
1638
2457
3276
4095
0
819
1638
2457
3276
4095
Code
Code
D019
D020
Figure 15. Typical DNL
Figure 16. Typical INL
0.5
0.3
0.5
0.3
Minimum
Maximum
Minimum
Maximum
0.1
0.1
-0.1
-0.3
-0.5
-0.1
-0.3
-0.5
-40
-7
26
59
92
125
2.35
2.6
2.85
3.1
3.35
3.6
Free-Air Temperature (èC)
AVDD Voltage (V)
D023
D024
Figure 17. DNL vs Temperature
Figure 18. DNL vs Reference Voltage
0.5
0.5
Minimum
Maximum
Minimum
Maximum
0.3
0.1
0.3
0.1
-0.1
-0.3
-0.5
-0.1
-0.3
-0.5
-40
-7
26
59
92
125
2.35
2.6
2.85
3.1
3.35
3.6
Free-Air Temperature (èC)
AVDD Voltage (V)
D025
D026
Figure 19. INL vs Temperature
Figure 20. INL vs Reference Voltage
Copyright © 2016, Texas Instruments Incorporated
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ZHCSH50 –DECEMBER 2016
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, DVDD = 1.8 V, fIN = 2 kHz, and fsample = 3 MSPS (unless otherwise noted)
40000
32000
24000
16000
8000
0
4
Calibrated
Uncalibrated
2
0
-2
-4
2046
2047
2048
2049
-40
-7
26
59
92
125
Code
Free-Air Temperature (èC)
D014
D015
VIN = AVDD / 2
Figure 21. DC Input Histogram
Figure 22. Offset vs Temperature
4
2
0.1
0.06
0.02
-0.02
-0.06
-0.1
Calibrated
Uncalibrated
Calibrated
Uncalibrated
0
-2
-4
2.35
2.6
2.85
3.1
3.35
3.6
-40
-7
26
59
92
125
AVDD Voltage (V)
Free-Air Temperature (èC)
D016
D017
Figure 23. Offset vs Reference Voltage (AVDD)
Figure 24. Gain Error vs Temperature
1.5
1.4
1.3
1.2
1.1
1
2
1.6
1.2
0.8
0.4
0
-40
-7
26
59
92
125
0
500
1000
1500
2000
2500
Free-Air Temperature (èC)
Throughput (kSPS)
D027
D028
Figure 25. AVDD Current vs Temperature
Figure 26. AVDD Current vs Throughput
12
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ZHCSH50 –DECEMBER 2016
Typical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, DVDD = 1.8 V, fIN = 2 kHz, and fsample = 3 MSPS (unless otherwise noted)
1000
800
600
400
200
0
2
1.6
1.2
0.8
0.4
0
2.35
2.6
2.85
3.1
3.35
3.6
-40
-7
26
59
92
125
AVDD Voltage (V)
Free-Air Temperature (èC)
D029
D030
CS = DVDD
Figure 27. AVDD Current vs AVDD Voltage
Figure 28. Static AVDD Current vs Temperature
6000
4800
3600
2400
1200
0
7500
6000
4500
3000
1500
0
3
5
-2.
2
5
-1.
1
-
5
-0.
0
1
2
3
1
0
1
2
3
4
5
6
7
8
9
-
-
09 08 07 06 05 04 03 02 01
-0.
-0. -0. -0. -0. -0. -0. -0. -0. -0.
0.5
1.5
2.5
0.1
0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0
D031
D032
14000 Devices
14000 Devices
Figure 29. Typical Offset Error Distribution
Figure 30. Typical Gain Error Distribution
15000
12000
9000
6000
3000
0
1
-
0
2
4
6
8
0.
0.
0.
0.
-0.8
-0.6
-0.4
-0.2
D033
14000 Devices
Figure 31. Typical INL Distribution
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7 Parameter Measurement Information
7.1 Digital Voltage Levels
The device complies with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V. Figure 32 shows voltage
levels for the digital input and output pins.
Digital Output
DVDD
VOH
DVDD-0.45V
SDO
0.45V
VOL
0V
ISource= 2 mA, ISink = 2 mA,
DVDD = 1.65 V to 1.95 V
Digital Inputs
DVDD + 0.3V
VIH
0.65DVDD
CS
SCLK
0.35DVDD
VIL
DVDD = 1.65 V to 1.95 V
-0.3V
Figure 32. Digital Voltage Levels as per the JESD8-7A Standard
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8 Detailed Description
8.1 Overview
The ADS7046 device belongs to a family of pin-to-pin compatible, high-speed, low-power, single-channel
successive-approximation register (SAR) type analog-to-digital converters (ADCs). The device family includes
multiple resolutions, throughputs, and analog input variants (see Table 1 for a list of devices).
The ADS7046 is a 12-bit, 3-MSPS SAR ADC that supports a single-ended input in the range of 0 V to AVDD, for
AVDD in the range of 2.35 V to 3.6 V (see the Analog Input section for details on the analog input pins).
The internal offset calibration feature (see the OFFCAL State section) maintains excellent offset specifications
over the entire AVDD and temperature operating range.
The device supports an SPI-compatible serial interface that is controlled by the CS and SCLK signals. The input
signal is sampled with the CS falling edge and SCLK is used for both, conversion and serial data output (see the
Device Functional Modes section, Timing Requirements table, and Switching Characteristics table).
The device supports a wide digital supply range (1.65 V to 3.6 V), enabling direct interfacing to a variety of host
controllers. The ADS7046 complies with the JESD8-7A standard (see the Digital Voltage Levels section) for a
normal DVDD range (1.65 V to 1.95 V).
The ADS7046 is available in an 8-pin, small, X2QFN package (see the 机械、封装和可订购信息 section for more
details) and is specified over the extended industrial temperature range (–40°C to +125°C).
The small form-factor and extremely-low power consumption make this device suitable for space-constrained and
battery-powered applications that require high-speed, high-resolution data acquisition (see the Application
Information section).
8.2 Functional Block Diagram
DVDD
AVDD
GND
Offset
Calibration
AINP
AINM
CS
SCLK
SDO
CDAC
Comparator
Serial
Interface
SAR
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8.3 Feature Description
8.3.1 Product Family
The devices listed in Table 1 are all part of the same pin-to-pin compatible, high-speed, low-power, single-
channel SAR ADC family. This device family includes multiple different ADC resolutions, throughputs, and analog
input types to allow for greater flexibility in the end system. Devices in the same package are pin-compatible to
offer a scalable family of devices for varying levels of end-system performance. The ADCs with device numbers
ending in -Q1 are also AEC-Q100 qualified for automotive applications.
Table 1. Device Family Comparison
THROUGHPUT
DEVICE NUMBER
ADS7040
RESOLUTION (Bits)
INPUT TYPE
Single-ended
PACKAGES(1)
(MSPS)
X2QFN (8): 1.5 mm × 1.5 mm
VSSOP (8): 2.0 mm × 3.1 mm
8
1
X2QFN (8): 1.5 mm × 1.5 mm
VSSOP (8): 2.0 mm × 3.1 mm
ADS7041
10
12
12
12
1
1
1
1
Single-ended
X2QFN (8): 1.5 mm × 1.5 mm
VSSOP (8): 2.0 mm × 3.1 mm
ADS7042
Single-ended
X2QFN (8): 1.5 mm × 1.5 mm
VSSOP (8): 2.0 mm × 3.1 mm
ADS7043
Pseudo-differential
Fully-differential
X2QFN (8): 1.5 mm × 1.5 mm
VSSOP (8): 2.0 mm × 3.1 mm
ADS7044
ADS7029-Q1
ADS7039-Q1
ADS7049-Q1
ADS7046
8
2
2
Single-ended
Single-ended
Single-ended
Single-ended
Fully-differential
Single-ended
Fully-differential
Single-ended
Fully-differential
VSSOP (8): 2.0 mm × 3.1 mm
VSSOP (8): 2.0 mm × 3.1 mm
VSSOP (8): 2.0 mm × 3.1 mm
X2QFN (8): 1.5 mm × 1.5 mm
X2QFN (8): 1.5 mm × 1.5 mm
X2QFN (8): 1.5 mm × 1.5 mm
X2QFN (8): 1.5 mm × 1.5 mm
X2QFN (8): 1.5 mm × 1.5 mm
X2QFN (8): 1.5 mm × 1.5 mm
10
12
12
12
14
14
14
14
2
3
ADS7047
3
ADS7052
1
ADS7054
1
ADS7056
2.5
2.5
ADS7057
(1) Devices listed in the same package are pin-compatible.
16
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8.3.2 Analog Input
The device supports a unipolar, single-ended analog input signal. Figure 33 shows a small-signal equivalent
circuit of the sample-and-hold circuit. The sampling switch is represented by a resistance (RS1 and RS2, typically
50 Ω) in series with an ideal switch (SW1 and SW2). The sampling capacitors, CS1 and CS2, are typically 16 pF.
AVDD
SW1
Rs1
AINP
Cs1
GND
V_BIAS
AVDD
Cs2
SW2
Rs2
AINM
GND
Figure 33. Equivalent Input Circuit for the Sampling Stage
During the acquisition process, both positive and negative inputs are individually sampled on CS1 and CS2,
respectively. During the conversion process, the device converts for the voltage difference between the two
sampled values: VAINP – VAINM
.
Each analog input pin has electrostatic discharge (ESD) protection diodes to AVDD and GND. Keep the analog
inputs within the specified range to avoid turning the diodes on.
The full-scale analog input range (FSR) is 0 V to AVDD.
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8.3.3 Reference
The device uses the analog supply voltage (AVDD) as the reference voltage for the analog to digital conversion.
During the conversion process, the internal capacitors are switched to the AVDD pin as per the successive
approximation algorithm. A voltage reference must be selected with low temperature drift, high output current
drive and low output impedance. TI recommends a 3.3-µF (CAVDD), low equivalent series resistance (ESR)
ceramic capacitor between the AVDD and GND pins. This decoupling capacitor provides the instantaneous
charge required by the internal circuit during the conversion process and maintains a stable dc voltage on the
AVDD pin.
See the Power Supply Recommendations and Layout Example sections for component recommendations and
layout guidelines.
AVDD
CAVDD
GND
CDVDD
DVDD
Figure 34. Reference for the Device
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8.3.4 ADC Transfer Function
The device supports a unipolar, single-ended analog input signal. The output is in straight binary format.
Figure 35 and Table 2 show the ideal transfer characteristics for the device.
The least significant bit for the device is given by:
1 LSB = VREF / 2N
where:
•
•
VREF = Voltage applied between the AVDD and GND pins
N = 12
(1)
PFSC
MC + 1
MC
NFSC+1
NFSC
VIN
V
REF
V
REF
VREF œ 1 LSB
+ 1LSB
1 LSB
2
2
Single-Ended Analog Input
(AINP œ AINM)
Figure 35. Ideal Transfer Characteristics
Table 2. Transfer Characteristics
IDEAL OUTPUT CODE
(Hex)
INPUT VOLTAGE (AINP – AINM)
CODE
DESCRIPTION
≤ 1 LSB
1 LSB to 2 LSB
NFSC
NFSC + 1
MC
Negative full-scale code
000
001
7FF
800
FFF
—
Mid code
VREF / 2 to VREF / 2 + 1 LSB
VREF / 2 + 1 LSB to VREF / 2 + 2 LSB
≥ VREF – 1 LSB
MC + 1
PFSC
—
Positive full-scale code
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8.4 Device Functional Modes
The device supports a simple, SPI-compatible interface to the external host. On power-up, the device is in the
ACQ state. The CS signal defines one conversion and serial data transfer frame. A frame starts with a CS falling
edge and ends with a CS rising edge. The SDO pin is tri-stated when CS is high. With CS low, the clock
provided on the SCLK pin is used for conversion and data transfer. Output data are available on the SDO pin.
As shown in Figure 36, the device supports three functional states: acquisition (ACQ), conversion (CNV), and
offset calibration (OFFCAL). The device status depends on the CS and SCLK signals provided by the host
controller.
ACQ
OFFCAL
CONV
Figure 36. Functional State Diagram
8.4.1 ACQ State
In the ACQ state, switches SW1 and SW2 connected to the analog input pins close and the device acquires the
analog input signal on CS1 and CS2. The device enters ACQ state at power-up, at the end of every conversion,
and after completing the offset calibration. A CS falling edge takes the device from the ACQ state to the CNV
state.
The device consumes extremely low power from the AVDD and DVDD power supplies when in ACQ state.
20
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Device Functional Modes (continued)
8.4.2 CNV State
In the CNV state, the device uses the external clock to convert the sampled analog input signal to an equivalent
digital code as per the transfer function illustrated in Figure 35. The conversion process requires a minimum of
15 SCLK falling edges to be provided within the frame. After the end of conversion process, the device
automatically moves from the CNV state to the ACQ state. For acquisition of the next sample, a minimum time of
tACQ must be provided.
Figure 37 shows a detailed timing diagram for the serial interface. In the first serial transfer frame after power-up,
the device provides the first data as all zeros. In any frame, the clocks provided on the SCLK pin are also used to
transfer the output data for the previous conversion. A leading 0 is output on the SDO pin on the CS falling edge.
The most significant bit (MSB) of the output data is launched on the SDO pin on the rising edge after the first
SCLK falling edge. Subsequent output bits are launched on the subsequent rising edges provided on SCLK.
When all 12 output bits are shifted out, the device outputs 0's on the subsequent SCLK rising edges. The device
enters the ACQ state after 15 clocks and a minimum time of tACQ must be provided for acquiring the next sample.
If the device is provided with less than 15 SCLK falling edges in the present serial transfer frame, the device
provides an invalid conversion result in the next serial transfer frame.
Sample
Sample
A+1
A
tACQ
tCYCLE
tph_CS
tCONV
CS
SCLK
SDO
1
2
3
13
14
15
0
D10
D0
0
0
D11
Data Output for Sample A-1
Figure 37. Serial Interface Timing Diagram
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Device Functional Modes (continued)
8.4.3 OFFCAL State
In the offset calibration (OFFCAL) state, the sampling capacitors are disconnected from the analog input pins
(AINP and AINM) and the device calibrates and corrects for any internal offset errors. The offset calibration is
effective for all subsequent conversions until the device is powered off. An offset calibration cycle is
recommended at power-up and whenever there is a significant change in the operating conditions for the device
(such as in the AVDD voltage and operating temperature).
The host controller must provide a serial transfer frame as described in Figure 38 or in Figure 39 to enter the
OFFCAL state.
8.4.3.1 Offset Calibration on Power-Up
On power-up, the host must provide 24 SCLKs in the first serial transfer to enter the OFFCAL state. The device
provides 0's on SDO during offset calibration. For acquisition of the next sample, a minimum time of tACQ must be
provided.
If the host controller starts the offset calibration process but then pulls the CS pin high before providing 24
SCLKs, then the offset calibration process is aborted and the device enters the ACQ state. Figure 38 and
Table 3 provide the timing for offset calibration on power-up.
First
Next
Sample
Sample
tCYCLE
tACQ
CS
SCLK
SDO
1
2
3
4
24
0
0
0
0
0
0
Data Output for First Sample
Figure 38. Timing for Offset Calibration on Power-Up
Table 3. Timing Specifications for Offset Calibration on Power-Up(1)
MIN
24 × tCLK + tACQ
80
TYP
MAX
UNIT
tcycle
tACQ
fSCLK
Cycle time for offset calibration on power-up
ns
ns
Acquisition time
Frequency of SCLK
60
MHz
(1) In addition to the timing specifications of Figure 38 and Table 3, the timing specifications described in Figure 2 and the Timing
Requirements table are also applicable for offset calibration on power-up.
22
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8.4.3.2 Offset Calibration During Normal Operation
During normal operation, the host must provide 64 SCLKs in the serial transfer frame to enter the OFFCAL state.
The device provides the conversion result for the previous sample during the first 15 SCLKs and 0's on SDO for
the rest of the SCLKs in the serial transfer frame. For acquisition of the next sample, a minimum time of tACQ
must be provided.
If the host controller provides more than 15 SCLKs but pulls the CS high before providing 64 SCLKs, then the
offset calibration process is aborted and the device enters the ACQ state. Figure 39 and Table 4 provide the
timing for offset calibration during normal operation.
Sample
A
Sample
A+1
tCYCLE
tACQ
CS
SCLK
SDO
4
14
15
64
1
2
3
D10
D0
0
0
0
D11
Data Output for Sample A-1
Figure 39. Timing for Offset Calibration During Normal Operation
Table 4. Timing Specifications for Offset Calibration During Normal Operation(1)
MIN
64 × tCLK + tACQ
80
TYP
MAX
UNIT
ns
tcycle
tACQ
fSCLK
Cycle time for offset calibration on power-up
Acquisition time
ns
Frequency of SCLK
60
MHz
(1) In addition to the timing specifications of Figure 39 and Table 4, the timing specifications described in Figure 2 and the Timing
Requirements table are also applicable for offset calibration during normal operation.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The two primary supporting circuits required to maximize the performance of a high-precision, successive
approximation register (SAR) analog-to-digital converter (ADC) are the input driver and the reference driver
circuits. This section details some general principles for designing the input driver circuit, reference driver circuit,
and provides typical application circuits designed for the device.
9.2 Typical Applications
9.2.1 Single-Supply Data Acquisition With the ADS7046
Reference Driver
REF1933
(AVDD + 0.2V) to 5.5 V
VIN
VOUT
GND
1uF
3.3uF
AVDD
3.3V
OPA_VDD
33 ꢀ
œ
VDD
VIN
+
SPI
Host
Controller
OPA836
Device
+
œ
VSOURCE
680pF
GND
GND
ADC
Input Driver
Figure 40. DAQ Circuit: Single-Supply DAQ
9.2.1.1 Design Requirements
The goal of the circuit shown in Figure 40 is to design a single-supply data acquisition (DAQ) circuit based on the
ADS7046 with SNR greater than 70 dB and THD less than –85 dB for input frequencies of 2 kHz to 200 kHz at a
throughput of 3 MSPS for applications such as sonar receivers and ultrasonic flow meters.
24
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Typical Applications (continued)
9.2.1.2 Detailed Design Procedure
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and charge
kickback filter. Careful design of the front-end circuit is critical to meet the linearity and noise performance of a
high-precision ADC.
9.2.1.2.1 Low Distortion Charge Kickback Filter Design
Figure 41 shows the input circuit of a typical SAR ADC. During the acquisition phase, the SW switch closes and
connects the sampling capacitor (CSH) to the input driver circuit. This action introduces a transient on the input
pins of the SAR ADC. An ideal amplifier with 0 Ω of output impedance and infinite current drive can settle this
transient in zero time. For a real amplifier with non-zero output impedance and finite drive strength, this switched
capacitor load can create stability issues.
Charge Kickback Filter
RFLT
SAR ADC
-
+
SW
CSH
VIN
CFLT
f-3dB
=
1
2 Πx RFLT x CFLT
Figure 41. Input Sample-and-Hold Circuit for a Typical SAR ADC
For ac signals, the filter bandwidth must be kept low to band-limit the noise fed into the ADC input, thereby
increasing the signal-to-noise ratio (SNR) of the system. Besides filtering the noise from the front-end drive
circuitry, the RC filter also helps attenuate the sampling charge injection from the switched-capacitor input stage
of the ADC. A filter capacitor, CFLT, is connected across the ADC inputs. This capacitor helps reduce the
sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold
capacitors during the acquisition process. As a rule of thumb, the value of this capacitor is at least 20 times the
specified value of the ADC sampling capacitance. For this device, the input sampling capacitance is equal to
16 pF. Thus, the value of CFLT is greater than 320 pF. Select a COG- or NPO-type capacitor because these
capacitor types have a high-Q, low-temperature coefficient, and stable electrical characteristics under varying
voltages, frequency, and time.
Driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of
the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a
result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance,
input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability
and distortion of the design.
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Typical Applications (continued)
9.2.1.2.2 Input Amplifier Selection
The input amplifier bandwidth is typically much higher than the cutoff frequency of the charge kickback filter.
Thus, TI strongly recommends performing a SPICE simulation to confirm that the amplifier has more than 40°
phase margin with the selected filter. Simulation is critical because even with high-bandwidth amplifiers, some
amplifiers can require more bandwidth than others to drive similar filters. To learn more about the SAR ADC
input driver design, see the TI Precision Labs training video series.
For the application circuit of Figure 40, the OPA836 is selected for its high bandwidth (205 MHz), low noise
(4.6 nV/√Hz), high output drive capacity (45 mA), and fast settling response (22 ns for 0.1% settling).
9.2.1.2.3 Reference Circuit
The ADS70xx uses the analog supply voltage (AVDD) as the reference voltage for the analog to digital
conversion. During the conversion process, the internal capacitors are switched to the level of the AVDD pin as
per the successive approximation algorithm. A voltage reference must be selected with low temperature drift,
high output current drive and low output impedance. For this application, the REF1933 was selected as the
voltage reference and analog power supply for the ADC. The REF1933 has excellent temperature drift
performance (25 ppm/°C), good initial accuracy (0.1%), high output drive capability (25 mA), and low quiescent
current (360 µA). The REF1933 also provides a bias voltage output of half the reference voltage (VREF/2) which
can be used as the common mode input for the amplifier.
TI recommends a 3.3-µF (CAVDD), low equivalent series resistance (ESR) ceramic capacitor between the AVDD
and GND pins. This decoupling capacitor provides the instantaneous charge required by the internal circuit
during the conversion process and maintains a stable dc voltage on the AVDD pin.
9.2.1.3 Application Curves
Figure 42 and Figure 43 provide the measurement results for the circuit described in Figure 40.
0
-50
0
-50
-100
-150
-200
-100
-150
-200
0
300
600
900
1200
1500
0
300
600
900
1200
1500
fIN, Input Frequency (kHz)
fIN, Input Frequency (kHz)
D001
D002
SNR = 70.7 dB, THD = –89.1 dB, SINAD = 70.5 dB
SNR = 70.3 dB, THD = –88.7 dB, SINAD = 70 dB
Figure 42. Test Results for the ADS7046 and OPA836 for a
2-kHz Input
Figure 43. Test Results for the ADS7046 and OPA836 for a
200-kHz Input
26
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Typical Applications (continued)
9.2.2 High Bandwidth (1 MHz) Data Acquisition With the ADS7046
Reference Driver
REF1933
(AVDD + 0.2V) to 5.5 V
VIN
VOUT
GND
1uF
3.3uF
499 ꢀ
AVDD
3.3V
+6V
499 ꢀ
10 ꢀ
œ
AVDD
VIN
+
VIN
+
SPI
œ
THS4031
Host
Device
Controller
VCM = 0.825V
-6V
470pF
GND
Input Driver
ADC
Figure 44. High Bandwidth DAQ Circuit
9.2.2.1 Design Requirements
Applications such as sonar, ultrasonic flow meters, global positioning systems (GPS), handheld radios, and
motor controls need analog-to-digital converters that are interfaced to high-frequency sensors (100 kHz to
1 MHz). The goal of the circuit described in Figure 44 is to design a circuit based on the ADS7046 with SNR
greater than 70 dB and THD less than –80 dB for input frequencies of 200 kHz to 1 MHz at a throughput of
3 MSPS.
9.2.2.2 Detailed Design Procedure
To achieve a SINAD greater than 69 dB, the operational amplifier must have high bandwidth in order to settle the
input signal within the acquisition time of the ADC. The operational amplifier must have low noise to keep the
total system noise below 20% of the input-referred noise of the ADC. For the application circuit shown in
Figure 44, the THS4031 is selected for its high bandwidth (275 MHz), low total harmonic distortion of –90 dB at
1 MHz, and ultra-low noise of 1.6 nV/√Hz. The THS4031 is powered up from dual power supply (VDD = 6 V and
VSS = –6 V).
For this application, the REF1933 was selected as the voltage reference and analog power supply for the ADC.
The REF1933 has excellent temperature drift performance (25 ppm/°C), good initial accuracy (0.1%), high output
drive capability (25 mA), and low quiescent current (360 µA). The REF1933 also provides a bias voltage output
of half the reference voltage (VREF / 2) that can be used as the common-mode input for the amplifier.
The SNR performance at higher input frequency is highly dependant on jitter on the sampling signal (CS). TI
recommends selecting a clock source that has very low jitter (< 20-ps RMS).
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Typical Applications (continued)
9.2.2.3 Application Curves
Figure 45 shows the FFT plot for the ADS7046 with a 500-kHz input frequency used for the circuit in Figure 44.
Figure 46 shows the FFT plot for the ADS7046 with a 1000-kHz input frequency used for the circuit in Figure 44.
0
0
-50
-50
-100
-150
-200
-100
-150
-200
0
300
600
900
1200
1500
0
300
600
900
1200
1500
fIN, Input Frequency (kHz)
fIN, Input Frequency (kHz)
D003
D004
SNR = 70.2 dB, THD = –90.4 dB, SINAD = 70 dB
SNR = 69.9 dB, THD = –87.8 dB, SINAD = 69.5 dB
Figure 45. Test Results for the ADS7046 and THS4031 for
a 500-kHz Input
Figure 46. Test Results for the ADS7046 and THS4031 for
a 1000-kHz Input
28
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Typical Applications (continued)
9.2.3 12-Bit, 10-kSPS DAQ Circuit Optimized for DC Sensor Measurements
AVDD
Sensor
RSOURCE
AVDD
AINP
+
TI Device
œ
CFLT
AINM
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 47. Interfacing the Device Directly With Sensors
In applications where the input is very slow moving and the overall system ENOB is not a critical parameter, a
DAQ circuit can be designed without the input driver for the ADC. This type of a use case is of particular interest
for applications in which the primary goal is to achieve the absolute lowest power possible. Typical applications
that fall into this category are low-power sensor applications (such as temperature, pressure, humidity, gas, and
chemical).
9.2.3.1 Design Requirements
For this design example, use the parameters listed in Table 5 as the input parameters.
Table 5. Design Parameters
DESIGN PARAMETER
Throughput
GOAL VALUE
10 kSPS
70 dB
SNR at 100 Hz
THD at 100 Hz
SINAD at 100 Hz
ENOB
–75 dB
69 dB
11 bits
Power
20 µW
9.2.3.2 Detailed Design Procedure
The ADS7046 can be directly interfaced with sensors at lower throughput without the need of an amplifier buffer,
however, the output impedance of the sensor must be taken into account. The sensor must be capable of driving
the switched capacitor load of a SAR ADC and settling the analog input signal within the acquisition time of the
SAR ADC. Figure 47 shows the simplified circuit for a sensor as a voltage source with output impedance
(Rsource). As the output impedance of the sensor increases, the device requires more acquisition time to settle the
input signal to the desired accuracy.
The acquisition time of a SAR ADC (such as the ADS7046 ) can be increased by reducing throughput in the
following ways:
1. Reducing the SCLK frequency to reduce the throughput or
2. Keeping the SCLK fixed at the highest permissible value (that is, 60 MHz for the device) and increasing the
CS high time
Copyright © 2016, Texas Instruments Incorporated
29
ADS7046
ZHCSH50 –DECEMBER 2016
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Table 6 lists the acquisition time for the above two cases for a throughput of 10 kSPS. Clearly, case 2 provides
more acquisition time for the input signal to settle.
Table 6. Acquisition Time With Different SCLK Frequencies
CONVERSION TIME
ACQUISITION TIME
CASE
SCLK
tcycle
(= 18 × tSCLK
)
(= tcycle – tconv
)
1
2
0.24 MHz
60 MHz
100 µs
100 µs
75 µs
25 µs
0.3 µs
99.7 µs
9.2.3.3 Application Curve
Figure 48 provides the results for ENOB achieved from the ADS7046 for case 2 at different throughputs with
different values of sensor output impedance.
12
25 ꢀ and 1.5 nF
250 ꢀ and 1.5 nF
11
10
9
0
200
400
600
800
1000
Sampling Rate (kSPS)
C029
Figure 48. Effective Number of Bits (ENOB) Achieved From the ADS7046 at Different Throughputs
Table 7 shows the results and performance summary for this 12-bit, 10-kSPS DAQ circuit application with a
sensor output impedance of 22 kΩ.
Table 7. Results and Performance Summary for a 12-Bit, 10-kSPS DAQ Circuit for DC Sensor
Measurements
DESIGN PARAMETER
Throughput
GOAL VALUE
10 kSPS
70 dB
ACHIEVED RESULT
10 kSPS
SNR at 100 Hz
THD at 100 Hz
SINAD at 100 Hz
ENOB
70.6 dB
–75 dB
–83.5 dB
69 dB
70.4 dB
11 bits
11.4 bits
Power
20 µW
17 µW
30
版权 © 2016, Texas Instruments Incorporated
ADS7046
www.ti.com.cn
ZHCSH50 –DECEMBER 2016
10 Power Supply Recommendations
10.1 AVDD and DVDD Supply Recommendations
The device has two separate power supplies: AVDD and DVDD.
AVDD powers the analog blocks and is also used as the reference voltage for the analog-to-digital conversion.
Use a low-noise, low-dropout regulator (LDO) or a discrete reference to supply AVDD (see the Reference and
Application Information sections). Always set the AVDD supply to be greater than or equal to the maximum input
signal to avoid code saturation. Decouple the AVDD pin to the GND pin with a 3.3-µF ceramic decoupling
capacitor.
DVDD is used for the interface circuits. Decouple the DVDD pin to the GND pin with a 1-µF ceramic decoupling
capacitor. 图 49 shows the decoupling recommendations.
AVDD
CAVDD
GND
CDVDD
DVDD
图 49. Power-Supply Decoupling
10.2 Optimizing Power Consumed by the Device
In order to best optimize the power consumed by the device, use the following design considerations:
•
Keep the analog supply voltage (AVDD) in the specified operating range and equal to the maximum analog
input voltage.
•
Keep the digital supply voltage (DVDD) in the specified operating range and at the lowest value supported by
the host controller.
•
•
Reduce the load capacitance on the SDO output.
Run the device at the optimum throughput. Power consumption reduces proportionally with the throughput.
10.2.1 Estimating Digital Power Consumption
The current consumption from the DVDD supply depends on the DVDD voltage, the load capacitance on the
SDO pin (CLOAD-SDO), and the output code, and can be calculated as:
IDVDD = CLOAD-SDO × V × f
where:
•
•
•
CLOAD-SDO = Load capacitance on the SDO pin
V = DVDD supply voltage
f = Frequency of transitions on the SDO output
(2)
The number of transitions on the SDO output depends on the output code, and thus changes with the analog
input. The maximum value of f occurs when data output on the SDO change on every SCLK (that is, for output
codes of AAAh or 555h). With an output code of AAAh or 555h, f = 18 MHz and when CLOAD-SDO = 20 pF and
DVDD = 1.8 V, IDVDD = 650 µA.
版权 © 2016, Texas Instruments Incorporated
31
ADS7046
ZHCSH50 –DECEMBER 2016
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11 Layout
11.1 Layout Guidelines
图 50 shows a typical connection diagram for the ADS7046.
AVDD
VDD
DVDD
CDVDD
CAVDD
RFLT
œ
R
VIN
R
+
Device
+
R
œ
VSOURCE
CFLT
GND
GND
Input Driver
图 50. Typical Connection Diagram
图 51 depicts a board layout example for the device for the typical connection diagram in 图 50. The key
considerations for layout are:
•
•
Use a solid ground plane underneath the device and partition the PCB into analog and digital sections
Avoid crossing digital lines with the analog signal path and keep the analog input signals and the reference
input signals away from noise sources.
•
The power sources to the device must be clean and well-bypassed. Use CAVDD decoupling capacitors in close
proximity to the analog (AVDD) power-supply pin.
•
•
•
•
Use a CDVDD decoupling capacitor close to the digital (DVDD) power-supply pin.
Avoid placing vias between the AVDD and DVDD pins and the bypass capacitors.
Connect the ground pin to the ground plane using a short, low-impedance path.
Place the charge kickback filter components close to the device.
Among ceramic surface-mount capacitors, COG (NPO) ceramic capacitors are recommended because these
components provide the most stable electrical properties over voltage, frequency, and temperature changes.
32
版权 © 2016, Texas Instruments Incorporated
ADS7046
www.ti.com.cn
ZHCSH50 –DECEMBER 2016
11.2 Layout Example
AVDD
Plane
RFLT
CDVDD
SCLK
AVDD
AINP
SDO
CS
CFLT
GND
PLANE
图 51. Example Layout
版权 © 2016, Texas Instruments Incorporated
33
ADS7046
ZHCSH50 –DECEMBER 2016
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
TI 高精度实验室培训视频系列
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档：
输入驱动器放大器（单端输入）：
•
•
•
《OPAx836 极低功耗、轨至轨输出、负轨输入、电压反馈运算放大器》
THS403x 100MHz 低噪声高速放大器
《OPAx365 50MHz、零交叉、低失真、高 CMRR、RRI/O、单电源运算放大器》
输入驱动器放大器（全差分输入）：
•
•
THS4551 低噪声 150MHz 全差分精密放大器
《OPAx836 极低功耗、轨至轨输出、负轨输入、电压反馈运算放大器》
基准驱动器：
•
•
《REF19xx 低漂移、低功率、双路输出、VREF 和 VREF/2 电压基准》
《具有集成 ADC 驱动器缓冲器的 REF61xx 高精度电压基准》
类似器件：
•
•
《ADS7042 超低功耗、超小尺寸、12 位、1MSPS、SAR ADC》
《ADS7049-Q1 小型低功耗 12 位、2MSPS SAR ADC》
参考设计：
•
•
TI 设计：采用 73dB SNR、7.5MSPS 时间交织 SAR ADC 且适用于成像应用的模拟前端参考设计
针对双极信号采用运算放大器和 FDA 的单端到差分
12.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
34
版权 © 2016, Texas Instruments Incorporated
ADS7046
www.ti.com.cn
ZHCSH50 –DECEMBER 2016
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2016, Texas Instruments Incorporated
35
ADS7046
ZHCSH50 –DECEMBER 2016
www.ti.com.cn
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。
36
版权 © 2016, Texas Instruments Incorporated
ADS7046
www.ti.com.cn
ZHCSH50 –DECEMBER 2016
PACKAGE OUTLINE
RUG0008A
X2QFN - 0.4 mm max height
SCALE 7.500
PLASTIC QUAD FLATPACK - NO LEAD
1.55
1.45
B
A
PIN 1 INDEX AREA
1.55
1.45
C
0.4 MAX
SEATING PLANE
0.05
0.00
0.08 C
SYMM
0.35
0.25
2X
(0.15)
TYP
0.45
0.35
2X
4
3
5
SYMM
2X
1
4X 0.5
0.25
0.15
2X
7
1
0.3
4X
8
0.2
0.1
0.05
PIN 1 ID
(45 X0.1)
C A
C
B
0.4
0.3
6X
4222060/A 05/14/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
版权 © 2016, Texas Instruments Incorporated
37
ADS7046
ZHCSH50 –DECEMBER 2016
www.ti.com.cn
EXAMPLE BOARD LAYOUT
RUG0008A
X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.3)
2X (0.6)
8
6X (0.55)
1
7
4X (0.25)
SYMM
(1.3)
4X (0.5)
2X (0.2)
3
5
(R0.05) TYP
4
SYMM
(1.35)
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL
UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4222060/A 05/14/2015
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
38
版权 © 2016, Texas Instruments Incorporated
ADS7046
www.ti.com.cn
ZHCSH50 –DECEMBER 2016
EXAMPLE STENCIL DESIGN
RUG0008A
X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.3)
2X (0.6)
8
6X (0.55)
1
7
4X (0.25)
SYMM
(1.3)
4X (0.5)
2X (0.2)
3
5
4
SYMM
(1.35)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICKNESS
SCALE:25X
4222060/A 05/14/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
版权 © 2016, Texas Instruments Incorporated
39
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS7046IRUGR
ACTIVE
X2QFN
RUG
8
3000 RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
9R
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jan-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS7046IRUGR
X2QFN
RUG
8
3000
180.0
8.4
1.6
1.6
0.66
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jan-2018
*All dimensions are nominal
Device
Package Type Package Drawing Pins
X2QFN RUG
SPQ
Length (mm) Width (mm) Height (mm)
183.0 183.0 20.0
ADS7046IRUGR
8
3000
Pack Materials-Page 2
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
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