ADS7142QDQCRQ1 [TI]
具有可编程阈值和主机唤醒功能的汽车类 2 通道 12 位、140kSPS、I2C 兼容型 ADC | DQC | 10 | -40 to 125;
| 型号： | ADS7142QDQCRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可编程阈值和主机唤醒功能的汽车类 2 通道 12 位、140kSPS、I2C 兼容型 ADC | DQC | 10 | -40 to 125 |
| 文件： | 总83页 (文件大小：4390K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
具有可编程阈值和主机唤醒功能的ADS7142-Q1 汽车类双通道12 位、
140kSPS、I2C 兼容型ADC
1 特性
2 应用
• 符合面向汽车应用的AEC-Q100 标准：
通用的电压、电流和温度监测用于：
– 温度等级1：–40°C 至+125°C，TA
• 提供功能安全型
• 数字驾驶舱处理单元
• 驾驶员监控
• 汽车音响主机
– 有助于进行功能安全系统设计的文档
• 小封装尺寸：3mm × 2mm
• 12 位无噪声分辨率
• 不具有处理功能的汽车摄像头模块
3 说明
• 采样率高达140kSPS
ADS7142-Q1 是 12 位 140kSPS 逐次逼近型寄存器
(SAR) 模数转换器 (ADC)，可以自主监测信号，同时
更大限度地提高系统功率、可靠性和性能。该器件使用
具有可编程高低警报阈值、迟滞和事件计数器的数字窗
口比较器，实施每通道事件触发的中断。器件包含一个
在SAR ADC 前端的双通道模拟多路复用器，然后是一
个用于转换和捕捉传感器数据的内部数据缓冲器。
• 高效的主机休眠和唤醒：
– 自主监控功耗为900nW
– 用于事件触发主机唤醒的窗口比较器
• 独立的配置和校准：
– 双通道、伪差分或接地感应输入配置
– 用于校准的可编程阈值
– 内部校准改善了失调电压和漂移
• 错误触发防护：
– 每个通道的可编程阈值
– 用于实现抗噪性能的可编程迟滞
– 用于瞬态抑制的事件计数器
• I2C 接口：
ADS7142-Q1 提供 10 引脚 WSON 封装，可以实现功
耗低至 900nW。该器件体积小巧，功耗低，非常适合
空间受限型应用。
封装信息(1)
封装尺寸（标称值）
器件名称
封装
– 兼容1.65V 至3.6V 的电压范围
– 8 个可配置地址
ADS7142-Q1
WSON (10)
3.00mm x 2.00mm
– 高达3.4MHz（高速）
• 模拟电源：1.65V 至3.6V
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
AVDD
DVDD
Threshold ±
Hysteresis
ALERT
AINP/AIN0
MUX
ADC
FIFO
ADDR
AINM/AIN1
SCL
I2C Interface
SDA
Offset
Calibration
BUSY / RDY
Accumulator
GND
方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS891
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
Table of Contents
7 Detailed Description......................................................21
7.1 Overview...................................................................21
7.2 Functional Block Diagram.........................................21
7.3 Feature Description...................................................22
7.4 Device Functional Modes..........................................30
7.5 Programming............................................................ 41
7.6 Register Map.............................................................44
8 Application and Implementation..................................63
8.1 Application Information............................................. 63
8.2 Typical Applications.................................................. 63
8.3 Power Supply Recommendations.............................68
8.4 Layout....................................................................... 69
9 Device and Documentation Support............................71
9.1 Electrostatic Discharge Caution................................71
9.2 术语表....................................................................... 71
9.3 Trademarks...............................................................71
9.4 接收文档更新通知..................................................... 71
9.5 支持资源....................................................................71
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics: All Modes...........................5
6.6 Electrical Characteristics: Manual Mode.....................7
6.7 Electrical Characteristics: Autonomous Modes...........9
6.8 Electrical Characteristics: High Precision Mode....... 10
6.9 Timing Requirements................................................10
6.10 Switching Characteristics........................................12
6.11 Timing Diagrams..................................................... 13
6.12 Typical Characteristics: All Modes.......................... 14
6.13 Typical Characteristics: Manual Mode.................... 15
6.14 Typical Characteristics: Autonomous Modes..........19
6.15 Typical Characteristics: High-Precision Mode.........20
Information.................................................................... 71
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (October 2019) to Revision B (September 2022)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式........................................................................................1
• 将提到SPI 的旧术语的所有实例更改为控制器和外设...................................................................................... 1
• 向特性部分添加了提供功能安全要点................................................................................................................ 1
• 添加了指向应用部分的链接................................................................................................................................1
• 更改了说明部分中的方框图图像....................................................................................................................... 1
• Changed low-power oscillator to high-speed oscillator in test condition for analog supply current in Electrical
Characteristics : Autonomous Modes section.....................................................................................................9
• Changed high-power oscillator to high-speed oscillator in test condition for digital supply current in Electrical
Characteristics : Autonomous Modes section.....................................................................................................9
• digital................................................................................................................................................................ 10
• Changed Functional Block Diagram figure....................................................................................................... 21
• Added remote ground sense to single-ended configuration discussion of Single-Channel, Single-Ended
Configuration With Remote Ground Sense section..........................................................................................23
• Clarified normal device operation in Offset Calibration section........................................................................ 23
Changes from Revision * (November 2018) to Revision A (October 2019)
Page
• 将文档状态从预告信息更改为量产数据...............................................................................................................1
Copyright © 2022 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
5 Pin Configuration and Functions
GND
AVDD
1
2
3
4
5
10
9
DVDD
SCL
Thermal
Pad
AINP/AIN0
AINM/AIN1
ADDR
8
SDA
7
ALERT
BUSY/RDY
6
Not to scale
图5-1. DQC Package, 10-Pin WSON (Top View)
表5-1. Pin Functions
PIN
NAME
I/O
DESCRIPTION
NO.
1
GND
Supply
Supply
Ground for power supply, all analog and digital signals are referred to this pin.
2
AVDD
Analog supply input, also used as the reference voltage for analog-to-digital conversion.
Single-channel operation: positive analog signal input.
Two-channel operation: analog signal input, channel 0.
3
4
5
6
7
AINP/AIN0
AINM/AIN1
ADDR
Analog input
Analog input
Analog Input
Digital output
Digital output
Single-channel operation: negative analog signal input.
Two-channel operation: analog signal input, channel 1.
Input for selecting the I2C address of the device.
See the I2C Address Selector section for details.
The device pulls this pin high when scanning through channels in a sequence and brings this pin
low when the sequence is completed or aborted.
BUSY/ RDY
ALERT
Active low, open-drain output. The status of this pin is controlled by the digital window comparator
block. Connect a pullup resistor from DVDD to this pin.
8
SDA
SCL
Digital input/output Serial data input/output for the I2C interface. Connect a pullup resistor from DVDD to this pin.
9
Digital input
Supply
Serial clock for the I2C interface. Connect a pullup resistor from DVDD to this pin.
10
DVDD
Digital I/O supply voltage.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–10
–0.3
–40
–60
MAX
UNIT
V
ADDR to GND
AVDD + 0.3
3.9
AVDD to GND
V
DVDD to GND
3.9
V
AINP/AIN0 to GND
AVDD + 0.3
AVDD + 0.3
10
V
AINM/AIN1 to GND
V
Input current on any pin except supply pins
Digital input to GND
Junction temperature, TJ
Storage temperature, Tstg
mA
V
DVDD + 0.3
150
°C
°C
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
±2000
Corner pins (1, 5, 6, and
10)
V(ESD)
Electrostatic discharge
±750
±500
V
Charged-device model (CDM), per AEC
Q100-011
All other pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.65
1.65
–40
NOM
MAX
3.6
UNIT
V
AVDD
DVDD
TA
Analog supply voltage range
Digital supply voltage range
Ambient temperature
3.6
V
125
°C
6.4 Thermal Information
ADS7142-Q1
THERMAL METRIC(1)
DQC (WSON)
10 PINS
61.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
66.3
29.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.1
ΨJT
29.7
ΨJB
RθJC(bot)
6.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2022 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
6.5 Electrical Characteristics: All Modes
at TA = -40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, All Channel Configurations (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ANALOG INPUT (Two-Channel Single-Ended Configuration)
Full-scale input voltage
AINP/AIN0 to GND or AINM/AIN1 to GND
AINP/AIN0 to GND or AINM/AIN1 to GND
0
AVDD
V
V
span(1)
Absolute input voltage
range
AVDD + 0.1
–0.1
ANALOG INPUT (Single-Channel Single-Ended Configuration with Remote Ground Sense)
Full-scale input voltage
AINP/AIN0 to AINM/AIN1
span(1)
0
AVDD
V
V
AINP/AIN0 to GND
AINM/AIN1 to GND
AVDD + 0.1
0.1
–0.1
–0.1
Absolute input voltage
range
ANALOG INPUT (Single-Channel Pseudo-Differential Configuration with Remote Ground Sense)
Full-scale input voltage
AINP/AIN0 to AINM/AIN1
AINP/AIN0 to GND
AVDD/2
AVDD + 0.1
V
V
–AVDD/2
–0.1
span(1)
Absolute input voltage
range
AVDD/2 –
AINM/AIN1 to GND
AVDD/2 + 0.1
0.1
INTERNAL OSCILLATOR
Time period for high-speed
oscillator
tHSO
50
110
300
ns
µs
Time period for low-power
oscillator
tLPO
95.2
DIGITAL INPUT/OUTPUT (SCL, SDA)
VIH
VIL
High-level input voltage
Low-level input voltage
0.7 × DVDD
DVDD
0.3 × DVDD
0.4
V
V
0
0
With 3 mA sink current and DVDD > 2 V
VOL
Low-level output voltage
V
With 3 mA sink current and 1.65 V < DVDD <
2 V
0
3
0.2 × DVDD
VOL = 0.4 V for standard and fast mode (100,
400 kHz)
Low-level output current
(sink)
IOL
mA
mA
VOL = 0.6 V for fast mode (400 kHz)
VOL = 0.4 V fast mode Plus (1 MHz)
6
20
Low-level output current
(sink)
IOL
VOL= 0.4 V high speed (1.7 MHz, 3.4 MHz)
25
II
Input current on pin
10
10
µA
pF
CI
Input capacitance on pin
DIGITAL OUTPUT (BUSY/RDY)
Isource = 200 µA
Isource = 2 mA
Isink = 200 µA
Isink = 2 mA
0.8 × DVDD
DVDD
DVDD
VOH
High-level output voltage
Low-level output voltage
V
V
0.7 × DVDD
0
0
0.2 × DVDD
0.3 × DVDD
VOL
DIGITAL OUTPUT (ALERT)
IOL
Low-level output current
Low-level output voltage
VOL < 0.25 V
Isink = 5 mA
5
mA
V
VOL
0
0.25
3.6
POWER-SUPPLY REQUIREMENTS
AVDD Analog supply voltage
1.65
V
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
at TA = -40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, All Channel Configurations (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DVDD Digital I/O supply voltage
1.65
3.6
V
(1) Ideal Input span, does not include gain or offset error.
Copyright © 2022 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
6.6 Electrical Characteristics: Manual Mode
at TA = -40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, All Channel Configurations (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SAMPLING DYNAMICS
tconv
tacq
Conversion time
Acquisition time
Cycle time
AVDD = 1.65 V to 3.6 V
1.8
7.1
µs
TSCL
µs
AVDD = 1.65 V to 3.6 V
18
tcycle
AVDD = 1.65 V to 3.6 V, SCL = 3.4 MHz
DC SPECIFICATIONS
Resolution
12
Bits
Bits
NMC
DNL
INL
No missing codes
AVDD = 1.65 V to 3.6 V
AVDD = 1.65 V to 3.6 V
12
–0.99
–2.75
–4
Differential nonlinearity
Integral nonlinearity
Offset error
±0.3
±0.5
±0.5
5
1
LSB(1)
2.75 LSB
EO
Post offset calibration
Post offset calibration
4
LSB
dVOS/dT
EG
Offset drift with temperature
Gain error
ppm/°C
±0.03
5
0.1 %FSR
ppm/°C
–0.1
Gain error drift with temperature
AC SPECIFICATIONS
fIN = 2 kHz, AVDD = 3 V,
fSAMPLE = 140 kSPS
68.75
70
68
SNR(2)
Signal-to-noise ratio
dB
dB
dB
fIN = 2 kHz, AVDD = 1.8 V,
fSAMPLE = 140 kSPS
fIN = 2 kHz, AVDD = 3 V,
fSAMPLE = 140 kSPS
–85
–80
69.5
67.5
THD(2) (3)
Total harmonic distortion
fIN = 2 kHz, AVDD = 1.8 V,
fSAMPLE = 140 kSPS
fIN = 2 kHz, AVDD = 3 V,
fSAMPLE = 140 kSPS
68.5
SINAD(2)
Signal-to-noise and distortion
fIN = 2 kHz, AVDD = 1.8 V,
fSAMPLE = 140 kSPS
fIN = 2 kHz, AVDD = 3 V,
fSAMPLE = 140 kSPS
SFDR(2)
BW
Spurious-free dynamic range
90
25
dB
MHz
–3-dB small-signal bandwidth
POWER CONSUMPTION
fSAMPLE = 140 kSPS, SCL = 3.4 MHz
fSAMPLE= 5.5 kSPS, SCL = 100 kHz
265
8
300
fSAMPLE = 140 kSPS, SCL = 3.4 MHz, AVDD =
1.8 V
IAVDD
Analog supply current
µA
160
5
fSAMPLE = 5.5 kSPS, SCL = 100 kHz, AVDD =
1.8 V
fSAMPLE = 140 kSPS, SCL = 3.4 MHz, SDA =
AAA0h
25
2
fSAMPLE = 5.5 kSPS, SCL = 100 kHz, SDA =
AAA0h
IDVDD
Digital supply current
µA
fSAMPLE = 140 kSPS, SCL = 3.4 MHz, AVDD =
1.8 V, SDA = AAA0h
15
IAVDD
IDVDD
Static analog supply current
Static digital supply current
No activity on SCL and SDA
No activity on SCL and SDA
6
2
nA
nA
(1) LSB means least significant byte. See the ADC Transfer Function for details.
(2) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-
scale, unless otherwise specified.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
(3) Calculated on the first nine harmonics of the input frequency.
Copyright © 2022 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
6.7 Electrical Characteristics: Autonomous Modes
at TA = -40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, All Channel Configurations (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SAMPLING DYNAMICS
High-speed oscillator
14
14
tHSO
tLPO
tHSO
tLPO
tHSO
tLPO
tconv
Conversion time
Low-power oscillator
High-speed oscillator
Low-power oscillator
High-speed oscillator
Low-power oscillator
7
4
tacq
Acquisition time
Cycle time
nCLK
nCLK
tcycle
DC SPECIFICATIONS
Resolution
12
±0.5
Bits
LSB
EO
EG
Offset error
Gain error
Post offset calibration
±0.03
%FSR
POWER CONSUMPTION
With low-power oscillator, nCLK = 18
0.75
0.45
With low-power oscillator, AVDD = 1.8 V,
nCLK = 18
IAVDD
Analog supply current
µA
µA
With low-power oscillator, nCLK = 250
With high-speed oscillator, nCLK = 21
0.5
940
With low-power oscillator, nCLK = 18, DVDD
= 3.3 V
0.15
0.25
0.15
0.15
With low-power oscillator, DVDD = 1.8 V,
nCLK = 18
IDVDD
Digital supply current
With low-power oscillator, nCLK = 250,
DVDD = 3.3 V
With high-speed oscillator, nCLK = 21,
DVDD = 3.3 V
IAVDD
IDVDD
Static analog supply current
Static digital supply current
No activity on SCL and SDA
No activity on SCL and SDA
5
nA
nA
0.6
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
6.8 Electrical Characteristics: High Precision Mode
at TA = -40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, All Channel Configurations (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DC SPECIFICATIONS
Resolution(2)
16
15.4
Bits
ENOB Effective number of bits
With DC input of AVDD / 2(3)
Post offset calibration
EO
EG
Offset error
Gain error
±10
LSB
±0.03
%FSR
POWER CONSUMPTION
With low-power oscillator, nCLK = 18
0.6
0.3
With low-power oscillator, AVDD = 1.8 V,
nCLK = 18
IAVDD
Analog supply current
µA
µA
With low-power oscillator, nCLK = 250
With high-speed oscillator, nCLK = 21
0.5
980
With low-power oscillator, nCLK = 21, DVDD
= 3.3 V
0.2
0.25
0.2
With low-power oscillator, DVDD = 1.8 V,
nCLK = 21
IDVDD
Digital supply current
With low-power oscillator, nCLK = 250,
DVDD = 3.3 V
With high-speed oscillator, nCLK = 21,
DVDD = 3.3 V
0.2
IAVDD
IDVDD
Static analog supply current
Static supply current
No activity on SCL and SDA
No activity on SCL and SDA
5
nA
nA
0.7
(1) Sampling dynamics for high precision mode are same as for autonomous modes.
(2) See 方程式5
(3) For DC input, ENOB = Ln[FSR/Standard deviation of Codes]/Ln[2].
6.9 Timing Requirements
at TA = -40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, All Channel Configurations (unless otherwise noted)(1)
PARAMETER
MIN
MAX
UNIT
STANDARD MODE (100 kHz)
fSCL
SCL clock frequency
0
4
100
kHz
µs
µs
µs
µs
µs
ns
µs
µs
pF
tHD-STA
tLOW
Hold time (repeated) START condition
Low period of SCL
4.7
4
tHIGH
High period of SCL
tSU-STA
tHD-DAT
tSU-DAT
tSU-STO
tBUF
Setup time for a repeated start condition
Data hold time
4.7
0
(2) (3)
Data setup time
250
4
Data setup time
Bus free time between a STOP and START condition
Capacitive load on each line
4.7
Cb
400
400
FAST MODE (400 kHz)
fSCL
SCL clock frequency
0
0.6
1.3
0.6
0.6
0
kHz
µs
tHD-STA
tLOW
Hold time (repeated) START condition
Low period of SCL
µs
tHIGH
High period of SCL
µs
tSU-STA
tHD-DAT
Setup time for a repeated start condition
Data hold time
µs
µs
Copyright © 2022 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
6.9 Timing Requirements (continued)
at TA = -40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, All Channel Configurations (unless otherwise noted)(1)
PARAMETER
MIN
100
0.6
MAX
UNIT
ns
tSU-DAT
tSU-STO
tBUF
Data setup time
Data setup time
µs
Bus free time between a STOP and START condition
Capacitive load on each line
1.3
µs
Cb
400
pF
FAST MODE PLUS (1000 kHz)
fSCL
SCL clock frequency
0
0.26
0.5
1000
kHz
µs
µs
µs
µs
µs
ns
µs
µs
pF
tHD-STA
tLOW
Hold time (repeated) START condition
Low period of SCL
tHIGH
High period of SCL
0.26
0.26
0
tSU-STA
tHD-DAT
tSU-DAT
tSU-STO
tBUF
Setup time for a repeated start condition
Data hold time
Data setup time
50
Data setup time
0.26
0.5
Bus free time between a STOP and START condition
Capacitive load on each line
Cb
550
1.7
HIGH SPEED MODE (1.7 MHz, Cb = 400 pF max)
fSCLH
SCLH clock frequency
Hold time (repeated) START condition
Low period of SCL
0
160
320
120
160
0
MHz
ns
tHD-STA
tLOW
ns
tHIGH
High period of SCL
ns
tSU-STA
tHD-DAT
tSU-DAT
tSU-STO
Cb
Setup time for a repeated start condition
Data hold time
ns
150
ns
Data setup time
10
ns
Data setup time
160
ns
Capacitive load on each line
100
3.4
pF
HIGH SPEED MODE (3.4 MHz, Cb = 100 pF max)
fSCLH
SCLH clock frequency
Hold time (repeated) START condition
Low period of SCL
0
160
160
60
MHz
ns
tHD-STA
tLOW
ns
tHIGH
High period of SCL
ns
tSU-STA
tHD-DAT
tSU-DAT
tSU-STO
Cb
Setup time for a repeated start condition
Data hold time
160
0
ns
70
ns
Data setup time
10
ns
Data setup time
160
ns
Capacitive load on each line
100
pF
(1) All values referred to VIH(min) (0.7 DVDD) and VIL(max) (0.3 DVDD).
(2) tHD-DAT is the data hold time that is measured from the falling edge of SCL and applies to data in transmission and the acknowledge.
(3) The maximum tHD-DAT can be 3.45 µs and 0.9 µs for standard-mode and fast-mode, but must be less than the maximum of tVD-DAT or
tVD-ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If
the clock is streched, the data must be valid by the setup time before being released.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
6.10 Switching Characteristics
at TA = -40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, All Channel Configurations (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
STANDARD MODE (100 kHz)
trCL
Rise time of SCL
1000
1000
300
ns
ns
ns
ns
µs
µs
trDA
Rise time of SDA
Fall time of SCL
Fall time of SDA
Data valid time
Data hold time
tfCL
tfDA
300
(2)
(2)
tVD-DAT
tVD-ACK
3.45
3.45
FAST MODE (400 kHz)
trCL
Rise time of SCL
20
20
300
300
300
300
0.9
ns
ns
ns
ns
µs
µs
trDA
Rise time of SDA
Fall time of SCL
Fall time of SDA
Data valid time
Data hold time
tfCL
20 × DVDD/3.6
20 × DVDD/3.6
tfDA
tVD-DAT
tVD-ACK
0.9
Pulse duration of spikes suppressed by the
input filter
(3)
tSP
0
50
ns
FAST MODE PLUS (1000 kHz)
trCL
Rise time of SCL
Rise time of SDA
Fall time of SCL
Fall time of SDA
Data valid time
Data hold time
120
120
120
120
0.45
0.45
ns
ns
ns
ns
µs
µs
trDA
tfCL
20 × DVDD/3.6
20 × DVDD/3.6
tfDA
tVD-DAT
tVD-ACK
Pulse duration of spikes suppressed by the
input filter
tSP
0
50
ns
HIGH SPEED MODE (1.7 MHz, Cb = 400 pF max)
trCL
Rise time of SCLH
20
20
80
ns
ns
Rise time of SCLH after a repeated start
condition and after an acknowledge bit
trCL1
160
trDA
tfCL
tfDA
Rise time of SDAH
Fall time of SCLH
Fall time of SDAH
20
20
20
160
80
ns
ns
ns
160
Pulse duration of spikes suppressed by the
input filter
tSP
0
10
ns
HIGH SPEED MODE (3.4 MHz, Cb = 100 pF max)
trCL
Rise time of SCLH
10
10
40
80
ns
ns
Rise time of SCLH after a repeated start
condition and after an acknowledge bit
trCL1
trDA
tfCL
tfDA
Rise time of SDAH
Fall time of SCLH
Fall time of SDAH
10
10
10
80
40
80
ns
ns
ns
Pulse duration of spikes suppressed by the
input filter
tSP
0
10
ns
(1) All values referred to VIH(min) ( 0.7 DVDD ) and VIL(max) ( 0.3 DVDD ).
(2) tVD-DAT = time for data signal from SCL LOW to SDA output.
(3) Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.
Copyright © 2022 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
6.11 Timing Diagrams
tf
tr
tSU-DAT
70%
SDA
…
70%
30%
cont.
30%
tHD-DAT
tVD-DAT
tf
tr
tHIGH
70%
30%
70%
30%
70%
30%
SCL
70%
…
tHD-STA
30%
cont.
9th clock
tLOW
S
1/fSCL
1st clock cycle
tBUF
. . . SDA
tVD-ACK
tSU-STA
tHD-STA
tSP
tSU-STO
70%
30%
. . . SCL
Sr
P
S
9th clock
VIL = 0.3VDD
VIH = 0.7VDD
图6-1. Timing Diagram for Standard Mode, Fast Mode, and Fast Mode Plus
trDA
Sr
Sr
P
tfDA
0.7 x VDD
0.3 x VDD
SDAH or SDA
tHD-DAT
tSU-STO
tSU-STA
tHD-STA
tSU-DAT
0.7 x VDD
0.3 x VDD
SCLH or SCL
tFCL
(A)
trCL1
trCL1
(A)
trCL
tLOW
tHIGH
tLOW
tHIGH
= MCS current source pull-up
= Rp resistor pull-up
A. First rising edge of the SCLH signal after Sr and after each acknowledge bit.
图6-2. Timing Diagram for High-Speed Mode
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
6.12 Typical Characteristics: All Modes
at TA = 25°C, AVDD = 3 V, DVDD = 3.3 V, and two-channel single-ended configuration (unless otherwise noted)
60
56
52
48
44
40
160
140
120
100
80
60
-40
-7
26
59
92
125
-40
-7
26
59
92
125
Free-Air Temperature (èC)
Free-Air Temperature (èC)
ADS7
ADS7
图6-3. High-Speed Oscillator Time Period vs Temperature
图6-4. Low-Power Oscillator Time Period vs Temperature
Copyright © 2022 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
6.13 Typical Characteristics: Manual Mode
at TA = 25°C, AVDD = 3 V, DVDD = 3.3 V, and two-channel single-ended configuration (unless otherwise noted)
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
0
10000
20000 30000
fIN, Input Frequency (Hz)
40000
50000
0
10000
20000 30000
fIN, Input Frequency (Hz)
40000
50000
ADS7
ADS7
SNR = 69.6 dB, THD = –84 dB, ENOB = 11.2,
SNR = 71.3 dB, THD = –87 dB, ENOB = 11.5,
fsample = 140 kSPS, SFDR = 87 dB, AVDD = 1.8 V
fsample = 140 kSPS, SFDR = 89.3 dB, AVDD = 3 V
图6-5. Typical FFT in Manual Mode
图6-6. Typical FFT in Manual Mode
73
72
71
70
69
68
72
71
70
69
68
67
SNR
SINAD
SNR
SINAD
-40
-7
26
59
92
125
1.8
2.16
2.52
2.88
3.24
3.6
Free-Air Temperature (èC)
Free-Air Temperature (èC)
ADS7
ADS7
fsample = 140 kSPS
fsample = 140 kSPS
图6-7. SNR and SINAD in Manual Mode vs Temperature
图6-8. SNR and SINAD in Manual Mode vs AVDD
-82
91
-83.6
-85.2
-86.8
-88.4
-90
90.4
89.8
89.2
88.6
88
-40
-7
26
59
92
125
-40
-7
26
59
92
125
Free-Air Temperature (èC)
Free-Air Temperature (èC)
ADS7
ADS7
fsample = 140 kSPS
fsample = 140 kSPS
图6-9. THD in Manual Mode vs Temperature
图6-10. SFDR in Manual Mode vs Temperature
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
6.13 Typical Characteristics: Manual Mode (continued)
at TA = 25°C, AVDD = 3 V, DVDD = 3.3 V, and two-channel single-ended configuration (unless otherwise noted)
-78
-81
-84
-87
-90
-93
60000
40000
20000
0
3790
2047
3046
2049
2048
1.8
2.16
2.52
2.88
3.24
3.6
ADS7
Output Code
AVDD (V)
ADS7
Mean code = 2047.9, standard deviation = 0.32
图6-12. Typical DC Code Spread in Manual Mode
fsample = 140 kSPS
图6-11. THD in Manual Mode vs AVDD
3
2.6
2.2
1.8
1.4
1
2.5
2.1
1.7
1.3
0.9
0.5
-40
-7
26
59
92
125
1.8
2.16
2.52
2.88
3.24
3.6
Free-Air Temperature (èC)
AVDD (V)
ADS7
ADS7
图6-13. Offset Error in Manual Mode vs Temperature
图6-14. Offset Error in Manual Mode vs AVDD
0.05
0.07
0.052
0.034
0.016
-0.002
-0.02
0.03
0.01
-0.01
-0.03
-0.05
-40
-7
26
59
92
125
1.8
2.16
2.52
2.88
3.24
3.6
Free-Air Temperature (èC)
AVDD (V)
ADS7
ADS7
图6-15. Gain Error in Manual Mode vs Free-Air Temperature
图6-16. Gain Error in Manual Mode vs AVDD
Copyright © 2022 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
6.13 Typical Characteristics: Manual Mode (continued)
at TA = 25°C, AVDD = 3 V, DVDD = 3.3 V, and two-channel single-ended configuration (unless otherwise noted)
0.5
0.3
0.5
0.3
0.1
0.1
-0.1
-0.3
-0.5
-0.1
-0.3
-0.5
0
819
1638
2457
3276
4095
0
819
1638
2457
3276
4095
Output Code
Output Code
ADS7
ADS7
AVDD = 3 V
图6-17. Typical DNL in Manual Mode
AVDD = 1.8 V
图6-18. Typical DNL in Manual Mode
1.2
0.6
0
1
0.6
0.2
-0.2
-0.6
-1
-0.6
-1.2
0
819
1638
2457
3276
4095
0
819
1638
2457
3276
4095
Output Code
Output Code
ADS7
ADS7
AVDD = 3 V
图6-19. Typical INL in Manual Mode
AVDD = 1.8 V
图6-20. Typical INL in Manual Mode
1
0.6
0.2
-0.2
-0.6
-1
1
0.6
0.2
-0.2
-0.6
-1
Maximum
Minimum
Maximum
Minimum
-40
-7
26
59
92
125
1.8
2.16
2.52
2.88
3.24
3.6
Free-Air Temperature (èC)
AVDD (V)
ADS7
ADS7
图6-21. DNL in Manual Mode vs Temperature
图6-22. DNL in Manual Mode vs AVDD
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
6.13 Typical Characteristics: Manual Mode (continued)
at TA = 25°C, AVDD = 3 V, DVDD = 3.3 V, and two-channel single-ended configuration (unless otherwise noted)
1
0.5
0
1
0.4
-0.2
-0.8
-1.4
-2
Maximum
Minimum
Maximum
Minimum
-0.5
-1
-1.5
-40
-7
26
59
92
125
1.8
2.16
2.52
2.88
3.24
3.6
Free-Air Temperature (èC)
AVDD (V)
ADS7
ADS7
图6-23. INL in Manual Mode vs Temperature
图6-24. INL in Manual Mode vs AVDD
350
300
250
200
150
100
260
254
248
242
236
230
1.8
2.16
2.52
2.88
3.24
3.6
-40
-7
26
59
92
125
AVDD (V)
Free-Air Temperature (èC)
ADS7
ADS7
fSample = 140 kSPS, SCL = 3.4 MHz
图6-25. IAVDD in Manual Mode vs AVDD
图6-26. IAVDD in Manual Mode vs Temperature
20
17.5
15
0.8
0.6
0.4
0.2
0
AVDD = 1.8 V
AVDD = 3 V
12.5
10
7.5
5
2.5
0
-0.2
0
500
1000
1500
2000
2500
3000
3500
-40
-7
26
59
92
125
SCL (kHz)
Free-Air Temperature (èC)
ADS7
ADS7
DVDD = 1.8 V
图6-27. IDVDD in Manual Mode vs SCL
No activity on SCL and SDA
图6-28. Static IAVDD in Manual Mode vs Temperature
Copyright © 2022 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
6.14 Typical Characteristics: Autonomous Modes
at TA = 25°C, AVDD = 3 V, DVDD = 3.3 V, and two-channel single-ended configuration (unless otherwise noted)
12
8
6.4
4.8
3.2
1.6
0
9
6
3
0
0
45
90
135
nCLK
180
225
270
0
45
90
135
nCLK
180
225
270
ADS7
AINC
Input voltage = 1.5 V, CH0, high-speed oscillator,
stop burst mode
Input voltage = 1.5 V, CH0, low-power oscillator,
stop burst mode
图6-29. Analog Input Current in Autonomous Modes vs nCLK
图6-30. Analog Input Current in Autonomous Modes vs nCLK
1500
1500
AVDD = 1.8 V
AVDD = 3 V
AVDD = 1.8 V
AVDD = 3 V
1200
900
600
300
0
1200
900
600
300
0
-40
-7
26
59
92
125
-40
-7
26
59
92
125
Free-Air Temperature (èC)
Free-Air Temperature (èC)
ADS7
Auto
Stop burst mode, low-power oscillator, nCLK = 25
Stop burst mode, high-speed oscillator, nCLK = 25
图6-31. IAVDD in Autonomous Modes vs Temperature
图6-32. IAVDD in Autonomous Modes vs Temperature
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
6.15 Typical Characteristics: High-Precision Mode
at TA = 25°C, AVDD = 3 V, DVDD = 3.3 V, and two-channel single-ended configuration (unless otherwise noted)
10
0.03
0.018
0.006
-0.006
-0.018
-0.03
7
4
1
-2
-40
-7
26
59
92
125
-40
-7
26
59
92
125
Free-Air Temperature (èC)
Free-Air Temperature(èC)
Offs
Gain
图6-33. Offset Error in High-Precision Mode vs Temperature
图6-34. Gain Error in High-Precision Mode vs Temperature
1200
1200
AVDD = 1.8 V
AVDD = 3 V
AVDD = 1.8 V
AVDD = 3 V
900
600
300
0
900
600
300
0
-40
-7
26
59
92
125
-40
-7
26
59
92
125
Free-Air Temperature (èC)
Free-Air Temperature (èC)
ADS7
IAVD
Low-power oscillator, nCLK = 25
High-speed oscillator, nCLK = 25
图6-36. IAVDD in High-Precision Mode vs Temperature
图6-35. IAVDD in High-Precision Mode vs Temperature
Copyright © 2022 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7 Detailed Description
7.1 Overview
The ADS7142-Q1 is a small size, dual-channel, 12-bit programmable sensor monitor with an integrated analog-
to-digital converter (ADC), input multiplexer, digital comparator, data buffer, accumulator, and internal oscillator.
The input multiplexer can be either configured as two single-ended channels, one single-ended channel with
remote ground sensing, or one pseudo-differential channel where the input can swing to approximately AVDD /
2. The device includes a digital window comparator with a dedicated ALERT pin, which can be used to alert the
host when a programmed high or low threshold is crossed. The device address is configured by the I2C address
selector block. The device uses internal oscillators (low power or high speed) for conversion. The start of
conversion is controlled by the host in manual mode or by the device in the autonomous modes.
The device also features a data buffer and an accumulator. The data buffer can store up to 16 conversion results
of the ADC in the autonomous modes and the accumulator can accumulate up to 16 conversion results of the
ADC in high-precision mode.
The device includes an offset calibration to calibrate the offset.
7.2 Functional Block Diagram
AVDD
DVDD
Threshold ±
Hysteresis
ALERT
AINP/AIN0
AINM/AIN1
MUX
ADC
FIFO
I2C Interface
ADDR
SCL
SDA
Offset
Calibration
BUSY / RDY
Accumulator
GND
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.3 Feature Description
7.3.1 Analog Input and Multiplexer
图 7-1 shows a small-signal equivalent circuit for the analog input pins. The device includes a two-channel
analog multiplexer with each input pin having ESD protection diodes to AVDD and GND. The sampling switches
are represented by ideal switches SW1 and SW2 in series with resistors Rs 1 and Rs2 (typically 150 Ω). The
sampling capacitors, Cs1 and Cs2, are typically 15 pF. The multiplexer configuration is set by the
CH_INPUT_CFG register.
During acquisition, switches SW1 and SW2 are closed to allow the input signal to charge the internal sampling
capacitors.
During conversion, switches SW1 and SW2 are opened to disconnect the input signal from the sampling
capacitors.
The analog inputs of the device are optimized to be driven by a high-impedance source (up to 100 kΩ) in
autonomous modes or in high precision mode with a low-power oscillator. When using the high-speed oscillator,
drive the analog inputs of the ADC with an external amplifier in autonomous modes or in high precision mode. 图
6-29 and 图6-30 provide the analog input current for CH0 and CH1 of the device.
图 7-2, 图 7-3, and 图 7-4 provide a simplified circuit for analog input for input configurations described in the
Two-Channel, Single-Ended Configuration, Single-Channel, Single-Ended Configuration With Remote Ground
Sense, and Single-Channel, Pseudo-Differential Configuration sections, respectively. The analog multiplexer
supports following input configurations (set by writing into the CH_INPUT_CFG register).
AVDD
AVDD
CH0
SW1
Rs1
AINP/AIN0
CH0
CH1
Cs1
SW1
Rs1
AINP/AIN0
GND
Cs1
V_BIAS
Cs2
AVDD
AVDD
MUX
MUX
V_BIAS
Cs2
CH1
SW2
Rs2
AINM/AIN1
SW2
Rs2
AINM/AIN1
GND
GND
GND
CHANNEL_INPUT_CFG_REG
图7-2. Two-Channel, Single-Ended Configuration
CHANNEL_INPUT_CFG_REG
图7-1. Equivalent Circuit for Analog Input
AVDD
AVDD
SW1
Rs1
AVDD/2
AINP/AIN0
SW1
Rs1
AINP/AIN0
Cs1
Cs1
GND
GND
MUX
MUX
V_BIAS
Cs2
V_BIAS
Cs2
AVDD/2 + 100mV
AVDD/2-100mV
GND + 100mV
GND -100mV
AVDD/2
SW2
Rs2
AINM/AIN1
SW2
Rs2
GND
AINM/AIN1
GND
GND
CHANNEL_INPUT_CFG_REG
CHANNEL_INPUT_CFG_REG
图7-4. Single-Channel, Pseudo-Differential
图7-3. Single-Channel, Single-Ended
Configuration With Remote Ground Sensing
Configuration
7.3.1.1 Two-Channel, Single-Ended Configuration
图 7-2 shows a simplified block diagram showing a two-channel, single-ended configuration. Set the
CH0_CH1_IP_CFG bits = 00b or 11b to select this configuration. This configuration is also the default for the
device after power up. In this configuration, CS2 always samples the GND pin and CS1 samples the input signal
provided on channel 0 (AINP/AIN0) or channel 1 (AINM/AIN1) based on the channel selection. Each analog
input channel can accept input signals in the range 0 V to AVDD V.
Copyright © 2022 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
On power-up, the device wakes up in manual mode with two-channel, single-ended configuration and samples
CH0 only. This configuration can also be set by setting OPMODE_SEL to 000b or 001b,
The device can be configured to sample either CH0 or CH1 or both channels by setting bits in the
AUTO_SEQ_CHEN register to select the channels.
• To select a channel in AUTO sequence, set the AUTO_SEQ_CHx bit in the AUTO_SEQ_CHEN register to 1.
• Set the bits in the OPMODE_SEL register to 100b or 101b for manual mode with AUTO sequence.
• Set the bits in the OPMODE_SEL register to 110b for autonomous modes with AUTO sequence.
• Set the bits in the OPMODE_SEL register to 111b for high-precision mode with AUTO sequence.
7.3.1.2 Single-Channel, Single-Ended Configuration With Remote Ground Sense
See 图 7-3 for a simplified block diagram showing a single-channel, single-ended configuration with remote
ground sense. Set the CH0_CH1_IP_CFG bits = 01b to select this configuration. In this configuration, CS1
samples the input signal provided on the AINP/AIN0 pin, whereas CS2 samples the input signal provided on the
AINM/AIN1 pin. The AINP/AIN0 pin can accept input signals in the range 0 V to AVDD V and the AINM/AIN1 pin
can accept input signals in the range –100 mV to +100 mV. This input configuration is useful in systems where
the sensor or the signal conditioning block is placed far from the device and there can be a small difference
between the ground potentials. In this channel configuration, remove channel 1 from the AUTO sequence by
setting the AUTO_SEQ_CH1 bit to 0. Selecting channel 1 in the AUTO sequence leads to an error condition and
the device sets an error flag in the SEQUENCE_STATUS register.
7.3.1.3 Single-Channel, Pseudo-Differential Configuration
See 图 7-4 for a simplified block diagram showing a single-channel, pseudo-differential configuration. Set the
CH0_CH1_IP_CFG bits = 10b to select this configuration. In this configuration, CS1 samples the input signal
provided on the AINP/AIN0 pin, whereas CS2 samples the input signal provided on the AINM/AIN1 pin. The
AINP/AIN0 pin can accept input signals in the range of 0 V to AVDD V and the AINM/AIN1 pin can accept input
signals in the range of (AVDD / 2) – 100 mV to (AVDD / 2) + 100 mV. This input configuration is useful to
interface with sensors that provide a pseudo-differential signal with a negative output of AVDD / 2 (such as an
electrochemical gas sensor). In this channel configuration, remove channel 1 from the AUTO sequence by
setting the AUTO_SEQ_CH1 bit to 0. Selecting channel 1 in the AUTO sequence leads to an error condition and
the device sets an error flag in the SEQUENCE_STATUS register.
7.3.2 Offset Calibration
The device automatically calibrates the offset on power up. The offset can also be calibrated during normal
device operation by setting the TRIG_OFFCAL bit in the OFFSET_CAL register. During offset calibration, the
sampling switches are open (图 7-1) and the device keep the BUSY/RDY pin high. The device calculates the
offset error and corrects for this error for subsequent conversions. To nullify the change in offset resulting from
change in temperature or in AVDD voltage, periodically perform this calibration.
7.3.3 Reference
The device uses the analog supply voltage (AVDD) as a reference for the analog-to-digital conversion process.
Place a 220-nF, low-ESR ceramic decoupling capacitor between the AVDD pin and the GND pin, close to the
AVDD pin; see the Power Supply Recommendations section.
7.3.4 ADC Transfer Function
The ADC provides data in straight binary format. The ADC resolution can be computed by 方程式1:
1 LSB = VREF / 2N
(1)
where:
• VREF = AVDD
• N = 12 for autonomous monitoring modes and manual mode
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
图 7-5 and 图 7-6 show the ideal transfer characteristics for single-ended input and pseudo-differential input,
respectively. 表7-1 lists the digital output codes for the transfer functions.
PFSC
MC + 1
MC
NFSC+1
NFSC
VIN
1 LSB
VREF/2
(VREF/2 + 1 LSB)
(VREF œ 1 LSB)
图7-5. Ideal Transfer Characteristics for Single-Ended Configurations
PFSC
MC + 1
MC
NFSC+1
NFSC
VIN
(-VREF/2 + 1 LSB)
0
1 LSB
(VREF/2 œ 1 LSB)
图7-6. Ideal Transfer Characteristics for Pseudo-Differential Configuration
表7-1. Transfer Characteristics
IDEAL
OUTPUT
CODE
INPUT VOLTAGE FOR PSEUDO
INPUT VOLTAGE FOR SINGLE-ENDED INPUT
CODE
DESCRIPTION
DIFFERENTIAL INPUT
NFSC
NFSC + 1
MC
Negative full-scale code
000
001
800
801
FFF
≤1 LSB
1 LSB to 2 LSBs
≤(–VREF / 2 + 1) LSB
(–VREF / 2 + 1) to (–VREF / 2 + 2) LSB
0 LSB to 1 LSB
—
(VREF / 2) to (VREF / 2) + 1 LSB
(VREF / 2) + 1 LSB to (VREF / 2) + 2 LSBs
≥VREF –1 LSB
Mid code
1 LSB to 2 LSB
MC + 1
PFSC
—
Positive full-scale code
≥VREF / 2 –1 LSB
7.3.5 Oscillator and Timing Control
The device uses one of the two internal oscillators (low-power oscillator or high-speed oscillator) for converting
the analog input voltage into a digital output code.
Copyright © 2022 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
The steps for selecting the oscillator and setting the sampling speed are:
1. Select the low-power oscillator (OSC_SEL = 1b) to monitor slow-moving signals (< 300 Hz) at extremely low-
power consumption and sampling speeds (< 600 SPS). Select the high-speed oscillator (OSC_SEL = 0b) to
scan the sensor signals with faster sampling speed (> 50 kHz).
2. Set the sampling speed by programming the NCLK_SEL register:
Oscillator frequency
fS =
(2)
• fs = Sampling speed.
• Oscillator frequency = 1 / tHSO or 1 / tLPO depending on the OSC_SEL bit; see the Specifications section for
1 / tHSO or 1 / tLPO
.
• nCLK is the number of clocks in one conversion cycle (see the NCLK_SEL register).
7.3.6 I2C Address Selector
The I2C address for the device is determined by connecting external resistors on the ADDR pin. The device
address is selected on power-up based on the resistor values. The device retains this address until the next
power up, until the next device reset, or until the device receives a command to program the address (General
Call With Write Software Programmable Part of the Target Address). 图 7-7 provides the connection diagram for
the ADDR pin and 表7-2 provides the resistor values for selecting a different addresses of the device.
AVDD
R1
ADDR
R2
图7-7. External Resistor Connection Diagram for the ADDR Pin
表7-2. I2C Address Selection
RESISTORS
ADDRESS
R1 (2)
0 Ω
R2(2)
DNP(1)
0011111b (1Fh)
0011110b (1Eh)
0011101b (1Dh)
0011100b (1Ch)
0011000b (18h)
0011001b (19h)
0011010b (1Ah)
0011011b (1Bh)
DNP(1)
11 kΩ
33 kΩ
100 kΩ
DNP(1)
DNP(1)
DNP(1)
DNP(1)
DNP(1)
DNP(1)
0Ωor DNP(1)
11 kΩ
33 kΩ
100 kΩ
(1) DNP = Do not populate.
(2) Tolerance for R1, R2 < ±5%.
7.3.7 Data Buffer
When operating in autonomous monitoring mode, the device can use the internal data buffer for data storage.
The internal data buffer is 16-bit wide and 16-words deep and follows the first-in, first-out (FIFO) approach.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.3.7.1 Filling of the Data Buffer
The write operation to the data buffer starts and stops as per the settings in the DATA_BUFFER_OPMODE
register. The DATA_BUFFER_STATUS register provides the number of entries filled in the data buffer and this
register can be read during an active sequence to get the current status of the data buffer.
The time between two consecutive conversions is set by the NCLK_SEL register and 方程式 3 provides the
relationship for time between two consecutive conversions of the same channel and nCLK parameter.
tcc = k × nCLK × OscillatorTimePeriod
(3)
where:
• tcc = Time between two consecutive conversions of the same channel, tcc = k × tcycle
• k = Number of channels enabled in the device sequence
• nCLK = Number of clocks used by the device for one conversion cycle
• Oscillator timer period = tLPO or tHSO depending on the OSC_SEL value; see the Specifications section for
tLPO or tHSO
The format of the 16-bit contents of each entry in the data buffer are set by programming the
DOUT_FORMAT_CFG register. The DATA_OUT_CFG register enables the channel ID and DATA_VALID flag in
the data buffer. The channel ID represents the channel number for the data entry in the data buffer. DATA_VALID
is set to zero in either of the following conditions:
• If the entry in the data buffer is not filled after the last start of the sequence
• If the I2C controller tries to read more than 16 entries from the data buffer, the device provides zeros with
DATA_VALID set to zero
At the end of the write operation, the data buffer always has results of 16 (or less) consecutive conversions. The
data buffer is filled in the order that the data are converted by the ADC. The channels converted by the ADC are
controlled by the AUTO_SEQ_CHEN register. The entries that are not filled during an active sequence are filled
with zeros.
7.3.7.2 Reading Data From the Data Buffer
The ADC drives a logic 0 on the BUSY/RDY pin after completion of the sequence when auto-sequencing is
disabled or after the SEQ_ABORT bit is set. As illustrated in 图 7-8, the device provides the contents of the data
buffer (in FIFO fashion) on receiving the I2C read frame, which consists of the device address and the read bit
set to 1.
S
Device Address (7 Bits)
R
A
MSB for Data Buffer Entry 0
A
LSB for Data Buffer Entry 0
A
MSB for Data Buffer Entry 1
A
LSB for Data Buffer Entry 15
N
P/Sr
Data from Host to Device
Data from Device to Host
图7-8. Reading Data Buffer (16 Bit Words × 16 Words)
The device returns zeroes with the DATA VALID flag set to zero for all I2C read frames received after all the valid
data words from the data buffer are read or when an I2C read frame is issued during an active sequence
(indicated by a high on the BUSY/RDY pin). The I2C controller must provide a NACK followed by a STOP or
RESTART condition in an I2C frame to finish the reading process. The data buffer is reset by setting the
SEQ_START bit or after resetting the device.
Copyright © 2022 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.3.8 Accumulator
When operating in high-precision mode, the device offers a 16-bit internal accumulator per channel. The
accumulator for a channel is enabled only if that channel is selected in the channel scanning sequence. The
accumulator adds sixteen 12-bit conversion results. The result of adding sixteen 12-bit words is one 16-bit word.
The time between two consecutive conversions for accumulation is controlled by the NCLK_SEL register and 方
程式 3 provides the relationship for time between two consecutive conversions of same channel and nCLK
parameter.
The accumulated data can be read from the ACC_CHx_MSB and ACC_CHx_LSB registers in the device. The
ACCUMULATOR_STATUS register provides the number of accumulations done in the accumulator since last
conversion. This register can be read during an active sequence to get the current status of the accumulator.
The accumulator is reset when setting the SEQ_START bit or on resetting the device.
方程式4 provides the relationship between high precision data and ADC conversion results.
16
High Precision Data for CHx =
Conversion Result[k] for CHx
ƒ
k=1
(4)
(5)
方程式5 provides the value of LSB in high precision mode for the accumulated result.
AVDD
216
1 LSB =
7.3.9 Digital Window Comparator
The internal digital window comparator is available in all modes. In autonomous modes with thresholds
monitoring and diagnostics, the digital window comparator controls the filling of the data into the FIFO and the
output of the ALERT pin. In the remaining modes, the digital window comparator only controls the output of the
ALERT pin. 图7-9 provides the block diagram for digital window comparator.
DWC_BLOCK_EN
ALERT_EN_CH1
Channel 1
ALERT_EN_CH0
Channel 0
High Side Comparator
(High Side Threshold, Hysteresis)
for CH0
High Side
Counter
S
R
High Latched Flag for CH0
Q
Write Bit to
Reset
End of
Conversion
Conversion Result for CH0
ADC
OR
ALERT
OR
R
S
Low Side
Counter
Low Latched Flag for CH0
Q
(Low Side Threshold, Hysteresis)
for CH0
Low Side Comaparator
图7-9. Digital Comparator Block Diagram
The low-side threshold, high-side threshold, and hysteresis parameters are independently programmable for
each input channel. 图 7-10 illustrates the comparison thresholds and hysteresis for the two comparators. A pre-
ALERT event counter after each comparator counts the output of the comparator and sets the latched flags. The
pre-ALERT event counter settings are common to the two channels.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
NOTE: PRE_ALT_MAX_EVENT_COUNT = 70h
(waits for 8 counts to set alert)
3
2
8
2
7
High Threshold
4
1
3
6
1
4
5
5
High Threshold - Hysteresis
6
Counter Reset because the high-side-comparator reset
before 8.
Counter Reset because the high-side-comparator reset
before 8.
Low Threshold + Hysteresis
Low Threshold
7
5
4
6
3
1
2
High Side Comparator
(Internal Only Signal)
Low Side Comparator
(Internal Only Signal)
ALERT
图7-10. Thresholds, Hysteresis, and Event Counter for the Digital Window Comparator
The DWC_BLOCK_EN bit in the ALERT_DWC_EN register enables and disables the complete digital window
comparator block (disabled at power-up) and the ALERT_EN_CHx bits in the ALERT_CHEN register enables
the digital window comparator for individual channels. Possible responses when using the digital comparator
when a new ADC conversion is completed include:
1. The output of the high-side comparator transitions to a logic high when the conversion result is greater than
the high threshold. This comparator resets when the conversion result is less than the high threshold –
hysteresis.
Copyright © 2022 Texas Instruments Incorporated
28
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
2. The output of the low-side comparator transitions to a logic high when the conversion result is less than the
low threshold. This comparator resets when the conversion result is greater than the low threshold +
hysteresis.
3. When the output of either the high-side or low-side comparator transitions high, the pre-ALERT event
counter begins to increment for each subsequent conversion. This counter continues to increment until the
value stored in the PRE_ALT_MAX_EVENT_COUNT register is reached. When the counter reaches
PRE_ALT_MAX_EVENT_COUNT, the alert becomes active and sets the latched flags. If the comparator
output becomes zero before the counter reaches PRE_ALT_MAX_EVENT_COUNT, then the event counter
is reset to zero, ALERT is not set, and the latched flag is not set.
Therefore, the latched flags (high and low) for the channel are updated only if the respective comparator output
remains 1 for the specified number of consecutive conversions (set by PRE_ALT_MAX_EVENT_COUNT).
The latched flags can be read from the ALERT_LOW_FLAGS and ALERT_HIGH_FLAGS registers. To clear a
latched flag, write 1 to the applicable bit location. The ALERT pin status is re-evaluated when an applicable
latched flag is set or is cleared.
The response time for the ALERT pin can be estimated by 方程式6
tresponse = [1 + k × (PRE_ALT_MAX_EVENT_COUNT + 1) ] × nCLK × Oscillator TimePeriod
(6)
where:
• k = Number of channels enabled in device sequence
• nCLK = Number of clocks used by device for one conversion cycle
• Oscillator timer period = tLPO or tHSO depending on the OSC_SEL value; see the Specifications section for
tLPO or tHSO
7.3.10 I2C Protocol Features
7.3.10.1 General Call
On receiving a general call (00h), the device provides an ACK.
7.3.10.2 General Call With Software Reset
On receiving a general call (00h) followed by a software reset (06h), the device resets.
7.3.10.3 General Call With Write Software Programmable Part of the Target Address
On receiving a general call (00h) followed by 04h, the ADC configures the I2C address configured by the ADDR
pin. During this operation, the ADC keeps the BUSY/RDY pin high and does not respond to other I2C commands
except a general call.
7.3.10.4 Configuring the ADC Into High-Speed I2C Mode
The ADC can be configured in high-speed I2C mode by providing an I2C frame with one of the HS-mode codes
(08h to 0Fh).
After receiving one of the HS-mode codes, the ADC sets the HS_MODE bit in the
OPMODE_I2CMODE_STATUS register and remains in high-speed I2C mode until a STOP condition is received
in an I2C frame.
7.3.10.5 Bus Clear
If the SDA line is stuck low because of an incomplete I2C frame, providing nine clocks on SCL is recommended.
The device releases the SDA line within these nine clocks, and then the next I2C frame can be started.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.4 Device Functional Modes
The ADC has the following functional modes:
• Manual mode:
– Manual mode with CH0 only
– Manual mode with auto-sequence
• Autonomous modes:
– Autonomous mode with threshold monitoring and diagnostics
– Autonomous mode with burst data
• High-precision mode
The ADC powers up in manual mode with CH0 only and can be configured into one of the other modes by
writing the configuration registers for the desired mode. Steps for configuring ADC into different modes are
shown in 图7-11.
A. Offset can also be calibrated anytime during normal operation by setting the bit in the OFFSET_CAL register.
B. Configure the CH_INPUT_CFG register.
C. Configure the OPMODE_SEL register for the desired operation mode.
D. See the Configuring the ADC Into High-Speed I2C Mode section.
E. The operating mode is selected by configuring the OPMODE_SEL register in step 3.
F. For reading and writing registers, see the Programming section.
图7-11. Configuring the ADC Into Different Modes
7.4.1 Device Power Up and Reset
On power up, the device calibrates the offset and calculates the address from the resistors connected on the
ADDR pin. During this time, the device keeps BUSY/RDY high.
The device can be reset by cycling power on the AVDD pin, by a general call (00h) followed by software reset
(06h), or by writing the WKEY register followed by setting the bit in the DEVICE_RESET register.
Copyright © 2022 Texas Instruments Incorporated
30
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
When cycling power on the AVDD pin and on general call (00h) followed by software reset (06h), all the device
configurations are reset, and the device initiates an offset calibration and re-evaluates the I2C address.
When setting the bit in the DEVICE_RESET register, all the device configurations except latched flags for the
digital window comparator and the WKEY register are reset, The device does not initiate offset calibration and
does not re-evaluate the I2C address.
7.4.2 Manual Mode
On power-up, the ADC is in manual mode using the single-ended and dual-channel configuration and samples
the analog input applied on channel 0. In this mode, the ADC uses the high-frequency oscillator for conversions.
Manual mode allows the external host processor to directly request and control when the data are sampled. The
data capture is initiated by an I2C command from the host processor and the data are then returned over the I2C
bus at a throughput rate of up to 140 kSPS.
After setting the operation mode to manual mode as illustrated in 图 7-11, steps for operating the ADC to be in
manual mode and reading data are illustrated in 图 7-12. The host can either configure the ADC to scan through
one channel or both channels by configuring the CH_INPUT_CFG and AUTO_SEQ_CHEN registers.
7.4.2.1 Manual Mode With CH0 Only
Set the OPMODE_SEL register to 000b or 001b for manual mode with channel 0 only. The host must provide the
ADC address and read bit to start the conversions. To continue with conversions and reading data, the host must
provide continuous SCL (图 7-13). In this mode, a NACK followed by a STOP condition in the I2C frame is
required to abort the operation. Then the ADC operation mode can be changed to another operation mode.
7.4.2.2 Manual Mode With AUTO Sequence
Set the OPMODE_SEL register to 100b or 101b for manual mode with AUTO sequence. The host must set the
SEQ_START bit in the START_SEQUENCE register and provide the device address and read bit to start the
conversions. To continue with conversions and reading data, the host must provide continuous SCL (图 7-13). In
this mode, the SEQ_ABORT bit in the ABORT_SEQUENCE register must be set to abort the operation. Then
the device operation mode can be changed to another operation mode. In this mode, a register read aborts the
AUTO sequence.
In manual mode, the device always uses the high-speed oscillator and the nCLK parameter has no effect. The
maximum scan rate is given by 方程式7:
1000
fS =
18ìTSCL + k
(7)
• fs = Maximum sampling speed in kSPS
• TSCL= Time period of SCL clock (in µs)
• if TSCL-LOW (low period of SCL) < 1.8.µs, k = (1.8 –TSCL-LOW) and the device stretches clock in manual
mode; not applicable for standard I2C mode (100 kHz)
• if TSCL-LOW (low period of SCL) ≥1.8.µs, k = 0, and the device does not stretch clock in manual mode
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
Manual Mode(A)
AUTO
Sequence
Select Manual Mode with
AUTO Sequence and
Select Channels in AUTO
Sequence(B)
No
Scan CH0
Only
Yes
Set SEQ_START Bit(C)
CH0 Only (Default)
Provide Device Address
and Read Bit to Start
Conversions(D)
Provide Device Address
and Read Bit to Start
Conversions(D)
Provide Continuous SCL to
the device(D)
Provide Continuous SCL to
the device(D)
Yes
Yes
Continue with
conversions and
reading data
Continue with
conversions and
reading data
No
Provide STOP Condition on
I2C Bus(D)
No
Set SEQ_ABORT Bit(E)
Yes
Continue in same
Operation Mode
Yes
Continue in same
Operation Mode
No
No
Exit to another Operation Mode(F)
A. For setting the operation mode to manual mode, see 图7-11.
B. Select manual mode with AUTO sequence in the OPMODE_SEL register. Select channels in the AUTO_SEQ_CHEN register.
C. Set the SEQ_START bit in the START_SEQUENCE register.
D. See 图7-13.
E. Set the SEQ_ABORT bit in the ABORT_SEQUENCE register.
F. Select another operation mode in the OPMODE_SEL register.
G. For reading and writing registers, see the Programming section.
图7-12. Device Operation in Manual Mode
Copyright © 2022 Texas Instruments Incorporated
32
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
Data can be read from the device by providing a device address and read bit followed by continuous SCL, as
shown in 图7-13.
Sample A
Sample A+1
Sample A+2
Device I2C Address from Host
ADC Data for Sample A
ADC Data for Sample A
ADC Data for Sample A+1
NA
CK
ACK
ACK
ACK
18
S
SDA
SCL
A6
A5
A4
A3
A2
A1
A0
R
8
D11
D10
D9
D8
D7
D6
D5
D4
D3
10
D2
11
D1
12
D0
13
0
0
0
0
D11
D10
0
1
2
3
4
5
6
7
9
1
2
3
4
5
6
7
8
9
14
15
16
17
1
2
17
18
Optional
Clock
Stretch
Optional
Clock
Stretch
Device in Acquisition
Device in Acquisition
Device in Acquisition
Data from Host to Device
Data from Device to Host
A. See 方程式7 for sampling speed in manual mode.
B. If the device scans both channels in AUTO sequence, the first data (for sample A) is from channel 0 and the second data (for sample A
+1) is from channel 1.
图7-13. Starting Conversion and Reading Data in Manual Mode
7.4.3 Autonomous Modes
In autonomous mode, the ADC can be programmed to monitor the voltage applied on the analog input pins. The
ADC generates a signal on the ALERT pin when the programmable high or low threshold values are crossed.
The host processor can read the ADC conversion results from the internal data buffer.
In autonomous mode, the first start of conversion must be provided by the host and the ADC generates the
subsequent start of conversions. The ADC initiates the following start of conversions using the internal oscillator.
After configuring the operation mode to autonomous mode (set the OPMODE_SEL register to 110b), as
illustrated in 图7-11, steps for operating the ADC to be in different autonomous modes are illustrated in 图7-14.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
Autonomous Modes(A)
Select the Channels in AUTO Sequence(B)
Select the Oscillator
& Set the nCLK value(C)
Select the Data Buffer Configuration(D)
Autonomous Mode with Threshold Monitoring and Diagnostics
Autonomous Mode with Burst Data
Stop Burst
Pre Alert
Post Alert
Start Burst
Set the Thresholds,
Hysteresis and
Enable Alert(E)
Set the Thresholds,
Hysteresis and
Enable Alert(E)
Set the SEQ_START
Bit(F)
Set the SEQ_Start
Bit(F)
Set the SEQ_START
Bit(F)
Set the SEQ_START
Bit(F)
Device Starts
conversions and
starts Filling Data
Buffer
Device Starts
conversions and
starts Filling Data
Buffer
Device Starts
conversions and
starts Filling Data
Buffer
Device Starts
Conversions
No
No
Is Alert Set?
No
No
Is Data Buffer
Filled or SEQ_ABORT
bit Set?
Is Alert Set or
SEQ_ABORT bit set ?
Is SEQ_ABORT
Bit Set ?
Yes
Device Starts Filling
Data Buffer
Yes
Yes
Yes
Is Data Buffer
Filled or SEQ_ABORT
bit Set?
No
Yes
Device Stops
Conversions & Stops
Filling Data Buffers
Device Stops
Conversions & Stops
Filling Data Buffers
Device Stops
Conversions & Stops
Filling Data Buffer
Device Stops
Conversions & Stops
Filling Data Buffer
Read the latched
flags of Digital
Window
Comparator(G)
Read the latched
flags of Digital
Window
Comparator(G)
Reset the latched
flags by writing 1(H)
Reset the latched
flags by writing 1(H)
Read the Data Buffer(I)
Exit to another Operation
Mode(J)
Continue in same
operation mode
No
Yes
Set the SEQ_START
Bit(F)
A. For setting the operation mode to Autonomous modes, see 图7-11.
B. Select channels in the AUTO_SEQ_CHEN register.
C. Select the oscillator by configuring the OSC_SEL register and configure the NCLK_SEL register.
D. Select the data buffer mode in the DATA_BUFFER_OPMODE register.
E. Configure the thresholds in the DWC_xTH_CHx_xxx registers and hysteresis in the DWC_HYS_CHx registers. Enable the alert for
channels in the ALERT_CHEN register and set the DWC_BLOCK_EN bit in the ALERT_DWC_EN register.
F. Set the bit SEQ_START bit in the START_SEQUENCE register.
G. Read the ALERT_LOW_FLAGS and ALERT_HIGH_FLAGS registers.
H. Reset the ALERT_LOW_FLAGS and ALERT_HIGH_FLAGS registers by writing 03h.
Copyright © 2022 Texas Instruments Incorporated
34
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
I.
See the Reading Data From the Data Buffer section.
J. Select another operation mode in the OPMODE_SEL register.
K. For reading and writing registers, see the Programming section.
图7-14. Configuring ADC in Autonomous Modes
Abort the present sequence by setting the SEQ_ABORT bit in the ABORT_SEQUENCE register before
changing the ADC operation mode or ADC configuration.
7.4.3.1 Autonomous Mode With Threshold Monitoring and Diagnostics
In this mode, the ADC automatically scans the input voltage on the analog input channels and asserts the
ALERT pin when the programmable high or low thresholds are crossed. The conversion results of the ADC
corresponding to the pre-ALERT or post-ALERT can be stored in the internal data buffer, as described in
Autonomous Mode With Pre-ALERT Data and Autonomous Mode With Post-ALERT Data respectively. This
mode is useful for applications where the output of the sensor must be continuously monitored and where action
is only taken when the sensor output deviates outside of an acceptable range.
7.4.3.1.1 Autonomous Mode With Pre-ALERT Data
In this mode, the ADC stores the 16 conversions prior to the assertion of the ALERT pin. Upon assertion of
ALERT, conversions stop. For this mode, set DATA_BUFFER_OPMODE to 100b. In this mode, the ADC starts
converting and stores the data when setting the SEQ_START bit in the START_SEQUENCE register and
continues to store data into the data buffer until one of the digital comparator flags is set for crossing a high
threshold or a low threshold for the channels selected in the sequence. If the SEQ_ABORT bit is set before the
data buffer is filled, the ADC aborts the sequence and stops storing conversion results. If more than 16
conversions occur between start of sequence and alert output, the first entries written into the data buffer are
overwritten.
图7-15 and 图7-16 show the filling of the data buffer in autonomous mode with pre-ALERT data.
Device stops conversions and Sets the Latched
flag and alert pin after count(=4) is reached
Conversion [N+ 15] for CHx
Device stops conversions and
stops storing data in the buffer
Conversion [N+ 15] for CHy
after the count is reached
High Threshold
Sets the Output of the Comparator
Hysteresis
High Threshold - Hysteresis
Sets the Output of the
Comparator
High Threshold
Data Buffer
Conversion [N] for CHx
Conversion [N + 1] for CHy
tCC
Conversion [N] for CHx
tCC
Conversion [N + 14] for CHx
Conversion [N + 15] for CHy
Data Buffer
Conversion [N] for CHx
CHy is the channel which first triggered the ALERT
Conversion [N+1] for CHy
Conversion [N] for CHx
Conversion [N + 14] for CHx
Conversion [N + 15] for CHx
SEQ_START bit is set
by user
Conversion [0] for CHx
Conversion [1] for CHy
SEQ_START bit is set
by user
Conversion [0] for CHx
BUSY/RDY
BUSY/RDY
Time
Time
图7-16. Pre-ALERT Data for Dual-Channel
图7-15. Pre-ALERT Data for Single-Channel
Configuration
Configurations
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.4.3.1.2 Autonomous Mode With Post-ALERT Data
In this mode, the ADC captures the next sixteen conversion results after the ALERT pin is asserted. Once these
sixteen conversions are stored in the data buffer, all conversion stops. For this mode, Set
DATA_BUFFER_OPMODE to 110b. In this mode, the ADC starts converting the data on setting the
SEQ_START bit and stores the data in the data buffer when one of the digital comparator flags is set after the
crossing a high threshold or a low threshold for the channels selected in the sequence. if the SEQ_ABORT bit is
set before the data buffer is filled, the ADC aborts the sequence and stops storing the conversion results.
图7-17 and 图7-18 show the filling of the data buffer in autonomous mode with post-ALERT data.
Conversion [N+ 14] for CHx
Device stops conversions and
stops storing data in the buffer
after the data buffer is filled
Conversion [N+ 15] for CHy
Device stops conversions and
stops storing data in buffer after
the data buffer is filled
Conversion [N+ 15] for CHx
Data Buffer
tCC
Conversion [N] for CHx
Conversion [N + 1] for CHy
Device Starts storing data in
buffer and sets the Latched flag
and alert pin after the count is
reached
tCC
Conversion [N] for CHx
Conversion [N+1] for CHy
High Threshold
Conversion [N + 14] for CHx
Conversion [N + 15] for CHy
Device Starts storing data in
buffer and sets the Latched flag
and alert pin after count(=4) is
reached
Data Buffer
CHx is the channel which first triggered the ALERT
Sets the Output of the
Comparator
Conversion [N] for CHx
Conversion [N] for CHx
SEQ_START bit is set
by user
Conversion [0] for CHx
Conversion [1] for CHy
High Threshold
Sets the Output of the
Comparator
Conversion [N + 14] for CHx
Conversion [N + 15] for CHx
Hysteresis
High Threshold - Hysteresis
SEQ_START bit is set
by user
Conversion [0] for CHx
BUSY/RDY
Time
BUSY/RDY
图7-18. Post-ALERT Data for Dual Channel
Configuration
Time
图7-17. Post-ALERT Data for Single Channel
Configurations
Copyright © 2022 Texas Instruments Incorporated
36
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.4.3.2 Autonomous Mode With Burst Data
In this mode, the ADC can be configured to store up to 16 conversion results in the data buffer based on user
command. In this mode, the user can either start or stop the burst of data as described in the following two
sections.
7.4.3.2.1 Autonomous Mode With Start Burst
For this mode, set DATA_BUFFER_OPMODE to 001b. With start burst, the user can configure the device to
start the filling of the data buffer with conversion results by setting the SEQ_START bit and the device stops
converting data and filling the data buffer after the data buffer is filled.
Conversion [14] for CH0
Device stops conversions and
stops storing data after the data
buffer is filled
Conversion [15] for CH1
Device stops conversions and stops filling
the data buffer after the buffer is filled
Conversion [15] for CHx
Data Buffer
Conversion [0] for CH0
Conversion [1] for CH1
Conversion [14] for CH0
Conversion [15] for CH1
Data Buffer
tCC
tCC
Conversion [0] for CHx
SEQ_START bit is set
by user
Device starts
conversions and starts
storing data in the buffer
on setting the
Conversion [0] for CHx
Conversion [14] for CHx
Conversion [15] for CHx
Conversion [0] for CH0
Conversion [1] for CH1
SEQ_START bit
BUSY/RDY
Time
BUSY/RDY
图7-20. Start Burst With a Dual-Channel
Time
Configuration
图7-19. Start Burst With a Single-Channel
Configuration
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.4.3.2.2 Autonomous Mode With Stop Burst
For this mode, set DATA_BUFFER_OPMODE to 000b. With stop burst, the user can configure the device to stop
filling the data buffer with conversion results by setting the SEQ_ABORT bit. If more than 16 conversions occur
between start of sequence and abort of sequence, the entries first written into the data buffer are overwritten. 图
7-21 and 图7-22 illustrate the filling of the data buffer in autonomous mode with stop burst.
Conversion [N+ 14] for CH0
Device stops conversions and
stops storing data on setting the
SEQ_ABORT bit
Conversion [N+ 15] for CH1
Device stops conversions and stops filling the
data buffer on setting the SEQ_ABORT bit
Conversion [N+ 15] for CHx
tCC
Data Buffer
Conversion [N] for CH0
Conversion [N + 1] for CH1
Conversion [N] for CH0
tCC
Data Buffer
Conversion [N + 14] for CH0
Conversion [N + 15] for CH1
Conversion [N] for CHx
Conversion [N+1] for CH1
Conversion [N] for CHx
Conversion [N + 14] for CHx
Conversion [N + 15] for CHx
SEQ_START bit is set
by user
SEQ_START bit is set
by user
Conversion [0] for CH0
Conversion [1] for CH1
Conversion [0] for CHx
BUSY/RDY
BUSY/RDY
Time
Time
图7-22. Stop Burst With a Dual-Channel
图7-21. Stop Burst With a Single-Channel
Configuration
Configuration
7.4.4 High-Precision Mode
High-precision mode increases the accuracy of the data measurement by accumulating ADC conversion results.
This accumulation is useful for applications where the level of precision required to accurately measure the
sensor output must be higher than 12 bits.
For this mode, set the OPMODE_SEL register to 111b. In this mode, the ADC starts converting and starts
accumulating the conversion results in an accumulator when the SEQ_START bit is set. The ADC stops
accumulating after 16 conversion results. The accumulator contains one 16-bit conversion result. The ADC has
an accumulator for each analog input channel. If the operation of the ADC is aborted in high-precision mode
before the BUSY/RDY pin goes low because the SEQ_ABORT bit is set by the user, the ADC provides invalid
data and the internal data buffer (图 7-8), provides zeroes as output. In this mode, the BUSY/RDY can wake up
the MCU or host from sleep or hibernation when accumulation completes. The steps for configuring the ADC into
high-precision mode are illustrated in 图7-23.
Copyright © 2022 Texas Instruments Incorporated
38
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
High Precision Mode(A)
Select the Channels in AUTO
Sequence(B)
Select the Oscillator
& Set the nCLK value(C)
Enable the accumulator(D)
Set the SEQ_START Bit(E)
Device Starts Conversions
& Starts Accumulating Data
Check Busy/RDY
pin to see if 16
accumulations are
completed
No
Yes
Read the Accumulated Results(F)
Yes
Continue in High
Presicion Mode
No
Exit to another Operation Mode(G)
A. For setting the operation mode to high-precision mode, see 图7-11.
B. Select the channels in the AUTO_SEQ_CHEN register.
C. Select the oscillator by configuring the OSC_SEL register and configure the NCLK_SEL register.
D. Enable the accumulator by setting the bits in the ACC_EN register.
E. Set the SEQ_START bit in the START_SEQUENCE register.
F. Read the ACC_CHx_xxx registers.
G. Select another operation mode in the OPMODE_SEL register.
H. For reading and writing registers, see the Programming section.
图7-23. Configuring ADC in High-Precision Mode
Abort the current sequence by setting the SEQ_ABORT bit before changing the ADC operation mode or ADC
configuration.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
39
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
图7-24 and 图7-25 show the accumulation of conversion results in high-precision mode.
Device stops after
accumulating 16
conversion results
Device starts
accumulating on setting
the SEQ_START bit
tCC
Conversion [15] for CHx
Conversion [0] for CHx
BUSY/RDY
Time
图7-24. High-Precision Mode With Single-Channel Configurations
Accumulated in
Accumulator for CH0
Device stops after
accumulating 16
conversion results
Device starts
accumulating on setting
the SEQ_START bit
tCC
Conversion [15] for CH0
Conversion [0]
for CH0
Conversion [15] for CH1
Accumulated in
Accumulator for CH1
Conversion [0] for CH1
BUSY/RDY
Time
图7-25. High-Precision Mode With Dual-Channel Configurations
Copyright © 2022 Texas Instruments Incorporated
40
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.5 Programming
表7-3 provides the acronyms for different conditions in an I2C frame.
表7-3. I2C Frame Acronyms
SYMBOL
DESCRIPTION
S
Sr
P
START condition for I2C frame
RESTART condition for I2C frame
STOP condition for I2C frame
ACK (low)
A
N
R
W
NACK (high)
Read bit (high)
Write bit (low)
表7-4. Opcodes for Commands
OPCODE
00010000b
00001000b
00011000b
00100000b
00110000b
00101000b
COMMAND DESCRIPTION
Single register read
Single register write
Set bit
Clear bit
Reading a continuous block of registers
Writing a continuous block of registers
7.5.1 Reading Registers
The I2C controller can either read a single register or a continuous block registers from the ADC, as described in
the Single Register Read and Reading a Continuous Block of Registers sections.
7.5.1.1 Single Register Read
To read a single register from the ADC, the I2C controller must first provide an I2C command with three frames
(of eight bits each) to set the address as shown in 图 7-26. The register address is the address of the register
that must be read. The opcode for register read command is listed in 表7-4.
Register Read or Block Read
Opcode (8 Bits)
S
Device Address (7 Bits)
W
A
A
Register Address (8 Bits)
A
P/Sr
Data from Host to Device
Data from Device to Host
图7-26. Setting Register Address for Reading Registers
Next, the I2C controller must provide another I2C frame containing the ADC address and read bit as illustrated in
图 7-27. After this frame, the ADC provides register data. If the host provides more clocks, the ADC provides the
same register data. To end the register read command, the controller must provide a STOP or a RESTART
condition in the I2C frame.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
41
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
S
Device Address (7 Bits)
R
A
Register Data (8 Bits)
A
P/Sr
Data from Host to Device
Data from Device to Host
图7-27. Reading Register Data
7.5.1.2 Reading a Continuous Block of Registers
To read a continuous block of registers, the I2C controller must first provide an I2C command to set the address,
as illustrated in 图 7-26. The register address is the address of the first register in the block that must be read.
The opcode for reading a continuous block of register is listed in 表7-4.
Next, the I2C controller must provide another I2C frame containing the ADC address and read bit, as shown in 图
7-28. After this frame, the ADC provides register data. On providing more clocks, the ADC provides data for the
next register. On reading data from addresses that do not exist in the Register Map of the ADC, the ADC returns
zeros. If the ADC does not have any further registers to provide the data, the ADC provides zeros. To end the
register read command, the controller must provide a STOP or a RESTART condition in the I2C frame.
S
Device Address (7 Bits)
R
A
Register Data (8 Bits) for Register N
A
Register Data (8 Bits) for Register N+1
A
Register Data (8 Bits) for Register N+2
A
Register Data (8 Bits) for Register N+k
A
P/Sr
Data from Host to Device
Data from Device to Host
图7-28. Reading a Continuous Block of Registers
7.5.2 Writing Registers
The I2C controller can either write a single register or a continuous block registers to the ADC. The I2C controller
can also set or clear a few bits in a register.
7.5.2.1 Single Register Write
To write to a single register in the ADC, the I2C controller has to provide an I2C command with four frames as
shown in 图 7-29. The register address is the address of the register which must be written and register data is
the value that must be written. The opcode for single register write is listed in 表 7-4. To end the register write
command, the controller has to provide a STOP or a RESTART condition in the I2C frame.
Write Register or Set Bit or Clear Bit
Opcode (8 Bits)
S
Device Address (7 Bits)
W
A
A
Register Address (8 Bits)
A
Register Data (8 Bits)
A
P/Sr
Data from Host to Device
Data from Device to Host
图7-29. Writing a Single Register
Copyright © 2022 Texas Instruments Incorporated
42
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.5.2.2 Writing a Continuous Block of Registers
To write to a continuous block of registers, the I2C controller must provide an I2C command as shown in 图 7-30.
The register address is the address of the first register in the block that must be written. The I2C controller must
provide data for registers in subsequent I2C frames in an ascending order of register addresses. Writing data to
addresses that do not exist in the Register Map of the ADC has no effect. The opcode for writing a continuous
block of registers is listed in 表 7-4. If the data provided by the I2C controller exceeds the address space of the
ADC, the ADC neglects the data beyond the address space. To end the register write command, the controller
must provide a STOP or a RESTART condition in the I2C frame.
S
Device Address (7 Bits)
W
A
Block Write Opcode (8 Bits)
A
Register Address (8 Bits)
A
Register Data (8 Bits) for Register N
A
Register Data (8 Bits) for Register N+1
A
Register Data (8 Bits) for Register N+k
A
P/Sr
Data from Host to Device
Data from Device to Host
图7-30. Writing a Continuous Block of Registers
7.5.2.3 Set Bit
To set bits in a register without changing the other bits, the I2C controller must provide an I2C command with four
frames, as illustrated in 图 7-29. The register address is the address of the register in which the bits must be set
and the register data are the values representing the bits that must be set. Bits with a value of 1 in register data
are set and bits with a value of 0 in register data are not changed. The opcode for set bit is listed in 表 7-4. To
end this command, the controller must provide a STOP or RESTART condition in the I2C frame.
7.5.2.4 Clear Bit
To clear bits in a register without changing the other bits, the I2C controller must provide an I2C command with
four frames, as illustrated in 图 7-29. The register address is the address of the register where the bits must be
cleared and where the register data are the values representing the bits that must be cleared. Bits with a value
of 1 in register data are cleared and bits with a value of 0 in register data are not changed. The opcode for
clearing a bit is listed in 表 7-4. To end this command, the controller must provide a STOP or a RESTART
condition in the I2C frame.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
43
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.6 Register Map
7.6.1 Page1 Registers
表 7-5 lists the memory-mapped registers for the Page1 registers. All register offset addresses not listed in 表
7-5 should be considered as reserved locations and the register contents should not be modified.
表7-5. PAGE1 Registers
Address Acronym
Register Name
Section
节7.6.1.1
节7.6.1.2
节7.6.1.3
节7.6.1.4
节7.6.1.5
节7.6.1.6
节7.6.1.7
节7.6.1.8
节7.6.1.9
节7.6.1.10
节7.6.1.11
节7.6.1.12
节7.6.1.13
节7.6.1.14
0x0
0x1
OPMODE_I2CMODE_STATUS
Device operation mode register
Data buffer status register
Status of ADC accumulator
Alert trigeer channel ID
DATA_BUFFER_STATUS
ACCUMULATOR_STATUS
ALERT_TRIG_CHID
SEQUENCE_STATUS
ACC_CH0_LSB
0x2
0x3
0x4
Sequence status register
0x8
CH0 accumulator data register (LSB)
CH0 accumulated data register (MSB)
CH1 accumulated data register (LSB)
CH1 accumulated data register (MSB)
Alert low flags register
0x9
ACC_CH0_MSB
0xA
0xB
0xC
0xE
0x14
0x15
0x17
ACC_CH1_LSB
ACC_CH1_MSB
ALERT_LOW_FLAGS
ALERT_HIGH_FLAGS
DEVICE_RESET
OFFSET_CAL
Alert high flags register
Device reset register
Offset calibration register
WKEY
Write key for writing into
DEVICE_RESET register
0x18
0x19
0x1C
0x1E
OSC_SEL
Oscillator selection register
nCLK selection register
节7.6.1.15
节7.6.1.16
节7.6.1.17
节7.6.1.18
NCLK_SEL
OPMODE_SEL
START_SEQUENCE
Device operation mode selection
Start channel scanning sequence
register
0x1F
0x20
0x24
0x28
0x2C
0x30
0x34
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
ABORT_SEQUENCE
AUTO_SEQ_CHEN
CH_INPUT_CFG
Abort channel sequence register
Auto sequencing channel select register
Channel input configuration register
Data buffer word configuration register
Data buffer operation mode register
Accumulator control register
节7.6.1.19
节7.6.1.20
节7.6.1.21
节7.6.1.22
节7.6.1.23
节7.6.1.24
节7.6.1.25
节7.6.1.26
节7.6.1.27
节7.6.1.28
节7.6.1.29
节7.6.1.30
节7.6.1.31
节7.6.1.32
节7.6.1.33
节7.6.1.34
节7.6.1.35
节7.6.1.36
DOUT_FORMAT_CFG
DATA_BUFFER_OPMODE
ACC_EN
ALERT_CHEN
Alert channel enable register
PRE_ALT_MAX_EVENT_COUNT
ALERT_DWC_EN
Pre-alert count register
Alert digital window comparator register
CH0 high threshold LSB register
CH0 high threshold MSB register
CH0 low threshold LSB register
CH0 low threshold MSB register
CH1 high threshold LSB register
CH1 high threshold MSB register
CH1 low threshold LSB register
CH1 low threshold MSB register
CH0 comparator hysterisis register
DWC_HTH_CH0_LSB
DWC_HTH_CH0_MSB
DWC_LTH_CH0_LSB
DWC_LTH_CH0_MSB
DWC_HTH_CH1_LSB
DWC_HTH_CH1_MSB
DWC_LTH_CH1_LSB
DWC_LTH_CH1_MSB
DWC_HYS_CH0
Copyright © 2022 Texas Instruments Incorporated
44
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
表7-5. PAGE1 Registers (continued)
Address Acronym
Register Name
Section
0x41
DWC_HYS_CH1
CH1 comparator hysterisis register
节7.6.1.37
Complex bit access types are encoded to fit into small table cells. 表 7-6 shows the codes that are used for
access types in this section.
表7-6. Page1 Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n
When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y
When this variable is used in a
register name, an offset, or an
address this variable refers to the
value of a register array.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
45
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.6.1.1 OPMODE_I2CMODE_STATUS Register (Address = 0x0) [Reset = 0x0]
OPMODE_I2CMODE_STATUS is shown in 图7-31 and described in 表7-7.
Return to the 表7-5.
Device operation mode register
图7-31. OPMODE_I2CMODE_STATUS Register
7
6
5
4
3
2
1
0
RESERVED
R-00000b
HS_MODE
R-0b
DEV_OPMODE[1:0]
R-00b
表7-7. OPMODE_I2CMODE_STATUS Register Field Descriptions
Bit
Field
Type
Reset
00000b
0b
Description
7-3
2
RESERVED
HS_MODE
R
Reserved bits. Read returns 00000b.
R
This bit indicates when device is in high speed mode for I2C
Interface.
0b = Device is not in high speed mode for I2C Interface.
1b = Device is in high speed mode for I2C Interface.
1-0
DEV_OPMODE[1:0]
R
00b
These bits indicate funtional mode of the device.
00b = Device is operating in manual mode.
01b = Not used.
10b = Device is operating in autonomous monitoring mode.
11b = Device is operating in high precision mode.
7.6.1.2 DATA_BUFFER_STATUS Register (Address = 0x1) [Reset = 0x0]
DATA_BUFFER_STATUS is shown in 图7-32 and described in 表7-8.
Return to the 表7-5.
Data buffer status register
图7-32. DATA_BUFFER_STATUS Register
7
6
5
4
3
2
1
0
RESERVED
R-000b
DATA_WORDCOUNT[4:0]
R-00000b
表7-8. DATA_BUFFER_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
4-0
RESERVED
R
000b
Reserved bits. Read returns 000b.
DATA_WORDCOUNT[4:0] R
00000b
DATA_WORDCOUNT [00000] to [10000] = Number of entries filled in
data buffer (0 to 16)
Copyright © 2022 Texas Instruments Incorporated
46
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.6.1.3 ACCUMULATOR_STATUS Register (Address = 0x2) [Reset = 0x0]
ACCUMULATOR_STATUS is shown in 图7-33 and described in 表7-9.
Return to the 表7-5.
Status of ADC accumulator
图7-33. ACCUMULATOR_STATUS Register
7
6
5
4
3
2
1
0
RESERVED
R-0000b
ACC_COUNT[3:0]
R-0000b
表7-9. ACCUMULATOR_STATUS Register Field Descriptions
Bit
Field
Type
Reset
0000b
0000b
Description
7-4
3-0
RESERVED
R
Reserved bits. Read returns 0000b.
ACC_COUNT[3:0]
R
ACC_COUNT = Number of accumulation completed till last finished
conversion.
7.6.1.4 ALERT_TRIG_CHID Register (Address = 0x3) [Reset = 0x0]
ALERT_TRIG_CHID is shown in 图7-34 and described in 表7-10.
Return to the 表7-5.
Alert trigeer channel ID
图7-34. ALERT_TRIG_CHID Register
7
6
5
4
3
2
1
0
ALERT_TRIG_CHID[3:0]
R-0000b
RESERVED
R-0000b
表7-10. ALERT_TRIG_CHID Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
ALERT_TRIG_CHID[3:0]
R
0000b
These bits provide the channel ID of channel which was first to set
the alert output.
0000b = Channel 0.
0001b = Channel 1.
3-0
RESERVED
R
0000b
Reserved bits. Reads returns 0000b.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
47
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.6.1.5 SEQUENCE_STATUS Register (Address = 0x4) [Reset = 0x0]
SEQUENCE_STATUS is shown in 图7-35 and described in 表7-11.
Return to the 表7-5.
Sequence status register
图7-35. SEQUENCE_STATUS Register
7
6
5
4
3
2
1
0
RESERVED
R-00000b
SEQ_ERR_ST[1:0]
R-00b
RESERVED
R-0b
表7-11. SEQUENCE_STATUS Register Field Descriptions
Bit
Field
Type
Reset
00000b
00b
Description
7-3
2-1
RESERVED
R
Reserved bits. Read returns 00000b.
SEQ_ERR_ST[1:0]
R
These bits give status of device sequence.
00b = Auto sequencing disabled, no error.
01b = Auto sequencing enabled, no error.
10b = Not used.
11b = Auto sequencing enabled, device in error.
0
RESERVED
R
0b
Reserved bit. Read returns 0b.
7.6.1.6 ACC_CH0_LSB Register (Address = 0x8) [Reset = 0x0]
ACC_CH0_LSB is shown in 图7-36 and described in 表7-12.
Return to the 表7-5.
CH0 accumulator data register (LSB)
图7-36. ACC_CH0_LSB Register
7
6
5
4
3
2
1
0
CH0_LSB[7:0]
R-00000000b
表7-12. ACC_CH0_LSB Register Field Descriptions
Bit
7-0
Field
CH0_LSB[7:0]
Type
Reset
Description
R
00000000b LSB of accumulated data for CH0.
Copyright © 2022 Texas Instruments Incorporated
48
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.6.1.7 ACC_CH0_MSB Register (Address = 0x9) [Reset = 0x0]
ACC_CH0_MSB is shown in 图7-37 and described in 表7-13.
Return to the 表7-5.
CH0 accumulated data register (MSB)
图7-37. ACC_CH0_MSB Register
7
6
5
4
3
2
1
0
CH0_MSB[7:0]
R-00000000b
表7-13. ACC_CH0_MSB Register Field Descriptions
Bit
7-0
Field
CH0_MSB[7:0]
Type
Reset
Description
R
00000000b MSB of accumulated data for CH0.
7.6.1.8 ACC_CH1_LSB Register (Address = 0xA) [Reset = 0x0]
ACC_CH1_LSB is shown in 图7-38 and described in 表7-14.
Return to the 表7-5.
CH1 accumulated data register (LSB)
图7-38. ACC_CH1_LSB Register
7
6
5
4
3
2
1
0
CH1_LSB[7:0]
R-00000000b
表7-14. ACC_CH1_LSB Register Field Descriptions
Bit
7-0
Field
CH1_LSB[7:0]
Type
Reset
Description
R
00000000b LSB of accumulated data for CH1.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
49
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.6.1.9 ACC_CH1_MSB Register (Address = 0xB) [Reset = 0x0]
ACC_CH1_MSB is shown in 图7-39 and described in 表7-15.
Return to the 表7-5.
CH1 accumulated data register (MSB)
图7-39. ACC_CH1_MSB Register
7
6
5
4
3
2
1
0
CH1_MSB[7:0]
R-00000000b
表7-15. ACC_CH1_MSB Register Field Descriptions
Bit
7-0
Field
CH1_MSB[7:0]
Type
Reset
Description
R
00000000b MSB of accumulated data for CH1.
7.6.1.10 ALERT_LOW_FLAGS Register (Address = 0xC) [Reset = 0x0]
ALERT_LOW_FLAGS is shown in 图7-40 and described in 表7-16.
Return to the 表7-5.
Alert low flags register
图7-40. ALERT_LOW_FLAGS Register
7
6
5
4
3
2
1
0
RESERVED
R-000000b
ALERT_LOW_ ALERT_LOW_
CH1
CH0
R/W-0b
R/W-0b
表7-16. ALERT_LOW_FLAGS Register Field Descriptions
Bit
Field
Type
Reset
000000b
0b
Description
7-2
1
RESERVED
R
Reserved bits. Read returns 000000b.
ALERT_LOW_CH1
R/W
This bit indicates alert on low side comparator for CH1.
0b = Alert is not set for low side comparator for CH1.
1b = Alert is set for low side comparator for CH1.
0
ALERT_LOW_CH0
R/W
0b
This bit indicates alert on low side comparator for CH0.
0b = Alert is not set for low side comparator for CH0.
1b = Alert is set for low side comparator for CH0.
Copyright © 2022 Texas Instruments Incorporated
50
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.6.1.11 ALERT_HIGH_FLAGS Register (Address = 0xE) [Reset = 0x0]
ALERT_HIGH_FLAGS is shown in 图7-41 and described in 表7-17.
Return to the 表7-5.
Alert high flags register
图7-41. ALERT_HIGH_FLAGS Register
7
6
5
4
3
2
1
0
RESERVED
R-000000b
ALERT_HIGH_ ALERT_HIGH_
CH1
CH0
R/W-0b
R/W-0b
表7-17. ALERT_HIGH_FLAGS Register Field Descriptions
Bit
Field
Type
Reset
000000b
0b
Description
7-2
1
RESERVED
R
Reserved bits. Read returns 000000b.
ALERT_HIGH_CH1
R/W
This bit indicates alert on high side comparator of CH1.
0b = Alert is not set for high side comparator for CH1.
1b = Alert is set for high side comparator for CH1.
0
ALERT_HIGH_CH0
R/W
0b
This bit indicates alert on high side comparator for CH0.
0b = Alert is not set for high side comparator for CH0.
1b = Alert is set for high side comparator for CH0.
7.6.1.12 DEVICE_RESET Register (Address = 0x14) [Reset = 0x0]
DEVICE_RESET is shown in 图7-42 and described in 表7-18.
Return to the 表7-5.
Device reset register
图7-42. DEVICE_RESET Register
7
6
5
4
3
2
1
0
RESERVED
R-0000000b
DEV_RST
W-0b
表7-18. DEVICE_RESET Register Field Descriptions
Bit
Field
Type
Reset
0000000b
0b
Description
7-1
0
RESERVED
DEV_RST
R
Reserved bits. Read returns 0000000b.
Writing 1 to this bit resets the device.
W
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
51
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.6.1.13 OFFSET_CAL Register (Address = 0x15) [Reset = 0x0]
OFFSET_CAL is shown in 图7-43 and described in 表7-19.
Return to the 表7-5.
Offset calibration register
图7-43. OFFSET_CAL Register
7
6
5
4
3
2
1
0
RESERVED
R-0000000b
TRIG_OFFCAL
W-0b
表7-19. OFFSET_CAL Register Field Descriptions
Bit
Field
Type
Reset
0000000b
0b
Description
7-1
0
RESERVED
R
Reserved bits. Read returns 0000000b.
TRIG_OFFCAL
W
Writing 1 into this bit triggers internal offset calibration.
7.6.1.14 WKEY Register (Address = 0x17) [Reset = 0x0]
WKEY is shown in 图7-44 and described in 表7-20.
Return to the 表7-5.
Write key for writing into DEVICE_RESET register
图7-44. WKEY Register
7
6
5
4
3
2
1
0
RESERVED
R-0000b
WKEY[3:0]
R/W-0000b
表7-20. WKEY Register Field Descriptions
Bit
Field
Type
Reset
0000b
0000b
Description
7-4
3-0
RESERVED
WKEY[3:0]
R
Reserved bits. Do not write. Read returns 0000b.
Write 1010b into these bits to get write access for the
R/W
DEVICE_RESET register. WKEY register is not reset to default value
on device reset (see Reset section). After coming out of device reset,
write 00h to the WKEY register to prevent erroneous reset.
Copyright © 2022 Texas Instruments Incorporated
52
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.6.1.15 OSC_SEL Register (Address = 0x18) [Reset = 0x0]
OSC_SEL is shown in 图7-45 and described in 表7-21.
Return to the 表7-5.
Oscillator selection register
图7-45. OSC_SEL Register
7
6
5
4
3
2
1
0
RESERVED
R-0000000b
HSZ_LP
R/W-0b
表7-21. OSC_SEL Register Field Descriptions
Bit
Field
Type
Reset
0000000b
0b
Description
7-1
0
RESERVED
HSZ_LP
R
Reserved bits. Read returns 0000000b.
R/W
This bit selects oscillator used for the conversion process and cycle
time for a single conversion.
0b = Device uses high speed oscillator.
1b = Device uses low power oscillator.
7.6.1.16 NCLK_SEL Register (Address = 0x19) [Reset = 0x0]
NCLK_SEL is shown in 图7-46 and described in 表7-22.
Return to the 表7-5.
nCLK selection register
图7-46. NCLK_SEL Register
7
6
5
4
3
2
1
0
NCLK[7:0]
R/W-00000000b
表7-22. NCLK_SEL Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
NCLK[7:0]
R/W
00000000b Sets number of clocks of the oscillator that the device uses for one
conversion cycle. When using the High Speed Oscillator: For Value x
written into the nCLK register •if x ≤21, nCLK is set to 21
(00010101b) •if x > 21, nCLK is set to x When using the Low Power
Oscillator, For Value x written into the nCLK register: •if x ≤18,
nCLK is set to 18 (00010010b) •if x > 18, nCLK is set to x
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
53
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.6.1.17 OPMODE_SEL Register (Address = 0x1C) [Reset = 0x0]
OPMODE_SEL is shown in 图7-47 and described in 表7-23.
Return to the 表7-5.
Device operation mode selection
图7-47. OPMODE_SEL Register
7
6
5
4
3
2
1
0
RESERVED
R-00000b
SEL_OPMODE[2:0]
R/W-000b
表7-23. OPMODE_SEL Register Field Descriptions
Bit
Field
Type
Reset
00000b
000b
Description
7-3
2-0
RESERVED
R
Reserved bits. Read returns 00000b
SEL_OPMODE[2:0]
R/W
These bits set the functional mode for the device.
000b = Manual mode with CH0 only (Default mode).
001b = Manual mode with CH0 only (Default mode).
010b = Reserved. Do not use.
011b = Reserved. Do not use.
100b = Manual mode with AUTO Sequencing enabled.
101b = Manual Mode with AUTO Sequencing enabled.
110b = Autonomous monitoring mode with AUTO sequencing
enabled.
111b = High precision mode with AUTO sequencing enabled.
7.6.1.18 START_SEQUENCE Register (Address = 0x1E) [Reset = 0x0]
START_SEQUENCE is shown in 图7-48 and described in 表7-24.
Return to the 表7-5.
Start channel scanning sequence register
图7-48. START_SEQUENCE Register
7
6
5
4
3
2
1
0
RESERVED
R-0000000b
SEQ_START
W-0b
表7-24. START_SEQUENCE Register Field Descriptions
Bit
Field
Type
Reset
0000000b
0b
Description
7-1
0
RESERVED
SEQ_START
R
Reserved bits. Read returns 0000000b.
W
Setting this bit to 1 brings the BUSY/RDY pin high and starts the first
conversion in the sequence.
Copyright © 2022 Texas Instruments Incorporated
54
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.6.1.19 ABORT_SEQUENCE Register (Address = 0x1F) [Reset = 0x0]
ABORT_SEQUENCE is shown in 图7-49 and described in 表7-25.
Return to the 表7-5.
Abort channel sequence register
图7-49. ABORT_SEQUENCE Register
7
6
5
4
3
2
1
0
RESERVED
R-0000000b
SEQ_ABORT
W-0b
表7-25. ABORT_SEQUENCE Register Field Descriptions
Bit
Field
Type
Reset
0000000b
0b
Description
7-1
0
RESERVED
R
Reserved bits. Read returns 0000000b.
SEQ_ABORT
W
Setting this bit to 1 aborts the ongoing conversion and brings the
BUSY/RDY pin low.
7.6.1.20 AUTO_SEQ_CHEN Register (Address = 0x20) [Reset = 0x3]
AUTO_SEQ_CHEN is shown in 图7-50 and described in 表7-26.
Return to the 表7-5.
Auto sequencing channel select register
图7-50. AUTO_SEQ_CHEN Register
7
6
5
4
3
2
1
0
RESERVED
R-000000b
AUTOSEQ_EN AUTOSEQ_EN
_CH1
_CH0
R/W-1b
R/W-1b
表7-26. AUTO_SEQ_CHEN Register Field Descriptions
Bit
Field
Type
Reset
000000b
1b
Description
7-2
1
RESERVED
R
Reserved bits. Read returns 000000b.
AUTOSEQ_EN_CH1
R/W
This bit selects CH1 for auto sequencing.
0b = Channel 1 is not selected for auto sequencing.
1b = Channel 1 is selected for auto sequencing.
0
AUTOSEQ_EN_CH0
R/W
1b
This bit selects CH0 for auto sequencing.
0b = Channel 0 is not selected for auto sequencing.
1b = Channel 0 is selected for auto sequencing.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
55
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.6.1.21 CH_INPUT_CFG Register (Address = 0x24) [Reset = 0x0]
CH_INPUT_CFG is shown in 图7-51 and described in 表7-27.
Return to the 表7-5.
Channel input configuration register
图7-51. CH_INPUT_CFG Register
7
6
5
4
3
2
1
0
RESERVED
R-000000b
CH0_CH1_IP_CFG[1:0]
R/W-00b
表7-27. CH_INPUT_CFG Register Field Descriptions
Bit
Field
Type
Reset
000000b
00b
Description
7-2
1-0
RESERVED
R
Reserved bits. Read returns 000000b.
CH0_CH1_IP_CFG[1:0]
R/W
This bit selects configuration for the input pins.
00b = Two-channel, single-ended configuration.
01b = Single-channel, single-ended configuration with remote ground
sensing.
10b = Single-channel, pseudo-differential configuration.
11b = Two-channel, single-ended configuration.
7.6.1.22 DOUT_FORMAT_CFG Register (Address = 0x28) [Reset = 0x0]
DOUT_FORMAT_CFG is shown in 图7-52 and described in 表7-28.
Return to the 表7-5.
Data buffer word configuration register
图7-52. DOUT_FORMAT_CFG Register
7
6
5
4
3
2
1
0
RESERVED
R-000000b
DOUT_FORMAT[1:0]
R/W-00b
表7-28. DOUT_FORMAT_CFG Register Field Descriptions
Bit
Field
Type
Reset
000000b
00b
Description
7-2
1-0
RESERVED
R
Reserved bits. Read returns 000000b.
DOUT_FORMAT[1:0]
R/W
These bits select 16-bit content of the data word in the data buffer.
00b = 12-bit conversion result followed by 0000b.
01b = 12-bit conversion result followed by 3-bit channel ID (000b for
CH0, 001b for CH1).
10b = 12-bit conversion result followed by 3-bit channel ID (000b for
CH0, 001b for CH1) followed by DATA_VALID bit.
11b = 12-bit conversion result followed by 0000b.
Copyright © 2022 Texas Instruments Incorporated
56
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.6.1.23 DATA_BUFFER_OPMODE Register (Address = 0x2C) [Reset = 0x1]
DATA_BUFFER_OPMODE is shown in 图7-53 and described in 表7-29.
Return to the 表7-5.
Data buffer operation mode register
图7-53. DATA_BUFFER_OPMODE Register
7
6
5
4
3
2
1
0
RESERVED
R-00000b
STARTSTOP_CNTRL[2:0]
R/W-001b
表7-29. DATA_BUFFER_OPMODE Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
00000b
001b
Description
7-3
2-0
R
Reserved bits. Read returns 00000b.
STARTSTOP_CNTRL[2:0] R/W
These bits select data buffer mode of operation.
000b = Stop burst mode.
001b = Start burst mode, default.
010b = Reserved, do not use.
011b = Reserved, do not use.
100b = Pre alert data mode.
101b = Reserved, do not use.
110b = Post alert data mode.
111b = Reserved, do not use.
7.6.1.24 ACC_EN Register (Address = 0x30) [Reset = 0x0]
ACC_EN is shown in 图7-54 and described in 表7-30.
Return to the 表7-5.
Accumulator control register
图7-54. ACC_EN Register
7
6
5
4
3
2
1
0
RESERVED
R-0000b
EN_ACC[3:0]
R/W-0000b
表7-30. ACC_EN Register Field Descriptions
Bit
Field
Type
Reset
0000b
0000b
Description
7-4
3-0
RESERVED
EN_ACC[3:0]
R
Reserved bits. Read returns 0000b.
R/W
These bits enable accumulator function of device. 0001b to 1110b
settings are reserved. Do not use.
0000b = Accumulator is disabled.
1111b = Accumulator is enabled.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
57
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.6.1.25 ALERT_CHEN Register (Address = 0x34) [Reset = 0x0]
ALERT_CHEN is shown in 图7-55 and described in 表7-31.
Return to the 表7-5.
Alert channel enable register
图7-55. ALERT_CHEN Register
7
6
5
4
3
2
1
0
RESERVED
R-000000b
ALERT_EN_CH ALERT_EN_CH
1
0
R/W-0b
R/W-0b
表7-31. ALERT_CHEN Register Field Descriptions
Bit
Field
Type
Reset
000000b
0b
Description
7-2
1
RESERVED
R
Reserved bits. Read returns 000000b.
ALERT_EN_CH1
R/W
This bit enables alert functionality of CH1.
0b = Alert is disabled for CH1, default.
1b = Alert is enabled for CH1.
0
ALERT_EN_CH0
R/W
0b
This bit enables alert functionality for CH0.
0b = Alert is disabled for CH0, default.
1b = Alert is enabled for CH0.
7.6.1.26 PRE_ALT_MAX_EVENT_COUNT Register (Address = 0x36) [Reset = 0x0]
PRE_ALT_MAX_EVENT_COUNT is shown in 图7-56 and described in 表7-32.
Return to the 表7-5.
Pre-alert count register
图7-56. PRE_ALT_MAX_EVENT_COUNT Register
7
6
5
4
3
2
1
0
PREALERT_COUNT[3:0]
R/W-0000b
RESERVED
R-0000b
表7-32. PRE_ALT_MAX_EVENT_COUNT Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
PREALERT_COUNT[3:0] R/W
0000b
These bits set the Pre-Alert Event Count = PREALERT_COUNT
[7:4] + 1
3-0
RESERVED
R
0000b
Reserved bits. Read returns 0000b.
Copyright © 2022 Texas Instruments Incorporated
58
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.6.1.27 ALERT_DWC_EN Register (Address = 0x37) [Reset = 0x0]
ALERT_DWC_EN is shown in 图7-57 and described in 表7-33.
Return to the 表7-5.
Alert digital window comparator register
图7-57. ALERT_DWC_EN Register
7
6
5
4
3
2
1
0
RESERVED
DWC_BLOCK_
EN
R-0000000b
R/W-0b
表7-33. ALERT_DWC_EN Register Field Descriptions
Bit
Field
Type
Reset
0000000b
0b
Description
7-1
0
RESERVED
R
Reserved bits. Read returns 0000000b.
DWC_BLOCK_EN
R/W
This bit enables digital window comparator block.
0b = Disables digital window comparator.
1b = Enables digital window comparator.
7.6.1.28 DWC_HTH_CH0_LSB Register (Address = 0x38) [Reset = 0x0]
DWC_HTH_CH0_LSB is shown in 图7-58 and described in 表7-34.
Return to the 表7-5.
CH0 high threshold LSB register
图7-58. DWC_HTH_CH0_LSB Register
7
6
5
4
3
2
1
0
HTH_CH0_LSB[7:0]
R/W-00000000b
表7-34. DWC_HTH_CH0_LSB Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
HTH_CH0_LSB[7:0]
R/W
00000000b These are 8 least significant bits of high threshold for CH0.
7.6.1.29 DWC_HTH_CH0_MSB Register (Address = 0x39) [Reset = 0x0]
DWC_HTH_CH0_MSB is shown in 图7-59 and described in 表7-35.
Return to the 表7-5.
CH0 high threshold MSB register
图7-59. DWC_HTH_CH0_MSB Register
7
6
5
4
3
2
1
0
RESERVED
R-0000b
HTH_CH0_MSB[3:0]
R/W-0000b
表7-35. DWC_HTH_CH0_MSB Register Field Descriptions
Bit
Field
Type
Reset
0000b
0000b
Description
7-4
3-0
RESERVED
R
Reserved bits. Read returns 0000b.
These are 4 most significant bits of high threshold for CH0.
HTH_CH0_MSB[3:0]
R/W
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
59
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.6.1.30 DWC_LTH_CH0_LSB Register (Address = 0x3A) [Reset = 0x0]
DWC_LTH_CH0_LSB is shown in 图7-60 and described in 表7-36.
Return to the 表7-5.
CH0 low threshold LSB register
图7-60. DWC_LTH_CH0_LSB Register
7
6
5
4
3
2
1
0
LTH_CH0_LSB[7:0]
R/W-00000000b
表7-36. DWC_LTH_CH0_LSB Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
LTH_CH0_LSB[7:0]
R/W
00000000b These are 8 least significant bits of low threshold for CH0.
7.6.1.31 DWC_LTH_CH0_MSB Register (Address = 0x3B) [Reset = 0x0]
DWC_LTH_CH0_MSB is shown in 图7-61 and described in 表7-37.
Return to the 表7-5.
CH0 low threshold MSB register
图7-61. DWC_LTH_CH0_MSB Register
7
6
5
4
3
2
1
0
RESERVED
R-0000b
LTH_CH0_MSB[3:0]
R/W-0000b
表7-37. DWC_LTH_CH0_MSB Register Field Descriptions
Bit
Field
Type
Reset
0000b
0000b
Description
7-4
3-0
RESERVED
R
Reserved bits. Read returns 0000b.
These are 4 most significant bits of low threshold for CH0.
LTH_CH0_MSB[3:0]
R/W
7.6.1.32 DWC_HTH_CH1_LSB Register (Address = 0x3C) [Reset = 0x0]
DWC_HTH_CH1_LSB is shown in 图7-62 and described in 表7-38.
Return to the 表7-5.
CH1 high threshold LSB register
图7-62. DWC_HTH_CH1_LSB Register
7
6
5
4
3
2
1
0
HTH_CH1_LSB[7:0]
R/W-00000000b
表7-38. DWC_HTH_CH1_LSB Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
HTH_CH1_LSB[7:0]
R/W
00000000b These are 8 least significant bits of high threshold for CH1.
Copyright © 2022 Texas Instruments Incorporated
60
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.6.1.33 DWC_HTH_CH1_MSB Register (Address = 0x3D) [Reset = 0x0]
DWC_HTH_CH1_MSB is shown in 图7-63 and described in 表7-39.
Return to the 表7-5.
CH1 high threshold MSB register
图7-63. DWC_HTH_CH1_MSB Register
7
6
5
4
3
2
1
0
RESERVED
R-0000b
HTH_CH1_MSB[3:0]
R/W-0000b
表7-39. DWC_HTH_CH1_MSB Register Field Descriptions
Bit
Field
Type
Reset
0000b
0000b
Description
7-4
3-0
RESERVED
R
Reserved bits. Read returns 0000b.
These are 4 most significant bits of high threshold for CH1.
HTH_CH1_MSB[3:0]
R/W
7.6.1.34 DWC_LTH_CH1_LSB Register (Address = 0x3E) [Reset = 0x0]
DWC_LTH_CH1_LSB is shown in 图7-64 and described in 表7-40.
Return to the 表7-5.
CH1 low threshold LSB register
图7-64. DWC_LTH_CH1_LSB Register
7
6
5
4
3
2
1
0
LTH_CH1_LSB[7:0]
R/W-00000000b
表7-40. DWC_LTH_CH1_LSB Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
LTH_CH1_LSB[7:0]
R/W
00000000b These are 8 least significant bits of low threshold for CH1.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
61
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
7.6.1.35 DWC_LTH_CH1_MSB Register (Address = 0x3F) [Reset = 0x0]
DWC_LTH_CH1_MSB is shown in 图7-65 and described in 表7-41.
Return to the 表7-5.
CH1 low threshold MSB register
图7-65. DWC_LTH_CH1_MSB Register
7
6
5
4
3
2
1
0
RESERVED
R-0000b
LTH_CH1_MSB[3:0]
R/W-0000b
表7-41. DWC_LTH_CH1_MSB Register Field Descriptions
Bit
Field
Type
Reset
0000b
0000b
Description
7-4
3-0
RESERVED
R
Reserved bits. Read returns 0000b.
LTH_CH1_MSB[3:0]
R/W
These are 4 most significant bits of low threshold for CH1.
7.6.1.36 DWC_HYS_CH0 Register (Address = 0x40) [Reset = 0x0]
DWC_HYS_CH0 is shown in 图7-66 and described in 表7-42.
Return to the 表7-5.
CH0 comparator hysterisis register
图7-66. DWC_HYS_CH0 Register
7
6
5
4
3
2
1
0
RESERVED
R-00b
HYS_CH0[5:0]
R/W-000000b
表7-42. DWC_HYS_CH0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-0
RESERVED
R
00b
Reserved bits. Read returns 00b.
HYS_CH0[5:0]
R/W
000000b
These bits set hysteresis for both comparators for CH0.
7.6.1.37 DWC_HYS_CH1 Register (Address = 0x41) [Reset = 0x0]
DWC_HYS_CH1 is shown in 图7-67 and described in 表7-43.
Return to the 表7-5.
CH1 comparator hysterisis register
图7-67. DWC_HYS_CH1 Register
7
6
5
4
3
2
1
0
RESERVED
R-00b
HYS_CH1[5:0]
R/W-000000b
表7-43. DWC_HYS_CH1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-0
RESERVED
R
00b
Reserved bits. Read returns 00b.
HYS_CH1[5:0]
R/W
000000b
These bits set hysteresis for both comparators for CH1.
Copyright © 2022 Texas Instruments Incorporated
62
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
In an increasing number of industrial applications, data acquisition sub-systems are collecting more data about
the environment in which the system is operating and applying deep learning algorithms in order to improve
system reliability, implement preventative maintenance, and enhance the quality of data collected by the system.
The ADS7142-Q1 can be used to connect to a variety of sensors and can provide deeper data analytics at lower
power levels than existing solutions. The depth of analysis that can be performed on the data collected by the
ADS7142-Q1 is enhanced by the internal data buffer, programmable alarm thresholds and hysteresis, event
counter, and internal calibration circuitry. The applications circuits described in this section highlight specific use
cases of the ADS7142-Q1 for data collection that can further increase the depth and quality of the data being
measured by the system.
8.2 Typical Applications
8.2.1 ADS7142-Q1 as a Programmable Comparator With False Trigger Prevention and Diagnostics
+VDD
R
RL
No 1
VREF(UPPER)
+
A1
VOUT
VIN
R
+
A2
VREF(LOWER)
R
图8-1. Analog Window Comparator
8.2.1.1 Design Requirements
In many automotive sensor monitors, a decision must be made at the system-level when the input signal crosses
a predefined threshold. Analog window comparators are used extensively in such applications.
An analog window comparator has a set of comparators. The external input signal is connected to the inverting
terminal of one comparator and the noninverting terminal of the other comparator. The remaining input of each
comparator is connected to the internal reference. The outputs are tied together and are often connected to a
reset or general-purpose input of a processor (such as a digital signal processor, field-programmable gate array,
or application-specific integrated circuit) or the enable input of a voltage regulator (such as a DC/DC or low-
dropout regulator). 图8-1 shows the circuit diagram for an analog window comparator.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
63
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
Though analog comparators are easy to design, there are certain disadvantages associated with analog
comparators.
• Higher power consumption: If the voltage being monitored is greater than the window comparator supply
voltage, then a resistive divider ladder must scale down that voltage. This resistive ladder draws a constant
current and adds to the power consumption of the system. In battery-powered applications, this current draw
becomes a challenge and can adversely affect the battery life.
• Fixed threshold voltages: The window comparator thresholds cannot be changed on-the-fly because these
thresholds are set by hardware (typically with a resistive ladder). These fixed voltages may add a limitation if
the comparator thresholds must be changed during operation without switching in a new resistor ladder.
Automotive systems often require a device that monitors either critical voltage rails, temperature of the critical
blocks or sensors, and gives an alert or interrupt to the host MCU only when the input being monitored crosses a
predefined, programmable threshold. The ADS7142-Q1 is an excellent fit for such system level monitoring
because this device can autonomously monitor sensor outputs and can wake up the host controller whenever
the sensor output crosses predefined thresholds. Additionally, the ADS7142-Q1 has an internal data buffer that
can store 16 sample data that can read in case further analysis is required. 图8-2 shows a typical block diagram
of the ADS7142-Q1 as a sensor monitor. As is shown in this figure, the sensor can be connected directly to the
input of the ADC (depending on the sensor output signal characteristics).
3V3
RFLT
SCL
C
AIN0
ADS7142-Q1
AIN1
Sensor 1
SDA
ALERT
Host MCU
GND
GND
RFLT
BUSY/RDY
C
Sensor 2
GND
GND
GND
GND
图8-2. Sensor Monitor Circuit With the ADS7142-Q1
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Programmable Thresholds and Hysteresis
The ADS7142-Q1 can be programmed to monitor sensor output voltages and generate an ALERT signal to the
host controller if the sensor output voltage crosses a threshold.
The device can be configured to monitor for signals rising above a programmed threshold. 图 8-3 illustrates the
operation of the device when monitoring for signal crossings on the low threshold by setting the high threshold to
0xFFF. In this case, the output of the low-side comparator is set whenever the ADC conversion result is less than
or equal to the low threshold, and the output of the high-side comparator is only set when the ADC conversion
result is equal to 0xFFF.
The device can also be configured to monitor for signals falling below a programmed threshold. 图 8-4 illustrates
the operation of the device when monitoring for signal crossings on the high threshold by setting the low
threshold to 0x000. In this case, the output of high-side comparator is set whenever the ADC conversion result is
greater than or equal to the high threshold and the output of the low-side comparator is only set when the ADC
conversion result is equal to 0x000.
Copyright © 2022 Texas Instruments Incorporated
64
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
High Threshold = 0xFFF
œ
Hysteresis
High Threshold - Hysteresis
+
High Side Comparator
Conversion [N] for CHx
Low Side Comparator
œ
Low Threshold + Hysteresis
Low Threshold
+
Conversion [N+5] for CHx
Conversion [N+10] for CHx
PRE_ALT_MAX_EVENT_COUNT = 50h
High Side Comparator Output
(Internal Signal Only)
Low Side Comparator Output
(Internal Signal Only)
ALERT
图8-3. Low Alert With the ADS7142-Q1
PRE_ALT_MAX_EVENT_COUNT = 50h
Conversion [N+9] for CHx
Conversion [N+4] for CHx
Hysteresis
High Threshold
High Threshold - Hysteresis
œ
+
High Side Comparator
Low Side Comparator
œ
Low Threshold + Hysteresis
+
Conversion [N] for CHx
Low Threshold = 0x000
Low Side Comparator Output
(Internal Signal Only)
High Side Comparator Output
(Internal Signal Only)
ALERT
图8-4. High Alert With the ADS7142-Q1
The device can also be configured to monitor for signals falling outside of a programmed window. 图 8-5 shows
the device operation for an out-of-range alert where the signal leaves the predefined window and crosses either
the high or low threshold. In this case, the output of the low-side comparator is set whenever the ADC
conversion result is less than or equal to the low threshold, and the output of the high-side comparator is set
when the ADC conversion result is greater than or equal to the high threshold.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
65
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
PRE_ALT_MAX_EVENT_COUNT = 50h
Conversion [N+12] for CHx
Conversion [N+7] for CHx
Hysteresis
High Threshold
œ
High Threshold - Hysteresis
+
High Side Comparator
Low Side Comparator
œ
Low Threshold + Hysteresis
Low Threshold
+
Conversion [N] for CHx
Low Side Comparator Output
(Internal Signal Only)
High Side Comparator Output
(Internal Signal Only)
ALERT
图8-5. Out of Range Alert With the ADS7142-Q1
8.2.1.2.2 False Trigger Prevention With an Event Counter
The pre-alert event counter in the digital window comparator helps prevent false triggers. The alert output is not
set until the output of the comparator remains set for a predefined number (count) of consecutive conversions.
8.2.1.2.3 Fault Diagnostics With the Data Buffer
The modes that are specifically designed for autonomous sensor monitor applications are pre-alert mode and
post-alert mode. In pre-alert mode, the ADS7142-Q1 can be configured to monitor sensor outputs and
continuously fill the internal data buffer until a threshold crossing occurs. The ADS7142-Q1 generates an ALERT
signal when the sensor output falls outside of the predefined window of operation. In this particular mode, the
ADS7142-Q1 stops filling the data buffer when the threshold is crossed and provides the last 16 samples (15
sample data preceding the sample at which the ALERT is generated and 1 sample data for which the ALERT is
generated). 图 8-6 depicts the ADS7142-Q1 operation in pre-alert mode showing 16 data samples before the
sensor output crosses the low threshold. This operation is useful for applications where the state of the signal
before the threshold is crossed is important to capture. Using the data captured before the alert, deep data
analysis can be performed to determine the state of the system before the alert. This type of data is not available
with analog comparators.
In post-alert mode, ADS7142-Q1 can be configured to monitor sensor outputs and start filling the internal data
buffer after a threshold crossing occurs. The ADS7142-Q1 generates an ALERT signal when the sensor output
falls outside of the predefined window of operation. In this particular mode, the ADS7142-Q1 continues to fill the
data buffer after the threshold is crossed for a total of 16 samples (1 sample data for which ALERT is generated
and 15 sample data after the sample at which ALERT is generated). 图 8-7 illustrates the ADS7142-Q1
operation in post-alert mode showing 16 data samples after the sensor output crosses the high threshold. This
operation is useful for applications where the state of the signal after the threshold is crossed is important to
capture. Using the data captured after the alert, deep data analysis can be performed for to determine the state
of the system after the alert to detect system-level events such as saturation. This data is not available with
analog comparators.
Copyright © 2022 Texas Instruments Incorporated
66
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
8.2.1.3 Application Curves
图8-6. Pre-Alert Data Capture
图8-7. Post-Alert Data Capture
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
67
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
8.2.2 Voltage and Temperature Monitoring in Remote Camera Modules Using the ADS7142-Q1
CO-AXIAL CABLE
HOST
CONTROLLER
(Image
FPD
LINK
FPD
LINK
IMAGER
NTC
I2C
I2C
Processing)
De-Serializer
Serializer
DC-DC
OR
LDO
DC/DC
OR
LDO
VBAT
ADS7142-Q1
图8-8. Voltage and Temperature Sensing in Remote Camera Modules Using the ADS7142-Q1
8.2.2.1 Design Requirements
Camera modules are an integral part of advanced driver assistance systems (ADAS), which are designed to
make cars safer. Automotive cameras and camera modules are often assist in blind spot detection, nap
prevention, lane and border detection, surround view and parking. Based on application, there are multiple types
of camera modules available such as front camera, rear camera, night vision camera. 图 8-8 shows the typical
block diagram of camera module used in an automotive environment with key electronics building blocks in the
system.
The camera module is usually situated externally at front, back or either side of the vehicle. Many times the main
controller that does the data processing can not be used on camera module side due to size constraints. The
camera module unit communicates with central processor over co-axial cable. The camera module data is
transmitted over a coaxial cable using a serializer. On the data processing unit, a deserializer is used to
communicate this data with the host processor. The power to the camera module is also transmitted over a
coaxial cable. Because the camera module is remotely placed and power is transferred over a coaxial cable that
can be few meters long, voltage received by camera module and critical voltage rails powering image sensors
are often monitored against permissible variations. Also, the difference between camera lens and external
ambient temperature can introduce dampness and degrade video quality. To ensure optimal video quality,
camera lens temperature is often monitored for any possible correction. The device monitoring these system-
level parameters must be a small size because of the limited board space available on the camera module side.
Also, the I2C interface is preferred because this interface enables the user to connect multiple monitoring and
sensing devices on the same I2C bus. The ADS7142-Q1 small footprint (2-mm × 3-mm, WSON package) and
the I2C interface capable of working over wide digital I/O voltages enable this device in camera module
monitoring applications without demanding extra board space.
8.3 Power Supply Recommendations
8.3.1 AVDD and DVDD Supply Recommendations
The ADS7142-Q1 has two separate power supplies: AVDD and DVDD. The device operates on AVDD; DVDD is
used for the interface circuits. AVDD and DVDD can be independently set to any value within the permissible
ranges. The AVDD supply also defines the full-scale input range of the device. Always set the AVDD supply to
be greater than or equal to the maximum input signal to avoid saturation of codes. Decouple the AVDD and
DVDD pins respectively with CAVDD = 220 nF and CDVDD = 100 nF ceramic decoupling capacitors, as illustrated
in 图8-9.
Copyright © 2022 Texas Instruments Incorporated
68
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
AVDD
GND
CAVDD
CDVDD
DVDD
图8-9. Power-Supply Decoupling
8.4 Layout
8.4.1 Layout Guidelines
• Use a solid ground plane underneath the device and partition the PCB into analog and digital sections.
• Avoid crossing digital lines with the analog signal path and keep the analog input signals and the reference
input signals away from noise sources.
• The power sources to the device must be clean and well-bypassed. Use CAVDD decoupling capacitors in
close proximity to the analog (AVDD) power-supply pin.
• Use a CDVDD decoupling capacitor close to the digital (DVDD) power-supply pin.
• Avoid placing vias between the AVDD and DVDD pins and the bypass capacitors.
• Connect the ground pin to the ground plane using a short, low-impedance path. Also connect the thermal pad
to the ground plane.
• Place the charge kickback filter components close to the device.
Among ceramic surface-mount capacitors, COG (NPO) ceramic capacitors are recommended because these
components provide the most stable electrical properties over voltage, frequency, and temperature changes.
图8-10 shows the typical connection diagram of the ADS7142-Q1.
DVDD
CDVDD
ADS7142-Q1
GND
DVDD
SCL
1
2
10
9
RSDA
RALERT
RSCL
CAVDD
AVDD
To I2C Controller
RFLT0
SDA
To I2C Controller
From Sensor
Output
8
3
AINP/AIN0
CFLT0
RFLT1
CFLT1
To I2C Controller
To I2C Controller
From Sensor
Output
7
6
ALERT
4
5
AINM/AIN1
ADDR
RADDR1
BUSY/RDY
AVDD
RADDR2
PAD
图8-10. Example Schematic
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
69
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
8.4.2 Layout Example
图8-11. Example Layout
Copyright © 2022 Texas Instruments Incorporated
70
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
9 Device and Documentation Support
9.1 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.2 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
9.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.4 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.5 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
71
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
Copyright © 2022 Texas Instruments Incorporated
72
Submit Document Feedback
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
73
Product Folder Links: ADS7142-Q1
ADS7142-Q1
ZHCSJ06B –NOVEMBER 2017 –REVISED SEPTEMBER 2022
www.ti.com.cn
Copyright © 2022 Texas Instruments Incorporated
74
Submit Document Feedback
Product Folder Links: ADS7142-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS7142QDQCRQ1
ACTIVE
WSON
DQC
10
3000 RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
1AU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS7142-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
Catalog : ADS7142
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Mar-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS7142QDQCRQ1
WSON
DQC
10
3000
180.0
8.4
2.3
3.2
1.0
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Mar-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WSON DQC 10
SPQ
Length (mm) Width (mm) Height (mm)
213.0 191.0 35.0
ADS7142QDQCRQ1
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DQC0010A
WSON - 0.8mm max height
S
C
A
L
E
4
.
5
0
0
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.3
0.2
0.35
0.25
OPTIONAL TERMINAL
TYPICAL
C
0.8 MAX
SEATING PLANE
0.08
0.84 0.1
SYMM
(0.2) TYP
0.05
0.00
5
6
8X 0.5
2X
2
SYMM
11
2.4 0.1
SEE OPTIONAL
TERMINAL
DETAIL
1
10
0.3
10X
0.2
0.1
0.05
PIN 1 ID
(45 X0.2)
C A B
C
0.4
10X
0.2
4218281/C 11/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DQC0010A
WSON - 0.8mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.84)
(
0.2) TYP
10X (0.5)
VIA
1
10
10X (0.25)
(0.95)
11
SYMM
(2.4)
8X (0.5)
6
5
(R0.05) TYP
SYMM
(1.9)
LAND PATTERN EXAMPLE
SCALE: 30X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218281/C 11/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DQC0010A
WSON - 0.8mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.8)
10X (0.5)
10
10X (0.25)
1
(1.08)
11
SYMM
8X (0.5)
(0.64)
METAL
TYP
6
5
(R0.05) TYP
SYMM
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
86% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE: 30X
4218281/C 11/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
ADS7223
Dual, 1MSPS, 16-/14-/12-Bit, 4x2 or 2x2 Channel, Simultaneous Sampling Analog-to-Digital Converter
TI
ADS7223SRHBR
Dual, 1MSPS, 16-/14-/12-Bit, 4 2 or 2 2 Channel, Simultaneous Sampling Analog-to-Digital Converter
TI
ADS7223SRHBT
Dual, 1MSPS, 16-/14-/12-Bit, 4 2 or 2 2 Channel, Simultaneous Sampling Analog-to-Digital Converter
TI
ADS7229
LOW-POWER, 12-BIT, 1MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE
TI
ADS7229I
LOW-POWER, 12-BIT, 1MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE
TI
ADS7229IPW
LOW-POWER, 12-BIT, 1MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE
TI
ADS7229IPWG4
LOW-POWER, 12-BIT, 1MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE
TI
ADS7229IPWR
LOW-POWER, 12-BIT, 1MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE
TI
ADS7229IPWRG4
LOW-POWER, 12-BIT, 1MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE
TI
ADS7229IRSAR
LOW-POWER, 12-BIT, 1MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE
TI
ADS7229IRSARG4
LOW-POWER, 12-BIT, 1MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE
TI
ADS7229IRSAT
LOW-POWER, 12-BIT, 1MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE
TI
©2020 ICPDF网 联系我们和版权申明