ADS7807 [TI]

低功耗 16 位采样 CMOS 模数转换器;


型号：	ADS7807
厂家：	TEXAS INSTRUMENTS
描述：	低功耗 16 位采样 CMOS 模数转换器转换器模数转换器
文件：	总28页 (文件大小：651K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS7807

S7807

SBAS022D – NOVEMBER 1992 – REVISED NOVEMBER 2006

Low-Power, 16-Bit, Sampling CMOS

ANALOG-to-DIGITAL CONVERTER

FEATURES

DESCRIPTION

ꢀ 35mW max POWER DISSIPATION

The ADS7807 is a low-power, 16-bit, sampling Analog-to-

Digital (A/D) converter using state-of-the-art CMOS struc-

tures. It contains a complete 16-bit, capacitor-based, Suc-

cessive Approximation Register (SAR) A/D converter with

sample-and-hold, clock, reference, and microprocessor inter-

face with parallel and serial output drivers.

ꢀ 50µW POWER-DOWN MODE

ꢀ 25µs max ACQUISITION AND CONVERSION

ꢀ ±1.5LSB max INL

ꢀ DNL: 16 Bits, No Missing Codes

ꢀ 86dB min SINAD WITH 1kHz INPUT

The ADS7807 can acquire and convert 16 bits to within

±1.5LSB in 25µs max while consuming only 35mW max.

Laser trimmed scaling resistors provide standard industrial

input ranges of ±10V and 0V to +5V. In addition, a 0V to +4V

range allows development of complete single-supply sys-

tems.

ꢀ ±10V, 0V TO +5V, AND 0V TO +4V INPUT RANGES

ꢀ SINGLE +5V SUPPLY OPERATION

ꢀ PARALLEL AND SERIAL DATA OUTPUT

ꢀ PIN-COMPATIBLE WITH THE 12-BIT ADS7806

ꢀ USES INTERNAL OR EXTERNAL REFERENCE

ꢀ 0.3" DIP-28 AND SO-28

The ADS7807 is available in a 0.3" DIP-28 and SO-28, both

fully specified for operation over the industrial –40°C to

+85°C temperature range.

R/C

BYTE

Clock

Successive Approximation Register and Control Logic

Power

Down

40kΩ

CDAC

R1_IN

BUSY

Parallel

and

Serial Data

Clock

20kΩ

40kΩ

10kΩ

Serial

Data

Out

Comparator

R2_IN

Serial Data

CAP

Parallel Data

Buffer

6kΩ

Internal

+2.5V Ref

Reference

Power-Down

REF

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

www.ti.com

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

Analog Inputs: R1_IN........................................................................... ±12V

R2_IN.......................................................................... ±5.5V

CAP .................................. V_ANA+ 0.3V to AGND2 – 0.3V

REF ......................................... Indefinite Short to AGND2,

Momentary Short to V_ANA

Ground Voltage Differences: DGND, AGND1, and AGND2 ............. ±0.3V

V_ANA....................................................................................................... 7V

_DIGto V_ANA...................................................................................... +0.3V

_DIG........................................................................................................ 7V

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

Digital Inputs ............................................................. –0.3V to V_DIG+ 0.3V

Maximum Junction Temperature ................................................... +165°C

Internal Power Dissipation ............................................................. 825mW

Lead Temperature (soldering, 10s) ............................................... +300°C

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”

may cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

PACKAGE/ORDERING INFORMATION⁽¹⁾

MINIMUM

MAXIMUM

INTEGRAL

SPECIFIED

NO MISSING

SIGNAL-TO-

(NOISE +

SPECIFIED

LINEARITY

ERROR (LSB)

CODE LEVEL DISTORTION)

PACKAGE

TEMPERATURE PACKAGE

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

PRODUCT

(LSB)

RATIO (DB) PACKAGE-LEAD DESIGNATOR

RANGE

MARKING

ADS7807P

±3

DIP-28

–40°C to +85°C

ADS7807P

ADS7807PB

ADS7807U

ADS7807U/1K Tape and Reel, 1000

ADS7807UB Tubes, 28

ADS7807UB/1K Tape and Reel, 1000

Tubes, 13

Tubes, 28

ADS7807PB

ADS7807U

±1.5

±3

SO-28

ADS7807PB

–40°C to +85°C ADS7807U

ADS7807UB

±1.5

ADS7807UB

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at

www.ti.com.

ELECTRICAL CHARACTERISTICS

At T_A= –40°C to +85°C, f_S= 40kHz, V_DIG= V_ANA= +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified.

ADS7807P, U

TYP

ADS7807PB, UB

TYP

PARAMETER

RESOLUTION

CONDITIONS

MIN

MAX

MIN

MAX

UNITS

ꢀ

Bits

ANALOG INPUT

Voltage Ranges

Impedance

±10, 0 to +5, 0 to +4

(See Table I)

Capacitance

ꢀ

THROUGHPUT SPEED

Conversion Time

Complete Cycle

ꢀ

µs

kHz

Acquire and Convert

Throughput Rate

DC ACCURACY

Integral Linearity Error

Differential Linearity Error

No Missing Codes

Transition Noise⁽²⁾

Gain Error

Full-Scale Error^(3,4)

±3

+3, –2

±1.5

+1.5, –1

LSB⁽¹⁾

LSB

Bits

LSB

ppm/°C

0.8

±0.2

ꢀ

±0.1

±0.5

±10

±3

±0.25

ꢀ

Full-Scale Error Drift

Full-Scale Error^(3,4)

±7

±5

ꢀ

Ext. 2.5000V Ref

±10V Range

Full-Scale Error Drift

Bipolar Zero Error⁽³⁾

Bipolar Zero Error Drift

Unipolar Zero Error⁽³⁾

Unipolar Zero Error Drift

Recovery Time to Rated Accuracy

from Power-Down⁽⁵⁾

Power-Supply Sensitivity

(V_DIG= V_ANA= V_S)

±0.5

±10V Range

0V to 5V, 0V to 4V Ranges

2.2µF Capacitor to CAP

ꢀ

±0.5

ꢀ

+4.75V < V_S< +5.25V

±8

ꢀ

LSB

ADS7807

SBAS022D

www.ti.com

ELECTRICAL CHARACTERISTICS (Cont.)

At T_A= –40°C to +85°C, f_S= 40kHz, V_DIG= V_ANA= +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified.

ADS7807P, U

TYP

ADS7807PB, UB

TYP

PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

UNITS

AC ACCURACY

Spurious-Free Dynamic Range

Total Harmonic Distortion

Signal-to-(Noise + Distortion)

_IN= 1kHz, ±10V

100

–100

ꢀ

dB⁽⁶⁾

f_IN= 1kHz, ±10V

–90

–96

f_IN= 1kHz, ±10V

–60dB Input

Signal-to-Noise

Usable Bandwidth⁽⁷⁾

Full-Power Bandwidth (–3dB)

f_IN= 1kHz, ±10V

130

600

kHz

SAMPLING DYNAMICS

Aperture Delay

Aperture Jitter

Transient Response

Over-Voltage Recovery⁽⁸⁾

ꢀ

µs

FS Step

No Load

ꢀ

750

ꢀ

REFERENCE

Internal Reference Voltage

Internal Reference Source Current

(Must use external buffer.)

Internal Reference Drift

External Reference Voltage Range

for Specified Linearity

2.48

2.3

2.5

2.52

ꢀ

µA

2.5

ꢀ

ppm/°C

2.7

ꢀ

External Reference Current Drain

External 2.5000V Ref

100

µA

DIGITAL INPUTS

Logic Levels

V_IL

V_IH

I_IL

–0.3

+2.0

+0.8

V_D+ 0.3V

±10

ꢀ

µA

(9)

V_IL= 0V

V_IH= 5V

I_IH

±10

DIGITAL OUTPUTS

Data Format

Data Coding

V_OL

Parallel 16 bits in 2-bytes; Serial

Binary Two’s Complement or Straight Binary

I_SINK= 1.6mA

I_SOURCE= 500µA

High-Z State,

+0.4

ꢀ

µA

V_OH

ꢀ

Leakage Current

±5

V_OUT= 0V to V_DIG

Output Capacitance

High-Z State

DIGITAL TIMING

Bus Access Time

Bus Relinquish Time

R_L= 3.3kΩ, C_L= 50pF

R_L= 3.3kΩ, C_L= 10pF

ꢀ

POWER SUPPLIES

Specified Performance

V_DIG

V_ANA

I_DIG

I_ANA

Must be ≤ V_ANA

+4.75

0.6

5.0

+5.25

ꢀ

µW

Power Dissipation

V_ANA= V_DIG= 5V, f_S= 40kHz

REFD HIGH

PWRD and REFD HIGH

ꢀ

TEMPERATURE RANGE

Specified Performance

Derated Performance

Storage

–40

–55

–65

+85

+125

+150

ꢀ

°C

Thermal Resistance (θ_JA

)

DIP

ꢀ

°C/W

ꢀ Same specifications as ADS7807P, U.

NOTES: (1) LSB means Least Significant Bit. One LSB for the ±10V input range is 305µV.

(2) Typical rms noise at worst-case transition.

(3) As measured with fixed resistors, see Figure 7b. Adjustable to zero with external potentiometer.

(4) Full-scale error is the worst case of –Full-Scale or +Full-Scale untrimmed deviation from ideal first and last code transitions, divided by the

transition voltage (not divided by the full-scale range) and includes the effect of offset error.

(5) This is the time delay after the ADS7807 is brought out of Power-Down mode until all internal settling occurs and the analog input is acquired to

rated accuracy. A Convert command after this delay will yield accurate results.

(6) All specifications in dB are referred to a full-scale input.

(7) Usable bandwidth defined as full-scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60dB.

(8) Recovers to specified performance after 2 • FS input overvoltage.

(9) The minimum V_IHlevel for the DATACLK signal is 3V.

ADS7807

SBAS022D

www.ti.com

PIN DESCRIPTIONS

DIGITAL

PIN #

NAME

I/O

DESCRIPTION

R1_IN

AGND1

R2_IN

CAP

REF

AGND2

SB/BTC

EXT/INT

Analog Input. See Figure 7.

Analog Sense Ground.

Analog Input. See Figure 7.

Reference Buffer Output. 2.2µF tantalum capacitor to ground.

Reference Input/Output. 2.2µF tantalum capacitor to ground.

Analog Ground

Selects Straight Binary or Binary Two’s Complement for Output Data Format.

External/Internal data clock select.

Data Bit 7 if BYTE is HIGH. Data bit 15 (MSB) if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW. Leave

unconnected when using serial output.

DGND

Data Bit 6 if BYTE is HIGH. Data bit 14 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.

Data Bit 5 if BYTE is HIGH. Data bit 13 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.

Data Bit 4 if BYTE is HIGH. Data bit 12 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.

Data Bit 3 if BYTE is HIGH. Data bit 11 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.

Digital Ground

Data Bit 2 if BYTE is HIGH. Data bit 10 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.

Data Bit 1 if BYTE is HIGH. Data bit 9 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.

Data Bit 0 (LSB) if BYTE is HIGH. Data bit 8 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.

Data Clock Output when EXT/INT is LOW. Data clock input when EXT/INT is HIGH.

Serial Output Synchronized to DATACLK

I/O

DATACLK

SDATA

TAG

BYTE

R/C

Serial Input When Using an External Data Clock

Selects 8 most significant bits (LOW) or 8 least significant bits (HIGH) on parallel output pins.

With CS LOW and BUSY HIGH, a Falling Edge on R/C Initiates a New Conversion. With CS LOW, a rising edge on R/C

enables the parallel output.

Internally OR’d with R/C. If R/C is LOW, a falling edge on CS initiates a new conversion. If EXT/INT is LOW, this same

falling edge will start the transmission of serial data results from the previous conversion.

At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs

have been updated.

BUSY

PWRD

REFD

V_ANA

PWRD HIGH shuts down all analog circuitry except the reference. Digital circuitry remains active.

REFD HIGH shuts down the internal reference. External reference will be required for conversions.

Analog Supply. Nominally +5V. Decouple with 0.1µF ceramic and 10µF tantalum capacitors.

V_DIG

Digital Supply. Nominally +5V. Connect directly to pin 27. Must be ≤ V_ANA.

PIN CONFIGURATION

ANALOG

INPUT

RANGE

CONNECT R1_IN

VIA 200Ω

CONNECT R2_IN

VIA 100Ω

IMPEDANCE

Top View

DIP, SO

±10V

0V to 5V

0V to 4V

V_IN

AGND

V_IN

CAP

V_IN

45.7kΩ

20.0kΩ

21.4kΩ

R1_IN

AGND1

R2_IN

28 V_DIG

27 V_ANA

26 REFD

25 PWRD

24 BUSY

23 CS

TABLE I. Input Range Connections. See Figure 7.

CAP

REF

AGND2

SB/BTC

EXT/INT

22 R/C

ADS7807

21 BYTE

20 TAG

19 SDATA

18 DATACLK

17 D0

D6 10

D5 11

D4 12

D3 13

16 D1

DGND 14

15 D2

ADS7807

SBAS022D

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TYPICAL CHARACTERISTICS

At T_A= +25°C, f_S= 40kHz, V_DIG= V_ANA= +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified.

FREQUENCY SPECTRUM

(8192 Point FFT; f_IN= 15kHz, 0dB)

(8192 Point FFT; f_IN= 1kHz, 0dB)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–100

–110

–120

–130

Frequency (kHz)

SIGNAL-TO-(NOISE + DISTORTION)

vs INPUT FREQUENCY (f_IN= 0dB)

SIGNAL-TO-(NOISE + DISTORTION)

vs INPUT FREQUENCY AND INPUT AMPLITUDE

100

0dB

–20dB

–60dB

100

10k

100k

Input Signal Frequency (kHz)

Input Signal Frequency (Hz)

SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE

(f_IN= 1kHz, 0dB; f_S= 10kHz to 40kHz)

AC PARAMETERS vs TEMPERATURE

(f_IN= 1kHz, 0dB)

100

110

105

100

–80

SFDR

–85

10kHz

30kHz

–90

20kHz

40kHz

–95

THD

SNR

–100

–105

–110

SINAD

–75 –50 –25

100 125 150

–75 –50 –25

100 125 150

Temperature (°C)

ADS7807

SBAS022D

www.ti.com

TYPICAL CHARACTERISTICS (Cont.)

At T_A= +25°C, f_S= 40kHz, V_DIG= V_ANA= +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified.

POWER-SUPPLY RIPPLE SENSITIVITY

INL/DNL DEGRADATION PER LSB OF P-P RIPPLE

LINEARITY ERROR vs CODE

10^–1

10^–2

10^–3

10^–4

10^–5

–1

–2

–3

All Codes INL

INL

–1

–2

–3

DNL

All Codes DNL

10¹

10²

10³

10⁴

10⁵

10⁶

10⁷

8192 16384 24576 32768 40960 49152 57344 65535

Decimal Code

Power-Supply Ripple Frequency (Hz)

ENDPOINT ERRORS (20V Bipolar Range)

ENDPOINT ERRORS (Unipolar Ranges)

BPZ Error

UPO Error

–1

–2

–1

–2

0.20

0.40

0.20

+F_SError

+F_SError (4V Range)

–0.20

0.20

0.40

–F_SError

–F_SError (5V Range)

0.20

–0.20

–75 –50

–25

100

125

150

–75 –50

–25

100

125

150

Temperature (°C)

INTERNAL REFERENCE VOLTAGE vs TEMPERATURE

CONVERSION TIME vs TEMPERATURE

2.520

2.515

2.510

2.505

2.500

2.495

2.490

2.485

2.480

19.4

19.2

18.8

18.6

–75 –50 –25

100 125 150

–75 –50 –25

100 125 150

Temperature (°C)

ADS7807

SBAS022D

www.ti.com

output valid data from the previous conversion on SDATA

(pin 19) synchronized to 16 clock pulses output on DATACLK

(pin 18). BUSY (pin 24) will go LOW and stay LOW until the

conversion is completed and the serial data has been trans-

mitted. Data will be output in BTC format, MSB first, and will

be valid on both the rising and falling edges of the data clock.

BUSY going HIGH can be used to latch the data. All convert

commands will be ignored while BUSY is LOW.

BASIC OPERATION

PARALLEL OUTPUT

Figure 1a shows a basic circuit to operate the ADS7807 with

a ±10V input range and parallel output. Taking R/C (pin 22)

LOW for a minimum of 40ns (12µs max) will initiate a

conversion. BUSY (pin 24) will go LOW and stay LOW until

the conversion is completed and the output register is up-

dated. If BYTE (pin 21) is LOW, the eight Most Significant

Bits (MSBs) will be valid when BUSY rises; if BYTE is HIGH,

the eight Least Significant Bits (LSBs) will be valid when

BUSY rises. Data will be output in Binary Two’s Complement

(BTC) format. BUSY going HIGH can be used to latch the

data. After the first byte has been read, BYTE can be toggled

allowing the remaining byte to be read. All convert com-

mands will be ignored while BUSY is LOW.

The ADS7807 will begin tracking the input signal at the end

of the conversion. Allowing 25µs between convert com-

mands assures accurate acquisition of a new signal.

The offset and gain are adjusted internally to allow external

trimming with a single supply. The external resistors compen-

sate for this adjustment and can be left out if the offset and

gain will be corrected in software (refer to the Calibration

section).

The ADS7807 will begin tracking the input signal at the end

of the conversion. Allowing 25µs between convert com-

mands assures accurate acquisition of a new signal.

STARTING A CONVERSION

The combination of CS (pin 23) and R/C (pin 22) LOW for a

minimum of 40ns puts the sample-and-hold of the ADS7807

in the hold state and starts conversion ‘n’. BUSY (pin 24) will

go LOW and stay LOW until conversion ‘n’ is completed and

the internal output register has been updated. All new con-

vert commands during BUSY LOW will be ignored. CS and/

or R/C must go HIGH before BUSY goes HIGH, or a new

conversion will be initiated without sufficient time to acquire

a new signal.

The offset and gain are adjusted internally to allow external

trimming with a single supply. The external resistors compen-

sate for this adjustment and can be left out if the offset and gain

will be corrected in software (refer to the Calibration section).

SERIAL OUTPUT

Figure 1b shows a basic circuit to operate the ADS7807 with

a ±10V input range and serial output. Taking R/C (pin 22)

LOW for 40ns (12µs max) will initiate a conversion and

Parallel Output

Serial Output

200Ω

±10V

0.1µF 10µF

+5V

0.1µF 10µF

66.5kΩ

2.2µF

+5V

66.5kΩ

2.2µF

+5V

100Ω

2.2µF

100Ω

2.2µF

BUSY

+5V

BUSY

R/C

Convert Pulse

40ns min

R/C

Convert Pulse

40ns min

ADS7807

BYTE

ADS7807

NC⁽¹⁾

SDATA

DATACLK

NC⁽¹⁾

Pin 21 B15 B14 B13 B12 B11

LOW (MSB)

B10 B9 B8

B2 B1 B0

Pin 21 B7 B6 B5 B4 B3

HIGH

(LSB)

NOTE: (1) These pins should be left unconnected.

They will be active when R/C is HIGH.

NOTE: (1) SDATA (pin 19) is always active.

FIGURE 1b. Basic ±10V Operation with Serial Output.

FIGURE 1a. Basic ±10V Operation, both Parallel and Serial

Output.

ADS7807

SBAS022D

www.ti.com

The ADS7807 will begin tracking the input signal at the end

of the conversion. Allowing 25µs between convert com-

mands assures accurate acquisition of a new signal. Refer to

CS and R/C are internally OR’ed and level triggered. There

is not a requirement which input goes LOW first when

initiating a conversion. If, however, it is critical that CS or R/C

initiates conversion ‘n’, be sure the less critical input is LOW

at least 10ns prior to the initiating input. If EXT/INT (pin 8) is

LOW when initiating conversion ‘n’, serial data from conver-

sion ‘n – 1’ will be output on SDATA (pin 19) following the

start of conversion ‘n’. See Internal Data Clock in the Read-

ing Data section.

Tables II and III for a summary of CS

, R/C, and BUSY states,

and Figures 2 through 6 for timing diagrams.

R/C BUSY OPERATION

None. Databus is in Hi-Z state.

↓

Initiates conversion ‘n’. Databus remains

in Hi-Z state.

To reduce the number of control pins, CS can be tied LOW

using R/C to control the read and convert modes. This will

have no effect when using the internal data clock in the serial

output mode. The parallel output and the serial output (only

when using an external data clock), however, will be affected

whenever R/C goes HIGH. Refer to the Reading Data

section.

↓

↑

Initiates conversion ‘n’. Databus enters Hi-Z

state.

Conversion ‘n’ completed. Valid data from

conversion ‘n’ on the databus.

Enables databus with valid data from

conversion ‘n’.

Enables databus with valid data from

conversion ‘n – 1’⁽¹⁾. Conversion n in progress.

Enables databus with valid data from

READING DATA

conversion ‘n – 1’⁽¹⁾. Conversion ‘n’ in progress.

The ADS7807 outputs serial or parallel data in Straight Binary

(SB) or Binary Two’s Complement data output format. If

SB/BTC (pin 7) is HIGH, the output will be in SB format, and

if LOW, the output will be in BTC format. Refer to Table IV for

ideal output codes.

New conversion initiated without acquisition

of a new signal. Data will be invalid. CS and/or

R/C must be HIGH when BUSY goes HIGH.

New convert commands ignored. Conversion

‘n’ in progress.

NOTE: (1) See Figures 2 and 3 for constraints on data valid from

The parallel output can be read without affecting the internal

output registers; however, reading the data through the serial

port will shift the internal output registers one bit per data

conversion ‘n – 1’.

TABLE II. Control Functions When Using Parallel Output

(DATACLK tied LOW, EXT/INT tied HIGH).

↓

R/C

BUSY

EXT/INT

DATACLK

Output

Input

OPERATION

Initiates conversion ‘n’. Valid data from conversion ‘n – 1’ clocked out on SDATA.

Initiates conversion ‘n’. Internal clock still runs conversion process.

↓

Input

Initiates conversion ‘n’. Internal clock still runs conversion process.

↓

Input

Conversion ‘n’ completed. Valid data from conversion ‘n’ clocked out on SDATA synchronized

to external data clock.

↓

↑

Input

Valid data from conversion ‘n – 1’ output on SDATA synchronized to external data clock.

Conversion ‘n’ in progress.

Valid data from conversion ‘n – 1’ output on SDATA synchronized to external data clock.

Conversion ‘n’ in progress.

New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/C

must be HIGH when BUSY goes HIGH.

New convert commands ignored. Conversion ‘n’ in progress.

NOTE: (1) See Figures 4, 5, and 6 for constraints on data valid from conversion ‘n – 1’.

TABLE III. Control Functions When Using Serial Output.

DIGITAL OUTPUT

DESCRIPTION

ANALOG INPUT

BINARY TWO’S COMPLEMENT

STRAIGHT BINARY

(SB/BTC HIGH)

Full-Scale Range

±10

0V to 5V

0V to 4V

(SB/BTC LOW)

Least Significant Bit (LSB)

305µV

76µV

61µV

HEX

CODE

7FFF

0000

HEX

CODE

FFFF

8000

BINARY CODE

+Full-Scale (FS – 1LSB)

Midscale

9.999695V

4.999924V

2.5V

3.999939V

0111 1111 1111 1111

0000 0000 0000 0000

1111 1111 1111 1111

1000 0000 0000 0000

1111 1111 1111 1111

1000 0000 0000 0000

0111 1111 1111 1111

0000 0000 0000 0000

One LSB Below Midscale

–Full-Scale

–305µV

–10V

2.499924V

1.999939V

FFFF

8000

7FFF

0000

TABLE IV. Output Codes and Ideal Input Voltages.

ADS7807

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clock pulse. As a result, data can be read on the parallel port

prior to reading the same data on the serial port, but data

cannot be read through the serial port prior to reading the

same data on the parallel port.

PARALLEL OUTPUT (AFTER A CONVERSION)

After conversion ‘n’ is completed and the output registers

have been updated, BUSY (pin 24) will go HIGH. Valid data

from conversion ‘n’ will be available on D7-D0 (pins 9-13 and

15-17). BUSY going high can be used to latch the data. Refer

to Table V and Figures 2 and 3 for timing constraints.

PARALLEL OUTPUT

To use the parallel output, tie EXT/INT (pin 8) HIGH and

DATACLK (pin 18) LOW. SDATA (pin 19) should be left

unconnected. The parallel output will be active when R/C (pin

22) is HIGH and CS (pin 23) is LOW. Any other combination

of CS and R/C will tri-state the parallel output. Valid conver-

sion data can be read in two 8-bit bytes on D7-D0 (pins 9-13

and 15-17). When BYTE (pin 21) is LOW, the 8 most signifi-

cant bits will be valid with the MSB on D7. When BYTE is

HIGH, the 8 least significant bits will be valid with the LSB on

D0. BYTE can be toggled to read both bytes within one

conversion cycle.

PARALLEL OUTPUT (DURING A CONVERSION)

After conversion ‘n’ has been initiated, valid data from con-

version ‘n – 1’ can be read and will be valid up to 12µs after

the start of conversion ‘n’. Do not attempt to read data

beyond 12µs after the start of conversion ‘n’ until BUSY (pin

24) goes HIGH; this may result in reading invalid data. Refer

to Table V and Figures 2 and 3 for timing constraints.

Upon initial power up, the parallel output will contain indeter-

minate data.

t₁

R/C

t₃

t₄

BUSY

t₅

t₆

t₇

t₈

Acquire

Convert

t₁₂

Acquire

MODE

t₁₂

t₁₁

t₁₀

Parallel

Data Bus

High Byte Valid

Previous High

Byte Valid

Previous Low

Byte Valid

High Byte

Valid

Low Byte

Valid

High Byte

Valid

Hi-Z

Not Valid

Hi-Z

t₉

t₂

t₁₂

t₉

t₁₂

BYTE

FIGURE 2. Conversion Timing with Parallel Output (CS and DATACLK tied LOW, EXT/INT tied HIGH).

t₂₁

R/C

t₁

t₃

t₄

BUSY

BYTE

t₂₁

DATA

BUS

Hi-Z State

High Byte Hi-Z State Low Byte

t₁₂t₉t₁₂

Hi-Z State

t₉

FIGURE 3. Using CS to Control Conversion and Read Timing with Parallel Outputs.

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INTERNAL DATA CLOCK

(During a Conversion)

SYMBOL

DESCRIPTION

MIN TYP MAX UNITS

t₁

Convert Pulse Width

Data Valid Delay after R/C LOW

BUSY Delay from

0.04

µs

(1)

t₂

To use the internal data clock, tie EXT/INT (pin 8) LOW. The

combination of R/C (pin 22) and CS (pin 23) LOW will initiate

conversion ‘n’ and activate the internal data clock (typically

900kHz clock rate). The ADS7807 will output 16 bits of valid

data, MSB first, from conversion ‘n-1’ on SDATA (pin 19),

synchronized to 16 clock pulses output on DATACLK (pin 18).

The data will be valid on both the rising and falling edges of the

internal data clock. The rising edge of BUSY (pin 24) can be

used to latch the data. After the 16th clock pulse, DATACLK will

remain LOW until the next conversion is initiated, while SDATA

will go to whatever logic level was input on TAG (pin 20) during

the first clock pulse. Refer to Table V and Figure 4.

(1)

t₃

Start of Conversion

µs

(1)

t₄

BUSY LOW

t₅

BUSY Delay after

End of Conversion

t₆

Aperture Delay

µs

(1)

t₇

Conversion Time

(1)

t₈

Acquisition Time

t₉

Bus Relinquish Time

BUSY Delay after Data Valid

Previous Data Valid

after Start of Conversion

Bus Access Time and BYTE Delay

Start of Conversion

t₁₀

(1)

t₁₁

(1)

t₁₂

(1)

t₁₃

2.4

µs

to DATACLK Delay

(1)

t₁₄

DATACLK Period

0.6 0.82 0.85

150 200

µs

EXTERNAL DATA CLOCK

(1)

t₁₅

Data Valid to DATACLK

HIGH Delay

To use an external data clock, tie EXT/INT (pin 8) HIGH. The

external data clock is not a conversion clock; it can only be

used as a data clock. To enable the output mode of the

ADS7807, CS (pin 23) must be LOW and R/C (pin 22) must

be HIGH. DATACLK must be HIGH for 20% to 70% of the

total data clock period; the clock rate can be between DC and

10MHz. Serial data from conversion ‘n’ can be output on

SDATA (pin 19) after conversion ‘n’ is completed or during

conversion ‘n + 1’.

(1)

t₁₆

Data Valid after DATACLK

LOW Delay

150 200

t₁₇

t₁₈

t₁₉

t₂₀

External DATACLK Period

External DATACLK LOW

External DATACLK HIGH

CS and R/C to External

DATACLK Setup Time

R/C to CS Setup Time

Valid Data after DATACLK HIGH

Throughput Time

100

t₂₁

µs

(1)

t₂₂

t₇+ t₈

An obvious way to simplify control of the converter is to tie

CS LOW and use R/C to initiate conversions.

DIP (NT) PACKAGE ONLY TIMING

t₂

t₃

Data Valid Delay after R/C LOW

µs

While this is perfectly acceptable, there is a possible problem

when using an external data clock. At an indeterminate point

from 12µs after the start of conversion ‘n’ until BUSY rises,

the internal logic will shift the results of conversion ‘n’ into the

output register. If CS is LOW, R/C HIGH, and the external

clock is HIGH at this point, data will be lost. So, with CS

LOW, either R/C and/or DATACLK must be LOW during this

period to avoid losing valid data.

BUSY Delay from

Start of Conversion

BUSY LOW

t₄

t₇

µs

Conversion Time

t₈

Acquisition Time

t₁₁

Previous Data Valid

after Start of Conversion

Bus Access Time and BYTE Delay

Start of Conversion

to DATACLK Delay

DATACLK Period

t₁₂

t₁₃

1.4

µs

t₁₄

t₁₅

1.1

µs

EXTERNAL DATA CLOCK

(After a Conversion)

Data Valid to DATACLK

HIGH Delay

t₁₆

t₂₂

Data Valid after DATACLK

LOW Delay

400 600

After conversion ‘n’ is completed and the output registers

have been updated, BUSY (pin 24) will go HIGH. With CS

LOW and R/C HIGH, valid data from conversion ‘n’ will be

output on SDATA (pin 19) synchronized to the external data

clock input on DATACLK (pin 18). The MSB will be valid on

the first falling edge and the second rising edge of the

external data clock. The LSB will be valid on the 16th falling

edge and 17th rising edge of the data clock. TAG (pin 20) will

input a bit of data for every external clock pulse. The first bit

input on TAG will be valid on SDATA on the 17th falling edge

and the 18th rising edge of DATACLK; the second input bit

will be valid on the 18th falling edge and the 19th rising edge,

etc. With a continuous data clock, TAG data will be output on

SDATA until the internal output registers are updated with

the results from the next conversion. Refer to Table V and

Figure 5.

Valid Data after DATACLK HIGH

NOTE: (1) See the bottom part of this table if using the DIP (NT) package.

TABLE V. Conversion and Data Timing. T_A= –40°C to +85°C.

SERIAL OUTPUT

Data can be clocked out with the internal data clock or an

external data clock. When using serial output, be careful with

the parallel outputs, D7-D0 (pins 9-13 and 15-17), as these

pins will come out of Hi-Z state whenever CS (pin 23) is LOW

and R/C (pin 22) is HIGH. The serial output can not be tri-

stated and is always active. Refer to the Applications

Information section for specific serial interfaces.

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t₇+ t₈

CS or R/C⁽¹⁾

DATACLK

t₁₄

t₁₃

t₁₆

t₁₅

MSB Valid

Bit 14 Valid

Bit 13 Valid

Bit 1 Valid

LSB Valid

MSB Valid

Bit 14 Valid

SDATA

BUSY

(Results from previous conversion.)

NOTE: (1) If controlling with CS, tie R/C LOW. Data bus pins will remain Hi-Z at all times.

If controlling with R/C, tie CS LOW. Data bus pins will be active when R/C is HIGH, and should be left unconnected.

FIGURE 4. Serial Data Timing Using Internal Data Clock (TAG tied LOW).

t₁₇

t₁₈

t₁₉

EXTERNAL

DATACLK

t₂₀

t₁

t₂₀

t₂₂

t₂₁

R/C

t₂₁

t₃

BUSY

Bit 15 (MSB)

Bit 14

Tag 2

Bit 1

Bit 0 (LSB)

Tag 16

Tag 0

Tag 1

SDATA

TAG

Tag 0

Tag 1

Tag 15

Tag 17

Tag 18

FIGURE 5. Conversion and Read Timing with External Clock (EXT/INT Tied HIGH) Read after Conversion.

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EXTERNAL DATA CLOCK

(During a Conversion)

INPUT RANGES

The ADS7807 offers three input ranges: standard ±10V and

0V-5V, and a 0V-4V range for complete, single-supply sys-

tems. See Figures 7a and 7b for the necessary circuit

connections for implementing each input range and optional

offset and gain adjust circuitry. Offset and full-scale error⁽¹⁾

specifications are tested with the fixed resistors, see Figure

7b. Adjustments for offset and gain are described in the

Calibration section of this data sheet.

After conversion ‘n’ has been initiated, valid data from con-

version ‘n – 1’ can be read and will be valid up to 12µs after

the start of conversion ‘n’. Do not attempt to clock out data

from 12µs after the start of conversion ‘n’ until BUSY (pin 24)

rises; this will result in data loss. NOTE: For the best possible

performance when using an external data clock, data should

not be clocked out during a conversion. The switching noise

of the asynchronous data clock can cause digital feedthrough

degrading the converter’s performance. Refer to Table V and

Figure 6.

The offset and gain are adjusted internally to allow external

trimming with a single supply. The external resistors compen-

sate for this adjustment and can be left out if the offset and

gain will be corrected in software (refer to the Calibration

section).

TAG FEATURE

TAG (pin 20) inputs serial data synchronized to the external

or internal data clock.

The input impedance, summarized in Table II, results from

the combination of the internal resistor network (see the front

page of this product data sheet) and the external resistors

used for each input range (see Figure 8). The input resistor

divider network provides inherent over-voltage protection to

at least ±5.5V for R2_INand ±12V for R1_IN.

When using an external data clock, the serial bit stream input

on TAG will follow the LSB output on SDATA until the internal

output register is updated with new conversion results. See

Table V and Figures 5 and 6.

The logic level input on TAG for the first rising edge of the

internal data clock will be valid on SDATA after all 16 bits of

valid data have been output.

Analog inputs above or below the expected range will yield

either positive full-scale or negative full-scale digital outputs,

respectively. Wrapping or folding over for analog inputs

outside the nominal range will not occur.

NOTE: (1) Full-scale error includes offset and gain errors measured at both

+FS and –FS.

t₁₇

t₁₈

t₁₉

EXTERNAL

DATACLK

t₂₀

t₂₂

t₂₁

t₂₀

R/C

t₁

t₁₁

BUSY

DATA

TAG

t₃

Bit 15 (MSB)

Bit 0 (LSB)

Tag 16

Tag 0

Tag 1

Tag 0

Tag 1

Tag 17

Tag 18

FIGURE 6. Conversion and Read Timing with External Clock (EXT/INT tied HIGH) Read During a Conversion.

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SOFTWARE CALIBRATION

CALIBRATION

To calibrate the offset and gain in software, no external

resistors are required. However, to get the data sheet speci-

fications for offset and gain, the resistors shown in Figure 7b

are necessary. See the No Calibration section for more

details on the external resistors. Refer to Table VIII for the

range of offset and gain errors with and without the external

resistors.

HARDWARE CALIBRATION

To calibrate the offset and gain of the ADS7807 in hardware,

install the resistors shown in Figure 7a. Table VI lists the

hardware trim ranges relative to the input for each input

range.

OFFSET ADJUST

RANGE (mV)

GAIN ADJUST

RANGE (mV)

INPUT RANGE

NO CALIBRATION

±10V

±15

±4

±60

±30

Figure 7b shows circuit connections. Note that the actual

voltage dropped across the external resistors is at least two

orders of magnitude lower than the voltage dropped across

the internal resistor divider network. This should be consid-

ered when choosing the accuracy and drift specifications of

the external resistors. In most applications, 1% metal-film

resistors will be sufficient.

0 to 5V

0 to 4V

±3

TABLE VI. Offset and Gain Adjust Ranges for Hardware

Calibration (see Figure 7a).

±10V

0V-5V

0V-4V

33.2kΩ

200Ω

R1_IN

V_IN

R1_IN

200Ω

33.2kΩ

AGND1

R2_IN

AGND1

R2_IN

V_IN

AGND1

R2_IN

V_IN

100Ω

50kΩ

100Ω

+5V

100Ω

+5V

CAP

33.2kΩ

CAP

+5V

2.2µF

CAP

50kΩ

2.2µF

50kΩ

REF

50kΩ

REF

50kΩ

1MΩ

REF

2.2µF

+5V

50kΩ

AGND2

1MΩ

2.2µF

AGND2

FIGURE 7a. Circuit Diagrams (With Hardware Trim).

±10V

0V-5V

0V-4V

33.2kΩ

200Ω

V_IN

R1_IN

200Ω

33.2kΩ

AGND1

R2_IN

AGND1

R2_IN

V_IN

AGND1

R2_IN

66.5kΩ

+5V

V_IN

100Ω

CAP

2.2µF

CAP

2.2µF

REF

2.2µF

AGND2

FIGURE 7b. Circuit Diagrams (Without Hardware Trim).

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The external resistors (see Figure 7b) may not be necessary

in some applications. These resistors provide compensation

for an internal adjustment of the offset and gain which allows

calibration with a single supply. Not using the external

resistors will result in offset and gain errors in addition to

those listed in the Electrical Characteristics section. Offset

refers to the equivalent voltage of the digital output when

converting with the input grounded. A positive gain error

occurs when the equivalent output voltage of the digital

output is larger than the analog input. Refer to Table VII for

nominal ranges of gain and offset errors with and without the

external resistors. Refer to Figure 8 for typical shifts in the

transfer functions which occur when the external resistors

are removed.

which reduces the input signal to a 0.3125V to 2.8125V input

range at the Capacitor Digital-to-Analog Converter (CDAC).

The internal resistors are laser trimmed to high relative accu-

racy to meet full scale specifications. The actual input imped-

ance of the internal resistor network looking into pin 1 or pin

3 however, is only accurate to ±20% due to process variations.

This should be taken into account when determining the

effects of removing the external resistors.

REFERENCE

The ADS7807 can operate with its internal 2.5V reference or

an external reference. By applying an external reference to

pin 5, the internal reference can be bypassed; REFD (pin 26)

tied HIGH will power-down the internal reference reducing

the overall power consumption of the ADS7807 by approxi-

mately 5mW.

To further analyze the effects of removing any combination of

the external resistors, consider Figure 9. The combination of

the external and the internal resistors form a voltage divider

OFFSET ERROR

GAIN ERROR

WITH RESISTORS

RANGE (mV)

WITHOUT RESISTORS

WITH RESISTORS

RANGE (% FS)

WITHOUT RESISTORS

INPUT

RANGE (V)

RANGE (mV)

TYP (mV)

RANGE (% FS)

TYP

±10

–10 ≤ BPZ ≤ 10

0 ≤ BPZ ≤ 35

–7.5

–6

–0.4 ≤ G ≤ 0.4

–0.3 ≤ G ≤ 0.5

+0.05

0.15 ≤ G⁽¹⁾≤ 0.15

–0.1 ≤ G⁽¹⁾≤ 0.2

0 to 5

0 to 4

–3 ≤ UPO ≤ 3

–12 ≤ UPO ≤ –3

–0.4 ≤ G ≤ 0.4

0.15 ≤ G⁽¹⁾≤ 0.15

–1.0 ≤ G ≤ 0.1

–0.55 ≤ G⁽¹⁾≤ –0.05

–0.2

–10.5 ≤ UPO ≤ –1.5

–0.4 ≤ G ≤ 0.4

–0.15 ≤ G⁽¹⁾≤ 0.15

–1.0 ≤ G ≤ 0.1

–0.55 ≤ G⁽¹⁾≤ –0.05

–0.2

NOTE: (1) High Grade.

TABLE VII. Range of Offset and Gain Errors With and Without External Resistors.

(a) Bipolar

(b) Unipolar

Digital Output

+Full-Scale

Analog Input

–Full-Scale

Analog Input

–Full-Scale

Typical Transfer Functions

With External Resistors

Typical Transfer Functions

Without External Resistors

FIGURE 8. Typical Transfer Functions With and Without External Resistors.

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200Ω

39.8kΩ

9.9kΩ

V_IN

CDAC

(0.3125V to 2.8125V)

20kΩ

40kΩ

66.5kΩ

+5V

100Ω

+2.5V

200Ω

39.8kΩ

9.9kΩ

CDAC

(0.3125V to 2.8125V)

33.2kΩ

100Ω

20kΩ

40kΩ

V_IN

+2.5V

200Ω

39.8kΩ

9.9kΩ

V_IN

CDAC

(0.3125V to 2.8125V)

33.2kΩ

100Ω

20kΩ

40kΩ

+2.5V

FIGURE 9. Circuit Diagrams Showing External and Internal Resistors.

The internal reference has approximately an 8ppm/°C drift

(typical) and accounts for approximately 20% of the full-scale

error (FSE = ±0.5% for low grade, ±0.25% for high grade).

REF

REF (pin 5) is an input for an external reference or the output

for the internal 2.5V reference. A 2.2µF tantalum capacitor

should be connected as close as possible to the REF pin

from ground. This capacitor and the output resistance of REF

create a low-pass filter to bandlimit noise on the reference.

Using a smaller value capacitor will introduce more noise to

the reference, degrading the SNR and SINAD. The REF pin

should not be used to drive external AC or DC loads, as

shown in Figure 10.

The ADS7807 also has an internal buffer for the reference

voltage. Figure 10 shows characteristic impedances at the

input and output of the buffer with all combinations of power-

down and reference down.

Z_CAP

CAP

(Pin 4)

CDAC

The range for the external reference is 2.3V to 2.7V and

determines the actual LSB size. Increasing the reference

voltage will increase the full-scale range and the LSB size of

the converter which can improve the SNR.

Buffer

Internal

REF

Reference

(Pin 5)

CAP

Z_REF

CAP (pin 4) is the output of the internal reference buffer. A

2.2µF tantalum capacitor should be placed as close as

possible to the CAP pin from ground to provide optimum

switching currents for the CDAC throughout the conversion

cycle. This capacitor also provides compensation for the

output of the buffer. Using a capacitor any smaller than 1µF

can cause the output buffer to oscillate and may not have

sufficient charge for the CDAC. Capacitor values larger than

2.2µF will have little affect on improving performance. See

Figures 10 and 11.

PWRD 0

REFD 0

PWRD 0

REFD 1

PWRD 1

REFD 0

PWRD 1

REFD 1

Z_CAP(Ω)

Z_REF(Ω)

200

100M

FIGURE 10. Characteristic Impedances of Internal Buffer.

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The output of the buffer is capable of driving up to 1mA of

current to a DC load. Using an external buffer will allow the

internal reference to be used for larger DC loads and AC

loads. Do not attempt to directly drive an AC load with the

output voltage on CAP. This will cause performance degra-

dation of the converter.

LAYOUT

POWER

For optimum performance, tie the analog and digital power

pins to the same +5V power supply and tie the analog and

digital grounds together. As noted in the electrical character-

istics, the ADS7807 uses 90% of its power for the analog

circuitry. The ADS7807 should be considered as an analog

component.

7000

6000

5000

4000

3000

2000

1000

The +5V power for the A/D converter should be separate

from the +5V used for the system’s digital logic. Connecting

V_DIG(pin 28) directly to a digital supply can reduce converter

performance due to switching noise from the digital logic. For

best performance, the +5V supply can be produced from

whatever analog supply is used for the rest of the analog

signal conditioning. If +12V or +15V supplies are present, a

simple +5V regulator can be used. Although it is not sug-

gested, if the digital supply must be used to power the

converter, be sure to properly filter the supply. Either using a

filtered digital supply or a regulated analog supply, both V_DIG

and V_ANAshould be tied to the same +5V source.

0.1

100

“CAP” Pin Value (µF)

FIGURE 11. Power-Down to Power-Up Time vs Capacitor

Value on CAP.

GROUNDING

Three ground pins are present on the ADS7807. D_GNDis the

digital supply ground. A_GND2is the analog supply ground.

REFERENCE

AND POWER-DOWN

A_GND1is the ground to which all analog signals internal to the

A/D converter are referenced. A_GND1is more susceptible to

current induced voltage drops and must have the path of

least resistance back to the power supply.

The ADS7807 has analog power-down and reference power

down capabilities via PWRD (pin 25) and REFD (pin 26),

respectively. PWRD and REFD HIGH will power-down all

analog circuitry maintaining data from the previous conver-

sion in the internal registers, provided that the data has not

already been shifted out through the serial port. Typical

power consumption in this mode is 50µW. Power recovery is

typically 1ms, using a 2.2µF capacitor connected to CAP.

Figure 11 shows power-down to power-up recovery time

relative to the capacitor value on CAP. With +5V applied to

All the ground pins of the A/D converter should be tied to an

analog ground plane, separated from the system’s digital

logic ground, to achieve optimum performance. Both analog

and digital ground planes should be tied to the “system”

ground as near to the power supplies as possible. This helps

to prevent dynamic digital ground currents from modulating

the analog ground through a common impedance to power

ground.

_DIG, the digital circuitry of the ADS7807 remains active at all

SIGNAL CONDITIONING

times, regardless of PWRD and REFD states.

The FET switches used for the sample hold on many CMOS

A/D converters release a significant amount of charge injec-

tion which can cause the driving op amp to oscillate. The

amount of charge injection due to the sampling FET switch

on the ADS7807 is approximately 5% to 10% of the amount

on similar A/D converters with the charge redistribution

Digital-to-Analog Converter (DAC) CDAC architecture. There

is also a resistive front end which attenuates any charge

which is released. The end result is a minimal requirement for

the drive capability on the signal conditioning preceding the

A/D converter. Any op amp sufficient for the signal in an

application will be sufficient to drive the ADS7807.

PWRD

PWRD HIGH will power-down all of the analog circuitry

except for the reference. Data from the previous conversion

will be maintained in the internal registers and can still be

read. With PWRD HIGH, a convert command yields mean-

ingless data.

REFD

REFD HIGH will power-down the internal 2.5V reference. All

other analog circuitry, including the reference buffer, will be

active. REFD should be HIGH when using an external

reference to minimize power consumption and the loading

effects on the external reference. See Figure 10 for the

characteristic impedance of the reference buffer’s input for

both REFD HIGH and LOW. The internal reference con-

sumes approximately 5mW.

The resistive front end of the ADS7807 also provides a speci-

fied ±25V over-voltage protection. In most cases, this elimi-

nates the need for external over-voltage protection circuitry.

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INTERMEDIATE LATCHES

The ADS7807 does have tri-state outputs for the parallel

port, but intermediate latches should be used if the bus will

be active during conversions. If the bus is not active during

conversion, the tri-state outputs can be used to isolate the

A/D converter from other peripherals on the same bus.

581

Intermediate latches are beneficial on any monolithic A/D

converter. The ADS7807 has an internal LSB size of 38µV.

Transients from fast switching signals on the parallel port,

even when the A/D converter is tri-stated, can be coupled

through the substrate to the analog circuitry causing degra-

dation of converter performance.

176

173

APPLICATIONS INFORMATION

TRANSITION NOISE

0001_H0002_H

Apply a DC input to the ADS7807 and initiate 1000 conver-

sions. The digital output of the converter will vary in output

codes due to the internal noise of the ADS7807. This is true

for all 16-bit SAR converters. The transition noise specifica-

tion found in the Electrical Characteristics section is a

statistical figure which represents the one sigma limit or rms

value of these output codes.

FFFD_HFFFE_HFFFF_H0000_H

0003_H

FIGURE 12. Histogram of 1000 Conversions with Input Grounded.

Using a histogram to plot the output codes, the distribution

should appear bell-shaped with the peak of the bell curve

representing the nominal output code for the input voltage

value. The ±1σ, ±2σ, and ±3σ distributions will represent

68.3%, 95.5%, and 99.7% of all codes. Multiplying TN by 6

will yield the ±3σ distribution or 99.7% of all codes. Statisti-

cally, up to 3 codes could fall outside the 5 code distribution

when executing 1000 conversions. The ADS7807 has a TN

of 0.8LSBs which yields 5 output codes for a ±3σ distribution.

Figures 12 and 13 show 1000 and 10000 conversion histo-

gram results.

5671

AVERAGING

2010

1681

176

The noise of the converter can be compensated by averag-

ing the digital codes. By averaging conversion results, tran-

sition noise will be reduced by a factor of 1/√Hz where n is

the number of averages. For example, averaging four con-

version results will reduce the TN by 1/2 to 0.4LSBs. Aver-

aging should only be used for input signals with frequencies

near DC.

438

182

0001_H0002_H

FFFD_HFFFE_HFFFF_H0000_H

0003_H

For AC signals, a digital filter can be used to low-pass filter

and decimate the output codes. This works in a similar

manner to averaging: for every decimation by 2, the signal-

to-noise ratio will improve 3dB.

FIGURE 13. Histogram of 10000 Conversions with Input Grounded.

ADS7807

SBAS022D

www.ti.com

QSPI™ INTERFACING

QSPI™

ADS7807

+5V

Figure 14 shows a simple interface between the ADS7807

and any QSPI equipped microcontroller. This interface as-

sumes that the convert pulse does not originate from the

microcontroller and that the ADS7807 is the only serial

peripheral.

R/C

EXT/INT

PCS0

PCS1

SCK

DATACLK

D7 (MSB)

MISO

Convert Pulse

BYTE

CPOL = 0

CPHA = 0

QSPI™

ADS7807

R/C

QSPI is a registered trademark of Motorola.

PCS0/SS

BUSY

FIGURE 15. QSPI Interface to the ADS7807. Processor

Initiates Conversions.

MOSI

SCK

SDATA

DATACLK

For both transfers, the DT register (delay after transfer) is

used to cause a 19µs delay. The interface is also set up to

wrap to the beginning of the queue. In this manner, the QSPI

is a state machine which generates the appropriate timing for

the ADS7807. This timing is thus locked to the crystal-based

timing of the microcontroller and not interrupt driven. So, this

interface is appropriate for both AC and DC measurements.

EXT/INT

BYTE

CPOL = 0 (Inactive State is LOW)

CPHA = 1 (Data valid on falling edge)

QSPI port is in slave mode.

QSPI is a registered trademark of Motorola.

For the fastest conversion rate, the baud rate should be set

to 2 (4.19MHz SCK), DT set to 10, the first serial transfer set

to 8 bits, the second set to 16 bits, and DSCK disabled (in the

command control byte). This will allow for a 23kHz maximum

conversion rate. For slower rates, DT should be increased.

Do not slow SCK as this may increase the chance of

affecting the conversion results or accidently initiating a

second conversion during the first 8-bit transfer.

FIGURE 14. QSPI Interface to the ADS7807.

Before enabling the QSPI interface, the microcontroller must

be configured to monitor the slave select line. When a

transition from LOW to HIGH occurs on Slave Select (SS

from BUSY (indicating the end of the current conversion), the

port can be enabled. If this is not done, the microcontroller

and the A/D converter may be “out-of-sync”.

)

In addition, CPOL and CPHA should be set to zero (SCK

normally LOW and data captured on the rising edge). The

command control byte for the 8-bit transfer should be set to

20_Hand for the 16-bit transfer to 61_H.

Figure 15 shows another interface between the ADS7807

and a QSPI equipped microcontroller which allows the micro-

controller to give the convert pulses while also allowing

multiple peripherals to be connected to the serial bus. This

interface and the following discussion assume a master clock

for the QSPI interface of 16.78MHz. Notice that the serial

data input of the microcontroller is tied to the MSB (D7) of the

ADS7807 instead of the serial output (SDATA). Using D7

instead of the serial port offers tri-state capability which

allows other peripherals to be connected to the MISO pin.

When communication is desired with those peripherals, PCS0

and PCS1 should be left HIGH; that will keep D7 tri-stated.

SPI™ INTERFACE

The SPI interface is generally only capable of 8-bit data

transfers. For some microcontrollers with SPI interfaces, it

might be possible to receive data in a similar manner as

shown for the QSPI interface in Figure 14. The microcontroller

will need to fetch the 8 most significant bits before the

contents are overwritten by the least significant bits.

A modified version of the QSPI interface shown in Figure 15

might be possible. For most microcontrollers with SPI inter-

face, the automatic generation of the start-of-conversion

pulse will be impossible and will have to be done with

software. This will limit the interface to ‘DC’ applications due

to the insufficient jitter performance of the convert pulse

itself.

In this configuration, the QSPI interface is actually set to do

two different serial transfers. The first, an 8-bit transfer, causes

PCS0 (R/C) and PCS1 (CS) to go LOW, starting a conver-

sion. The second, a 16-bit transfer, causes only PCS1 (CS) to

go LOW. This is when the valid data will be transferred.

QSPI is a registered trademark of Motorola.

SPI is a registered trademark of Motorola.

ADS7807

SBAS022D

www.ti.com

DSP56000 INTERFACING

The DSP56000 serial interface has SPI compatibility mode

with some enhancements. Figure 16 shows an interface

between the ADS7807 and the DSP56000 which is very

similar to the QSPI interface seen in Figure 14. As mentioned

in the QSPI section, the DSP56000 must be programmed to

enable the interface when a LOW to HIGH transition on SC1

is observed (BUSY going HIGH at the end of conversion).

Convert Pulse

DSP56000

ADS7807

R/C

The DSP56000 can also provide the convert pulse by includ-

ing a monostable multi-vibrator, as seen in Figure 17. The

receive and transmit sections of the interface are decoupled

(asynchronous mode) and the transmit section is set to

generate a word length frame sync every other transmit

frame (frame rate divider set to 2). The prescale modulus

should be set to 3.

SC1

BUSY

SRD

SCO

SDATA

DATACLK

EXT/INT

BYTE

The monostable multi-vibrator in this circuit will provide

varying pulse widths for the convert pulse. The pulse width

will be determined by the external R and C values used with

the multi-vibrator. The 74HCT123N data sheet shows that

the pulse width is (0.7) RC. Choosing a pulse width as close

to the minimum value specified in this data sheet will offer the

best performance. See the Starting A Conversion section

of this data sheet for details on the conversion pulse width.

SYN = 0 (Asychronous)

GCK = 1 (Gated clock)

SCD1 = 0 (SC1 is an input)

SHFD = 0 (Shift MSB first)

WL1 = 1 WL0 = 0 (Word length = 16 bits)

The maximum conversion rate for a 20.48MHz DSP56000 is

exactly 40kHz. Note that this will not be the case for the

ADS7806. See the ADS7806 data sheet (SBAS021B) for

more information.

FIGURE 16. DSP56000 Interface to the ADS7807.

74HCT123N

+5V

DSP56000

R_EXT1

ADS7807

SC2

CLR1

C_EXT1

R/C

SC0

SRD

DATACLK

SDATA

EXT/INT

BYTE

SYN = 0 (Asychronous)

GCK = 1 (Gated clock)

SCD2 = 1 (SC2 is an output)

SHFD = 0 (Shift MSB first)

WL1 = 1 WL0 = 0 (Word length = 16 bits)

FIGURE 17. DSP56000 Interface to the ADS7807. Processor Initiates Conversions.

ADS7807

SBAS022D

www.ti.com

Revision History

DATE

REVISION PAGE

SECTION

Electrical Characteristics Changed Analog Input Capacitance from 35pF to 45pF.

Table V Updated Table V and added PDIP package timing; page layout reflowed.

DESCRIPTION

11/06

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

ADS7807

SBAS022D

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

14-Oct-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

ADS7807U

ADS7807U/1K

ADS7807UB

ACTIVE

SOIC

RoHS & Green

NIPDAU-DCC

Level-3-260C-168 HR

-40 to 85

ADS7807U

Samples

1000 RoHS & Green

NIPDAU-DCC

ADS7807U

RoHS & Green

ADS7807U

ADS7807UE4

ACTIVE

SOIC

NIPDAU-DCC

Level-3-260C-168 HR

-40 to 85

ADS7807U

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

14-Oct-2022

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADS7807U/1K

SOIC

1000

330.0

32.4

11.35 18.67

3.1

16.0

32.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC DW 28

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 66.0

ADS7807U/1K

1000

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TUBE

T - Tube

height

L - Tube length

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

ADS7807U

ADS7807UB

ADS7807UE4

SOIC

506.98

12.7

4826

6.6

Pack Materials-Page 3

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ADS7807 [TI]

相关型号：

ADS7807P

ADS7807PB

ADS7807PBG4

ADS7807PG4

ADS7807U

ADS7807U

ADS7807U/1K

ADS7807U/1K

ADS7807U/1KE4

ADS7807U/1KG4

ADS7807UB

ADS7807UB