ADS7812PB [TI]
低功耗串行 12 位采样模数转换器 | N | 16;
| 型号： | ADS7812PB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 低功耗串行 12 位采样模数转换器 | N | 16 光电二极管 转换器 模数转换器 |
| 文件： | 总28页 (文件大小：1242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS7812
ADS7812
A
D
S
7
8
1
2
SBAS042A – MARCH 1997 – REVISED SEPTEMBER 2003
Low-Power, Serial 12-Bit Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
ꢀ 20µs max CONVERSION TIME
ꢀ SINGLE +5V SUPPLY OPERATION
ꢀ PIN-COMPATIBLE WITH 16-BIT ADS7813
ꢀ EASY-TO-USE SERIAL INTERFACE
ꢀ 0.3" DIP-16 AND SO-16
The ADS7812 is a low-power, single +5V supply, 12-bit
sampling analog-to-digital converter. It contains a complete
12-bit capacitor-based SAR A/D with a sample/hold, clock,
reference, and serial data interface.
The converter can be configured for a variety of input ranges
including ±10V, ±5V, 0V to 10V, and 0.5V to 4.5V. A high
impedance 0.3V to 2.8V input range is also available (input
impedance > 10MΩ). For most input ranges, the input
voltage can swing to +16.5V or –16.5V without damage to
the converter.
ꢀ ±0.5LSB max INL AND DNL
ꢀ 72dB min SINAD
ꢀ USES INTERNAL OR EXTERNAL
REFERENCE
A flexible SPI compatible serial interface allows data to be
synchronized to an internal or external clock. The ADS7812
is specified at a 40kHz sampling rate over the –40°C to
+85°C temperature range. It is available in a 0.3" DIP-16 or
an SO-16 package.
ꢀ MULTIPLE INPUT RANGES
ꢀ 35mW max POWER DISSIPATION
ꢀ NO MISSING CODES
ꢀ 50µW POWER DOWN MODE
APPLICATIONS
ꢀ DATA ACQUISITION SYSTEMS
ꢀ INDUSTRIAL CONTROL
ꢀ TEST EQUIPMENT
BUSY
PWRD
CONV
CS
Successive Approximation Register and Control Logic
Clock
ꢀ DIGITAL SIGNAL PROCESSING
40kΩ(1)
CDAC
R1IN
8kΩ(1)
EXT/INT
DATACLK
DATA
R2IN
Serial
20kΩ(1)
Data
Out
Comparator
R3IN
BUF
CAP
Internal
+2.5V Ref
Buffer
4kΩ(1)
NOTE: (1) Actual value may vary ±30%.
REF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1997-2003, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
Analog Inputs: R1IN ......................................................................... ±16.5V
R2IN ................................................ GND – 0.3V to +16.5V
R3IN ......................................................................... ±16.5V
REF ............................................ GND – 0.3V to VS + 0.3V
CAP ............................................... Indefinite Short to GND
Momentary Short to VS
VS ........................................................................................................... 7V
Digital Inputs ...................................................... GND – 0.3V to VS + 0.3V
Maximum Junction Temperature ................................................... +165°C
Internal Power Dissipation ............................................................. 825mW
Lead Temperature (soldering, 10s) ............................................... +300°C
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
PACKAGE/ORDERING INFORMATION
MINIMUM
MAXIMUM
INTEGRAL
SPECIFIED
NO MISSING
SIGNAL-TO-
(NOISE +
SPECIFIED
LINEARITY
ERROR (LSB)
CODE LEVEL DISTORTION)
PACKAGE
TEMPERATURE PACKAGE
RANGE MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
(LSB)
RATIO (DB) PACKAGE-LEAD DESIGNATOR(1)
ADS7812P
±1
12
12
70
72
Dip-16
N
–40°C to +85°C ADS7812P
ADS7812PB
–40°C to +85°C ADS7812U
ADS7812P
Tubes, 25
Tubes, 25
ADS7812PB
±0.5
"
"
DW
"
"
ADS7812PB
ADS7812U
"
±1
"
12
"
70
"
SO-16
"
ADS7812U
ADS7812U/1K Tape and Reel, 1000
Tubes, 48
"
"
ADS7812UB
"
±0.5
12
"
72
"
SO-16
"
DW
"
–40°C to +85°C ADS7812UB
ADS7812UB Tubes, 48
"
"
"
ADS7812UB/1K Tape and Reel, 1000
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
SPECIFICATIONS
At TA = –40°C to +85°C, fS = 40kHz, VS = +5V ±5%, using internal reference, unless otherwise specified.
ADS7812P, U
ADS7812PB, UB
PARAMETER
RESOLUTION
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
12
ꢀ
Bits
ANALOG INPUT
Voltage Range
Impedance
See Table I
See Table I
35
ꢀ
ꢀ
ꢀ
Capacitance
pF
THROUGHPUT SPEED
Conversion Time
Complete Cycle
20
25
ꢀ
ꢀ
µs
µs
Acquire and Convert
Throughput Rate
40
ꢀ
kHz
DC ACCURACY
Integral Linearity Error
Differential Linearity Error
No Missing Codes
Transition Noise(2)
Full Scale Error(3)
Full Scale Error Drift
Full Scale Error(3)
Full Scale Error Drift
Bipolar Zero Error
Bipolar Zero Error Drift
Unipolar Zero Error
Unipolar Zero Error Drift
Recovery Time to Rated Accuracy
from Power Down(4)
Power Supply Sensitivity
0.1
0.1
Specified
0.05
±1
±1
ꢀ
ꢀ
ꢀ
ꢀ
±0.5
±0.5
LSB(1)
LSB
LSB
%
ppm/°C
%
ppm/°C
mV
ppm/°C
mV
±0.5
±0.5
±10
±6
±0.25
±0.25
ꢀ
±14
±5
ꢀ
ꢀ
ꢀ
Ext. 2.5000V Ref
Ext. 2.5000V Ref
Bipolar Ranges
Bipolar Ranges
±3
Unipolar Ranges
Unipolar Ranges
1.0µF Capacitor to CAP
ꢀ
±3
300
ꢀ
ꢀ
ppm/°C
µs
+4.75V < (VS = +5V) < +5.25
±0.75
ꢀ
ꢀ
LSB
AC ACCURACY
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise+Distortion)
Signal-to-Noise
Useable Bandwidth(6)
Full Power –3dB Bandwidth
fIN = 1kHz
fIN = 1kHz
80
98
–96
74
74
130
600
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
dB(5)
dB
dB
dB
kHz
kHz
–80
f
f
IN = 1kHz
IN = 1kHz
70
70
72
72
ADS7812
2
SBAS042A
www.ti.com
SPECIFICATIONS (Cont.)
At TA = –40°C to +85°C, fS = 40kHz, VS = +5V ±5%, using internal reference, unless otherwise specified.
ADS7812P, U
ADS7812PB, UB
TYP
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
Overvoltage Recovery(7)
40
20
5
ꢀ
ꢀ
ꢀ
ꢀ
ns
ps
µs
ns
FS Step
750
REFERENCE
Internal Reference Voltage
Internal Reference Source Current
Internal Reference Drift
External Reference Voltage Range
External Reference Current Drain
2.48
2.3
2.5
100
8
2.52
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
µA
ppm/°C
V
2.5
2.7
100
ꢀ
ꢀ
V
REF = +2.5V
µA
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
–0.3
+2.0
+0.8
VS +0.3V
±10
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
µA
µA
(8)
IIH
±10
DIGITAL OUTPUTS
Data Format
Data Coding
VOL
Serial
Binary Two’s Complement
ISINK = 1.6mA
ISOURCE = 500µA
High-Z State,
+0.4
ꢀ
ꢀ
V
V
µA
VOH
+4
ꢀ
Leakage Current
±1
V
OUT = 0V to VS
High-Z State
Output Capacitance
15
15
pF
POWER SUPPLY
VS
Power Dissipation
+4.75
+5
+5.25
35
ꢀ
ꢀ
ꢀ
ꢀ
V
mW
fS = 40kHz
TEMPERATURE RANGE
Specified Performance
Derated Performance
–40
–55
+85
+125
ꢀ
ꢀ
ꢀ
ꢀ
°C
°C
ꢀ Same specification as grade to the left.
NOTES: (1) LSB means Least Significant Bit. For the ±10V input range, one LSB is 4.88mV. (2) Typical rms noise at worst case transitions and temperatures.
(3) Full scale error is the worst case of –Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage
(not divided by the full-scale range) and includes the effect of offset error. (4) After the ADS7812 is initially powered on and fully settles, this is the time delay after
it is brought out of Power Down Mode until all internal settling occurs and the analog input is acquired to rated accuracy, and normal conversions can begin again.
(5) All specifications in dB are referred to a full-scale input. (6) Useable Bandwidth defined as Full-Scale input frequency at which Signal-to-(Noise+Distortion)
degrades to 60dB, or 10 bits of accuracy. (7) Recovers to specified performance after 2 x FS input overvoltage. (8) The minimum VIH level for the DATACLK signal
is 3V.
ADS7812
SBAS042A
3
www.ti.com
PIN CONFIGURATION
PIN #
NAME
DESCRIPTION
1
2
3
4
5
6
7
R1IN
GND
R2IN
R3IN
BUF
CAP
REF
Analog Input. See Tables I and IV.
Ground
Analog Input. See Tables I and IV.
Analog Input. See Tables I and IV.
Reference Buffer Output. Connect to R1IN, R2IN, or R3IN, as needed.
Reference Buffer Compensation Node. Decouple to ground with a 1µF tantalum capacitor in parallel with a 0.01µF ceramic capacitor.
Reference Input/Output. Outputs internal +2.5V reference via a series 4kΩ resistor. Decouple this voltage with a 1µF to 2.2µF
tantalum capacitor to ground. If an external reference voltage is applied to this pin, it will override the internal reference.
8
9
GND
Ground
DATACLK
Data Clock Pin. With EXT/INT LOW, this pin is an output and provides the synchronous clock for the serial data. The output
is tri-stated when CS is HIGH. With EXT/INT HIGH, this pin is an input and the serial data clock must be provided externally.
10
11
12
DATA
EXT/INT
CONV
Serial Data Output. The serial data is always the result of the last completed conversion and is synchronized to DATACLK.
If DATACLK is from the internal clock (EXT/INT LOW), the serial data is valid on both the rising and falling edges of DATACLK.
DATA is tri-stated when CS is HIGH.
External or Internal DATACLK Pin. Selects the source of the synchronous clock for serial data. If HIGH, the clock must be
provided externally. If LOW, the clock is derived from the internal conversion clock. Note that the clock used to time the
conversion is always internal regardless of the status of EXT/INT.
Convert Input. A falling edge on this input puts the internal sample/hold into the hold state and starts a conversion regardless
of the state of CS. If a conversion is already in progress, the falling edge is ignored. If EXT/INT is LOW, data from the previous
conversion will be serially transmitted during the current conversion.
13
14
15
CS
Chip Select. This input tri-states all outputs when HIGH and enables all outputs when LOW. This includes DATA, BUSY, and
DATACLK (when EXT/INT is LOW). Note that a falling edge on CONV will initiate a conversion even when CS is HIGH.
BUSY
PWRD
Busy Output. When a conversion is started, BUSY goes LOW and remains LOW throughout the conversion. If EXT/INT is
LOW, data is serially transmitted while BUSY is LOW. BUSY is tri-stated when CS is HIGH.
Power Down Input. When HIGH, the majority of the ADS7812 is placed in a low power mode and power consumption is
significantly reduced. CONV must be taken LOW prior to PWRD going LOW in order to achieve the lowest power
consumption. The time required for the ADS7812 to return to normal operation after power down depends on a number of
factors. Consult the Power Down section for more information.
16
VS
+5V Supply Input. For best performance, decouple to ground with a 0.1µF ceramic capacitor in parallel with a 10µF tantalum
capacitor.
PIN CONFIGURATION
ANALOG
INPUT
RANGE (V)
CONNECT
R1IN
CONNECT
R2IN
CONNECT
R3IN
INPUT
IMPEDANCE
(kΩ)
Top View
DIP, SOIC
TO
TO
TO
±10V
VIN
BUF
GND
45.7
0.3125V to
2.8125V
R1IN
GND
R2IN
R3IN
BUF
CAP
REF
GND
1
2
3
4
5
6
7
8
16 VS
VIN
GND
BUF
BUF
VIN
VIN
BUF
GND
VIN
VIN
VIN
> 10,000
26.7
15 PWRD
14 BUSY
13 CS
±5V
0V to 10V
0V to 4V
±3.33V
VIN
26.7
GND
VIN
21.3
ADS7812
BUF
21.3
12 CONV
11 EXT/INT
10 DATA
0.5V to
4.5V
GND
VIN
GND
21.3
TABLE I. ADS7812 Input Ranges.
9
DATACLK
ADS7812
4
SBAS042A
www.ti.com
TYPICAL PERFORMANCE CURVES
At TA = +25°C, fS = 40kHz, VS = +5V, ±10V input range, using internal reference, unless otherwise noted.
FREQUENCY SPECTRUM
(8192 Point FFT; fIN = 9.8kHz, 0dB)
FREQUENCY SPECTRUM
(8192 Point FFT; fIN = 980Hz, 0dB)
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
5
10
15
20
0
5
10
15
20
Frequency (kHz)
Frequency (kHz)
SNR AND SINAD vs TEMPERATURE
(fIN = 1kHz, 0dB)
SFDR AND THD vs TEMPERATURE
(fIN = 1kHz, 0dB)
77
76
75
74
73
72
71
100
99
98
97
96
95
94
–100
–99
–98
–97
–96
–95
–94
SFDR
SNR and SINAD
THD
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
SIGNAL-TO-(NOISE + DISTORTION)
vs INPUT FREQUENCY (fIN = 0dB)
INTERNAL REFERENCE VOLTAGE
vs TEMPERATURE
74.0
73.8
73.6
73.4
73.2
73.0
2.515
2.510
2.505
2.500
2.495
2.490
2.485
100
1k
10k
20k
–50
–25
0
25
50
75
100
Input Signal Frequency (Hz)
Temperature (°C)
ADS7812
SBAS042A
5
www.ti.com
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, fS = 40kHz, VS = +5V, ±10V input range, using internal reference, unless otherwise noted.
ILE AND DLE AT –40°C
ILE AND DLE AT +25°C
0.2
0.1
0.2
0.1
0
0
–0.1
–0.2
–0.1
–0.2
0.2
0.1
0.2
0.1
0
0
–0.1
–0.1
–0.2
–0.2
800h
C00h
000h
400h
7FFh
800h
C00h
000h
400h
7FFh
Hex BTC Code
Hex BTC Code
POWER SUPPLY RIPPLE SENSITIVITY
ILE/DLE DEGRADATION PER LSB OF P-P RIPPLE
ILE AND DLE AT +85°C
0.2
0.1
1
10–1
0
–0.1
–0.2
10–2
10–3
10–4
10–5
ILE
0.2
0.1
0
DLE
–0.1
101
102
103
104
105
106
107
–0.2
Power Supply Ripple Frequency (Hz)
800h
C00h
000h
400h
7FFh
Hex BTC Code
ADS7812
6
SBAS042A
www.ti.com
EXTERNAL DATACLK
BASIC OPERATION
Figure 1b shows a basic circuit to operate the ADS7812 with
a ±10V input range. To begin a conversion, a falling edge
must be provided to the CONV input. BUSY will go LOW
indicating that a conversion has started and will stay LOW
until the conversion is complete. Just prior to BUSY rising
near the end of the conversion, the internal working register
holding the conversion result will be transferred to the
internal shift register.
INTERNAL DATACLK
Figure 1a shows a basic circuit to operate the ADS7812 with
a ±10V input range. To begin a conversion and serial
transmission of the results from the previous conversion, a
falling edge must be provided to the CONV input. BUSY
will go LOW indicating that a conversion has started and
will stay LOW until the conversion is complete. During the
conversion, the results of the previous conversion will be
transmitted via DATA while DATACLK provides the syn-
chronous clock for the serial data. The data format is 12-bit,
Binary Two’s Complement, and MSB first. Each data bit is
valid on both the rising and falling edge of DATACLK.
BUSY is LOW during the entire serial transmission and can
be used as a frame synchronization signal.
The internal shift register is clocked via the DATACLK
input. The recommended method of reading the conversion
result is to provide the serial clock after the conversion has
completed. See External DATACLK under the Reading
Data section of this data sheet for more information.
C1
C2
ADS7812
0.1µF 10µF
+5V
±10V
1
2
3
4
5
6
7
8
R1IN
GND
R2IN
R3IN
BUF
CAP
REF
GND
VS 16
PWRD 15
BUSY 14
CS 13
+
Frame Sync (optional)
Convert Pulse
CONV 12
EXT/INT 11
DATA 10
+
C3
C4
0.01µF
1µF
+
C5
1µF
40ns min
DATACLK
9
FIGURE 1a. Basic Operation, ±10V Input Range, Internal DATACLK.
C1
C2
ADS7812
0.1µF 10µF
+5V
±10V
1
2
3
4
5
6
7
8
R1IN
GND
R2IN
R3IN
BUF
CAP
REF
GND
VS 16
PWRD 15
BUSY 14
CS 13
+
Interrupt (optional)
Chip Select (optional(1)
)
Convert Pulse
CONV 12
EXT/INT 11
DATA 10
+
C3
C4
0.01µF
+5V
1µF
+
40ns min
C5
1µF
External Clock
DATACLK
9
NOTE: (1) Tie CS to GND if the outputs will always be active.
FIGURE 1b. Basic Operation, ±10V Input Range, External DATACLK.
ADS7812
SBAS042A
7
www.ti.com
SYMBOL
DESCRIPTION
MIN TYP MAX UNITS
STARTING A CONVERSION
t1
t2
Conversion Plus Acquisition Time
25
8
µs
µs
If a conversion is not currently in progress, a falling edge on
the CONV input places the sample and hold into the hold
mode and begins a conversion, as shown in Figure 2 and
with the timing given in Table II. During the conversion, the
CONV input is ignored. Starting a conversion does not
depend on the state of CS. A conversion can be started once
every 25µs (40kHz maximum conversion rate). There is no
minimum conversion rate.
CONV LOW to All Digital
Inputs Stable
t3
t4
CONV LOW to Initiate a Conversion 40
ns
ns
BUSY Rising to Any Digital
Input Active
0
t5
CONV HIGH Prior to Start
of Conversion
2
µs
t6
t7
BUSY LOW
CONV LOW to BUSY LOW
Aperture Delay
15
85
40
14
1.1
20
µs
ns
ns
µs
µs
120
Even though the CONV input is ignored while a conversion
is in progress, this input should be held static during the
conversion period. Transitions on this digital input can
easily couple into sensitive analog portions of the converter,
adversely affecting the conversion results (see the Sensitiv-
ity to External Digital Signals section of this data sheet for
more information).
t8
t9
Conversion Time
20
2
t10
Conversion Complete to
BUSY Rising
t11
t12
Acquisition Time
5
µs
µs
CONV LOW to Rising Edge
of First DATACLK
1.4
t13
t14
t15
t16
Internal DATACLK HIGH
Internal DATACLK LOW
Internal DATACLK Period
250 350 500
ns
ns
µs
ns
Ideally, the CONV input should go LOW and remain LOW
throughout the conversion. It should return HIGH sometime
after BUSY goes HIGH. In addition, it should be HIGH
prior to the start of the next conversion for a minimum time
period given by t5. This will ensure that the digital transition
on the CONV input will not affect the signal that is acquired
for the next conversion.
600 760 875
1.1
20
DATA Valid to Internal
DATACLK Rising
t17
t18
t19
t20
Internal DATACLK Falling
to DATA Not Valid
400
800
15
ns
ns
ns
ns
Falling Edge of Last DATACLK
to BUSY Rising
An acceptable alternative is to return the CONV input HIGH
as soon as possible after the start of the conversion. For
example, a negative going pulse 100ns wide would make a
good CONV input signal. It is strongly recommended that
from time t2 after the start of a conversion until BUSY rises,
the CONV input should be held static (either HIGH or
LOW). During this time, the converter is more sensitive to
external noise.
External DATACLK Rising
to DATA Not Valid
External DATACLK Rising
to DATA Valid
55
85
t21
t22
t23
t24
External DATACLK HIGH
External DATACLK LOW
External DATACLK Period
50
50
ns
ns
ns
ns
100
120
CONV LOW to External
DATACLK Active
t25
External DATACLK LOW
2
µs
or CS HIGH to BUSY Rising
t26
t27
CS LOW to Digital Outputs Enabled
85
ns
ns
CS HIGH to Digital Outputs Disabled 85
TABLE II. ADS7812 Timing. TA = –40°C to +85°C.
t1
t2
t3
t4
t5
CONV
t6
t7
BUSY
t8
t10
t9
t11
MODE
Acquire
Convert
Acquire
Convert
FIGURE 2. Basic Conversion Timing.
ADS7812
8
SBAS042A
www.ti.com
DIGITAL OUTPUT
DESCRIPTION
ANALOG INPUT
BINARY TWO’S COMPLEMENT
Full-Scale Range
±10V
0.5V to 4.5V
Least Significant Bit (LSB)
4.88mV
0.98mV
BINARY CODE
HEX CODE
+Full Scale –1LSB
Midscale
9.99512V
0V
4.49902V
2.5V
0111 1111 1111
0000 0000 0000
1111 1111 1111
1000 0000 0000
7FF
000
FFF
800
Midscale –1LSB
–Full Scale
–4.88mV
–10V
2.49902 V
0.5V
TABLE III. Ideal Input Voltage and Corresponding Digital Output for Two Common Input Ranges.
Converter Core
REF
CDAC
CONV
Clock
Control Logic
BUSY
Each flip-flop in the
working register is
latched as the
conversion proceeds
Working Register
D Q
D
Q
D
Q
D
Q
D
Q
• • •
W0
W1
W2
W10
W11
Update of the shift
register occurs just prior
to BUSY Rising(1)
Shift Register
DATA
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
EXT/INT
S0
S1
S2
S10
S11
SOUT
Delay
DATACLK
CS
NOTE: (1) If EXT/INT is HIGH (external clock), DATACLK is HIGH, and CS is LOW
during this time, the shift register will not be updated and the conversion result will be lost.
FIGURE 3. Block Diagram of the ADS7812’s Digital Inputs and Outputs.
READING DATA
The ADS7812’s digital output is in Binary Two’s Comple-
ment (BTC) format. Table III shows the relationship be-
tween the digital output word and the analog input voltage
under ideal conditions.
CONV
t25
t6 – t25
Figure 3 shows the relationship between the various digital
inputs, digital outputs, and internal logic of the ADS7812.
Figure 4 shows when the internal shift register of the
ADS7812 is updated and how this relates to a single conver-
sion cycle. Together, these two figures point out a very
important aspect of the ADS7812: the conversion result is
not available until after the conversion is complete. The
implications of this are discussed in the following sections.
BUSY
NOTE: Update of the internal shift register occurs in the
shaded region. If EXT/INT is HIGH, then DATACLK
must be LOW or CS must be HIGH during this time.
FIGURE 4. Timing of the Shift Register Update.
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INTERNAL DATACLK
EXTERNAL DATACLK
With EXT/INT tied LOW, the result from conversion ‘n’ is
serially transmitted during conversion ‘n+1’, as shown in
Figure 5 and with the timing given in Table II. Serial
transmission of data occurs only during a conversion. When
a transmission is not in progress, DATA and DATACLK are
LOW.
With EXT/INT tied HIGH, the result from conversion ‘n’ is
clocked out after the conversion has completed, during the
next conversion (‘n+1’), or a combination of these two.
Figure 6 shows the case of reading the conversion result
after the conversion is complete. Figure 7 describes reading
the result during the next conversion. Figure 8 combines the
important aspects of Figures 6 and 7 as to reading part of the
result after the conversion is complete and the remainder
during the next conversion.
During the conversion, the results of the previous conver-
sion will be transmitted via DATA, while DATACLK
provides the synchronous clock for the serial data. The data
format is 12-bit, Binary Two’s Complement, and MSB first.
Each data bit is valid on both the rising and falling edges of
DATACLK. BUSY is LOW during the entire serial trans-
mission and can be used as a frame synchronization signal.
The serial transmission of the conversion result is initiated
by a rising edge on DATACLK. The data format is 12-bit,
Binary Two’s Complement, and MSB first. Each data bit is
valid on the falling edge of DATACLK. In some cases, it
t1
CONV
BUSY
t13
t12
t15
t18
DATACLK
DATA
1
2
3
10
11
12
1
t16
t14
t17
Bit 10
MSB
Bit 2
Bit 1
LSB
Bit 9
MSB
FIGURE 5. Serial Data Timing, Internal Clock (EXT/INT and CS LOW).
t1
t5
CONV
BUSY
t21
t4
t23
DATACLK
DATA
1
2
3
4
10
11
12
t19
t20
t22
LSB
MSB
Bit 10
Bit 9
Bit 2
Bit 1
FIGURE 6. Serial Data Timing, External Clock, Clocking After the Conversion Completes (EXT/INT HIGH, CS LOW).
ADS7812
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External DATACLK Active After the Conversion
might be possible to use the rising edge of the DATACLK
signal. However, one extra clock period (not shown in
Figures 6, 7, and 8) is needed for the final bit.
The preferred method of obtaining the conversion result is to
provide the DATACLK signal after the conversion has been
completed and before the next conversion starts—as shown
in Figure 6. Note that the DATACLK signal should be static
before the start of the next conversion. If this is not ob-
served, the DATACLK signal could affect the voltage that
is acquired.
The external DATACLK signal must be LOW or CS must
be HIGH prior to BUSY rising (see time t25 in Figures 7 and
8). If this is not observed, the output shift register of the
ADS7812 will not be updated with the conversion result.
Instead, the previous contents of the shift register will
remain and the new result will be lost.
External DATACLK Active During the Next Conversion
If more than 12 clock cycles are provided to the DATACLK
input, the DATA output will go LOW after the rising edge
of the 13th clock period. The operation of the ADS7812 will
not be affected as long as the timing specifications are met.
Another method of obtaining the conversion result is shown
in Figure 7. Since the output shift register is not updated until
the end of the conversion, the previous result remains valid
during the next conversion. If a fast clock (≥ 2MHz) can be
provided to the ADS7812, the result can be read during time
t2. During this time, the noise from the DATACLK signal is
less likely to affect the conversion result.
Before reading the next three paragraphs, consult the Sensi-
tivity to External Digital Signals section of this data sheet.
This will explain many of the concerns regarding how and
when to apply the external DATACLK signal.
t1
t2
CONV
BUSY
t21
t24
t23
t25
DATACLK
DATA
1
2
3
4
11
12
1
t19
t20
t22
MSB
Bit 10
Bit 9
Bit 1
LSB
MSB
FIGURE 7. Serial Data Timing, External Clock, Clocking During the Next Conversion (EXT/INT HIGH,
CS LOW).
CONV
BUSY
t5
t4
t24
t25
DATACLK
DATA
1
2
n
n+1
11
12
Bit n-1
MSB
Bit 10
Bit n
Bit 1
LSB
FIGURE 8. Serial Data Timing, External Clock, Clocking After the Conversion Completes and During the Next Conversion
(EXT/INT HIGH, CS LOW).
ADS7812
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External DATACLK Active After the Conversion
and During the Next Conversion
CHIP SELECT (CS)
The CS input allows the digital outputs of the ADS7812 to
be disabled and gates the external DATACLK signal when
EXT/INT is HIGH. See Figure 9 for the enable and disable
time associated with CS and Figure 3 for a block diagram of
the ADS7812’s logic. The digital outputs can be disabled at
any time.
Figure 8 shows a method that is a hybrid of the two previous
approaches. This method works very well for microcontrollers
that do serial transfers 8 bits at a time and for slower
microcontrollers. For example, if the fastest serial clock that
the microcontroller can produce is 1µs, and two 8-bit trans-
fers must be used to obtain the serial data, the approach
shown in Figure 6 would result in a diminished throughput
(26kHz maximum conversion rate). The method described
in Figure 7 could not be used because time t25 would be
violated. The approach in Figure 8 results in an improved
throughput rate (33kHz maximum with a 1µs clock) and
DATACLK is LOW during t25.
Note that a conversion is initiated on the falling edge of CONV
even if CS is HIGH. If the EXT/INT input is LOW (internal
DATACLK) and CS is HIGH during the entire conversion, the
previous conversion result will be lost (the serial transmission
occurs but DATA and DATACLK are disabled).
CS
COMPATIBILITY WITH THE ADS7813
The only difference between the ADS7812 and the ADS7813
is in the internal control logic and the digital interface. Since
the ADS7813 is a 16-bit converter, the internal shift register
is 16 bits wide. In addition, only 16-bit decisions are made
during the conversion. Thus, the ADS7813’s conversion
time is approximately 133% of the ADS7812’s.
t26
t27
BUSY, DATA,
DATACLK(1)
HI-Z
Active
HI-Z
NOTE: (1) DATACLK is an output only when EXT/INT is LOW.
FIGURE 9. Enable and Disable Timing for Digital Outputs.
The timing presented in this data sheet will allow as much
compatibility as possible with the ADS7813. The main
concern will be the different number of serial clocks. If a
design must be compatible with both the ADS7812 and
ADS7813, it is recommended to consider the ADS7813
first. If the design works with the ADS7813, it will certainly
work with the ADS7812. This is also true in regards to
layout (see the Layout section of this data sheet).
ANALOG INPUT
The ADS7812 offers a number of input ranges. This is
accomplished by connecting the three input resistors to
either the analog input (VIN), to ground (GND), or to the
2.5V reference buffer output (BUF). Table I shows the
input ranges that are typically used in data acquisition
applications. These ranges are all specified to meet the
specifications given in the Specifications table. Table IV
contains a complete list of ideal input ranges, associated
input connections, and comments regarding the range.
ANALOG
INPUT
RANGE (V)
CONNECT
R1IN
CONNECT
R2IN
CONNECT
INPUT
IMPEDANCE
(kΩ)
R3IN
TO
TO
TO
COMMENT
0.3125 to 2.8125
–0.417 to 2.916
0.417 to 3.750
±3.333
VIN
VIN
VIN
VIN
VIN
BUF
GND
VIN
> 10,000
26.7
26.7
21.3
45.7
45.7
21.3
45.7
45.7
45.7
21.3
21.3
26.7
26.7
45.7
21.3
21.3
26.7
26.7
Specified offset and gain
VIN cannot go below GND – 0.3V
Offset and gain not specified
Specified offset and gain
VIN
VIN
VIN
BUF
BUF
BUF
GND
GND
GND
VIN
–15 to 5
VIN
BUF
GND
VIN
Offset and gain not specified
Specified offset and gain
±10
VIN
0.833 to 7.5
–2.5 to 17.5
2.5 to 22.5
0 to 2.857
–1 to 3
VIN
Offset and gain not specified
Exceeds absolute maximum VIN
Exceeds absolute maximum VIN
Offset and gain not specified
VIN cannot go below GND – 0.3V
Specified offset and gain
VIN
BUF
GND
VIN
VIN
BUF
BUF
BUF
BUF
BUF
GND
GND
GND
GND
GND
VIN
BUF
GND
VIN
0 to 4
VIN
–6.25 to 3.75
0 to 10
BUF
GND
VIN
Offset and gain not specified
Specified offset and gain
VIN
0.357 to 3.214
–0.5 to 3.5
0.5 to 4.5
±5
VIN
Offset and gain not specified
VIN cannot go below GND – 0.3V
Specified offset and gain
VIN
BUF
GND
VIN
VIN
BUF
GND
Specified offset and gain
1.25 to 11.25
VIN
Offset and gain not specified
TABLE IV. Complete List of Ideal Input Ranges.
ADS7812
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The input impedance results from the various connections
and the internal resistor values (refer to the block diagram on
the front page of this data sheet). The internal resistor values
are typical and can change by ±30%, due to process varia-
tions. However, the ratio matching of the resistors is consid-
erably better than this. Thus, the input range will vary only
a few tenths of a percent from part to part, while the input
impedance may vary up to ±30%.
time with slower amplifiers. Be very careful with single-
supply amplifiers, particularly if their output will be re-
quired to swing very close to the supply rails.
In addition, be careful in regards to the amplifier’s linearity.
The outputs of single-supply and “rail-to-rail” amplifiers
can saturate as they approach the supply rails. Rather than
the amplifier’s transfer function being a straight line, the
curve can become severely ‘S’ shaped. Also, watch for the
point where the amplifier switches from sourcing current to
sinking current. For some amplifiers, the transfer function
can be noticeably discontinuous at this point, causing a
significant change in the output voltage for a much smaller
change on the input.
The Specifications table contains the maximum limits for
the variation of the analog input range, but only for those
ranges where the comment field shows that the offset and
gain are specified (this includes all the ranges listed in Table
I). For the other ranges, the offset and gain are not tested and
are not specified.
Texas Instruments manufactures a wide variety of opera-
tional and instrumentation amplifiers that can be used to
drive the input of the ADS7812. These include the OPA627,
OPA134, OPA132, and INA110.
Five of the input ranges in Table IV are not recommended
for general use. For two of the these, the input voltage
exceeds the absolute maximum. These ranges can still be
used as long as the input voltage remains under the absolute
maximum, but this will moderately to significantly reduce
the full-scale range of the converter.
REFERENCE
The other three input ranges involve the connection at R2IN
being driven below GND – 0.3V. This input has a reverse-
biased ESD protection diode connection to ground. If R2IN
is taken below ground, this diode will be forward-biased and
will clamp the negative input at –0.4V to –0.7V, depending
on the temperature. Here again, these ranges can still be used
at the cost of the full-scale range of the converter.
The ADS7812 can be operated with its internal 2.5V refer-
ence or an external reference. By applying an external
reference voltage to the REF pin, the internal reference
voltage is overdriven. The voltage at the REF input is
internally buffered by a unity gain buffer. The output of this
buffer is present at the BUF and CAP pins.
Note that Table IV assumes that the voltage at the REF pin
is 2.5V. This is true if the internal reference is being used or
if the external reference is 2.5V. Other reference voltages
will change the values in Table IV.
REF
The REF pin is the output of the internal 2.5V reference or
the input for an external reference. A 1µF to 2.2µF tantalum
capacitor should be connected between this pin and ground.
The capacitor should be placed as close as possible to the
ADS7812.
HIGH IMPEDANCE MODE
When R1IN, R2IN, and R3IN are connected to the analog input,
the input range of the ADS7812 is 0.3125V to 2.8125V and
the input impedance is greater than 10MΩ. This input range
can be used to connect the ADS7812 directly to a wide
variety of sensors. Figure 10 shows the impedance of the
sensor versus the change in ILE and DLE of the ADS7812.
The performance of the ADS7812 can be improved for higher
sensor impedance by allowing more time for acquisition. For
example, 10µs of acquisition time will approximately double
sensor impedance for the same ILE/DLE performance.
When using the internal reference, the REF pin should not
be connected to any type of significant load. An external
load will cause a voltage drop across the internal 4kΩ
resistor that is in series with the internal reference. Even a
4MΩ external load to ground will cause a decrease in the
full-scale range of the converter by 4 LSBs.
LINEARITY ERROR vs SOURCE IMPEDANCE
0.60
0.55
TA = +25°C
The input impedance and capacitance of the ADS7812 are
very stable with temperature. Assuming that this is true of
the sensor as well, the graph shown in Figure 10 will vary
less than a few percent over the specified temperature range
of the ADS7812. If the sensor impedance varies signifi-
cantly with temperature, the worst-case impedance should
be used.
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
Acquisition Time = 5µs
DLE
ILE
DRIVING THE ADS7812 ANALOG INPUT
In general, any “reasonably fast”, high quality operational or
instrumentation amplifier can be used to drive the ADS7812
input. When the converter enters the acquisition mode, there
is some charge injection from the converter’s input to the
amplifier’s output. This can result in inadequate settling
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
External Source Impedance (kΩ)
FIGURE 10. Linearity Error vs Source Impedance in the High
Impedance Mode (R1IN = R2IN = R3IN = VIN).
ADS7812
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While in the power-down mode, the voltage on the capaci-
tors connected to CAP and REF will begin to leak off. The
voltage on the CAP capacitor leaks off much more rapidly
than the REF capacitor (the REF input of the ADS7812
becomes high impedance when PWDN is HIGH—this is not
true for the CAP input). When the power-down mode is
exited, these capacitors must be allowed to recharge and
settle to a 12-bit level. Figure 11 shows the amount of time
typically required to obtain a valid 12-bit result based on the
amount of time spent in power down (at room temperature).
This figure assumes that the total capacitance on the CAP
pin is 1.01µF.
The range for the external reference is 2.3V to 2.7V. The
voltage on REF determines the full-scale range of the con-
verter and the corresponding LSB size. Increasing the refer-
ence voltage will increase the LSB size in relation to the
internal noise sources which, in turn, can improve signal-to-
noise ratio. Likewise, decreasing the reference voltage will
reduce the LSB size and signal-to-noise ratio.
CAP
The CAP pin is used to compensate the internal reference
buffer. A 1µF tantalum capacitor in parallel with a 0.01µF
ceramic capacitor should be connected between this pin and
ground, with the ceramic capacitor placed as close as pos-
sible to the ADS7812. The total value of the capacitance on
the CAP pin is critical to optimum performance of the
ADS7812. A value larger than 2.0µF could overcompensate
the buffer while a value lower than 0.5µF may not provide
adequate compensation.
Figure 12 provides a circuit which can significantly reduce
the power up time if the power down time will be fairly brief
(a few seconds or less). A low on-resistance MOSFET is
used to disconnect the capacitance on the CAP pin from the
leakage paths internal to the ADS7812. This allows the
capacitors to retain their charge for a much longer period of
time, reducing the time required to recharge them at power
up. With this circuit, the power down time can be extended
to tens or hundreds of milliseconds with almost instanta-
neous power up.
BUF
The voltage on the BUF pin is the output of the internal
reference buffer. This pin is used to provide +2.5V to the
analog input or inputs for the various input configurations.
The BUF output can provide up to 1mA of current to an
external load. The load should be constant as a variable load
could affect the conversion result by modulating the BUF
voltage. Also note that the BUF output will show significant
glitches as each bit decision is made during a conversion.
Between conversions, the BUF output is quiet.
POWER-DOWN TO POWER-UP RESPONSE
300
TA = +25°C
250
200
150
100
50
POWER DOWN
The ADS7812 has a power-down mode that is activated by
taking CONV LOW and then PWRD HIGH. This will
power down all of the analog circuitry including the refer-
ence, reducing power dissipation to under 50µW. To exit the
power-down mode, CONV is taken HIGH and then PWRD
is taken LOW. Note that a conversion will be initiated if
PWRD is taken HIGH while CONV is LOW.
0
0.1
1
10
100
Power-Down Duration (ms)
FIGURE 11. Power-Down to Power-Up Response.
1RF7604
1
2
3
4
8
7
6
5
1
2
3
4
5
6
7
8
R1IN
GND
R2IN
R3IN
BUF
CAP
REF
GND
VS 16
PWRD 15
BUSY 14
CS 13
Power-Down Signal
CONV 12
EXT/INT 11
DATA 10
+
1µF
0.01µF
DATACLK
9
FIGURE 12. Improved Power-Up Response Circuit.
ADS7812
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For example, the timing diagram in Figure 2 shows that the
CONV signal should return HIGH sometime during time t2.
In fact, the CONV signal can return HIGH at any time
during the conversion. However, after time t2, the transition
of the CONV signal has the potential of creating a good deal
of noise on the ADS7812 die. If this transition occurs at just
precisely the wrong time, the conversion results could be
affected. In a similar manner, transitions on the DATACLK
input could affect the conversion result.
LAYOUT
The ADS7812 should be treated as a precision analog
component and should reside completely on the “analog”
portion of the printed circuit board. Ideally, a ground plane
should extend underneath the ADS7812 and under all other
analog components. This plane should be separate from the
digital ground until they are joined at the power supply
connection. This will help prevent dynamic digital ground
currents from modulating the analog ground through a
common impedance to power ground.
For the ADS7812, there are 12 separate bit decisions which
are made during the conversion. The most significant bit
decision is made first, proceeding to the least significant bit
at the end of the conversion. Each bit decision involves the
assumption that the bit being tested should be set. This is
combined with the result that has been achieved so far. The
converter compares this combined result with the actual
input voltage. If the combined result is too high, the bit is
cleared. If the result is equal to or lower than the actual input
voltage, the bit remains HIGH. This is why the basic
architecture is referred to as “successive approximation
register.”
The +5V power should be clean, well-regulated, and sepa-
rate from the +5V power for the digital portion of the design.
One possibility is to derive the +5V supply from a linear
regulator located near the ADS7812. If derived from the
digital +5V power, a 5Ω to 10Ω resistor should be placed in
series with the power connection from the digital supply. It
may also be necessary to increase the bypass capacitance
near the VS pin (an additional 100µF or greater capacitor in
parallel with the 10µF and 0.1µF capacitors). For designs
with a large number of digital components or very high
speed digital logic, this simple power supply filtering scheme
may not be adequate.
If the result so far is getting very close to the actual input
voltage, then the comparison involves two voltages which are
very close together. The ADS7812 has been designed so that
the internal noise sources are a minimum just prior to the
comparator result being latched. However, if a external digital
signal transitions at this time, a great deal of noise will be
coupled into the sensitive analog section of the ADS7812.
Even if this noise produces a difference between the two
voltages of only 2mV, the conversion result will be off by 3
counts or least significant bits (LSBs). (The internal LSB size
of the ADS7812 is 610µV regardless of the input range.)
SENSITIVITY TO EXTERNAL
DIGITAL SIGNALS
All successive approximation register-based A/D converters
are sensitive to external sources of noise. The reason for this
will be explained in the following paragraphs. For the
ADS7812 and similar A/D converters, this noise most often
originates due to the transition of external digital signals.
While digital signals that run near the converter can be the
source of the noise, the biggest problem occurs with the
digital inputs to the converter itself.
Once a digital transition has caused the comparator to make
a wrong bit decision, the decision cannot be corrected. All
subsequent bit decisions will then be wrong (unless some
type of error correction is employed). Figure 13 shows a
successive approximation process that has gone awry. The
dashed line represents what the correct bit decisions should
have been. The solid line represents the actual result of the
conversion.
In many cases, the system designer may not be aware that
there is a problem or a potential for a problem. For a 12-bit
system, these problems typically occur at the least significant
bits and only at certain places in the converter’s transfer
function. For a 16-bit converter, the problem can be much
easier to spot.
External Noise
SAR Operation after
Wrong Bit Decision
Actual Input
Voltage
Converter’s
Full-Scale
Input Voltage
Range
Proper SAR Operation
Internal DAC
Voltage
Wrong Bit Decision Made Here
t
Conversion Clock
1
1
0
0
1
0
1
0
0
0
Incorrect Result
Correct Result
Conversion Start
(Hold Mode)
(1
1)
FIGURE 13. SAR Operation When External Noise Affects the Conversion.
ADS7812
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Keep in mind that the time period when the comparator is
most sensitive to noise is fairly small. Also, the peak portion
of the noise “event” produced by a digital transition is fairly
brief as most digital signals transition in a few nanoseconds.
The subsequent noise may last for a period of time longer
than this and may induce further effects which require a
longer settling time; however, in general, the event is over
within a few tens of nanoseconds.
three converters. After the conversions are finished, each
result is transferred, in turn. The QSPI port is completely
programmable to handle the timing and transfers without
processor intervention. If the CONV signal is generated in
this way, it should be possible to make both AC and DC
measurements with the ADS7812, as the CONV signal will
have low jitter. Note that if the CONV signal is generated via
software commands, it will have a good deal of jitter and
only low frequency (DC) measurements can be made.
For the ADS7812, error correction is done when the tenth bit
is decided. During this bit decision, it is possible to correct
limited errors that may have occurred during previous bit
decisions. However, after the tenth bit, no such correction is
possible. Note that for the timing diagrams shown in Figures
2, 5, 6, 7, and 8, all external digital signals should remain
static from 8µs after the start of a conversion until BUSY
rises. The tenth bit is decided approximately 10µs to 11µs
into the conversion.
QSPI
ADS7812
CONV EXT/INT
+5V
PCS0
PCS1
PCS2
PCS3
SCK
CS
DATACLK
DATA
MIS0
APPLICATIONS INFORMATION
+5V
ADS7812
QSPI INTERFACING
CONV
CS
EXT/INT
Figure 14 shows a simple interface between the ADS7812
and any queued serial peripheral interface (QSPI) equipped
microcontroller (available on several Motorola devices).
This interface assumes that the convert pulse does not
originate from the microcontroller and that the ADS7812 is
the only serial peripheral.
DATACLK
DATA
+5V
ADS7812
Before enabling the QSPI interface, the microcontroller must
be configured to monitor the slave select (SS) line. When a
LOW to HIGH transition occurs (indicating the end of a
conversion), the port can be enabled. If this is not done, the
microcontroller and A/D converter may not be properly syn-
chronized. (The slave select line simply enables communica-
tion—it does not indicate the start or end of a serial transfer.)
CONV
CS
EXT/INT
DATACLK
DATA
FIGURE 15. QSPI Interface to the Three ADS7812s.
DSP56002 INTERFACING
Convert Pulse
The DSP56002 serial interface has an serial peripheral
interface (SPI) compatibility mode with some enhance-
ments. Figure 16 shows an interface between the ADS7812
and the DSP56002. As with the QSPI interface of Figure 14,
QSPI
ADS7812
CONV
Convert Pulse
PCS0/SS
MOSI
BUSY
DATA
DSP56002
ADS7812
SCK
DATACLK
CS
CONV
SC1
BUSY
EXT/INT
SRD
SCO
DATA
CPOL = 0 (Inactive State is LOW)
CPHA = 1 (Data valid on falling edge)
QSPI port is in slave mode.
DATACLK
CS
FIGURE 14. QSPI Interface to the ADS7812.
EXT/INT
SYN = 0 (Asychronous)
GCK = 1 (Gated clock)
Figure 15 shows a QSPI-equipped microcontroller interfac-
ing to three ADS7812s. There are many possible variations
to this interface scheme. As shown, the QSPI port produces
a common CONV signal which initiates a conversion on all
SCD1 = 0 (SC1 is an input)
SHFD = 0 (Shift MSB first)
WL1 = 0 WL0 = 1 (Word length = 12 bits)
FIGURE 16. DSP56002 Interface to the ADS7812.
ADS7812
16
SBAS042A
www.ti.com
the DSP56002 must be programmed to enable the serial
interface when a LOW to HIGH transition on SCI occurs.
APPLICATIONS CIRCUIT
Figure 18 shows a multiplexed data acquisition circuit using
the ADS7812. The MPC508A provides the multiplexing
function while the OPA134 is configured as a Sallen-Key,
two-pole, unity gain lowpass filter.
The DSP56002 can also provide the CONV signal, as shown
in Figure 17. The receive and transmit sections of the
interface are decoupled (asynchronous mode) and the trans-
mit section is set to generate a word length frame sync every
other transmit frame (frame rate divider set to 2). The
prescale modulus should be set to produce a transmit frame
at twice the desired conversion rate.
DSP56002
ADS7812
SC2
CONV
BUSY
SC0
SRD
DATACLK
DATA
CS
SYN = 0 (Asychronous)
EXT/INT
GCK = 1 (Gated clock)
SCD2 = 1 (SC2 is an output)
SHFD = 0 (Shift MSB first)
WL1 = 0 WL0 = 1 (Word length = 12 bits)
FIGURE 17. DSP56002 Interface to the ADS7812. Processor Initiates Conversions.
+15V
C1
2.2nF
MPC508A
In 1
±10V
Full Scale
ADS7812
R1
1.4kΩ
R2
15.4kΩ
In 2
In 3
In 4
In 5
In 6
In 7
In 8
R1IN
BUSY
CONV
OPA134
R2IN
R3IN
BUF
C2
330pF
DATA
–15V
DATACLK
µP
A0
A1
A2
FIGURE 18. Multiplexed Data Acquisition Circuit.
ADS7812
SBAS042A
17
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS7812PB
ADS7812UB
ACTIVE
PDIP
SOIC
SOIC
N
16
16
16
25
RoHS & Green
RoHS & Green
Call TI
N / A for Pkg Type
Level-3-260C-168 HR
Level-3-260C-168 HR
ADS7812P
B
Samples
Samples
Samples
ACTIVE
ACTIVE
DW
40
Call TI
Call TI
-40 to 85
-40 to 85
ADS7812U
B
ADS7812UB/1K
DW
1000 RoHS & Green
ADS7812U
B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS7812UB/1K
SOIC
DW
16
1000
330.0
16.4
10.75 10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 16
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
ADS7812UB/1K
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ADS7812PB
ADS7812UB
N
PDIP
SOIC
16
16
25
40
506
507
13.97
12.83
11230
5080
4.32
6.6
DW
Pack Materials-Page 3
GENERIC PACKAGE VIEW
DW 16
7.5 x 10.3, 1.27 mm pitch
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016A
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4220721/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SEE
DETAILS
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
R0.05 TYP
9
8
(9.3)
LAND PATTERN EXAMPLE
SCALE:7X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220721/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
R0.05 TYP
8
9
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
4220721/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
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Copyright © 2022, Texas Instruments Incorporated
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