ADS7819 [TI]
ANALOG-to-DIGITAL CONVERTER;
| 型号： | ADS7819 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ANALOG-to-DIGITAL CONVERTER |
| 文件： | 总13页 (文件大小：248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ADS7819
ADS7819
FPO
ADS7819
12-Bit 800kHz Sampling CMOS
ANALOG-to-DIGITAL CONVERTER
FEATURES
DESCRIPTION
● 1.25µs THROUGHPUT TIME
The ADS7819 is a complete 12-bit sampling A/D
using state-of-the-art CMOS structures. It contains a
complete 12-bit capacitor-based SAR A/D with inher-
ent S/H, reference, clock, interface for microprocessor
use, and three-state output drivers.
● STANDARD ±2.5V INPUT RANGE
● 70dB min SINAD WITH 250kHz INPUT
● ±3/4 LSB max INL AND ±1 LSB max DNL
● INTERNAL REFERENCE
The ADS7819 is specified at an 800kHz sampling
rate, and guaranteed over the full temperature range.
Laser-trimmed scaling resistors provide a ±2.5V input
range and inherent overvoltage protection up to ±25V.
● COMPLETE WITH S/H, REF, CLOCK, ETC.
● PARALLEL DATA w/ LATCHES
● 28-PIN 0.3" PDIP AND SOIC
The 28-pin ADS7819 is available in a plastic 0.3" DIP
and in an SOIC, both fully specified for operation over
the industrial –40°C to +85°C range.
Successive Approximation Register and Control Logic
Clock
CDAC
Output
Latches
BUSY
575Ω
±2.5V Input
and
Three
Three
State
State
Parallel
2.5kΩ
Comparator
Drivers
Data
Bus
Cap
18kΩ
Buffer
4.8kΩ
8.6kΩ
Internal
Ref
2.5V Ref Out/In
International Airport Industrial Park
•
Mailing Address: PO Box 11400
Cable: BBRCORP
•
Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd.
•
Tucson, AZ 85706
Tel: (520)746-1111 Twx: 910-952-1111
•
•
•
Telex: 066-6491
•
FAX: (520)889-1510
•
Immediate Product Info: (800)548-6132
© 1992 Burr-Brown Corporation
PDS-1193C
Printed in U.S.A. February, 1995
SBAS027
SPECIFICATIONS
At TA = –40°C to +85°C, fS = 800kHz, +VDIG = +VANA = +5V, –VANA = –5V, using internal reference and the 50Ω input resistor shown in Figure 4b, unless otherwise specified.
ADS7819P, U
TYP
ADS7819PB, UB
PARAMETER
RESOLUTION
CONDITIONS
MIN
MAX
MIN
TYP
MAX
*
UNITS
12
Bits
ANALOG INPUT
Voltage Range
Impedance
±2.5
3.1
5
*
*
*
V
kΩ
pF
Capacitance
THROUGHPUT SPEED
Conversion Time
Complete Cycle
940
*
ns
ns
Acquire & Convert
1250
*
Throughput Rate
800
*
kHz
DC ACCURACY
Integral Linearity Error
Differential Linearity Error
No Missing Codes
±1
±1
±0.75
*
LSB(1)
LSB
Guaranteed
0.1
*
*
Transition Noise(2)
LSB
%
ppm/°C
%
ppm/°C
LSB
ppm/°C
Full Scale Error(3, 4)
Full Scale Error Drift
Full Scale Error(3, 4)
Full Scale Error Drift
Bipolar Zero Error(3)
Bipolar Zero Error Drift
Power Supply Sensitivity
(+VDIG = +VANA = VD)
±0.5
±0.5
±8
±0.25
±12
±12
±2
*
*
*
Ext. 2.5000V Ref
Ext. 2.5000V Ref
*
±4
+4.75V < VD < +5.25V
–5.25V < –VANA < –4.75V
±5
±0.5
*
*
LSB
LSB
AC ACCURACY
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise+Distortion)
Signal-to-Noise
f
IN = 250kHz
74
84
–82
71
71
1.5
77
85
–83
*
*
*
dB(5)
dB
dB
dB
MHz
fIN = 250kHz
–74
–77
f
f
IN = 250kHz
IN = 250kHz
68
68
70
70
Usable Bandwidth(6)
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
Overvoltage Recovery(7)
20
10
180
250
*
*
*
*
ns
ps
ns
ns
FS Step
REFERENCE
Internal Reference Voltage
Internal Reference DC Source Current
(External load should be static)
Internal Reference Drift
External Reference Voltage Range
For Specified Linearity
2.48
2.3
2.5
100
2.52
*
*
*
*
*
V
µA
6
2.5
ppm/°C
V
2.7
*
*
*
External Reference Current Drain
Ext. 2.5000V Ref
100
µA
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
–0.3
+2.4
+0.8
VD + 0.3
±10
*
*
*
*
*
*
V
V
µA
µA
VIL = 0V
VIH = 5V
IIH
±10
DIGITAL OUTPUTS
Data Format
Data Coding
VOL
Parallel 12-bits
Binary Two’s Complement
+0.4
ISINK = 1.6mA
ISOURCE = 500µA
High-Z State,
*
*
*
V
V
µA
VOH
+2.8
*
Leakage Current
±5
V
OUT = 0V to VDIG
High-Z State
Output Capacitance
15
pF
DIGITAL TIMING
Bus Access Time
Bus Relinquish Time
62
83
*
*
ns
ns
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
2
ADS7819
SPECIFICATIONS (CONT)
At TA = –40°C to +85°C, fS = 800kHz, +VDIG = +VANA = +5V, –VANA = –5V, using internal reference and the 50Ω input resistor shown in Figure 4b, unless otherwise specified.
ADS7819P, U
TYP
ADS7819PB, UB
PARAMETER
CONDITIONS
MIN
MAX
MIN
TYP
MAX
UNITS
POWER SUPPLIES
Specified Performance
+VDIG = +VANA
–VANA
+IDIG
+IANA
+4.75
–5.25
+5
–5
+16
+16
–13
+5.25
–4.75
*
*
*
*
*
*
*
*
*
V
V
mA
mA
mA
–IANA
Derated Performance
+VDIG = +VANA
–VANA
+4.5
–5.5
+5
–5
225
+5.5
–4.5
275
*
*
*
*
*
*
*
V
V
mW
2
Power Dissipation
fS = 800kHz
TEMPERATURE RANGE
Specified Performance
Derated Performance
Storage
–40
–55
–65
+85
+125
+150
*
*
*
*
*
*
°C
°C
°C
Thermal Resistance (θJA
)
Plastic DIP
SOIC
75
75
*
*
°C/W
°C/W
NOTES: (1) LSB means Least Significant Bit. For the 12-bit, ±2.5V input ADS7819, one LSB is 1.22mV. (2) Typical rms noise at worst case transitions and
temperatures. (3) Measured with 50Ω in series with analog input. Adjustable to zero with external potentiometer. (4) Full scale error is the worst case of –Full Scale
or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the
effect of offset error. (5) All specifications in dB are referred to a full-scale ±2.5V input. (6) Usable Bandwidth defined as Full-Scale input frequency at which Signal-
to-(Noise+Distortion) degrades to 60dB, or 10 bits of accuracy. (7) Recovers to specified performance after 2 x FS input over voltage.
ABSOLUTE MAXIMUM RATINGS
Analog Inputs: VIN .............................................................................. ±25V
ELECTROSTATIC
DISCHARGE SENSITIVITY
REF .................................... +VANA +0.3V to AGND2 –0.3V
CAP ........................................... Indefinite Short to AGND2
Momentary Short to +VANA
Ground Voltage Differences: DGND, AGND1, AGND2 ................... ±0.3V
+VANA ................................................................................................... +7V
performance degradation to complete device failure. Burr-
+VDIG to +VANA ................................................................................. +0.3V
+VDIG ..................................................................................................... 7V
Electrostatic discharge can cause damage ranging from
BrownCorporationrecommendsthatallintegrated circuitsbe
–VANA ................................................................................................... –7V
handled and stored using appropriate ESD protection
Digital Inputs ............................................................ –0.3V to +VDIG +0.3V
methods.
Maximum Junction Temperature ................................................... +165°C
Internal Power Dissipation ............................................................. 825mW
Lead Temperature (soldering, 10s) ................................................ +300°C
ORDERING AND PACKAGE INFORMATION
MINIMUM
MAXIMUM
INTEGRAL
LINEARITY
ERROR (LSB)
SIGNAL-TO-
(NOISE +
DISTORTION)
RATIO (dB)
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE DRAWING
NUMBER(1)
MODEL
PACKAGE
ADS7819P
ADS7819PB
ADS7819U
ADS7819UB
±1
±0.75
±1
68
70
68
70
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
28-Pin Plastic DIP
28-Pin Plastic DIP
28-Pin SOIC
246
246
217
217
±0.75
28-Pin SOIC
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book.
®
3
ADS7819
PIN ASSIGNMENTS
DIGITAL
I/O
PIN #
NAME
DESCRIPTION
1
2
3
VIN
AGND1
REF
Analog Input. Connect via 50Ω to analog input. Full-scale input range is ±2.5V.
Analog Ground. Used internally as ground reference point. Minimal current flow.
Reference Input/Output. Outputs internal reference of +2.5V nominal. Can also be driven by external system
reference. In both cases, decouple to ground with a 0.1µF ceramic capacitor.
Reference Buffer Output. 10µF tantalum capacitor to ground. Nominally +2V.
Analog Ground.
4
5
6
CAP
AGND2
D11 (MSB)
O
Data Bit 11. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is
LOW, or when a conversion is in progress.
7
8
9
D10
D9
D8
D7
D6
D5
D4
DGND
D3
D2
O
O
O
O
O
O
O
Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Digital Ground.
Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW, or when a conversion is in progress.
Data Bit 0. Least Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is
LOW, or when a conversion is in progress.
10
11
12
13
14
15
16
17
18
O
O
O
O
D1
D0 (LSB)
19
20
21
22
23
Not internally connected.
+VANA
+VDIG
DGND
R/C
Analog Positive Supply Input. Nominally +5V. Connect directly to pins 21, 27 and 28.
Digital Supply Input. Nominally +5V. Connect directly to pins 20, 27 and 28.
Digital ground.
Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and
starts a conversion. With CS LOW and no conversion in progress, a rising edge on R/C enables the output
data bits.
I
24
25
CS
I
Chip Select. With R/C LOW, a falling edge on CS will initiate a conversion. With R/C HIGH and no conversion
in progress, a falling edge on CS will enable the output data bits.
Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the
data is latched into the output register. With CS LOW and R/C HIGH, output data will be valid when BUSY
rises, so that the rising edge can be used to latch the data.
BUSY
O
26
–VANA
Analog Negative Supply Input. Nominally –5V. Decouple to ground with 0.1µF ceramic and 10µF tantalum
capacitors.
27
28
+VDIG
+VANA
Digital Supply Input. Nominally +5V. Connect directly to pins 20, 21 and 28.
Analog Positive Supply Input. Nominally +5V. Connect directly to pins 20, 21 and 27, and decouple to ground
with 0.1µF ceramic and 10µF tantalum capacitors.
PIN CONFIGURATION
VIN
AGND1
REF
1
2
3
4
5
6
7
8
9
28 +VANA
27 +VDIG
26 –VANA
25 BUSY
24 CS
CAP
AGND2
D11 (MSB)
D10
23 R/C
22 DGND
21 +VDIG
20 +VANA
19 NC(1)
18 D0 (LSB)
17 D1
ADS7819
D9
D8
D7 10
D6 11
D5 12
D4 13
16 D2
DGND 14
15 D3
NOTE: (1) Not Internally Connected.
®
4
ADS7819
TYPICAL PERFORMANCE CURVES
T = +25°C, fS =800kHz, +VDIG = +VANA = +5V, –VANA = –5V, using internal reference and the input 50Ω resistors as shown in Figure 4b, unless otherwise specified.
FREQUENCY SPECTRUM
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 252kHz, –0.5dB)
(4096 Point FFT; fIN = 502kHz, –0.5dB)
0
–20
0
–2
–40
–4
–60
–6
–80
–8
–100
–120
–10
–120
0
100
200
300
400
400
10M
0
100
200
300
400
Frequency (kHz)
Frequency (kHz)
FREQUENCY SPECTRUM
(4096 Point FFT; f1IN = 232kHz, –6.5dB;
f2IN = 272kHz, –6.5dB)
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 1.002MHz, –0.5dB)
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
100
200
300
0
100
200
300
400
Frequency (kHz)
Frequency (kHz)
A.C. PARAMETERS vs TEMPERATURE
(fIN = 250kHz, –0.5dB)
SIGNAL-TO-(NOISE + DISTORTION)
vs INPUT FREQUENCY (fIN = –0.5dB)
100
95
90
85
80
75
70
65
60
90
80
70
60
50
40
30
20
10
SFDR
THD
SNR
SINAD
1k
10k
100k
1M
–75 –50 –25
0
25
50
75
100 125 150
Input Signal Frequency (Hz)
Temperature (°C)
®
5
ADS7819
TYPICAL PERFORMANCE CURVES (CONT)
T = +25°C, fS =800kHz, +VDIG = +VANA = +5V, –VANA = –5V, using internal reference and the 50Ω input resistors as shown in Figure 4b, unless otherwise specified.
CODE TRANSITION NOISE
1
0.5
0
100
75
–0.5
–1
All Codes INL
50
0
512
1024
1536
2048
2560
3072
3584
4095
Decimal Code
25
0
1
0.5
0
0
0.25
0.5
0.75
1
–0.5
–1
Analog Input Voltage – Expected Code Center (LSBs)
All Codes DNL
0
512
1024
1536
2048
2560
3072
3584
4095
Decimal Code
D.C. PARAMETERS vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE vs TEMPERATURE
2
1
0
–1
–2
2.520
2.515
2.510
2.505
2.500
2.495
2.490
2.485
2.480
Offset Error
0.2
0.1
0
–0.1
–0.2
+FS Error
0.2
0.1
0
–FS Error
–0.1
–75 –50 –25
0
25
50
75
100 125 150
–0.2
Temperature (°C)
–75 –50
–25
0
25
50
75
100 125 150
Temperature (°C)
CONVERSION TIME (t7) vs TEMPERATURE
1200
1150
1100
1050
1000
950
900
850
800
750
–75 –50 –25
0
25
50
75
100 125 150
Temperature (°C)
®
6
ADS7819
The ADS7819 will begin tracking the input signal at the end
of the conversion. Allowing 1.25µs between convert com-
mands assures accurate acquisition of a new signal.
BASIC OPERATION
Figure 1 shows a basic circuit to operate the ADS7819.
Taking R/C (pin 23) LOW for 40ns will initiate a conver-
sion. BUSY (pin 25) will go LOW and stay LOW until the
conversion is completed and the output registers are up-
dated. Data will be output in Binary Two’s Complement
with the MSB on D11 (pin 6). BUSY going HIGH can be
used to latch the data. All convert commands will be ignored
while BUSY is LOW.
STARTING A CONVERSION
The combination of CS (pin 24) and R/C (pin 23) LOW for
a minimum of 40ns puts the sample/hold of the ADS7819 in
the hold state and starts a conversion. BUSY (pin 25) will go
LOW and stay LOW until the conversion is completed and
the internal output register has been updated. All new
convert commands during BUSY LOW will be ignored.
CS
1
R/C
X
BUSY OPERATION
X
1
None. Databus in Hi-Z state.
2
The ADS7819 will begin tracking the input signal at the end
↓
0
Initiates conversion. Databus remains in
Hi-Z state.
of the conversion. Allowing 1.25µs between convert com-
mands assures accurate acquisition of a new signal. Refer to
Table I for a summary of CS, R/C, and BUSY states and
Figures 2 and 3 for timing parameters.
0
0
↓
1
Initiates conversion. Databus enters Hi-Z
state.
1
↑
Conversion completed. Valid data from the
most recent conversion on the databus.
↓
↓
0
0
1
1
↑
0
1
0
0
↑
Enables databus with valid data from the
most recent conversion.
DESCRIPTION
ANALOG VALUE
±2.5V
DIGITAL OUTPUT
Full Scale Range
Conversion in progress. Databus in Hi-Z
state, enabled when the conversion is completed.
BINARY TWO'S COMPLEMENT
Least Significant
Bit (LSB)
1.22mV
BINARY CODE
HEX CODE
Conversion in progress. Databus in Hi-Z
state, enabled when the conversion is completed.
+Full Scale
(2.5V – 1LSB)
2.499V
0111 1111 1111
7FF
Conversion completed. Valid data from the
most recent conversion in the output register
but the output pins D11-D0 are tri-stated.
Midscale
0V
0000 0000 0000
1111 1111 1111
000
FFF
One LSB below
Midscale
–1.22mV
X
X
0
New convert commands ignored. Conversion
in progress.
–Full Scale
–2.5V
1000 0000 0000
800
Table I. Control Line Functions for ‘read’ and ‘convert’.
TABLE II. Ideal Input Voltages and Output Codes.
0.1µF 10µF
+5V
+
50Ω
±2.5V
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
0.1µF 10µF
+
–5V
3
10µF
+
4
BUSY
0.1µF
5
Convert Pulse
D11 (MSB)
6
D10
D9
D8
D7
D6
D5
D4
7
ADS7819
8
40ns min
9
10
11
12
13
14
NC
D0 (LSB)
D1
D2
D3
FIGURE 1. Basic Operation
®
7
ADS7819
CS and R/C are internally OR’d and level triggered. There
is not a requirement which input goes LOW first when
initiating a conversion. If it is critical that CS or R/C initiate
the conversion, be sure the less critical input is LOW at least
10ns prior to the initiating input.
The nominal input impedance of 3.125kΩ results from the
combination of the internal resistor network shown on the
front page of the product data sheet and the external 50Ω
resistor. The input resistor divider network provides inherent
over-voltage protection guaranteed to at least ±25V. The
50Ω, 1% resistor does not compromise the accuracy or drift
of the converter. It has little influence relative to the internal
resistors, and tighter tolerances are not required.
To reduce the number of control pins, CS can be tied LOW
using R/C to control the read and convert modes. Note that
the parallel output will be active whenever R/C is HIGH and
no conversion is in progress. See the Reading Data section
and refer to Table I for control line functions for ‘read’ and
‘convert’ modes.
Note: The values shown for the internal resistors are for
reference only. The exact values can vary by ±30%. This is
true of all resistors internal to the ADS7819. Each resistive
divider is trimmed so that the proper division is achieved.
READING DATA
NOTE: (1) Full scale error includes offset and gain errors and is measured at
both +FS and –FS.
The ADS7819 outputs full parallel data in Binary Two’s
Complement data format. The parallel output will be active
when R/C (pin 23) is HIGH, CS (pin 24) is LOW, and no
conversion is in progress. Any other combination will tri-state
the parallel output. Valid conversion data can be read in a full
parallel, 12-bit word on D11-D0 (pins 6-13 and 15-18). Refer
to Table II for ideal output codes.
SYMBOL
DESCRIPTION
MIN
TYP
MAX UNITS
t1
t2
Convert Pulse Width
40
ns
Data Valid Delay
After Start of Conversion
965
70
1100
125
ns
t3
BUSY Delay
ns
After the conversion is completed and the output registers
have been updated, BUSY (pin 25) will go HIGH. Valid data
from the most recent conversion will be available on
D11-D0 (pins 6-13 and 15-18). BUSY going HIGH can be
used to latch the data. Refer to Table III and Figures 2 and 3.
From Start of Conversion
t4
t5
BUSY LOW
960
90
1085
ns
ns
BUSY Delay After
End of Conversion
t6
Aperture Delay
Conversion Time
Acquisition Time
Throughput Time
Bus Relinquish Time
20
940
180
1120
50
ns
ns
ns
ns
ns
ns
Note: For best performance, the external data bus connected
to D11-D0 should not be active during a conversion. The
switching noise of the external asynchronous data signals
can cause digital feed through degrading the converter’s
performance.
t7
1030
220
1250
83
t8
t7 & t8
t9
10
20
t10
BUSY Delay
65
100
The number of control lines can be reduced by tieing CS
LOW while using R/C to initiate conversions and activate
the output mode of the converter. See Figure 2.
After Data Valid
t11
t12
t13
R/C to CS
Setup Time
10
1250
10
ns
ns
ns
Time Between
Conversions
INPUT RANGES
Bus Access Time
30
62
The ADS7819 has a ±2.5V input range. Figures 4a and 4b
show the necessary circuit connections for the ADS7819
with and without external hardware trim. Offset and full
scale error(1) specifications are tested and guaranteed with
the 50Ω resistor shown in Figure 4b. This external resistor
makes it possible to trim the offset ±12mV using a trim pot
or trim DAC. This resistor may be left out if the offset and
gain errors will be corrected in software or if they are
negligible in regards to the particular application. See the
Calibration section of the data sheet for details.
TABLE III. Timing Specifications (TMIN to TMAX).
®
8
ADS7819
t1
R/C
t12
t2
t3
t5
t4
BUSY
MODE
t6
Convert
t7
Acquire
t8
Convert
Acquire
2
Hi-Z State
Data Valid
t10
Hi-Z State
DATA BUS
Data Valid
t9
FIGURE 2. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low).
t11
t11
t11
t11
R/C
CS
t1
t3
t5
t4
BUSY
t6
Convert
t7
Acquire
Acquire
MODE
t2
DATA
BUS
Hi-Z State
Data Valid Hi-Z State
t9
t13
FIGURE 3. Using CS to Control Conversion and Read Timing.
50Ω
50Ω
VIN
VIN
VIN
VIN
+5V
R1
20kΩ
AGND1
REF
AGND1
REF
P1
5kΩ
R2
604kΩ
+5V
–5V
0.1µF
10µF
P2
5kΩ
0.1µF
10µF
CAP
CAP
+
+
AGND2
AGND2
NOTE: Use 1% metal film resistors. Trim offset at 0V first, then trim
gain at 2.5V.
FIGURE 4b. Circuit Diagram Without External Hardware
Trim.
FIGURE 4a. Circuit Diagram With External Hardware Trim.
®
9
ADS7819
The external 50Ω resistor shown in Figure 4b may not be
necessary in some applications. This resistor provides trim
capability for the offset and compensates for a slight gain
adjustment internal to the ADS7819. Not using the 50Ω
resistor will cause a small gain error but will have no effect
on the inherent offset error. Figure 5 shows typical transfer
function characteristics with and without the 50Ω resistor in
the circuit.
CALIBRATION
The ADS7819 can be trimmed in hardware or software. The
offset should be trimmed before the gain since the offset
directly affects the gain.
Hardware Calibration
To calibrate the offset and gain of the ADS7819, install the
proper resistors and potentiometers as shown in Figure 4a.
The calibration range is ±12mV for bipolar zero and ±30mV
for full scale.
REFERENCE
Potentiometer P1 and resistor R1 form the offset adjust
circuit and P2 and R2 the gain adjust circuit. The exact values
are not critical. R1 and R2 should not be made any larger than
the value shown. They can easily be made smaller to provide
increased adjustment range. Reducing these below 15% of
the indicated values could begin to adversely affect the
operation of the converter.
The ADS7819 can operate with its internal 2.5V reference or an
external reference. By applying an external reference to pin 3,
the internal reference can be bypassed. The reference voltage at
REF is buffered internally and output on CAP (pin 4).
The internal reference has a 6 ppm/°C drift (typical) and
accounts for approximately 20% of the full scale error
(FSE = ±0.5% for low grade, ±0.25% for high grade.)
P1 and P2 can also be made larger to reduce power dissipa-
tion. However, larger resistances will push the useful adjust-
ment range to the edges of the potentiometer. P1 should
probably not exceed 20kΩ and P2 100kΩ in order to main-
tain reasonable sensitivity.
REF
REF (pin 3) is an input for an external reference or the
output for the internal 2.5V reference. A 0.1µF capacitor
should be connected as close to the REF pin as possible. The
capacitor and the output resistance of REF create a low pass
filter to band limit noise on the reference. Using a smaller
value capacitor will introduce more noise to the reference
degrading the SNR and SINAD. The REF pin should not be
used to drive external AC or DC loads.
Software Calibration
To calibrate the offset and gain of the ADS7819, no external
resistors are required. See the No Calibration section for
details on the effects of the external resistor.
No Calibration
See Figure 4b for circuit connections. Note that the actual
voltage dropped across the 50Ω resistor is nearly two orders
of magnitude lower than the voltage dropped across the
internal resistor divider network. This should be taken into
consideration when choosing the accuracy and drift specifi-
cations of the external resistors. In most applications, 1%
metal-film resistors will be sufficient.
The range for the external reference is 2.3V to 2.7V and
determines the actual LSB size. Increasing the reference
voltage will increase the full scale range and the LSB size
of the converter which can improve the SNR.
Digital
Output
+ Full Scale
–2.5V –2.46V
Analog
Input
2.5V
2.46V
Typical Transfer Function
with 50Ω Resistor
Typical Transfer Function
Without 50Ω Resistor
– Full Scale
FIGURE 5. Circuit Diagram With and Without External Resistors.
®
10
ADS7819
CAP
other CMOS A/D converters, releases 5%—10% of the
charge. There is also a resistive front end which attenuates
any charge which is released. The end result is a minimal
requirement for the op amp on the front end. Any op amp
sufficient for the signal in an application will be sufficient to
the drive the ADS7819.
CAP (pin 4) is the output of the internal reference buffer. A
10µF tantalum capacitor should be placed as close to the
CAP as possible to provide optimum switching currents for
the CDAC throughout the conversion cycle and compensa-
tion for the output of the buffer. Using a capacitor any
smaller than 1µF can cause the output buffer to oscillate and
may not have sufficient charge for the CDAC. Capacitor
values larger than 10µF will have little effect on improving
performance. The voltage on the CAP pin is approximately
2V when using the internal reference, or 80% of an exter-
nally supplied reference.
The resistive front end of the ADS7819 also provides a
guaranteed ±25V over voltage protection. In most cases, this
eliminates the need for external input protection circuitry.
INTERMEDIATE LATCHES
The ADS7819 does have 2tri-state outputs for the parallel
port, but intermediate latches should be used if the bus will
be active during conversions. If the bus is not active during
conversions, the tri-state outputs can be used to isolate the
A/D from other peripherals on the same bus.
LAYOUT
POWER
The ADS7819 uses the majority of its power for analog and
static circuitry, and it should be considered as an analog
component. For optimum performance, tie the analog and
digital +5V power pins to the same +5V power supply and
tie the analog and digital grounds together.
Intermediate latches are beneficial on any monolithic A/D
converter. The ADS7819 has an internal LSB size of 610µV.
Transients from fast switching signals on the parallel port,
even when the A/D is tri-stated, can be coupled through the
substrate to the analog circuitry causing degradation of
converter performance.
For best performance, the ±5V supplies can be produced
from whatever analog supply is used for the rest of the
analog signal conditioning. If ±12V or ±15V supplies are
present, simple regulators can be used. The +5V power for
the A/D should be separate from the +5V used for the
system’s digital logic. Connecting +VDIG (pin 27) directly to
a digital supply can reduce converter performance due to
switching noise from the digital logic.
Although it is not suggested, if the digital supply must be
used to power the converter, be sure to properly filter the
supply. Either using a filtered digital supply or a regulated
analog supply, both VDIG and VANA should be tied to the
same +5V source.
GROUNDING
Three ground pins are present on the ADS7819. DGND (pin 22)
is the digital supply ground. AGND2 (pin 5) is the analog
supply ground. AGND1 (pin 2) is the ground which all analog
signals internal to the A/D are referenced. AGND1 is more
susceptible to current induced voltage drops and must have the
path of least resistance back to the power supply.
All the ground pins of the ADS should be tied to the
analog ground plane, separated from the system’s digital
logic ground, to achieve optimum performance. Both ana-
log and digital ground planes should be tied to the “sys-
tem” ground as near to the power supplies as possible.
This helps to prevent dynamic digital ground currents
from modulating the analog ground through a common
impedance to power ground.
SIGNAL CONDITIONING
The FET switches used for the sample hold on many CMOS
A/D converters release a significant amount of charge injec-
tion which can cause the driving op amp to oscillate. The
FET switch on the ADS7819, compared to FET switches on
®
11
ADS7819
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jun-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ADS7819P
ADS7819PB
ADS7819U
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
NT
NT
28
28
28
28
28
28
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Replaced by ADS7810U
Replaced by ADS7810U
Replaced by ADS7810U
Replaced by ADS7810U
Replaced by ADS7810U
Replaced by ADS7810U
DW
DW
DW
DW
ADS7819U/1K
ADS7819UB
ADS7819UB/1K
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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