ADS7820U_技术文档

®

ADS7820

12-Bit 10µs Sampling CMOS

ANALOG-to-DIGITAL CONVERTER

DESCRIPTION

FEATURES

The ADS7820 is a complete 12-bit sampling A/D

using state-of-the-art CMOS structures. It contains a

complete 12-bit, capacitor-based SAR A/D with S/H,

reference, clock, interface for microprocessor use, and

three-state output drivers.

● 100kHz min SAMPLING RATE

● 0 to +5V INPUT RANGE

● 72dB min SINAD WITH 45kHz INPUT

● ±1/2 LSB max INL AND DNL

● SINGLE +5V SUPPLY OPERATION

● PIN-COMPATIBLE WITH 16-BIT ADS7821

The ADS7820 is specified at a 100kHz sampling rate,

and guaranteed over the full temperature range. Laser-

trimmed scaling resistors provide a 0 to +5V input

range, with power dissipation under 100mW.

● USES INTERNAL OR EXTERNAL

REFERENCE

The 28-pin ADS7820 is available in a plastic 0.3" DIP

and in an SOIC, both fully specified for operation over

the industrial –40°C to +85°C range.

● COMPLETE WITH S/H, REF, CLOCK, ETC.

● FULL PARALLEL DATA OUTPUT

● 100mW max POWER DISSIPATION

● 28-PIN 0.3" PLASTIC DIP AND SOIC

R/C

Clock

CS

BYTE

BUSY

Successive Approximation Register and Control Logic

CDAC

Output

Three

Latches

State

and

5kΩ

0 to +5V Input

Parallel

Three

Data

6.66kΩ

20kΩ

State

Bus

Comparator

Drivers

CAP

Internal

+2.5V Ref

Buffer

4kΩ

REF

International Airport Industrial Park

•

Mailing Address: PO Box 11400

Cable: BBRCORP

•

Tucson, AZ 85734

•

Street Address: 6730 S. Tucson Blvd.

• Tucson, AZ 85706

Tel: (520) 746-1111

•

Twx: 910-952-1111

•

Telex: 066-6491

•

FAX: (520) 889-1510

•

Immediate Product Info: (800) 548-6132

®

Printed in U.S.A. June, 1996

ADS7820

_PDS1_-1322

SBAS047

SPECIFICATIONS

ELECTRICAL

T_A= –40°C to +85°C, f_S= 100kHz, V_DIG= V_ANA= +5V, using internal reference, unless otherwise specified.

ADS7820P/U

ADS7820PB/UB

TYP

PARAMETER

RESOLUTION

CONDITIONS

MIN

TYP

MAX

MIN

MAX

UNITS

12

✱

Bits

ANALOG INPUT

Voltage Ranges

Impedance

0 to +5

10

35

✱

V

kΩ

pF

Capacitance

THROUGHPUT SPEED

Conversion Time

Complete Cycle

5.7

8

10

✱

µs

Acquire and Convert

Throughput Rate

100

✱

kHz

DC ACCURACY

Integral Linearity Error

Differential Linearity Error

No Missing Codes

Transition Noise⁽²⁾

Full Scale Error^(3,4)

Full Scale Error Drift

Full Scale Error^(3,4)

Full Scale Error Drift

Offset Error

±1.0

±0.5

LSB⁽¹⁾

LSB

Bits

LSB

%

ppm/°C

%

ppm/°C

mV

ppm/°C

LSB

Guaranteed

0.1

✱

±0.5

±8

±0.25

±4

±7

±2

±5

✱

Ext. 2.5000V Ref

Offset Error Drift

Power Supply Sensitivity

(V_DIG= V_ANA= V_D)

✱

+4.75V < V_D< +5.25V

±0.75

±0.5

AC ACCURACY

Spurious-Free Dynamic Range

Total Harmonic Distortion

Signal-to-(Noise+Distortion)

Signal-to-Noise

f

_IN= 45kHz

80

✱

dB⁽⁵⁾

dB

kHz

f_IN= 45kHz

–80

✱

70

72

Full-Power Bandwidth⁽⁶⁾

250

✱

SAMPLING DYNAMICS

Aperture Delay

Transient Response

Overvoltage Recovery⁽⁷⁾

40

✱

ns

µs

ns

FS Step

2

✱

150

REFERENCE

Internal Reference Voltage

Internal Reference Source Current

(Must use external buffer.)

External Reference Voltage Range

for Specified Linearity

2.48

2.3

2.5

1

2.52

✱

V

µA

2.5

2.7

✱

V

External Reference Current Drain

Ext. 2.5000V Ref

100

µA

DIGITAL INPUTS

Logic Levels

V_IL

V_IH

I_IL

–0.3

+2.0

+0.8

V_D+0.3V

±10

✱

V

µA

I_IH

±10

DIGITAL OUTPUTS

Data Format

Data Coding

V_OL

Parallel 12 bits

Straight Binary

+0.4

I_SINK= 1.6mA

I_SOURCE= 500µA

High-Z State,

V_OUT= 0V to V_DIG

High-Z State

✱

V

µA

V_OH

+4

✱

Leakage Current

±5

Output Capacitance

15

pF

DIGITAL TIMING

Bus Access Time

Bus Relinquish Time

83

✱

ns

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN

assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject

to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not

authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

®

2

ADS7820

SPECIFICATIONS (CONT)

ELECTRICAL

T_A= –40°C to +85°C, f_S= 100kHz, V_DIG= V_ANA= +5V, using internal reference, unless otherwise specified.

ADS7820P/U

ADS7820PB/UB

TYP

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

MAX

UNITS

POWER SUPPLIES

Specified Performance

V_DIG

Must be ≤ V_ANA

+4.75

+5

0.3

16

+5.25

✱

V

mA

V_ANA

+I_DIG

+I_ANA

Power Dissipation

f

_S= 100kHz

100

✱

mW

TEMPERATURE RANGE

Specified Performance

Derated Performance

Storage

–40

–55

–65

+85

+125

+150

✱

°C

Thermal Resistance (θ_JA

)

Plastic DIP

SOIC

75

✱

°C/W

NOTES: (1) LSB means Least Significant Bit. For the 12-bit, 0 to +5V input ADS7820, one LSB is 1.22mV. (2) Typical rms noise at worst case transitions and

temperatures. (3) Adjustable to zero with external potentiometer as shown in Figure 4b. (4) Full scale error is the worst case of Full Scale untrimmed deviation from

ideal last code transition divided by the transition voltage and includes the effect of offset error. (5) All specifications in dB are referred to a full-scale input. (6) Full-

Power Bandwidth defined as Full-Scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60dB, or 10 bits of accuracy. (7) Recovers to specified

performance after 2 x FS input overvoltage.

ABSOLUTE MAXIMUM RATINGS

ELECTROSTATIC

Analog Inputs: V_IN....................................................–0.7V to +V_ANA+0.3V

REF .................................... +V_ANA+0.3V to AGND2 –0.3V

DISCHARGE SENSITIVITY

CAP ........................................... Indefinite Short to AGND2

Momentary Short to V_ANA

Electrostatic discharge can cause damage ranging from per-

formance degradation to complete device failure. Burr-

Brown Corporation recommends that all integrated circuits

Ground Voltage Differences: DGND, AGND1, AGND2 ................... ±0.3V

V_ANA....................................................................................................... 7V

V_DIGto V_ANA..................................................................................... +0.3V

V_DIG....................................................................................................... 7V

be handled and stored using appropriate ESD protection

methods.

Digital Inputs ............................................................ –0.3V to +V_DIG+0.3V

Maximum Junction Temperature ................................................... +165°C

Internal Power Dissipation ............................................................. 825mW

Lead Temperature (soldering, 10s) ................................................ +300°C

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet

PACKAGE INFORMATION

PACKAGE DRAWING

published specifications.

PRODUCT

PACKAGE

NUMBER⁽¹⁾

ADS7820P

ADS7820PB

ADS7820U

ADS7820UB

Plastic DIP

SOIC

246

217

SOIC

NOTE: (1) For detailed drawing and dimension table, please see end of data

sheet, or Appendix D of Burr-Brown IC Data Book.

ORDERING INFORMATION

MINIMUM

SIGNAL-TO-

MAXIMUM

LINEARITY

ERROR (LSB)

(NOISE +

DISTORTION)

RATIO (dB)

SPECIFICATION

TEMPERATURE

RANGE

PRODUCT

PACKAGE

ADS7820P

ADS7820PB

ADS7820U

ADS7820UB

±1.0

±0.5

±1.0

±0.5

70

72

70

72

–40°C to +85°C

Plastic DIP

SOIC

®

3

ADS7820

PIN CONFIGURATION

1

2

3

4

5

6

7

8

9

28

V_DIG

V_IN

AGND1

REF

27 V_ANA

26 BUSY

25 CS

CAP

AGND2

D11 (MSB)

D10

24 R/C

23 BYTE

22 DZ

ADS7820

D9

21 DZ

D8

20 DZ

D7 10

D6 11

19 DZ

18 D0 (LSB)

17 D1

D5 12

D4 13

16 D2

DGND 14

15 D3

PIN ASSIGNMENTS

PIN #

NAME

DESCRIPTION

1

2

3

V_IN

AGND1

REF

Analog Input. Full-scale input range is 0 to +5V.

Analog Ground. Used internally as ground reference point.

Reference Input/Output. Outputs internal reference of +2.5V nominal. Can also be driven by external system reference. In both

cases, connect to ground with a 2.2µF Tantalum capacitor.

4

CAP

Reference Buffer Capacitor. 2.2µF Tantalum to ground.

5

AGND2

Analog Ground.

6

D11 (MSB) Data Bit 11. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.

7

D10

D9

Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW.

8

Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW.

9

D8

Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW.

10

11

12

13

14

15

16

17

18

19

20

21

22

23

D7

Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW.

D6

Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW.

D5

Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW.

D4

Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW.

DGND

D3

Digital Ground.

Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW.

D2

Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW.

D1

Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW.

D0 (LSB)

DZ

Data Bit 0. Lease Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.

Data Zero. LOW when CS LOW and R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.

DZ

BYTE

Byte Select. With BYTE LOW, data will be output as indicated above, causing pin 6 (D11) to output the MSB, and pin 18 (D0) to

output the LSB. Pins 19 to 22 will output LOWs. With BYTE HIGH, the top and bottom 8 bits of data will be switched, so that pin 6

outputs data bit 3, pin 9 outputs data bit 0 (LSB), pin 10 to 13 output LOWs, pin 15 outputs data bit 11 (MSB) and pin 22 outputs

data bit 4.

24

25

26

R/C

CS

Read/Convert input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a conversion.

With CS LOW, a rising edge on R/C enables the output data bits.

Chip Select. Internally OR’d with R/C. With R/C LOW, a falling edge on CS will initiate a conversion. With R/C HIGH, a falling edge

on CS will enable the output data bits.

BUSY

Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the data is latched into the

output register. With CS LOW and R/C HIGH, output data will be valid when BUSY rises, so that the rising edge can be used to

latch the data. CS or R/C must be high when BUSY rises, or another conversion will start, without time for signal acquisition.

27

28

V_ANA

Analog Supply Input. Nominally +5V. Connect directly to pin 28. Decouple to ground with 0.1µF ceramic and 10µF Tantalum

capacitors.

V_DIG

Digital Supply Input. Nominally +5V. Connect directly to pin 27. Must be ≤ V_ANA.

®

4

ADS7820

TYPICAL PERFORMANCE CURVES

At T_A= –40°C to +85°C, f_S= 100kHz, V_DIG= V_ANA= +5V, using internal reference, unless otherwise specified.

INTERNAL REFERENCE VOLTAGE vs TEMPERATURE

CONVERSION TIME vs TEMPERATURE

2.52

2.515

2.51

6.2

6.1

6

2.505

2.5

5.9

5.8

5.7

5.6

5.5

5.4

2.495

2.49

2.485

2.48

–40

–15

10

35

60

85

–40

–15

10

35

60

85

Temperature (°C)

ADS7820 AT +25°C

Min/Max INL Errors

–0.051 at 03962

0.086 at 02048

Min/Max DNL Errors

–0.073 at 00512

0.087 at 02047

0.2

+0.1

0

0.2

+0.1

0

–0.1

–0.2

–0.1

–0.2

0

512 1024 1536 2048 2560 3072 3584 4096

Decimal Code

0

512 1024 1536 2048 2560 3072 3584 4096

Decimal Code

®

5

ADS7820

CS and R/C are internally OR’d and level triggered. There

is not a requirement which input goes LOW first when

initiating a conversion. If, however, it is critical that CS or

R/C initiates conversion ‘n’, be sure the less critical input is

LOW at least 10ns prior to the initiating input.

BASIC OPERATION

Figure 1 shows a basic circuit to operate the ADS7820 with

a full parallel data output. Taking R/C (pin 24) LOW for a

minimum of 40ns (5.4µs max) will initiate a conversion.

BUSY (pin 26) will go LOW and stay LOW until the

conversion is completed and the output registers are up-

dated. Data will be output in Straight Binary with the MSB

on pin 6. BUSY going HIGH can be used to latch the data.

All convert commands will be ignored while BUSY is

LOW.

To reduce the number of control pins, CS can be tied LOW

using R/C to control the read and convert modes. However,

the output will become active whenever R/C goes HIGH.

Refer to the Reading Data section.

The ADS7820 will begin tracking the input signal at the end

of the conversion. Allowing 10µs between convert com-

mands assures accurate acquisition of a new signal.

CS

1

R/C BUSY OPERATION

X

0

X

1

None. Databus is in Hi-Z state.

↓

Initiates conversion “n”. Databus remains

in Hi-Z state.

0

↓

0

↓

1

↑

0

1

↑

1

0

↑

Initiates conversion “n”. Databus enters Hi-Z

state.

STARTING A CONVERSION

Conversion “n” completed. Valid data from

conversion “n” on the databus.

The combination of CS (pin 25) and R/C (pin 24) LOW for

a minimum of 40ns immediately puts the sample/hold of the

ADS7820 in the hold state and starts conversion ‘n’. BUSY

(pin 26) will go LOW and stay LOW until conversion ‘n’ is

completed and the internal output register has been updated.

All new convert commands during BUSY LOW will be

ignored. CS and/or R/C must go HIGH before BUSY goes

HIGH or a new conversion will be initiated without suffi-

cient time to acquire a new signal.

Enables databus with valid data from

conversion “n”.

Enables databus with valid data from

conversion “n-1”⁽¹⁾. Conversion n in process.

Enables databus with valid data from

conversion “n-1”⁽¹⁾. Conversion “n” in process.

New conversion initiated without acquisition

of a new signal. Data will be invalid. CS and/or

R/C must be HIGH when BUSY goes HIGH.

The ADS7820 will begin tracking the input signal at the end

of the conversion. Allowing 10µs between convert com-

mands assures accurate acquisition of a new signal. Refer to

Table I for a summary of CS, R/C, and BUSY states and

Figures 3 through 5 for timing diagrams.

X

0

New convert commands ignored. Conversion

“n” in process.

NOTE: (1) See Figures 2 and 3 for constraints on data valid from

conversion “n-1”.

Table I. Control Line Functions for “Read” and “Convert”.

0 to +5V

1

2

28

+5V

27

26

25

24

23

22

21

20

19

18

17

16

15

+

0.1µF

10µF

2.2µF

+

3

4

2.2µF

Convert Pulse

5

B11 (MSB)

6

B10

B9

B8

B7

B6

B5

B4

LOW

7

40ns min

ADS7820

5.4µs max

LOW

B0 (LSB)

B1

8

9

10

11

12

13

14

B2

B3

FIGURE 1. Basic Operation (Byte Low).

®

6

ADS7820

PARALLEL OUTPUT (During a Conversion)

READING DATA

After conversion ‘n’ has been initiated, valid data from

conversion ‘n-1’ can be read and will be valid up to 16µs

after the start of conversion ‘n’. Do not attempt to read data

from 16µs after the start of conversion ‘n’ until BUSY (pin

26) goes HIGH; this may result in reading invalid data.

Refer to Table III and Figures 3 and 5 for timing specifica-

tions.

The ADS7820 outputs full or byte-reading parallel data in

Straight Binary data output format. The parallel output will

be active when R/C (pin 24) is HIGH and CS (pin 25) is

LOW. Any other combination of CS and R/C will tri-state

the parallel output. Valid conversion data can be read in a

full parallel, 12-bit word or two 8-bit bytes on pins 6-13 and

pins 15-22. BYTE (pin 23) can be toggled to read both bytes

within one conversion cycle. Refer to Table II for ideal

output codes and Figure 2 for bit locations relative to the

state of BYTE.

Note! For the best possible performance, data should not be

read during a conversion. The switching noise of the asyn-

chronous data transfer can cause digital feedthrough degrad-

ing the converter’s performance.

The number of control lines can be reduced by tieing CS

LOW while using R/C to initiate conversions and activate

the output mode of the converter. See Figure 3.

DIGITAL OUTPUT

STRAIGHT BINARY

DESCRIPTION

ANALOG INPUT

0 to +5V

BINARY CODE

HEX CODE

Full Scale Range

Least Significant

Bit (LSB)

1.22mV

SYMBOL

DESCRIPTION

Convert Pulse Width

MIN TYP MAX UNITS

t₁

t₂

40

5400

8

ns

Full Scale

Midscale

4.99878V

2.5V

1111 1111 1111

1000 0000 0000

0111 1111 1111

FFF

800

7FF

Data Valid Delay after R/C LOW

µs

t₃

t₄

BUSY Delay from R/C LOW

BUSY LOW

65

8

ns

µs

One LSB below

Midscale

2.49878V

t₅

BUSY Delay after

End of Conversion

220

ns

Zero Scale

0V

0000 0000 0000

0

Table II. Ideal Input Voltages and Output Codes.

t₆

t₇

Aperture Delay

Conversion Time

40

ns

µs

ns

µs

7.6

8

2

t₈

Acquisition Time

PARALLEL OUTPUT (After a Conversion)

t₉

Bus Relinquish Time

BUSY Delay after Data Valid

10

35

83

After conversion ‘n’ is completed and the output registers

have been updated, BUSY (pin 26) will go HIGH. Valid data

from conversion ‘n’ will be available on D11-D0 (pin 6-13

and 15-18 when BYTE is LOW). BUSY going HIGH can be

used to latch the data. Refer to Table III and Figures 3 and

5 for timing specifications.

t₁₀

t₁₁

50 200

7.4

Previous Data Valid

after R/C LOW

t

₇+ t₆

Throughput Time

R/C to CS Setup Time

Time Between Conversions

9

10

83

µs

ns

µs

ns

t₁₂

10

t₁₃

10

t₁₄

Bus Access Time

and BYTE Delay

10

TABLE III. Conversion Timing.

BYTE LOW

BYTE HIGH

+5V

6

7

23

22

21

20

19

18

17

16

15

6

7

23

22

21

20

19

18

17

16

15

Bit 11 (MSB)

Bit 10

Bit 9

Bit 3

Bit 2

LOW

Bit 0 (LSB)

Bit 1

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

Bit 9

ADS7820

8

Bit 1

9

Bit 8

Bit 0 (LSB)

LOW

10

11

12

13

14

10

11

12

13

14

Bit 7

Bit 6

LOW

Bit 5

LOW

Bit 4

Bit 2

LOW

Bit 10

Bit 11

Bit 3

FIGURE 2. Bit Locations Relative to State of BYTE (pin 23).

®

7

ADS7820

t₁

R/C

BUSY

t₁₃

t₂

t₄

t₃

t₆

t₅

Convert

t₇

Acquire

t₈

Convert

Acquire

MODE

Hi-Z

Not Valid

Data Valid

t₁₀

Hi-Z

Data Valid

DATA BUS

t₉

t₁₁

FIGURE 3. Conversion Timing with Outputs Enabled after Conversion (CS Tied LOW.)

t₁₂

R/C

CS

t₁

t₃

t₄

BUSY

MODE

t₆

Convert

t₇

Acquire

Hi-Z State

Data Valid

t₉

Hi-Z State

DATA BUS

t₁₄

FIGURE 4. Using CS to Control Conversion and Read Timing.

t₁₂

R/C

CS

BYTE

Pins 6 - 13

Hi-Z

High Byte

t₁₄

Low Byte

Hi-Z

t₁₄

High Byte

t₉

Pins 15 - 22

Low Byte

Hi-Z

FIGURE 5. Using CS and BYTE to Control Data Bus.

®

8

ADS7820

INPUT RANGE

REF

The ADS7820 offers a standard 0V to 5V input range.

Figure 6 shows the required circuit connections for the

ADS7820 with and without the gain adjustment hardware.

Adjustments for offset and gain are described in the calibra-

tion section of this data sheet.

REF (pin 3) is an input for an external reference or the output

for the internal 2.5V reference. A 2.2µF capacitor should be

connected as close to the REF pin as possible. The capacitor

and the output resistance of REF create a low pass filter to

bandlimit noise on the reference. Using a smaller value

capacitor will introduce more noise to the reference degrad-

ing the SNR and SINAD. The REF pin should not be used

to drive external AC or DC loads.

CALIBRATION

The range for the external reference is 2.3V to 2.7V and

determines the actual LSB size. Increasing the reference

voltage will increase the full scale range and the LSB size of

the converter which can improve the SNR.

The ADS7820 can be trimmed in hardware or software. There

is no external, offset adjustment. If offset adjustment is re-

quired, an op amp featuring an offset trim pin should be used

to drive the ADS7820. The offset should be trimmed before

the gain since the offset directly affects the gain. To achieve

optimum performance, several iterations may be required.

CAP

CAP (pin 4) is the output of the internal reference buffer. A

2.2µF capacitor should be placed as close to the CAP pin as

possible to provide optimum switching currents for the

CDAC throughout the conversion cycle and compensation

for the output of the internal buffer. Using a capacitor any

smaller than 1µF can cause the output buffer to oscillate and

may not have sufficient charge for the CDAC. Capacitor

values larger than 2.2µF will have little affect on improving

performance.

GAIN ADJUSTMENT

To calibrate the gain of the ADS7820, a 576kΩ resistor must

be tied between the REF pin and a 5V potentiometer (see

Figure 6b). The calibration range is ±15mV for the gain.

REFERENCE

The ADS7820 can operate with its internal 2.5V reference or

an external reference. By applying an external reference to

pin 3, the internal reference can be bypassed. The reference

voltage at REF is buffered internally with the output on CAP

(pin 4).

The output of the buffer is capable of driving up to 2mA of

current to a DC load. DC loads requiring more than 2mA of

current from the CAP pin will begin to degrade the linearity

of the ADS7820. Using an external buffer will allow the

internal reference to be used for larger DC loads and AC

loads. Do not attempt to directly drive an AC load with the

output voltage on CAP. This will cause performance degra-

dation of the converter.

The internal reference has an 8 ppm/°C drift (typical) and

accounts for approximately 20% of the full scale error

(FSE = ±0.5% for low grade, ±0.25% for high grade).

a) WITHOUT EXTERNAL GAIN ADJUSTMENT

b) WITH EXTERNAL GAIN ADJUSTMENT

1

0 to +5V

V_IN

0 to +5V

2.2µF

V_IN

2

3

4

5

2

3

4

5

AGND1

REF

AGND1

REF

2.2µF

576kΩ

2.2µF

+5V

+

50kΩ

CAP

Gain

2.2µF

AGND2

FIGURE 6. Circuit Diagram With and Without External Gain Adjustment.

®

9

ADS7820

SIGNAL CONDITIONING

LAYOUT

The FET switches used for the sample hold on many CMOS

A/D converters release a significant amount of charge injec-

tion which can cause the driving op amp to oscillate. The

FET switch on the ADS7820, compared to the FET switches

on other CMOS A/D converters, releases 5%-10% of the

charge. There is also a resistive front end which attenuates

any charge which is released. The end result is a minimal

requirement for the anti-alias filter on the front end. Any op

amp sufficient for the signal in an application will be

sufficient to drive the ADS7820.

POWER

For optimum performance, tie the analog and digital power

pins to the same +5V power supply and tie the analog and

digital grounds together. As noted in the electrical specifica-

tions, the ADS7820 uses 90% of its power for the analog

circuitry. The ADS7820 should be considered as an analog

component.

The +5V power for the A/D should be separate from the +5V

used for the system’s digital logic. Connecting V_DIG(pin 28)

directly to a digital supply can reduce converter performance

due to switching noise from the digital logic. For best

performance, the +5V supply can be produced from what-

ever analog supply is used for the rest of the analog signal

conditioning. If +12V or +15V supplies are present, a simple

+5V regulator can be used. Although it is not suggested, if

the digital supply must be used to power the converter, be

sure to properly filter the supply. Either using a filtered

digital supply or a regulated analog supply, both V_DIGand

V_ANAshould be tied to the same +5V source.

INTERMEDIATE LATCHES

The ADS7820 does have tri-state outputs for the parallel

port, but intermediate latches should be used if the bus will

be active during conversions. If the bus is not active during

conversion, the tri-state outputs can be used to isolate the

A/D from other peripherals on the same bus. Tri-state

outputs can also be used when the A/D is the only peripheral

on the data bus.

Intermediate latches are beneficial on any monolithic A/D

converter. The ADS7820 has an internal LSB size of 610µV.

Transients from fast switching signals on the parallel port,

even when the A/D is tri-stated, can be coupled through the

substrate to the analog circuitry causing degradation of

converter performance. The effects of this phenomenon will

be more obvious when using the pin-compatible ADS7821

or any of the other 16-bit converters in the ADS Family. This

is due to the smaller internal LSB size of 38µV.

GROUNDING

Three ground pins are present on the ADS7820. DGND is

the digital supply ground. AGND2 is the analog supply

ground. AGND1 is the ground which all analog signals

internal to the A/D are referenced. AGND1 is more suscep-

tible to current induced voltage drops and must have the path

of least resistance back to the power supply.

All the ground pins of the A/D should be tied to the analog

ground plane, separated from the system’s digital logic

ground, to achieve optimum performance. Both analog and

digital ground planes should be tied to the “system” ground

as near to the power supplies as possible. This helps to

prevent dynamic digital ground currents from modulating

the analog ground through a common impedance to power

ground.

®

10

ADS7820

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.


型号：	ADS7820U
厂家：	TEXAS INSTRUMENTS
描述：	12-Bit 10us Sampling CMOS Analog-To-Digital Converter 28-SOIC -40 to 85 光电二极管转换器
文件：	总11页 (文件大小：198K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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