ADS7822EB/2K5 [TI]
12-Bit, High-Speed, 2.7V microPower Sampling ANALOG-TO-DIGITAL CONVERTER; 12位，高速， 2.7V微功耗采样模拟数字转换器
| 型号： | ADS7822EB/2K5 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-Bit, High-Speed, 2.7V microPower Sampling ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总20页 (文件大小：430K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS7822
A
D
S
7
O
8
2
2
A
D
S
7
8
2
2
SBAS062A – JANUARY 1996 – REVISED MARCH 2005
12-Bit, High-Speed, 2.7V microPower Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
● 75kHz SAMPLING RATE
The ADS7822 is a 12-bit sampling analog-to-digital (A/D)
converter with ensured specifications over a 2.7V to 5.25V
supply range. It requires very little power even when oper-
ating at the full 75kHz rate. At lower conversion rates, the
high speed of the device enables it to spend most of its time
in the power-down mode—the power dissipation is less than
60µW at 7.5kHz.
● MICRO POWER:
0.54mW at 75kHz
0.06mW at 7.5kHz
● POWER DOWN: 3µA max
● MINI-DIP-8, SOIC-8, AND MSOP-8
● PSEUDO-DIFFERENTIAL INPUT
● SERIAL INTERFACE
The ADS7822 also features operation from 2.0V to 5V, a
synchronous serial interface, and a pseudo-differential input.
The reference voltage can be set to any level within the
range of 50mV to VCC
.
APPLICATIONS
● BATTERY-OPERATED SYSTEMS
● REMOTE DATA ACQUISITION
● ISOLATED DATA ACQUISITION
Ultra low power and small size make the ADS7822 ideal for
battery-operated systems. It is also a perfect fit for remote
data acquisition modules, simultaneous multi-channel sys-
tems, and isolated data acquisition. The ADS7822 is avail-
able in a plastic mini-DIP-8, an SOIC-8, or an MSOP-8
package.
● SIMULTANEOUS SAMPLING,
MULTI-CHANNEL SYSTEMS
Control
SAR
VREF
DOUT
+In
CDAC
Serial
Interface
DCLOCK
CS/SHDN
–In
Comparator
S/H Amp
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1996-2005, Texas Instruments Incorporated
www.ti.com
SPECIFICATIONS: +VCC = +2.7V
At –40°C to +85°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 75kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.
ADS7822
TYP
ADS7822B
TYP
ADS7822C
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
ANALOG INPUT
Full-Scale Input Span
Absolute Input Range
+In – (–In)
+In
0
–0.2
–0.2
VREF
VCC +0.2
+1.0
0
–0.2
–0.2
VREF
VCC +0.2 –0.2
+1.0
0
VREF
VCC +0.2
+1.0
V
V
V
–In
–0.2
Capacitance
Leakage Current
25
±1
25
±1
25
±1
pF
µA
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Noise
Power Supply Rejection
12
12
12
Bits
Bits
11
–2
–2
–3
–3
12
–1
–1
–3
–3
11
–0.75
–0.75
–1
±0.5
±0.5
+2
+2
+3
+3
±0.5
±0.5
+1
+1
+3
+3
±0.25
±0.25
+0.75
+0.75
+1
LSB(1)
LSB
LSB
LSB
µVrms
dB
–1
+1
33
82
33
82
33
82
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
12
75
12
75
12
75
Clk Cycles
Clk Cycles
kHz
1.5
1.5
1.5
Throughput Rate
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion
SINAD
V
V
V
IN = 2.5Vp-p at 1kHz
IN = 2.5Vp-p at 1kHz
IN = 2.5Vp-p at 1kHz
–82
71
86
–82
71
86
–82
71
86
dB
dB
dB
Spurious Free Dynamic Range
REFERENCE INPUT
Voltage Range
Resistance
0.05
VCC
0.05
VCC
0.05
VCC
V
CS = GND, fSAMPLE = 0Hz
CS = VCC
5
5
8
5
5
8
5
5
8
GΩ
GΩ
µA
µA
µA
Current Drain
At Code 710h
fSAMPLE = 7.5kHz
CS = VCC
40
3
40
3
40
3
0.8
0.001
0.8
0.001
0.8
0.001
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels:
VIH
VIL
VOH
CMOS
CMOS
CMOS
IIH = +5µA
IIL = +5µA
IOH = –250µA
IOL = 250µA
2.0
–0.3
2.1
5.5
0.8
2.0
–0.3
2.1
5.5
0.8
2.0
–0.3
2.1
5.5
0.8
V
V
V
V
VOL
0.4
0.4
0.4
Data Format
Straight Binary
Straight Binary
Straight Binary
POWER SUPPLY REQUIREMENTS
VCC
Specified Performance
See Notes 2 and 3
See Note 3
2.7
2.0
3.6
3.6
2.7
5.25
325
2.7
2.0
3.6
3.6
2.7
5.25
325
2.7
2.0
3.6
3.6
2.7
5.25
325
V
V
V
µA
µA
µA
Quiescent Current
200
20
180
200
20
180
200
20
180
fSAMPLE = 7.5kHz(4,5)
fSAMPLE = 75kHz(5)
Power Down
CS = VCC
3
3
3
µA
TEMPERATURE RANGE
Specified Performance
–40
+85
–40
+85
–40
+85
°C
NOTES: (1) LSB means Least Significant Bit. With VREF equal to +2.5V, one LSB is 0.61mV.
(2) The maximum clock rate of the ADS7822 is less than 1.2MHz in this power supply range.
(3) See the Typical Performance Curves for more information.
(4) fCLK = 1.2MHz, CS = VCC for 145 clock cycles out of every 160.
(5) See the Power Dissipation section for more information regarding lower sample rates.
ADS7822
2
SBAS062A
www.ti.com
SPECIFICATIONS: +VCC = +5V
At –40°C to +85°C, +VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.
ADS7822
ADS7822B
TYP
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
ANALOG INPUT
Full-Scale Input Span
Absolute Input Range
+In – (–In)
+In
0
–0.2
–0.2
VREF
VCC +0.2
+1.0
0
–0.2
–0.2
VREF
VCC +0.2
+1.0
V
V
V
–In
Capacitance
Leakage Current
25
±1
25
±1
pF
µA
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Noise
Power Supply Rejection
12
12
Bits
Bits
11
–2
12
–1
–1
–3
–3
+2
+1
+1
+3
+3
LSB(1)
LSB
LSB
LSB
µVrms
dB
±0.8
±0.5
–3
–4
+3
+4
33
70
33
70
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
12
12
Clk Cycles
Clk Cycles
kHz
1.5
1.5
Throughput Rate
200
200
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion
SINAD
V
V
V
IN = 5Vp-p at 10kHz
IN = 5Vp-p at 10kHz
IN = 5Vp-p at 10kHz
–78
71
79
–78
71
79
dB
dB
dB
Spurious Free Dynamic Range
REFERENCE INPUT
Voltage Range
Resistance
0.05
VCC
0.05
VCC
V
CS = GND, fSAMPLE = 0Hz
CS = VCC
5
5
40
2.5
0.001
5
5
40
2.5
0.001
GΩ
GΩ
µA
µA
µA
Current Drain
At Code 710h
fSAMPLE = 12.5kHz
CS = VCC
100
3
100
3
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels:
VIH
VIL
VOH
CMOS
CMOS
IIH = +5µA
IIL = +5µA
IOH = –250µA
IOL = 250µA
3.0
–0.3
3.5
5.5
0.8
3.0
–0.3
3.5
5.5
0.8
V
V
V
V
VOL
0.4
0.4
Data Format
Straight Binary
320
Straight Binary
320
POWER SUPPLY REQUIREMENTS
VCC
Quiescent Current
Power Down
Specified Performance
fSAMPLE = 200kHz
CS = VCC
4.5
5.25
550
3
4.75
5.25
550
3
V
µA
µA
TEMPERATURE RANGE
Specified Performance
–40
+85
–40
+85
°C
NOTES: (1) LSB means Least Significant Bit. With VREF equal to +5V, one LSB is 1.22mV.
ADS7822
SBAS062A
3
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
VCC ....................................................................................................... +6V
Analog Input .............................................................. –0.3V to (VCC + 0.3V)
Logic Input ...............................................................................–0.3V to 6V
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +125°C
External Reference Voltage .............................................................. +5.5V
Top View
DIP, MSOP, SO
NOTE: (1) Stresses above these ratings may permanently damage the device.
VREF
+In
1
2
3
4
8
7
6
5
+VCC
DCLOCK
DOUT
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from per-
formance degradation to complete device failure. Texas
Instruments recommends that all integrated circuits be handled
and stored using appropriate ESD protection methods.
ADS7822
–In
GND
CS/SHDN
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
PIN ASSIGNMENTS
PIN
NAME
DESCRIPTION
1
2
3
4
5
6
VREF
+In
Reference Input.
Non Inverting Input.
–In
Inverting Input. Connect to ground or to remote ground sense point.
Ground.
GND
CS/SHDN
DOUT
Chip Select when LOW, Shutdown Mode when HIGH.
The serial output data word is comprised of 12 bits of data. In operation the data is valid on the falling edge of DCLOCK. The
second clock pulse after the falling edge of CS enables the serial output. After one null bit the data is valid for the next 12 edges.
Data Clock synchronizes the serial data transfer and determines conversion speed.
7
8
DCLOCK
+VCC
Power Supply.
PACKAGE/ORDERING INFORMATION(1)
MAXIMUM
INTEGRAL
LINEARITY
ERROR
MAXIMUM
DIFFERENTIAL
LINEARITY
ERROR
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING(2)
ORDERING
NUMBER(3)
TRANSPORT
MEDIA
PRODUCT
(LSB)
(LSB)
PACKAGE
ADS7822E
ADS7822E
ADS7822EB
ADS7822EB
ADS7822EC
ADS7822EC
ADS7822P
ADS7822PB
ADS7822PC
ADS7822U
ADS7822U
ADS7822UB
ADS7822UB
ADS7822UC
ADS7822UC
±2
±2
MSOP-8
DGK
–40°C to +85°C
A22
"
A22
"
A22
"
ADS7822E/250
ADS7822E/2K5
ADS7822EB/250 Tape and Reel
ADS7822EB/2K5
ADS7822EC/250 Tape and Reel
ADS7822EC/2K5
ADS7822P
ADS7822PB
ADS7822PC
ADS7822U
ADS7822U/2K5
ADS7822UB
ADS7822UB/2K5 Tape and Reel
ADS7822UC Rails
ADS7822UC/2K5 Tape and Reel
Tape and Reel
"
±1
"
±0.75
"
±2
±1
±0.75
±2
"
±1
"
±0.75
"
"
±1
"
±0.75
"
±2
±1
±0.75
±2
"
±1
"
±0.75
"
"
"
"
"
MSOP-8
DGK
–40°C to +85°C
"
"
DGK
"
P
P
"
"
MSOP-8
–40°C to +85°C
"
"
"
Rails
Rails
Rails
Rails
Plastic DIP-8
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
"
ADS7822P
ADS7822PB
ADS7822PC
ADS7822U
"
ADS7822UB
"
ADS7822UC
"
Plastic DIP-8
Plastic DIP-8
SOIC-8
P
D
"
"
Tape and Reel
Rails
SOIC-8
D
"
–40°C to +85°C
"
–40°C to +85°C
"
"
SOIC-8
"
D
"
NOTES: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at
www.ti.com.
(2) Performance Grade information is marked on the reel.
(3) Models with a slash(/) are available only in tape and reel in quantities indicated (e.g. /250 indicates 250 units per reel, /2K5 indicates 2500
devices per reel). Ordering 2500 pieces of ”ADS7822E/2K5“ will get a single 2500-piece tape and reel.
ADS7822
4
SBAS062A
www.ti.com
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VCC = +2.7V, VREF = +2.5V, fSAMPLE = 75kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.
INTEGRAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
1.00
0.75
1.00
0.75
0.50
0.50
0.25
0.25
0.00
0.00
–0.25
–0.50
–0.75
–1.00
–0.25
–0.50
–0.75
–1.00
0
2048
Code
4095
0
2048
Code
4095
POWER DOWN SUPPLY CURRENT
vs TEMPERATURE
SUPPLY CURRENT vs TEMPERATURE
350
300
250
200
150
100
50
120
100
80
60
40
20
0
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
QUIESCENT CURRENT vs VCC
MAXIMUM SAMPLE RATE vs VCC
400
350
300
250
200
150
100
1000
100
10
1
1
2
3
4
5
1
2
3
4
5
VCC (V)
VCC (V)
ADS7822
SBAS062A
5
www.ti.com
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VCC = +2.7V, VREF = +2.5V, fSAMPLE = 75kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.
CHANGE IN OFFSET vs TEMPERATURE
CHANGE IN OFFSET vs REFERENCE VOLTAGE
0.6
0.4
1.2
1.0
VCC = 5V
0.8
0.6
0.2
0.4
0
0.2
0.0
–0.2
–0.4
–0.6
–0.2
–0.4
–0.6
–0.8
–50
–25
0
25
50
75
100
100
10
1
2
3
4
5
Temperature (°C)
Reference Voltage (V)
CHANGE IN GAIN vs REFERENCE VOLTAGE
VCC = 5V
CHANGE IN GAIN vs TEMPERATURE
2.5
2.0
0.15
0.1
1.5
0.05
0
1.0
0.5
0.0
–0.05
–0.1
–0.15
–0.5
–1.0
–1.5
–50
–25
0
25
50
75
1
2
3
4
5
Reference Voltage (V)
Temperature (°C)
EFFECTIVE NUMBER OF BITS
vs REFERENCE VOLTAGE
PEAK-TO-PEAK NOISE vs REFERENCE VOLTAGE
VCC = 5V
12
11.75
11.5
11.25
11
10
9
8
7
6
5
4
3
2
1
0
VCC = 5V
10.75
10.5
10.25
10
0.1
1
10
0.1
1
Reference Voltage (V)
Reference Voltage (V)
ADS7822
6
SBAS062A
www.ti.com
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VCC = +2.7V, VREF = +2.5V, fSAMPLE = 75kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.
SPURIOUS FREE DYNAMIC RANGE and
SIGNAL-TO-NOISE RATIO vs FREQUENCY
TOTAL HARMONIC DISTORTION vs FREQUENCY
100
90
80
70
60
50
40
30
20
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Spurious Free Dynamic Range
Signal-to-Noise Ratio
1
10
100
1
10
100
Frequency (kHz)
Frequency (kHz)
SIGNAL-TO-(NOISE + DISTORTION) vs FREQUENCY
SIGNAL-TO-(NOISE + DISTORTION) vs INPUT LEVEL
100
90
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
1
10
100
–40
–35
–30
–25
–20
–15
–10
–5
0
Frequency (kHz)
Input Level (dB)
REFERENCE CURRENT vs TEMPERATURE
(Code = 710h)
REFERENCE CURRENT vs SAMPLE RATE
14
12
10
8
14
12
10
8
6
6
4
4
2
0
2
0
15
30
45
60
75
–50
–25
0
25
50
75
100
Sample Rate (kHz)
Temperature (°C)
ADS7822
SBAS062A
7
www.ti.com
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VCC = +2.7V, VREF = +2.5V, fSAMPLE = 75kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.
POWER SUPPLY REJECTION vs RIPPLE FREQUENCY
POWER SUPPLY REJECTION vs RIPPLE FREQUENCY
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
VCC = 5V
Ripple = 500mVPP
VIN = 2.5VDC
VCC = 2.7V
Ripple = 500mVPP
VIN = 1.25VDC
VREF = 2.5V
V
REF = 5V
PSR (dB) = 20log(500mV/∆VO)
where ∆VO = change in digital result
PSR (dB) = 20log(500mV/∆VO)
where ∆VO = change in digital result
1k
10k
100k
1M
10M
10
1
1k
10k
100k
1M
10M
Ripple Frequency (Hz)
Ripple Frequency (Hz)
CHANGE IN INTEGRAL LINEARITY AND DIFFERENTIAL
LINEARITY vs REFERENCE VOLTAGE
0.20
0.15
0.10
0.05
0.00
–0.05
VCC = 5V
Change in Integral
Linearity (LSB)
Change in Differential
Linearity (LSB)
–0.10
1
2
3
4
5
Reference Voltage (V)
ADS7822
8
SBAS062A
www.ti.com
ANALOG INPUT
THEORY OF OPERATION
The +In and –In input pins allow for a pseudo-differential
input signal. Unlike some converters of this type, the –In
input is not re-sampled later in the conversion cycle. When
the converter goes into the hold mode, the voltage difference
between +In and –In is captured on the internal capacitor
array.
The ADS7822 is a classic successive approximation register
(SAR) analog-to-digital (A/D) converter. The architecture is
based on capacitive redistribution which inherently includes
a sample/hold function. The converter is fabricated on a 0.6µ
CMOS process. The architecture and process allow the
ADS7822 to acquire and convert an analog signal at up to
75,000 conversions per second while consuming very little
power.
The range of the –In input is limited to –0.2V to +1V.
Because of this, the differential input can be used to reject
only small signals that are common to both inputs. Thus, the
–In input is best used to sense a remote signal ground that
may move slightly with respect to the local ground potential.
The ADS7822 requires an external reference, an external
clock, and a single power source (VCC). The external refer-
ence can be any voltage between 50mV and VCC. The value
of the reference voltage directly sets the range of the analog
input. The reference input current depends on the conversion
rate of the ADS7822.
The input current on the analog inputs depends on a number
of factors: sample rate, input voltage, source impedance, and
power-down mode. Essentially, the current into the ADS7822
charges the internal capacitor array during the sample period.
After this capacitance has been fully charged, there is no
further input current. The source of the analog input voltage
must be able to charge the input capacitance (25pF) to a
12-bit settling level within 1.5 clock cycles. When the
converter goes into the hold mode or while it is in the power
down mode, the input impedance is greater than 1GΩ.
The external clock can vary between 10kHz (625Hz through-
put) and 1.2MHz (75kHz throughput). The duty cycle of the
clock is essentially unimportant as long as the minimum high
and low times are at least 400ns (VCC = 2.7V or greater).
The minimum clock frequency is set by the leakage on the
capacitors internal to the ADS7822.
The analog input is provided to two input pins: +In and –In.
When a conversion is initiated, the differential input on these
pins is sampled on the internal capacitor array. While a
conversion is in progress, both inputs are disconnected from
any internal function.
Care must be taken regarding the absolute analog input
voltage. To maintain the linearity of the converter, the –In
input should not drop below GND – 200mV or exceed
GND + 1V. The +In input should always remain within the
range of GND – 200mV to VCC + 200mV. Outside of these
ranges, the converter’s linearity may not meet specifications.
The digital result of the conversion is clocked out by the
DCLOCK input and is provided serially, most significant bit
first, on the DOUT pin. The digital data that is provided on the
DOUT pin is for the conversion currently in progress—there
is no pipeline delay. It is possible to continue to clock the
ADS7822 after the conversion is complete and to obtain the
serial data least significant bit first. See the digital timing
section for more information.
ADS7822
SBAS062A
9
www.ti.com
With lower reference voltages, extra care should be taken to
provide a clean layout including adequate bypassing, a clean
power supply, a low-noise reference, and a low-noise input
signal. Because the LSB size is lower, the converter will also
be more sensitive to external sources of error such as nearby
digital signals and electromagnetic interference.
REFERENCE INPUT
The external reference sets the analog input range. The
ADS7822 will operate with a reference in the range of 50mV
to VCC. There are several important implications of this.
As the reference voltage is reduced, the analog voltage
weight of each digital output code is reduced. This is often
referred to as the LSB (least significant bit) size and is equal
to the reference voltage divided by 4096. This means that any
offset or gain error inherent in the A/D converter will appear
to increase, in terms of LSB size, as the reference voltage is
reduced.
DIGITAL INTERFACE
SIGNAL LEVELS
The digital inputs of the ADS7822 can accommodate logic
levels up to 6V regardless of the value of VCC. Thus, the
ADS7822 can be powered at 3V and still accept inputs from
logic powered at 5V.
The noise inherent in the converter will also appear to
increase with lower LSB size. With a 2.5V reference, the
internal noise of the converter typically contributes only 0.32
LSB peak-to-peak of potential error to the output code. When
the external reference is 50mV, the potential error contribu-
tion from the internal noise will be 50 times larger—16
LSBs. The errors due to the internal noise are gaussian in
nature and can be reduced by averaging consecutive conver-
sion results.
The CMOS digital output (DOUT) will swing 0V to VCC. If
VCC is 3V and this output is connected to a 5V CMOS logic
input, then that IC may require more supply current than
normal and may have a slightly longer propagation delay.
SERIAL INTERFACE
The ADS7822 communicates with microprocessors and other
digital systems via a synchronous 3-wire serial interface as
shown in Figure 1 and Table I. The DCLOCK signal syn-
chronizes the data transfer with each bit being transmitted on
the falling edge of DCLOCK. Most receiving systems will
capture the bitstream on the rising edge of DCLOCK. How-
ever, if the minimum hold time for DOUT is acceptable, the
system can use the falling edge of DCLOCK to capture each
bit.
For more information regarding noise, consult the typical
performance curves “Effective Number of Bits vs Reference
Voltage” and “Peak-to-Peak Noise vs Reference Voltage.”
Note that the effective number of bits (ENOB) figure is
calculated based on the converter’s signal-to-(noise + distor-
tion) ratio with a 1kHz, 0dB input signal. SINAD is related
to ENOB as follows
SINAD = 6.02 • ENOB + 1.76
tCYC
CS/SHDN
Power
Down
tSUCS
DCLOCK
tCSD
Null
Null
Bit
Hi-Z
Hi-Z
Bit
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0(1)
B11 B10 B9 B8
DOUT
(MSB)
tSMPL
tCONV
tDATA
Note: (1) After completing the data transfer, if further clocks are applied with CS
LOW, the A/D will output LSB-First data then followed with zeroes indefinitely.
tCYC
CS/SHDN
DCLOCK
DOUT
tSUCS
Power Down
tCSD
Null
Hi-Z
Hi-Z
Bit
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
(1)
(MSB)
tSMPL
tCONV
tDATA
Note: (1) After completing the data transfer, if further clocks are applied with CS
LOW, the A/D will output zeroes indefinitely.
tDATA: During this time, the bias current and the comparator power down and the reference input
becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes.
FIGURE 1. ADS7822 Basic Timing Diagrams.
ADS7822
10
SBAS062A
www.ti.com
periods, DOUT will output the conversion result, most signifi-
cant bit first. After the least significant bit (B0) has been
output, subsequent clocks will repeat the output data but in a
least significant bit first format.
SYMBOL
DESCRIPTION
MIN
TYP MAX
UNITS
tSMPL
tCONV
tCYC
Analog Input Sample Time
Conversion Time
1.5
2.0
Clk Cycles
Clk Cycles
kHz
12
75
0
Throughput Rate
tCSD
CS Falling to
DCLOCK LOW
ns
After the most significant bit (B11) has been repeated, DOUT
will tri-state. Subsequent clocks will have no effect on the
converter. A new conversion is initiated only when CS has
been taken HIGH and returned LOW.
tSUCS
thDO
tdDO
CS Falling to
DCLOCK Rising
30
15
ns
ns
ns
DCLOCK Falling to
Current DOUT Not Valid
DATA FORMAT
DCLOCK Falling to Next
DOUT Valid
130
200
The output data from the ADS7822 is in straight binary
format as shown in Table II. This table represents the ideal
output code for the given input voltage and does not include
the effects of offset, gain error, or noise.
tdis
ten
CS Rising to DOUT Tri-State
40
75
80
ns
ns
DCLOCK Falling to DOUT
Enabled
175
tf
tr
DOUT Fall Time
DOUT Rise Time
90
200
200
ns
ns
110
DESCRIPTION
ANALOG VALUE
VREF
TABLE I. Timing Specifications (VCC = 2.7V and above,
DIGITAL OUTPUT
STRAIGHT BINARY
Full Scale Range
–40°C to +85°C.
Least Significant
Bit (LSB)
VREF/4096
BINARY CODE
HEX CODE
FFF
A falling CS signal initiates the conversion and data transfer.
The first 1.5 to 2.0 clock periods of the conversion cycle are
used to sample the input signal. After the second falling
DCLOCK edge, DOUT is enabled and will output a LOW
value for one clock period. For the next 12 DCLOCK
Full Scale
Midscale
VREF –1 LSB
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
VREF/2
800
Midscale – 1 LSB
Zero
V
REF/2 – 1 LSB
7FF
0V
000
TABLE II. Ideal Input Voltages and Output Codes.
1.4V
VOH
3kΩ
DOUT
VOL
DOUT
Test Point
tr
tf
100pF
CLOAD
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
Load Circuit for tdDO, tr, and tf
Test Point
DCLOCK
VIL
VCC
tdis Waveform 2, ten
3kΩ
DOUT
tdDO
VOH
VOL
tdis Waveform 1
100pF
CLOAD
DOUT
thDO
Load Circuit for tdis and ten
Voltage Waveforms for DOUT Delay Times, tdDO
VIH
CS/SHDN
CS/SHDN
DCLOCK
1
2
DOUT
Waveform 1(1)
90%
10%
tdis
VOL
DOUT
B11
DOUT
Waveform 2(2)
ten
Voltage Waveforms for ten
Voltage Waveforms for tdis
NOTES: (1) Waveform 1 is for an output with internal conditions such that the output
is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with
internal conditions such that the output is LOW unless disabled by the output control.
FIGURE 2. Timing Diagrams and Test Circuits for the Parameters in Table I.
ADS7822
SBAS062A
11
www.ti.com
POWER DISSIPATION
1000
100
10
TA = 25°C
fCLK = 1.2MHz
The architecture of the converter, the semiconductor fabrica-
tion process, and a careful design allow the ADS7822 to
convert at up to a 75kHz rate while requiring very little
power. Still, for the absolute lowest power dissipation, there
are several things to keep in mind.
VCC = 5.0V
VREF = 5.0V
VCC = 2.7V
VREF = 2.5V
The power dissipation of the ADS7822 scales directly with
conversion rate. So, the first step to achieving the lowest
power dissipation is to find the lowest conversion rate that
will satisfy the requirements of the system.
1
In addition, the ADS7822 is in power-down mode under two
conditions: when the conversion is complete and whenever
CS is HIGH (see Figure 1). Ideally, each conversion should
occur as quickly as possible, preferably at a 1.2MHz clock
rate. This way, the converter spends the longest possible time
in the power-down mode. This is very important as the
converter not only uses power on each DCLOCK transition
(as is typical for digital CMOS components) but also uses
some current for the analog circuitry, such as the comparator.
The analog section dissipates power continuously, until the
power-down mode is entered.
0.1
1
10
100
Sample Rate (kHz)
FIGURE 3. Maintaining fCLK at the Highest Possible Rate
Allows Supply Current to Drop Linearly with
Sample Rate.
1000
100
Figure 3 shows the current consumption of the ADS7822
versus sample rate. For this graph, the converter is clocked at
1.2MHz regardless of the sample rate—CS is HIGH for the
remaining sample period. Figure 4 also show current con-
sumption versus sample rate. However, in this case, the
DCLOCK period is 1/16th of the sample period—CS is
HIGH for one DCLOCK cycle out of every 16.
10
TA = 25°C
V
V
CC = 2.7V
REF = 2.5V
f
CLK = 16 • fSAMPLE
There is an important distinction between the power-down
mode that is entered after a conversion is complete and the
full power-down mode that is enabled when CS is HIGH.
While both shutdown the analog section, the digital section
is completely shutdown only when CS is HIGH. Thus, if CS
is left LOW at the end of a conversion and the converter is
continually clocked, the power consumption will not be as
low as when CS is HIGH. See Figure 5 for more information.
1
0.1
1
10
100
Sample Rate (kHz)
FIGURE 4. Scaling fCLK Reduces Supply Current Only
Slightly with Sample Rate.
10.0
Power dissipation can also be reduced by lowering the power
supply voltage and the reference voltage. The ADS7822 will
operate over a VCC range of 2.0V to 5.25V. However, at
voltages below 2.7V, the converter will not run at a 75kHz
sample rate. See the typical performance curves for more
information regarding power supply voltage and maximum
sample rate.
TA = 25°C
V
V
CC = 2.7V
REF = 2.5V
8.0
6.0
4.0
2.0
0.0
f
CLK = 16 • fSAMPLE
CS LOW (GND)
SHORT CYCLING
CS HIGH (VCC
)
Another way of saving power is to utilize the CS signal to
short-cycle the conversion. Because the ADS7822 places the
latest data bit on the DOUT line as it is generated, the
converter can easily be short-cycled. This term means that
the conversion can be terminated at any time. For example,
if only 8 bits of the conversion result are needed, then the
conversion can be terminated (by pulling CS HIGH) after the
8th bit has been clocked out.
0.050
0.00
0.1
1
10
100
Sample Rate (kHz)
FIGURE 5. Shutdown Current with CS HIGH is 50nA
Typically, Regardless of the Clock. Shutdown
Current with CS LOW Varies with Sample
Rate.
ADS7822
12
SBAS062A
www.ti.com
This technique can be used to lower the power dissipation (or
to increase the conversion rate) in those applications where
an analog signal is being monitored until some condition
becomes true. For example, if the signal is outside a prede-
termined range, the full 12-bit conversion result may not be
needed. If so, the conversion can be terminated after the first
n-bits, where n might be as low as 3 or 4. This results in lower
power dissipation in both the converter and the rest of the
system, as they spend more time in the power-down mode.
can drive the bypass capacitor without oscillation (the series
resistor can help in this case). Keep in mind that while the
ADS7822 draws very little current from the reference on
average, there are still instantaneous current demands placed
on the external reference circuitry.
Also, keep in mind that the ADS7822 offers no inherent
rejection of noise or voltage variation in regards to the
reference input. This is of particular concern when the
reference input is tied to the power supply. Any noise and
ripple from the supply will appear directly in the digital
results. While high frequency noise can be filtered out as
described in the previous paragraph, voltage variation due to
the line frequency (50Hz or 60Hz), can be difficult to
remove.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7822 circuitry. This will be
particularly true if the reference voltage is low and/or the
conversion rate is high. At a 75kHz conversion rate, the
ADS7822 makes a bit decision every 830ns. That is, for each
subsequent bit decision, the digital output must be updated
with the results of the last bit decision, the capacitor array
appropriately switched and charged, and the input to the
comparator settled to a 12-bit level all within one clock cycle.
The GND pin on the ADS7822 should be placed on a clean
ground point. In many cases, this will be the “analog”
ground. Avoid connecting the GND pin too close to the
grounding point for a microprocessor, microcontroller, or
digital signal processor. If needed, run a ground trace directly
from the converter to the power supply connection point. The
ideal layout will include an analog ground plane for the
converter and associated analog circuitry.
The basic SAR architecture is sensitive to spikes on the
power supply, reference, and ground connections that occur
just prior to latching the comparator output. Thus, during any
single conversion for an n-bit SAR converter, there are n
“windows” in which large external transient voltages can
easily affect the conversion result. Such spikes might origi-
nate from switching power supplies, digital logic, and high
power devices, to name a few. This particular source of error
can be very difficult to track down if the glitch is almost
synchronous to the converter’s DCLOCK signal—as the
phase difference between the two changes with time and
temperature, causing sporadic misoperation.
APPLICATION CIRCUITS
Figures 6 and 7 show some typical application circuits for
the ADS7822. Figure 6 uses an ADS7822 and a multiplexer
to provide for a flexible data acquisition circuit. A resistor
string provides for various voltages at the multiplexer input.
The selected voltage is buffered and driven into VREF. As
shown in Figure 6, the input range of the ADS7822 is
programmable to 100mV, 200mV, 300mV, or 400mV. The
100mV range would be useful for sensors such as the
thermocouple shown.
With this in mind, power to the ADS7822 should be clean
and well-bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the ADS7822 package as possible. In
addition, a 1 to 10µF capacitor and a 5Ω or 10Ω series
resistor may be used to lowpass filter a noisy supply.
Figure 7 shows a basic data acquisition system. The ADS7822
input range is 0V to VCC, as the reference input is connected
directly to the power supply. The 5Ω resistor and 1µF to
10µF capacitor filter the microcontroller “noise” on the
supply, as well as any high-frequency noise from the supply
itself. The exact values should be picked such that the filter
provides adequate rejection of the noise.
The reference should be similarly bypassed with a 0.1µF
capacitor. Again, a series resistor and large capacitor can be
used to lowpass filter the reference voltage. If the reference
voltage originates from an op amp, be careful that the op amp
ADS7822
SBAS062A
13
www.ti.com
+3V
+3V
+3V
R8
26kΩ
0.4V
0.3V
R7
5Ω
R9
1kΩ
R1
150kΩ
OPA237
D1
C2
0.1µF
U2
R3
500kΩ
R10
1kΩ
C1
10µF
MUX
R6
1MΩ
R2
59kΩ
VREF
0.2V
0.1V
DCLOCK
DOUT
R11
1kΩ
C3
0.1µF
ADS7822
TC1
A0
TC2
TC3
CS/SHDN
A1
Thermocouple
R12
1kΩ
U1
C4
10µF
R4
1kΩ
U3
C5
0.1µF
R5
500Ω
µP
ISO Thermal Block
3-Wire
Interface
U4
FIGURE 6. Thermocouple Application Using a MUX to Scale the Input Range of the ADS7822.
+2.7V to +3.6V
5Ω
+
1µF to
10µF
ADS7822
VREF
VCC
1µF to
10µF
+
0.1µF
Microcontroller
+In
CS
DOUT
–In
GND
DCLOCK
FIGURE 7. Basic Data Acquisition System.
ADS7822
14
SBAS062A
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
28-Nov-2005
PACKAGING INFORMATION
Orderable Device
ADS7822E/250
ADS7822E/2K5
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
MSOP
DGK
8
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
MSOP
DGK
8
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
ADS7822E/2K5G4
ADS7822EB/250
ACTIVE
ACTIVE
MSOP
MSOP
DGK
DGK
8
8
2500
TBD
CU NIPDAU Level-1-220C-UNLIM
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
ADS7822EB/250G4
ADS7822EB/2K5
ADS7822EB/2K5G4
ADS7822EC/250
ADS7822EC/2K5
ADS7822EC/2K5G4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
MSOP
MSOP
MSOP
MSOP
MSOP
MSOP
DGK
DGK
DGK
DGK
DGK
DGK
8
8
8
8
8
8
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
ADS7822P
ADS7822PB
ADS7822PC
ADS7822U
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
PDIP
PDIP
SOIC
P
P
P
D
8
8
8
8
50
50
50
TBD
TBD
TBD
Call TI
Call TI
Call TI
Level-NA-NA-NA
Level-NA-NA-NA
Level-NA-NA-NA
100 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
ADS7822U/2K5
ADS7822U/2K5G4
ADS7822UB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
D
8
8
8
8
8
8
8
8
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
100 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
ADS7822UB/2K5
ADS7822UC
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
100 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
ADS7822UC/2K5
ADS7822UC/2K5G4
ADS7822UG4
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
100 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Nov-2005
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.430 (10,92)
MAX
0.010 (0,25)
M
0.015 (0,38)
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明