ADS7823EB/2K5 [TI]
Sampling A/D Converter;
| 型号： | ADS7823EB/2K5 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Sampling A/D Converter 光电二极管 转换器 |
| 文件： | 总19页 (文件大小：642K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS7823
SBAS180B – JUNE 2001 - REVISED SEPTEMBER 2003
12-Bit, Sampling A/D Converter
with I2C™ INTERFACE
DESCRIPTION
The ADS7823 is a single-supply, low-power, 12-bit data
FEATURES
ꢀ 50kHz SAMPLING RATE
ꢀ NO MISSING CODES
ꢀ 2.7V TO 5V OPERATION
ꢀ FOUR-WORD FILO
acquisition device that features a serial I2C interface. The
Analog-to-Digital (A/D) converter features a sample-and-
hold amplifier and internal, asynchronous clock. The combi-
nation of an I2C serial two-wire interface and micropower
consumption makes the ADS7823 ideal for applications
requiring the A/D converter to be close to the input source in
remote locations and for applications requiring isolation. The
ADS7823 is available in an MSOP-8 package.
ꢀ A0, A1 ADDRESS PINS
ꢀ I2C INTERFACE SUPPORTS:
Standard, Fast, and High-Speed Modes
ꢀ MSOP-8 PACKAGE
APPLICATIONS
ꢀ VOLTAGE SUPPLY MONITORING
ꢀ ISOLATED DATA ACQUISITION
ꢀ TRANSDUCER INTERFACE
ꢀ BATTERY-OPERATED SYSTEMS
ꢀ REMOTE DATA ACQUISITION
SAR
VREF
SDA
SCL
AIN
CDAC
Serial
Interface
A0
Comparator
S/H Amp
A1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2001-2003, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
+VDD to GND ........................................................................ –0.3V to +6V
Digital Input Voltage to GND ................................. –0.3V to +VDD + 0.3V
Analog Input Voltage to GND ........................................... –0.3V to +6.0V
Operating Temperature Range ........................................–40°C to +85°C
Storage Temperature Range .........................................–65°C to +150°C
Junction Temperature (TJ max) .................................................... +150°C
TSSOP Package
Power Dissipation .................................................... (TJ max – TA)/θJA
θJA Thermal Impedance ...................................................... +240°C/W
Lead Temperature, Soldering
ESD damage can range from subtle performance degradation
tocompletedevicefailure. Precisionintegratedcircuitsmaybe
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
Vapor Phase (60s) ............................................................ +215°C
Infrared (15s) ..................................................................... +220°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
MAXIMUM
INTEGRAL
LINEARITY
ERROR (LSB)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR(1)
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
ADS7823E
±2
–40°C to +85°C
MSOP-8
DGK
B23
ADS7823E/250
ADS7823E/2K5
Tape and Reel, 250
Tape and Reel, 2500
"
"
"
"
"
"
ADS7823EB
±1
–40°C to +85°C
MSOP-8
DGK
B23
ADS7823EB/250
ADS7823EB/2K5
Tape and Reel, 250
Tape and Reel, 2500
"
"
"
"
"
"
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
ELECTRICAL CHARACTERISTICS: +2.7V
At TA = –40°C to +85°C, +VDD = +2.7V, VREF = +2.5V, SCL Clock Frequency = 3.4MHz (High Speed Mode) unless otherwise noted.
ADS7823E
TYP
ADS7823EB
TYP
PARAMETER
RESOLUTION
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
12
ꢀ
Bits
ANALOG INPUT
Full-Scale Input Range
Input Capacitance
Input Leakage Current
0
VREF
ꢀ
ꢀ
V
pF
µA
25
±1
ꢀ
ꢀ
SYSTEM PERFORMANCE
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Noise
Power Supply Rejection
12
ꢀ
Bits
LSB(1)
LSB
LSB
LSB
±1.0
±2
±0.5
±0.5
±0.75
±0.75
ꢀ
±1
ꢀ
±3
±3
–0.5, +1.0 –1.0, +3.0
±1.0
±1.0
33
±4
±4
µVrms
dB
82
ꢀ
SAMPLING DYNAMICS
Throughput Frequency
High Speed Mode: SCL = 3.4MHz
Fast Mode: SCL = 400kHz
Standard Mode, SCL = 100kHz
50
8
2
ꢀ
ꢀ
ꢀ
kHz
kHz
kHz
µs
Conversion Time
8
ꢀ
AC ACCURACY
Total Harmonic Distortion
Signal-to-Ratio
Signal-to-(Noise+Distortion) Ratio
Spurious Free Dynamic Range
V
IN = 2.5VPP at 10kHz
–82
72
71
ꢀ
ꢀ
ꢀ
ꢀ
dB(2)
dB
dB
VIN = 2.5VPP at 10kHz
V
V
IN = 2.5VPP at 10kHz
IN = 2.5VPP at 10kHz
86
dB
VOLTAGE REFERENCE INPUT
Range
0.05
VDD
ꢀ
ꢀ
V
Resistance
Current Drain
All Modes
1.0
9.0
ꢀ
ꢀ
GΩ
µA
At Code 800H, HS Mode: SCL = 3.4MHz
ADS7823
SBAS180B
2
ELECTRICAL CHARACTERISTICS: +2.7V (Cont.)
At TA = –40°C to +85°C, +VDD = +2.7V, VREF = +2.5V, SCL Clock Frequency = 3.4MHz (High Speed Mode) unless otherwise noted.
ADS7823E
TYP
ADS7823EB
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
DIGITAL INPUT/OUTPUT
Logic Family
CMOS
ꢀ
Logic Levels: VIH
+VDD • 0.7
–0.3
+VDD + 0.5
+VDD • 0.3
0.4
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
µA
µA
VIL
VOL
At min 3mA Sink Current
VIH = +VDD +0.5
VIL = -0.3
Input Leakage: IIH
IIL
10
-10
ꢀ
Data Format
Straight
Binary
ꢀ
ꢀ
ADS7823 HARDWARE ADDRESS
10010
Binary
POWER SUPPLY REQUIREMENTS
Power Supply Voltage, +VDD
Quiescent Current
Specified Performance
High Speed Mode: SCL = 3.4MHz
Fast Mode: SCL = 400kHz
Standard Mode, SCL = 100kHz
High Speed Mode: SCL = 3.4MHz
Fast Mode: SCL = 400kHz
Standard Mode, SCL = 100kHz
High Speed Mode: SCL = 3.4MHz
Fast Mode: SCL = 400kHz
Standard Mode, SCL = 100kHz
SCL Pulled HIGH, SDA Pulled HIGH
2.7
3.6
370
ꢀ
ꢀ
ꢀ
V
250
137
109
680
370
290
60
23
5.4
2
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
µA
µA
µA
µW
µW
µW
µA
µA
µA
nA
Power Dissipation
1000
ꢀ
Powerdown Mode
w/Wrong Address Selected
Full Powerdown
3000
85
ꢀ
ꢀ
TEMPERATURE RANGE
Specified Performance
–40
ꢀ
°C
ꢀ Specifications same as ADS7823E.
NOTES: (1) LSB means Least Significant Bit. With VREF equal to 2.5V, 1LSB is 610µV. (2) THD measured out to the 9th-harmonic.
ELECTRICAL CHARACTERISTICS: +5V
At TA = –40°C to +85°C, +VDD = +5.0V, VREF = +5.0V, SCL Clock Frequency = 3.4MHz (High Speed Mode) unless otherwise noted.
ADS7823E
TYP
ADS7823EB
TYP
PARAMETER
RESOLUTION
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
12
ꢀ
Bits
ANALOG INPUT
Full-Scale Input Range
Input Capacitance
Input Leakage Current
0
VREF
ꢀ
ꢀ
V
pF
µA
25
±1
ꢀ
ꢀ
SYSTEM PERFORMANCE
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Noise
Power Supply Rejection
12
ꢀ
Bits
LSB(1)
LSB
LSB
LSB
±1.0
–0.5, +1.0
±1.0
±1.0
33
±2
–1, +3
±4
±0.5
±0.5
±0.75
±0.75
ꢀ
±1
ꢀ
±3
±3
±4
µVrms
dB
82
ꢀ
SAMPLING DYNAMICS
Throughput Frequency
High Speed Mode: SCL = 3.4MHz
Fast Mode: SCL = 400kHz
Standard Mode, SCL = 100kHz
50
8
2
ꢀ
ꢀ
ꢀ
kHz
kHz
kHz
µs
Conversion Time
8
ꢀ
AC ACCURACY
Total Harmonic Distortion
Signal-to-Ratio
Signal-to-(Noise+Distortion) Ratio
Spurious Free Dynamic Range
V
IN = 2.5VPP at 10kHz
–82
72
71
ꢀ
ꢀ
ꢀ
ꢀ
dB(2)
dB
dB
VIN = 2.5VPP at 10kHz
V
V
IN = 2.5VPP at 10kHz
IN = 2.5VPP at 10kHz
86
dB
VOLTAGE REFERENCE INPUT
Range
0.05
VDD
ꢀ
ꢀ
V
Resistance
Current Drain
All Modes
1.0
20
ꢀ
ꢀ
GΩ
µA
At Code 800H, HS Mode: SCL = 3.4MHz
ADS7823
SBAS180B
3
ELECTRICAL CHARACTERISTICS: +5V (Cont.)
At TA = –40°C to +85°C, +VDD = +5.0V, VREF = +5.0V, SCL Clock Frequency = 3.4MHz (High Speed Mode) unless otherwise noted.
ADS7823E
TYP
ADS7823EB
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
DIGITAL INPUT/OUTPUT
Logic Family
CMOS
ꢀ
Logic Levels: VIH
+VDD
–0.3
•
0.7
+VDD + 0.5
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
µA
µA
VIL
VOL
+VDD
•
0.3
At min 3mA Sink Current
VIH = +VDD +0.5
VIL = -0.3
0.4
10
Input Leakage: IIH
IIL
-10
ꢀ
Data Format
Straight
Binary
ꢀ
ꢀ
ADS7823 HARDWARE ADDRESS
10010
Binary
POWER SUPPLY REQUIREMENTS
Power Supply Voltage, +VDD
Quiescent Current
Specified Performance
High Speed Mode: SCL= 3.4MHz
Fast Mode: SCL= 400kHz
4.75
5
5.25
1.0
ꢀ
ꢀ
ꢀ
V
0.72
380
240
ꢀ
ꢀ
ꢀ
mA
µA
µA
Standard Mode, SCL=100kHz
Power Dissipation
High Speed Mode: SCL= 3.4MHz
Fast Mode: SCL= 400kHz
Standard Mode, SCL=100kHz
3.6
1.9
1.2
5.0
ꢀ
ꢀ
ꢀ
ꢀ
mW
mW
mW
Powerdown Mode
High Speed Mode: SCL= 3.4MHz
346
ꢀ
µA
w/Wrong Address Selected
Fast Mode: SCL= 400kHz
Standard Mode, SCL=100kHz
136
34
ꢀ
ꢀ
µA
µA
Full Powerdown
SCL Pulled HIGH, SDA Pulled HIGH
3
3000
85
ꢀ
ꢀ
ꢀ
nA
TEMPERATURE RANGE
Specified Performance
–40
ꢀ
°C
ꢀ Specifications same as ADS7823E.
NOTES: (1) LSB means Least Significant Bit. With VREF equal to 2.5V, 1LSB is 610µV. (2) THD measured out to the 9th-harmonic.
PIN DESCRIPTIONS
PIN CONFIGURATION
Top View
MSOP
PIN
1
NAME
VREF
AIN
DESCRIPTION
Reference Input, 2.5V Nominal
Analog Input.
2
VREF
AIN
1
2
3
4
8
7
6
5
+VDD
SCL
SDA
A1
3
A0
Slave Address Bit 0
Ground
4
GND
A1
ADS7823
A0
5
Slave Address Bit 1
Serial Data
GND
6
SDA
SCL
+VDD
7
Serial Clock
8
Power Supply, 3.3V Nominal
TIMING DIAGRAM
SDA
tBUF
tLOW
tR
tF
tHD; STA
tSP
SCL
tHD; STA
tSU; STA
tSU; STO
tHD; DAT
tHIGH
tSU; DAT
STOP START
REPEATED
START
ADS7823
SBAS180B
4
TIMING CHARACTERISTICS(1)
At TA = –40°C to +85°C, +VDD = +2.7V, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
SCL Clock Frequency
fSCL
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max
High-Speed Mode, CB = 400pF max
100
400
3.4
kHz
kHz
MHz
MHz
1.7
Bus Free Time Between a STOP and
START Condition
tBUF
Standard Mode
Fast Mode
4.7
1.3
µs
µs
Hold Time (Repeated) START
Condition
tHD;STA
Standard Mode
Fast Mode
High-Speed Mode
4.0
600
160
µs
ns
ns
LOW Period of the SCL Clock
tLOW
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
4.7
1.3
160
320
µs
µs
ns
ns
HIGH Period of the SCL Clock
tHIGH
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
4.0
600
60
µs
ns
ns
ns
120
Setup Time for a Repeated START
Condition
tSU;STA
Standard Mode
Fast Mode
High-Speed Mode
4.7
600
160
µs
ns
ns
Data Setup Time
Data Hold Time
tSU DAT
;
Standard Mode
Fast Mode
High-Speed Mode
250
100
10
ns
ns
ns
tHD;DAT
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
0
0
0(3)
0(3)
3.45
0.9
70
µs
µs
ns
ns
150
Rise Time of SCL Signal
tRCL
tRCL1
tFCL
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
1000
300
40
ns
ns
ns
ns
20 + 0.1CB
10
20
80
Rise Time of SCL Signal After a
Repeated START Condition and
After an Acknowledge Bit
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
1000
300
80
ns
ns
ns
ns
20 + 0.1CB
10
20
160
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP Condition
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
300
300
40
ns
ns
ns
ns
20 + 0.1CB
10
20
80
tRDA
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
1000
300
80
ns
ns
ns
ns
20 + 0.1CB
10
20
160
tFDA
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
300
300
80
ns
ns
ns
ns
20 + 0.1CB
10
20
160
tSU;STO
Standard Mode
Fast Mode
High-Speed Mode
4.0
600
160
µs
ns
ns
Capacitive Load for SDA and SCL
Line
CB
tSP
400
pF
Pulse Width of Spike Suppressed
Fast Mode
50
10
ns
ns
High-Speed Mode
Noise Margin at the HIGH Level for
Each Connected Device (Including
Hysteresis)
Standard Mode
Fast Mode
High-Speed Mode
VNH
0.2VDD
0.1VDD
V
V
Noise Margin at the LOW Level for
Each Connected Device (Including
Hysteresis)
Standard Mode
Fast Mode
High-Speed Mode
VNL
NOTES: (1) All values referred to VIHMIN and VILMAX levels. (2) For bus line loads CB between 100pF and 400pF the timing parameters must be linearly interpolated.
(3) A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH signal. An input circuit with
a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
ADS7823
SBAS180B
5
TYPICAL CHARACTERISTICS
At TA = +25°C, +VDD = +2.7V, VREF = External +2.5V, fSAMPLE = 50kHz, unless otherwise noted.
FREQUENCY SPECTRUM
(4096 Point FFT, fIN = 1kHz, 0dB)
INTEGRAL LINEARITY ERROR vs CODE (+25°C)
1.00
0
0.75
0.50
–40
0.25
0
–0.25
–80
–0.50
–0.75
–1.00
000H
–120
800H
FFFH
0
10
20
25
Hex Code
Frequency (kHz)
DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C)
CHANGE IN OFFSET vs TEMPERATURE
1.00
0.75
0.50
0.25
0
1.5
1.0
0.5
0
–0.25
–0.50
–0.75
–1.00
–0.5
–1.0
–1.5
000H
800H
FFFH
–50
–25
0
25
50
75
100
Hex Code
Temperature (°C)
CHANGE IN GAIN vs TEMPERATURE
SUPPLY CURRENT vs TEMPERATURE
1.5
400
350
300
250
200
150
100
1.0
0.5
0
–0.5
–1.0
–1.5
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
ADS7823
SBAS180B
6
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, +VDD = +2.7V, VREF = External +2.5V, fSAMPLE = 50kHz, unless otherwise noted.
POWER DOWN SUPPLY CURRENT
vs TEMPERATURE
SUPPLY CURRENT vs I2C BUS RATE
40
30
350
300
250
200
150
100
50
20
10
0
–10
–20
–50
–25
0
25
50
75
100
125
10
100
1000
10000
I2C Bus Rate (kHz)
Temperature (°C)
ADS7823
SBAS180B
7
REFERENCE INPUT
THEORY OF OPERATION
The external reference sets the analog input range. The
ADS7823 will operate with a reference in the range of 50mV
to VDD. There are several important implications of this.
The ADS7823 is a classic Successive Approximation Register
(SAR) A/D converter. The architecture is based on capacitive
redistribution which inherently includes a sample-and-hold
function. The converter is fabricated on a 0.6µ CMOS process.
As the reference voltage is reduced, the analog voltage
weight of each digital output code is reduced. This is often
referred to as the LSB (least significant bit) size and is equal
to the reference voltage divided by 4096. This means that
any offset or gain error inherent in the A/D converter will
appear to increase, in terms of LSB size, as the reference
voltage is reduced.
The ADS7823 core is controlled by an internally-generated
free-running clock. When the ADS7823 is not performing
conversions or being addressed, it keeps the A/D converter
core powered off, and the internal clock does not operate.
The ADS7823 has an internal 4-word first-in last-out buffer
(FILO) that stores the results of up to four conversions while
they are waiting to be read out over the I2C bus.
The noise inherent in the converter will also appear to increase
with lower LSB size. With a 2.5V reference, the internal noise
of the converter typically contributes only 0.32LSB peak-to-
peak of potential error to the output code. When the external
reference is 50mV, the potential error contribution from the
internal noise will be 50 times larger—16LSBs. The errors due
to the internal noise are Gaussian in nature and can be
reduced by averaging consecutive conversion results.
The simplified diagram of input and output for the ADS7823
is shown in Figure 1.
ANALOG INPUT
When the converter enters the hold mode, the voltage on the
AIN pin is captured on the internal capacitor array. The input
current on the analog inputs depends on the conversion rate
of the device. During the sample period, the source must
charge the internal sampling capacitor (typically 25pF). After
the capacitor has been fully charged, there is no further input
current. The amount of charge transfer from the analog
source to the converter is a function of conversion rate.
DIGITAL INTERFACE
The ADS7823 supports the I2C serial bus and data transmis-
sion protocol, in all three defined modes: standard, fast, and
high-speed. A device that sends data onto the bus is defined
as a transmitter, and a device receiving data as a receiver.
+2.7V to +3.6V
5Ω
+
1µF to
10µF
2kΩ
2kΩ
VREF
VDD
+
0.1µF
1µF to
10µF
Microcontroller
AIN
A0
SDA
SCL
ADS7823
A1
GND
FIGURE 1. Simplified I/O of the ADS7823.
ADS7823
SBAS180B
8
The device that controls the message is called a “master.”
The devices that are controlled by the master are “slaves.”
The bus must be controlled by a master device that gener-
ates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The ADS7823
operates as a slave on the I2C bus. Connections to the bus
are made via the open-drain I/O lines SDA and SCL.
A device that acknowledges must pull down the SDA line
during the acknowledge clock pulse in such a way that the
SDA line is stable LOW during the HIGH period of the
acknowledge clock pulse. Of course, setup and hold times
must be taken into account. A master must signal an end of
data to the slave by not generating an acknowledge bit on the
last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master
to generate the STOP condition.
The following bus protocol has been defined (as shown in
Figure 2):
Figure 2 details how data transfer is accomplished on the I2C
bus. Depending upon the state of the R/W bit, two types of
data transfer are possible:
• Data transfer may be initiated only when the bus is not
busy.
• During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data line
while the clock line is HIGH will be interpreted as control
signals.
1. Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The
slave returns an acknowledge bit after the slave address
and each received byte.
Accordingly, the following bus conditions have been defined:
Bus Not Busy: Both data and clock lines remain HIGH.
2. Data transfer from a slave transmitter to a master
receiver. The first byte, the slave address, is transmitted
by the master. The slave then returns an acknowledge bit.
Next, a number of data bytes are transmitted by the slave
to the master. The master returns an acknowledge bit
after all received bytes other than the last byte. At the end
of the last received byte, a not-acknowledge is returned.
Start Data Transfer: A change in the state of the data line,
from HIGH to LOW, while the clock is HIGH, defines a
START condition.
Stop Data Transfer: A change in the state of the data line,
from LOW to HIGH, while the clock line is HIGH, defines the
STOP condition.
The master device generates all of the serial clock pulses
and the START and STOP conditions. A transfer is ended
with a STOP condition or a repeated START condition. Since
a repeated START condition is also the beginning of the next
serial transfer, the bus will not be released.
Data Valid: The state of the data line represents valid data,
when, after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal. There is one
clock pulse per bit of data.
Each data transfer is initiated with a START condition and
terminated with a STOP condition. The number of data bytes
transferred between START and STOP conditions is not
limited and is determined by the master device. The informa-
tion is transferred byte-wise and each receiver acknowl-
edges with a ninth bit.
The ADS7823 may operate in the following two modes:
• Slave Receiver Mode: Serial data and clock are received
through SDA and SCL. After each byte is received, an
acknowledge bit is transmitted. START and STOP condi-
tions are recognized as the beginning and end of a serial
transfer. Address recognition is performed by hardware
after reception of the slave address and direction bit.
Within the I2C bus specifications a standard mode (100kHz
clock rate), a fast mode (400kHz clock rate), and a high-
speed mode (3.4MHz clock rate) are defined. The ADS7823
works in all three modes.
• Slave Transmitter Mode: The first byte (the slave ad-
dress) is received and handled as in the slave receiver
mode. However, in this mode the direction bit will indicate
that the transfer direction is reversed. Serial data is trans-
mitted on SDA by the ADS7823 while the serial clock is
input on SCL. START and STOP conditions are recog-
nized as the beginning and end of a serial transfer.
Acknowledge: Each receiving device, when addressed, is
obliged to generate an acknowledge after the reception of
each byte. The master device must generate an extra clock
pulse that is associated with this acknowledge bit.
SDA
MSB
Slave Address
R/W
Direction
Bit
Acknowledgement
Signal from
Receiver
Acknowledgement
Signal from
Receiver
1
2
6
7
8
9
1
2
3-8
8
9
SCL
ACK
ACK
START
Condition
STOP Condition
or Repeated
Repeated If More Bytes Are Transferred
START Condition
FIGURE 2. Basic Operation of the ADS7823.
ADS7823
SBAS180B
9
ADDRESS BYTE
COMMAND BYTE
MSB
1
6
0
5
0
4
1
3
0
2
1
LSB
R/W
MSB
0
6
0
5
0
4
3
2
1
LSB
X
A1
A0
X
X
X
X
The address byte is the first byte received following the
START condition from the master device. The first five bits
(MSBs) of the slave address are factory pre-set to 10010.
The next two bits of the address byte are the device select
bits, A1 and A0. Input pins (A1-A0) on the ADS7823 deter-
mine these two bits of the device address for a particular
ADS7823. A maximum of four devices with the same pre-set
code can therefore be connected on the same bus at one
time.
The ADS7823 operating mode is determined by a command
byte.
The ADS7823 command byte simply consists of three zeros
in the most significant bits, while the remaining 5 bits are
don’t cares.
INITIATING CONVERSION
Provided the master has write-addressed it, the ADS7823
turns on the A/D converter section and begins conversions
when it receives bit 5 of the command byte shown in the
Command Byte. If the command byte is correct, the ADS7823
will return an ACK condition.
The A1-A0 Address Inputs can be connected to VDD or digital
ground. The device address is set by the state of these pins
upon power-up of the ADS7823.
The last bit of the address byte (R/W) defines the operation
to be performed. When set to a “1” a read operation is
selected; when set to a “0” a write operation is selected.
Following the START condition the ADS7823 monitors the
SDA bus, checking the device type identifier being transmit-
ted. Upon receiving the 10010 code, the appropriate device
select bits, and the R/W bit, the slave device outputs an
acknowledge signal on the SDA line.
The converter will ignore any wrong command byte (that is,
setting any of the top three MSBs to 1), remain in the A/D
converter power-down mode, and reset the internal 4-word
stack.
The ADS7823 will ignore a second valid command byte if two
valid commands are issued consecutively. The ADS7823 will
respond with a not-acknowledge, and will go to the A/D con-
verter power-down mode after the responded not-acknowledge.
ADC Power-Down Mode
ADC Wake-UpMode
S
1
0
0
1
0
A
A
W
A
0
0
0
X
X
X
X
X
A
1
0
Write-AddressingByte
CommandByte
ADC Power-Down Mode
Sr
1
0
0
1
0
A
A
R
A
0
0
0
0
D
D
D
D
A
D
D
.D
D
0
N
P
1
0
11 10
9
8
7
6 . .
1
(See
Note B)
Read-AddressingByte
(see Note A)
Max. 4× [2×(8 bits + ack/not-ack)]
A
N
S
P
= acknowledge (SDA Low)
= not-acknowledge (SDA High)
= START Condition
W = 0 (WRITE)
R = 1 (READ)
From master to slave
From slave to master
= STOP Condition
Sr = repeatedSTARTCondition
NOTES: (A) Failure for master to send read-addressing byte—setting R/W flag to “1”—will result in internal clock remaining ON, increasing power consumption.
(B) Use repeated START to secure bus operation and loop back to the stage of write-addressing for next conversion.
FIGURE 3. Typical Read Sequence in F/S Mode.
ADS7823
SBAS180B
10
READING DATA
acknowledge after the fourth data word has been read. This
tells the ADS7823 that no further reads will be performed. No
more than four data words should be read at a time; further
reads will return undefined data.
Data can be read from the ADS7823 by read-addressing the
part (LSB of address byte set to 1) and receiving the
transmitted bytes. Converted data can only be read from the
ADS7823 once a conversion has been initiated as described
in the preceding section.
Although a STOP condition is shown at the end of the figure,
it is permissible to issue a repeated START; this will have the
same effect.
Each 12-bit data word is returned in two bytes, as shown
below, where D11 is the MSB of the data word, and D0 is the
LSB. Byte 0 is sent first, followed by Byte 1.
READING IN HS MODE
High Speed (HS) mode is fast enough that codes can be
read out one at a time, without employing the FILO. In HS
mode there is not enough time for a single conversion to
complete between the reception of command bit 5 and the
read address byte, so the ADS7823 stretches the clock after
the command byte has been fully received, holding it LOW
until the conversion is complete.
MSB
6
5
4
3
2
1
LSB
BYTE0
BYTE1
0
0
0
0
D11
D3
D10
D2
D9
D1
D8
D0
D7
D6
D5
D4
READING IN F/S MODE
In Fast and Standard (F/S) modes, the A/D converter has
time to make four complete conversions between the recep-
tion of bit 5 of the command byte and the complete reception
of the read address, even when operating in Fast mode.
A typical read sequence for HS mode is shown in Figure 4.
Included in the read sequence is the shift from
F/S to HS modes. It may be desirable to remain in HS mode
after reading a code; to do this, issue a repeated START
instead of a STOP at the end of the read sequence, since a
STOP causes the part to return to F/S mode.
Because the ADS7823 can perform these conversions much
faster than they can be transmitted in F/S mode, data is
stored in a four-level FILO. During the read operation, the A/
D converter is powered down and the contents of the stack
are read out one by one in the correct order.
It is very important not to read more than one code at a time
from the ADS7823 during HS mode. If codes are read out
more than one at a time, as in F/S mode, the results for all
codes (except the first) are undefined, and the data stream
will be corrupt.
A typical transfer sequence for reading four words of data in
F/S mode (see Figure 3). Note that the master sends a not-
F/S Mode
S
0
0
0
0
1
X
X
X
N
HS Mode Master Code
HS Mode Enabled
ADC Power-Down Mode
ADC Wake-UpMode
Sr
1
0
0
1
0
A
A
W
A
0
0
0
X
X
X
X
X
A
SCLH is stretched in wait-state
1
0
Return to
F/S Mode
See Note B
Write-AddressingByte
CommandByte
HS Mode Enabled
ADC Power-Down Mode
Sr
1
0
0
1
0
A
A
R
A
0
0
0
0
D
D
D
D
A
D
D
.D
D
0
N
P
1
0
11 10
9
8
7
6 . .
1
Read-AddressingByte
(see Note A)
2×(8 bits + ack/not-ack)
A
N
S
P
= acknowledge (SDA Low)
= not-acknowledge (SDA High)
= START Condition
W = 0 (WRITE)
R = 1 (READ)
From master to slave
From slave to master
= STOP Condition
Sr = repeatedSTART Condition
NOTES: (A) Failure for master to send read-addressing byte—setting R/W flag to “1”—will result in internal clock remaining ON, increasing power consumption.
(B) Use repeated START to remain in HS mode instead of STOP.
FIGURE 4. Typical Read Sequence in HS Mode.
ADS7823
SBAS180B
11
TERMINATING A CONVERSION
external transient voltages can easily affect the conversion
result. Such glitches might originate from switching power
supplies, nearby digital logic, and high-power devices.
There are three methods to terminate the conversion of the
A/D converter in the ADS7823 after the master initiates
conversion:
With this in mind, power to the ADS7823 should be clean and
well bypassed. A 0.1µF ceramic bypass capacitor should be
placed as close to the device as possible. A 1µF to 10µF
capacitor may also be needed if the impedance of the
connection between +VDD and the power supply is high.
1) In normal operation sequence (see Figures 3 and 4). The
conversion is terminated after the read-addressing has
been received.
2) A STOP condition will always terminate a conversion. It
will also terminate the HS mode returning the ADS7823 to
the F/S mode.
The ADS7823 architecture offers no inherent rejection of
noise or voltage variation in regards to using an external
reference input. This is of particular concern when the
reference input is tied to the power supply. Any noise and
ripple from the supply will appear directly in the digital results.
While high-frequency noise can be filtered out, voltage varia-
tion due to line frequency (50Hz or 60Hz) can be difficult to
remove.
3) A not-acknowledge by the ADS7823 following a second
command byte will end a conversion.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7823 circuitry. The basic SAR
architecture is sensitive to glitches or sudden changes on the
power supply, reference, ground connections, and digital
inputs that occur just prior to latching the output of the analog
comparator. Therefore, during any single conversion for an
“n-bit” SAR converter, there are n “windows” in which large
The GND pin should be connected to a clean ground point.
In many cases, this will be the “analog” ground. Avoid
connections that are too near the grounding point of a
microcontroller or digital signal processor. The ideal layout
will include an analog ground plane dedicated to the con-
verter and associated analog circuitry.
ADS7823
SBAS180B
12
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
ADS7823E/250
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
DGK
8
8
8
8
8
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
CU NIPDAUAG
CU NIPDAUAG
CU NIPDAUAG
CU NIPDAUAG
CU NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
B23
B23
B23
B23
B23
B23
ADS7823E/250G4
ADS7823E/2K5
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DGK
DGK
DGK
DGK
DGK
250
2500
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
ADS7823EB/250
ADS7823EB/250G4
ADS7823EB/2K5
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
2500
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS7823E/250
ADS7823E/2K5
ADS7823EB/250
ADS7823EB/2K5
VSSOP
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
DGK
8
8
8
8
250
2500
250
180.0
330.0
180.0
330.0
12.4
12.4
12.4
12.4
5.3
5.3
5.3
5.3
3.4
3.4
3.4
3.4
1.4
1.4
1.4
1.4
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS7823E/250
ADS7823E/2K5
ADS7823EB/250
ADS7823EB/2K5
VSSOP
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
DGK
8
8
8
8
250
2500
250
210.0
367.0
210.0
367.0
185.0
367.0
185.0
367.0
35.0
35.0
35.0
35.0
2500
Pack Materials-Page 2
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相关型号：
ADS7824PBG4
4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PDIP28, GREEN, PLASTIC, DIP-28
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