ADS7828E/2K5G4 [TI]
具有内部基准源和 I2C 接口的 12 位 8 通道 SAR ADC | PW | 16 | -40 to 85;
| 型号： | ADS7828E/2K5G4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有内部基准源和 I2C 接口的 12 位 8 通道 SAR ADC | PW | 16 | -40 to 85 光电二极管 转换器 |
| 文件： | 总17页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS7828
A
D
®
S7828
SBAS181B – NOVEMBER 2001 - REVISED SEPTEMBER 2003
12-Bit, 8-Channel Sampling
ANALOG-TO-DIGITAL CONVERTER
with I2C™ Interface
DESCRIPTION
FEATURES
ꢀ 8-CHANNEL MULTIPLEXER
ꢀ 50kHz SAMPLING RATE
ꢀ NO MISSING CODES
The ADS7828 is a single-supply, low-power, 12-bit data
acquisition device that features a serial I2C interface and an
8-channel multiplexer. The Analog-to-Digital (A/D) converter
features a sample-and-hold amplifier and internal,
asynchronous clock. The combination of an I2C serial,
2-wire interface and micropower consumption makes the
ADS7828 ideal for applications requiring the A/D converter to
be close to the input source in remote locations and for
applications requiring isolation. The ADS7828 is available in
a TSSOP-16 package.
ꢀ 2.7V TO 5V OPERATION
ꢀ INTERNAL 2.5V REFERENCE
ꢀ I2C INTERFACE SUPPORTS:
Standard, Fast, and High-Speed Modes
ꢀ TSSOP-16 PACKAGE
APPLICATIONS
ꢀ VOLTAGE-SUPPLY MONITORING
ꢀ ISOLATED DATA ACQUISITION
ꢀ TRANSDUCER INTERFACE
ꢀ BATTERY-OPERATED SYSTEMS
ꢀ REMOTE DATA ACQUISITION
CH0
CH1
CH2
CH3
SAR
8-Channel
MUX
CH4
CH5
CH6
CH7
COM
SDA
SCL
CDAC
Serial
Interface
A0
Comparator
A1
S/H Amp
2.5V VREF
REFIN/REFOUT
Buffer
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2001-2003, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
+VDD to GND ........................................................................ –0.3V to +6V
Digital Input Voltage to GND ................................. –0.3V to +VDD + 0.3V
Operating Temperature Range ...................................... –40°C to +105°C
Storage Temperature Range .........................................–65°C to +150°C
Junction Temperature (TJ max) .................................................... +150°C
TSSOP Package
Power Dissipation .................................................... (TJ max – TA)/θJA
θJA Thermal Impedance ........................................................ 240°C/W
Lead Temperature, Soldering
ESD damage can range from subtle performance degradation to
completedevicefailure.Precisionintegratedcircuitsmaybemore
susceptible to damage because very small parametric changes
could cause the device not to meet its published specifications.
Vapor Phase (60s) ............................................................ +215°C
Infrared (15s) ..................................................................... +220°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
MAXIMUM
INTEGRAL
SPECIFIED
LINEARITY
ERROR (LSB)
PACKAGE
DESIGNATOR(1)
TEMPERATURE
RANGE
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
ADS7828E
±2
TSSOP-16
PW
–40°C to +85°C
ADS7828E/250
ADS7828E/2K5
Tape and Reel, 250
Tape and Reel, 2500
"
"
"
"
"
ADS7828EB
±1
TSSOP-16
PW
–40°C to +85°C
ADS7828EB/250
ADS7828EB/2K5
Tape and Reel, 250
Tape and Reel, 2500
"
"
"
"
"
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
ELECTRICAL CHARACTERISTICS: +2.7V
At TA = –40°C to +85°C, +VDD = +2.7V, VREF = +2.5V, SCL Clock Frequency = 3.4MHz (High-Speed Mode), unless otherwise noted.
ADS7828E
TYP
ADS7828EB
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
ANALOG INPUT
Full-Scale Input Scan
Absolute Input Range
Positive Input - Negative Input
Positive Input
0
–0.2
–0.2
VREF
+VDD + 0.2
+0.2
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
Negative Input
Capacitance
Leakage Current
25
±1
ꢀ
ꢀ
pF
µA
SYSTEM PERFORMANCE
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Offset Error
Offset Error Match
Gain Error
Gain Error Match
Noise
12
ꢀ
Bits
LSB(1)
LSB
LSB
LSB
LSB
LSB
µVRMS
dB
±1.0
±1.0
±1.0
±0.2
±1.0
±0.2
33
±2
±0.5
±0.5
±0.75
ꢀ
±0.75
ꢀ
±1
–1, +2
±2
ꢀ
±3
±3
±1
±4
±1
ꢀ
ꢀ
ꢀ
Power-Supply Rejection
82
SAMPLING DYNAMICS
Throughput Frequency
High Speed Mode: SCL = 3.4MHz
Fast Mode: SCL = 400kHz
Standard Mode, SCL = 100kHz
50
8
2
ꢀ
ꢀ
ꢀ
kHz
kHz
Conversion Time
6
ꢀ
µs
AC ACCURACY
Total Harmonic Distortion
Signal-to-Ratio
Signal-to-(Noise+Distortion) Ratio
Spurious-Free Dynamic Range
Isolation Channel-to-Channel
V
IN = 2.5VPP at 10kHz
–82
72
71
86
120
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
dB(2)
dB
dB
dB
dB
VIN = 2.5VPP at 10kHz
VIN = 2.5VPP at 10kHz
V
IN = 2.5VPP at 10kHz
VOLTAGE REFERENCE OUTPUT
Range
Internal Reference Drift
Output Impedance
2.475
0.05
2.5
15
110
1
2.525
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
ppm/°C
Ω
GΩ
µA
Internal Reference ON
Internal Reference OFF
Int. Ref. ON, SCL and SDA pulled HIGH
ꢀ
ꢀ
ꢀ
Quiescent Current
850
VOLTAGE REFERENCE INPUT
Range
VDD
V
Resistance
Current Drain
1
20
ꢀ
ꢀ
GΩ
µA
High Speed Mode: SCL= 3.4MHz
ADS7828
SBAS181B
2
www.ti.com
ELECTRICAL CHARACTERISTICS: +2.7V (Cont.)
At TA = –40°C to +85°C, +VDD = +2.7V, VREF = +2.5V, SCL Clock Frequency = 3.4MHz (High-Speed Mode), unless otherwise noted.
ADS7828E
TYP
ADS7828EB
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
DIGITAL INPUT/OUTPUT
Logic Family
CMOS
ꢀ
Logic Levels: VIH
+VDD • 0.7
–0.3
+VDD + 0.5
+VDD • 0.3
0.4
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
µA
µA
VIL
VOL
Min. 3mA Sink Current
VIH = +VDD +0.5
VIL = -0.3
Input Leakage: IIH
IIL
10
-10
ꢀ
Data Format
Straight
Binary
ꢀ
ꢀ
ADS7828 HARDWARE ADDRESS
10010
Binary
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage, +VDD
Quiescent Current
Specified Performance
High Speed Mode: SCL = 3.4MHz
Fast Mode: SCL = 400kHz
Standard Mode, SCL = 100kHz
High Speed Mode: SCL = 3.4MHz
Fast Mode: SCL = 400kHz
Standard Mode, SCL = 100kHz
High Speed Mode: SCL = 3.4MHz
Fast Mode: SCL = 400kHz
Standard Mode, SCL = 100kHz
SCL Pulled HIGH, SDA Pulled HIGH
2.7
3.6
320
ꢀ
ꢀ
ꢀ
V
225
100
60
675
300
180
70
25
6
400
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
µA
µA
µA
µW
µW
µW
µA
µA
µA
nA
Power Dissipation
1000
ꢀ
Power-Down Mode
w/Wrong Address Selected
Full Power-Down
3000
85
ꢀ
ꢀ
TEMPERATURE RANGE
Specified Performance
–40
ꢀ
°C
ꢀ Specifications same as ADS7828E.
NOTES: (1) LSB means Least Significant Bit. With VREF equal to 2.5V, 1LSB is 610µV. (2) THD measured out to the 9th-harmonic.
ELECTRICAL CHARACTERISTICS: +5V
At TA = –40°C to +85°C, +VDD = +5.0V, VREF = External +5.0V, SCL Clock Frequency = 3.4MHz (High-Speed Mode), unless otherwise noted.
ADS7828E
TYP
ADS7828EB
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
ANALOG INPUT
Full-Scale Input Scan
Absolute Input Range
Positive Input - Negative Input
Positive Input
0
–0.2
–0.2
VREF
+VDD + 0.2
+0.2
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
Negative Input
Capacitance
Leakage Current
25
±1
ꢀ
ꢀ
pF
µA
SYSTEM PERFORMANCE
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Offset Error
Offset Error Match
Gain Error
Gain Error Match
Noise
12
ꢀ
Bits
LSB(1)
LSB
LSB
LSB
LSB
LSB
µVRMS
dB
±1.0
±1.0
±1.0
±2
±0.5
±0.5
±0.75
±1
–1, +2
±2
ꢀ
±2
±3
±1
±3
±1
±1.0
±0.75
ꢀ
33
82
ꢀ
ꢀ
Power-Supply Rejection
SAMPLING DYNAMICS
Throughput Frequency
High Speed Mode: SCL = 3.4MHz
Fast Mode: SCL = 400kHz
Standard Mode, SCL = 100kHz
50
8
2
ꢀ
ꢀ
ꢀ
kHz
kHz
kHz
µs
Conversion Time
6
ꢀ
AC ACCURACY
Total Harmonic Distortion
Signal-to-Ratio
Signal-to-(Noise+Distortion) Ratio
Spurious-Free Dynamic Range
Isolation Channel-to-Channel
VIN = 2.5VPP at 10kHz
VIN = 2.5VPP at 10kHz
VIN = 2.5VPP at 10kHz
VIN = 2.5VPP at 10kHz
–82
72
71
86
120
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
dB(2)
dB
dB
dB
dB
VOLTAGE REFERENCE OUTPUT
Range
Internal Reference Drift
Output Impedance
2.475
0.05
2.5
15
110
1
2.525
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
ppm/°C
Ω
GΩ
µA
Internal Reference ON
Internal Reference OFF
Int. Ref. ON, SCL and SDA pulled HIGH
ꢀ
ꢀ
ꢀ
Quiescent Current
1300
VOLTAGE REFERENCE INPUT
Range
VDD
V
Resistance
Current Drain
1
20
ꢀ
ꢀ
GΩ
µA
High Speed Mode: SCL = 3.4MHz
ADS7828
SBAS181B
3
www.ti.com
ELECTRICAL CHARACTERISTICS: +5V (Cont.)
At TA = –40°C to +85°C, +VDD = +5.0V, VREF = External +5.0V, SCL Clock Frequency = 3.4MHz (High-Speed Mode), unless otherwise noted.
ADS7828E
TYP
ADS7828EB
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
DIGITAL INPUT/OUTPUT
Logic Family
CMOS
+VDD • 0.7
–0.3
ꢀ
ꢀ
ꢀ
Logic Levels:
VIH
+VDD + 0.5
ꢀ
V
VIL
+VDD • 0.3
ꢀ
ꢀ
ꢀ
V
V
µA
µA
VOL
Min. 3mA Sink Current
VIH = +VDD +0.5
VIL = -0.3
0.4
10
Input Leakage: IIH
IIL
-10
ꢀ
Data Format
Straight
Binary
ꢀ
ꢀ
ADS7828 HARDWARE ADDRESS
10010
Binary
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage, +VDD
Quiescent Current
Specified Performance
High Speed Mode: SCL = 3.4MHz
Fast Mode: SCL = 400kHz
4.75
5
5.25
1000
ꢀ
ꢀ
ꢀ
V
750
300
150
ꢀ
ꢀ
ꢀ
µA
µA
µA
Standard Mode, SCL = 100kHz
Power Dissipation
High Speed Mode: SCL = 3.4MHz
Fast Mode: SCL = 400kHz
Standard Mode, SCL = 100kHz
3.75
1.5
0.75
5
ꢀ
ꢀ
ꢀ
ꢀ
mW
mW
mW
Power-Down Mode
High Speed Mode: SCL = 3.4MHz
400
ꢀ
µA
w/Wrong Address Selected
Fast Mode: SCL = 400kHz
Standard Mode, SCL = 100kHz
150
35
ꢀ
ꢀ
µA
µA
Full Power-Down
SCL Pulled HIGH, SDA Pulled HIGH
400
3000
85
ꢀ
ꢀ
ꢀ
nA
TEMPERATURE RANGE
Specified Performance
–40
ꢀ
°C
ꢀ Specifications same as ADS7828E.
NOTES: (1) LSB means Least Significant Bit. With VREF equal to 5.0V, 1LSB is 1.22mV. (2) THD measured out to the 9th-harmonic.
PIN DESCRIPTIONS
PIN CONFIGURATION
PIN
NAME
DESCRIPTION
Top View
TSSOP
1
2
3
4
5
6
7
8
9
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
GND
Analog Input Channel 0
Analog Input Channel 1
Analog Input Channel 2
Analog Input Channel 3
Analog Input Channel 4
Analog Input Channel 5
Analog Input Channel 6
Analog Input Channel 7
Analog Ground
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
1
2
3
4
5
6
7
8
16 +VDD
15 SDA
14 SCL
13 A1
ADS7828
12 A0
10 REFIN / REFOUT Internal +2.5V Reference, External Reference Input
11 COM
11
12
13
14
15
16
COM
A0
Common to Analog Input Channel
Slave Address Bit 0
Slave Address Bit 1
Serial Clock
10 REFIN / REFOUT
A1
9
GND
SCL
SDA
+VDD
Serial Data
Power Supply, 3.3V Nominal
TIMING DIAGRAM
SDA
tBUF
tLOW
tR
tF
tHD; STA
tSP
SCL
tHD; STA
tSU; STA
tSU; STO
tHD; DAT
tHIGH
tSU; DAT
STOP START
REPEATED
START
ADS7828
SBAS181B
4
www.ti.com
TIMING CHARACTERISTICS(1)
At TA = –40°C to +85°C, +VDD = +2.7V, unless otherwise noted.
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
SCL Clock Frequency
fSCL
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max
High-Speed Mode, CB = 400pF max
100
400
3.4
1.7
kHz
kHz
MHz
MHz
Bus Free Time Between a STOP and
START Condition
tBUF
Standard Mode
Fast Mode
4.7
1.3
µs
µs
Hold Time (Repeated) START
Condition
tHD;STA
Standard Mode
Fast Mode
High-Speed Mode
4.0
600
160
µs
ns
ns
LOW Period of the SCL Clock
tLOW
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
4.7
1.3
160
320
µs
µs
ns
ns
HIGH Period of the SCL Clock
tHIGH
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
4.0
600
60
µs
ns
ns
ns
120
Setup Time for a Repeated START
Condition
tSU;STA
Standard Mode
Fast Mode
High-Speed Mode
4.7
600
160
µs
ns
ns
Data Setup Time
Data Hold Time
tSU DAT
;
Standard Mode
Fast Mode
High-Speed Mode
250
100
10
ns
ns
ns
tHD;DAT
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
0
0
0(3)
0(3)
3.45
0.9
70
µs
µs
ns
ns
150
Rise Time of SCL Signal
tRCL
tRCL1
tFCL
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
1000
300
40
ns
ns
ns
ns
20 + 0.1CB
10
20
80
Rise Time of SCL Signal After a
Repeated START Condition and
After an Acknowledge Bit
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
1000
300
80
ns
ns
ns
ns
20 + 0.1CB
10
20
160
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP Condition
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
300
300
40
ns
ns
ns
ns
20 + 0.1CB
10
20
80
tRDA
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
1000
300
80
ns
ns
ns
ns
20 + 0.1CB
10
20
160
tFDA
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
300
300
80
ns
ns
ns
ns
20 + 0.1CB
10
20
160
tSU;STO
Standard Mode
Fast Mode
High-Speed Mode
4.0
600
160
µs
ns
ns
Capacitive Load for SDA and SCL
Line
CB
tSP
400
pF
Pulse Width of Spike Suppressed
Fast Mode
High-Speed Mode
50
10
ns
ns
Noise Margin at the HIGH Level for
Each Connected Device (Including
Hysteresis)
Standard Mode
Fast Mode
High-Speed Mode
VNH
0.2VDD
0.1VDD
V
V
Noise Margin at the LOW Level for
Each Connected Device (Including
Hysteresis)
Standard Mode
Fast Mode
High-Speed Mode
VNL
NOTES: (1) All values referred to VIHMIN and VILMAX levels. (2) For bus line loads CB between 100pF and 400pF the timing parameters must be linearly interpolated.
(3) A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH signal. An input circuit with
a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
ADS7828
SBAS181B
5
www.ti.com
TYPICAL CHARACTERISTICS
TA = +25°C, VDD = +2.7V, VREF = External +2.5V, fSAMPLE = 50kHz, unless otherwise noted.
FREQUENCY SPECTRUM
(4096 Point FFT: fIN = 1kHz, 0dB)
INTEGRAL LINEARITY ERROR vs CODE
(2.5V Internal Reference)
0.00
–40.00
–80.00
–120.0
2.00
1.50
1.00
0.50
0.00
–0.50
–1.00
–1.50
–2.00
0
10
20
25
0
1024
2048
3072
4095
4095
100
Frequency (kHz)
Output Code
INTEGRAL LINEARITY ERROR vs CODE
(2.5V External Reference)
DIFFERENTIAL LINEARITY ERROR vs CODE
(2.5V Internal Reference)
2.00
1.50
2.00
1.50
1.00
1.00
0.50
0.50
0.00
0.00
–0.50
–1.00
–1.50
–2.00
–0.50
–1.00
–1.50
–2.00
0
1024
2048
3072
0
1024
2048
3072
4095
Output Code
Output Code
DIFFERENTIAL LINEARITY ERROR vs CODE
(2.5V External Reference)
CHANGE IN OFFSET vs TEMPERATURE
1.5
1.0
2.00
1.50
1.00
0.5
0.50
0.0
0.00
–0.50
–1.00
–1.50
–2.00
–0.5
–1.0
–1.5
–50
–25
0
25
50
75
0
1024
2048
3072
4095
Output Code
Temperature (°C)
ADS7828
SBAS181B
6
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
TA = +25°C, VDD = +2.7V, VREF = External +2.5V, fSAMPLE = 50kHz, unless otherwise noted.
CHANGE IN GAIN vs TEMPERATURE
INTERNAL REFERENCE vs TEMPERATURE
1.5
1.0
2.51875
2.51250
2.50625
2.50000
2.49375
2.48750
2.48125
0.5
0.0
–0.5
–1.0
–1.5
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
POWER-DOWN SUPPLY CURRENT
vs TEMPERATURE
SUPPLY CURRENT vs TEMPERATURE
750
600
450
300
150
0
400
350
300
250
200
150
100
–150
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
SUPPLY CURRENT vs I2C BUS RATE
300
250
200
150
100
50
0
10
100
1k
10k
I2C Bus Rate (KHz)
ADS7828
SBAS181B
7
www.ti.com
range for a 0V to +VDD analog input. This external reference
can be as low as 50mV.
THEORY OF OPERATION
The ADS7828 is a classic Successive Approximation Regis-
ter (SAR) A/D converter. The architecture is based on ca-
pacitive redistribution which inherently includes a sample-
and-hold function. The converter is fabricated on a 0.6µ
CMOS process.
As the reference voltage is reduced, the analog voltage
weight of each digital output code is reduced. This is often
referred to as the LSB (least significant bit) size and is equal
to the reference voltage divided by 4096. This means that
any offset or gain error inherent in the A/D converter will
appear to increase, in terms of LSB size, as the reference
voltage is reduced.
The ADS7828 core is controlled by an internally generated
free-running clock. When the ADS7828 is not performing
conversions or being addressed, it keeps the A/D converter
core powered off, and the internal clock does not operate.
The noise inherent in the converter will also appear to increase
with lower LSB size. With a 2.5V reference, the internal noise
of the converter typically contributes only 0.32LSB peak-to-
peak of potential error to the output code. When the external
reference is 50mV, the potential error contribution from the
internal noise will be 50 times larger—16LSBs. The errors due
to the internal noise are Gaussian in nature and can be
reduced by averaging consecutive conversion results.
The simplified diagram of input and output for the ADS7828
is shown in Figure 1.
ANALOG INPUT
When the converter enters the hold mode, the voltage on the
selected CHx pin is captured on the internal capacitor array.
The input current on the analog inputs depends on the
conversion rate of the device. During the sample period, the
source must charge the internal sampling capacitor (typically
25pF). After the capacitor has been fully charged, there is no
further input current. The amount of charge transfer from the
analog source to the converter is a function of conversion rate.
DIGITAL INTERFACE
The ADS7828 supports the I2C serial bus and data transmis-
sion protocol, in all three defined modes: standard, fast, and
high-speed. A device that sends data onto the bus is defined
as a transmitter, and a device receiving data as a receiver.
The device that controls the message is called a “master.”
The devices that are controlled by the master are “slaves.”
The bus must be controlled by a master device that gener-
ates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The ADS7828
operates as a slave on the I2C bus. Connections to the bus
are made via the open-drain I/O lines SDA and SCL.
REFERENCE
The ADS7828 can operate with its internal 2.5V reference or
an external reference. When using a +2.7V supply, the
internal 2.5V reference will provide full dynamic range for a
0V to +VDD analog input. If a +5V supply is used, an external
5V reference is required in order to provide full dynamic
+2.7V to +3.6V
5Ω
+
1µF to
10µF
2kΩ
2kΩ
REFIN
/
VDD
+
REFOUT
0.1µF
1µF to
10µF
Microcontroller
CH0
SDA
CH1
CH2
SCL
A0
ADS7828
CH3
CH4
CH5
CH6
CH7
COM
A1
GND
FIGURE 1. Simplified I/O of the ADS7828.
ADS7828
SBAS181B
8
www.ti.com
The following bus protocol has been defined (as shown in
Figure 2):
must be taken into account. A master must signal an end of
data to the slave by not generating an acknowledge bit on the
last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master
to generate the STOP condition.
• Data transfer may be initiated only when the bus is not
busy.
• During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data line
while the clock line is HIGH will be interpreted as control
signals.
Figure 2 details how data transfer is accomplished on the I2C
bus. Depending upon the state of the R/W bit, two types of
data transfer are possible:
1. Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The
slave returns an acknowledge bit after the slave address
and each received byte.
Accordingly, the following bus conditions have been defined:
Bus Not Busy: Both data and clock lines remain HIGH.
Start Data Transfer: A change in the state of the data line,
from HIGH to LOW, while the clock is HIGH, defines a
START condition.
2. Data transfer from a slave transmitter to a master
receiver. The first byte, the slave address, is transmitted
by the master. The slave then returns an acknowledge bit.
Next, a number of data bytes are transmitted by the slave
to the master. The master returns an acknowledge bit
after all received bytes other than the last byte. At the end
of the last received byte, a not-acknowledge is returned.
Stop Data Transfer: A change in the state of the data line,
from LOW to HIGH, while the clock line is HIGH, defines the
STOP condition.
Data Valid: The state of the data line represents valid data,
when, after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal. There is one
clock pulse per bit of data.
The master device generates all of the serial clock pulses
and the START and STOP conditions. A transfer is ended
with a STOP condition or a repeated START condition. Since
a repeated START condition is also the beginning of the next
serial transfer, the bus will not be released.
Each data transfer is initiated with a START condition and
terminated with a STOP condition. The number of data bytes
transferred between START and STOP conditions is not
limited and is determined by the master device. The informa-
tion is transferred byte-wise and each receiver acknowl-
edges with a ninth-bit.
The ADS7828 may operate in the following two modes:
• Slave Receiver Mode: Serial data and clock are received
through SDA and SCL. After each byte is received, an
acknowledge bit is transmitted. START and STOP condi-
tions are recognized as the beginning and end of a serial
transfer. Address recognition is performed by hardware
after reception of the slave address and direction bit.
Within the I2C bus specifications a standard mode (100kHz
clock rate), a fast mode (400kHz clock rate), and a high-
speed mode (3.4MHz clock rate) are defined. The ADS7828
works in all three modes.
Acknowledge: Each receiving device, when addressed, is
obliged to generate an acknowledge after the reception of
each byte. The master device must generate an extra clock
pulse that is associated with this acknowledge bit.
• Slave Transmitter Mode: The first byte (the slave ad-
dress) is received and handled as in the slave receiver
mode. However, in this mode the direction bit will indicate
that the transfer direction is reversed. Serial data is trans-
mitted on SDA by the ADS7828 while the serial clock is
input on SCL. START and STOP conditions are recog-
nized as the beginning and end of a serial transfer.
A device that acknowledges must pull down the SDA line
during the acknowledge clock pulse in such a way that the
SDA line is stable LOW during the HIGH period of the
acknowledge clock pulse. Of course, setup and hold times
SDA
MSB
Slave Address
R/W
Direction
Bit
Acknowledgement
Signal from
Receiver
Acknowledgement
Signal from
Receiver
1
2
6
7
8
9
1
2
3-8
8
9
SCL
ACK
ACK
START
Condition
STOP Condition
or Repeated
Repeated If More Bytes Are Transferred
START Condition
FIGURE 2. Basic Operation of the ADS7828.
ADS7828
SBAS181B
9
www.ti.com
Address Byte
Command Byte
MSB
1
6
0
5
0
4
1
3
0
2
1
LSB
R/W
MSB
SD
6
5
4
3
2
1
LSB
X
A1
A0
C2
C1
C0
PD1
PD0
X
The address byte is the first byte received following the
START condition from the master device. The first five bits
(MSBs) of the slave address are factory pre-set to 10010.
The next two bits of the address byte are the device select
bits, A1 and A0. Input pins (A1-A0) on the ADS7828 deter-
mine these two bits of the device address for a particular
ADS7828. A maximum of four devices with the same pre-set
code can therefore be connected on the same bus at one
time.
The ADS7828’s operating mode is determined by a com-
mand byte which is illustrated above.
SD: Single-Ended/Differential Inputs
0: Differential Inputs
1: Single-Ended Inputs
C2 - C0: Channel Selections
PD1 - 0: Power-Down Selection
X: Unused
See Table I for Truth Table.
The A1-A0 Address Inputs can be connected to VDD or digital
ground. The device address is set by the state of these pins
upon power-up of the ADS7828.
POWER-DOWN SELECTION
The last bit of the address byte (R/W) defines the operation
to be performed. When set to a “1” a read operation is
selected; when set to a “0” a write operation is selected.
Following the START condition the ADS7828 monitors the
SDA bus, checking the device type identifier being transmit-
ted. Upon receiving the 10010 code, the appropriate device
select bits, and the R/W bit, the slave device outputs an
acknowledge signal on the SDA line.
PD1 PD0
DESCRIPTION
0
0
1
1
0
1
0
1
Power Down Between A/D Converter Conversions
Internal Reference OFF and A/D Converter ON
Internal Reference ON and A/D Converter OFF
Internal Reference ON and A/D Converter ON
INITIATING CONVERSION
Provided the master has write-addressed it, the ADS7828
turns on the A/D converter’s section and begins conversions
when it receives BIT 4 of the command byte shown in the
Command Byte. If the command byte is correct, the ADS7828
will return an ACK condition.
CHANNEL SELECTION CONTROL
SD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
C0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CH0
+IN
—
CH1
–IN
—
CH2
—
CH3
—
CH4
—
CH5
—
CH6
—
CH7
—
COM
—
+IN
—
–IN
—
—
—
—
—
—
—
—
+IN
—
–IN
—
—
—
—
—
—
—
—
+IN
—
–IN
—
—
–IN
—
+IN
—
—
—
—
—
—
–IN
—
+IN
—
—
—
—
—
—
—
—
–IN
—
+IN
—
—
—
—
—
—
—
—
–IN
—
+IN
—
—
+IN
—
—
—
—
—
—
–IN
–IN
–IN
–IN
–IN
–IN
–IN
–IN
—
+IN
—
—
—
—
—
—
—
—
—
+IN
—
—
—
—
—
—
—
—
—
+IN
—
—
—
+IN
—
—
—
—
—
—
—
—
+IN
—
—
—
—
—
—
—
—
—
+IN
—
—
—
—
—
—
—
—
—
+IN
TABLE I. Channel Selection Control Addressed by Command BYTE.
ADS7828
SBAS181B
10
www.ti.com
modes. It may be desirable to remain in HS mode after
reading a conversion; to do this, issue a repeated START
instead of a STOP at the end of the read sequence, since a
STOP causes the part to return to F/S mode.
READING DATA
Data can be read from the ADS7828 by read-addressing the
part (LSB of address byte set to 1) and receiving the
transmitted bytes. Converted data can only be read from the
ADS7828 once a conversion has been initiated as described
in the preceding section.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7828 circuitry. The basic SAR
architecture is sensitive to glitches or sudden changes on the
power supply, reference, ground connections, and digital
inputs that occur just prior to latching the output of the analog
comparator. Therefore, during any single conversion for an
“n-bit” SAR converter, there are n “windows” in which large
external transient voltages can easily affect the conversion
result. Such glitches might originate from switching power
supplies, nearby digital logic, and high-power devices.
Each 12-bit data word is returned in two bytes, as shown
below, where D11 is the MSB of the data word, and D0 is the
LSB. Byte 0 is sent first, followed by Byte 1.
MSB
6
5
4
3
2
1
LSB
BYTE 0
BYTE 1
0
0
0
0
D11
D3
D10
D2
D9
D1
D8
D0
D7
D6
D5
D4
READING IN F/S MODE
With this in mind, power to the ADS7828 should be clean and
well-bypassed. A 0.1µF ceramic bypass capacitor should be
placed as close to the device as possible. A 1µF to 10µF
capacitor may also be needed if the impedance of the
connection between +VDD and the power supply is high.
Figure 3 describes the interaction between the master and
the slave ADS7828 in Fast or Standard (F/S) mode. At the
end of reading conversion data the ADS7828 can be issued
a repeated START condition by the master to secure bus
operation for subsequent conversions of the A/D converter.
This would be the most efficient way to perform continuous
conversions.
The ADS7828 architecture offers no inherent rejection of
noise or voltage variation in regards to using an external
reference input. This is of particular concern when the
reference input is tied to the power supply. Any noise and
ripple from the supply will appear directly in the digital results.
While high-frequency noise can be filtered out, voltage varia-
tion due to line frequency (50Hz or 60Hz) can be difficult to
remove.
READING IN HS MODE
High Speed (HS) mode is fast enough that codes can be
read out one at a time. In HS mode, there is not enough time
for a single conversion to complete between the reception of
a repeated START condition and the read-addressing byte,
so the ADS7828 stretches the clock after the read-address-
ing byte has been fully received, holding it LOW until the
conversion is complete.
The GND pin should be connected to a clean ground point.
In many cases, this will be the “analog” ground. Avoid
connections that are too near the grounding point of a
microcontroller or digital signal processor. The ideal layout
will include an analog ground plane dedicated to the con-
verter and associated analog circuitry.
See Figure 4 for a typical read sequence for HS mode.
Included in the read sequence is the shift from F/S to HS
ADC Power-Down Mode
ADC Sampling Mode
S
1
0
0
1
0
A
A
W
A
SD
C
C
C
PD PD X
0
X
A
1
0
2
1
0
1
Write-AddressingByte
CommandByte
ADC Power-Down Mode
(Depends on Power-Down Selection Bits)
ADC Converting Mode
Sr
1
0
0
1
0
A
A
R
A
0
0
0
0
D
D
D
D
A
D
D
.D
D
0
N
P
1
0
11 10
9
8
7
6 . .
1
See
Note A
Read-AddressingByte
2×(8 bits + ack/not-ack)
A
N
S
P
= acknowledge (SDA Low)
= not-acknowledge (SDA High)
= START Condition
W = 0 (WRITE)
R = 1 (READ)
From master to slave
From slave to master
= STOP Condition
Sr = repeatedSTART Condition
NOTE: (A) Use repeated START to secure bus operation and loop back to the stage of write-addressing for next conversion.
FIGURE 3. Typical Read Sequence in F/S Mode.
ADS7828
SBAS181B
11
www.ti.com
F/S Mode
S
0
0
0
0
1
X
X
X
N
HS Mode Master Code
HS Mode Enabled
ADC Power-Down Mode
ADC Sampling Mode
Sr
1
0
0
1
0
A
A
W
A
SD
C
C
C
PD PD X
0
X
A
1
0
2
1
0
1
Write-AddressingByte
CommandByte
HS Mode Enabled
ADC Converting Mode
Sr
1
0
0
1
0
A
A
R
A
SCLH is stretched LOW for waiting the data converted
Return to F/S Mode (see Note A)
1
0
Read-AddressingByte
HS Mode Enabled
ADC Power-Down Mode
(Depends on Power-Down Selection Bits)
0
0
0
0
D
D
D
D
A
D
D
.D
D
0
N
P
11 10
9
8
7
6 . .
1
2×(8 bits + ack/not-ack)
A
N
S
P
= acknowledge (SDA Low)
= not-acknowledge (SDA High)
= START Condition
W = 0 (WRITE)
R = 1 (READ)
From master to slave
From slave to master
= STOP Condition
Sr = repeatedSTART Condition
NOTE: (A) Use repeated START to remain in HS mode instead of STOP.
FIGURE 4. Typical Read Sequence in HS Mode.
ADS7828
SBAS181B
12
www.ti.com
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
ADS7828E/250
ADS7828E/2K5
ADS7828EB/250
ADS7828EB/2K5
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
16
16
16
16
250
2500
250
2500
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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