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ADS7866_14 [TI]

1.2-V, 12-/10-/8-BIT, 200-KSPS/100-KSPS, MICRO-POWER, MINIATURE ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE;
ADS7866_14
型号： ADS7866_14
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

1.2-V, 12-/10-/8-BIT, 200-KSPS/100-KSPS, MICRO-POWER, MINIATURE ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE
文件： 总24页 (文件大小：532K)
中文：  中文翻译
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B u r rĆ B ro w n P ro d u ct s  
ADS7866  
ADS7867  
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ADS7868  
SLAS465–JUNE 2005  
1.2-V, 12-/10-/8-BIT, 200-KSPS/100-KSPS, MICRO-POWER, MINIATURE  
ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE  
The sampling, conversion, and activation of digital  
output SDO are initiated on the falling edge of CS.  
The serial clock SCLK is used for controlling the  
conversion rate and shifting data out of the converter.  
Furthermore, SCLK provides a mechanism to allow  
digital host processors to synchronize with the con-  
FEATURES  
•
Single 1.2-V to 3.6-V Supply Operation  
•
High Throughput  
– 200/240/280KSPS for 12/10/8-Bit VDD ≥ 1.6 V  
– 100/120/140KSPS for 12/10/8-Bit VDD ≥ 1.2 V  
±1.5LSB INL, 12-Bit NMC (ADS7866)  
verter.  
These  
converters  
interface  
with  
•
•
micro-processors or DSPs through a high-speed SPI  
compatible serial interface. There are no pipeline  
delays associated with the device.  
71 dB SNR, –83 dB THD at fIN = 30 kHz  
(ADS7866)  
•
•
•
•
Synchronized Conversion with SCLK  
SPI Compatible Serial Interface  
No Pipeline Delays  
The minimum conversion time is determined by the  
frequency of the serial clock input, SCLK, while the  
maximum frequency of SCLK is determined by the  
minimum sampling time required to charge the input  
capacitance to 12/10/8-bit accuracy for the  
Low Power  
ADS7866/67/68,  
respectively.  
The  
maximum  
– 1.39 mW Typ at 200 KSPS, VDD = 3.6 V  
– 0.39 mW Typ at 200 KSPS, VDD = 1.6 V  
– 0.22 mW Typ at 100 KSPS, VDD = 1.2 V  
Auto Power-Down: 8 nA Typ, 300 nA Max  
0 V to VDD Unipolar Input Range  
6-Pin SOT-23 Package  
throughput is determined by how often a conversion  
is initiated when the minimum sampling time is met  
and the maximum SCLK frequency is used. Each  
device automatically powers down after each conver-  
sion, which allows each device to save power when  
the throughput is reduced while using the maximum  
SCLK frequency.  
•
•
•
The converter reference is taken internally from the  
supply. Hence, the analog input range for these  
APPLICATIONS  
•
•
•
•
•
•
Battery Powered Systems  
Isolated Data Acquisition  
Medical Instruments  
Portable Communication  
Portable Data Acquisition Systems  
Automatic Test Equipment  
devices is 0 V to VDD  
.
These devices are available in a 6-pin SOT-23  
package and are characterized over the industrial  
–40°C to 85°C temperature range.  
REF/V  
DD  
DESCRIPTION  
12/10/8 BIT ADC  
Comparator  
The ADS7866/67/68 are low power, miniature,  
12/10/8-bit A/D converters each with a unipolar,  
single-ended input. These devices can operate from a  
single 1.6 V to 3.6 V supply with a 200-KSPS  
throughput for ADS7866. In addition, these devices  
can maintain at least a 100-KSPS throughput with a  
supply as low as 1.2 V.  
+
VIN  
S/H  
CDAC  
_
Conversion  
and  
Control  
Logic  
CS  
SCLK  
SDO  
SAR  
GND  
Micro-Power Miniature SAR Converter Family  
RESOLUTION/SPEED  
< 200 KSPS  
1 MSPS – 1.25 MSPS  
12-Bit  
10-Bit  
8-Bit  
ADS7866 (1.2 VDD to 3.6 VDD  
ADS7867 (1.2 VDD to 3.6 VDD  
ADS7868 (1.2 VDD to 3.6 VDD  
)
)
)
ADS7886 (2.35 VDD to 5.25 VDD  
ADS7887 (2.35 VDD to 5.25 VDD  
ADS7888 (2.35 VDD to 5.25 VDD  
)
)
)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
ADS7866  
ADS7867  
ADS7868  
www.ti.com  
SLAS465–JUNE 2005  
These devices have limited built-in ESD protection. The leads should be shorted together or the device  
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.  
ORDERING INFORMATION(1)  
MAXIMUM  
INTEGRAL  
LINEARITY  
(LSB)  
MAXIMUM  
DIFFERENTIAL  
LINEARITY  
(LSB)  
NO MISSING  
CODES  
RESOLULTION  
(BIT)  
PACKAGE  
MARKING  
(SYMBOL)  
SPECIFIED  
TEMPERATURE  
RANGE  
TRANSPORT  
MEDIA,  
QUANTITY  
PACKAGE  
TYPE  
PACKAGE  
DESIGNATOR  
ORDERING  
NUMBER  
MODEL  
ADS7866I  
ADS7866I  
ADS7867I  
ADS7867I  
ADS7868I  
ADS7868I  
±1.5  
±1.5  
±0.5  
±0.5  
±0.5  
±0.5  
–1/+1.5  
–1/+1.5  
±0.5  
12  
12  
10  
10  
8
SOT23-6  
SOT23-6  
SOT23-6  
SOT23-6  
SOT23-6  
SOT23-6  
A66Y  
A66Y  
A67Y  
A67Y  
A68Y  
A68Y  
DBV  
DBV  
DBV  
DBV  
DBV  
DBV  
–40°C to 85°C  
–40°C to 85°C  
–40°C to 85°C  
–40°C to 85°C  
–40°C to 85°C  
–40°C to 85°C  
ADS7866IDBVT  
ADS7866IDBVR  
ADS7867IDBVT  
ADS7867IDBVR  
ADS7868IDBVT  
ADS7868IDBVR  
Small tape and reel, 250  
Tape and reel, 3000  
Small tape and reel, 250  
Tape and reel, 3000  
±0.5  
±0.5  
Small tape and reel, 250  
Tape and reel, 3000  
±0.5  
8
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature range (unless otherwise noted)  
RATING  
VDD to GND  
–0.3 V to 4.0 V  
–0.3 V to VDD + 0.3 V  
–0.3 V to 4.0 V  
–0.3 V to VDD + 0.3 V  
–40°C to 85°C  
–65°C to 150°C  
150°C  
Analog input voltage to GND  
Digital input voltage to GND  
Digital output voltage to GND  
Operating free-air temperature range  
TA  
TSTORAGE Storage temperature range  
TJ  
Junction temperature  
θJA Thermal impedance  
θJC Thermal impedance  
Vapor phase (10–40 sec)  
Infrared (10–30 sec)  
110.9°C/W  
SOT-23 Package  
22.31°C/W  
250°C  
Lead temperature,  
soldering  
260°C  
ESD  
3 kV  
2
ADS7866  
ADS7867  
ADS7868  
www.ti.com  
SLAS465–JUNE 2005  
SPECIFICATIONS, ADS7866  
At –40°C to 85°C, fSAMPLE = 200 KSPS and fSCLK = 3.4 MHz if 1.6 V ≤ VDD ≤ 3.6 V; fSAMPLE = 100 KSPS and fSCLK = 1.7 MHz if  
1.2 V ≤ VDD < 1.6 V (unless otherwise noted)  
PARAMETER  
SYSTEM PERFORMANCE  
Resolution  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
12  
Bits  
Bits  
No missing codes  
12  
–1.5  
–1  
Integral linearity  
1.5 LSB(1)  
Differential linearity  
1.5  
2
LSB  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD ≤ 3.6 V  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD ≤ 3.6 V  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD ≤ 3.6 V  
–2  
Offset error(2)  
LSB  
–3  
3
–2  
2
Gain error(3)  
LSB  
LSB  
–2  
2
–2.5  
–3.5  
2.5  
3.5  
Total unadjusted error(4)  
SAMPLING DYNAMICS (See Timing Characteristics Section)  
tCONVERT Conversion time fSCLK = 3.4 MHz, 13 SCLK cycles  
fSCLK = 3.4 MHz, 1.6 V ≤ VDD ≤ 3.6 V  
3.82  
0.64  
µs  
µs  
tSAMPLE  
fSAMPLE  
Acquisition time  
Throughput rate  
Aperture delay  
Aperture jitter  
fSCLK = 3.4 MHz, 1.6 V ≤ VDD ≤ 3.6 V  
200  
KSPS  
ns  
10  
40  
ps  
DYNAMIC CHARACTERISTICS  
fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V  
fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V  
fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V  
fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V  
fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V  
fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V  
fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V  
fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V  
At 0.1 dB, 1.2 V ≤ VDD < 1.6 V  
At 0.1 dB, 1.6 V ≤ VDD ≤ 3.6 V  
At 3 dB, 1.2 V ≤ VDD < 1.6 V  
68  
70  
70  
71  
–70  
–83  
75  
85  
2
Signal-to-noise  
SINAD  
dB  
dB  
dB  
dB  
and distortion  
69  
70  
SNR  
THD  
Signal-to-noise ratio  
Total harmonic distortion(5)  
Spurious free dynamic  
range  
SFDR  
4
Full-power bandwidth(6)  
MHz  
3
At 3 dB, 1.6 V ≤ VDD ≤ 3.6 V  
8
ANALOG INPUT  
Full-scale input span(7)  
VIN – GND  
0
VDD  
V
CS  
Input capacitance  
12  
pF  
µA  
Input leakage current  
–1  
1
DIGITAL INPUT  
Logic family , CMOS  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD < 1.8 V  
1.8 V ≤ VDD < 2.5 V  
2.5 V ≤ VDD ≤ 3.6 V  
0.7×VDD  
0.7×VDD  
0.7×VDD  
2
3.6  
3.6  
3.6  
3.6  
VIH  
Input logic high level  
V
(1) LSB = Least Significant BIt  
(2) The difference in the first code transition 000...000 to 000...001 from the ideal value of GND + 1 LSB.  
(3) The difference in the last code transition 011...111 to 111...111 from the ideal value of VDD - 1 LSB with the offset error removed.  
(4) The absolute difference from the ideal transfer function of the converter. This specification is similar to INL error except the effects of  
offset error and gain error are included.  
(5) The 2nd through 10th harmonics are used to determine THD.  
(6) Input frequency where the amplitude of the digitized signal has decreased by 0.1 dB or 3 dB.  
(7) Ideal input span which does not include gain or offset errors.  
3
ADS7866  
ADS7867  
ADS7868  
www.ti.com  
SLAS465–JUNE 2005  
SPECIFICATIONS, ADS7866 (continued)  
At –40°C to 85°C, fSAMPLE = 200 KSPS and fSCLK = 3.4 MHz if 1.6 V ≤ VDD ≤ 3.6 V; fSAMPLE = 100 KSPS and fSCLK = 1.7 MHz if  
1.2 V ≤ VDD < 1.6 V (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
–0.2  
–0.2  
–0.2  
–0.2  
–1  
TYP  
MAX  
0.2×VDD  
0.2×VDD  
0.3×VDD  
0.8  
UNIT  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD < 1.8 V  
1.8 V ≤ VDD < 2.5 V  
2.5 V ≤ VDD ≤ 3.6 V  
Digital input = 0 V or VDD  
VIL  
Input logic low level  
V
ISCLK  
ICS  
SCLK pin leakage current  
CS pin leakage current  
0.02  
1
µA  
µA  
pF  
±1  
CIN  
Digital input pin capacitance  
10  
DIGITAL OUTPUT  
VOH  
VOL  
ISDO  
Output logic high level  
ISOURCE = 200 µA  
ISINK = 200 µA  
Floating output  
VDD–0.2  
VDD  
0.2  
1
V
V
Output logic low level  
0
SDO pin leakage current  
–1  
µA  
Digital output pin  
capacitance  
COUT  
Floating output  
10  
pF  
Data format, straight binary  
POWER SUPPLY REQUIREMENTS  
VDD  
IDD  
IDD  
Supply voltage  
1.2  
3.6  
V
fSAMPLE = 200 KSPS, fSCLK = 3.4 MHz, VDD = 3.6 V  
fSAMPLE = 100 KSPS, fSCLK = 3.4 MHz, VDD = 3.6 V  
fSAMPLE = 50 KSPS, fSCLK = 3.4 MHz, VDD = 3.6 V  
fSAMPLE = 20 KSPS, fSCLK = 3.4 MHz, VDD = 3.6 V  
fSAMPLE = 200 KSPS, fSCLK = 3.4 MHz, VDD = 3 V  
fSAMPLE = 100 KSPS, fSCLK = 3.4 MHz, VDD = 3 V  
fSAMPLE = 50 KSPS, fSCLK = 3.4 MHz, VDD = 3 V  
fSAMPLE = 20 KSPS, fSCLK = 3.4 MHz, VDD = 3 V  
fSAMPLE = 200 KSPS, fSCLK = 3.4 MHz, VDD = 2.5 V  
fSAMPLE = 100 KSPS, fSCLK = 3.4 MHz, VDD = 2.5 V  
fSAMPLE = 50 KSPS, fSCLK = 3.4 MHz, VDD = 2.5 V  
fSAMPLE = 20 KSPS, fSCLK = 3.4 MHz, VDD = 2.5 V  
fSAMPLE = 200 KSPS, fSCLK = 3.4 MHz, VDD = 1.8 V  
fSAMPLE = 100 KSPS, fSCLK = 3.4 MHz, VDD = 1.8 V  
fSAMPLE = 50 KSPS, fSCLK = 3.4 MHz, VDD = 1.8 V  
fSAMPLE = 20 KSPS, fSCLK = 3.4 MHz, VDD = 1.8 V  
fSAMPLE = 200 KSPS, fSCLK = 3.4 MHz, VDD = 1.6 V  
fSAMPLE = 100 KSPS, fSCLK = 3.4 MHz, VDD = 1.6 V  
fSAMPLE = 50 KSPS, fSCLK = 3.4 MHz, VDD = 1.6 V  
fSAMPLE = 20 KSPS, fSCLK = 3.4 MHz, VDD = 1.6 V  
fSAMPLE = 100 KSPS, fSCLK = 1.7 MHz, VDD = 1.2 V  
fSAMPLE = 50 KSPS, fSCLK = 1.7 MHz, VDD = 1.2 V  
fSAMPLE = 20 KSPS, fSCLK = 1.7 MHz, VDD = 1.2 V  
385  
193  
97  
500  
µA  
39  
340  
170  
85  
µA  
µA  
µA  
µA  
35  
305  
153  
77  
Supply current,  
normal operation  
Digital inputs = 0 V  
or VDD  
31  
256  
128  
65  
26  
241  
121  
61  
330  
25  
186  
93  
250  
0.3  
µA  
µA  
37  
Power-down mode  
SCLK on or off  
0.008  
POWER DISSIPATION  
fSAMPLE = 200 KSPS, fSCLK = 3.4 MHz, VDD = 3.6 V  
fSAMPLE = 200 KSPS, fSCLK = 3.4 MHz, VDD = 1.6 V  
fSAMPLE = 100 KSPS, fSCLK = 1.7 MHz, VDD = 1.2 V  
SCLK on or off, VDD = 3.6 V  
1.39  
0.39  
0.22  
1.08  
1.80  
0.53  
0.3  
Normal operation  
mW  
µW  
°C  
Power-down mode  
TEMPERATURE RANGE  
Specified performance  
–40  
85  
4
ADS7866  
ADS7867  
ADS7868  
www.ti.com  
SLAS465–JUNE 2005  
SPECIFICATIONS, ADS7867  
At –40°C to 85°C, fSAMPLE = 240 KSPS and fSCLK = 3.4 MHz if 1.6 V ≤ VDD ≤ 3.6 V; fSAMPLE = 120 KSPS and fSCLK = 1.7 MHz if  
1.2 V ≤ VDD < 1.6 V (unless otherwise noted)  
PARAMETER  
SYSTEM PERFORMANCE  
Resolution  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
10  
Bits  
Bits  
No missing codes  
10  
–0.5  
–0.5  
–0.75  
–1  
Integral linearity  
0.5  
0.5  
0.75  
1
LSB(1)  
LSB  
Differential linearity  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD ≤ 3.6 V  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD ≤ 3.6 V  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD ≤ 3.6 V  
Offset error(2)  
LSB  
LSB  
LSB  
–0.5  
–0.5  
–2  
0.5  
0.5  
2
Gain error(3)  
Total unadjusted error(4)  
–2  
2
SAMPLING DYNAMICS (See Timing Characteristics Section)  
tCONVERT Conversion time fSCLK = 3.4 MHz, 11 SCLK cycles  
fSCLK = 3.4 MHz, 1.6 V ≤ VDD ≤ 3.6 V  
3.235  
0.64  
µs  
µs  
tSAMPLE  
fSAMPLE  
Acquisition time  
Throughput rate  
Aperture delay  
Aperture jitter  
fSCLK = 3.4 MHz, 1.6 V ≤ VDD ≤ 3.6 V  
240  
KSPS  
ns  
10  
40  
ps  
DYNAMIC CHARACTERISTICS  
fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V  
fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V  
fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V  
fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V  
fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V  
fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V  
fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V  
fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V  
At 0.1 dB, 1.2 V ≤ VDD < 1.6 V  
61  
61.7  
61.5  
61.8  
-68  
-78  
73  
Signal-to-noise  
SINAD  
dB  
dB  
dB  
dB  
and distortion  
61  
SNR  
THD  
Signal-to-noise ratio  
Total harmonic distortion(5)  
Spurious free dynamic range  
-72  
SFDR  
74  
80  
2
At 0.1 dB, 1.6 V ≤ VDD ≤ 3.6 V  
4
Full-power bandwidth(6)  
MHz  
At 3 dB, 1.2 V ≤ VDD < 1.6 V  
3
At 3 dB, 1.6 V ≤ VDD ≤ 3.6 V  
8
ANALOG INPUT  
Full-scale input span(7)  
VIN – GND  
0
VDD  
V
CS  
Input capacitance  
12  
pF  
µA  
Input leakage current  
–1  
1
DIGITAL INPUT  
Logic family, CMOS  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD < 1.8 V  
1.8 V ≤ VDD < 2.5 V  
2.5 V ≤ VDD ≤ 3.6 V  
0.7×VDD  
0.7×VDD  
0.7×VDD  
2
3.6  
3.6  
3.6  
3.6  
VIH  
Input logic high level  
V
(1) LSB = Least Significant BIt  
(2) The difference in the first code transition 000...000 to 000...001 from the ideal value of GND + 1 LSB.  
(3) The difference in the last code transition 011...111 to 111...111 from the ideal value of VDD - 1 LSB with the offset error removed.  
(4) The absolute difference from the ideal transfer function of the converter. This specification is similar to INL error except the effects of  
offset error and gain error are included.  
(5) The 2nd through 10th harmonics are used to determine THD.  
(6) Input frequency where the amplitude of the digitized signal has decreased by 0.1 dB or 3 dB.  
(7) Ideal input span which does not include gain or offset errors.  
5
ADS7866  
ADS7867  
ADS7868  
www.ti.com  
SLAS465–JUNE 2005  
SPECIFICATIONS, ADS7867 (continued)  
At –40°C to 85°C, fSAMPLE = 240 KSPS and fSCLK = 3.4 MHz if 1.6 V ≤ VDD ≤ 3.6 V; fSAMPLE = 120 KSPS and fSCLK = 1.7 MHz if  
1.2 V ≤ VDD < 1.6 V (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
–0.2  
–0.2  
–0.2  
–0.2  
–1  
TYP  
MAX  
0.2×VDD  
0.2×VDD  
0.3×VDD  
0.8  
UNIT  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD < 1.8 V  
1.8 V ≤ VDD < 2.5 V  
2.5 V ≤ VDD ≤ 3.6 V  
Digital input = 0 V or VDD  
VIL  
Input logic low level  
V
ISCLK  
ICS  
SCLK pin leakage current  
CS pin leakage current  
0.02  
1
µA  
µA  
pF  
±1  
CIN  
Digital input pin capacitance  
10  
DIGITAL OUTPUT  
VOH  
VOL  
ISDO  
Output logic high level  
ISOURCE = 200 µA  
ISINK = 200 µA  
Floating output  
VDD–0.2  
VDD  
0.2  
1
V
V
Output logic low level  
0
SDO pin leakage current  
–1  
µA  
Digital output pin  
capacitance  
COUT  
Floating output  
10  
pF  
Data format, straight binary  
POWER SUPPLY REQUIREMENTS  
VDD  
IDD  
IDD  
Supply voltage  
1.2  
3.6  
V
fSAMPLE = 240 KSPS, fSCLK = 3.4 MHz, VDD = 3.6 V  
fSAMPLE = 100 KSPS, fSCLK = 3.4 MHz, VDD = 3.6 V  
fSAMPLE = 240 KSPS, fSCLK = 3.4 MHz, VDD = 1.6 V  
fSAMPLE = 100 KSPS, fSCLK = 3.4 MHz, VDD = 1.6 V  
fSAMPLE = 120 KSPS, fSCLK = 1.7 MHz, VDD = 1.2 V  
fSAMPLE = 50 KSPS, fSCLK = 1.7 MHz, VDD = 1.2 V  
420  
172  
261  
107  
202  
83  
500  
µA  
330  
250  
0.3  
Supply current,  
normal operation  
Digital Inputs = 0 V  
or VDD  
µA  
µA  
µA  
Power-down mode  
SCLK on or off  
0.008  
POWER DISSIPATION  
fSAMPLE = 240 KSPS, fSCLK = 3.4 MHz, VDD = 3.6 V  
fSAMPLE = 240 KSPS, fSCLK = 3.4 MHz, VDD = 1.6 V  
fSAMPLE = 120 KSPS, fSCLK = 1.7 MHz, VDD = 1.2 V  
SCLK on or off, VDD = 3.6 V  
1.51  
0.42  
0.24  
1.80  
0.53  
0.30  
1.08  
Normal operation  
mW  
µW  
°C  
Power-down mode  
TEMPERATURE RANGE  
Specified performance  
–40  
85  
6
ADS7866  
ADS7867  
ADS7868  
www.ti.com  
SLAS465–JUNE 2005  
SPECIFICATIONS, ADS7868  
At –40°C to 85°C, fSAMPLE = 280 KSPS and fSCLK = 3.4 MHz if 1.6 V ≤ VDD ≤ 3.6 V; fSAMPLE = 140 KSPS and fSCLK = 1.7 MHz if  
1.2 V ≤ VDD < 1.6 V (unless otherwise noted)  
PARAMETER  
SYSTEM PERFORMANCE  
Resolution  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
8
Bits  
Bits  
No missing codes  
Integral linearity  
8
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
–1  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
1
LSB(1)  
LSB  
Differential linearity  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD ≤ 3.6 V  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD ≤ 3.6 V  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD ≤ 3.6 V  
Offset error(2)  
LSB  
LSB  
LSB  
Gain error(3)  
Total unadjusted error(4)  
–1  
1
SAMPLING DYNAMICS (See Timing Characteristics Section)  
tCONVERT Conversion time fSCLK = 3.4 MHz, 9 SCLK cycles  
2.647  
0.64  
µs  
µs  
tSAMPLE  
fSAMPLE  
Acquisition time  
Throughput rate  
Aperture delay  
Aperture jitter  
fSCLK = 3.4 MHz, 1.6 V ≤ VDD ≤ 3.6 V  
fSCLK = 3.4 MHz, 1.6 V ≤ VDD ≤ 3.6 V  
280  
KSPS  
ns  
10  
40  
ps  
DYNAMIC CHARACTERISTICS  
fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V  
fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V  
fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V  
fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V  
fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V  
fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V  
fSAMPLE = 100 KSPS, fIN = 30 kHz, 1.2 V ≤ VDD < 1.6 V  
fSAMPLE = 200 KSPS, fIN = 30 kHz, 1.6 V ≤ VDD ≤ 3.6 V  
At 0.1 dB, 1.2 V ≤ VDD < 1.6 V  
49  
49.4  
49.4  
49.8  
–65  
–72  
67  
Signal-to-noise  
SINAD  
dB  
dB  
dB  
dB  
and distortion  
49  
SNR  
THD  
Signal-to-noise ratio  
Total harmonic  
distortion(5)  
-66  
Spurious free dynamic  
range  
SFDR  
66  
67  
2
At 0.1 dB, 1.6 V ≤ VDD ≤ 3.6 V  
4
Full-power bandwidth(6)  
MHz  
At 3 dB, 1.2 V ≤ VDD < 1.6 V  
3
At 3 dB, 1.6 V ≤ VDD ≤ 3.6 V  
8
ANALOG INPUT  
Full-scale input span(7)  
VIN – GND  
0
VDD  
V
CS  
Input capacitance  
12  
pF  
µA  
Input leakage current  
–1  
1
DIGITAL INPUT  
Logic family, CMOS  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD < 1.8 V  
1.8 V ≤ VDD < 2.5 V  
2.5 V ≤ VDD ≤ 3.6 V  
0.7×VDD  
0.7×VDD  
0.7×VDD  
2
3.6  
3.6  
3.6  
3.6  
VIH  
Input logic high level  
V
(1) LSB = Least Significant BIt  
(2) The difference in the first code transition 000...000 to 000...001 from the ideal value of GND + 1 LSB.  
(3) The difference in the last code transition 011...111 to 111...111 from the ideal value of VDD - 1 LSB with the offset error removed.  
(4) The absolute difference from the ideal transfer function of the converter. This specification is similar to INL error except the effects of  
offset error and gain error are included.  
(5) The 2nd through 10th harmonics are used to determine THD.  
(6) Input frequency where the amplitude of the digitized signal has decreased by 0.1 dB or 3 dB.  
(7) Ideal input span which does not include gain or offset errors.  
7
ADS7866  
ADS7867  
ADS7868  
www.ti.com  
SLAS465–JUNE 2005  
SPECIFICATIONS, ADS7868 (continued)  
At –40°C to 85°C, fSAMPLE = 280 KSPS and fSCLK = 3.4 MHz if 1.6 V ≤ VDD ≤ 3.6 V; fSAMPLE = 140 KSPS and fSCLK = 1.7 MHz if  
1.2 V ≤ VDD < 1.6 V (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
–0.2  
–0.2  
–0.2  
–0.2  
–1  
TYP  
MAX  
0.2×VDD  
0.2×VDD  
0.3×VDD  
0.8  
UNIT  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD < 1.8 V  
1.8 V ≤ VDD < 2.5 V  
2.5 V ≤ VDD ≤ 3.6 V  
VIL  
Input logic low level  
V
ISCLK  
ICS  
SCLK pin leakage current Digital input = 0 V or VDD  
CS pin leakage current  
0.02  
1
µA  
µA  
±1  
Digital input pin  
capacitance  
CIN  
10  
pF  
DIGITAL OUTPUT  
VOH  
VOL  
ISDO  
Output logic high level  
Output logic low level  
ISOURCE = 200 µA  
ISINK = 200 µA  
VDD–0.2  
VDD  
0.2  
1
V
V
0
SDO pin leakage current Floating output  
–1  
µA  
Digital output pin  
Floating output  
capacitance  
COUT  
10  
pF  
Data format, straight  
binary  
POWER SUPPLY REQUIREMENTS  
VDD  
IDD  
IDD  
Supply voltage  
1.2  
3.6  
V
fSAMPLE = 280 KSPS, fSCLK = 3.4 MHz, VDD = 3.6 V  
fSAMPLE = 100 KSPS, fSCLK = 3.4 MHz, VDD = 3.6 V  
fSAMPLE = 280 KSPS, fSCLK = 3.4 MHz, VDD = 1.6 V  
fSAMPLE = 100 KSPS, fSCLK = 3.4 MHz, VDD = 1.6 V  
fSAMPLE = 140 KSPS, fSCLK = 1.7 MHz, VDD = 1.2 V  
fSAMPLE = 50 KSPS, fSCLK = 1.7 MHz, VDD = 1.2 V  
439  
154  
264  
93  
500  
µA  
330  
250  
0.3  
Supply current,  
normal operation  
Digital Inputs = 0 V  
or VDD  
µA  
201  
70  
µA  
µA  
Power-down mode  
SCLK on or off  
0.008  
POWER DISSIPATION  
fSAMPLE = 280 KSPS, fSCLK = 3.4 MHz, VDD = 3.6 V  
fSAMPLE = 280 KSPS, fSCLK = 3.4 MHz, VDD = 1.6 V  
fSAMPLE = 140 KSPS, fSCLK = 1.7 MHz, VDD = 1.2 V  
SCLK on or off, VDD = 3.6 V  
1.58  
0.42  
0.24  
1.8  
0.53  
0.3  
Normal operation  
mW  
µW  
°C  
Power-down mode  
TEMPERATURE RANGE  
Specified performance  
1.08  
–40  
85  
8
ADS7866  
ADS7867  
ADS7868  
www.ti.com  
SLAS465–JUNE 2005  
TIMING REQUIREMENTS(1)(2)  
At –40°C to 85°C, fSCLK = 3.4 MHz if 1.6 V ≤ VDD ≤ 3.6 V; fSCLK = 1.7 MHz if 1.2 V ≤ VDD < 1.6 V, 50-pF Load on SDO Pin,  
unless otherwise noted  
PARAMETER  
Sample time  
TEST CONDITIONS  
MIN  
TYP  
tSU(CSF-FSCLKF) + 2 × tC(SCLK)  
13 × tC(SCLK)  
MAX  
UNIT  
tsample  
µs  
ADS7866  
tconvert  
Conversion time  
ADS7867  
11 × tC(SCLK)  
µs  
µs  
ADS7868  
9 × tC(SCLK)  
(3)  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD < 1.8 V  
1.8 V ≤ VDD < 2.5 V  
2.5 V ≤ VDD ≤ 3.6 V  
See  
100  
100  
(3)  
(3)  
(3)  
See  
See  
See  
tC(SCLK)  
Cycle time  
50  
6.7  
tWH(SCLK)  
tWL(SCLK)  
Pulse duration  
Pulse duration  
0.4 × tC(SCLK)  
0.6 × tC(SCLK)  
0.6 × tC(SCLK)  
ns  
ns  
0.4 × tC(SCLK)  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD < 1.8 V  
1.8 V ≤ VDD ≤ 3.6 V  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD < 1.8 V  
1.8 V ≤ VDD ≤ 3.6 V  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD < 1.8 V  
1.8 V ≤ VDD ≤ 3.6 V  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD < 1.8 V  
1.8 V ≤ VDD ≤ 3.6 V  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD < 1.8 V  
1.8 V ≤ VDD ≤ 3.6 V  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD < 1.8 V  
1.8 V ≤ VDD ≤ 3.6 V  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD < 1.8 V  
1.8 V ≤ VDD ≤ 3.6 V  
192  
55  
tSU(CSF-FSCLKF)  
Setup time  
Delay time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
55  
65  
55  
55  
tD(CSF-SDOVALID)  
20  
10  
10  
tH(SCLKF-SDOVALID) Hold time  
140  
140  
140  
80  
tD(SCLKF-SDOVALID) Delay time  
10  
7
tDIS(EOC-SDOZ)  
Disable time  
Pulse duration  
Setup time  
60  
7
60  
20  
10  
10  
20  
10  
10  
tWH(CS)  
tSU(LSBZ-CSF)  
(1) All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.  
(2) See timing diagram in Figure 1.  
(3) Min tC(SCLK) is determined by the Min tSAMPLE of the specific resolution and supply voltage. See Acquisition Time, Conversion Time, and  
Total Cycle Time section for further details.  
t
C(SCLK)  
Last SCLK= 16 for ADS7866  
14for ADS 7867  
HOLD  
3
EOC  
12for ADS 7868  
16  
14  
12  
t
WH(SCLK)  
6 7  
t
SU(CSF−FSCLKF)  
2
1
4
9
2
5
8
10  
1
SCLK  
t
WL(SCLK)  
t
WH(CS)  
t
SU(CSF−FSCLKF)  
CS  
t
SAMPLE  
t
t
CONVERT  
SU(LSBZ−CSF)  
t
t
t
DIS(EOC−SDOZ)  
H(SCLKF−SDOVALID)  
D(SCLKF−SDOVALID)  
t
D(CSF−SDOVALID)  
t
D(CSF−SDOVALID)  
Hi−Z  
Hi−Z  
SDO  
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5  
LSB  
“0” “0”  
“0”  
“0” “0”  
“0” “0”  
−
−
Auto Power Down  
Auto Power Down  
t
CYCLE  
Figure 1. Timing Diagram  
9
 
ADS7866  
ADS7867  
ADS7868  
www.ti.com  
SLAS465–JUNE 2005  
PIN CONFIGURATION  
ADS7866/67/68  
DBV PACKAGE  
(TOP VIEW)  
1
2
3
6
5
4
CS  
REF/V  
DD  
SDO  
SCLK  
GND  
VIN  
TERMINAL FUNCTIONS  
TERMINAL  
DESCRIPTION  
NAME  
REF/VDD  
GND  
NO.  
1
External reference input and power supply  
2
Ground for signal and power supply. All analog and digital signals are referred with respect to this pin.  
Analog signal input  
VIN  
3
SCLK  
4
Serial clock input. This clock is used for clocking data out, and it is the source of conversion clock.  
This is the serial data output of the conversion result. The serial stream comes with MSB first. The MSB is clocked out  
(changed) on the falling edge one SCLK after the sampling period ends. This results in four leading zeros after CS  
becomes active. SDO is 3-stated once all the valid bits are clocked out (12 for ADS7866, 10 for ADS7867, and 8 for  
ADS7868).  
SDO  
CS  
5
6
This is an active low input signal. It is used as a chip select to gate the SCLK input, to initiate a conversion, and to  
frame output data.  
10  
ADS7866  
ADS7867  
ADS7868  
www.ti.com  
SLAS465–JUNE 2005  
TYPICAL CHARACTERISTICS ADS7866  
FFT (8192 Points)  
0
−10  
V
= 1.6 V,  
DD  
f
= 200 kSPS,  
SAMPLE  
−20  
−30  
−40  
−50  
−60  
−70  
−80  
−90  
−100  
f = 30 kHz,  
SNR = 72.31 dB,  
SINAD = 71.97 dB,  
THD (9) = −83.18 dB,  
SFDR = 86.83 dB  
i
0
10  
20  
30  
40  
50  
60  
70  
80  
90  
100  
f − Input Frquency − kHz  
i
Figure 2.  
FFT (8192 Points)  
0
−10  
−20  
−30  
−40  
−50  
−60  
V
= 1.2 V,  
DD  
f
= 100 kSPS,  
SAMPLE  
f = 30 kHz,  
i
SNR = 71.42 dB,  
SINAD = 67.62 dB,  
THD (9) = −69.96 dB,  
SFDR = 75.14 dB  
−70  
−80  
−90  
−100  
0
5
10  
15  
20  
25  
30  
35  
40  
45  
50  
f − Input Frquency − kHz  
i
Figure 3.  
SIGNAL-TO-NOISE RATIO  
vs  
SIGNAL-TO-NOISE  
AND DISTORTION  
vs  
TOTAL HARMONIC DISTORTION  
vs  
INPUT FREQUENCY  
INPUT FREQUENCY  
INPUT FREQUENCY  
73  
72.5  
72  
−56  
−58  
−60  
−62  
−64  
−66  
−68  
−70  
−72  
−74  
−76  
−78  
73  
71  
69  
67  
65  
63  
61  
59  
57  
THD Using 2nd − 10th harmonics,  
V
DD  
= 3.6 V, 200 KSPS  
T
A
= 25°C  
V
DD  
= 2.5 V, 200 KSPS  
V
= 3.6 V,  
DD  
V
= 1.2 V,  
DD  
V
= 2.5 V,  
200 KSPS  
DD  
100 KSPS  
200 KSPS  
71.5  
71  
V
DD  
= 1.6 V, 200 KSPS  
70.5  
70  
V
= 1.6 V,  
DD  
V
= 1.2 V,  
V
= 2.5 V,  
DD  
V
= 1.6 V,  
DD  
DD  
200 KSPS  
100 KSPS  
200 KSPS  
200 KSPS  
V
= 1.2 V,  
DD  
100 KSPS  
69.5  
69  
68.5  
68  
V
= 3.6V,  
DD  
−80  
−82  
67.5  
67  
200 KSPS  
10  
100  
1000  
10  
1
1
10  
100  
1000  
100  
1000  
1
f − Input Frequency − kHz  
i
f − Input Frequency − kHz  
i
f − Input Frequency − kHz  
i
Figure 4.  
Figure 5.  
Figure 6.  
11  
ADS7866  
ADS7867  
ADS7868  
www.ti.com  
SLAS465–JUNE 2005  
TYPICAL CHARACTERISTICS ADS7866 (continued)  
SPURIOUS FREE DYNAMIC RANGE  
SUPPLY CURRENT  
SUPPLY CURRENT  
vs  
vs  
vs  
INPUT FREQUENCY  
SCLK FREQUENCY  
SUPPLY VOLTAGE  
425  
400  
375  
350  
325  
300  
275  
250  
84  
82  
325  
300  
V
= 3.6V,  
f
f
= 200 KSPS,  
DD  
200 KSPS  
T
= 25°C,  
SAMPLE  
SCLK  
A
V
DD  
= 3.6 V  
= 3.4 MHz  
f
= 100 KSPS  
SAMPLE  
T
A
= 855C  
V
DD  
= 3 V  
80  
78  
V
= 2.5 V  
DD  
V
= 2.5V,  
DD  
200 KSPS  
275  
250  
225  
T
A
= 255C  
V
DD  
= 1.8 V  
V
= 1.6 V  
DD  
T
A
= −405C  
76  
74  
72  
70  
68  
66  
64  
62  
V
= 1.6 V,  
200 KSPS  
DD  
200  
175  
150  
V
DD  
= 1.2 V, 100 KSPS  
125  
100  
225  
200  
10  
− Input Frequency − kHz  
100  
1000  
1
1.6 1.8  
2
2.2 2.4 2.6 2.8  
3
3.2 3.4  
1.6 1.8  
2
2.2 2.4 2.6 2.8  
3
3.2 3.4 3.6  
f
i
SCLK Frequency − MHz  
V
DD  
− Supply Voltage − V  
Figure 7.  
Figure 8.  
Figure 9.  
POWER CONSUMPTION  
TOTAL HARMONIC DISTORTION  
vs  
vs  
THROUGHPUT  
INPUT FREQUENCY  
1.4  
1.2  
1
−58  
−60  
−62  
−64  
T
= 25°C,  
A
V
T
= 1.6 V,  
DD  
A
SCLK = 3.4 MHz  
V
= 3.6 V  
= 25°C,  
DD  
f
f
= 200 KSPS,  
SAMPLE  
= 3.4 MHz  
SCLK  
V
= 3 V  
DD  
V
= 2.5 V  
DD  
−66  
−68  
−70  
−72  
−74  
−76  
V
= 1.8 V  
DD  
0.8  
0.6  
0.4  
0.2  
0
V
DD  
= 1.6 V  
R
= 100 W  
I
R
I
= 500 W  
R
= 1000 W  
I
−78  
−80  
−82  
−84  
R
I
= 0 W  
R
I
= 10 W  
20 40  
60 80 100 120 140 160 180 200  
Throughput − KSPS  
1
10  
100  
1000  
f
i
− Input Frequency − kHz  
Figure 10.  
Figure 11.  
INL  
1
V
= 1.6 V,  
DD  
0.8  
0.6  
T = 25°C,  
A
f
f
= 200 KSPS,  
= 3.4 MHz  
SAMPLE  
SCLK  
0.4  
0.2  
0
−0.2  
−0.4  
−0.6  
−0.8  
−1  
0
512  
1024  
1536  
2048  
Code  
2560  
3072  
3584  
4096  
(Straight Binary in Decimal)  
Figure 12.  
12  
 
 
ADS7866  
ADS7867  
ADS7868  
www.ti.com  
SLAS465–JUNE 2005  
TYPICAL CHARACTERISTICS ADS7866 (continued)  
DNL  
1
V
= 1.6 V,  
DD  
0.8  
0.6  
0.4  
0.2  
0
T = 25°C,  
A
f
f
= 200 KSPS,  
= 3.4 MHz  
SAMPLE  
SCLK  
−0.2  
−0.4  
−0.6  
−0.8  
0
512  
1024  
1536  
2048  
2560  
3072  
3584  
4096  
Code  
(Straight Binary in Decimal)  
Figure 13.  
INL  
1
0.8  
V
= 1.2 V,  
DD  
T = 25°C,  
A
f
f
= 100 KSPS,  
= 1.7 MHz  
0.6  
SAMPLE  
SCLK  
0.4  
0.2  
0
−0.2  
−0.4  
−0.6  
−0.8  
−1  
0
512  
1024  
1536  
2048  
2560  
3072  
3584  
4096  
Code  
(Straight Binary in Decimal)  
Figure 14.  
DNL  
1
0.8  
0.6  
0.4  
0.2  
0
V
= 1.2 V,  
DD  
T = 25°C,  
A
f
f
= 100 KSPS,  
= 1.7 MHz  
SAMPLE  
SCLK  
−0.2  
−0.4  
−0.6  
−0.8  
0
512  
1024  
1536  
2048  
2560  
3072  
3584  
4096  
Code  
(Straight Binary in Decimal)  
Figure 15.  
13  
ADS7866  
ADS7867  
ADS7868  
www.ti.com  
SLAS465–JUNE 2005  
TYPICAL CHARACTERISTICS ADS7866 (continued)  
MAX SUPPLY CURRENT  
vs  
THROUGHPUT RATE  
THROUGHPUT RATE  
vs  
vs  
SUPPLY VOLTAGE  
SUPPLY VOLTAGE  
SUPPLY VOLTAGE  
425  
400  
375  
350  
325  
300  
275  
250  
300  
275  
250  
225  
200  
450  
425  
400  
375  
12-Bit NMC, T = 25°C,  
T
= 25°C,  
A
A
f
= (f  
)/16  
t
t
= 2.375/f  
,
SAMPLE  
SCLK  
SAMPLE  
SCLK  
+t  
= 0.375/f  
,
DIS(EOC-SDOZ) SU(LSBZ-CSF)  
SCLK  
Throughput Rate = 16 SCLK Cycles  
f
= 3.4 MHz  
SCLK  
f
= 2.4 MHz  
SCLK  
f
= 1.7 MHz  
350  
325  
300  
275  
250  
SCLK  
12-Bit NMC, T = 25°C,  
175  
150  
A
t
t
= 2.25/f  
,
SAMPLE  
DIS(EOC-SDOZ) SU(LSBZ-CSF)  
SCLK  
225  
200  
+t  
= 0.25/f  
,
SCLK  
Throughput Rate = 16 SCLK Cycles  
1.2  
1.4  
V − Supply Voltage − V  
DD  
1.6  
1.8  
1.6 1.8  
2
2.2 2.4 2.6 2.8  
3
3.2 3.4 3.6  
1.2 1.4 1.6 1.8  
2
2.2 2.4 2.6 2.8  
− Supply Voltage − V  
3
3.2 3.4 3.6  
V
V
DD  
− Supply Voltage − V  
DD  
Figure 16.  
Figure 17.  
Figure 18.  
14  
ADS7866  
ADS7867  
ADS7868  
www.ti.com  
SLAS465–JUNE 2005  
TYPICAL CHARACTERISTICS ADS7867  
FFT (8192 Points)  
0
−10  
−20  
−30  
−40  
V
= 1.2 V,  
DD  
f
= 100 KSPS,  
SAMPLE  
f = 30 kHz,  
i
SNR = 60.419 dB,  
SINAD = 59.877 dB,  
THD (9) = −69.181 dB,  
SFDR = 73.682 dB  
−50  
−60  
−70  
−80  
−90  
−100  
0
5
10  
15  
20  
25  
30  
35  
40  
45  
50  
f − Input Frequency − kHz  
i
Figure 19.  
FFT (8192 Points)  
0
−10  
−20  
−30  
−40  
−50  
−60  
−70  
−80  
−90  
−100  
V
= 1.6 V,  
DD  
f
= 200 KSPS,  
SAMPLE  
f = 30 kHz,  
i
SNR = 61.173 dB,  
SINAD = 61.128 dB,  
THD (9) = −80.986 dB,  
SFDR = 83.468 dB  
0
10  
20  
30  
40  
50  
60  
70  
80  
90  
100  
f − Input Frequency − kHz  
i
Figure 20.  
THROUGHPUT RATE  
vs  
SUPPLY VOLTAGE  
THROUGHPUT RATE  
vs  
SUPPLY VOLTAGE  
450  
425  
400  
375  
350  
325  
300  
275  
250  
275  
250  
225  
200  
10-Bit NMC, T = 25°C,  
A
175  
150  
t
t
= 2.25/f  
,
SAMPLE  
DIS(EOC-SDOZ) SU(LSBZ-CSF)  
SCLK  
10-Bit NMC, T = 25°C,  
A
+t  
= 0.25/f  
,
SCLK  
t
t
= 2.375/f  
,
SAMPLE  
DIS(EOC-SDOZ) SU(LSBZ-CSF)  
SCLK  
Throughput Rate = 14 SCLK Cycles  
+t  
= 0.375/f  
,
SCLK  
Throughput Rate = 14 SCLK Cycles  
1.6 1.8  
2
2.2 2.4 2.6 2.8  
3
3.2 3.4 3.6  
1.2  
1.4  
1.6  
1.8  
V
DD  
− Supply Voltage − V  
V
DD  
− Supply Voltage − V  
Figure 21.  
Figure 22.  
15  
ADS7866  
ADS7867  
ADS7868  
www.ti.com  
SLAS465–JUNE 2005  
TYPICAL CHARACTERISTICS ADS7868  
FFT (8192 Points)  
0
−10  
−20  
−30  
−40  
−50  
−60  
−70  
−80  
−90  
V
= 1.2 V,  
DD  
f
= 100 KSPS,  
SAMPLE  
f = 30 kHz,  
i
SNR = 48.669 dB,  
SINAD = 48.605 dB,  
THD (9) = −66.910 dB,  
SFDR = 67.041 dB  
10  
15  
0
5
20  
25  
30  
35  
40  
45  
50  
f − Input Frequency − kHz  
i
Figure 23.  
FFT (8192 Points)  
0
−10  
−20  
−30  
−40  
−50  
−60  
−70  
−80  
−90  
V
= 1.6 V,  
DD  
f
= 200 KSPS,  
SAMPLE  
f = 30 kHz,  
i
SNR = 49.420 dB,  
SINAD = 49.413 dB,  
THD (9) = −77.085 dB,  
SFDR = 67.893 dB  
0
10  
20  
30  
40  
50  
60  
70  
80  
90  
100  
f − Input Frequency − kHz  
i
Figure 24.  
THROUGHPUT RATE  
vs  
SUPPLY VOLTAGE  
THROUGHPUT RATE  
vs  
SUPPLY VOLTAGE  
300  
275  
250  
225  
575  
550  
525  
500  
475  
450  
425  
400  
375  
350  
200  
175  
8-Bit NMC, T = 25°C,  
A
8-Bit NMC, T = 25°C,  
A
t
t
= 2.375/f  
,
SAMPLE  
DIS(EOC-SDOZ) SU(LSBZ-CSF)  
SCLK  
t
t
= 2.25/f  
,
SAMPLE  
DIS(EOC-SDOZ) SU(LSBZ-CSF)  
Throughput Rate = 12 SCLK Cycles  
SCLK  
+t  
= 0.375/f  
,
SCLK  
+t  
= 0.25/f  
,
325  
300  
SCLK  
Throughput Rate = 12 SCLK Cycles  
150  
1.2  
1.4  
1.6  
1.8  
1.6 1.8  
2
2.2 2.4 2.6 2.8  
3
3.2 3.4 3.6  
V
DD  
− Supply Voltage − V  
V
DD  
− Supply Voltage − V  
Figure 25.  
Figure 26.  
16  
ADS7866  
ADS7867  
ADS7868  
www.ti.com  
SLAS465–JUNE 2005  
THEORY OF OPERATION  
The ADS7866/67/68 is a family of low supply voltage, low power, high-speed successive approximation register  
(SAR) analog-to-digital converters (ADCs). The devices can be operated from a supply range from 1.2 V to 3.6  
V. There is no need for an external reference. The reference is derived internally from the supply voltage, so the  
analog input range can be from 0 V to VDD. These ADCs use a charge redistribution architecture, which  
inherently includes a sample/hold function.  
START OF A CONVERSION CYCLE  
A conversion cycle is initiated by bringing the CS pin low and supplying the serial clock SCLK. The time between  
the falling edge of CS and the third falling edge of SCLK after CS falls is used to acquire the input signal. This  
must be greater than or equal to the minimum acquisition time (MIN tSAMPLE in Table 1) specified for the desired  
resolution and supply voltage. On the third falling edge of SCLK after CS falls, the device goes into hold mode  
and the process of digitizing the sampled input signal starts.  
Acquisition Time, Conversion Time, and Total Cycle Time  
The maximum SCLK frequency is determined by the minimum acquisition time (MIN tSAMPLE) specified for the  
specific resolution and supply voltage of the device. The conversion time is determined by the frequency of SCLK  
since this is a synchronous converter. The conversion time is 13 times the SCLK cycle time tC(SCLK) for the  
ADS7866, 11 times for the ADS7867, and 9 times for the ADS7868. The acquisition time, which is also the  
power up time, is the set-up time between the first falling edge of SCLK after CS falls (tSU(CSF-FSCLKF)) plus 2  
times tC(SCLK)  
.
The total cycle time, tCYCLE, which is the inverse of the maximum sample rate, can be calculated as follows:  
tCYCLE = tSAMPLE + tCONVERT + 0.5 × tC(SCLK)  
if tDIS(EOC-SDOZ) + tSU(LSBZ-CSF) ≤ 0.5 × tC(SCLK)  
tCYCLE = tSAMPLE + tCONVERT + tDIS(EOC-SDOZ) + tSU(LSBZ-CSF)  
if tDIS(EOC-SDOZ) + tSU(LSBZ-CSF) > 0.5 × tC(SCLK)  
17  
ADS7866  
ADS7867  
ADS7868  
www.ti.com  
SLAS465–JUNE 2005  
THEORY OF OPERATION (continued)  
Table 1. Acquisition, Conversion, SCLK, and Potential Throughput Calculation  
PARAMETER  
SUPPLY VOLTAGE  
1.2 V ≤ VDD < 1.6 V  
ADS7866  
192  
ADS7867  
192  
ADS7868  
UNIT  
192  
55  
MIN tSU(CSF-FSCLKF)  
MAX tDIS(EOC-SDOZ)  
MIN tSU(LSBZ-CSF)  
MAX fSCLK  
Setup time  
1.6 V ≤ VDD < 1.8 V  
1.8 V ≤ VDD ≤ 3.6 V  
1.2 V ≤ VDD < 1.6V  
1.6 V ≤ VDD < 1.8 V  
1.8 V ≤ VDD ≤ 3.6 V  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD < 1.8 V  
1.8 V ≤ VDD ≤ 3.6 V  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD < 1.8 V  
1.8 V ≤ VDD ≤ 3.6 V  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD < 1.8 V  
1.8 V ≤ VDD ≤ 3.6 V  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD < 1.8 V  
1.8 V ≤ VDD ≤ 3.6 V  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD < 1.8 V  
1.8 V ≤ VDD ≤ 3.6 V  
1.2 V ≤ VDD < 1.6 V  
1.6 V ≤ VDD < 1.8 V  
1.8 V ≤ VDD ≤ 3.6 V  
55  
55  
55  
55  
ns  
ns  
55  
80  
80  
80  
Disable time  
Setup time  
60  
60  
60  
60  
60  
60  
20  
20  
20  
10  
10  
10  
ns  
10  
10  
10  
1.7  
1.7  
1.7  
Frequency  
3.4  
3.4  
3.4  
MHz  
ns  
3.4  
3.4  
3.4  
1368  
643  
643  
7647  
3824  
3824  
9116  
4537  
4537  
110  
220  
220  
1368  
643  
643  
6471  
3235  
3235  
7939  
3949  
3949  
126  
253  
253  
1368  
643  
643  
5294  
2647  
2647  
6763  
3360  
3360  
148  
298  
298  
MIN tsample  
Sample time  
Conversion time  
Cycle time  
MIN tconvert  
ns  
MIN tCYCLE  
ns  
Theoretical sample fre-  
quency  
fsample  
KSPS  
TYPICAL CONNECTION  
For a typical connection circuit for the ADS7866/67/68 see Figure 27. A REF3112 is used to supply 1.2 V to the  
device. A 0.1-µF decoupling capacitor is required between the REF/VDD and GND pins of the converter. This  
capacitor should be placed as close as possible to the pins of the device. Designers should strive to minimize the  
routing length of the traces that connect the terminals of the capacitor to the pins of the converter.  
Keep in mind the converter offers no inherent rejection of noise or voltage variation in regards to the reference  
input. This is of particular concern because the reference input is tied to the power supply. Any noise and ripple  
from the supply appears directly in the digital results. While high frequency noise can be filtered out as described  
in the previous paragraph, voltage variation due to the line frequency (50 Hz or 60 Hz) can be difficult to remove.  
1.8 V  
REF3112  
1.2 V  
GND  
0.1 mF  
Host  
Processor  
REF/V  
GND  
DD  
CS  
SS  
ADS7866/67/68  
SCK  
SCLK  
VIN  
Analog Input  
MISO  
SDO  
Figure 27. Typical Circuit Configuration  
18  
 
ADS7866  
ADS7867  
ADS7868  
www.ti.com  
SLAS465–JUNE 2005  
ANALOG INPUT  
Figure 28 shows the analog input equivalent circuit for the ADS7866/67/68. The analog input is provided  
between the VIN and GND pins. When a conversion is initiated, the input signal is sampled on the internal  
capacitor array. When the converter enters hold mode, the input signal is captured on the internal capacitor  
array. The VIN input range is limited to 0 V to VDD because the reference is derived from the supply.  
The current flowing into the analog input depends upon a number of factors, such as the sample rate, the input  
voltage, and the input source impedance. The current from the input source charges the internal capacitor array  
during the sample period. After this capacitance has been fully charged, there is no further input current. The  
source of the analog input voltage must be able to charge the input capacitance CS (12 pF typical) within the  
minimum acquisition time (MIN tSAMPLE) specified for the desired resolution and supply voltage. In the case of the  
ADS7866, the MIN tSAMPLE for 12-bit resolution is 643 ns (VDD between 1.6 V and 3.6 V). When the converter  
goes into hold mode, the input impedance is greater than 1 GΩ.  
Care must be taken regarding the absolute analog input voltage. In order to maintain the linearity of the  
converter, the span (VIN – GND) should be within the limits specified. Outside of these limits, the converter’s  
linearity may not meet specifications. Noise introduced into the converter from the input source may be  
minimized by using low bandwidth input signals along with low-pass filters.  
V
DD  
Device is in Hold Mode  
12 pF  
60 W  
VIN  
+
4 pF  
2.105 kW  
_
V
MID  
GND  
Figure 28. Analog Input Equivalent Circuit (Typical Impedance Values at VDD = 1.6 V, TA = 27°C)  
Choice of Input Driving Amplifier  
The analog input to the converter needs to be driven with a low noise, low voltage op amp like the OPA364 or  
OPA333. An RC filter is recommended at the input pin to low-pass filter the noise from the source. The input to  
the converter is a unipolar input voltage in the range 0 V to VDD  
.
DIGITAL INTERFACE  
The ADS7866/67/68 interface with microprocessors or DSPs through a high-speed SPI compatible serial  
interface with CPOL = 1 (inactive SCLK returns to logic high or SCLK leading edge is the rising edge), CPHA = 1  
(output data changes on falling edge of SCLK and is available on the rising edge of SCLK). The sampling,  
conversion, and activation of SDO are initiated on the falling edge of CS. The serial clock (SCLK) is used for  
controlling the rate of conversion. It also provides a mechanism allowing synchronization with digital host  
processors.  
The digital inputs, CS and SCLK, can exceed the supply voltage VDD as long as they do not exceed the  
maximum VIH of 3.6 V. This allows the ADS7866/67/68 family to interface with host processors which use a  
different supply voltage than the converter without requiring external level-shifting circuitry. Furthermore, the  
digital inputs can be applied to CS and SCLK before the supply voltage of the converter is activated without the  
risk of creating a latch-up condition.  
Conversion Result  
The ADS7866/67/68 outputs 12/10/8-bit data after 4 leading zeros, respectively. These codes are in straight  
binary format as shown in Table 2.  
19  
 
ADS7866  
ADS7867  
ADS7868  
www.ti.com  
SLAS465–JUNE 2005  
The serial output SDO is activated on the falling edge of CS. The first leading zero is available on SDO until the  
first falling edge of SCLK after CS falls. The remaining 3 leading zeros are shifted out on SDO on the first,  
second, and third falling edges of SCLK after CS falls. The MSB of the converted result follows 4 leading zeros  
and is clocked out on the fourth falling edge of SCLK. The rising edge of CS or the falling edge of SCLK when  
the EOC occurs puts SDO output into 3-state. Refer to Table 2 for ideal output codes versus input voltages.  
Table 2. ADS7866/67/68 Ideal Output Codes Versus Input Voltages  
DIGITAL OUTPUT STRAIGHT BINARY  
DESCRIPTION  
ADS7866  
ANALOG INPUT VOLTAGE  
BINARY CODE  
HEX CODE  
Least Significant Bit (LSB)  
Full Scale  
VDD/4096  
VDD – 1LSB  
VDD/2  
1111 1111 1111  
1000 0000 0000  
0111 1111 1111  
0000 0000 0000  
FFF  
800  
7FF  
000  
Midscale  
Midscale – 1LSB  
Zero  
VDD/2 – 1LSB  
0V  
ADS7867  
Least Significant Bit (LSB)  
Full Scale  
VDD/1024  
VDD – 1LSB  
VDD/2  
11 1111 1111  
10 0000 0000  
01 1111 1111  
00 0000 0000  
3FF  
200  
1FF  
000  
Midscale  
Midscale – 1LSB  
Zero  
VDD/2 – 1LSB  
0V  
ADS7868  
Least Significant Bit (LSB)  
Full Scale  
VDD/256  
VDD – 1LSB  
VDD/2  
1111 1111  
1000 0000  
0111 1111  
0000 0000  
FF  
80  
7F  
00  
Midscale  
Midscale – 1LSB  
Zero  
VDD/2 – 1LSB  
0V  
POWER DISSIPATION  
The ADS7866/67/68 family is capable of operating with very low supply voltages while drawing a fraction of a  
milliamp. Furthermore, there is an auto power-down mode to reduce the power dissipation between conversion  
cycles. Carefully selected system design can take advantage of these features to achieve optimum power  
performance.  
Auto Power-Down Mode  
The ADS7866/67/68 family has an auto power-down feature. Besides powering down all circuitry, the converter  
consumes only 8 nA typically in this mode. The device automatically wakes up when CS falls. However, not all of  
the functional blocks are fully powered until sometime before the third falling edge of SCLK. The device powers  
down once it reaches the end of conversion (EOC) which is the 16th falling edge of SCLK for the ADS7866 (the  
14th and 12th for the ADS7867 and ADS7868, respectively). If CS is pulled high before the device reaches the  
EOC, the converter goes into power-down mode and the ongoing conversion is aborted. Refer to the timing  
diagram in Figure 1 for further information.  
Power Saving: SCLK Frequency and Throughput  
These converters achieve lower power dissipation for a fixed throughput rate fsample = 1/tcycle by using higher  
SCLK frequencies. Higher SCLK frequencies reduce the acquisition time (tsample) and conversion time (tconvert).  
This means the converters spend more time in auto power-down mode per conversion cycle. This can be  
observed in Figure 8 which shows the ADS7866 supply current versus SCLK frequency for fsample = 100 KSPS.  
For a particular SCLK frequency, the acquisition time and conversion time are fixed. Therefore, a lower  
throughput increases the proportion of the time the converters are in power down. Figure 10 shows this case for  
the ADS7866 power consumption versus throughput rate for fSCLK = 3.4 MHz.  
20  
 
ADS7866  
ADS7867  
ADS7868  
www.ti.com  
SLAS465–JUNE 2005  
Power-On Initialization  
There is no specific initialization requirement for these converters after power-on, but the first conversion might  
not yield a valid result. In order to set the converter in a known state, CS should be toggled low then high after  
VDD has stabilized during power-on. By doing this, the converter is placed in auto power-down mode, and the  
serial data output (SDO) is 3-stated.  
21  
PACKAGE OPTION ADDENDUM  
www.ti.com  
8-Aug-2005  
PACKAGING INFORMATION  
Orderable Device  
ADS7866IDBVR  
ADS7866IDBVRG4  
ADS7866IDBVT  
ADS7866IDBVTG4  
ADS7867IDBVR  
ADS7867IDBVRG4  
ADS7867IDBVT  
ADS7867IDBVTG4  
ADS7868IDBVR  
ADS7868IDBVRG4  
ADS7868IDBVT  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SOT-23  
DBV  
6
6
6
6
6
6
6
6
6
6
6
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
DBV  
DBV  
DBV  
DBV  
DBV  
DBV  
DBV  
DBV  
DBV  
DBV  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
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Addendum-Page 1  
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ADS7867

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ADS7867I

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ADS7867IDBVR

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ADS7867IDBVR

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ADS7867IDBVRG4

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ADS7867IDBVRG4

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ADS7867IDBVT

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