ADS7881IPFBR [TI]
12-BIT, 4-MSPS LOW POWER SAR ANALOG-TO-DIGITAL CONVERTER; 12位， 4 MSPS低功耗SAR模拟数字转换器
| 型号： | ADS7881IPFBR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-BIT, 4-MSPS LOW POWER SAR ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总26页 (文件大小：335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂ ꢃꢄ ꢄꢅ
SLAS400 − SEPTEMBER 2003
ꢅꢆ ꢇ ꢈꢉ ꢊꢋ ꢌꢇ ꢍ ꢂ ꢎꢂ
ꢏ ꢐꢑ ꢎꢐꢑ ꢒꢓ ꢂꢀ ꢓ ꢀ ꢔꢀꢏ ꢐꢕ ꢇ ꢊꢐ ꢇ ꢁꢉ ꢕ ꢉꢊꢀꢏ ꢖꢐ ꢔ ꢗꢒ ꢓꢊꢒ ꢓ
FEATURES
APPLICATIONS
D
D
D
D
D
D
D
D
D
D
D
4 MHz Sample Rate, 12-Bit Resolution
Zero Latency
Unipolar, Pseudo Differential Input, Range:
− 0 V to 2.5 V
High Speed Parallel Interface
71 dB SNR and −88.5 dB THD at 1 MHz I/P
Power Dissipation 95 mW at 4 MSPS
Nap Mode (10 mW Power Dissipation)
Power Down (10 mW)
D
Optical Networking (DWDM, MEMS Based
Switching)
D
D
D
D
D
Spectrum Analyzers
High Speed Data Acquisition Systems
High Speed Close-Loop Systems
Telecommunication
Ultra-Sound Detection
Internal Reference
Internal Reference Buffer
48-Pin TQFP Package
DESCRIPTION
The ADS7881 is a 12-bit 4-MSPS A-to-D converter with
2.5-V internal reference. The device includes a capacitor
based SAR A/D converter with inherent sample and hold.
The device offers a 12-bit parallel interface with an
additional byte mode that provides easy interface with 8-bit
processors. The device has a pseudo-differential input
stage.
The −IN swing of 200 mV is useful to compensate for
ground voltage mismatch between the ADC and sensor
and also to cancel common-mode noise. With nap mode
enabled, the device operates at lower power when used at
lower conversion rates. The device is available in a 48-pin
TQFP package.
BYTE
SAR
Output
Latches
and
3-State
Drivers
+
_
+IN
−IN
CDAC
12/8-Bit Parallel
Data Output Bus
Comparator
CLOCK
REFIN
CONVST
Conversion
and
Control Logic
BUSY
CS
2.5 V
RD
REFOUT
Internal
Reference
PWD/RST
A_PWD
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢎꢓ ꢐ ꢁꢘ ꢖ ꢊꢉ ꢐꢔ ꢁ ꢀꢊꢀ ꢙꢚ ꢛꢜ ꢝ ꢞꢟ ꢠꢙꢜꢚ ꢙꢡ ꢢꢣ ꢝ ꢝ ꢤꢚꢠ ꢟꢡ ꢜꢛ ꢥꢣꢦ ꢧꢙꢢ ꢟꢠꢙ ꢜꢚ ꢨꢟ ꢠꢤꢩ ꢎꢝ ꢜꢨꢣ ꢢꢠꢡ
ꢢ ꢜꢚ ꢛꢜꢝ ꢞ ꢠꢜ ꢡ ꢥꢤ ꢢ ꢙ ꢛꢙ ꢢ ꢟ ꢠꢙ ꢜꢚꢡ ꢥ ꢤꢝ ꢠꢪꢤ ꢠꢤ ꢝ ꢞꢡ ꢜꢛ ꢊꢤꢫ ꢟꢡ ꢉꢚꢡ ꢠꢝ ꢣꢞ ꢤꢚꢠ ꢡ ꢡꢠ ꢟꢚꢨ ꢟꢝ ꢨ ꢬ ꢟꢝ ꢝ ꢟ ꢚꢠꢭꢩ
ꢎꢝ ꢜ ꢨꢣꢢ ꢠ ꢙꢜ ꢚ ꢥꢝ ꢜ ꢢ ꢤ ꢡ ꢡ ꢙꢚ ꢮ ꢨꢜ ꢤ ꢡ ꢚꢜꢠ ꢚꢤ ꢢꢤ ꢡꢡ ꢟꢝ ꢙꢧ ꢭ ꢙꢚꢢ ꢧꢣꢨ ꢤ ꢠꢤ ꢡꢠꢙ ꢚꢮ ꢜꢛ ꢟꢧ ꢧ ꢥꢟ ꢝ ꢟꢞ ꢤꢠꢤ ꢝ ꢡꢩ
Copyright 2003, Texas Instruments Incorporated
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SLAS400 − SEPTEMBER 2003
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
MAXIMUM
INTEGRAL
LINEARITY
(LSB)
MAXIMUM
DIFFERENTIAL
LINEARITY
(LSB)
NO MISSING
CODES AT
RESOLUTION
(BIT)
PACKAGE
TYPE
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
ORDERING
INFORMATION
TRANSPORT
MEDIA QUANTITY
MODEL
Tape and reel
250
ADS7881IPFBT
ADS7881IPFBR
48-Pin
TQFP
ADS7881
1
1
12
PFB
−40°C to 85°C
Tape and reel
1000
:
NOTE For most current specifications and package information, refer to the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range
UNIT
+IN to AGND
−0.3 V to +VA + 0.1 V
−IN to AGND
−0.3 V to 0.5 V
−0.3 V to 7 V
+VA to AGND
+VBD to BDGND
−0.3 V to 7 V
Digital input voltage to GND
Digital output to GND
Operating temperature range
Storage temperature range
−0.3 V to (+VBD + 0.3 V)
−0.3 V to (+VBD + 0.3 V)
−40°C to 85°C
−65°C to 150°C
150°C
Junction temperature (T max)
J
Power dissipation
(T Max–T )/ θ
J
A
JA
TQFP package
θ
JA
Thermal impedance
86°C/W
Vapor phase (60 sec)
Infrared (15 sec)
215°C
220°C
Lead temperature, soldering
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
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SLAS400 − SEPTEMBER 2003
SPECIFICATIONS
A
T
= −40°C to 85°C, +VA = 5 V, +VBD = 5 V or 3.3 V, V = 2.5 V, f
= 4 MHz (unless otherwise noted)
ref
sample
TEST CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
ANALOG INPUT
(1)
Full-scale input span
+IN – (−IN)
0
−0.2
−0.2
V
V
V
ref
+IN
−IN
V
ref
+ 0.2
+0.2
Absolute input range
Input capacitance
27
pF
pA
Input leakage current
SYSTEM PERFORMANCE
Resolution
500
12
Bits
Bits
No missing codes
12
−1
(2)
Integral linearity
(3)
LSB
1
1
(3)
LSB
Differential linearity
(4)
−1
Offset error
(4)
External reference
External reference
−1.5
−2
1.5
2
mV
Gain error
mV
With common mode input signal = 200
mVp−p at 1 MHz
Common-mode rejection ratio
60
80
dB
At FF0 output code,
H
+VA = 4.75 V to 5.25 V , Vref = 2.50 V
Power supply rejection
dB
SAMPLING DYNAMICS
+VDB = 5 V
+VDB = 3 V
+VDB = 5 V
+VDB = 3 V
185
65
200
205
nsec
nsec
nsec
nsec
MHz
nsec
psec
nsec
nsec
Conversion time
Acquisition time
50
45
Maximum throughput rate
Aperture delay
4
2
20
50
50
Aperture jitter
Step response
Over voltage recovery
DYNAMIC CHARACTERISTICS
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
= 2.496 Vp−p at 100 kHz/2.5 Vref
= 2.496 Vp−p at 1 MHz/2.5 Vref
= 2.496 Vp−p at 1.8 MHz/2.5 Vref
= 2.496 Vp−p at 100 kHz/2.5 Vref
= 2.496 Vp−p at 1 MHz/2.5 Vref
= 2.496 Vp−p at 1.8 MHz/2.5 Vref
= 2.496 Vp−p at 100 kHz/2.5 Vref
= 2.496 Vp−p at 1 MHz/2.5 Vref
= 2.496 Vp−p at 1.8 MHz/2.5 Vref
= 2.496 Vp−p at 1 MHz/2.5 Vref
−91
−88.5
74
(5)
−86
Total harmonic distortion
dB
dB
dB
71.5
71
69
69
SNR
69.7
71.5
71
SINAD
68.3
90
SFDR
dB
−3 dB Small signal bandwidth
EXTERNAL REFERENCE INPUT
50
MHz
Input V
REF
range
2.4
2.5
2.6
V
(6)
Resistance
To internal reference voltage
500
kΩ
3
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SLAS400 − SEPTEMBER 2003
SPECIFICATIONS Continued
A
T
= −40°C to 85°C, +VA = 5 V, +VBD = 5 V or 3.3 V, V = 2.5 V, f
= 4 MHz (unless otherwise noted)
ref
sample
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL REFERENCE OUTPUT
From 95% (+VA), with 1-µF storage
capacitor on REFOUT to AGND
Start-up time
120
2.53
msec
V
REF
Range
IOUT=0
2.47
2.5
V
µA
Source current
Line regulation
Drift
Static load
10
+VA = 4.75 V to 5.25 V
IOUT = 0
1
mV
25
PPM/C
DIGITAL INPUT/OUTPUT
Logic family
CMOS
V
V
V
V
I
I
I
I
= 5 µA
= 5 µA
+V
BD
−1
+V
BD
+ 0.3
0.8
V
V
V
V
IH
IH
−0.3
− 0.6
0
IL
IL
Logic level
= 2 TTL loads
= 2 TTL loads
+V
BD
+V
OH
OL
OH
OL
BD
0.4
Straight
Binary
Data format
POWER SUPPLY REQUIREMENTS
+VBD
Power supply voltage
+VA
2.7
3.3
5
5.25
5.25
22
V
V
4.75
Supply current, +VA, 4 MHz sample rate
Power dissipation, 4 MHz sample rate
NAP MODE
19
95
mA
mW
+VA = 5 V
110
Supply current, +VA
2
3
mA
(7)
Power-up time
60
nsec
POWER DOWN
Supply current, +VA
2
2.5
µA
(8)
Power down time
From simulation results
10
µsec
1-µF Storage capacitor on REFOUT to
AGND
Power up time
25
4
msec
Invalid conversions after power up or reset
TEMPERATURE RANGE
Numbers
Operating free-air
−40
85
°C
(1)
Ideal input span; does not include gain or offset error.
This is endpoint INL, not best fit.
LSB means least significant bit.
Measured relative to actual measured reference.
Calculated on the first nine harmonics of the input frequency.
Can vary 20%.
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Minimum acquisition time for first sampling after the end of nap state must be 60 nsec more than normal.
Time required to reach level of 2.5 µA.
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TIMING REQUIREMENTS
All specifications typical at −40°C to 85°C, +VA = +5 V, +VBD = +5 V (see Notes 1, 2, 3, and 4)
PARAMETER
SYMBOL
MIN
TYP
185
65
MAX UNITS REF FIG.
Conversion time
Acquisition time
t
200
ns
ns
5
5
(conv)
t
50
(acq)
SAMPLING AND CONVERSION START
Hold time CS low to CONVST high (with BUSY high)
Delay CONVST high to acquisition start
t
t
t
t
t
10
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
1
1
1
1
2
2
2
2
h1
d1
h2
h3
d2
4
4
5
Hold time, CONVST high to CS high with BUSY low
Hold time, CONVST low to CS high
10
10
Delay CONVST low to BUSY high
40
5
CS width for acquisition or conversion to start
Delay CS low to acquisition start with CONVST high
Pulse width, from CS low to CONVST low for acquisition to start
Delay CS low to BUSY high with CONVST low
t
20
2
w3
t
d3
t
20
w1
t
d4
40
(3)
Quiet sampling time
25
CONVERSION ABORT
Setup time CONVST high to CS low with BUSY high
Delay time CS low to BUSY low with CONVST high
DATA READ
t
15
20
ns
ns
4
4
s1
t
d5
Delay RD low to data valid with CS low
Delay BYTE high to LSB word valid with CS and RD low
Delay time RD high to data 3-state with CS low
Delay time end of conversion to BUSY low
Quiet sampling time RD high to CONVST low
Delay CS low to data valid with RD low
Delay CS high to data 3-state with RD low
Quiet sampling time CS low to CONVST low
BACK-TO-BACK CONVERSION
t
t
t
25
25
25
20
25
25
25
25
ns
ns
ns
ns
ns
ns
ns
ns
5
5
5
5
5
6
6
6
d6
d7
d9
t
d11
t
1
t
d8
t
d10
t
2
Delay BUSY low to data valid
t
10
ns
ns
ns
7, 8
7, 8
7
d12
Pulse width, CONVST high
t
60
20
w4
w5
Pulse width, CONVST low
t
POWER DOWN/RESET
Pulse width, low for PWD/RST to reset the device
Pulse width, low for PWD/RST to power down the device
Delay time, power up after PWD/RST is high
t
t
45
6140
25
ns
ns
10
9
w6
w7
7200
t
ms
9
d13
(1)
(2)
(3)
(4)
All input signals are specified with t = t = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (V + V )/2.
IL IH
r
f
See timing diagram.
Quiet period before conversion start, no data bus activity including data bus 3-state is allowed in this period.
All timings are measured with 20 pF equivalent loads on all data bits and BUSY pin.
5
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PIN ASSIGNMENTS
48 47 46 45 44 43 42 41 40 39 38 37
BUSY
BDGND
+VBD
NC
36
35
REFIN
REFOUT
NC
1
2
34
33
32
3
4
5
+VA
NC
AGND
+IN
31
30
NC
6
7
NC
−IN
29
28
27
26
AGND
+VA
DB0
DB1
8
9
+VA 10
11
DB2
AGND
DB3
25
AGND
BDGND
12
13
14 15 16 17 18 19 20 21 22 23 24
NC − No connection
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Terminal Functions
PIN
NAME
DATA BUS
BYTE =
DB11
DB10
DB9
I/O
DESCRIPTION
1
8 BIT BUS
16 BIT BUS
0
16−23,
26−31
0
16
17
18
19
20
21
22
23
26
27
28
29
30
31
36
39
O
O
O
O
O
O
O
O
O
O
O
O
D11 (MSB)
D10
D9
D3
D11 (MSB)
D10
D9
D2
D1
DB8
D8
D0 (LSB)
D8
DB7
D7
0
0
0
0
0
0
0
0
D7
DB6
D6
D6
DB5
D5
D5
DB4
D4
D4
DB3
D3
D3
DB2
D2
D2
DB1
D1
D1
DB0
D0 (LSB)
D0 (LSB)
NC
NC
BUSY
BYTE
O
I
Status output. This pin is high when a conversion is in progress.
Byte select input. Used for 8-bit bus reading.
0: No fold back.
1: Lower byte D[3:0] is folded back to high byte so D3 is available in D11 place.
40
41
37
CONVST
RD
I
I
I
Conversion start. The rising edge starts the acquisition. The falling edge of this input ends the
acquisition and starts the conversion. Refer to the timing diagrams for more details.
Active low synchronization pulse for the parallel output. When CS is low, this serves as the output
enable and puts the previous conversion results on the bus.
A_PWD
+VBD
Nap mode enable, active low
24, 34
25, 35
Digital power supply for all digital inputs and outputs. Refer to Table 3 for layout guidelines.
BDGND
Digital ground for all digital inputs and outputs. Needs to be shorted to analog ground plane below
the device.
42
CS
I
I
Chip Select. Active low signal enables chip operation like acquisition start, conversion start, bus
release from 3-state. Refer to the timing diagrams for more details.
38
PWD/RST
AGND
Active low input, acts as device power down/device reset signal.
5, 8, 11, 12, 14,
15, 44, 45
Analog ground pins. Need to be shorted to analog ground plane below the device.
4, 9, 10, 13, 43, +VA
46
Analog power supplies. Refer to Table 3 for layout guidelines.
6
7
1
+IN
I
I
I
Non inverting analog input channel
Inverting analog input channel
−IN
REFIN
Reference (positive) input. Needs to be decoupled with REFM pin using 0.1-µF bypass capacitor
and 1-µF storage capacitor.
2
REFOUT
O
I
Internal reference output. To be shorted to REFIN pin when internal reference is used. Do not
connect to REFIN pin when external reference is used. Always needs to be decoupled with AGND
using 0.1-µF bypass capacitor.
47, 48
REFM
NC
Reference ground. To be connected to analog ground plane.
No connection pins.
3, 32, 33
7
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DESCRIPTION AND TIMING DIAGRAMS
SAMPLING AND CONVERSION START
There are three ways to start sampling. The rising edge of CONVST starts sampling with CS and BUSY being low
(see Figure 1) or it can be started with the falling edge of CS when CONVST is high and BUSY is low (see
Figure 2). Sampling can also be started with an internal conversion end (before BUSY falling edge) with CS
being low and CONVST high before an internal conversion end (see Figure 3). Also refer to the section DEVICE
OPERATION AND DATA READ IN BACK-TO-BACK CONVERSION for more details.
A conversion can be started two ways (a conversion start is the end of sampling). Either with the falling edge
of CONVST when CS is low (see Figure 1) or the falling edge of CS when CONVST is low (see Figure 2). A
clean and low jitter falling edge of these respective signals triggers a conversion start and is important to the
performance of the converter. The BUSY pin is brought high immediately following the CONVST falling edge.
BUSY stays high throughout the conversion process and returns low when the conversion has ended.
t
h2
t
h3
CS
CONVST
t
d1
t
d2
BUSY
t
(acq)
Figure 1. Sampling and Conversion Start Control With CONVST Pin
t
t
w3
w3
CS
t
d4
CONVST
t
d3
t
w1
BUSY
t
(acq)
Figure 2. Sampling and Conversion Start Control With CS Pin
CS
t
h1
t
w5
CONVST
BUSY
t
w4
t
d2
t
(acq)
Figure 3. Sampling Start With CS Low and CONVST High (Back-to-Back)
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CONVERSION ABORT
The falling edge of CS aborts the conversion while BUSY is high and CONVST is high (see Figure 4). The device
outputs FE0 (hex) to indicate a conversion abort.
t
d5
BUSY
CONVST
CS
t
su1
RD
1111 1110 0000
D11−D0
Figure 4. Conversion Abort
DATA READ
Two conditions need to be satisfied for a read operation. Data appears on the D11 through D0 pins (with D11
MSB) when both CS and RD are low. Figure 5 and Figure 6 illustrate the device read operation. The bus is
three-stated if any one of the signals is high.
t
1
t
w5
t
d2
CONVST
BUSY
t
(conv)
t
+ t
d1 (acq)
t
d11
CS
RD
BYTE
t
d6
t
d7
t
d9
D11−4 & D3−0
D3−0
D11−D0
Figure 5. Read Control Via CS and RD
There are two output formats available. Twelve bit data appears on the bus during a read operation while BYTE
is low. When BYTE is high, the lower byte (D3 through D0 followed by all zeroes) appears on the data bus with
D3 in the MSB. This feature is useful for interfacing with eight bit microprocessors and microcontrollers.
9
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t
2
CONVST
BUSY
t
+ t
d1 (acq)
Conversion No N
t
d2
CS
BYTE
t
t
d10
d7
D11−4 & D3−0
Data For Conv. N
D3−0
D11−D0
Data For Conv. N−1
t
d8
Figure 6. Read Control Via CS and RD Tied to BDGND
DEVICE OPERATION AND DATA READ IN BACK-TO-BACK CONVERSION
The following two figures illustrate device operation in back-to-back conversion mode. It is possible to operate
the device at any throughput in this mode, but this is the only mode in which the device can be operated at
throughputs exceeding 3.5 MSPS.
A conversion starts on the CONVST falling edge. The BUSY output goes high after a delay (t ). Note that care
d2
must be taken not to abort the conversion (see Figure 4) apart from timing restrictions shown in Figure 7 and
Figure 8. The conversion ends within the conversion time, t
, after the CONVST falling edge. The new
(conv)
acquisition can be immediately started without waiting for the BUSY signal to go low. This can be ensured with
aCONVSThigh pulse width that is more than or equal to (t – t
+ 10 nsec) which is t for a 4-MHz operation.
0
(conv)
w4
Sample N
CONVST
t
t
w4
w5
t
(acq)
Conversion N
BUSY
t
+ t
d11
t
(conv)
d12
Data For Conversion N−1
D11−D0
(Data read Without Latency)
t0 = 250 ns for 4 MSPS Operation
Figure 7. Back-To-Back Operation With CS and RD Low
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CS
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Sample N
t
h1
CONVST
t
t
w3
w4
t
+ t
(conv) d11
Conversion N
t
(acq)
BUSY
Data For Conversion N−1
t
d12
D11−D0
(Data read Without Latency)
t0 = 250 ns for 4 MSPS Operation
Figure 8. Back-To-Back operation With CS Toggling and RD Low
NAP MODE
The device can be put in nap mode following the sequences shown in Figure 9. This provides substantial power
saving while operating at lower sampling rates.
While operating the device at throughput rates lower than 3.2 MSPS, A_PWD can be held low (see Figure 9).
In this condition, the device goes into the nap state immediately after BUSY goes low and remains in that state
until the next sampling starts. The minimum acquisition time is 60 nsec more than t
requirements section.
as defined in the timing
(acq)
Alternately, A_PWD can be toggled any time during operation (see Figure 10). This is useful when the system
acquires data at the maximum conversion speed for some period of time (back-to-back conversion) and it does
not acquire data for some time while the acquired data is being processed. During this period, the device can
be put in the nap state to save power. The device remains in the nap state as long as A_PWD is low with BUSY
being low and sampling has not started. The minimum acquisition time for the first sampling after the nap state
is 60 nsec more than t
as defined in the timing requirements section.
(acq)
A_PWD
(Held Low)
BUSY
SAMPLE
(Internal)
t
+ 60 ns
(acq)
NAP
(Internal Active High)
:
NOTE The SAMPLE (Internal) signal is generated as described in the Sampling and Conversion
Start section.
Figure 9. Device Operation While A_PWD is Held Low
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A_PWD
BUSY
SAMPLE
(Internal)
t
+ 60 ns
(acq)
NAP
(Internal Active High)
:
NOTE The SAMPLE (Internal) signal is generated as described in the Sampling and Conversion
Start section.
Figure 10. Device Operation While A_PWD is Toggling
POWERDOWN/RESET
A low level on the PWD/RST pin puts the device in the powerdown phase. This is an asynchronous signal. As
shown in Figure 11, the device is in the reset phase for the first t period after a high-to-low transition of
w6
PWD/RST. During this period the output code is FE0 (hex) to indicate that the device is in the reset phase. The
device powers down if the PWD/RST pin continues to be low for a period of more than t . Data is not valid for
w7
the first four conversions after a power-up (see Figure 11) or an end of reset (see Figure 12). The device is
initialized during the first four conversions.
t
w7
Valid Conversions
5
PWD/RST
BUSY
First 4 Invalid Conversions
1
2
3
4
t
d13
1111 1110 0000
RESET Phase
D11−D0
Power Down
Phase
Invalid Data
Valid Data
Figure 11. Device Power Down
t
w6
45 ns
PWD/RST
Valid Conversions
5
First 4 Invalid Conversions
BUSY
1
2
3
4
D11−D0
1111 1110 0000
RESET Phase
Invalid Data
Valid Data
Figure 12. Device Reset
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(1)
TYPICAL CHARACTERISTICS
EFFECTIVE NUMBER OF BITS
HISTOGRAM
(DC CODE SPREAD AT THE CENTER OF CODE)
vs
FREE-AIR TEMPERATURE
140000
12
11.9
11.8
11.7
11.6
11.5
11.4
11.3
11.2
Count = 130879
f = 100 kHz,
+VA = 5 V,
+VBD = 5 V,
Code = 2048,
i
+VA = 5 V,
120000
100000
80000
60000
40000
+VBD = 5 V
T
A
= 255C
20000
0
Count
= 0
Count
= 1
Count
= 192
Count
= 0
11.1
11
2046
2047
2048
2049
2050
−40
−20
0
20
40
60
80
Code
T
A
− Free-Air Temperature − °C
Figure 13
Figure 14
SIGNAL-TO-NOISE AND DISTORTION
SIGNAL-TO-NOISE RATIO
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
72
71.9
71.8
71.7
71.6
72
f = 100 kHz,
+VA = 5 V,
+VBD = 5 V
f = 100 kHz,
i
i
+VA = 5 V,
+VBD = 5 V
71.8
71.6
71.5
71.4
71.3
71.2
71.4
71.2
71
71.1
71
−40
−20
0
20
40
60
80
−40
−20
T
0
20
40
60
80
T
A
− Free-Air Temperature − °C
− Free-Air Temperature − °C
A
Figure 15
Figure 16
(1)
At sample rate = 4 MSPS, V = 2.5 V external, unless otherwise specified.
ref
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SPURIOUS FREE DYNAMIC RANGE
TOTAL HARMONIC DISTORTION
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
105
100
95
−85
−90
f = 100 kHz,
+VA = 5 V,
+VBD = 5 V
i
f = 100 kHz,
+VA = 5 V,
+VBD = 5 V
i
−95
90
85
−100
−40
−20
0
20
40
60
80
−40
−20
0
20
40
60
80
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 17
Figure 18
EFFECTIVE NUMBER OF BITS
SIGNAL-TO-NOISE AND DISTORTION
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
73
12
+VA = 5 V,
+VBD = 5 V,
+VA = 5 V,
+VBD = 5 V,
72
71
70
69
T
A
= 25°C,
T
A
= 25°C,
11.5
11
68
67
10.5
10
66
65
0
300
600
900
1200
1500
1800
0
300
600
900
1200
1500 1800
f − Input Frequency − kHz
i
f − Input Frequency − kHz
i
Figure 19
Figure 20
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SPURIOUS FREE DYNAMIC RANGE
SIGNAL-TO-NOISE RATIO
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
105
100
95
73
+VA = 5 V,
+VBD = 5 V,
+VA = 5 V,
+VBD = 5 V,
= 25°C,
72
71
70
T
= 25°C,
T
A
A
90
85
69
68
80
75
67
66
70
65
60
65
0
0
300
600
900
1200
1500
1800
300
600
900
1200
1500
1800
f − Input Frequency − kHz
i
f − Input Frequency − kHz
i
Figure 21
Figure 22
GAIN ERROR
vs
TOTAL HARMONIC DISTORTION
vs
SUPPLY VOLTAGE
INPUT FREQUENCY
−60
0.9
+VBD = 5 V,
= 25°C,
+VA = 5 V,
+VBD = 5 V,
T
A
−65
−70
−75
−80
−85
−90
T
A
= 25°C,
0.85
0.8
0.75
0.7
−95
−100
0
300
600
900
1200
1500
1800
4.75 4.8 4.85 4.9 4.95
5
5.05 5.1 5.15 5.2 5.25
+VA − Supply Voltage − V
f − Input Frequency − kHz
i
Figure 23
Figure 24
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GAIN ERROR
vs
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
1.5
0.5
+VA = 5 V,
+VBD = 5 V,
+VBD = 5 V,
T
= 25°C,
A
1.25
1
0.4
0.3
0.2
0.75
0.5
0.1
0
0.25
0
4.75 4.8 4.85 4.9 4.95
5
5.05 5.1 5.15 5.2 5.25
−40
−20
0
20
40
60
80
+VA − Supply Voltage − V
T
A
− Free-Air Temperature − °C
Figure 25
Figure 26
POWER DISSIPATION
vs
OFFSET ERROR
vs
SAMPLE RATE
FREE-AIR TEMPERATURE
100
90
1
+VA = 5 V,
+VBD = 5 V,
= 25°C,
+VA = 5 V,
+VBD = 5 V
0.75
T
A
80
NAP Disabled
0.5
70
60
50
40
30
0.25
NAP Enabled
0
−0.25
−0.5
20
10
0
−0.75
−1
0
500 1000 1500 2000 2500 3000 3500 4000
Sample Rate − KSPS
−40
−20
0
20
40
60
80
T
− Free-Air Temperature − °C
A
Figure 27
Figure 28
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POWER DISSIPATION
vs
DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
97
1
+VA = 5 V,
+VBD = 5 V
+VA = 5 V,
+VBD = 5 V
0.75
Max
96
95
0.5
0.25
0
94
−0.25
Min
−0.5
93
92
−0.75
−1
−40
−20
0
20
40
60
80
−40
−20
0
20
40
60
80
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 29
Figure 30
INTEGRAL NONLINEARITY
vs
INTERNAL REFERENCE OUTPUT
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1
2.505
2.5045
2.504
+VA = 5 V,
+VBD = 5 V
+VA = 5 V,
+VBD = 5 V
0.75
0.5
0.25
0
Max
2.5035
2.503
2.5025
2.502
2.5015
2.501
2.5005
2.5
−0.25
−0.5
Min
20
−0.75
−1
−40
−20
0
40
60
80
−40
−20
0
20
40
60
80
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 31
Figure 32
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INTERNAL REFERENCE OUTPUT
vs
SUPPLY VOLTAGE
2.505
+VBD = 5 V,
2.5045
T
= 255C
A
2.504
2.5035
2.503
2.5025
2.502
2.5015
2.501
2.5005
2.5
4.75 4.8 4.85 4.9 4.95
5
5.05 5.1 5.15 5.2 5.25
+VA − Supply Voltage − V
Figure 33
DIFFERENTIAL NONLINEARITY
1
0.8
+VA = 5 V,
+VBD = 5 V,
0.6
T
A
= 25°C,
0.4
Sample Rate = 4 MSPS
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
1028
2056
3084
4096
0
Code
Figure 34
INTEGRAL NONLINEARITY
1
0.8
0.6
+VA = 5 V,
+VBD = 5 V,
T
= 25°C,
0.4
0.2
A
Sample Rate = 4 MSPS
0
−0.2
−0.4
−0.6
−0.8
−1
0
1028
2056
3084
4096
Code
Figure 35
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FFT
20
+VA = 5 V,
+VBD = 5 V,
0
−20
T
A
= 25°C,
−40
−60
Sample Rate = 4 MSPS
−80
−100
−120
−140
−160
0
0.4
0.8
1.2
1.6
2
f − Frequency − MHz
Figure 36
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PRINCIPLES OF OPERATION
The ADS7881 is a member of a family of high-speed successive approximation register (SAR) analog-to-digital
converters (ADC). The architecture is based on charge redistribution, which inherently includes a sample/hold
function.
The conversion clock is generated internally. The conversion time is 200 ns max (at 5 V +VBD).
The analog input is provided to two input pins: +IN and −IN. (Note that this is pseudo differential input and there
are restrictions on –IN voltage range.) When a conversion is initiated, the difference voltage between these pins
is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from
any internal function.
REFERENCE
The ADS7881 has a built-in 2.5-V (nominal value) reference but can operate with an external reference. When
an internal reference is used, pin 2 (REFOUT) should be connected to pin 1 (REFIN) with an 0.1-µF decoupling
capacitor and a 1-µF storage capacitor between pin 2 (REFOUT) and pins 47, 48 (REFM). The internal
reference of the converter is buffered . There is also a buffer from REFIN to CDAC. This buffer provides isolation
between the external reference and the CDAC and also recharges the CDAC during conversion. It is essential
to decouple REFOUT to AGND with a 0.1-µF capacitor while the device operates with an external reference.
ANALOG INPUT
When the converter enters hold mode, the voltage difference between the +IN and −IN inputs is captured on
the internal capacitor array. The voltage on the −IN input is limited to between –0.2 V and 0.2 V, thus allowing
the input to reject a small signal which is common to both the +IN and −IN inputs. The +IN input has a range
of –0.2 V to (+V +0.2 V). The input span (+IN – (−IN)) is limited from 0 V to VREF.
ref
The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, signal
frequency, and source impedance. Essentially, the current into the ADS7881 charges the internal capacitor
array during the sample period. After this capacitance has been fully charged, there is no further input current
(this may not happen when a signal is moving continuously). The source of the analog input voltage must be
able to charge the input capacitance (27 pF) to better than a 12-bit settling level with a step input within the
acquisition time of the device. The step size can be selected equal to the maximum voltage difference between
two consecutive samples at the maximum signal frequency. (Refer to Figure 39 for the suggested input circuit.)
When the converter goes into hold mode, the input impedance is greater than 1 GΩ.
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, both
−IN and +IN inputs should be within the limits specified. Outside of these ranges, the converter’s linearity may
not meet specifications.
Care should be taken to ensure that +IN and −IN see the same impedance to the respective sources. (For
example, both +IN and −IN are connected to a decoupling capacitor through a 21-Ω resistor as shown in
Figure 39.) If this is not observed, the two inputs could have different settling times. This may result in an offset
error, gain error, or linearity error which changes with temperature and input voltage.
DIGITAL INTERFACE
TIMING AND CONTROL
Refer to the SAMPLING AND CONVERSION START section and the CONVERSION ABORT section.
READING DATA
The ADS7881 outputs full parallel data in straight binary format as shown in Table 1. The parallel output is active
when CS and RD are both low. There is a minimal quiet sampling period requirement around the falling edge
of CONVST as stated in the timing requirements section. Data reads or bus three-state operations should not
be attempted within this period. Any other combination of CS and RD three-states the parallel output. Refer to
Table 1 for ideal output codes.
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(1)
Table 1. Ideal Input Voltages and Output Codes
DESCRIPTION
Full scale
ANALOG VALUE
− 1 LSB
BINARY CODE
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
HEX CODE
FFF
V
ref
Midscale
V
/2
800
7FF
000
ref
/2 − 1 LSB
Midscale − 1 LSB
Zero
V
ref
0 V
(1)
Full-scale range = V and least significant bit (LSB) = V /4096
ref ref
The output data appears as a full 12-bit word (D11−D0) on pins DB11 – DB0 (MSB−LSB) if BYTE is low.
READING THE DATA IN BYTE MODE
The result can also be read on an 8-bit bus for convenience by using pins DB11−DB4. In this case two reads
are necessary; the first as before, leaving BYTE low and reading the 8 most significant bits on pins DB11−DB4,
and then bringing BYTE high. When BYTE is high, the lower bits (D3−D0) followed by all zeros are on pins DB11
− DB4 (refer to Table 2).
These multi-word read operations can be performed with multiple active RD signals (toggling) or with RD tied
low for simplicity.
Table 2. Conversion Data Read Out
DATA READ OUT
BYTE
DB11 − DB4
DB3 − DB0
All zeroes
D3 − D0
High
Low
D3 − D0, 0000
D11 − D4
Also refer to the DATA READ and DEVICE OPERATION AND DATA READ IN BACK-TO-BACK
CONVERSION sections for more details.
Reset
Refer to the POWERDOWN/RESET section for the device reset sequence.
It is recommended to reset the device after power on. A reset can be issued once the power has reached 95%
of its final value.
PWD/RST is an asynchronous active low input signal. A current conversion is aborted no later than 45 ns after
the converter is in the reset mode. In addition, the device outputs a FE0 code to indicate a reset condition. The
converter returns back to normal operation mode immediately after the PWD/RST input is brought high.
Data is not valid for the first four conversions after a device reset.
Powerdown
Refer to the POWERDOWN/RESET section for the device powerdown sequence.
The device enters powerdown mode if a PWD/RST low duration is extended for more than a period of t
.
w7
The converter goes back to normal operation mode no later than a period of t
brought high.
after the PWD/RST input is
d13
After this period, normal conversion and sampling operation can be started as discussed in previous sections.
Data is not valid for the first four conversions after a device reset.
Nap Mode
Refer to the NAP MODE section in the DESCRIPTION AND TIMING DIAGRAMS section for information.
21
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APPLICATION INFORMATION
LAYOUT
For optimum performance, care should be taken with the physical layout of the ADS7881 circuitry.
As the ADS7881 offers single-supply operation, it is often used in close proximity with digital logic,
micro-controllers, microprocessors, and digital signal processors. The more digital logic present in the design
and the higher the switching speed, the more difficult it is to achieve acceptable performance from the converter.
The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground
connections, and digital inputs that occur just prior to the end of sampling (within quiet sampling time) and just
prior to latching the output of the analog comparator during the conversion phase. Thus, driving any single
conversion for an n-bit SAR converter, there are n+1 windows in which large external transient voltages can
affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic,
or high power devices.
The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the
external event.
On average, the ADS7881 draws very little current from an external reference as the reference voltage is
internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive
the bypass capacitor or capacitors without oscillation. A 0.1-µF bypass capacitor and 1-µF storage capacitor
are recommended from REFIN (pin 1) directly to REFM (pin 48).
The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the analog
ground. Avoid connections which are too close to the grounding point of a micro-controller or digital signal
processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal
layout consists of an analog ground plane dedicated to the converter and associated analog circuitry.
As with the AGND connections, +VA should be connected to a 5-V power supply plane that is separate from
the connection for +VBD and digital logic until they are connected at the power entry point onto the PCB. Power
to the ADS7881 should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as
close to the device as possible. See Table 3 for the placement of capacitor. In addition to a 0.1-µF capacitor,
a 1-µF capacitor is recommended. In some situations, additional bypassing may be required, such as a 100-µF
electrolytic capacitor or even a Pi filter made up of inductors and capacitors, all designed to essentially low-pass
filter the 5-V supply, removing the high frequency noise.
Table 3. Power Supply Decoupling Capacitor Placement
POWER SUPPLY PLANE
CONVERTER ANALOG SIDE
CONVERTER DIGITAL SIDE
SUPPLY PINS
Pairs of pins that require a shortest path to decoupling
capacitors
(4,5), (9,8), (10,11), (13, 15), (43, 44) (46, 45) (24, 25), (34, 35)
14, 12
Pins that require no decoupling
Analog 5 V
AGND
+VA
ADS7881
0.1 µF
1 µF
AGND
0.1 µF
REFOUT
REFIN
External
Reference in
0.1 µF
1 µF
REFM
+IN
AGND
21 Ω
21 Ω
Analog Input
Circuit
−IN
Figure 37. Using External Reference
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Analog 5 V
AGND
+VA
ADS7881
0.1 µF
0.1 µF
1 µF
1 µF
AGND
REFOUT
REFIN
REFM
+IN
AGND
21 Ω
21 Ω
Analog Input
Circuit
−IN
Figure 38. Using Internal Reference
130 pF
604 Ω
Signal Input
604 Ω
100 Ω
_
12 Ω
150 pF
21 Ω
21 Ω
2.5 V DC
THS4211
+IN
−IN
3 kΩ
1 kΩ
ADS7881
+
1 nF
AGND
AGND
Figure 39. Typical Analog Input Circuit
CS
GPIO
GPIO
GPIO
BYTE
CONVST
Microcontroller
P[7:0]
ADS7881
DB[11:4]
RD
RD
INT
BUSY
Figure 40. Interfacing With Microcontroller
23
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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