ADS802U [TI]
12 位、10MSPS 模数转换器 (ADC) | DW | 28 | -40 to 85;
| 型号： | ADS802U |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12 位、10MSPS 模数转换器 (ADC) | DW | 28 | -40 to 85 光电二极管 转换器 模数转换器 |
| 文件： | 总19页 (文件大小：471K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS802
AD
S802U
SBAS039B – MAY 1995 – REVISED FEBRUARY 2005
12-Bit, 10MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
DESCRIPTION
FEATURES
● NO MISSING CODES
The ADS802 is a low-power, monolithic 12-bit, 10MHz Ana-
log-to-Digital (A/D) converter utilizing a small geometry CMOS
process. This complete converter includes a 12-bit quantizer,
wideband track-and-hold, reference, and three-state outputs.
It operates from a single +5V power supply and can be
configured to accept either differential or single-ended input
signals.
● LOW POWER: 250mW
● INTERNAL REFERENCE
● WIDEBAND TRACK-AND-HOLD: 65MHz
● SINGLE +5V SUPPLY
The ADS802 employs digital error correction in order to
provide excellent Nyquist differential linearity performance
for demanding imaging applications. Its low distortion, high
SNR, and high oversampling capability give it the extra
margin needed for telecommunications, test instrumentation,
and video applications.
APPLICATIONS
● IF AND BASEBAND DIGITIZATION
● DATA ACQUISITION CARDS
● TEST INSTRUMENTATION
● CCD IMAGING
Copiers
This high-performance A/D converter is specified for AC and
DC performance at a 10MHz sampling rate. The ADS802 is
available in an SO-28 package.
Scanners
Cameras
● VIDEO DIGITIZING
● GAMMA CAMERAS
CLK
MSBI
OE
Timing
Circuitry
IN
12-Bit
Digital
Data
Pipeline
A/D
Converter
Error
Correction
Logic
3-State
Outputs
T/H
IN
+3.25V
REFT
CM
REFB
+1.25V
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1995-2005, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
+VS ........................................................................................................ +6V
Analog Input .............................................................. 0V to (+VS + 300mV)
Logic Input................................................................. 0V to (+VS + 300mV)
Case Temperature .......................................................................... +100°C
Junction Temperature ..................................................................... +150°C
Storage Temperature ...................................................................... +125°C
External Top Reference Voltage (REFT) .................................. +3.4V Max
External Bottom Reference Voltage (REFB) .............................. +1.1V Min
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTE: (1) Stresses above these ratings may permanently damage the device.
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
ADS802U
ADS802U
SO-28
DW
–40°C to +85°C
ADS802U
ADS802U
ADS802U
Rails, 28
"
"
"
ADS802U/1K
Tape and Reel, 1000
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at
www.ti.com.
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VS = +5V, and Sampling Rate = 10MHz, and with a 50% duty cycle clock having 2ns rise-and-fall time, unless otherwise noted.
ADS802U
PARAMETER
CONDITIONS
TEMP
MIN
TYP
MAX
UNITS
RESOLUTION
12
Bits
Specified Temperature Range
TAMBIENT
–40
+85
°C
ANALOG INPUT
Differential Full-Scale Input Range
Common-Mode Voltage
Analog Input Bandwidth (–3dB)
Small-Signal
Both Inputs
+1.25
+3.25
V
V
+2.25
–20dBFS(1) Input
0dBFS Input
+25°C
+25°C
400
65
MHz
MHz
Full-Power
Input Impedance
1.25 || 4
MΩ || pF
DIGITAL INPUT
Logic Family
Convert Command
TTL/HCT Compatible CMOS
Falling Edge
Start Conversion
fS = 2.5MHz
ACCURACY(2)
Gain Error
+25°C
Full
±0.6
±1.0
±85
0.03
±2.1
0.05
±1.5
±2.5
%
%
Gain Tempco
Power-Supply Rejection of Gain
Input Offset Error
ppm/°C
%FSR/%
%
∆ +VS = ±5%
∆ +VS = ±5%
+25°C
Full
+25°C
0.1
±3.0
0.1
Power-Supply Rejection of Offset
%FSR/%
CONVERSION CHARACTERISTICS
Sample Rate
10k
10M
Sample/s
Data Latency
6.5
Convert Cycle
DYNAMIC CHARACTERISTICS
Differential Linearity Error
f = 500kHz
+25°C
0°C to +85°C
+25°C
0°C to +85°C
0°C to +85°C
0°C to +85°C
±0.3
±0.4
±0.4
±0.4
Tested
±1.7
±1.0
±1.0
±1.0
±1.0
LSB
LSB
LSB
LSB
LSB
LSB
f = 5MHz
No Missing Codes
Integral Linearity Error at f = 500kHz
Spurious-Free Dynamic Range (SFDR)
f = 500kHz (–1dBFS input)
Best Fit
±2.75
+25°C
Full
+25°C
Full
67
66
63
62
77
75
67
66
dBFS
dBFS
dBFS
dBFS
f = 5MHz (–1dBFS input)
NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) IMD is referred
to the larger of the two input signals. If referred to the peak envelope signal (≈0dB), the intermodulation products will be 7dB lower. (4) No “rollover” of bits.
ADS802
2
SBAS039B
www.ti.com
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, and Sampling Rate = 10MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.
ADS802U
PARAMETER
CONDITIONS
TEMP
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS (Cont.)
2-Tone Intermodulation Distortion (IMD)(3)
f = 4.4MHz and 4.5MHz (–7dBFS each tone)
+25°C
Full
–65
–64
dBc
dBc
Signal-to-Noise Ratio (SNR)
f = 500kHz (–1dBFS input)
+25°C
Full
+25°C
Full
65
64
64
62
67
67
66
66
dB
dB
dB
dB
f = 5MHz (–1dBFS input)
Signal-to-(Noise + Distortion) (SINAD)
f = 500kHz (–1dBFS input)
+25°C
Full
+25°C
Full
+25°C
+25°C
+25°C
+25°C
+25°C
63
61
61
60
66
65
63
62
0.5
0.1
2
dB
dB
dB
dB
%
Degrees
ns
ps rms
ns
f = 5MHz (–1dBFS input)
Differential Gain Error
Differential Phase Error
Aperture Delay Time
Aperture Jitter
NTSC or PAL
NTSC or PAL
7
2
Over-Voltage Recovery Time(4)
1.5x Full-Scale Input
OUTPUTS
Logic Family
Logic Coding
Logic Levels
TTL/HCT Compatible CMOS
SOB or BTC
Logic Selectable
Logic LOW
Logic HIGH
Full
Full
Full
Full
0
2.0
0.4
+VS
40
V
V
ns
ns
3-State Enable Time
3-State Disable Time
20
2
10
POWER-SUPPLY REQUIREMENTS
Supply Voltage: +VS
Supply Current: +IS
Operating
Operating
Operating
Operating
Operating
Full
+25°C
Full
+25°C
Full
+4.75
+5.0
50
52
250
260
+5.25
62
62
310
310
V
mA
mA
mW
mW
Power Consumption
Thermal Resistance, θJA
SO-28
75
°C/W
NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) IMD is referred
to the larger of the two input signals. If referred to the peak envelope signal (≈0dB), the intermodulation products will be 7dB lower. (4) No “rollover” of bits.
ADS802
SBAS039B
3
www.ti.com
PIN CONFIGURATION
PIN DESCRIPTIONS
PIN
DESIGNATOR DESCRIPTION
Top View
SO
1
2
GND
B1
Ground
Bit 1, Most Significant Bit (MSB)
3
B2
Bit 2
4
B3
Bit 3
5
6
7
8
B4
B5
B6
B7
B8
B9
B10
B11
B12
GND
+VS
CLK
+VS
OE
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
GND
B1
B2
B3
B4
B5
B6
B7
B8
1
2
3
4
5
6
7
8
9
28 GND
27 IN
26 IN
9
10
11
12
13
14
15
16
17
18
25 GND
24 +VS
23 REFT
22 CM
21 REFB
20 +VS
19 MSBI
18 OE
Bit 12, Least Significant Bit (LSB)
Ground
+5V Power Supply
Convert Clock Input, 50% Duty Cycle
+5V Power Supply
ADS802
HIGH: High-Impedance State. LOW or Floating:
Normal Operation. Internal pull-down resistors.
Most Significant Bit Inversion, HIGH: MSB in-
verted for complementary output. LOW or Float-
ing: Straight output. Internal pull-down resistors.
+5V Power Supply
Bottom Reference Bypass. For external bypass-
ing of internal +1.25V reference.
Common-Mode Voltage. It is derived by
(REFT + REFB)/2.
Top Reference Bypass. For external bypassing
of internal +3.25V reference.
+5V Power Supply
Ground
Input
19
MSBI
B9 10
B10 11
B11 12
B12 13
GND 14
20
21
+VS
REFB
17 +VS
16 CLK
15 +VS
22
23
CM
REFT
24
25
26
27
28
+VS
GND
IN
IN
GND
Complementary Input
Ground
TIMING DIAGRAM
tCONV
Convert
Clock
tL
tH
tD
DATA LATENCY
(6.5 Clock Cycles)
(1)
Hold
“N”
Hold
“N + 1”
Hold
“N + 2”
Hold
“N + 3”
Hold
N + 4
Hold
N + 5
Hold
Track
N + 6”
Internal
Track-and-Hold
Track
Track
Track
Track
Track
Track
Track
“
”
“
”
“
t2
Output
Data
Data Valid
N – 8
Data Valid
N – 7
Data Valid
N – 6
N – 5
N – 4
N – 3
N – 2
N – 1
N
t1
Data Invalid
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tCONV
tL
tH
tD
t1
Convert Clock Period
Clock Pulse LOW
Clock Pulse HIGH
Aperture Delay
Data Hold Time, CL = 0pF
100
48
48
100µs
ns
ns
ns
ns
ns
ns
50
50
2
3.9
t2
New Data Delay Time, CL = 15pF max
12.5
NOTE: (1) “ ” indicates the portion of the waveform that will stretch out at slower sample rates.
ADS802
4
SBAS039B
www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = +5V, Sampling Rate = 10MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
1.0
2.0
3.0
4.0
5.0
0
0.0
0
1.0
2.0
3.0
4.0
5.0
5.0
4.0
Frequency (MHz)
Frequency (MHz)
SPECTRAL PERFORMANCE
2-TONE INTERMODULATION
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
1.0
2.0
3.0
4.0
5.0
1.25
2.5
3.75
Frequency (MHz)
Frequency (MHz)
DIFFERENTIAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
fIN = 5MHz
2.0
2.0
1.0
fIN = 500kHz
–
–2.0
–1.0
–2.0
0
1.0
2.0
3.0
4.0
1.0
2.0
3.0
Code
Code
ADS802
SBAS039B
5
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, Sampling Rate = 10MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.
OUTPUT NOISE HISTOGRAM (NO SIGNAL)
SWEPT POWER SFDR
800k
600k
400k
200k
0.0
100
80
60
40
20
0
fIN = 10MHz
N – 2
N – 1
N
N + 1
N + 2
–50
–40
–30
–20
–10
0
10
Code
Input Amplitude (dBm)
SWEPT POWER SNR
INTEGRAL LINEARITY ERROR
80
60
40
20
0
4.0
2.0
fIN = 500kHz
fIN = 5MHz
0
–2.0
–4.0
–50
–40
–30
–20
–10
0
10
0
1.0
2.0
3.0
4096
Input Amplitude (dBm)
Code
DYNAMIC PERFORMANCE vs
DYNAMIC PERFORMANCE vs
SINGLE-ENDED FULL-SCALE INPUT RANGE
DIFFERENTIAL FULL-SCALE INPUT RANGE
75
70
65
60
55
75
70
65
60
55
SFDR (fIN = 5MHz)
SNR (fIN = 5MHz)
SFDR (fIN = 5MHz)
SNR (fIN = 5MHz)
2
3
4
5
2
3
4
5
1
1
Single-Ended Full-Scale Range (Vp-p)
Differential Full-Scale Input Range (Vp-p)
ADS802
6
SBAS039B
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, Sampling Rate = 10MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.
DIFFERENTIAL LINEARITY ERROR vs
TEMPERATURE
SPURIOUS-FREE DYNAMIC RANGE (SFDR) vs
TEMPERATURE
1.0
0.8
0.6
0.4
0.2
0.1
80
75
70
65
60
fIN = 500kHz
fIN = 5MHz
fIN = 5MHz
fIN = 500kHz
–50
–25
0
25
50
75
100
100
100
0
25
50
75
100
–25
Temperature (°C)
Temperature (°C)
SIGNAL-TO-(NOISE + DISTORTION) vs
TEMPERATURE
SIGNAL-TO-NOISE RATIO vs TEMPERATURE
fIN = 500kHz
70
68
66
64
62
68
66
64
62
60
fIN = 500kHz
fIN = 5MHz
fIN = 5MHz
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
Temperature (°C)
Temperature (°C)
SUPPLY CURRENT vs TEMPERATURE
POWER DISSIPATION vs TEMPERATURE
265
260
255
250
53
52
51
50
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
Temperature (°C)
Temperature (°C)
ADS802
SBAS039B
7
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, Sampling Rate = 10MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.
GAIN ERROR vs TEMPERATURE
OFFSET ERROR vs TEMPERATURE
–0.05
–0.55
–1.05
–1.55
–1.25
–1.5
–2.0
–2.5
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
TRACK-MODE SMALL-SIGNAL INPUT BANDWIDTH
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
1
0
80
75
70
65
60
55
SFDR
–1
–2
–3
–4
–5
SNR
10k
100k
1M
10M
100M
1G
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
ADS802
8
SBAS039B
www.ti.com
THEORY OF OPERATION
Op Amp
Bias
VCM
The ADS802 is a high-speed, sampling A/D converter with
pipelining. It uses a fully differential architecture and digital
error correction to ensure 12-bit resolution. The differential
track-and-hold circuit is shown in Figure 1. The switches are
controlled by an internal clock that has a non-overlapping 2-
phase signal, φ1 and φ2. At the sampling time, the input
signal is sampled on the bottom plates of the input capaci-
tors. In the next clock phase, φ2, the bottom plates of the
input capacitors are connected together and the feedback
capacitors are switched to the op amp output. At this time,
the charge redistributes between CI and CH, completing one
track-and-hold cycle. The differential output is a held DC
representation of the analog input at the sample time. The
track-and-hold circuit can also convert a single-ended input
signal into a fully differential signal for the quantizer.
φ1
φ1
CH
φ2
φ2
CI
CI
IN
IN
OUT
OUT
φ1
φ1
φ2
φ1
CH
φ1
φ1
Input Clock (50%)
Op Amp
Bias
VCM
Internal Non-Overlapping Clock
φ1 φ2 φ1
The pipelined quantizer architecture has 11 stages with each
stage containing a 2-bit quantizer and a 2-bit Digital-to-
Analog Converter (DAC), as shown in Figure 2. Each 2-bit
quantizer stage converts on the edge of the sub-clock, which
is twice the frequency of the externally applied clock. The
output of each quantizer is fed into its own delay line to time-
FIGURE 1. Input Track-and-Hold Configuration with Timing
Signals.
IN
Digital Delay
Input
T/H
IN
2-Bit
Flash
2-Bit
DAC
+
STAGE 1
–
Σ
x2
B1 (MSB)
Digital Delay
B2
B3
B4
B5
B6
B7
B8
B9
B10
2-Bit
Flash
2-Bit
DAC
STAGE 2
+
–
Σ
x2
B11
Digital Delay
B12 (LSB)
2-Bit
Flash
2-Bit
DAC
STAGE 10
+
–
Σ
x2
2-Bit
Flash
Digital Delay
STAGE 11
FIGURE 2. Pipeline A/D Converter Architecture.
ADS802
SBAS039B
9
www.ti.com
align it with the data created from the following quantizer
stages. This aligned data is fed into a digital error correction
circuit that can adjust the output data based on the informa-
tion found on the redundant bits. This technique gives the
ADS802 excellent differential linearity and ensures no miss-
ing codes at the 12-bit level.
DIGITAL OUTPUT DATA
The 12-bit output data is provided at CMOS logic levels. The
standard output coding is Straight Offset Binary (SOB) where
a full-scale input signal corresponds to all “1s” at the output,
as shown in Table I. This condition is met with pin 19 “LO” or
Floating due to an internal pull-down resistor. By applying a
logic “HI” voltage to this pin, a Binary Two’s Complement
(BTC) output will be provided where the most significant bit
is inverted. The digital outputs of the ADS802 can be set to
a high-impedance state by driving OE (pin 18) with a logic
“HI”. Normal operation is achieved with pin 18 “LO” or floating
due to internal pull-down resistors. This function is provided
for testability purposes and is not meant to drive digital buses
directly, or be dynamically changed during the conversion
process.
Since there are two pipeline stages per external clock cycle,
there is a 6.5 clock cycle data latency from the start convert
signal to the valid output data. The output data is available in
Straight Offset Binary (SOB) or Binary Two’s Complement
(BTC) format.
THE ANALOG INPUT AND INTERNAL REFERENCE
The analog input of the ADS802 can be configured in various
ways and driven with different circuits, depending on the
nature of the signal and the level of performance desired.
The ADS802 has an internal reference that sets the full-scale
input range of the A/D converter. The differential input range
has each input centered around the common-mode of +2.25V,
with each of the two inputs having a full-scale range of
+1.25V to +3.25V. Since each input is 2Vp-p and 180° out-
of-phase with the other, a 4V differential input signal to the
quantizer results. As shown in Figure 3, the positive full-scale
reference (REFT) and the negative full-scale (REFB) are
brought out for external bypassing. In addition, the common-
mode voltage (CM) may be used as a reference to provide
the appropriate offset for the driving circuitry. However, care
must be taken not to appreciably load this reference node.
For more information regarding external references, single-
ended input, and ADS802 drive circuits, refer to the applica-
tions section.
OUTPUT CODE
SOB
PIN 19
FLOATING or LOW
BTC
PIN 19
HIGH
DIFFERENTIAL INPUT(1)
+FS (IN = +3.25V, IN = +1.25V)
+FS – 1LSB
+FS – 2LSB
+3/4 Full-Scale
+1/2 Full-Scale
+1/4 Full-Scale
+1LSB
Bipolar Zero (IN = IN = +2.25V)
–1LSB
–1/4 Full-Scale
111111111111
111111111111
111111111110
111000000000
110000000000
101000000000
100000000001
100000000000
011111111111
011000000000
010000000000
001000000000
000000000001
000000000000
011111111111
011111111111
011111111110
011000000000
010000000000
001000000000
000000000001
000000000000
111111111111
111000000000
110000000000
101000000000
100000000001
100000000000
–1/2 Full-Scale
–3/4 Full-Scale
–FS + 1LSB
–FS (IN = +1.25V, IN = +3.25V)
NOTE: (1) In the single-ended input mode, +FS = +4.25V and –FS = +0.25V.
TABLE I. Coding Table for the ADS802.
ADS802
+3.25V
APPLICATIONS
REFT
23
DRIVING THE ADS802
0.1µF
2kΩ
The ADS802 has a differential input with a common-mode of
+2.25V. For AC-coupled applications, the simplest way to
create this differential input is to drive the primary winding of
a transformer with a single-ended input. A differential output is
created on the secondary if the center tap is tied to the
common-mode voltage of +2.25V, as in Figure 4. This trans-
To
Internal
Comparators
CM
22
21
+2.25V
2kΩ
REFB
0.1µF
+1.25V
FIGURE 3. Internal Reference Structure.
22 CM
0.1µF
CLOCK REQUIREMENTS
26
IN
IN
The CLK pin accepts a CMOS level clock input. The rising
and falling edges of the externally applied convert command
clock controls the various interstage conversions in the
pipeline. Therefore, the duty cycle of the clock should be held
at 50% with low jitter and fast rise-and-fall times of 2ns or
less. This is particularly important when digitizing a high-
frequency input and operating at the maximum sample rate.
Deviation from a 50% duty cycle will effectively shorten some
of the interstage settling times, thus degrading the SNR and
DNL performance.
ac Input
Signal
ADS802
22pF
27
22pF
Mini-Circuits
TT1-6-KK81
or Equivalent
FIGURE 4. AC-Coupled Single-Ended to Differential Drive
Circuit Using a Transformer.
ADS802
10
SBAS039B
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former-coupled input arrangement provides good high-fre-
quency AC performance. It is important to select a transformer
that gives low distortion and does not exhibit core saturation at
full-scale voltage levels. Since the transformer does not appre-
ciably load the ladder, there is no need to buffer the Common-
Mode (CM) output in this instance. In general, it is advisable
to keep the current draw from the CM output pin below 0.5µA
to avoid nonlinearity in the internal reference ladder. A FET
input operational amplifier, such as the OPA130, can provide
a buffered reference for driving external circuitry. The analog
IN and IN inputs should be bypassed with 22pF capacitors to
minimize track-and-hold glitches and to improve high input
frequency performance.
mined by fC = 1/(2pRSER • (CSH + CADC)), where RSER is the
resistor in series with the input, CSH is the external capacitor
from the input to ground, and CADC is the internal input
capacitance of the A/D converter (typically 4pF).
Resistors R1 and R2 are used to derive the necessary
common-mode voltage from the buffered top and bottom
references. The total load of the resistor string should be
selected so that the current does not exceed 1mA. Although
the circuit in Figure 5 uses two resistors of equal value so
that the common-mode voltage is centered between the top
and bottom reference (+2.25V), it is not necessary to do so.
In all cases the center point, VCM, should be bypassed to
ground in order to provide a low-impedance AC ground.
Figure 5 illustrates another possible low-cost interface circuit
that utilizes resistors and capacitors in place of a trans-
former. Depending on the signal bandwidth, the component
values should be carefully selected in order to maintain the
product performance. The input capacitors, CIN, and the input
resistors, RIN, create a high-pass filter with the lower corner
frequency at fC = 1/(2pRINCIN). The corner frequency can be
reduced by either increasing the value of RIN or CIN. If the
circuit operates with a 50Ω or 75Ω impedance level, the
resistors are fixed and only the value of the capacitor can be
increased. Usually AC-coupling capacitors are electrolytic or
tantalum capacitors with values of 1µF or higher. It should be
noted that these large capacitors become inductive with
increased input frequency, which could lead to signal ampli-
tude errors or oscillation. To maintain a low AC-coupling
impedance throughout the signal band, a small value (e.g.
1µF) ceramic capacitor could be added in parallel with the
polarized capacitor.
If the signal needs to be DC-coupled to the input of the
ADS802, an operational amplifier input circuit is required. In
the differential input mode, any single-ended signal must be
modified to create a differential signal. This can be accom-
plished by using two operational amplifiers; one in the
noninverting mode for the input and the other amplifier in the
inverting mode for the complementary input. The low distor-
tion circuit in Figure 6 will provide the necessary input shifting
required for signals centered around ground. It also employs
a diode for output level shifting to ensure a low distortion
+3.25V output swing. Other amplifiers can be used in place
of the OPA842s if the lowest distortion is not necessary. If
output level shifting circuits are not used, care must be taken
to select operational amplifiers that give the necessary per-
formance when swinging to +3.25V with a ±5V supply opera-
tional amplifier.
The ADS802 can also be configured with a single-ended
input full-scale range of +0.25V to +4.25V by tying the
complementary input to the common-mode reference volt-
age (see Figure 7). This configuration will result in increased
even-order harmonics, especially at higher input frequen-
cies. However, this tradeoff may be quite acceptable for time-
domain applications. The driving amplifier must give ad-
equate performance with a +0.25V to +4.25V output swing in
this case.
Capacitors CSH1 and CSH2 are used to minimize current
glitches resulting from the switching in the input track-and-
hold stage and to improve signal-to-noise performance. These
capacitors can also be used to establish a low-pass filter and
effectively reduce the noise bandwidth. In order to create a
real pole, resistors RSER1 and RSER2 were added in series
with each input. The cutoff frequency of the filter is deter-
C1
0.1µF
R1
(6kΩ)
(1)
CIN
0.1µF
RSER1
+3.25V
Top Reference
49.9Ω
IN
IN
CSH1
22pF
RIN1
25Ω
R3
1kΩ
ADS8xx
VCM
C2
0.1µF
RIN2
25Ω
(1)
CIN
0.1µF
RSER2
49.9Ω
CSH2
22pF
+1.25V
Bottom Reference
R2
(6kΩ)
C3
0.1µF
NOTE: (1) Indicates optional component.
FIGURE 5. AC-Coupled Differential Input Circuit.
ADS802
SBAS039B
11
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+5V
604Ω
+5V
301Ω
BAS16(1)
Optional
High Impedance
Input Amplifier
27 IN
301Ω
OPA842
301Ω
2.49kΩ
0.1µF
22pF
+5V(2)
0.1µF
+5V
–5V
604Ω
DC-Coupled
Input Signal
ADS802
OPA842
604Ω
49.9Ω
+2.25V
OPA130
2.49kΩ
22 CM
+5V
–5V
+5V
24.9Ω
301Ω
Input Level
Shift Buffer
301Ω
BAS16(1)
0.1µF
26 IN
OPA842
22pF
–5V
604Ω
NOTES: (1) A Philips BAS16 diode or equivalent
may be used. (2) Supply bypassing not shown.
301Ω
FIGURE 6. A Low-Distortion, DC-Coupled, Single-Ended to Differential Input Driver Circuit.
For the differential configuration, the full-scale input
range will be set to the external reference values that are
selected. For the single-ended mode, the input range is
2 • (REFTEXT – REFBEXT), with the common-mode being
centered at (REFTEXT + REFBEXT)/2. Refer to the typical
characteristics for expected performance versus full-scale
input range.
22 CM
0.1µF
ADS802
Single-Ended
Input Signal
26 IN
27 IN
22pF
The circuit in Figure 8 works completely on a single +5V
supply. As a reference element, it uses micro-power refer-
ence REF1004-2.5 that is set to a quiescent current of
0.1mA. Amplifier A2 is configured as a follower to buffer the
+1.25V generated from the resistor divider. To provide the
necessary current drive, a pull-down resistor (RP) is added.
Full-Scale = +0.25V to +4.25V with internal references.
FIGURE 7. Single-Ended Input Connection.
EXTERNAL REFERENCES AND ADJUSTMENT
OF FULL-SCALE RANGE
Amplifier A1 is configured as an adjustable-gain stage, with
a range of approximately 1 to 1.32. The pull-up resistor again
relieves the op amp from providing the full current drive. The
value of the pull-up, pull-down resistors is not critical and can
be varied to optimize power consumption. The need for pull-
up, pull-down resistors depends only on the drive capability
of the selected drive amplifiers, and thus can be omitted.
The internal reference buffers are limited to approximately
1mA of output current. As a result, these internal +1.25V and
+3.25V references may be overridden by external references
that have at least 18mA (at room temperature) of output drive
capability. In this instance, the common-mode voltage will be
set halfway between the two references. This feature can be
used to adjust the gain error, improve gain drift, or to change
the full-scale input range of the ADS802. Changing the full-
scale range to a lower value has the benefit of easing the
swing requirements of external input amplifiers. The external
references can vary as long as the value of the external top
reference (REFTEXT) is less than or equal to +3.4V, the value
of the external bottom reference (REFBEXT) is greater than or
equal to +1.1V, and the difference between the external
references are greater than or equal to 1.5V.
PC-BOARD LAYOUT AND BYPASSING
A well-designed, clean pc-board layout will assure proper
operation and clean spectral response. Proper grounding and
bypassing, short lead lengths, and the use of ground planes
are particularly important for high-frequency circuits. Multilayer
pc-boards are recommended for best performance, but if
carefully designed, a two-sided pc-board with large, heavy
ADS802
12
SBAS039B
www.ti.com
+5V
RP
220Ω
A1
Top
1/2
OPA2234
Reference
+5V
+2.5V to +3.25V
2kΩ
10kΩ
6.2kΩ
10kΩ
REF1004
10kΩ(1)
A2
+2.5V
0.1µF
+1.25V
1/2
Bottom
Reference
OPA2234
10kΩ
RP
10kΩ(1)
220Ω
NOTE: (1) Use parts alternatively for adjustment capability.
FIGURE 8. Optional External Reference to Set the Full-Scale Range Utilizing a Dual, Single-Supply Op Amp.
ground planes can give excellent results. It is recommended
that the analog and digital ground pins of the ADS802 be
connected directly to the analog ground plane. In our experi-
ence, this gives the most consistent results. The A/D converter
power-supply commons should be tied together at the analog
ground plane. Power supplies should be bypassed with 0.1µF
ceramic capacitors as close to the pin as possible.
DYNAMIC PERFORMANCE DEFINITIONS
1.
2.
3.
Signal-to-Noise-and-Distortion Ratio (SINAD):
Sinewave SignalPower
10 log
Noise + Harmonic Power first 15 harmonics
(
)
Signal-to-Noise Ratio (SNR):
Sinewave SignalPower
10 log
NoisePower
DYNAMIC PERFORMANCE TESTING
Intermodulation Distortion (IMD):
The ADS802 is a high-performance converter and careful
attention to test techniques is necessary to achieve accurate
results. Highly accurate phase-locked signal sources allow
high resolution FFT measurements to be made without using
data windowing functions. A low-jitter signal generator, such
as the HP8644A for the test signal, phase-locked with a low-
jitter HP8022A pulse generator for the A/D converter clock,
gives excellent results. Low-pass filtering (or bandpass filter-
ing) of test signals is absolutely necessary to test the low
distortion of the ADS802. Using a signal amplitude slightly
lower than full-scale will allow a small amount of “headroom”
so that noise or DC-offset voltage will not overrange the A/D
converter and cause clipping on signal peaks.
Highest IMDProduct Power to 5th − order
(
)
10 log
Sinewave SignalPower
IMD is referenced to the larger of the test signals f1 or f2. Five
“bins” either side of peak are used for calculation of funda-
mental and harmonic power. The “0” frequency bin (DC) is
not included in these calculations, as it is of little importance
in dynamic signal processing applications.
ADS802
SBAS039B
13
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FIGURE 9. ADS802 Interface Schematic with AC-Coupling and External Buffers.
ADS802
14
SBAS039B
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS802U
ACTIVE
SOIC
DW
28
20
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS802U
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
DW SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ADS802U
28
20
506.98
12.7
4826
6.6
Pack Materials-Page 1
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