ADS808Y/250 [TI]

12-Bit, 70-MSPS Analog-to-Digital Converter (ADC) 48-HTQFP -40 to 85;


型号：	ADS808Y/250
厂家：	TEXAS INSTRUMENTS
描述：	12-Bit, 70-MSPS Analog-to-Digital Converter (ADC) 48-HTQFP -40 to 85 转换器
文件：	总23页 (文件大小：886K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS808

SBAS179C – DECEMBER 2000 – REVISED SEPTEMBER 2002

12-Bit, 70MHz Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

DESCRIPTION

● DYNAMIC RANGE:

SNR: 64dB at 10MHz f_IN

SFDR: 68dB at 10MHz f_IN

The ADS808 is a high-dynamic range, 12-bit, 70MHz,

pipelined Analog-to-Digital Converter (ADC). It includes a

high-bandwidth linear track-and-hold that has a low jitter of

only 0.25ps rms, leading to excellent SNR performance. The

clock input can accept a low-level differential sine wave or

square wave signal down to 0.5Vp-p, further improving the

SNR performance. It also accepts a single-ended clock

signal and has flexible threshold levels.

● PREMIUM TRACK-AND-HOLD:

Low Jitter: 0.25ps rms

Differential or Single-Ended Inputs

Selectable Full-Scale Input Range

● FLEXIBLE CLOCKING:

The ADS808 has a 2Vp-p differential input range (1Vp-p • 2

inputs) for optimum signal-to-noise ratio. The differential

operation gives the lowest even-order harmonic compo-

nents. A lower input voltage of 1.5Vp-p or 1Vp-p can also be

selected using the internal references, further optimizing

SFDR. Alternatively, a single-ended input range can be used

by tying the IN input to the common-mode voltage, if desired.

Differential or Single-Ended

Accepts Sine or Square Wave Clocking

Down to 0.5Vp-p

Variable Threshold Level

APPLICATIONS

● BASESTATION WIDEBAND RADIOS:

The ADS808 also provides an over-range flag that indicates

when the input signal has exceeded the converter’s full-scale

range. This flag can also be used to reduce the gain of the

front-end signal conditioning circuitry. It also employs digital

error-correction techniques to provide excellent differential

linearity for demanding imaging applications. The ADS808 is

available in a small TQFP-48 PowerPAD™ thermally en-

hanced package.

CDMA, GSM, TDMA, 3G, AMPS, and NMT

● TEST INSTRUMENTATION

● CCD IMAGING

PowerPAD is a registered trademark of Texas Instruments.

+V_S

CLK

ADS808

Timing Circuitry

CLK

1Vp-p

12-Bit

Pipelined

ADC Core

Error

Correction

Logic

3-State

Outputs

•

T&H

D11

(+2.5V)

OVR

Reference Ladder

and Driver

Reference and

Mode Select

REFT

V_REFSEL1 SEL2

REFB

OE VDRV

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

www.ti.com

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas

Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper han-

dling and installation procedures can cause damage.

+V_S....................................................................................................... +6V

Analog Input .......................................................... (–0.3V) to (+V_S+ 0.3V)

Logic Input ............................................................ (–0.3V) to (+V_S+ 0.3V)

Case Temperature ......................................................................... +100°C

Junction Temperature .................................................................... +150°C

Storage Temperature ..................................................................... +150°C

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”

may cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

PACKAGE/ORDERING INFORMATION

SPECIFIED

PACKAGE

DESIGNATOR⁽¹⁾

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

PRODUCT

PACKAGE-LEAD

ADS808Y

TQFP-48

PHP

–40°C to +85°C

ADS808Y

ADS808Y/250

ADS808Y/2K

Tape and Reel, 250

Tape and Reel, 2000

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

ELECTRICAL CHARACTERISTICS

At T_A= full specified temperature range, differential input range = 1V to 2V, sampling rate = 70MHz, V_S= +5V, and internal reference, unless otherwise noted.

ADS808Y

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

RESOLUTION

12 Tested

Bits

SPECIFIED TEMPERATURE RANGE

Ambient Air

–40 to +85

°C

ANALOG INPUT

Standard Differential Input Range

Single-Ended Input Voltage

Common-Mode Voltage

Optional Input Ranges

Analog Input Bias Current

Track-Mode Input Bandwidth

Input Impedance

(1Vp-p • 2, +10dBm)

µA

1Vp-p

2.5

Selectable

1Vp-p or 1.5Vp-p

–3dBFS

Static, No Clock

GHz

MΩ || pF

1.25 || 9

CONVERSION CHARACTERISTICS

Sample Rate

Data Latency

70M

Samples/s

Clk Cyc

DYNAMIC CHARACTERISTICS

Differential Linearity Error (largest code error)

f = 1MHz

±0.7

Tested

±4.0

+1.7/–1.0

±7.0

LSB

No Missing Codes

Integral Nonlinearity Error, f = 1MHz

Spurious-Free Dynamic Range⁽¹⁾

f = 1MHz

LSBs

dBFS⁽²⁾

dBFS

f = 10MHz

2-Tone Intermodulation Distortion

f_IN= 19.4MHz and 20.4MHz (–7dB each tone)

Signal-to-Noise Ratio (SNR)

f = 1MHz

–77

dBFS

64.5

dBFS

f = 10MHz

Signal-to-(Noise + Distortion) (SINAD)

f = 2.2MHz

f = 10MHz

Output Noise

Aperture Delay Time

0.3

dBFS

LSBs rms

Input AC-Grounded

Aperture Jitter

Over-Voltage Recovery Time

Full-Scale Step Acquisition Time

0.25

ps rms

DIGITAL INPUTS

Logic Family

Convert Command

+3V/+5V Logic Compatible CMOS

Rising Edge of Convert Clock

Start Conversion

High-Level Input Current (V_IN= 5V)⁽³⁾

Low-Level Input Current (V_IN= 0V)

High-Level Input Voltage

Low-Level Input Voltage

Input Capacitance

100

±10

µA

+2.0

+1.0

ADS808

SBAS179C

www.ti.com

ELECTRICAL CHARACTERISTICS (Cont.)

At T_A= full specified temperature range, differential input range = 1V to 2V, sampling rate = 70MHz, V_S= +5V, and internal reference, unless otherwise noted.

ADS808Y

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DIGITAL OUTPUTS

Logic Family

Logic Coding

+3V/+5V Compatible CMOS

Straight Offset Binary

Low Output Voltage (I_OL= 50µA to 1.6mA)

High Output Voltage, (I_OH= 50µA to 0.5mA)

Low Output Voltage, (I_OL= 50µA to 1.6mA)

High Output Voltage, (I_OH= 50µA to 1.6mA)

3-State Enable Time

VDRV = 3V

VDRV = 5V

+0.2

+2.5

OE = LOW

OE = HIGH

3-State Disable Time

Output Capacitance

ACCURACY (Internal Reference, = 2V, Unless Otherwise Noted)

Zero Error (Midscale)

Zero Error Drift (Midscale)

Gain Error⁽⁴⁾

at 25°C

0.5

±1.5

±0.75

%FS

ppm/°C

%FS

ppm/°C

%FS

ppm/°C

at 25°C

Gain Error Drift⁽⁴⁾

Gain Error⁽⁵⁾

Gain Error Drift⁽⁵⁾

Power-Supply Rejection of Gain

Internal REF Tolerance (V_REFP– V_REFN

Reference Input Resistance

∆V_S= ±5%

Deviation from Ideal

)

±10

660

±40

Ω

POWER-SUPPLY REQUIREMENTS

Supply Voltage: +V_S

Supply Current: +I_S

Output Driver Supply Current (VDRV)

Power Dissipation: VDRV = 5V

VDRV = 3V

Operating

+4.75

+5.0

142

740

720

700

+5.25

Internal Reference

External Reference

Operating

770

VDRV = 5V

VDRV = 3V

Power Down

Thermal Resistance, θ_JA

TQFP-48

28.8

°C/W

NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full-Scale. (3) A 50kΩ pull-down

resistor is inserted internally. (4) Includes internal reference. (5) Excludes internal reference.

ADS808

SBAS179C

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PIN DIAGRAM

Top View

TQFP

48 47 46 45 44 43 42 41 40 39 38 37

BYP

+V_S

36 GND

35 GND

34 V_REF

33 SEL1

32 SEL2

31 GND

30 BTC

29 PD

+V_S

GND

CLK

GND

ADS808Y

28 OE

OVR 10

DV 11

NC 12

27 GND

26 VDRV

25 D0 (LSB)

13 14 15 16 17 18 19 20 21 22 23 24

PIN DESCRIPTIONS

I/O

DESIGNATOR

DESCRIPTION

I/O

DESIGNATOR

DESCRIPTION

BYP

+V_S

GND

CLK

GND

OVR

D11

D10

Bypass Point

VDRV

GND

Output Bit Driver Voltage Supply

Ground

Supply Voltage

Ground

Clock Input

Complementary Clock Input

Ground

Output Enable: HI = High Impedance;

LO or Floating: Normal Operation

Power Down: HI = Power Down; LO = Normal

HI = Binary Two’s Complement;

LO = Straight Binary

Ground

Reference Select 2: See Table on Page 5.

Reference Select 1: See Table on Page 5.

Internal Reference Voltage

Ground

BTC

GND

SEL2

SEL1

V_REF

GND

REFB

REFT

GND

Ground

Over-Range Indicator

Data Valid Pulse: HI = Data Valid

No Connection

Data Bit 11, (MSB)

Data Bit 10

Data Bit 9

Data Bit 8

Data Bit 7

Data Bit 6

Data Bit 5

Data Bit 4

Data Bit 3

Data Bit 2

Data Bit 1

Data Bit 0, (LSB)

Ground

Bottom Reference Voltage Bypass

Common-Mode Voltage (mid-scale)

Top Reference Voltage Bypass

Ground

Complementary Analog Input

Ground

Analog Input

Supply Voltage

+V_S

ADS808

SBAS179C

www.ti.com

TIMING DIAGRAM

N + 6

N + 4

t_A

N + 7

N + 3

t_H

Analog In

Clock

N + 5

N + 1

t_CONV

N + 2

t_L

t₁

5 Clock Cycles

Data Bits Out

N – 5

N – 4

N – 3

N – 2

N – 1

N + 1

t₂

t_DV

Data Valid Pulse

SYMBOL

DESCRIPTION

MIN⁽¹⁾

TYP

MAX⁽¹⁾

UNITS

t_CONV

t_H

t_L

t_A

t_DV

t₁

Convert Clock Period

Clock Pulse HIGH

Clock Pulse LOW

Aperture Delay

Data Valid Pulse Delay⁽²⁾

Data Hold Time, C_L= 0pF

14.3

1µs

t_CONV/2

4.6

11.5

6.1

t₂

New Data Delay Time, C_L= 15pF max

NOTES: (1) Timing values based on simulation at room temperature. Min/Max values provided for

design estimation only. (2) Measured from the 50% point of the clock to the time when signals are

within valid logic levels.

REFERENCE AND FULL-SCALE RANGE SELECT

DESIRED

FULL-SCALE RANGE

INTERNAL

V_REF

SEL1

SEL2

1Vp-p

1.5Vp-p

2Vp-p

V_REF

GND

+V_S

GND

0.5V

0.75V

1.0V

NOTE: For external reference operation, tie V_REFto +V_Sand apply REFT and REFB externally. Internal voltage buffer of CM is powered up. The full-scale input range

is equal to 2x the reference value (REFT – REFB).

ADS808

SBAS179C

www.ti.com

TYPICAL CHARACTERISTICS

At T_A= full specified temperature range, differential input range = 1V to 2V, sampling rate = 70MHz, and internal reference, unless otherwise noted.

SPECTRAL PERFORMANCE

(Differential, 2Vp-p)

DYNAMIC PERFORMANCE

vs SAMPLING FREQUENCY

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

f_IN= 1MHz (–1.0dBFS)

f_IN= 1MHz

SFDR

SFDR = 71.40dBFS

SNR = 64.41dBFS

SINAD = 63.33dBFS

SNR

SINAD

50 55

Frequency (MHz)

Sampling Frequency (MHz)

DYNAMIC PERFORMANCE

vs SAMPLING FREQUENCY

(2Vp-p, Differential)

DYNAMIC PERFORMANCE

vs SAMPLING FREQUENCY

(2Vp-p, Differential)

f_IN= 10MHz

f_IN= 20MHz

SFDR

SNR

SINAD

50 55

Sample Frequency (MHz)

DYNAMIC PERFORMANCE vs INPUT FREQUENCY

SFDR

TOTAL POWER vs SAMPLING FREQUENCY

f_IN= 10MHz

760

740

720

700

680

660

640

620

600

580

560

540

520

500

f_IN= 1MHz

SNR

SINAD

45 50

Input Frequency (MHz)

Sampling Frequency (MHz)

ADS808

SBAS179C

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TYPICAL CHARACTERISTICS (Cont.)

At T_A= full specified temperature range, differential input range = 1V to 2V, sampling rate = 70MHz, and internal reference, unless otherwise noted.

INTEGRAL LINEARITY ERROR

DIFFERENTIAL LINEARITY ERROR

0.8

0.6

0.4

0.3

–0.2

–0.4

–0.6

–0.8

–1

–2

–3

1024

2048

Code

3072

4096

1024

2048

Code

3072

4096

OUTPUT NOISE HISTOGRAM

(2Vp-p, Grounded Input)

300k

250k

200k

150k

100k

50k

N – 2

N – 1

N + 1

N + 2

Code

ADS808

SBAS179C

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particularly suited for communication systems that digitize

wideband signals. Features on the ADS808, like the input

range selector or the option of an external reference, provide

the needed flexibility to accommodate a wide range of

applications. In any case, the analog interface/driver require-

ments should be carefully examined before selecting the

appropriate circuit configuration. The circuit definition should

include considerations on the input frequency spectrum and

amplitude, single-ended versus differential driver configura-

tion, as well as the available power supplies.

APPLICATION INFORMATION

THEORY OF OPERATION

The ADS808 is a high-speed, high-performance, CMOS

ADC built with a fully differential, 9-stage pipeline architec-

ture. Each stage contains a low-resolution quantizer and

digital error-correction logic, ensuring excellent differential

linearity and no missing codes at the 12-bit level. The

conversion process is initiated by a rising edge of the

external convert clock. Once the signal is captured by the

input track-and-hold amplifier, the bits are sequentially en-

coded starting with the MSB. This process results in a data

latency of five clock cycles, after which the output data is

available as a 12-bit parallel word either coded in a straight

binary or binary two’s complement format.

Differential versus Single-Ended

The ADS808 input structure allows it to be driven either

single-ended or differentially. Differential operation of the

ADS808 requires an input signal that consists of an in-phase

and a 180° out-of-phase component simultaneously applied

to the inputs (IN, IN). Differential signals offer a number of

advantages that in many applications will be instrumental in

achieving the best harmonic performance of the ADS808:

The analog input of the ADS808 consists of a differential

track-and-hold circuit, as shown in Figure 1. The differential

topology produces a high level of AC-performance at high

sampling rates. It also results in a very high usable input

bandwidth that is especially important for IF, or undersampling

applications. Both inputs (IN, IN) require external biasing up

to a common-mode voltage that is typically at the mid-supply

level (+V_S/2). This is because the on-resistance of the CMOS

switches is lowest at this voltage, minimizing the effects of

the signal dependent nonlinearity of R_ON. The track-and-hold

circuit can also convert a single-ended input signal into a fully

differential signal for the quantizer. For ease of use, the

ADS808 incorporates a selectable voltage reference, a ver-

satile clock input, and a logic output driver designed to

interface to 3V or 5V logic.

•

The signal amplitude is half of that required for the single-

ended operation and is, therefore, less demanding to

achieve while maintaining good linearity performance from

the signal source.

•

The reduced signal swing allows for more headroom of

the interface circuitry and, therefore, a wider selection of

the best suitable driver amplifier.

•

Even-order harmonics are minimized.

Improves the noise immunity based on the converter’s

common-mode input rejection.

For the single-ended mode, the signal is applied to one of the

inputs while the other input is biased with a DC voltage to the

required common-mode level. Both inputs are identical in

terms of their impedance and performance except that apply-

ing the signal to the complementary input (IN) instead of the

IN-input will invert the orientation of the input signal relative

to the output code. For example, if the input driver operates

in inverting mode using IN as the signal input, it will restore

the phase of the signal to its original orientation. Time-

domain applications may benefit from a single-ended inter-

face configuration and a reduced circuit complexity. Driving

the ADS808 with a single-ended signal will result in a trade-

off of the excellent distortion performance, while maintaining

a good signal-to-noise ratio (SNR). The trade-off of the

differential input configuration over the single-ended is its

increase in circuit complexity. In either case, the selection of

the driver amplifier should be such that the amplifier’s perfor-

mance will not degrade the A/D converter’s performance.

S₅

ADS808

S₃

S₁

S₂

C_IN

T&H

S₄

S₆

Tracking Phase: S₁, S₂, S₃, S₄Closed; S₅, S₆Open

Hold Phase: S₁, S₂, S₃, S₄Open; S₅, S₆Closed

FIGURE 1. Simplified Circuit of Input Track-and-Hold Amplifier.

Input Full-Scale Range versus Performance

Employing dual-supply amplifiers and AC-coupling will usually

yield the best results. DC-coupling and/or single-supply ampli-

fiers impose additional design constrains due to their head-

room requirements, especially when selecting the 2Vp-p input

range. The full-scale input range of the ADS808 is defined

either by the settings of the reference select pins (SEL1,

SEL2) or by an external reference voltage (see Table I).

DRIVING THE ANALOG INPUTS

Types of Applications

The analog input of the ADS808 can be configured in various

ways and driven with different circuits, depending on the

application and the desired level of performance. Offering a

high dynamic range at high input frequencies, the ADS808 is

ADS808

SBAS179C

www.ti.com

By choosing between the three different signal input ranges,

trade-offs can be made between noise and distortion perfor-

mance. In order to maximize the SNR, which is important for

time-domain applications, the 2Vp-p range may be se-

lected. This range may also be used with low-level (–6dBFS

to –40dBFS) to high-frequency inputs (multi-tone). The

1.5Vp-p range may be considered for achieving a combina-

tion of both low noise and distortion performance. Here the

SNR number is typically 3dB down compared to the 2Vp-p

range, while an improvement in the distortion performance

of the driver amplifier may be realized due to the reduced

output power level required. The third option, 1Vp-p FSR,

may be considered mainly for applications requiring DC-

coupling and/or single-supply operation of the driver and the

converter.

ADS808 INPUT IMPEDANCE vs INPUT FREQUENCY

1000

100

0.1

0.01

0.1

100

1000

_IN(MHz)

Input Biasing (V_CM

)

FIGURE 2. Differential Input Impedance versus Input

Frequency.

The ADS808 operates from a single +5V supply, and re-

quires each of the analog inputs to be externally biased to a

common-mode voltage of typically +2.5V. This allows a

symmetrical signal swing while maintaining sufficient head-

room to either supply rail. Communication systems are usu-

ally AC-coupled in-between signal processing stages, mak-

ing it convenient to set individual common-mode voltages

and allow optimizing the DC operating point for each stage.

Other applications (e.g., imaging) process only unipolar or

DC-restored signals. In this case, the common-mode voltage

may be shifted such that the full-input range of the converter

is utilized.

noise ratio, however, depending on the signal source, large

resistor values may reduce the harmonic distortion perfor-

mance. In any case, the use of the RC network is optional but

optimizing the values to adapt to the specific application is

encouraged.

INPUT DRIVER CONFIGURATIONS

The following section provides some principal circuit sugges-

tions on how to interface the analog input signal to the

ADS808. A first example of a typical analog interface circuit

is shown in Figure 3. Here it is assumed that the input signal

is already available in differential form (e.g., coming from a

preceding mixer stage). The differential driver performs an

impedance transformation as well as amplifying the signal to

match the selected full-scale input range of the ADS808 (for

example, 2Vp-p). The common-mode voltage (V_CM) for the

converter input is established by connecting the inputs to the

midpoints of the resistor divider. The input signal is AC-

coupled through capacitors C_INto the inputs of the converter

It should be noted that the CM pin is internally buffered.

However, it is recommended to keep the loading of this pin

to a minimum to avoid an increase in the converter’s

nonlinearity. Additionally, the DC voltage at the CM pin is not

exactly +2.5V, but is subject to the tolerance of the top and

bottom references, as well as the resistor ladder.

Input Impedance

The input of the ADS808 is of a capacitive nature and the

driving source needs to provide the slew current to charge or

discharge the input sampling capacitor while the track-and-

hold amplifier is in track mode (see Figure 1). This effectively

results in a dynamic input impedance that is a function of the

sampling frequency. Figure 2 depicts the differential input

impedance of the ADS808 as a function of the input fre-

quency.

that are set to a V_CMof approximately +2.5V_DC

1kΩ

C_IN

0.1µF

For applications that use op amps to drive the ADC, it is

recommended to add a series resistor between the amplifier

output and the converter inputs. This will isolate the converter’s

capacitive input from the driving source and avoid gain

peaking, or instability. Furthermore, it will create a 1st-order,

low-pass filter in conjunction with the specified input capaci-

tance of the ADS808. Its cutoff frequency can be adjusted

even further by adding an external shunt capacitor from each

signal input to ground. However, the optimum values of this

RC network depend on a variety of factors, including the

ADS808’s sampling rate, the selected op amp, the interface

configuration, and the particular application (time domain

versus frequency domain). Generally, increasing the size of

the series resistor and/or capacitor will improve the signal-to-

REFT

V_IN

Differential

Driver

C_IN

0.1µF

V_CM= +2.5V

ADS808

V_IN

REFB

1kΩ

NOTE: Reference bypassing omitted for clarity.

FIGURE 3. AC Coupling Allows for Easy DC Biasing of the

ADS808 Inputs While the Input Signal is Applied

by the Differential Input Driver.

ADS808

SBAS179C

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Some differential driver circuits may allow setting an appropri-

ate common-mode voltage directly at the driver input. This will

simplify the interface to the ADS808 and eliminate the external

biasing resistors and the coupling capacitors. Texas Instru-

ments offers a line of fully differential high-speed amplifiers

(refer to our web site at www.ti.com). The THS4150, for

example, may be used for input frequencies from DC to

approximately 10MHz, for which the part maintains good

distortion performance, providing a 2Vp-p (max) output swing

on ±5V supplies. Combining a differential driver circuit with a

step-up transformer can lead to significant improvement of the

distortion performance (see Figure 6).

A variety of miniature RF transformers are readily available

from different manufacturers, i.e., Mini-Circuits, Coilcraft, or

Trak. When choosing a selection, it is important to carefully

examine the application requirements and determine the

correct model, the desired impedance ratio, and frequency

characteristics. Furthermore, the appropriate model must

support the targeted distortion level and should not exhibit

any core saturation at full-scale voltage levels. Since the

transformer does not appreciably load the ladder, its center

tap can be directly tied to the CM pin of the converter, as

shown in Figure 4. The value of termination resistor (R_T)

should be chosen to satisfy the termination requirements of

the source impedance (R_S). It can be calculated using the

equation R_T= n²• R_Sto ensure proper impedance matching.

Transformer Coupled Interface Circuits

If the application allows for AC-coupling, but requires a signal

conversion from a single-ended source to drive the ADS808

differentially, using a transformer offers a number of advan-

tages. As a passive component, it does not add to the total

noise; plus by using a step-up transformer, further signal

amplification can be realized. As a result, the signal swing

out of the amplifier driving the transformer can be reduced,

leading to more headroom for the amplifier and improved

distortion performance.

Transformer Coupled, Single-Ended to

Differential Configuration

For applications in which the input frequency is limited to

about 40MHz (e.g., baseband), the wideband, current-feed-

back, operational amplifier OPA685 may be used. As shown

in Figure 5, the OPA685 is configured for the noninverting

mode, amplifies the single-ended input signal, and drives the

primary of an RF transformer. To maintain the very low

distortion performance of the OPA685, it may be advanta-

geous to reduce the full-scale input range (FSR) of the

ADS808 from 2Vp-p to 1.5Vp-p or 1Vp-p (refer to the “Ref-

erence” section for details on selecting the converter’s full-

scale range).

One possible interface solution that uses a transformer is

given in Figure 4. The input signal is assumed to be an

Intermediate Frequency (IF) and bandpass filtered prior to

the IF amplifier. Dedicated IF amplifiers, for example the

RF2312 or MAR-6, are fixed-gain broadband amplifiers and

feature a very high bandwidth, a low-noise figure, and a high

intercept point at the expense of high quiescent currents of

50-120mA. The IF amplifier may be AC-coupled or directly

connected to the primary side of the transformer.

The circuit also shows the use of an additional RC low-pass

filter placed in series with each converter input. This optional

filter can be used to set a defined corner frequency and

+V_S

+5V

1:n

XFMR

R_S

0.1µF

R_IN

Optional

Bandpass

Filter

Amp

V_IN(IF)

C_IN

R_T

R_IN

ADS808

C_IN

–V_S

V_CM+2.5V

0.1µF

4.7µF

FIGURE 4. Driving the ADS808 with a Low Distortion RF Amplifier and a Transformer Suited for IF Sampling Applications.

+V –V

+5V

R_G

0.1µF

1:n

XFMR

R_S

R_IN

V_IN

OPA685

C_IN

R_T

ADS808

R₁

C_IN

V_CM+2.5V

R₂

0.1µF

2.2µF

FIGURE 5. Converting a Single-Ended Input Signal into a Differential Signal Using a RF Transformer.

ADS808

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attenuate some of the wideband noise. The actual compo-

nent values would need to be tuned for the individual appli-

cation requirements. As a guideline, resistor values are

typically in the range of 10Ω to 100Ω, capacitors in the range

of 10pF to 200pF. In any case, the R_INand C_INvalues should

have a low tolerance. This will ensure that the ADS808 sees

closely matched source impedances.

metrical layout, is instrumental in achieving a substantial

reduction of the 2nd-harmonic, while retaining excellent 3rd-

order performance. A common-mode voltage (V_CM) is ap-

plied to the noninverting inputs of the OPA685. Additional

series of 43.2Ω resistors isolate the output of the op amps

from the capacitive load presented by the 22pF capacitors

and the input capacitance of the ADS808. This 43.2Ω/22pF

combination sets a pole at approximately 167MHz and rolls

off some of the wideband noise.

AC-Coupled, Differential Interface with Gain

The interface circuit example presented in Figure 6 employs

two OPA685s, (current-feedback op amps), optimized for

gains of 8V/V or higher. The input transformer (T1) converts

the single-ended input signal to a differential signal required

at the amplifier’s inverting inputs, that are tuned to provide a

50Ω impedance match to an assumed 50Ω source. To

achieve the 50Ω input match at the primary of the 1:2

transformer, the secondary input must see a 200Ω load

impedance. Both amplifiers are configured for the inverting

mode resulting in close gain and phase matching of the

differential signal. This technique, along with a highly sym-

REFERENCE

REFERENCE OPERATION

Integrated into the ADS808 is a bandgap reference circuit

including some logic that provides a +0.5V, +0.75V, or +1V

reference output by selecting the corresponding pin-strap

configuration. Table I gives a complete overview of the

possible reference options and pin configurations.

+5V

Power-supply decoupling

not shown.

DIS

V_CM

OPA685

1:2

100Ω

600Ω

43.2Ω

50Ω Source

–5V

V_I

22pF

V_O

A/D Converter Input

Noise

Figure

11.8dB

600Ω

43.2Ω

+5V

OPA685

–5V

22pF

DIS

V_CM

V_O

V_I

= 12V/V (21.6dB)

FIGURE 6. Wideband Differential A/D Converter Driver.

DESIRED FULL-SCALE RANGE,

FSR (Differential)

CONNECT SEL1

(Pin 33)

CONNECT SEL2

(Pin 32)

VOLTAGE AT V_REF

(Pin 34)

VOLTAGE AT REFT

VOLTAGE AT REFB

(Pin 39)

(Pin 41)

2Vp-p (+10dBm)

1.5Vp-p (+7.5dBm)

1Vp-p

GND

V_REF

—

GND

+V_S

GND

—

+1.0V

+0.75V

+0.5V

+3V

+2.875V

+2V

+2.125V

+2.75V

+2.25V

External Reference

> +3.5V

+2.75V to +4.5V

+0.5V to +2.25V

TABLE I. Reference Pin Configurations and Corresponding Voltage on the Reference Pins.

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Figure 7 shows the basic model of the internal reference

circuit. The functional blocks are a 1V bandgap voltage

reference, a selectable gain amplifier, the drivers for the top

and bottom reference (REFT, REFB), and the resistive refer-

ence ladder. The ladder resistance measures approximately

660Ω between the REFT and REFB pin. The ladder is split

into two equal segments, establishing a common-mode volt-

age at the ladder midpoint, labeled “CM”. The ADS808

requires solid bypassing for all reference pins to keep the

effect of clock feedthrough to a minimum and to achieve the

specified level of performance. Figure 7 also demonstrates

the recommended decoupling scheme. All 0.1µF capacitors

should be located as close to the pins as possible.

Using External References

For even more design flexibility, the ADS808 can be oper-

ated with an external reference.

The utilization of an external reference voltage may be

considered for applications requiring higher accuracy, im-

proved temperature stability, or a continuous adjustment of

the converter’s full-scale range. Especially in multichannel

applications, the use of a common external reference offers

the benefit of improving the gain matching between convert-

ers. Selection between internal or external reference opera-

tion is controlled through the V_REFpin. The internal reference

will become disabled if the voltage applied to the V_REFpin

exceeds +3.5V_DC. Once selected, the ADS808 requires two

reference voltages—a top-reference voltage applied to the

REFT pin and a bottom-reference voltage applied to the

REFB pin (see Table I). As illustrated in Figure 8, a micropower

reference (REF1004) and a dual, single-supply amplifier may

be used to generate a precision external reference. Note that

the function of the range select pins, SEL1 and SEL2, are

disabled while the converter is in external mode.

When operating the ADS808 from the internal reference, the

effective full-scale input span for each of the inputs, IN and

IN, is determined by the voltages at REFT and REFB pins,

given as:

Input Span (differential) = 2x (REFT – REFB), in Vp-p = 2 • V_REF

The top and bottom reference outputs may be used to

provide up to 1mA (sink or source) of current to external

circuits. Degradation of the differential linearity (DNL) and,

consequently, of the dynamic performance of the ADS808

may occur if this limit is exceeded.

SEL1 SEL2

Range Select

and

Gain Amplifier

Top

Reference

Driver

ByP

REFT

0.1µF

330Ω

+1V_DC

0.1µF

Bandgap

Reference

1µF

330Ω

Bottom

Reference

Driver

REFB

ADS808

0.1µF

V_REF

FIGURE 7. Internal Reference Circuit of the ADS808 and Recommended Bypass Scheme.

+5V

1/2

OPA2234

REFT

4.7kΩ

2.2µF

0.1µF

R₃

ADS808

R₄

R₁

REF1004

+2.5V

10µF

1/2

OPA2234

REFB

R₂

0.1µF

2.2µF

0.1µF

FIGURE 8. Example for an External Reference Circuit Using a Dual, Single-Supply Op Amp.

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Applying a single-ended clock signal will provide satisfactory

results in many applications. However, unbalanced high-

speed logic signals often introduce a high amount of distur-

bances, such as ringing or ground bouncing. Also, a high

amplitude may cause the clock signal to have unsymmetrical

rise and fall times, potentially effecting the converter’s distor-

tion performance. Proper termination practice and a clean

PCB layout will help to keep those effects to a minimum.

DIGITAL INPUTS AND OUTPUTS

CLOCK INPUT

Unlike most A/D converters, the ADS808 contains an internal

clock conditioning circuitry. This enables the converter to

adapt to a variety of application requirements and different

clock sources. Some interface examples are given in the

following section. With no input signal connected to either

clock pin, the threshold level is set to about +1.6V by the

on-chip resistive voltage divider, as shown in Figure 9. The

parallel combination of R₁|| R₂and R₃|| R₄sets the input

impedance of the clock inputs (CLK, CLK) to approximately

2.7kΩ single-ended, or 5.4kΩ differentially. The associated

ground-referenced input capacitance is approximately 5pF

for each input. If a logic voltage other than the nominal +1.6V

is desired, the clock inputs can be externally driven to

establish an alternate threshold voltage.

To take full advantage of the excellent distortion performance

of the ADS808, it is recommended to drive the clock inputs

differentially. A low-level, differential clock improves the digi-

tal feedthrough immunity and minimizes the effect of modu-

lation between the signal and the clock. Figure 11 illustrates

a simple method of converting a square wave clock from

single-ended to differential using a RF transformer. Small

surface-mount transformers are readily available from sev-

eral manufacturers (e.g.: model ADT1-1 by Mini-Circuits). A

capacitor in series with the primary side may be inserted to

block any DC voltage present in the signal. Since the clock

inputs are self-biased, the secondary side connects directly

to the two clock inputs of the converter.

+5V

ADS808

R₁

R₃

8.5kΩ

CLK

0.1µF

1:1

Square Wave

Clock Source

CLK

R₂

4kΩ

R₄

4kΩ

ADS808

FIGURE 11. Connecting a Ground Referenced Square Wave

Clock Source to the ADS808 Using a RF Trans-

former.

FIGURE 9. The Differential Clock Inputs are Internally Biased.

The ADS808 can be interfaced to standard TTL or CMOS

logic and accepts 3V or 5V compliant logic levels. In this case,

the clock signal should be applied to the CLK input, while the

complementary clock input (CLK) should be bypassed to

ground by a low-inductance ceramic chip capacitor, as shown

in Figure 10. Depending on the quality of the signal, inserting

a series damping resistor may be beneficial to reduce ringing.

When digitizing at high sampling rates (f_S> 50MHz), the clock

should have a 50% duty cycle (t_H= t_L) to maintain a good

distortion performance.

The clock inputs of the ADS808 can be connected in a

number of ways. However, the best performance is obtained

when the clock input pins are driven differentially. When

operating in this mode, the clock inputs accommodate signal

swings ranging from 2.5Vp-p down to 0.5Vp-p, differentially.

This allows direct interfacing of clock sources, such as

voltage-controlled crystal oscillators (VCXO) to the ADS808.

The advantage here is the elimination of external logic

usually necessary to convert the clock signal into a suitable

logic (TTL or CMOS) signal, that otherwise would create an

additional source of jitter. In any case, a very low-jitter clock

is fundamental to preserving the excellent AC performance

of the ADS808. The converter itself is specified for a very low

0.25ps (rms) jitter, characterizing the outstanding capability

of the internal clock and track-and-hold circuitry. Generally,

as the input frequency increases, the clock jitter becomes

more dominant in maintaining a good SNR. This is particu-

larly critical in IF sampling applications where the sampling

frequency is lower than the input frequency (or

CLK

TTL/CMOS

Clock Source

(3V/5V)

ADS808

CLK

47nF

FIGURE 10. Single-Ended TTL/CMOS Clock Source.

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undersampling). The following equation can be used to

calculate the achievable SNR for a given input frequency and

clock jitter (t_JAin ps rms):

SINGLE-ENDED

INPUT (IN)

(IN Biased to V_CM

BINARY TWO’S

COMPLEMENT

(BTC)

STRAIGHT OFFSET

BINARY (SOB)

)

+FS – 1LSB

1111 1111 1111

0111 1111 1111

(

IN = CMV + FSR/2)

SNR = 20log₁₀

2πf t

+1/2 FS

1100 0000 0000

1000 0000 0000

0100 0000 0000

0000 0000 0000

(

)

IN JA

Bipolar Zero

(IN = CMV)

Depending on the nature of the clock source’s output imped-

ance, an impedance matching might become necessary. For

this, a termination resistor (R_T) may be installed, as shown in

Figure 12. To calculate the correct value for this resistor,

consider the impedance ratio of the selected transformer and

the differential clock input impedance of the ADS808, which

is approximately 5.4kΩ.

–1/2 FS

0100 0000 0000

0000 0000 0000

1100 0000 0000

1000 0000 0000

–FS

(IN = CMV – FSR/2)

TABLE II. Coding Table for Single-Ended Input Configuration

with IN Tied to the Common-Mode Voltage (CMV).

STRAIGHT OFFSET

BINARY

BINARY TWO’S

COMPLEMENT

(BTC)

It is not recommended to employ any type of differential TTL

logic that suffers from mismatch in delay time and slew-rate

leading to performance degradation. Alternatively, a low jitter

ECL or PECL clock may be AC-coupled directly to the clock

inputs using small (0.1µF) capacitors.

DIFFERENTIAL INPUT

(SOB)

+FS – 1LSB

(IN = +3V, IN = +2V)

1111 1111 1111

0111 1111 1111

+1/2 FS

1100 0000 0000

1000 0000 0000

0100 0000 0000

0000 0000 0000

Bipolar Zero

(IN = IN = CMV)

–1/2 FS

0100 0000 0000

0000 0000 0000

1100 0000 0000

1000 0000 0000

–FS

1:1

(IN = +2V, IN = +3V)

CLK

RF Sine

Source

ADS808

R_T

TABLE III. Coding Table for Differential Input Configuration

and 2Vp-p Full-Scale Input Range.

Output Enable (

)

The digital outputs of the ADS808 can be set to high

impedance (tri-state), exercising the output enable pin ( ).

FIGURE 12. Applying a Sinusoidal Clock to the ADS808.

MINIMUM SAMPLING RATE

For normal operation, this pin must be at a logic LOW

potential, while a logic HIGH voltage disables the outputs.

Even though this function effects the output driver stage, the

The pipeline architecture of the ADS808 uses the switched

capacitor technique in its internal track-and-hold stages. With

each clock cycle charges representing the captured signal

level are moved within the ADC pipeline core. The high

sampling speed necessitates the use of very small capacitor

values. In order to hold the droop errors LOW, the capacitors

require a minimum “refresh rate”. Therefore, the sampling

clock on the ADS808 should not drop below the specified

minimum of 1MHz.

threshold voltages for the

pin do not depend on the

output driver supply (VDRV), but are fixed (see the Digital

Inputs of the Electrical Characteristics table). Operating the

function dynamically (i.e., high speed multiplexing) should

be avoided, as it will corrupt the conversion process.

Power Down (PD)

A power-down of the ADS808 is initiated by taking the PD pin

HIGH. This shuts down portions within the converter and

reduces the power dissipation to about 20mW. The remain-

ing active blocks include the internal reference, ensuring a

fast reactivation time. During power-down, data in the con-

verter pipeline will be lost and new valid data will be subject

to the specified pipeline delay. In case the PD pin is not used,

it should be tied to ground or a logic LOW level.

DATA OUTPUT FORMAT (BTC)

The ADS808 makes two data output formats available, either

the “Straight Offset Binary” code (SOB) or the “Binary Two’s

Complement” code (BTC). The selection of the output coding

is controlled through the BTC pin. Applying a logic HIGH will

enable the BTC coding, while a logic LOW will enable the

SOB code. The BTC output format is widely used to interface

to microprocessors and such. The two code structures are

identical with the exception that the MSB is inverted for the

BTC format, as shown in Tables II and III.

Over-Range Indicator (OVR)

If the analog input voltage exceeds the full-scale range set by

the reference voltages, an over-range condition exists. The

ADS808 incorporates a function, that monitors the input volt-

age and detects any such out-of-range condition. The current

state can be read at the over-range indicator pin (OVR).

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This output is LOW when the input voltage is within the

defined input range. It will change to HIGH if the applied

signal exceeds the full-scale range. It should be noted that the

OVR output is updated along with the data output, corre-

sponding to the particular sampled analog input voltage.

Therefore, the OVR data is subject to the same pipeline delay

as the digital data (5 clock cycles).

LAYOUT AND DECOUPLING CONSIDERATIONS

Proper grounding and bypassing, short lead length, and the

use of ground planes are particularly important for high-

frequency designs. Achieving optimum performance with a

fast sampling converter, like the ADS808, requires careful

attention to the pc-board layout to minimize the effect of

board parasitics and optimize component placement.

Output Loading

A multilayer board usually ensures best results and allows

convenient component placement.

It is recommended to keep the capacitive loading on the data

output lines as low as possible, preferably below 15pF.

Higher capacitive loading will cause larger dynamic currents

to flow as the digital outputs are changing. For example, with

a typical output slew-rate of 0.8V/ns and a total capacitive

loading of 10pF (including 4pF output capacitance, 5pF input

capacitance of external logic buffer, and 1pF pc-board

parasitics), a bit transition can cause a dynamic current of

10pF • 0.8V/1ns = 8mA. Those high current surges can feed

back to the analog portion of the ADS808 and adversely

affect the performance. External buffers, or latches, close to

the converter’s output pins may be used to minimize the

capacitive loading. They also provide the added benefit of

isolating the ADS808 from any digital activities on the bus

from coupling back high-frequency noise.

The ADS808 should be treated as an analog component with

the +V_Spins connected to clean analog supplies. This will

ensure the most consistent results, since digital supplies

often carry a high level of switching noise that could couple

into the converter and degrade the performance. As men-

tioned previously, the driver supply pins (VDRV) should also

be connected to a low-noise supply. Supplies of adjacent

digital circuits may carry substantial current transients. The

supply voltage must be thoroughly filtered before connecting

to the VDRV supply of the converter. All ground connections

on the ADS808 are internally bonded to the metal flag

(bottom of package) that forms a large ground plane. All

ground pins should directly connect to an analog ground

plane that covers the pc-board area under the converter.

Due to its high sampling frequency, the ADS808 generates

high-frequency current transients and noise (clock

feedthrough) that are fed back into the supply and reference

lines. If not sufficiently bypassed, this will add noise to the

conversion process. Figure 13 shows the recommended

supply decoupling scheme for the ADS808. All +V_Spins may

be connected together and bypassed with a combination of

10nF to 0.1µF ceramic chip capacitors (0805, low ESR) and

a 10µF tantalum tank capacitor. A similar approach may be

used on the driver supply pins, VDRV. In order to minimize

the lead and trace inductance, the capacitors should be

located as close to the supply pins as possible. Where

double-sided component mounting is allowed, they are best

placed directly under the package. In addition, larger bipolar

decoupling capacitors (2.2µF to 10µF), effective at lower

frequencies, should also be used on the main supply pins.

They can be placed on the pc-board in proximity (< 0.5") of

the ADC.

POWER SUPPLIES

When defining the power supplies for the ADS808, is it highly

recommended to consider linear supplies instead of switch-

ing types. Even with good filtering, switching supplies may

radiate noise that could interfere with any high-frequency

input signal and cause unwanted modulation products. At its

full conversion rate of 70MHz, the ADS808 requires typically

170mA of supply current on the +5V supply (+V_S). Note that

this supply voltage should stay within a 5% tolerance. The

ADS808 does not require separate analog and digital sup-

plies, but only one single +5V supply to be connected to all

its +V_Spins. This is with the exception of the output driver

supply pin, denoted VDRV (see the following section).

Digital Output Driver Supply (VDRV)

A dedicated supply pin, denoted VDRV, provides power to

the logic output drivers of the ADS808, and may be operated

with a supply voltage in the range of +3.0V to +5.0V. This can

simplify interfacing to various logic families, in particular low-

voltage CMOS. It is recommended to operate the ADS808

with a +3.0V supply voltage on VDRV. This will lower the

power dissipation in the output stages due to the lower output

swing and reduce current glitches on the supply line that may

affect the AC performance of the converter. The analog

supply (+V_S) and driver supply (VDRV) may be tied together,

with a ferrite bead or inductor between the supply pins. Each

of the these supply pins must be bypassed separately with at

least one 0.1µF ceramic chip capacitor, forming a pi-filter.

The recommended operation for the ADS808 is +5V for the

+V_Spins and +3.0V on the output driver pin (VDRV).

ADS808

GND

35, 36, 37, 38

42, 43, 45

GND

9, 27

+V_S

2, 47, 48

+V_S

3, 4

VDRV

5, 8, 31

0.01µF

0.1µF

+5V

+3V, +5V

FIGURE 13. Recommended Supply Decoupling Scheme.

ADS808

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If the analog inputs to the ADS808 are driven differentially, it

is especially important to optimize towards a highly symmetri-

cal layout. Small trace length differences may create phase

shifts compromising a good distortion performance. For this

reason, the use of two single op amps (rather than one dual

amplifier) enables a more symmetrical layout and a better

match of parasitic capacitances. The pin orientation of the

ADS808 package follows a “flow-through” design with the

analog inputs located on one side of the package while the

digital outputs are located on the opposite side of the quad-

flat package. This provides a good physical isolation be-

tween the analog and digital connections. While designing

the layout, it is important to keep the analog signal traces

separated from any digital lines to prevent noise coupling

onto the analog portion.

be buffered (with a 74LCX571, for example). Dynamic perfor-

mance may also be improved with the insertion of series

resistors at each data output line. This sets a defined time

constant and reduces the slew rate that would otherwise

flow, due to the fast edge rate. The resistor value may be

chosen to result in a time constant of 15% to 25% of the used

data rate.

LAYOUT OF PCB WITH

PowerPAD THERMALLY

ENHANCED PACKAGES

The ADS808 is housed in a 48-lead PowerPAD thermally

enhanced package. To make optimum use of the thermal

efficiencies designed into the PowerPAD package, the PCB

must be designed with this technology in mind. Please refer

to SLMA004 PowerPAD brief “PowerPAD Made Easy” on

our web site at www.ti.com, which addresses the specific

considerations required when integrating a PowerPAD pack-

age into the PCB design. For more detailed information,

including thermal modeling and repair procedures, please

see SLMA002 technical brief “PowerPAD Thermally En-

hanced Package” (www.ti.com).

Also, try to match trace length for the differential clock signal

(if used) to avoid mismatches in propagation delays. Single-

ended clock lines must be short and should not cross any

other signal traces.

Short-circuit traces on the digital outputs will minimize ca-

pacitive loading. Trace length should be kept short to the

receiving gate (< 2") with only one CMOS gate connected to

one digital output. If possible, the digital data outputs should

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PACKAGE OPTION ADDENDUM

www.ti.com

21-May-2010

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

ADS808Y/250

ACTIVE

HTQFP

PHP

250

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

ADS808Y/250G4

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Dec-2011

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADS808Y/250

HTQFP

PHP

250

177.8

16.4

9.6

1.5

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Dec-2011

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTQFP PHP 48

SPQ

Length (mm) Width (mm) Height (mm)

210.0 185.0 35.0

ADS808Y/250

250

Pack Materials-Page 2

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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Audio

Applications

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

www.ti.com/industrial

www.ti.com/medical

www.ti.com/security

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

Medical

Security

Logic

Space, Avionics and Defense www.ti.com/space-avionics-defense

Transportation and Automotive www.ti.com/automotive

Power Mgmt

Microcontrollers

RFID

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Video and Imaging

www.ti.com/video

OMAP Mobile Processors www.ti.com/omap

Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community Home Page

e2e.ti.com

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