ADS830E/2K5 [TI]
8 位、60MSPS 模数转换器 (ADC) | DBQ | 20 | -40 to 85;
| 型号： | ADS830E/2K5 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8 位、60MSPS 模数转换器 (ADC) | DBQ | 20 | -40 to 85 转换器 模数转换器 |
| 文件： | 总17页 (文件大小：882K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS830
ADS830
¤
SBAS086A – APRIL 2001
TM
8-Bit, 60MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
● HIGH SNR: 49.5dB
DESCRIPTION
The ADS830 is a pipeline, CMOS Analog-to-Digital (A/D)
converter that operates from a single +5V power supply.
This converter provides excellent performance with a single-
ended input and can be operated with a differential input
for added spurious performance. This high performance
converter includes an 8-bit quantizer, high bandwidth
track/hold, and a high accuracy internal reference. It also
allows for the user to disable the internal reference and
utilize external references. This external reference option
provides excellent gain and offset matching when used in
multi-channel applications or in applications where DC full
scale range adjustment is required.
● INTERNAL/EXTERNAL REFERENCE
OPTION
● SINGLE-ENDED OR
DIFFERENTIAL ANALOG INPUT
● PROGRAMMABLE INPUT RANGE:
1Vp-p /2Vp-p
● LOW POWER: 170mW
● LOW DNL: 0.2LSB
● SINGLE +5V SUPPLY OPERATION
● SSOP-20 PACKAGE
The ADS830 employs digital error correction techniques to
provide excellent differential linearity for demanding im-
aging applications. Its low distortion and high SNR give
the extra margin needed for medical imaging, communica-
tions, video, and test instrumentation.
APPLICATIONS
● MEDICAL IMAGING
● VIDEO DIGITIZING
● COMMUNICATIONS
● DISK-DRIVE CONTROL
The ADS830 is specified at a maximum sampling fre-
quency of 60MHz and a single-ended input range of 1.5V
to 3.5V. The ADS830 is available in a SSOP-20 package
and is pin-for-pin compatible with the 8-bit, 80MHz ADS831.
+VS
CLK
VDRV
ADS830
Timing
Circuitry
VIN
IN
D0
8-Bit
Pipelined
A/D Core
Error
Correction
Logic
3-State
Outputs
•
•
•
T/H
IN
(Opt)
D7
Internal
Reference
Int/Ext
Optional External
Reference
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2001, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
+VS ....................................................................................................... +6V
Analog Input ............................................................. –0.3V to (+VS + 0.3V)
Logic Input ............................................................... –0.3V to (+VS + 0.3V)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +150°C
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
DEMO BOARD ORDERING INFORMATION
PRODUCT
DEMO BOARD
ADS830
DEM-ADS830E
PACKAGE/ORDERING INFORMATION
PACKAGE
SPECIFIED
DRAWING
NUMBER
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
PRODUCT
PACKAGE
ADS830E
"
SSOP-20 (QSOP)
"
349
"
–40°C to +85°C
ADS830E
"
ADS830E
ADS830E/1K
Rails
Tape and Reel
"
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of “ADS830E/1K” will get a single 1000-piece Tape and Reel.
ELECTRICAL CHARACTERISTICS
At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 60MHz, and external reference, unless otherwise noted.
ADS830E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
8 Guaranteed
Bits
SPECIFIED TEMPERATURE RANGE
Ambient Air
–40 to +85
°C
ANALOG INPUT
Standard Single-Ended Input Range
Optional Single-Ended Input Range
Common-Mode Voltage
2Vp-p
1Vp-p
1.5
2
3.5
3
V
V
V
2.5
Optional Differential Input Range
Analog Input Bias Current
Input Impedance
2Vp-p
2
3
V
µA
MΩ || pF
MHz
1
1.25 || 5
300
Track-Mode Input Bandwidth
–3dBFS
CONVERSION CHARACTERISTICS
Sample Rate
Data Latency
10k
60M
Samples/s
Clk Cyc
4
DYNAMIC CHARACTERISTICS
Differential Linearity Error (Largest Code Error)
f = 1MHz
f = 10MHz
No Missing Codes
Integral Nonlinearity Error, f = 1MHz
Spurious Free Dynamic Range(1)
f = 1MHz (–1dB input)
f = 10MHz (–1dB input)
Two-Tone Intermodulation Distortion(3)
f = 9.5MHz and 9.9MHz (–7dB each tone)
Signal-to-Noise Ratio (SNR)
f = 1MHz
f = 10MHz
Signal-to-(Noise + Distortion) (SINAD)
f = 1MHz
f = 10MHz
Effective Number of Bits(4), f = 1MHz
Differential Gain Error
Differential Phase Error
Output Noise
Aperture Delay Time
±0.1
±0.2
Guaranteed
±0.3
±1.0
±1.5
LSB
LSB
LSBs
67
65
dBFS(2)
dBFS
54
–60
dBc
Referred to Full Scale
Referred to Full Scale
49.5
49.5
dB
dB
47
45
48
48
7.7
0.2
0.2
0.2
3
dB
dB
Bits
NTSC, PAL
NTSC, PAL
Input Tied to Common-Mode
%
degrees
LSBs rms
ns
Aperture Jitter
Overvoltage Recovery Time
Full-Scale Step Acquisition Time
1.2
2
2.5
ps rms
ns
ns
ADS830
2
SBAS086A
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 60MHz, and external reference, unless otherwise noted.
ADS830E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS
Logic Family
CMOS/TTL Compatible
Convert Command
Start Conversion
Rising Edge of Convert Clock
High Level Input Current(5) (VIN = 5V)
Low Level Input Current (VIN = 0V)
High Level Input Voltage
Low Level Input Voltage
Input Capacitance
100
10
µA
µA
V
+2.4
+1.0
V
5
pF
DIGITAL OUTPUTS
Logic Family
Logic Coding
CMOS/TTL Compatible
Straight Offset Binary
Low Output Voltage (IOL = 50µA)
Low Output Voltage, (IOL = 1.6mA)
High Output Voltage, (IOH = 50µA)
High Output Voltage, (IOH = 0.5mA)
Low Output Voltage, (IOL = 50µA)
High Output Voltage, (IOH = 50µA)
Output Capacitance
VDRV = 5V
VDRV = 3V
+0.1
+0.2
V
V
V
V
V
+4.9
+4.8
+0.1
+2.8
V
pF
5
ACCURACY (External Reference, 2Vp-p, Unless Otherwise Noted)
Zero Error (Referred to –FS)
Zero Error Drift (Referred to –FS)
Gain Error(6)
fS = 2.5MHz
at 25°C
–2.5
–2.5
±0.25
±53
±0.3
±75
58
+2.5
+2.5
%FS
ppm/°C
%FS
ppm/°C
dB
at 25°C
Gain Error Drift(6)
Power Supply Rejection of Gain
∆ VS = ±5%
Internal REFT Tolerance
Internal REFB Tolerance
Deviation from Ideal 3.0V
Deviation from Ideal 2.0V
±10
±10
±100
±100
mV
mV
External REFT Voltage Range
External REFB Voltage Range
Reference Input Resistance
REFB + 0.8
1.25
3.0
2.0
800
VS – 1.25
REFT – 0.8
V
V
kΩ
REFT to REFB
POWER SUPPLY REQUIREMENTS
Supply Voltage: +VS
Supply Current: +IS
Power Dissipation: VDRV = 5V
VDRV = 3V
Operating
Operating
External Reference
External Reference
Internal Reference
Internal Reference
+4.75
+5.0
37
185
170
215
200
+5.25
45
225
V
mA
mW
mW
mW
mW
VDRV = 5V
VDRV = 3V
Thermal Resistance, θJA
SSOP-20
115
°C/W
NOTES: (1) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full Scale. (3) Two-tone
intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental
envelope. (4) Effective number of bits (ENOB) is defined by (SINAD – 1.76) /6.02. (5) A 50kΩ pull-down resistor is inserted internally. (6) Excludes internal
reference.
ADS830
SBAS086A
3
PIN CONFIGURATION
PIN DESCRIPTIONS
PIN
DESIGNATOR DESCRIPTION
Top View
SSOP
1
2
GND
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
CLK
Ground
Data Bit 1 (D7) (MSB)
Data Bit 2 (D6)
3
GND
Bit 1 (MSB)
Bit 2
1
2
3
4
5
6
7
8
9
20 VDRV
19 +VS
4
Data Bit 3 (D5)
5
Data Bit 4 (D4)
6
Data Bit 5 (D3)
18 GND
17 IN
7
Data Bit 6 (D2)
8
Data Bit 7 (D1)
Bit 3
9
Data Bit 8 (D0) (LSB)
Convert Clock
Bit 4
16 IN
10
11
12
13
14
15
16
17
18
19
20
ADS830
RSEL
INT/EXT
REFB
REFT
CM
Input Range Select: HI = 2V; LO = 1V
Reference Select: HI = External; LO = Internal
Bottom Reference
Top Reference
Bit 5
15 CM
Bit 6
14 REFT
13 REFB
12 INT/EXT
11 RSEL
Bit 7
Common-Mode Voltage Output
Complementary Input
Analog Input
IN
Bit 8 (LSB)
IN
CLK 10
GND
+VS
Ground
+5V Supply
VDRV
Output Logic Drive Supply Voltage
TIMING DIAGRAM
N+2
N+1
N+4
N+3
tL
Analog In
N+7
N+5
N
N+6
tH
tD
tCONV
Clock
4 Clock Cycles
N–3 N–2
t2
Data Out
N–4
N–1
N
N+1
N+2
N+3
Data Invalid
t1
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tCONV
tL
tH
tD
t1
Convert Clock Period
Clock Pulse Low
Clock Pulse High
Aperture Delay
16.6
7.3
7.3
100µs
ns
ns
ns
ns
ns
ns
8.3
8.3
3
Data Hold Time, CL = 0pF
New Data Delay Time, CL = 15pF max
3.9
t2
5.9
12
ADS830
4
SBAS086A
TYPICAL CHARACTERISTICS
At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 60MHz, and external reference, unless otherwise noted.
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
7.5
15
22.5
30
0
0
0
7.5
15
22.5
30
30
30
Frequency (MHz)
Frequency (MHz)
SPECTRAL PERFORMANCE
(Single-Ended, 1Vp-p)
SPECTRAL PERFORMANCE
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
7.5
15
22.5
0
7.5
15
22.5
30
Frequency (MHz)
Frequency (MHz)
TWO-TONE INTERMODULATION DISTORTION
DIFFERENTIAL LINEARITY ERROR
fIN = 10MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0.2
0.1
f1 = 9.5MHz at –7dBFS
0
–0.1
–0.2
7.5
15
Frequency (MHz)
22.5
0
64
128
192
256
Output Code
ADS830
SBAS086A
5
TYPICAL CHARACTERISTICS (Cont.)
At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 60MHz, and external reference, unless otherwise noted.
INTEGRAL LINEARITY ERROR
fIN = 1MHz
DIFFERENTIAL LINEARITY ERROR
fIN = 20MHz
1.0
0.5
0.2
0.1
0
0
–0.5
–1.0
–0.1
–0.2
0
64
128
192
256
0
64
128
192
256
Output Code
Output Code
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
POWER DISSIPATION vs TEMPERATURE
VDRV = +5V
70
60
50
40
220
210
200
190
180
170
160
SFDR
Internal Reference
SNR
External Reference
0.1
1
10
Frequency (MHz)
100
–50
–25
0
25
50
75
100
Temperature (°C)
OUTPUT NOISE HISTOGRAM (DC Input)
800k
600k
400k
200k
0
N–2
N–1
N
N+1
N+2
Output Code
ADS830
6
SBAS086A
individual application requirements and system structure.
For example, communications applications often process a
band of frequencies that does not include DC, whereas in
imaging applications, the previously restored DC level must
be maintained correctly up to the A/D converter. Features on
the ADS830 like the input range select (RSEL pin) or the
option for an external reference provide the needed flexibil-
ity to accommodate a wide range of applications. In any
case, the ADS830 should be configured such that the appli-
cation objectives are met while observing the headroom
requirements of the driving amplifier in order to yield the
best overall performance.
APPLICATION INFORMATION
THEORY OF OPERATION
The ADS830 is a high-speed CMOS A/D converter which
employs a pipelined converter architecture consisting of 6
internal stages. Each stage feeds its data into the digital error
correction logic ensuring excellent differential linearity and
no missing codes at the 8-bit level. The output data becomes
valid on the rising clock edge (see Timing Diagram). The
pipeline architecture results in a data latency of 4 clock
cycles.
The analog input of the ADS830 is a differential track and
hold, see Figure 1. The differential topology along with
tightly matched capacitors produce a high level of ac perfor-
mance while sampling at very high rates.
INPUT CONFIGURATIONS
AC-Coupled, Single-Supply Interface
Figure 2 shows the typical circuit for an ac-coupled analog
input configuration of the ADS830 where all components
are powered from a single +5V supply.
The ADS830 allows its analog inputs to be driven either
single-ended or differentially. The typical configuration for
the ADS830 is for the single-ended mode in which the input
track and hold performs a single-ended to differential con-
version of the analog input signal.
With the RSEL pin connected HIGH, the full-scale input
range is set to 2Vp-p. In this configuration, the top and
bottom references (REFT, REFB) provide an output voltage
of +3.0V and +2.0V, respectively. Two resistors ( 2 x 1kΩ)
are used to create a common-mode voltage (VCM) of ap-
proximately +2.5V to bias the inputs of the driving ampli-
fier. Using the OPA681 on a single +5V supply, its ideal
common-mode point is at +2.5V. This coincides with the
recommended common-mode input level for the ADS830
thus, obviating the need for a coupling capacitor between the
amplifier and the converter. Even though the OPA681 has an
ac gain of +2, the dc gain is only +1 due to the blocking
capacitor at resistor RG.
Both inputs (IN, IN) require external biasing using a com-
mon-mode voltage that is typically at the mid-supply level
(+VS/2).
The following application discussion focuses on the single-
ended configuration. Typically, its implementation is easier
to achieve and the rated specifications for the ADS830 are
characterized using the single-ended mode of operation.
DRIVING THE ANALOG INPUT
The ADS830 achieves excellent ac performance either in the
single-ended or differential mode of operation. The selection
for the optimum interface configuration will depend on the
The addition of a small series resistor (RS) between the
output of the op amp and the input of the ADS830 will be
beneficial in almost all interface configurations. This will
de-couple the op amp’s output from the capacitive load and
avoid gain peaking, which can result in increased noise. For
best spurious and distortion performance, the resistor value
should be kept below 75Ω. The series resistor in combina-
tion with the 47pF capacitor establishes a passive low-pass
filter, limiting the bandwidth for the wideband noise thus
help improving the SNR performance.
Op Amp
VCM
Bias
φ1
φ1
CH
φ2
φ2
CI
CI
IN
IN
AC-Coupled, Dual Supply Interface
OUT
OUT
φ1
φ1
φ2
φ1
The circuit provided in Figure 3 shows typical connections
for the analog input in case the selected amplifier operates
on dual supplies. This might be necessary to take full
advantage of very low distortion operational amplifiers,
such as the OPA642. The advantage is that the driving
amplifier can be operated with a ground referenced bipolar
signal swing. This will keep the distortion performance at its
lowest since the signal range stays within the linear region
of the op amp and sufficient headroom to the supply rails can
be maintained. By capacitively coupling the single-ended
signal to the input of the ADS830, its common-mode re-
quirements can easily be satisfied with two resistors con-
nected between the top and bottom reference.
CH
φ1
φ1
Input Clock (50%)
Op Amp
Bias
VCM
Internal Non-overlapping Clock
φ1 φ2 φ1
FIGURE 1. Simplified Circuit of Input Track and Hold with
Timing Diagram.
ADS830
SBAS086A
7
1kΩ
+5V
+VS
VCM = +2.5VDC
1kΩ
+5V
REFB
+2.0V
REFT
+3.0V
RSEL
0.1µF
RS
39Ω
VIN
IN
OPA681
47pF
+VIN
ADS830
0V
RF
402Ω
–VIN
CM
IN
RG
402Ω
0.1µF
INT/EXT
GND
0.1µF
FIGURE 2. AC-Coupled Input Configuration for a 2Vp-p Full-Scale Range and a Common-Mode Voltage, VCM, at +2.5V
Derived from the Internal Top (REFT) and Bottom Reference (REFB). The OPA680 can be used in place of the
OPA681 if a voltage feedback amplifier is preferred.
+5V
1kΩ
+5V
REFT
+3.0V
RSEL
+VS
RS
24.9Ω
0.1µF
VIN
IN
OPA642
47pF
–5V
ADS830
RF
402Ω
1kΩ
CM
IN
0.1µF
RG
402Ω
REFB
+2.0V INT/EXT
GND
FIGURE 3. AC-Coupling the Dual Supply Amplifier OPA642 to the ADS830 for a 2Vp-p Full Scale Input Range.
For applications requiring the driving amplifier to provide a
signal amplification, with a gain ≥ 5, consider using decom-
pensated voltage feedback op amps, such as the OPA643, or
current feedback op amps OPA681 and OPA658.
ately biased using the +2.5V common-mode voltage avail-
able at the CM pin. One-half of the amplifier (OPA2681)
buffers the REFB pin and drives the voltage divider R1, R2.
Because of the op amp’s noise gain of +2V/V, assuming
RF = RIN , the common-mode voltage (VCM) has to be re-
scaled to +1.25V, resulting in the correct DC level of +2.5V
for the signal input (IN). Any DC voltage differences be-
tween the IN and IN inputs of the ADS830 effectively
produce an offset, which can be corrected for by adjusting
the resistor values of the divider, R1 and R2. The selection
criteria for a suitable op amp should include the supply
voltage, input bias current, output voltage swing, distortion
and noise specification. Note that in this example the overall
signal phase is inverted. To re-establish the original signal
polarity, it is always possible to interchange the IN and IN
connections.
DC-Coupled with Level Shift
Several applications may require that the bandwidth of the
signal path includes DC, in which case the signal has to be
DC-coupled to the A/D converter. In order to accomplish
this, the interface circuit has to provide a DC level shift to
the analog input signal. The circuit shown in Figure 4
employs a dual op amp, A1, to drive the input of the
ADS830 and level shift the signal to be compatible with
the selected input range. With the RSEL pin tied to the
supply and the INT/EXT pin to ground, the ADS830 is
configured for a 2Vp-p input range and uses the internal
references. The complementary input (IN) may be appropri-
ADS830
8
SBAS086A
+5V
+VS
RF
499Ω
RIN
499Ω
RSEL
RS
VIN
39Ω
1/2
IN
OPA2681
2Vp-p
47pF
ADS830
NOTE: RF = RIN, G = –1
CM (+2.5V)
IN
0.1µF
REFB
REFT
+5V
(+2.0V)
(+3.0V)
INT/EXT
50Ω
R2
301Ω
0.1µF
1/2
VCM = +1.25V
OPA2681
0.1µF
R1
499Ω
RF
1kΩ
FIGURE 4. DC-Coupled Interface Circuit with Dual Current-Feedback Amplifier OPA2681. The OPA2680 can be used in place
of the OPA2681 if a voltage feedback amplifier is preferred.
SINGLE-ENDED-TO-DIFFERENTIAL CONFIGURATION
(Transformer Coupled)
cuit. The component values of the R-C lowpass may be
optimized depending on the desired roll-off frequency. The
resistor across the secondary side (RT) should be calculated
using the equation RT = n2 x RG to match the source
impedance (RG) for good power transfer and VSWR.
If the application requires a signal conversion from a single-
ended source to feed the ADS830 differentially, a RF trans-
former might be a good solution. The selected transformer
must have a center tap in order to apply the common-mode
DC voltage necessary to bias the converter inputs.
AC grounding the center tap will generate the differential
signal swing across the secondary winding. Consider a step-
up transformer to take advantage of a signal amplification
without the introduction of another noise source. Further-
more, the reduced signal swing from the source may lead to
an improved distortion performance.
REFERENCE OPERATION
Figure 6 depicts the simplified model of the internal refer-
ence circuit. The internal blocks are the bandgap voltage
reference, the drivers for the top and bottom reference, and
RSEL
+VS
INT/EXT
The differential input configuration may provide a notice-
able advantage of achieving good SFDR performance over
a wide range of input frequencies. In this mode both inputs
of the ADS830 see closely matched impedances, and the
differential signal swing is reduced to half of the swing
required for single-ended drive. Figure 5 shows the sche-
matic for the suggested transformer coupled interface cir-
ADS830
50kΩ
50kΩ
Bandgap Reference and Logic
VREF
+1
+1
RG
0.1µF
22Ω
1:n
VIN
IN
IN
47pF
400Ω
400Ω
RT
ADS830
22Ω
REFT
CM
REFB
CM RSEL INT/EXT
47pF
+5V
+
10µF
0.1µF
Bypass Capacitors: 0.1µF || 2.2µF each
FIGURE 6. Equivalent Reference Circuit with Recommended
Reference Bypassing.
FIGURE 5. Transformer Coupled Input.
ADS830
SBAS086A
9
the resistive reference ladder. The bandgap reference circuit
includes logic functions that allow to set the analog input
swing of the ADS830 to either a 1Vp-p or 2Vp-p full-scale
range simply by tying the RSEL pin to a LOW or HIGH
potential, respectively. While operating the ADS830 in the
external reference mode, the buffer amplifiers for REFT and
REFB are disconnected from the reference ladder.
The common-mode voltage available at the CM pin may be
used as a bias voltage to provide the appropriate offset for
the driving circuitry. However, care must be taken not to
appreciably load this node, which is not buffered and has a
high impedance. An alternative way of generating a com-
mon-mode voltage is given in Figure 7. Here, two external
precision resistors (1% tolerance or better) are located
between the top and bottom reference pins. The common-
mode voltage, CMV, will appear at the midpoint.
As shown, the ADS830 has internal 50kΩ pull-up resistors
at the Range Select pin (RSEL) and Reference Select pin
(INT/EXT). Leaving those pins open configures the ADS830
for a 2Vp-p input range and external reference operation.
Setting the ADS830 up for internal reference mode requires
to bring the INT/EXT pin LOW.
EXTERNAL REFERENCE OPERATION
For even more design flexibility, the internal reference can
be disabled and an external reference voltage be used. The
utilization of an external reference may be considered for
applications requiring higher accuracy, improved tempera-
ture performance, or a wide adjustment range of the
converter’s full-scale range. Especially in multichannel
applications, the use of a common external reference has the
benefit of obtaining better matching of the full-scale range
between converters.
The reference buffers can be utilized to supply up to 1mA
(sink and source) to external circuitry. To ensure proper
operation with any reference configurations, it is necessary
to provide solid bypassing at the reference pins in order to
keep the clock feedthrough to a minimum (Figure 6). All
bypassing capacitors should be located as close to their
respective pins as possible.
The external references can vary as long as the value of the
external top reference REFTEXT stays within the range of
(VS – 1.25V) and (REFB + 0.8V), and the external bottom
reference REFBEXT stays within 1.25V and (REFT – 0.8V),
see Figure 8.
ADS830
REFT
+3.0V
REFB
+2.0V
The full-scale input signal range (FSR) of the ADS830 is
determined by the voltage difference across the reference
pins REFT and REFB (FSR = REFT – REFB), while the
common-mode voltage is defined by CMV = (REFT +
REFB)/2. In order to maintain good ac performance, it is
recommended that the typical common-mode voltage be
kept at +2.5V while setting the external reference voltages.
It is possible, however, to deviate from this common-mode
level without significantly impacting the performance. In
particular, DC-coupled applications may benefit from a
R1
1kΩ
R2
1kΩ
+
+
2.2µF
0.1µF
0.1µF
2.2µF
CMV
+2.5V
FIGURE 7. Alternative Circuit to Generate Common-Mode
Voltage.
+5V
B
A
A - Short for 1Vp-p Input Range
B - Short for 2Vp-p Input Range (Default)
+VS
INT/EXT
RSEL
GND
IN
VIN
ADS830
CMV
IN
REFT
GND
REFB
External Top Reference
REFT = REFB +0.8V to +3.75V
External Bottom Reference
REFB = REFT –0.8V to +1.25V
FIGURE 8. Configuration Example for External Reference Operation.
10
ADS830
SBAS086A
Digital Output Driver (VDRV)
lower CMV as it increases the signal headroom of the
driving amplifier. The internal reference ladder has a nomi-
nal impedance of 800Ω. Depending on the selected refer-
ence voltages, the required drive current will vary accord-
ingly and the external reference circuitry should be designed
to supply the maximum required current.
The ADS830 features a dedicated supply pin for the output
logic drivers, VDRV, which is not internally connected to
the other supply pins. Setting the voltage at VDRV to +5V
or +3V, the ADS830 produces corresponding logic levels
and can directly interface to the selected logic family. The
output stages are designed to supply sufficient current to
drive a variety of logic families. However, it is recom-
mended to use the ADS830 with +3V logic supply. This will
lower the power dissipation in the output stages due to the
lower output swing and reduce current glitches on the supply
line which may affect the ac performance of the converter.
In some applications, it might be advantageous to decouple
the VDRV pin with additional capacitors or a pi-filter.
DIGITAL INPUTS AND OUTPUTS
Clock Input Requirements
Clock jitter is critical to the SNR performance of high speed,
high resolution Analog to Digital Converters. It leads to
aperture jitter (tA) which adds noise to the signal being
converted. The ADS830 samples the input signal on the
rising edge of the CLK input. Therefore, this edge should
have the lowest possible jitter. The jitter noise contribution
to total SNR is given by the following equation. If this value
is near your system requirements, input clock jitter must be
reduced.
GROUNDING AND DECOUPLING
Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for high
frequency designs. Multilayer PC boards are recommended
for best performance since they offer distinct advantages
like minimizing ground impedance, separation of signal
layers by ground layers, etc. The ADS830 should be treated
as an analog component. Whenever possible, the supply pins
should be powered by the analog supply. This will ensure
the most consistent results, since digital supply lines often
carry high levels of noise which otherwise would be coupled
into the converter and degrade the achievable performance.
All ground connections on the ADS830 are internally joined
together, obviating the design of split ground planes. The
ground pins (1, 18) should directly connect to an analog
ground plane which covers the PC board area around the
converter. While designing the layout, it is important to keep
the analog signal traces separated from any digital lines to
prevent noise coupling onto the analog signal path. Because
of its high sampling rate, the ADS830 generates high fre-
quency current transients and noise (clock feedthrough) that
are fed back into the supply and reference lines. This
requires that all supply and reference pins are sufficiently
bypassed. Figure 9 shows the recommended decoupling
scheme for the ADS830. In most cases 0.1µF ceramic chip
capacitors at each pin are adequate to keep the impedance
low over a wide frequency range. Their effectiveness largely
depends on the proximity to the individual supply pin.
Therefore, they should be located as close to the supply pins
as possible. In addition, a larger bipolar capacitor (1µF to
22µF) should be placed on the PC board in proximity of the
converter circuit.
1
Jitter SNR = 20 log
rms signal to rms noise
2πƒIN tA
Where: ƒIN is Input Signal Frequency
tA is rms Clock Jitter
Particularly in udersampling applications, special consider-
ation should be given to clock jitter. The clock input should
be treated as an analog input in order to achieve the highest
level of performance. Any overshoot or undershoot of the
clock signal may cause degradation of the performance.
When digitizing at high sampling rates, the clock should
have a 50% duty cycle (tH = tL), along with fast rise and fall
times of 2ns or less.
Digital Outputs
The output data format of the ADS830 is in positive Straight
Offset Binary code, see Table I. This format can easily
converted into the Two’s Binary Complement code by
inverting the MSB.
SINGLE-ENDED INPUT (2Vp-p)
(IN = CMV)
STRAIGHT OFFSET BINARY
(SOB)
+FS (IN = +3.5V)
+1/2 FS
+1LSB
Bipolar Zero (IN = 2.5V)
–1LSB
–1/2 FS
1111 1111
1100 0000
1000 0001
1000 0000
0111 1111
0100 0000
0000 0000
–FS (IN = +1.5V)
ADS830
TABLE I. Coding Table for the ADS830.
GND
1
+VS
19
GND
18
VDRV
20
It is recommended to keep the capacitive loading on the data
lines as low as possible (≤ 15pF). Higher capacitive loading
will cause larger dynamic currents as the digital outputs are
changing. Those high current surges can feed back to the
analog portion of the ADS830 and affect the performance. If
necessary, external buffers or latches close to the converter’s
output pins may be used to minimize the capacitive loading.
They also provide the added benefit of isolating the ADS830
from any digital noise activities on the bus coupling back
high frequency noise.
0.1µF
0.1µF
10µF
+
+5V
+3/+5V
FIGURE 9. Recommended Bypassing for the Supply Pins.
ADS830
SBAS086A
11
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS830E
ACTIVE
ACTIVE
SSOP
SSOP
DBQ
DBQ
20
20
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
ADS830E
ADS830E
ADS830E/2K5
2500 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS830E/2K5
SSOP
DBQ
20
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SSOP DBQ 20
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
ADS830E/2K5
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
DBQ SSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ADS830E
20
50
505.46
6.76
3810
4
Pack Materials-Page 3
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