ADS8320 [TI]

16-Bit, High-Speed, 2.7V to 5V microPower Sampling ANALOG-TO-DIGITAL CONVERTER; 16位高速2.7V到5V微功耗采样模拟数字转换器


型号：	ADS8320
厂家：	TEXAS INSTRUMENTS
描述：	16-Bit, High-Speed, 2.7V to 5V microPower Sampling ANALOG-TO-DIGITAL CONVERTER 16位高速2.7V到5V微功耗采样模拟数字转换器转换器
文件：	总21页 (文件大小：860K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS8320

SBAS108D – MAY 2000 – REVISED MARCH 2007

16-Bit, High-Speed, 2.7V to 5V microPower Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

DESCRIPTION

ꢀ 100kHz SAMPLING RATE

The ADS8320 is a 16-bit, sampling analog-to-digital (A/D)

converter with ensured specifications over a 2.7V to 5.25V

supply range. It requires very little power even when operat-

ing at the full 100kHz data rate. At lower data rates, the high

speed of the device enables it to spend most of its time in the

power-down mode—the average power dissipation is less

than 100mW at 10kHz data rate.

ꢀ microPOWER:

1.8mW at 100kHz and 2.7V

0.3mW at 10kHz and 2.7V

ꢀ POWER-DOWN: 3µA max

ꢀ MSOP-8 PACKAGE

ꢀ PIN-COMPATIBLE TO ADS7816 AND ADS7822

ꢀ SERIAL (SPI™/SSI) INTERFACE

The ADS8320 also features operation from 2.0V to 5.25V, a

synchronous serial (SPI/SSI compatible) interface, and a

differential input. The reference voltage can be set to any

level within the range of 500mV to V_CC

APPLICATIONS

ꢀ BATTERY-OPERATED SYSTEMS

ꢀ REMOTE DATA ACQUISITION

ꢀ ISOLATED DATA ACQUISITION

Ultra-low power and small size make the ADS8320 ideal

for portable and battery-operated systems. It is also a

perfect fit for remote data acquisition modules, simulta-

neous multi-channel systems, and isolated data acquisi-

tion. The ADS8320 is available in an MSOP-8 package.

ꢀ SIMULTANEOUS SAMPLING,

MULTICHANNEL SYSTEMS

ꢀ INDUSTRIAL CONTROLS

ꢀ ROBOTICS

ꢀ VIBRATION ANALYSIS

Control

SAR

V_REF

D_OUT

+In

CDAC

Serial

Interface

DCLOCK

CS/SHDN

–In

Comparator

S/H Amp

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

www.ti.com

SPECIFICATIONS: +V_CC= +5V

At –40°C to +85°C, V_REF= +5V, –IN = GND, f_SAMPLE= 100kHz, and f_CLK= 24 • f_SAMPLE, unless otherwise specified.

ADS8320E

ADS8320EB

TYP

PARAMETER

RESOLUTION

CONDITIONS

MIN

TYP

MAX

MIN

MAX

UNITS

ꢀ

Bits

ANALOG INPUT

Full-Scale Input Span

Absolute Input Range

+In – (–In)

+In

V_REF

V_CC+ 0.1

+1.0

ꢀ

–0.1

–In

Capacitance

ꢀ

Leakage Current

SYSTEM PERFORMANCE

No Missing Codes

Integral Linearity Error

Offset Error

Bits

±0.008 ±0.018

±0.006

±0.5

ꢀ

±0.012 % of FSR

±1

±3

±2

±1

µV/°C

Offset Temperature Drift

Gain Error

±0.05

±0.024

Gain Temperature Drift

Noise

±0.3

ꢀ

ppm/°C

µVrms

LSB⁽¹⁾

Power-Supply Rejection Ratio

+4.7V < V_CC< 5.25V

SAMPLING DYNAMICS

Conversion Time

ꢀ

Clk Cycles

kHz

Acquisition Time

4.5

ꢀ

Throughput Rate

100

2.4

ꢀ

Clock Frequency Range

0.024

MHz

DYNAMIC CHARACTERISTICS

Total Harmonic Distortion

SINAD

V_IN= 5V_PPat 10kHz

–84

–86

Spurious-Free Dynamic Range

SNR

REFERENCE INPUT

Voltage Range

Resistance

0.5

V_CC

ꢀ

CS = GND, f_SAMPLE= 0Hz

CS = V_CC

ꢀ

GΩ

µA

Current Drain

0.8

0.1

f_SAMPLE= 10kHz

CS = V_CC

DIGITAL INPUT/OUTPUT

Logic Family

Logic Levels:

V_IH

CMOS

ꢀ

I_IH= +5µA

I_IL= +5µA

3.0

–0.3

4.0

V_CC+ 0.3

0.8

ꢀ

V_IL

V_OH

I_OH= –250µA

I_OL= 250µA

V_OL

0.4

ꢀ

Data Format

Straight Binary

ꢀ

POWER-SUPPLY REQUIREMENTS

V_CC

V_CCRange⁽²⁾

Specified Performance

4.75

2.0

5.25

1700

ꢀ

Quiescent Current

900

200

4.5

0.3

ꢀ

µA

f_SAMPLE= 10kHz^{(3, 4)}

CS = V_CC

Power Dissipation

Power-Down

8.5

ꢀ

TEMPERATURE RANGE

Specified Performance

–40

+85

ꢀ

°C

ꢀ Specifications same as ADS8320E.

NOTES: (1) LSB means Least Significant Bit. With V_REFequal to +5.0V, one LSB is 0.076mV.

(2) See Typical Performance Curves for more information.

(3) f_CLK= 2.4MHz, CS = V_CCfor 216 clock cycles out of every 240.

(4) See the Power Dissipation section for more information regarding lower sample rates.

ADS8320

SBAS108D

www.ti.com

SPECIFICATIONS: +V_CC= +2.7V

At –40°C to +85°C, V_REF= 2.5V, –IN = GND, f_SAMPLE= 100kHz, and f_CLK= 24 • f_SAMPLE, unless otherwise specified.

ADS8320E

ADS8320EB

TYP

PARAMETER

RESOLUTION

CONDITIONS

MIN

TYP

MAX

MIN

MAX

UNITS

ꢀ

Bits

ANALOG INPUT

Full-Scale Input Span

Absolute Input Range

+In – (–In)

+In

V_REF

V_CC+ 0.1

+0.5

ꢀ

–0.1

–In

Capacitance

ꢀ

Leakage Current

SYSTEM PERFORMANCE

No Missing Codes

Integral Linearity Error

Offset Error

Bits

±0.008 ±0.018

±0.006

±0.5

ꢀ

±0.012 % of FSR

±1

±3

±2

±1

Offset Temperature Drift

Gain Error

µV/°C

±0.05

±0.024 % of FSR

ppm/°C

Gain Temperature Drift

Noise

±0.3

ꢀ

µVrms

LSB⁽¹⁾

Power-Supply Rejection Ratio

+2.7V < V_CC< +3.3V

SAMPLING DYNAMICS

Conversion Time

ꢀ

Clk Cycles

kHz

Acquisition Time

4.5

ꢀ

Throughput Rate

100

2.4

ꢀ

Clock Frequency Range

0.024

MHz

DYNAMIC CHARACTERISTICS

Total Harmonic Distortion

SINAD

V_IN= 2.7Vp-p at 1kHz

–86

–88

Spurious-Free Dynamic Range

SNR

REFERENCE INPUT

Voltage Range

Resistance

0.5

V_CC

ꢀ

CS = GND, f_SAMPLE= 0Hz

CS = V_CC

ꢀ

GΩ

µA

Current Drain

0.1

ꢀ

CS = V_CC

DIGITAL INPUT/OUTPUT

Logic Family

Logic Levels:

V_IH

CMOS

ꢀ

I_IH= +5µA

I_IL= +5µA

2.0

–0.3

2.1

V_CC+ 0.3

0.8

ꢀ

V_IL

V_OH

I_OH= –250µA

I_OL= 250µA

V_OL

0.4

ꢀ

Data Format

Straight Binary

ꢀ

POWER-SUPPLY REQUIREMENTS

V_CC

V_CCRange⁽³⁾

Specified Performance

See Note 2

2.7

2.0

3.3

5.25

2.7

ꢀ

Quiescent Current

650

100

1.8

0.3

1300

ꢀ

µA

f_SAMPLE= 10kHz^(4,5)

CS = V_CC

Power Dissipation

Power-Down

3.8

ꢀ

TEMPERATURE RANGE

Specified Performance

–40

+85

ꢀ

°C

ꢀ Specifications same as ADS8320E.

NOTES: (1) LSB means Least Significant Bit. With V_REFequal to +2.5V, one LSB is 0.038mV.

(2) The maximum clock rate of the ADS8320 is less than 2.4MHz in this power supply range.

(3) See the Typical Performance Curves for more information.

(4) f_CLK= 2.4MHz, CS = V_CCfor 216 clock cycles out of every 240.

(5) See the Power Dissipation section for more information regarding lower sample rates.

ADS8320

SBAS108D

www.ti.com

PIN CONFIGURATION

ELECTROSTATIC

DISCHARGE SENSITIVITY

Top View

MSOP

Electrostatic discharge can cause damage ranging from

performance degradation to complete device failure. Texas

Instruments recommends that all integrated circuits be handled

and stored using appropriate ESD protection methods.

V_REF

+In

+V_CC

DCLOCK

D_OUT

ADS8320

–In

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet

published specifications.

GND

CS/SHDN

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

PIN ASSIGNMENTS

NAME

DESCRIPTION

V_CC....................................................................................................... +6V

Analog Input .............................................................. –0.3V to (V_CC+ 0.3V)

Logic Input ...............................................................................–0.3V to 6V

Case Temperature ......................................................................... +100°C

Junction Temperature .................................................................... +150°C

Storage Temperature ..................................................................... +125°C

External Reference Voltage .............................................................. +5.5V

Input current to any pin except supply ............................................ ±10mA

V_REF

+In

Reference Input.

Noninverting Input.

–In

Inverting Input. Connect to ground or to remote

ground sense point.

GND

Ground.

CS/SHDN

Chip Select when LOW, Shutdown Mode when

HIGH.

NOTE: (1) Stresses above these ratings may permanently damage the device.

D_OUT

The serial output data word is comprised of 16

bits of data. In operation the data is valid on the

falling edge of DCLOCK. The

second clock pulse after the falling edge of CS

enables the serial output. After one null bit the

data is valid for the next 16 edges.

DCLOCK

+V_CC

Data Clock synchronizes the serial data transfer

and determines conversion speed.

Power Supply.

PACKAGE/ORDERING INFORMATION⁽¹⁾

MAXIMUM

INTEGRAL

LINEARITY

ERROR

MISSING

CODE

ERROR

(LSB)

SPECIFICATION

TEMPERATURE

RANGE

PACKAGE

DESIGNATOR

PACKAGE

MARKING⁽²⁾

ORDERING

NUMBER⁽³⁾

TRANSPORT

MEDIA

PRODUCT

(%)

PACKAGE

ADS8320E

ADS8320EB

0.018

MSOP-8

DGK

–40°C to +85°C

A20

ADS8320E/250

ADS8320E/2K5

ADS8320EB/250

ADS8320EB/2K5

Tape and Reel

0.012

MSOP-8

DGK

–40°C to +85°C

NOTES: (1) For the most current product and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website

at www.ti.com.

(2) Performance Grade information is marked on the reel.

(3) Models with a slash(/) are available only in tape and reel in quantities indicated (for example, /250 indicates 250 units per reel, /2K5 indicates

2500 devices per reel). Ordering 2500 pieces of ”ADS8320E/2K5“ will get a single 2500-piece tape and reel.

ADS8320

SBAS108D

www.ti.com

TYPICAL PERFORMANCE CURVES

At T_A= +25°C, V_CC= +5V, V_REF= +5V, f_SAMPLE= 100kHz, and f_CLK= 24 • f_SAMPLE, unless otherwise specified.

INTEGRAL LINEARITY ERROR vs CODE (+25°C)

DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C)

2 0

1.0

3.0

2.0

0.0

1.0

–1.0

–2.0

–3.0

–4.0

–5.0

–6.0

0.0

–1.0

–2.0

–3.0

0000_H

4000_H

8000_H

C000_H

FFFF_H

100

0000_H

4000_H

8000_H

C000_H

FFFF_H

Hex Code

POWER-DOWN SUPPLY CURRENT

vs TEMPERATURE

SUPPLY CURRENT vs TEMPERATURE

1200

1000

800

600

400

200

600

500

400

300

200

100

2.7V

–50

–25

100

–50

–25

Temperature (°C)

QUIESCENT CURRENT vs V_CC

MAXIMUM SAMPLE RATE vs V_CC

1200

1000

800

1000

100

600

400

200

V_CC(V)

_CC(V)

ADS8320

SBAS108D

www.ti.com

TYPICAL PERFORMANCE CURVES (Cont.)

At T_A= +25°C, V_CC= +2.7V, V_REF= +2.5V, f_SAMPLE= 100kHz, and f_CLK= 24 • f_SAMPLE, unless otherwise specified.

CHANGE IN OFFSET vs TEMPERATURE

CHANGE IN OFFSET vs REFERENCE VOLTAGE

V_CC= 5V

2.7V

−1

−2

−3

–1

–2

–3

−50

−25

100

Temperature (°C)

Reference Voltage (V)

CHANGE IN GAIN vs REFERENCE VOLTAGE

V_CC= 5V

CHANGE IN GAIN vs TEMPERATURE

–2

–4

–6

2.7V

–1

–2

–50

–25

Reference Voltage (V)

Temperature (°C)

FREQUENCY SPECTRUM

PEAK-TO-PEAK NOISE vs REFERENCE VOLTAGE

V_CC= 5V

(8192 Point FFT, F_IN= 10.120kHz, –0.3dB)

–20

–40

–60

–80

–100

–120

–140

0.1

Frequency (kHz)

Reference Voltage (V)

ADS8320

SBAS108D

www.ti.com

TYPICAL PERFORMANCE CURVES (Cont.)

At T_A= +25°C, V_CC= +5V, V_REF= +5V, f_SAMPLE= 100kHz, and f_CLK= 24 • f_SAMPLE, unless otherwise specified.

SPURIOUS-FREE DYNAMIC RANGE AND

SIGNAL-TO-NOISE RATIO vs FREQUENCY

TOTAL HARMONIC DISTORTION vs FREQUENCY

100

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

Signal-to-Noise Ratio

Spurious-Free Dynamic Range

100

Frequency (kHz)

SIGNAL-TO-(NOISE + DISTORTION) vs FREQUENCY

SIGNAL-TO-(NOISE + DISTORTION) vs INPUT LEVEL

100

–40

–35

–30

–25

–20

–15

–10

–5

Frequency (kHz)

Input Level (dB)

REFERENCE CURRENT vs SAMPLE RATE

REFERENCE CURRENT vs TEMPERATURE

2.7V

100

–50

–25

100

Sample Rate (kHz)

Temperature (°C)

ADS8320

SBAS108D

www.ti.com

charges the internal capacitor array during the sample pe-

riod. After this capacitance has been fully charged, there is

no further input current. The source of the analog input

voltage must be able to charge the input capacitance (45pF)

to a 16-bit settling level within 4.5 clock cycles. When the

converter goes into the hold mode or while it is in the power-

down mode, the input impedance is greater than 1GΩ.

THEORY OF OPERATION

The ADS8320 is a classic successive approximation register

(SAR) analog-to-digital (A/D) converter. The architecture is

based on capacitive redistribution, which inherently includes

a sample/hold function. The converter is fabricated on a 0.6µ

CMOS process. The architecture and process allow the

ADS8320 to acquire and convert an analog signal at up to

100,000 conversions per second while consuming less than

Care must be taken regarding the absolute analog input

voltage. To maintain the linearity of the converter, the –In

input should not drop below GND – 100mV or exceed

GND + 1V. The +In input should always remain within the

range of GND – 100mV to V_CC+ 100mV. Outside of these

ranges, the converter linearity may not meet specifications.

To minimize noise, low bandwidth input signals with low-

pass filters should be used.

4.5mW from +V_CC

The ADS8320 requires an external reference, an external

clock, and a single power source (V_CC). The external refer-

ence can be any voltage between 500mV and V_CC. The value

of the reference voltage directly sets the range of the analog

input. The reference input current depends on the conversion

rate of the ADS8320.

The external clock can vary between 24kHz (1kHz through-

put) and 2.4MHz (100kHz throughput). The duty cycle of

the clock is essentially unimportant, as long as the minimum

high and low times are at least 200ns (V_CC= 2.7V or

greater). The minimum clock frequency is set by the leakage

on the capacitors internal to the ADS8320.

REFERENCE INPUT

The external reference sets the analog input range. The

ADS8320 operates with a reference in the range of 500mV

to V_CC. There are several important implications of this.

As the reference voltage is reduced, the analog voltage

weight of each digital output code is reduced. This is often

referred to as the Least Significant Bit (LSB) size and is

equal to the reference voltage divided by 65,536. This means

that any offset or gain error inherent in the A/D converter

will appear to increase, in terms of LSB size, as the reference

voltage is reduced.

The analog input is provided to two input pins: +In and –In.

When a conversion is initiated, the differential input on these

pins is sampled on the internal capacitor array. While a

conversion is in progress, both inputs are disconnected from

any internal function.

The digital result of the conversion is clocked out by the

DCLOCK input and is provided serially, most significant bit

first, on the D_OUTpin. The digital data that is provided on the

D_OUTpin is for the conversion currently in progress—there

is no pipeline delay. It is possible to continue to clock the

ADS8320 after the conversion is complete and to obtain the

serial data least significant bit first. See the digital timing

section for more information.

The noise inherent in the converter also appears to increase

with lower LSB size. With a +5V reference, the internal

noise of the converter typically contributes only 1.5 LSB

peak-to-peak of potential error to the output code. When the

external reference is 500mV, the potential error contribution

from the internal noise will be 10 times larger—15 LSBs.

The errors due to the internal noise are gaussian in nature

and can be reduced by averaging consecutive conversion

results.

ANALOG INPUT

For more information regarding noise, consult the typical

performance curve “Peak-to-Peak Noise vs Reference Volt-

age.” Note that the Effective Number of Bits (ENOB) figure

is calculated based on the converter’s signal-to-(noise +

distortion) ratio with a 1kHz, 0dB input signal. SINAD is

related to ENOB as follows:

The +In and –In input pins allow for a differential input

signal. Unlike some converters of this type, the –In input is

not re-sampled later in the conversion cycle. When the

converter goes into the hold mode, the voltage difference

between +In and –In is captured on the internal capacitor

array.

SINAD = 6.02 • ENOB + 1.76

The range of the –In input is limited to –0.1V to +1V (–0.1V

to +0.5V when using a 2.7V supply). Because of this, the

differential input can be used to reject only small signals that

are common to both inputs. Thus, the –In input is best used

to sense a remote signal ground that may move slightly with

respect to the local ground potential.

With lower reference voltages, extra care should be taken to

provide a clean layout including adequate bypassing, a clean

power supply, a low-noise reference, and a low-noise input

signal. Because the LSB size is lower, the converter is also

more sensitive to external sources of error such as nearby

digital signals and electromagnetic interference.

The input current on the analog inputs depends on a number

of factors: sample rate, input voltage, source impedance, and

power-down mode. Essentially, the current into the ADS8320

ADS8320

SBAS108D

www.ti.com

converter varies in output code due to the internal noise of

the ADS8320. This is true for all 16-bit SAR-type A/D

converters. Using a histogram to plot the output codes, the

distribution should appear bell-shaped with the peak of the

bell curve representing the nominal code for the input value.

The ±1σ, ±2σ, and ±3σ distributions represents the 68.3%,

95.5%, and 99.7%, respectively, of all codes. The transition

noise can be calculated by dividing the number of codes

measured by 6 and this yields the ±3σ distribution or 99.7%

of all codes. Statistically, up to 3 codes could fall outside the

distribution when executing 1000 conversions. The

ADS8320, with < 3 output codes for the ±3σ distribution,

yields a < ±0.5LSB transition noise. Remember, to achieve

this low noise performance, the peak-to-peak noise of the

input signal and reference must be < 50µV.

NOISE

The noise floor of the ADS8320 itself is extremely low, as

can be seen from Figures 1 and 2, and is much lower than

competing A/D converters. It was tested by applying a low-

noise DC input and a 5.0V reference to the ADS8320 and

initiating 5000 conversions. The digital output of the A/D

2510

2490

AVERAGING

The noise of the A/D converter can be compensated by

averaging the digital codes. By averaging conversion re-

sults, transition noise is reduced by a factor of 1/√n, where

n is the number of averages. For example, averaging four

conversion results reduces the transition noise by 1/2 to

±0.25 LSBs. Averaging should only be used for input

signals with frequencies near DC.

Code

FIGURE 1. Histogram of 5000 Conversions of a DC Input

at the Code Transition.

For AC signals, a digital filter can be used to low-pass filter

and decimate the output codes. This works in a similar

manner to averaging; for every decimation by 2, the signal-

to-noise ratio improves 3dB.

4864

DIGITAL INTERFACE

SIGNAL LEVELS

The digital inputs of the ADS8320 can accommodate logic

levels up to 5.5V regardless of the value of V_CC. Thus, the

ADS8320 can be powered at 3V and still accept inputs from

logic powered at 5V.

The CMOS digital output (D_OUT) swings 0V to V_CC. If V_CC

is 3V and this output is connected to a 5V CMOS logic

input, then that IC may require more supply current than

normal and may have a slightly longer propagation delay.

Code

FIGURE 2. Histogram of 5000 Conversions of a DC Input

at the Code Center.

ADS8320

SBAS108D

www.ti.com

SERIAL INTERFACE

DATA FORMAT

The ADS8320 communicates with microprocessors and other

digital systems via a synchronous 3-wire serial interface, as

shown in Figure 3 and Table I. The DCLOCK signal syn-

chronizes the data transfer with each bit being transmitted on

the falling edge of DCLOCK. Most receiving systems will

capture the bitstream on the rising edge of DCLOCK. How-

ever, if the minimum hold time for D_OUTis acceptable, the

system can use the falling edge of DCLOCK to capture each

bit.

The output data from the ADS8320 is in Straight Binary

format, as shown in Table II. This table represents the ideal

output code for the given input voltage and does not include

the effects of offset, gain error, or noise.

DESCRIPTION

ANALOG VALUE

V_REF

DIGITAL OUTPUT

STRAIGHT BINARY

Full-Scale Range

Least Significant

Bit (LSB)

V_REF/65,536

BINARY CODE

HEX CODE

FFFF

A falling CS signal initiates the conversion and data transfer.

The first 4.5 to 5.0 clock periods of the conversion cycle are

used to sample the input signal. After the fifth falling

DCLOCK edge, D_OUTis enabled and outputs a LOW value

for one clock period. For the next 16 DCLOCK periods,

D_OUToutputs the conversion result, most significant bit first.

After the least significant bit (B0) has been output, subse-

quent clocks repeat the output data but in a least significant

bit first format.

Full-Scale

Midscale

V_REF– 1 LSB

1111 1111 1111 1111

1000 0000 0000 0000

0111 1111 1111 1111

0000 0000 0000 0000

_REF/2

8000

Midscale – 1LSB

Zero

_REF/2 – 1 LSB

7FFF

0000

TABLE II. Ideal Input Voltages and Output Codes.

POWER DISSIPATION

After the most significant bit (B15) has been repeated, D_OUT

will tri-state. Subsequent clocks will have no effect on the

converter. A new conversion is initiated only when CS has

been taken HIGH and returned LOW.

The architecture of the converter, the semiconductor fabrica-

tion process, and a careful design allow the ADS8320 to

convert at up to a 100kHz rate while requiring very little

power. Still, for the absolute lowest power dissipation, there

are several things to keep in mind.

SYMBOL

t_SMPL

DESCRIPTION

Analog Input Sample Time

Conversion Time

MIN

TYP MAX

UNITS

The power dissipation of the ADS8320 scales directly with

conversion rate. Therefore, the first step to achieving the

lowest power dissipation is to find the lowest conversion

rate that satisfies the requirements of the system.

4.5

5.0

Clk Cycles

kHz

t_CONV

t_CYC

100

Throughput Rate

t_CSD

CS Falling to

DCLOCK LOW

In addition, the ADS8320 is in power-down mode under two

conditions: when the conversion is complete and whenever

CS is HIGH (as shown in Figure 3). Ideally, each conversion

should occur as quickly as possible, preferably at a 2.4MHz

clock rate. This way, the converter spends the longest

possible time in the power-down mode. This is very impor-

tant as the converter not only uses power on each DCLOCK

transition (as is typical for digital CMOS components), but

also uses some current for the analog circuitry, such as the

comparator. The analog section dissipates power continu-

ously, until the power-down mode is entered.

t_SUCS

t_hDO

t_dDO

CS Falling to

DCLOCK Rising

DCLOCK Falling to

Current D_OUTNot Valid

DCLOCK Falling to Next

D_OUTValid

t_dis

t_en

CS Rising to D_OUTTri-State

100

DCLOCK Falling to D_OUT

Enabled

t_f

t_r

D_OUTFall Time

D_OUTRise Time

TABLE I. Timing Specifications (V_CC= 2.7V and above,

–40°C to +85°C.

Complete Cycle

CS/SHDN

t_SUCS

Power Down

Sample

Conversion

DCLOCK

D_OUT

t_CSD

Use positive clock edge for data transfer

Hi-Z

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

(MSB) (LSB)

t_SMPL

t_CONV

NOTE: Minimum 22 clock cycles required for 16-bit conversion. Shown are 24 clock cycles.

If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again.

FIGURE 3. ADS8320 Basic Timing Diagrams.

ADS8320

SBAS108D

www.ti.com

1.4V

V_OH

V_OL

3kΩ

D_OUT

Test Point

t_r

t_f

100pF

C_LOAD

Voltage Waveforms for D_OUTRise and Fall Times, t_r, t_f

Load Circuit for t_dDO, t_r, and t_f

Test Point

DCLOCK

V_IL

V_CC

t_disWaveform 2, t_en

3kΩ

D_OUT

t_dDO

V_OH

V_OL

t_disWaveform 1

100pF

C_LOAD

D_OUT

t_hDO

Voltage Waveforms for D_OUTDelay Times, t_dDO

Load Circuit for t_disand t_en

V_IH

CS/SHDN

DCLOCK

D_OUT

Waveform 1⁽¹⁾

90%

10%

t_dis

V_OL

D_OUT

B11

D_OUT

Waveform 2⁽²⁾

t_en

Voltage Waveforms for t_en

Voltage Waveforms for t_dis

NOTES: (1) Waveform 1 is for an output with internal conditions such that the output

is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with

internal conditions such that the output is LOW unless disabled by the output control.

FIGURE 4. Timing Diagrams and Test Circuits for the Parameters in Table I.

ADS8320

SBAS108D

www.ti.com

Figure 5 shows the current consumption of the ADS8320

versus sample rate. For this graph, the converter is clocked

at 2.4MHz regardless of the sample rate—CS is HIGH for

the remaining sample period. Figure 6 also shows current

consumption versus sample rate. However, in this case, the

DCLOCK period is 1/24th of the sample period—CS is

HIGH for one DCLOCK cycle out of every 16.

1000

100

T_A= 25°C

_CLK= 2.4MHz

V_CC= 5.0V

V_REF= 5.0V

V_CC= 2.7V

_REF= 2.5V

There is an important distinction between the power-down

mode that is entered after a conversion is complete and the

full power-down mode which is enabled when CS is HIGH.

CS LOW will shut down only the analog section. The digital

section is completely shut down only when CS is HIGH.

Thus, if CS is left LOW at the end of a conversion and the

converter is continually clocked, the power consumption

will not be as low as when CS is HIGH. Figure 7 shows

more information.

0.1

100

Sample Rate (kHz)

FIGURE 5. Maintaining f_CLKat the Highest Possible Rate

Allows Supply Current to Drop Linearly with

Sample Rate.

Power dissipation can also be reduced by lowering the

power-supply voltage and the reference voltage. The

ADS8320 operates over a V_CCrange of 2.0V to 5.25V.

However, at voltages below 2.7V, the converter will not run

at a 100kHz sample rate. See the typical performance curves

for more information regarding power supply voltage and

maximum sample rate.

1000

100

SHORT CYCLING

Another way of saving power is to utilize the CS signal to

short cycle the conversion. Because the ADS8320 places the

latest data bit on the D_OUTline as it is generated, the

converter can easily be short cycled. This term means that

the conversion can be terminated at any time. For example,

if only 14 bits of the conversion result are needed, then the

conversion can be terminated (by pulling CS HIGH) after

the 14th bit has been clocked out.

T_A= 25°C

_CC= 5.0V

_REF= 5.0V

_CLK= 24 • f_SAMPLE

0.1

100

Sample Rate (kHz)

This technique can be used to lower the power dissipation

(or to increase the conversion rate) in those applications

where an analog signal is being monitored until some con-

dition becomes true. For example, if the signal is outside a

predetermined range, the full 16-bit conversion result may

not be needed. If so, the conversion can be terminated after

the first n bits, where n might be as low as 3 or 4. This results

in lower power dissipation in both the converter and the rest

of the system, as they spend more time in the power-down

mode.

FIGURE 6. Scaling f_CLKReduces Supply Current Only

Slightly with Sample Rate.

1000

T_A= 25°C

_CC= 5.0V

_REF= 5.0V

800

600

400

200

0.0

_CLK= 24 • f_SAMPLE

CS LOW (GND)

LAYOUT

For optimum performance, care should be taken with the

physical layout of the ADS8320 circuitry. This is particu-

larly true if the reference voltage is low and/or the conver-

sion rate is high. At a 100kHz conversion rate, the ADS8320

makes a bit decision every 416ns. That is, for each subse-

quent bit decision, the digital output must be updated with

the results of the last bit decision, the capacitor array

appropriately switched and charged, and the input to the

comparator settled to a 16-bit level all within one clock

cycle.

CS HIGH (V_CC

)

0.250

0.00

0.1

100

Sample Rate (kHz)

FIGURE 7. Shutdown Current with CS HIGH is 50nA

Typically, Regardless of the Clock. Shutdown

Current with CS LOW Varies with Sample

Rate.

ADS8320

SBAS108D

www.ti.com

The basic SAR architecture is sensitive to spikes on the

power supply, reference, and ground connections that occur

just prior to latching the comparator output. Thus, during

any single conversion for an n-bit SAR converter, there are

n “windows” in which large external transient voltages can

easily affect the conversion result. Such spikes might origi-

nate from switching power supplies, digital logic, and high

power devices, to name a few. This particular source of error

can be very difficult to track down if the glitch is almost

synchronous to the converter DCLOCK signal—as the phase

difference between the two changes with time and tempera-

ture, causing sporadic misoperation.

Also, keep in mind that the ADS8320 offers no inherent

rejection of noise or voltage variation in regards to the

reference input. This is of particular concern when the

reference input is tied to the power supply. Any noise and

ripple from the supply will appear directly in the digital

results. While high-frequency noise can be filtered out as

described in the previous paragraph, voltage variation due to

the line frequency (50Hz or 60Hz), can be difficult to

remove.

The GND pin on the ADS8320 should be placed on a clean

ground point. In many cases, this will be the “analog”

ground. Avoid connecting the GND pin too close to the

grounding point for a microprocessor, microcontroller, or

digital signal processor. If needed, run a ground trace di-

rectly from the converter to the power-supply connection

point. The ideal layout includes an analog ground plane for

the converter and associated analog circuitry.

With this in mind, power to the ADS8320 should be clean

and well bypassed. A 0.1µF ceramic bypass capacitor should

be placed as close to the ADS8320 package as possible. In

addition, a 1µF to 10µF capacitor and a 5Ω or 10Ω series

resistor may be used to low-pass filter a noisy supply.

The reference should be similarly bypassed with a 0.1µF

capacitor. Again, a series resistor and large capacitor can be

used to low-pass filter the reference voltage. If the reference

voltage originates from an op amp, be careful that the op

amp can drive the bypass capacitor without oscillation (the

series resistor can help in this case). Keep in mind that while

the ADS8320 draws very little current from the reference on

average, there are still instantaneous current demands placed

on the external input and reference circuitry.

APPLICATION CIRCUITS

Figure 8 shows a basic data acquisition system. The ADS8320

input range is 0V to V_CC, as the reference input is connected

directly to the power supply. The 5Ω resistor and 1µF to

10µF capacitor filter the microcontroller “noise” on the

supply, as well as any high-frequency noise from the supply

itself. The exact values should be picked such that the filter

provides adequate rejection of the noise.

Texas Instruments' OPA627 op amp provides optimum

performance for buffering both the signal and reference

inputs. For low-cost, low-voltage, single-supply applica-

tions, the OPA2350 or OPA2340 dual op amps are recom-

mended.

+2.7V to +5.25V

5Ω

1µF to

10µF

ADS8320

V_REF

V_CC

1µF to

10µF

0.1µF

Microcontroller

+In

D_OUT

–In

GND

DCLOCK

FIGURE 8. Basic Data Acquisition System.

ADS8320

SBAS108D

www.ti.com

Revision History

DATE

3/07

REVISION PAGE

SECTION

DESCRIPTION

Added last row, Input current to any pin except supply...±10mA

Absolute Max Ratings

7/06

Typ Performance Curves Changed CHANGE IN OFFSET vs TEMPERATURE plot

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

ADS8320

SBAS108D

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

PACKAGING INFORMATION

Orderable Device

ADS8320E/250

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

ACTIVE

VSSOP

DGK

250

Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR

& no Sb/Br)

A20

ADS8320E/250G4

ADS8320E/2K5

ACTIVE

DGK

250

2500

250

Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR

& no Sb/Br)

Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR

& no Sb/Br)

ADS8320E/2K5G4

ADS8320EB/250

ADS8320EB/250G4

ADS8320EB/2K5

ADS8320EB/2K5G4

Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR

& no Sb/Br)

Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR

& no Sb/Br)

250

Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR

& no Sb/Br)

2500

Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR

& no Sb/Br)

Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF ADS8320 :

NOTE: Qualified Version Definitions:

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

6-Nov-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADS8320E/250

ADS8320E/2K5

ADS8320EB/250

ADS8320EB/2K5

VSSOP

DGK

250

2500

250

180.0

330.0

180.0

330.0

12.4

5.3

3.4

1.4

8.0

12.0

2500

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

6-Nov-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ADS8320E/250

ADS8320E/2K5

ADS8320EB/250

ADS8320EB/2K5

VSSOP

DGK

250

2500

250

210.0

367.0

210.0

367.0

185.0

367.0

185.0

367.0

35.0

2500

Pack Materials-Page 2

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ADS8320 [TI]

相关型号：

ADS8320-HT

ADS8320E

ADS8320E/250

ADS8320E/250G4

ADS8320E/2K5

ADS8320E250

ADS8320E250G4

ADS8320E2K5

ADS8320E2K5G4

ADS8320EB

ADS8320EB

ADS8320EB/250