ADS8324E/2K5G4 [TI]
1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8, GREEN, PLASTIC, MSOP-8;
| 型号： | ADS8324E/2K5G4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8, GREEN, PLASTIC, MSOP-8 光电二极管 转换器 |
| 文件： | 总19页 (文件大小：736K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS8324
SBAS172A – AUGUST 2001 – REVISED MARCH 2004
14-Bit, High Speed, 1.8V MicroPower Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
● BIPOLAR INPUT RANGE
The ADS8324 is a 14-bit, sampling Analog-to-Digital (A/D)
converter with tested specifications using a 1.8V supply
voltage. It requires very little power, even when operating at
the full 50kHz data rate. At lower data rates, the high speed
of the device enables it to spend most of its time in the
power-down mode—the average power dissipation is less
than 1mW at 10kHz data rate.
● 1.8V OPERATION
● 50kHz SAMPLING RATE
● MICRO POWER:
5.0mW at 2.7V
2.5mW at 1.8V
● POWER DOWN: 3μA max
● MSOP-8 PACKAGE
The ADS8324 also features a synchronous serial (SPI/SSI
compatible) interface, and a differential input. The refer-
ence voltage can be set to any level within the range of
500mV to VCC/2.
● PIN-COMPATIBLE TO 12-BIT ADS7817
● SERIAL (SPI/SSI) INTERFACE
Ultra-low power and small size make the ADS8324 ideal
for portable and battery-operated systems. It is also a
perfect fit for remote data acquisition modules, simulta-
neous multi-channel systems, and isolated data acquisi-
tion. The ADS8324 is available in an MSOP-8 package.
APPLICATIONS
● BATTERY OPERATED SYSTEMS
● REMOTE DATA ACQUISITION
● ISOLATED DATA ACQUISITION
● SIMULTANEOUS SAMPLING,
MULTI-CHANNEL SYSTEMS
● INDUSTRIAL CONTROLS
● ROBOTICS
● VIBRATION ANALYSIS
SAR
VREF
ADS8324
DOUT
+In
–In
CDAC
Serial
Interface
DCLOCK
CS/SHDN
S/H Amp
Comparator
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2001-2004, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
VCC ....................................................................................................... +6V
Analog Input ............................................................. –0.3V to (VCC + 0.3V)
Logic Input .............................................................................. –0.3V to 6V
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +125°C
External Reference Voltage .............................................................. +5.5V
Top View
MSOP
VREF
+In
1
2
3
4
8
7
6
5
+VCC
DCLOCK
DOUT
ADS8324
–In
NOTE: (1) Stresses above these ratings may permanently damage the device.
GND
CS/SHDN
ELECTROSTATIC
DISCHARGE SENSITIVITY
PIN ASSIGNMENTS
PIN
1
NAME
VREF
DESCRIPTION
Reference Input
Non Inverting Input
Inverting Input
Ground
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
2
+In
3
–In
4
GND
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
5
CS/SHDN
Chip Select when LOW, Shutdown Mode when
HIGH.
6
DOUT
The serial output data word is comprised of 16
bits of data. In operation, the data is valid on the
rising edge of DCLOCK. The fifth falling edge of
DCLOCK after the falling edge of CS enables
the serial output. After one null bit, data is valid
for the next 16 edges.
7
8
DCLOCK
+VCC
Data Clock synchronizes the serial data transfer
and determines conversion speed.
Power Supply
PACKAGE/ORDERING INFORMATION
MAXIMUM
INTEGRAL
LINEARITY
ERROR (LSB)
NO
MISSING
CODES
PACKAGE
DRAWING
NUMBER(1)
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
MARKING(2)
ORDERING
NUMBER(3)
TRANSPORT
MEDIA
PRODUCT
ERROR (LSB)
PACKAGE
ADS8324E
3
"
2
14
"
14
MSOP
337
"
337
–40°C to +85°C
A24
"
A24
ADS8324E/250
ADS8324E/2K5
Tape and Reel
Tape and Reel
"
"
MSOP
"
"
ADS8324EB
–40°C to +85°C
ADS8324EB/250
Tape and Reel
"
"
"
"
"
"
ADS8324EB/2K5 Tape and Reel
NOTES: (1) For detail drawing and dimension table, please see end of data sheet or package drawing file on web. (2) Performance grade information is marked
on the reel. (3) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500
pieces of “ADS8324EB/2K5” will get a single 2500-piece Tape and Reel.
ADS8324
2
SBAS172A
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ELECTRICAL CHARACTERISTICS: +VCC = +1.8V
At –40°C to +85°C, VREF = 0.9V, –In = 0.9V, fSAMPLE = 50kHz, and fCLK = 24 • fSAMPLE, unless otherwise specified.
ADS8324E
ADS8324EB
TYP
PARAMETER
RESOLUTION
CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
14
✻
Bits
ANALOG INPUT
Full-Scale Input Span
Absolute Input Range
+In – (–In)
+In
–VREF
–0.1
0.8
+VREF
VCC + 0.1
+1.0
✻
✻
✻
✻
✻
✻
V
V
–In
V
Capacitance
25
1
✻
✻
pF
nA
Leakage Current
SYSTEM PERFORMANCE
No Missing Codes
14
14
Bits
LSB
Integral Linearity Error
Bipolar Zero Error
3
8
2
4
4
0.1
4
2
✻
✻
✻
✻
✻
✻
LSB
Bipolar Zero Error Drift
Gain Error
μV/°C
LSB
8
✻
Gain Temperature Drift
Noise
0.4
60
74
3
ppm/°C
μVrms
dB
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
at DCC
+1.8V < VCC < +3.6V
LSB(1)
SAMPLING DYNAMICS
Conversion Time
16
✻
Clk Cycles
Clk Cycles
kHz
Acquisition Time
4.5
✻
✻
Throughput Rate
50
✻
✻
Clock Frequency Range
0.024
1.8
MHz
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion
SINAD
VIN = 5Vp-p at 10kHz
VIN = 5Vp-p at 10kHz
VIN = 5Vp-p at 10kHz
–84
77
–86
78
86
✻
dB
dB
dB
dB
Spurious Free Dynamic Range
SNR
85
78
REFERENCE INPUT
Voltage Range
Resistance
0.5
VCC/2
✻
✻
✻
V
CS = GND, fSAMPLE = 0Hz
CS = VCC
5
✻
✻
✻
✻
✻
GΩ
GΩ
μA
μA
μA
5
Current Drain
40
0.8
0.1
80
3
fSAMPLE = 10kHz
CS = VCC
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels:
VIH
CMOS
✻
IIH = +5μA
IIL = +5μA
IOH = –250μA
IOL = 250μA
1.3
–0.3
1.4
VCC + 0.3
0.5
✻
✻
✻
✻
✻
V
V
V
V
VIL
VOH
VOL
0.4
✻
✻
Data Format
Binary Two’s Complement
POWER SUPPLY REQUIREMENTS
VCC
VCC Range(2)
Specified Performance
1.8
✻
V
V
1.8
3.6
✻
✻
✻
Quiescent Current
1400
250
2.5
1700
✻
✻
✻
✻
μA
μA
mW
μA
fSAMPLE = 10kHz(3, 4)
VCC = 1.8V
Power Dissipation
Power Down
3.0
3.0
✻
✻
CS = VCC
0.3
TEMPERATURE RANGE
Specified Performance
–40
+85
✻
✻
°C
✻ Specifications same as ADS8324E.
NOTES: (1) LSB means Least Significant Bit. (2) See Typical Performance Curves for more information. (3) fCLK = 1.2MHz, CS = VCC for 216 clock cycles out
of every 240. (4) See the Power Dissipation section for more information regarding lower sample rates.
ADS8324
3
SBAS172A
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TYPICAL CHARACTERISTICS
At TA = +25°C, VCC = 1.8V, VREF = 0.9V, fSAMPLE = 50kHz, fCLK = 24 • fSAMPLE, unless otherwise specified.
FREQUENCY SPECTRUM
FREQUENCY SPECTRUM
(4096 point FFT, fIN = 0.989kHz, –0.2dB)
(4096 point FFT, fIN = 9.998kHz, –0.2dB)
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–100
–120
–140
0
5
10
15
20
25
0
5
10
15
20
25
Frequency (kHz)
Frequency (kHz)
SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-(NOISE + DISTORTION)
vs INPUT FREQUENCY
FREQUENCY SPECTRUM
(4096 point FFT, fIN = 20.001kHz, –0.2dB)
0
–20
90
85
80
75
70
65
60
SNR
–40
–60
–80
SINAD
–100
–120
–140
1
10
100
0
5
10
15
20
25
Frequency (kHz)
Frequency (kHz)
SIGNAL-TO-NOISE RATIO AND
TOTAL HARMONIC DISTORTION
vs INPUT FREQUENCY
COMMON-MODE REJECTION vs FREQUENCY
100
95
90
85
80
75
70
65
60
–100
–95
–90
–85
–80
–75
–70
–65
–60
80
75
70
65
60
55
50
45
40
SFDR
THD(1)
VCM = 400mVp-p sinewave centered around VREF
NOTE: (1) First nine harmonics
of the input frequency.
1
10
Frequency (kHz)
100
100
1k
10k
100k
1M
Frequency (kHz)
ADS8324
4
SBAS172A
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TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VCC = 1.8V, VREF = 0.9V, fSAMPLE = 50kHz, fCLK = 24 • fSAMPLE, unless otherwise specified.
DIFFERENTIAL LINEARITY ERROR vs CODE
INTEGRAL LINEARITY ERROR vs CODE
2
1
2
1
0
0
–1
–2
–1
2000H
3000H
0000H
1000H
1FFFH
2000H
3000H
0000H
1000H
1FFFH
Output Code
Output Code
QUIESCENT CURRENT vs VCC
REFERENCE CURRENT vs TEMPERATURE
2.5
2
10
9
8
7
6
5
4
3
2
1
0
1.5
1
0.5
0
1.5
2
2.5
3
3.5
4
–50
–30
–10
10
30
50
70
90
VCC (V)
Temperature (°C)
SUPPLY CURRENT vs TEMPERATURE
REFERENCE CURRENT vs SAMPLE RATE
2
1.8
1.6
1.4
1.2
1
10
9
8
7
6
5
4
3
2
1
0
0.8
0.6
0.4
0.2
0
–50
–30
–10
10
30
50
70
90
0
20
40
60
80
Temperature (°C)
Sample Rate (kHz)
ADS8324
5
SBAS172A
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TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VCC = 1.8V, VREF = 0.9V, fSAMPLE = 50kHz, fCLK = 24 • fSAMPLE, unless otherwise specified.
CHANGE IN BIPOLAR OFFSET vs TEMPERATURE
CHANGE IN GAIN vs TEMPERATURE
1
0.8
1
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1
–0.2
–0.4
–0.6
–0.8
–1
–50
0.4
0.4
–30
–10
10
30
50
70
90
110
1.1
1.1
–50
–30
–10
10
30
50
70
90
110
Temperature (°C)
Temperature (°C)
CHANGE IN BPZ vs REFERENCE VOLTAGE
CHANGE IN GAIN vs REFERENCE VOLTAGE
10
8
10
8
6
6
4
4
2
2
0
0
–2
–4
–6
–8
–10
–2
–4
–6
–8
–10
0.5
0.6
0.7
0.8
0.9
1
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
Reference Voltage (V)
Reference Voltage (V)
MAXIMUM SAMPLING RATE vs SUPPLY VOLTAGE
NOISE vs REFERENCE VOLTAGE
1000
100
10
10
9
8
7
6
5
4
3
2
1
0
1
1.5
2
2.5
Supply (V)
3
3.5
4
0.5
0.6
0.7
0.8
0.9
1
Reference Voltage (V)
ADS8324
6
SBAS172A
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THEORY OF OPERATION
2 • VREF
peak-to-peak
The ADS8324 is a classic Successive Approximation Reg-
ister (SAR) A/D converter. The architecture is based on
capacitive redistribution that inherently includes a sample-
and-hold function. The converter is fabricated on a 0.6μ
CMOS process. The architecture and process allow the
ADS8324 to acquire and convert an analog signal at up to
50,000 conversions per second while consuming less than
ADS8324
Common
Voltage
Single-Ended Input
VREF
peak-to-peak
3.0mW from +VCC
.
ADS8324
The ADS8324 requires an external reference, an external
clock, and a single power source (VCC). The external refer-
ence can be any voltage between 500mV and VCC /2. The
value of the reference voltage directly sets the range of the
analog input. The reference input current depends on the
conversion rate of the ADS8324.
Common
Voltage
VREF
peak-to-peak
Differential Input
FIGURE 1. Methods of Driving the ADS8324—Single-Ended
or Differential.
The external clock can vary between 24kHz (1kHz through-
put) and 1.2MHz (50kHz throughput). The duty cycle of the
clock is essentially unimportant as long as the minimum
high and low times are at least 200ns. The minimum clock
frequency is set by the leakage on the capacitors internal to
the ADS8324.
2
VCC = 1.8V
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
The analog input is provided to two input pins: +In and –In.
When a conversion is initiated, the differential input on these
pins is sampled on the internal capacitor array. While a
conversion is in progress, both inputs are disconnected from
any internal function.
Single-Ended Input
The digital result of the conversion is clocked out by the
DCLOCK input and is provided serially, most significant bit
first, on the DOUT pin. The digital data that is provided on the
DOUT pin is for the conversion currently in progress—there
is no pipeline delay. It is possible to continue to clock the
ADS8324 after the conversion is complete and to obtain the
serial data least significant bit first. See the digital timing
section for more information.
–0.2
–0.4
–0.6
–0.8
–1
0.5
0.6
0.7
0.8
0.9
1
V
REF (V)
FIGURE 2. Single-Ended Input—Common Voltage Range
vs VREF
.
ANALOG INPUT
The analog input is bipolar and fully differential. There are
two general methods of driving the analog input of the
ADS8324: single-ended or differential, as shown in Figure
1. When the input is single-ended, the –In input is held at a
fixed voltage. The +In input swings around the same voltage
and the peak-to-peak amplitude is 2 • VREF. The value of
VREF determines the range over which the common voltage
may vary, as shown in Figure 2.
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
Differential Input
When the input is differential, the amplitude of the input is
the difference between the +In and –In input, or, +In – (–In).
A voltage or signal is common to both of these inputs. The
peak-to-peak amplitude of each input is VREF about this
common voltage. However, since the inputs are 180° out-of-
phase, the peak-to-peak amplitude of the difference voltage
is 2 • VREF. The value of VREF also determines the range of
the voltage that may be common to both inputs, as shown in
Figure 3.
VCC = 1.8V
0.6
0.5
0.7
0.8
0.9
1
VREF (V)
In each case, care should be taken to ensure that the output
impedance of the sources driving the +In and –In inputs are
matched. If this is not observed, the two inputs could have
FIGURE 3. Differential Input—Common Voltage Range vs
VREF.
ADS8324
7
SBAS172A
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NOISE
different settling times. This may result in offset error, gain
error, and linearity error that changes with both temperature
and input voltage. If the impedance cannot be matched, the
errors can be lessened by giving the ADS8324 additional
acquisition time.
The noise floor of the ADS8324 itself is extremely low, as
can be seen from Figure 4, and is much lower than compet-
ing A/D converters. It was tested by applying a low noise
DC input and a 0.9V reference to the ADS8324 and initiat-
ing 5,000 conversions. The digital output of the A/D con-
verter will vary in output code due to the internal noise of
the ADS8324. This is true for all 14-bit SAR-type A/D
converters. Using a histogram to plot the output codes, the
distribution should appear bell-shaped, with the peak of the
bell curve representing the nominal code for the input value.
The 1σ, 2σ, and 3σ distributions will represent the
68.3%, 95.5%, and 99.7%, respectively, of all codes. The
transition noise can be calculated by dividing the number of
codes measured by 6 and this will yield the 3σ distribution
or 99.7% of all codes. Statistically, up to 3 codes could fall
outside the distribution when executing 1000 conversions.
The ADS8324, with five output codes for the 3σ distribu-
tion, will yield a 0.8LSB transition noise. Remember, to
achieve this low-noise performance, the peak-to-peak noise
of the input signal and reference must be < 50μV.
The input current on the analog inputs depends on a number
of factors: sample rate, input voltage, and source impedance.
Essentially, the current into the ADS8324 charges the inter-
nal capacitor array during the sample period. After this
capacitance has been fully charged, there is no further input
current. The source of the analog input voltage must be able
to charge the input capacitance (25pF) to the 14-bit settling
level within 4.5 clock cycles. When the converter goes into
the hold mode, or while it is in the power-down mode, the
input impedance is greater than 1GΩ.
Care must be taken regarding the absolute analog input
voltage. The +In input should always remain within the
range of GND – 100mV to VCC + 100mV. The –In input
should always remain within the range of GND – 100mV to
2V. Outside of these ranges, the converter’s linearity may
not meet specifications.
REFERENCE INPUT
3857
The external reference sets the analog input range. The
ADS8324 will operate with a reference in the range of
500mV to VCC /2. There are several important implications
of this. As the reference voltage is reduced, the analog
voltage weight of each digital output code is reduced. This
is often referred to as the Least Significant Bit (LSB) size
and is equal to 2 • VREF divided by 16,384. This means that
any offset or gain error inherent in the A/D converter will
appear to increase, in terms of LSB size, as the reference
voltage is reduced.
583
560
0
0
3FFEH 3FFFH 0000H
Code
0001H 0002H
The noise inherent in the converter will also appear to increase
with lower LSB size. With a 0.9V reference, the internal noise
of the converter typically contributes only 5LSB peak-to-peak
of potential error to the output code. When the external
reference is 500mV, the potential error contribution from the
internal noise will be 7LSBs. The errors due to the internal
noise are gaussian in nature and can be reduced by averaging
consecutive conversion results.
FIGURE 4. Histogram of 5,000 Conversions of a DC Input
at the Code Transition.
AVERAGING
The noise of the A/D converter can be compensated by
averaging the digital codes. By averaging conversion re-
sults, transition noise will be reduced by a factor of 1/√n,
where n is the number of averages. For example, averaging
4 conversion results will reduce the transition noise by 1/2
to 0.25LSBs. Averaging should only be used for input
signals with frequencies near DC.
For more information regarding noise, consult the typical
performance curve “Noise vs Reference Voltage.” Note that
the Effective Number of Bits (ENOB) figure is calculated
based on the converter’s signal-to-(noise + distortion) ratio
with a 1kHz, 0dB input signal. SINAD is related to ENOB
as follows:
For AC signals, a digital filter can be used to low-pass filter
and decimate the output codes. This works in a similar
manner to averaging; for every decimation by 2, the signal-
to-noise ratio will improve 3dB.
SINAD = 6.02 • ENOB + 1.76
With lower reference voltages, extra care should be taken to
provide a clean layout including adequate bypassing, a clean
power supply, a low-noise reference, and a low-noise input
signal. Because the LSB size is lower, the converter will also
be more sensitive to external sources of error such as nearby
digital signals and electromagnetic interference.
ADS8324
8
SBAS172A
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SYMBOL
DESCRIPTION
MIN
TYP MAX
UNITS
DIGITAL INTERFACE
tSMPL
tCONV
tCYC
Analog Input Sample Time
Conversion Time
Throughput Rate
CS Falling to
4.5
5.0
Clk Cycles
Clk Cycles
kHz
SIGNAL LEVELS
16
50
0
The CMOS digital output (DOUT) will swing from 0V to
VCC. If VCC is 3V, and this output is connected to a 5V
CMOS logic input, then that IC may require more supply
current than normal and may have a slightly longer propaga-
tion delay.
tCSD
ns
DCLOCK LOW
tSUCS
CS Falling to
50
5
ns
DCLOCK Rising
thDO
tdDO
DCLOCK Falling to
Current DOUT Not Valid
20
ns
ns
SERIAL INTERFACE
DCLOCK Falling to Next
DOUT Valid
100
250
The ADS8324 communicates with microprocessors and
other digital systems via a synchronous 3-wire serial inter-
face, as shown in Figure 5 and Table I. The DCLOCK signal
synchronizes the data transfer with each bit being transmit-
ted on the falling edge of DCLOCK. Most receiving systems
will capture the bitstream on the rising edge of DCLOCK.
However, if the minimum hold time for DOUT is acceptable,
the system can use the falling edge of DCLOCK to
capture each bit.
tdis
ten
CS Rising to DOUT Tri-State
50
100
200
ns
ns
DCLOCK Falling to DOUT
Enabled
100
tf
tr
DOUT Fall Time
DOUT Rise Time
50
75
150
200
ns
ns
TABLE I. Timing Specifications (VCC = 1.8V) –40°C to
+85°C.
See Figure 6 for test conditions.
A falling CS signal initiates the conversion and data transfer.
The first 4.5 to 5.0 clock periods of the conversion cycle are
used to sample the input signal. After the fifth falling
DCLOCK edge, DOUT is enabled and will output a LOW
value for one clock period. For the next 16 DCLOCK
periods, DOUT will output the conversion result, most sig-
nificant bit first followed by two zeros on clock cycles 15
and 16. After the two zero “dummy bits” have been output,
subsequent clocks will repeat the output data but in a least
significant bit first format starting with a zero.
DATA FORMAT
The output data from the ADS8324 is in Binary Two’s
Complement format, as shown in Table II. This table repre-
sents the ideal output code for the given input voltage and
does not include the effects of offset, gain error, or noise.
DESCRIPTION
ANALOG VALUE
2 • VREF
DIGITAL OUTPUT
Full-Scale Range
BINARY TWO’S COMPLEMENT
CS must be taken HIGH following a conversion in order to
place DOUT in tri-state. Subsequent clocks will have no
effect on the converter. A new conversion is initiated only
when CS has been taken HIGH and returned LOW.
Least Significant
Bit (LSB)
2 • VREF/16384
BINARY CODE
HEX CODE
7FFC
+Full Scale
Midscale
+VREF – 1 LSB
0V
0111 1111 1111 1100
0000 0000 0000 0000
1111 1111 1111 1100
1000 0000 0000 0000
0000
Midscale – 1LSB
–Full Scale
0V – 1 LSB
–VREF
FFFC
8000
TABLE II. Ideal Input Voltages and Output Codes.
Complete Cycle
CS/SHDN
tSUCS
Power Down
Sample
Conversion
DCLOCK
DOUT
tCSD
Use positive clock edge for data transfer
Hi-Z
Hi-Z
0
B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0
0
(MSB)
(LSB)
tSMPL
tCONV
NOTE: Minimum 22 clock cycles required for 14-bit conversion. Shown are 24 clock cycles.
If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again.
FIGURE 5. ADS8324 Basic Timing Diagrams.
ADS8324
9
SBAS172A
www.ti.com
In addition, the ADS8324 is in power-down mode under two
conditions: when the conversion is complete and whenever
CS is HIGH (see Figure 5). Ideally, each conversion should
occur as quickly as possible, preferably at a 1.2MHz clock
rate. This way, the converter spends the longest possible
time in the power-down mode. This is very important as the
converter not only uses power on each DCLOCK transition
(as is typical for digital CMOS components) but also uses
some current for the analog circuitry, such as the compara-
tor. The analog section dissipates power continuously, until
the power-down mode is entered.
POWER DISSIPATION
The architecture of the converter, the semiconductor fabrica-
tion process, and a careful design allow the ADS8324 to
convert at up to a 50kHz rate while requiring very little
power. Still, for the absolute lowest power dissipation, there
are several things to keep in mind.
The power dissipation of the ADS8324 scales directly with
the conversion rate. Therefore, the first step to achieving the
lowest power dissipation is to find the lowest conversion rate
that will satisfy the requirements of the system.
0.9V
VOH
3kΩ
DOUT
VOL
DOUT
Test Point
tr
tf
30pF
CLOAD
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
Load Circuit for tdDO, tr, and tf
Test Point
DCLOCK
VIL
VCC
tdis Waveform 2, ten
3kΩ
DOUT
tdDO
VOH
tdis Waveform 1
30pF
CLOAD
DOUT
VOL
thDO
Load Circuit for tdis and ten
Voltage Waveforms for DOUT Delay Times, tdDO
VIH
CS/SHDN
CS/SHDN
DCLOCK
5
6
DOUT
Waveform 1(1)
90%
10%
tdis
VOL
DOUT
B11
DOUT
Waveform 2(2)
ten
Voltage Waveforms for ten
Voltage Waveforms for tdis
NOTES: (1) Waveform 1 is for an output with internal conditions such that the output
is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with
internal conditions such that the output is LOW unless disabled by the output control.
FIGURE 6. Timing Diagrams and Test Circuits for the Parameters in Table I.
ADS8324
10
SBAS172A
www.ti.com
Figure 7 shows the current consumption of the ADS8324
versus sample rate. For this graph, the converter is clocked
at 1.2MHz regardless of the sample rate—CS is HIGH for
the remaining sample period. Figure 8 also shows current
consumption versus sample rate. However, in this case, the
DCLOCK period is 1/24th of the sample period—CS is
HIGH for one DCLOCK cycle out of every 16.
10000
1000
800
TA = 25°C
VCC = 1.8V
VREF = 0.9V
fCLK = 24 • fSAMPLE
600
There is an important distinction between the power-down
mode that is entered after a conversion is complete and the
full power-down mode that is enabled when CS is HIGH. CS
LOW will shut down only the analog section. The digital
section is completely shutdown only when CS is HIGH.
Thus, if CS is left LOW at the end of a conversion and the
converter is continually clocked, the power consumption
will not be as low as when CS is HIGH, shown in Figure 9.
400
CS LOW (GND)
200
0.250
0.00
CS HIGH (VCC
)
0.1
1
10
100
Sample Rate (kHz)
10000
FIGURE 9. Shutdown Current with CS HIGH is 50nA
Typically, Regardless of the Clock. Shutdown
Current with CS LOW Varies with Sample
Rate.
TA = 25°C
V
CC = 1.8V
VREF = 0.9V
CLK = 2.4MHz
f
1000
100
10
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS8324 circuitry. This will be
particularly true if the reference voltage is low and/or the
conversion rate is high. At a 50kHz conversion rate, the
ADS8324 makes a bit decision every 213ns. That is, for each
subsequent bit decision, the digital output must be updated
with the results of the last bit decision, the capacitor array
appropriately switched and charged, and the input to the
comparator settled to a 14-bit level all within one clock
cycle.
0.1
1
10
100
Sample Rate (kHz)
FIGURE 7. Maintaining fCLK at the Highest Possible Rate
Allows Supply Current to Drop Linearly with
Sample Rate.
The basic SAR architecture is sensitive to spikes on the
power supply, reference, and ground connections that occur
just prior to latching the comparator output. Thus, during
any single conversion for an n-bit SAR converter, there are
n “windows” in which large external transient voltages can
easily affect the conversion result. Such spikes might origi-
nate from switching power supplies, digital logic, and high
power devices, to name a few. This particular source of error
can be very difficult to track down if the glitch is almost
synchronous to the converter’s DCLOCK signal—as the
phase difference between the two changes with time and
temperature, causing sporadic misoperation.
10000
1000
100
TA = 25°C
VCC = 1.8V
VREF = 0.9V
fCLK = 24 • fSAMPLE
100
With this in mind, power to the ADS8324 should be clean
and well bypassed. A 0.1μF ceramic bypass capacitor should
be placed as close to the ADS8324 package as possible. In
addition, a 1μF to 10μF capacitor and a 5Ω or 10Ω series
resistor may be used to low-pass filter a noisy supply.
10
0.1
1
10
Sample Rate (kHz)
FIGURE 8. Scaling fCLK Reduces Supply Current Only
Slightly with Sample Rate.
The reference should be similarly bypassed with a 0.1μF
capacitor. Again, a series resistor and large capacitor can be
used to low-pass filter the reference voltage. If the reference
voltage originates from an op amp, be careful that the op
ADS8324
11
SBAS172A
www.ti.com
amp can drive the bypass capacitor without oscillation (the
series resistor can help in this case). Keep in mind that while
the ADS8324 draws very little current from the reference on
average, there are still instantaneous current demands placed
on the external input and reference circuitry.
The GND pin on the ADS8324 should be placed on a clean
ground point. In many cases, this will be the “analog”
ground. Avoid connecting the GND pin too close to the
grounding point for a microprocessor, microcontroller, or
digital signal processor. If needed, run a ground trace di-
rectly from the converter to the power supply connection
point. The ideal layout will include an analog ground plane
for the converter and associated analog circuitry.
Texas Instruments OPA627 op amp provides optimum per-
formance for buffering both the signal and reference inputs.
For low-cost, low-voltage, single-supply applications, the
OPA2350 or OPA2340 dual op amps are recommended.
Also, keep in mind that the ADS8324 offers no inherent
rejection of noise or voltage variation in regards to the
reference input. This is of particular concern when the
reference input is tied to the power supply. Any noise and
ripple from the supply will appear directly in the digital
results. While high frequency noise can be filtered out as
described in the previous paragraph, voltage variation due to
the line frequency (50Hz or 60Hz), can be difficult to
remove.
APPLICATION CIRCUITS
Figure 10 shows a basic data acquisition system. The
ADS8324 input range is 0V to VCC, as the reference input is
connected directly to the power supply. The 5Ω resistor and
1μF to 10μF capacitor filter the microcontroller “noise” on
the supply, as well as any high-frequency noise from the
supply itself. The exact values should be picked such that the
filter provides adequate rejection of the noise.
1.8V
5Ω
+
1μF to 10μF
ADS8324
VREF
0.9V
Reference
VCC
1μF to
10μF
+
0.1μF
Microcontroller
+In
CS
DOUT
0V to 1.8V
–In
GND
DCLOCK
FIGURE 10. Basic Data Acquisition System.
ADS8324
12
SBAS172A
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ADS8324E
OBSOLETE
ACTIVE
VSSOP
VSSOP
DGK
8
8
TBD
Call TI
Call TI
A24
A24
ADS8324E/250
DGK
250
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
ADS8324E/250G4
ADS8324E/2K5
ACTIVE
ACTIVE
VSSOP
VSSOP
DGK
DGK
8
8
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
CU NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
A24
A24
2500
Green (RoHS
& no Sb/Br)
ADS8324EB
OBSOLETE
ACTIVE
VSSOP
VSSOP
DGK
DGK
8
8
TBD
Call TI
Call TI
A24
A24
ADS8324EB/250
250
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
ADS8324EB/250G4
ADS8324EB/2K5
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
8
8
8
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
CU NIPDAUAG
CU NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
A24
A24
A24
2500
2500
Green (RoHS
& no Sb/Br)
ADS8324EB/2K5G4
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS8324E/250
ADS8324E/2K5
ADS8324EB/250
ADS8324EB/2K5
VSSOP
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
DGK
8
8
8
8
250
2500
250
180.0
330.0
180.0
330.0
12.4
12.4
12.4
12.4
5.3
5.3
5.3
5.3
3.4
3.4
3.4
3.4
1.4
1.4
1.4
1.4
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS8324E/250
ADS8324E/2K5
ADS8324EB/250
ADS8324EB/2K5
VSSOP
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
DGK
8
8
8
8
250
2500
250
210.0
367.0
210.0
367.0
185.0
367.0
185.0
367.0
35.0
35.0
35.0
35.0
2500
Pack Materials-Page 2
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