ADS8326IDGKT [TI]
16 位、伪差动输入、250kSPS 串行输出、2.7V 至 5.5V 微功耗采样 ADC | DGK | 8 | -40 to 85;
| 型号： | ADS8326IDGKT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16 位、伪差动输入、250kSPS 串行输出、2.7V 至 5.5V 微功耗采样 ADC | DGK | 8 | -40 to 85 |
| 文件： | 总39页 (文件大小：1144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS8326
www.ti.com.................................................................................................................................................. SBAS343C –MAY 2007–REVISED SEPTEMBER 2009
16-Bit, High-Speed, 2.7V to 5.5V microPower Sampling
ANALOG-TO-DIGITAL CONVERTER
Check for Samples: ADS8326
1
FEATURES
APPLICATIONS
•
•
•
•
Battery-Operated Systems
Remote Data Acquisition
Isolated Data Acquisition
Simultaneous Sampling, Multichannel
Systems
Industrial Controls
Robotics
Vibration Analysis
23
•
16 Bits No Missing Codes (Full-Supply Range,
High or Low Grade)
•
•
Very Low Noise: 3LSBPP
Excellent Linearity:
±1LSB typ, ±1.5LSB max INL
±0.6LSB typ, ±1LSB max DNL
±1mV max Offset
•
•
•
±12LSB typ Gain Error
•
microPower:
DESCRIPTION
10mW at 5V, 250kHz
4mW at 2.7V, 200kHz
2mW at 2.7V, 100kHz
0.2mW at 2.7V, 10kHz
The ADS8326 is a 16-bit, sampling, analog-to-digital
(A/D) converter specified for a supply voltage range
from 2.7V to 5.5V. It requires very little power, even
when operating at the full data rate. At lower data
rates, the high speed of the device enables it to
spend most of its time in the power-down mode. For
example, the average power dissipation is less than
0.2mW at a 10kHz data rate.
•
•
•
MSOP-8 and SON-8 Packages
(SON-8 package same as 3x3 QFN)
16-Bit Upgrade to the 12-Bit ADS7816 and
ADS7822
Pin-Compatible with the ADS7816, ADS7822,
ADS7826, ADS7827, ADS7829, ADS8320, and
ADS8325
The ADS8326 offers excellent linearity and very low
noise and distortion. It also features a synchronous
serial (SPI/SSI-compatible) interface and a differential
input. The reference voltage can be set to any level
•
Serial ( SPI™/SSI) Interface
within the range of 0.1V to VDD
.
Low power and small size make the ADS8326 ideal
for portable and battery-operated systems. It is also a
perfect fit for remote data-acquisition modules,
simultaneous multichannel systems, and isolated
data acquisition. The ADS8326 is available in either
an MSOP-8 and an SON-8 package.
SAR
REF
ADS8326
DOUT
+IN
CDAC
Serial
Interface
DCLOCK
CS/SHDN
-IN
S/H Amp
Comparator
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
SPI is a trademark of Motorola, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2009, Texas Instruments Incorporated
ADS8326
SBAS343C –MAY 2007–REVISED SEPTEMBER 2009.................................................................................................................................................. www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
MAXIMUM
INTEGRAL
LINEARITY
ERROR
NO
MISSING
CODES
ERROR
(LSB)
SPECIFIED
TEMPERATURE
RANGE
TRANSPORT
MEDIA,
QUANTITY
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
(2)
PRODUCT
(LSB)
Tape and Reel,
250
ADS8326IDGKT
ADS8326IDGKR
ADS8326IBDGKT
ADS8326IBDGKR
ADS8326IDRBT
ADS8326IDRBR
ADS8326IBDRBT
ADS8326IBDRBR
ADS8326I
±3
±1.5
±3
16
16
16
16
MSOP-8
MSOP-8
SON-8
DGK
DGK
DRB
DRB
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
D26
D26
D26
D26
Tape and Reel,
2500
Tape and Reel,
250
ADS8326IB
ADS8326I
ADS8326IB
Tape and Reel,
2500
Tape and Reel,
250
Tape and Reel,
2500
Tape and Reel,
250
±1.5
SON-8
Tape and Reel,
2500
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see
the TI website at www.ti.com.
(2) Maximum Integral Linearity Error specifies a 5V power supply and reference voltage.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted).
ADS8326
–0.3 to +7
UNIT
V
Supply voltage, VDD to GND
Analog input voltage(2)
Reference input voltage(2)
Digital input voltage(2)
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–20 to +20
V
V
V
Input current to any pin except supply
Power dissipation
mA
See Dissipation Ratings Table
–40 to +150
Operating virtual junction temperature range, TJ
Operating free-air temperature range, TA
Storage temperature range, TSTG
Lead Temperature 1.6mm (1/16 inch) from case for 10sec
°C
°C
°C
°C
–40 to +85
–65 to +150
+260
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to ground terminal.
2
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Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8326
ADS8326
www.ti.com.................................................................................................................................................. SBAS343C –MAY 2007–REVISED SEPTEMBER 2009
DISSIPATION RATINGS
DERATING
FACTOR ABOVE
TA = +25°C
T
A ≤ +25°C
TA = +70°C
POWER RATING
TA = +85°C
POWER RATING
PACKAGE
DGK
R θ JC
+39.1°C/W
+5°C/W
R θ JA
POWER RATING
+206.3°C/W
+45.8°C/W
4.847mW/°C
3.7mW/°C
606mW
388mW
204mW
315mW
148mW
DRB
370mW
RECOMMENDED OPERATING CONDITIONS
MIN
2.7
4.5
0.1
–0.3
–0.3
0
TYP
5.0
0
MAX
UNIT
V
Supply voltage, GND to VDD
Supply voltage, GND to VDD
Reference input voltage
Low-voltage levels
5V logic levels
3.6
5.5
V
VDD
V
–IN to GND
+IN to GND
+IN – (–IN)
0.5
V
Analog input voltage
VDD + 0.2
VREF
+125
V
V
Operating junction temperature, TJ
–40
°C
ELECTRICAL CHARACTERISTICS: VDD = +5V
At –40°C to +85°C, VREF = +5V, –IN = GND, fSAMPLE = 250kHz, and fDCLOCK = 24 × fSAMPLE, unless otherwise noted.
ADS8326I
TYP
ADS8326IB
TYP
PARAMETER
ANALOG INPUT
TEST CONDITIONS
MIN
MAX
MIN
MAX
UNIT
Full-scale range
FSR +IN – (–IN)
0
VREF
0.5
0
VREF
0.5
V
V
Operating common-mode signal
–0.3
–0.3
–IN = GND, off
5
50
5
50
GΩ
Ω
Input resistance
RON
–IN = GND, on
100
100
Input capacitance
–IN = GND, during sampling
–IN = GND
48
48
pF
nA
pF
Input leakage current
Differential input capacitance
±50
20
±50
20
+IN to –IN, during sampling
FS sinewave, SINAD =
–60dB
Full-power bandwidth
FSBW
500
500
kHz
DC ACCURACY
Resolution
16
16
16
16
Bits
Bits
No missing codes
Integral linearity error
Differential linearity error
Offset error
NMC
INL
–3
±2
±0.5
+3
+2
–1.5
–1
±1
±0.4
±0.5
±0.2
+1.5
+1
LSB
DNL
–1
LSB
VOS
–1.5
±0.75
±0.2
+1.5
–1
+1
mV
Offset error drift
Gain error
TCVOS
GERR
ppm/°C
LSB
–24
+24
–12
+12
Gain error drift
TCGERR
±0.3
30
±0.3
30
ppm/°C
μVRMS
LSB
Noise
Power-supply rejection
SAMPLING DYNAMICS
4.75V ≤ VDD ≤ 5.25V
0.5
0.5
Conversion time
(16 DCLOCKs)
tCONV 24kHz ≤ fDCLOCK ≤ 6MHz
2.667
0.75
666.7
2.667
0.75
666.7
μs
μs
Acquisition time
(4.5 DCLOCKs)
tAQ fDCLOCK = 6MHz
Throughput rate
(22 DCLOCKs)
250
6
250
6
kSPS
MHz
Clock frequency
fDCLOCK
0.024
0.024
Copyright © 2007–2009, Texas Instruments Incorporated
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ADS8326
SBAS343C –MAY 2007–REVISED SEPTEMBER 2009.................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS: VDD = +5V (continued)
At –40°C to +85°C, VREF = +5V, –IN = GND, fSAMPLE = 250kHz, and fDCLOCK = 24 × fSAMPLE, unless otherwise noted.
ADS8326I
TYP
ADS8326IB
TYP
PARAMETER
AC ACCURACY
TEST CONDITIONS
MIN
MAX
MIN
MAX
UNIT
5VPP sinewave at 2kHz
5VPP sinewave at 10kHz
5VPP sinewave at 2kHz
5VPP sinewave at 10kHz
5VPP sinewave at 2kHz
5VPP sinewave at 10kHz
5VPP sinewave at 2kHz
5VPP sinewave at 10kHz
5VPP sinewave at 2kHz
5VPP sinewave at 10kHz
–98
–90
102
94
–99
–91
103
95
dB
dB
dB
dB
dB
dB
dB
dB
Bits
Bits
Total harmonic distortion
THD
SFDR
SNR
Spurious-free dynamic
range
91
91.5
91.5
91
Signal-to-noise ratio
91
90
Signal-to-noise + distortion
Effective number of bits
SINAD
ENOB
87.5
14.69
14.28
88
14.86
14.35
VOLTAGE REFERENCE INPUT
Reference voltage
0.1
VDD
0.1
VDD
V
CS = GND, fSAMPLE = 0Hz
CS = VDD
5
5
5
5
GΩ
GΩ
pF
μA
μA
μA
μA
μA
Reference input resistance
Reference input capacitance
24
24
fS = 250kHz
fS = 200kHz
fS = 100kHz
fS = 10kHz
CS = VDD
170
140
70
220
180
90
170
140
70
220
180
90
Reference input current
11
14
11
14
0.1
0.1
DIGITAL INPUTS(1)
Logic family
CMOS
CMOS
High-level input voltage
Low-level input voltage
Input current
VIH
VIL
0.7 × VDD
–0.3
VDD + 0.3 0.7 × VDD
VDD + 0.3
0.3 × VDD
+50
V
V
0.3 × VDD
+50
–0.3
–50
IIN VI = VDD or GND
CI
–50
nA
pF
Input capacitance
DIGITAL OUTPUTS(1)
Logic family
5
5
CMOS
CMOS
High-level output voltage
Low-level output voltage
VOH VDD = 4.5V, IOH = –100μA
VOL VDD = 4.5V, IOL = 100μA
4.44
–50
4.44
–50
V
V
0.5
0.5
High-impedance state
output current
IOZ CS = VDD, VI = VDD or GND
+50
+50
nA
Output capacitance
Load capacitance
CO
CL
5
5
pF
pF
30
30
Straight
binary
Straight
binary
Data format
(1) Applies for 5.0V nominal supply: VDD (min) = 4.5V and VDD (max) = 5.5V.
4
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Product Folder Link(s): ADS8326
ADS8326
www.ti.com.................................................................................................................................................. SBAS343C –MAY 2007–REVISED SEPTEMBER 2009
ELECTRICAL CHARACTERISTICS: VDD = +2.7V
At –40°C to +85°C, VREF = +2.5V, –IN = GND, fSAMPLE = 200kHz, and fDCLOCK = 24 × fSAMPLE, unless otherwise noted.
ADS8326I
TYP
ADS8326IB
TYP
PARAMETER
ANALOG INPUT
TEST CONDITIONS
MIN
MAX
MIN
MAX
UNIT
Full-scale range
FSR +IN – (–IN)
0
VREF
0.5
0
VREF
0.5
V
V
Operating common-mode signal
–0.3
–0.3
–IN = GND, off
5
100
48
5
100
48
GΩ
Ω
Input resistance
RON
–IN = GND, on
150
150
Input capacitance
–IN = GND, during sampling
–IN = GND
pF
nA
pF
Input leakage current
Differential input capacitance
±50
20
±50
20
+IN to –IN, during sampling
FS sinewave, SINAD =
–60dB
Full-power bandwidth
FSBW
60
60
kHz
DC ACCURACY
Resolution
16
16
16
16
Bits
Bits
No missing codes
Integral linearity error
Differential linearity error
Offset error
NMC
INL
–3
±2
±0.5
±0.75
±0.2
±33
+3
+2
–2.5
–1
±1
±0.4
±0.5
±0.2
±16
±0.3
30
+2.5
+1
LSB
DNL
–1
LSB
VOS
–1.5
+1.5
–1
+1
mV
Offset error drift
Gain error
TCVOS
GERR
ppm/°C
LSB
Gain error drift
TCGERR
±0.3
30
ppm/°C
μVRMS
LSB
Noise
Power-supply rejection
SAMPLING DYNAMICS
2.7V ≤ VDD ≤ 3.6V
0.5
0.5
Conversion time
(16 DCLOCKs)
tCONV 24kHz ≤ fDCLOCK ≤ 4.8MHz
3.333
666.7
3.333
666.7
μs
μs
Acquisition time
(4.5 DCLOCKs)
tAQ fDCLOCK = 4.8MHz
0.9375
0.9375
Throughput rate
(22 DCLOCKs)
200
4.8
200
4.8
kSPS
MHz
Clock frequency
fDCLOCK
0.024
0.024
AC ACCURACY
2.5VPP sinewave at 2kHz
2.5VPP sinewave at 10kHz
2.5VPP sinewave at 2kHz
2.5VPP sinewave at 10kHz
2.5VPP sinewave at 2kHz
2.5VPP sinewave at 10kHz
2.5VPP sinewave at 2kHz
2.5VPP sinewave at 10kHz
2.5VPP sinewave at 2kHz
2.5VPP sinewave at 10kHz
–88
–75
–88.5
–75.5
91.5
78
dB
dB
dB
dB
dB
dB
dB
dB
Bits
Bits
Total harmonic distortion
THD
SFDR
SNR
91
Spurious-free dynamic
range
77.5
86.5
86
87
Signal-to-noise ratio
86.5
85.5
75
85
Signal-to-noise + distortion
Effective number of bits
SINAD
ENOB
74.5
13.86
12.12
13.94
12.20
VOLTAGE REFERENCE INPUT
Reference voltage
0.1
VDD
0.1
VDD
V
CS = GND, fSAMPLE = 0Hz
CS = VDD
5
5
5
5
GΩ
GΩ
pF
Reference input resistance
Reference input capacitance
24
70
25
5
24
70
25
5
fS = 200kHz
fS = 100kHz
fS = 10kHz
CS = VDD
90
33
7
90
33
7
μA
μA
μA
μA
Reference input current
0.1
0.1
Copyright © 2007–2009, Texas Instruments Incorporated
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ADS8326
SBAS343C –MAY 2007–REVISED SEPTEMBER 2009.................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS: VDD = +2.7V (continued)
At –40°C to +85°C, VREF = +2.5V, –IN = GND, fSAMPLE = 200kHz, and fDCLOCK = 24 × fSAMPLE, unless otherwise noted.
ADS8326I
TYP
ADS8326IB
TYP
PARAMETER
DIGITAL INPUTS(1)
TEST CONDITIONS
MIN
MAX
MIN
MAX
UNIT
Logic family
LVCMOS
LVCMOS
High-level input voltage
Low-level input voltage
Input current
VIH VDD = 3.6V
2
–0.3
–50
VDD + 0.3
0.8
2
–0.3
–50
VDD + 0.3
0.8
V
V
VIL VDD = 2.7V
IIN VI = VDD or GND
CI
+50
+50
nA
pF
Input capacitance
DIGITAL OUTPUTS(1)
Logic family
5
5
LVCMOS
LVCMOS
High-level output voltage
Low-level output voltage
VOH VDD = 2.7V, IOH = –100μA
VOL VDD = 2.7V, IOL = 100μA
VDD – 0.2
–50
VDD – 0.2
–50
V
V
0.2
0.2
High-impedance state
output current
IOZ CS = VDD, VI = VDD or GND
+50
+50
nA
Output capacitance
Load capacitance
CO
CL
5
5
pF
pF
30
30
Straight
binary
Straight
binary
Data format
(1) Applies for 3.0V nominal supply: VDD (min) = 2.7V and VDD (max) = 3.6V.
ELECTRICAL CHARACTERISTICS
At –40°C to +85°C, –IN = GND, and fDCLOCK = 24 × fSAMPLE, unless otherwise noted.
ADS8326I
ADS8326IB
TYP
PARAMETER
ANALOG INPUT
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNIT
Low-voltage levels
5V logic levels
2.7
4.5
3.6
5.5
2.7
4.5
3.6
5.5
V
V
Power supply
VDD
IDD
IDD
VDD = 2.7V, fS = 10kHz,
fDCLOCK = 4.8MHz
0.065
0.69
1.38
1.9
0.085
1.0
0.065
0.69
1.38
1.9
0.085
1.0
mA
mA
mA
mA
mA
VDD = 2.7V, fS = 100kHz,
fDCLOCK = 4.8MHz
VDD = 2.7V, fS = 200kHz,
fDCLOCK = 4.8MHz
Operating supply current
Power-down supply current
Power dissipation
2.0
2.0
VDD = 5V, fS = 200kHz,
fDCLOCK = 6MHz
2.7
2.7
VDD = 5V, fS = 250kHz,
fDCLOCK = 6MHz
2.0
3.0
2.0
3.0
VDD = 2.7V
VDD = 5V
0.1
0.2
0.1
0.2
μA
μA
VDD = 2.7V, fS = 10kHz,
fDCLOCK = 4.8MHz
0.18
1.86
3.73
9.5
0.23
2.7
0.18
1.86
3.73
9.5
0.23
2.7
mW
mW
mW
mW
mW
VDD = 2.7V, fS = 100kHz,
fDCLOCK = 4.8MHz
VDD = 2.7V, fS = 200kHz,
fDCLOCK = 4.8MHz
5.4
5.4
VDD = 5V, fS = 200kHz,
fDCLOCK = 6MHz
13.5
15
13.5
15
VDD = 5V, fS = 250kHz,
fDCLOCK = 6MHz
10
10
VDD = 2.7V, CS = VDD
VDD = 5V, CS = VDD
0.3
0.6
0.3
0.6
μW
μW
Power dissipation in power-down
6
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Product Folder Link(s): ADS8326
ADS8326
www.ti.com.................................................................................................................................................. SBAS343C –MAY 2007–REVISED SEPTEMBER 2009
PIN CONFIGURATION
DGK PACKAGE
MSOP-8
(TOP VIEW)
REF
+IN
1
2
3
4
8
7
6
5
VDD
DCLOCK
DOUT
ADS8326
-IN
GND
CS/SHDN
DRB PACKAGE
SON-8
(TOP VIEW)
1
8
VDD
REF
2
3
4
7
DCLOCK
DOUT
+IN
-IN
ADS8326
6
(Thermal Pad)
5
CS/SHDN
GND
(1) The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left
floating. Keep the thermal pad separate from the digital ground, if possible.
PIN ASSIGNMENTS
PIN
I/O
DESCRIPTION
NAME
REF
NO.
1
Analog input
Analog input
Analog input
Reference input
+IN
2
Noninverting input
Inverting analog input
–IN
3
GND
4
Power-supply connection Ground
CS/SHDN
DOUT
5
Digital input
Digital output
Digital input
Chip select when low; Shutdown mode when high.
6
Serial output data word
DCLOCK
VDD
7
Data clock synchronizes the serial data transfer and determines conversion speed.
8
Power-supply connection Power supply
Equivalent Input Circuit (VDD = 5.0V)
VDD
VDD
VDD
C(SAMPLE)
48pF
RON
RON
24pF
50W
50W
ANALOG IN
REF
I/O
GND
GND
GND
Diode Turn-On Voltage: 0.35V
Equivalent Analog Input Circuit
Equivalent Reference Input Circuit
Equivalent Digital Input/Output Circuit
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ADS8326
SBAS343C –MAY 2007–REVISED SEPTEMBER 2009.................................................................................................................................................. www.ti.com
TIMING INFORMATION
tCYC
CS/SHDN
Power Down
Sample
tSUCS
Conversion
DCLOCK
tCSD
Use positive clock edge for data transfer
Hi-Z
Hi-Z
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0(1)
DOUT
0
(MSB)
(LSB)
tSMPL
tCONV
NOTE: (1) A minimum of 22 clock cycles are required for 16-bit conversion; 24 clock cycles are shown.
If CS remains low at the end of conversion, a new data stream is shifted out with LSB-first data followed by zeroes indefinitely.
tCYC
CS/SHDN
DCLOCK
DOUT
tSUCS
Power Down
tCSD
Hi-Z
Hi-Z
(2)
0
B15 B14 BB5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B0 B11 B12 B13 B14 B15
(MSB) (LSB) (MSB)
tCONV
tSMPL
NOTE: (2) After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zeroes indefinitely.
1.4V
90%
10%
3kW
DOUT
DOUT
Test Point
tr
tf
100pF
CLOAD
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
Load Circuit for tdDO, tr, and tf
Test Point
DCLOCK
VDD
tdis Waveform 2, ten
tdis Waveform 1
3kW
DOUT
tdDO
100pF
CLOAD
DOUT
thDO
Voltage Waveforms for DOUT Delay Times, tdDO
Load Circuit for tdis and ten
90%
CS/SHDN
CS/SHDN
DCLOCK
1
4
5
DOUT
Waveform 1(3)
90%
10%
tdis
DOUT
B15
DOUT
Waveform 2(4)
ten
Voltage Waveforms for ten
Voltage Waveforms for tdis
(3) Waveform 1 is for an output with internal conditions such that
the output is high unless disabled by the output control.
(4) Waveform 2 is for an output with internal conditions such that
the output is low unless disabled by the output control.
NOTES:
Figure 1. Timing Diagrams and Test Circuits for the Parameters in Table 1
8
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TIMING INFORMATION (continued)
Table 1. Timing Characteristics
SYMBOL
tSMPL
tCONV
tCYC
tCSD
tSUCS
tHDO
tDIS
DESCRIPTION
MIN
TYP
MAX
UNIT
Analog input sample time
Conversion time
4.5
5.0
DCLOCKs
16
DCLOCKs
Complete cycle time
22
DCLOCKs
CS falling to DCLOCK low
CS falling to DCLOCK rising
DCLOCK falling to current DOUT not valid
CS rising to DOUT tri-state
DCLOCK falling to DOUT enabled
DOUT fall time
0
ns
ns
ns
ns
ns
ns
ns
20
5
15
70
20
5
100
50
tEN
tF
25
tR
DOUT rise time
7
25
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TYPICAL CHARACTERISTICS: VDD = +5V
At TA = +25°C, VDD = +5V, VREF = +5V. fSAMPLE = 250kHz, fCLK = 24 × fSAMPLE, unless otherwise noted.
INTEGRAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs
vs
CODE
CODE
3
2
3
2
1
1
0
0
-1
-2
-3
-1
-2
-3
0000h
4000h
8000h
C000h
FFFFh
0000h
4000h
8000h
C000h
FFFFh
Output Code
Output Code
Figure 2.
Figure 3.
CHANGE IN OFFSET
vs
CHANGE IN GAIN
vs
TEMPERATURE
TEMPERATURE
0.50
0.25
0
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
75
100
75
100
-50
-25
0
25
50
-50
-25
0
25
50
Temperature (°C)
Figure 4.
Temperature (°C)
Figure 5.
10
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TYPICAL CHARACTERISTICS: VDD = +5V (continued)
At TA = +25°C, VDD = +5V, VREF = +5V. fSAMPLE = 250kHz, fCLK = 24 × fSAMPLE, unless otherwise noted.
CHANGE IN OFFSET
vs
CHANGE IN GAIN
vs
COMMON-MODE VOLTAGE
COMMON-MODE VOLTAGE
30
25
20
15
10
5
30
25
20
15
10
5
0
0
-5
-10
-5
-10
0
0.1 0.2 0.3 0.4 0.5 0.6
0
0.1 0.2 0.3 0.4 0.5 0.6
-0.5 -0.4 -0.3 -0.2 -0.1
-0.5 -0.4 -0.3 -0.2 -0.1
VCM (V)
VCM (V)
Figure 6.
Figure 7.
FREQUENCY SPECTRUM
FREQUENCY SPECTRUM
(8192 point FFT, fIN = 1.9836kHz, –0.2dB)
(8192 point FFT, fIN = 9.9792kHz, –0.2dB)
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
25
50
75
100
125
0
25
50
75
100
125
Frequency (kHz)
Frequency (kHz)
Figure 8.
Figure 9.
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TYPICAL CHARACTERISTICS: VDD = +5V (continued)
At TA = +25°C, VDD = +5V, VREF = +5V. fSAMPLE = 250kHz, fCLK = 24 × fSAMPLE, unless otherwise noted.
SIGNAL-TO-NOISE AND
SIGNAL-TO-NOISE + DISTORTION
vs
SPURIOUS-FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
INPUT FREQUENCY
100
95
90
85
80
75
70
65
105
100
95
-105
-100
-95
-90
-85
-80
-75
-70
-65
SNR
SFDR
90
85
SINAD
THD(1)
80
75
70
NOTE: (1) First nine harmonics of the input frequency.
65
100 200
1
10
100 200
1
10
Frequency (kHz)
Frequency (kHz)
Figure 10.
Figure 11.
EFFECTIVE NUMBER OF BITS
CHANGE IN SIGNAL-TO-NOISE + DISTORTION
vs
vs
INPUT FREQUENCY
TEMPERATURE
16.0
15.0
14.0
13.0
12.0
11.0
10.0
0.25
0.20
0.15
0.10
0.05
0
fIN = 1.98364kHz, -0.2dB
-0.05
-0.10
-0.15
-0.20
100 200
75
100
1
10
-50
-25
0
25
50
Frequency (kHz)
Temperature (°C)
Figure 12.
Figure 13.
12
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TYPICAL CHARACTERISTICS: VDD = +5V (continued)
At TA = +25°C, VDD = +5V, VREF = +5V. fSAMPLE = 250kHz, fCLK = 24 × fSAMPLE, unless otherwise noted.
SIGNAL-TO-NOISE + DISTORTION
PEAK-TO-PEAK NOISE FOR A DC INPUT
vs
vs
INPUT LEVEL
REFERENCE VOLTAGE
100
90
80
70
60
50
40
30
20
10
200
100
fIN = 1.98364kHz, -0.2dB
10
1
5
0
0.1
1
-80
-70
-60
-50
-40
-30
-20
-10
Reference Voltage (V)
Input Level (dB)
Figure 14.
Figure 15.
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
TEMPERATURE
SAMPLING RATE
1.84
1.83
1.82
1.81
1.80
1.79
10
1
0.1
0.01
0.001
75
100
250
-50
-25
0
25
50
1
10
100
Temperature (°C)
Sampling Rate (kHz)
Figure 16.
Figure 17.
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TYPICAL CHARACTERISTICS: VDD = +5V (continued)
At TA = +25°C, VDD = +5V, VREF = +5V. fSAMPLE = 250kHz, fCLK = 24 × fSAMPLE, unless otherwise noted.
REFERENCE CURRENT
vs
POWER-DOWN CURRENT
vs
SAMPLING RATE
TEMPERATURE
1000
100
10
30
28
26
24
22
20
18
1
0.1
250
1
10
100
75
100
-50
-25
0
25
50
Sampling Rate (kHz)
Temperature (°C)
Figure 18.
Figure 19.
OUTPUT CODE HISTOGRAM FOR A DC INPUT
(8192 Conversions)
6990
592
610
0
0
0
0
8001 8002
7FFC 7FFD 7FFE 7FFF 8000
Code
Figure 20.
14
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TYPICAL CHARACTERISTICS: VDD = +2.7V
At TA = +25°C, VDD = +2.7V, VREF = +2.5V. fSAMPLE = 200kHz, fCLK = 24 × fSAMPLE, unless otherwise noted.
INTEGRAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs
vs
CODE
CODE
3
2
3
2
1
1
0
0
-1
-2
-3
-1
-2
-3
0000h
4000h
8000h
C000h
FFFFh
0000h
4000h
8000h
C000h
FFFFh
Output Code
Output Code
Figure 21.
Figure 22.
CHANGE IN OFFSET
vs
CHANGE IN GAIN
vs
TEMPERATURE
TEMPERATURE
0.50
0.25
0
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
75
100
75
100
-50
-25
0
25
50
-50
-25
0
25
50
Temperature (°C)
Figure 23.
Temperature (°C)
Figure 24.
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TYPICAL CHARACTERISTICS: VDD = +2.7V (continued)
At TA = +25°C, VDD = +2.7V, VREF = +2.5V. fSAMPLE = 200kHz, fCLK = 24 × fSAMPLE, unless otherwise noted.
CHANGE IN OFFSET
vs
CHANGE IN GAIN
vs
COMMON-MODE VOLTAGE
COMMON-MODE VOLTAGE
30
25
20
15
10
5
30
25
20
15
10
5
0
0
-5
-10
-5
-10
0
0.1 0.2 0.3 0.4 0.5 0.6
0
0.1 0.2 0.3 0.4 0.5 0.6
-0.5 -0.4 -0.3 -0.2 -0.1
-0.5 -0.4 -0.3 -0.2 -0.1
VCM (V)
VCM (V)
Figure 25.
Figure 26.
FREQUENCY SPECTRUM
FREQUENCY SPECTRUM
(8192 point FFT, fIN = 1.9775kHz, –0.2dB)
(8192 point FFT, fIN = 9.9854kHz, –0.2dB)
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
10 20 30 40 50 60 70 80 90 100
Frequency (kHz)
0
10 20 30 40 50 60 70 80 90 100
Frequency (kHz)
Figure 27.
Figure 28.
16
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TYPICAL CHARACTERISTICS: VDD = +2.7V (continued)
At TA = +25°C, VDD = +2.7V, VREF = +2.5V. fSAMPLE = 200kHz, fCLK = 24 × fSAMPLE, unless otherwise noted.
SIGNAL-TO-NOISE AND
SIGNAL-TO-NOISE + DISTORTION
vs
SPURIOUS-FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
INPUT FREQUENCY
100
95
90
85
80
75
70
65
60
55
50
45
40
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
95
90
85
80
75
70
65
60
55
50
55
SNR
SFDR
SINAD
THD(1)
NOTE: (1) First nine harmonics of the input frequency.
100 200
100 200
1
10
1
10
Frequency (kHz)
Frequency (kHz)
Figure 29.
Figure 30.
EFFECTIVE NUMBER OF BITS
CHANGE IN SIGNAL-TO-NOISE + DISTORTION
vs
vs
INPUT FREQUENCY
TEMPERATURE
15
14
13
12
11
10
9
0.4
fIN = 1.97754kHz, -0.2dB
0.2
0
-0.2
-0.4
-0.6
-0.8
8
7
100 200
75
100
1
10
-50
-25
0
25
50
Frequency (kHz)
Temperature (°C)
Figure 31.
Figure 32.
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TYPICAL CHARACTERISTICS: VDD = +2.7V (continued)
At TA = +25°C, VDD = +2.7V, VREF = +2.5V. fSAMPLE = 200kHz, fCLK = 24 × fSAMPLE, unless otherwise noted.
SIGNAL-TO-NOISE + DISTORTION
SUPPLY CURRENT
vs
vs
INPUT LEVEL
TEMPERATURE
100
90
80
70
60
50
40
30
20
10
1.38
1.37
1.36
1.35
1.34
1.33
1.32
1.31
1.30
fIN = 1.97754kHz, -0.2dB
0
75
100
-80
-70
-60
-50
-40
-30
-20
-10
-50
-25
0
25
50
Input Level (dB)
Temperature (°C)
Figure 33.
Figure 34.
SUPPLY CURRENT
vs
REFERENCE CURRENT
vs
SAMPLING RATE
SAMPLING RATE
10
1000
100
10
1
0.1
0.01
1
0.001
0.0001
0.1
100 200
100 200
1
10
1
10
Sampling Rate (kHz)
Sampling Rate (kHz)
Figure 35.
Figure 36.
OUTPUT CODE HISTOGRAM FOR A DC INPUT
(8192 Conversions)
4791
1665
1643
40
0
0
53
8001 8002
7FFC 7FFD 7FFE 7FFF
8000
Code
Figure 37.
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THEORY OF OPERATION
The ADS8326 is a classic Successive Approximation
Register (SAR) Analog-to-Digital (A/D) converter. The
architecture is based on capacitive redistribution that
inherently includes a sample-and-hold function. The
converter is fabricated on a 0.6μ CMOS process. The
architecture and process allow the ADS8326 to
acquire and convert an analog signal at up to
250,000 conversions per second while consuming
The external clock can vary between 24kHz (1kHz
throughput) and 6.0MHz (250kHz throughput). The
duty cycle of the clock is essentially unimportant, as
long as the minimum high and low times are at least
200ns (VDD = 4.75V or greater). The minimum clock
frequency is set by the leakage on the internal
capacitors to the ADS8326.
The analog input is provided to two input pins: +IN
less than 10mW from VDD
.
and –IN. When
a conversion is initiated, the
Differential linearity
for
the
ADS8326
is
differential input on these pins is sampled on the
internal capacitor array. While a conversion is in
progress, both inputs are disconnected from any
internal function.
factory-adjusted via a package-level trim procedure.
The state of the trim elements is stored in non-volatile
memory and is continuously updated after each
acquisition cycle, just prior to the start of the
successive approximation operation. This process
ensures that one complete conversion cycle always
returns the part to its factory-adjusted state in the
event of a power interruption.
The digital result of the conversion is clocked out by
the DCLOCK input and is provided serially (most
significant bit first) on the DOUT pin.
The digital data that is provided on the DOUT pin is for
the conversion currently in progress–there is no
pipeline delay. It is possible to continue to clock the
ADS8326 after the conversion is complete and to
obtain the serial data least significant bit first. See the
Timing Information section for more information.
The ADS8326 requires an external reference, an
external clock, and a single power source (VDD). The
external reference can be any voltage between 0.1V
and VDD. The value of the reference voltage directly
sets the range of the analog input. The reference
input current depends on the conversion rate of the
ADS8326.
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ANALOG INPUT
0V to +VREF
The analog input of ADS8326 is differential. The +IN
and –IN input pins allow for a differential input signal.
ADS8326
Peak-to-Peak
The amplitude of the input is the difference between
the +IN and –IN input, or (+IN) – (–IN). Unlike some
Common-Mode
Voltage
converters of this type, the –IN input is not resampled
later in the conversion cycle. When the converter
goes into Hold mode or conversion, the voltage
difference between +IN and –IN is captured on the
internal capacitor array.
Figure 38. Methods of Driving the ADS8326
The range of the –IN input is limited to –0.3V to
+0.5V. As a result of this limitation, the differential
1
VDD = 5V
input could be used to reject signals that are common
to both inputs in the specified range. Thus, the –IN
0.5
input is best used to sense a remote signal ground
that may move slightly with respect to the local
0
ground potential.
-0.3
The general method for driving the analog input of the
ADS8326 is shown in Figure 38 and Figure 40. The
–IN input is held at the common-mode voltage. The
-1
+IN input swings from –IN (or common-mode voltage)
2
2.5
3
4
5
6
4.8
to –IN + VREF (or common-mode voltage + VREF ),
and the peak-to-peak amplitude is +VREF . The value
of VREF determines the range over which the
common-mode voltage may vary, as shown in
Figure 39. Figure 6 and Figure 7 (+5V), and
Figure 25 and Figure 26 (+2.7V) illustrate the typical
change in gain and offset as a function of the
common-mode voltage applied to the –IN pin.
VREF (V)
Figure 39. +IN Analog Input: Common-Mode
Voltage Range vs VREF
+IN
Common-Mode Voltage + VREF
+VREF
t
Common-Mode Voltage
-IN = Common-Mode Voltage
NOTE: The maximum differential voltage between +IN and –IN of the ADS8326 is VREF. See Figure 39 for a further
explanation of the common-mode voltage range for differential inputs.
Figure 40. Differential Input Mode of the ADS8326
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The input current required by the analog inputs
Single-Ended
depends on a number of factors: sample rate, input
voltage, source impedance, and power-down mode.
48pF
10W
50W
Essentially, the current into the ADS8326 charges the
internal capacitor array during the sample period.
After this capacitance has been fully charged, there is
no further input current. The source of the analog
input voltage must be able to charge the input
capacitance (48pF) to a 16-bit settling level within 4.5
clock cycles (0.750μs). When the converter goes into
Hold mode, or while it is in Power-Down mode, the
input impedance is greater than 1GΩ.
+IN
OPA365
1000pF
ADS8326
48pF
50W
-IN
Differential
Care must be taken regarding the absolute analog
input voltage. To maintain the linearity of the
converter, the –IN input should not drop below GND –
0.3V or exceed GND + 0.5V. The +IN input should
always remain within the range of GND – 0.3V to VDD
+ 0.3V, or –IN to –IN + VREF , whichever limit is
reached first. Outside of these ranges, the converter
linearity may not meet specifications. To minimize
noise, low bandwidth input signals with low-pass
filters should be used. In each case, care should be
taken to ensure that the output impedance of the
sources driving the +IN and –IN inputs are matched.
Often, a small capacitor (20pF) between the positive
and negative inputs helps to match their impedance.
To obtain maximum performance from the ADS8326,
the input circuit from Figure 41 is recommended.
48pF
10W
50W
+IN
OPA365
1000pF
ADS8326
1nF
48pF
10W
50W
-IN
OPA365
1000pF
Figure 41. Single-Ended and Differential Methods
of Interfacing the ADS8326
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REFERENCE INPUT
ADS8326
The external reference sets the analog input range.
The ADS8326 operates with a reference in the range
24pF
50W
VREF
OPA350
of 0.1V to VDD
. There are several important
implications to this.
47mF
As the reference voltage is reduced, the analog
voltage weight of each digital output code is reduced.
This is often referred to as the least significant bit
(LSB) size and is equal to the reference voltage
divided by 65,536. This means that any offset or gain
error inherent in the A/D converter will appear to
increase (in terms of LSB size) as the reference
voltage is reduced. For a reference voltage of 2.5V,
the value of the LSB is 38.15μV, and for a reference
voltage of 5V, the LSB is 76.3μV.
Figure 42. Input Reference Circuit and Interface
When the ADS8326 is in Power-Down mode, the
input resistance of the reference pin will have a value
of 5GΩ. Since the input capacitors must be
recharged before the next conversion starts, an
operational
amplifier
with
good
dynamic
characteristics must be used to buffer the reference
input.
The noise inherent in the converter will also appear to
increase with a lower LSB size. With a 5V reference,
the internal noise of the converter typically contributes
only 1.5LSB peak-to-peak of potential error to the
output code. When the external reference is 2.5V, the
potential error contribution from the internal noise will
be two times larger (3LSB). The errors arising from
the internal noise are Gaussian in nature and can be
reduced by averaging consecutive conversion results.
Noise
The transition noise of the ADS8326 itself is
extremely low, as shown in Figure 20 (+5V) and
Figure 37 (+2.7V); it is much lower than competing
A/D converters. These histograms were generated by
applying a low-noise DC input and initiating 8192
conversions. The digital output of the A/D converter
will vary in output code because of the internal noise
of the ADS8326. This is true for all 16-bit, SAR-type
A/D converters. Using a histogram to plot the output
codes, the distribution should appear bell-shaped with
the peak of the bell curve representing the nominal
code for the input value. The ±1σ, ±2σ, and ±3σ
distributions will represent 68.3%, 95.5%, and 99.7%,
respectively, of all codes. The transition noise can be
calculated by dividing the number of codes measured
by 6, which yields the ±3σ distribution, or 99.7%, of
all codes. Statistically, up to three codes could fall
outside the distribution when executing 1000
conversions. The ADS8326, with < 3 output codes for
the ±3σ distribution, yields < ±0.5LSB of transition
noise. Remember, to achieve this low-noise
performance, the peak-to-peak noise of the input
signal and reference must be < 50μV.
For more information regarding noise, see Figure 15,
Peak-to-Peak Noise for a DC Input vs Reference
Voltage. Note that the Effective Number Of Bits
(ENOB) figure is calculated based on the converter
signal-to-(noise + distortion) ratio with a 1kHz, 0dB
input signal. SINAD is related to ENOB as follows:
SINAD = 6.02 × ENOB + 1.76
With lower reference voltages, extra care should be
taken to provide a clean layout including adequate
bypassing,
a clean power supply, a low-noise
reference, and a low-noise input signal. Due to the
lower LSB size, the converter is also more sensitive
to external sources of error, such as nearby digital
signals and electromagnetic interference.
The equivalent input circuit for the reference voltage
is presented in Figure 42. During the conversion
process, an equivalent capacitor of 24pF is switched
on. To obtain optimum performance from the
ADS8326, special care must be taken in designing
the interface circuit to the reference input pin. To
ensure a stable reference voltage, a 47μF tantalum
capacitor with low ESR should be connected as close
as possible to the input pin. If a high output
impedance reference source is used, an additional
operational amplifier with a current-limiting resistor
must be placed in front of the capacitors.
Averaging
The noise of the A/D converter can be compensated
by averaging the digital codes. By averaging
conversion results, transition noise is reduced by a
factor of 1/√n , where n is the number of averages.
For example, averaging four conversion results
reduces the transition noise from ±0.5LSB to
±0.25LSB. Averaging should only be used for input
signals with frequencies near DC.
For AC signals, a digital filter can be used to
low-pass filter and decimate the output codes. This
works in a similar manner to averaging; for every
decimation by 2, the signal-to-noise ratio improves by
3dB.
22
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Product Folder Link(s): ADS8326
ADS8326
www.ti.com.................................................................................................................................................. SBAS343C –MAY 2007–REVISED SEPTEMBER 2009
DIGITAL INTERFACE
Signal Levels
A falling CS signal initiates the conversion and data
transfer. The first 4.5 to 5.0 clock periods of the
conversion cycle are used to sample the input signal.
After the fifth falling DCLOCK edge, DOUT is enabled
and will output a low value for one clock period. For
the next 16 DCLOCK periods, DOUT will output the
conversion result, most significant bit first. After the
least significant bit (B0) has been output, subsequent
clocks will repeat the output data, but in a least
significant bit first format.
The ADS8326 has a wide range of power-supply
voltage. The A/D converter, as well as the digital
interface circuit, is designed to accept and operate
from 2.7V up to 5.5V. This voltage range will
accommodate different logic levels. When the
ADS8326 power-supply voltage is in the range of
4.5V to 5.5V (5V logic level), the ADS8326 can be
connected directly to another 5V, CMOS-integrated
circuit. When the ADS8326 power-supply voltage is in
the range of 2.7V to 3.6V (3V logic level), the
ADS8326 can be connected directly to another 3.3V
LVCMOS integrated circuit.
After the most significant bit (B15) has been
repeated, DOUT will tri-state. Subsequent clocks will
have no effect on the converter. A new conversion is
initiated only when CS has been taken high and
returned low.
Serial Interface
Data Format
The ADS8326 communicates with microprocessors
and other digital systems via a synchronous 3-wire
serial interface, as illustrated in the Timing
The output data from the ADS8326 is in Straight
Binary format, as shown in Figure 43. This figure
represents the ideal output code for a given input
voltage and does not include the effects of offset,
gain error, or noise.
Information
section.
The
DCLOCK
signal
synchronizes the data transfer, with each bit being
transmitted on the falling edge of DCLOCK. Most
receiving systems will capture the bitstream on the
rising edge of DCLOCK. However, if the minimum
hold time for DOUT is acceptable, the system can use
the falling edge of DCLOCK to capture each bit.
Copyright © 2007–2009, Texas Instruments Incorporated
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Product Folder Link(s): ADS8326
ADS8326
SBAS343C –MAY 2007–REVISED SEPTEMBER 2009.................................................................................................................................................. www.ti.com
Straight Binary
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
65535
65534
65533
1000 0000 0000 0001
1000 0000 0000 0000
32769
32768
32767
0111 1111 1111 1111
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
2
1
0
2.499962V
VZ = VCM = 0V
2.500038V
VFS = VCM + VREF = 5V
FS - 1LSB = 4.999924V
4.999847V
1LSB = 76.29mV
38.15mV
76.29mV
152.58mV
V
VMS = VCM + VREF/2 = 2.5V
Unipolar Analog Input Voltage
VCM = 0V
VREF = 5V
16-BIT
Straight Binary Output
VZ = 0000h
Unipolar Analog Input
Zero Code
VCODE = VCM
Midscale Code
Full- Scale Code
VMS = 8000h
VCODE = VCM + VREF/2
VCODE = (VCM + VREF) - 1LSB
VFS = FFFFh
Figure 43. Ideal Conversion Characteristics (Conditions: VCM = 0V, VREF = 5V)
24
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Product Folder Link(s): ADS8326
ADS8326
www.ti.com.................................................................................................................................................. SBAS343C –MAY 2007–REVISED SEPTEMBER 2009
Short Cycling
POWER DISSIPATION
Another way to save power is to use the CS signal to
short-cycle the conversion. The ADS8326 places the
latest data bit on the DOUT line as it is generated;
therefore, the converter can easily be short-cycled.
This term means that the conversion can be
terminated at any time. For example, if only 14 bits of
the conversion result are needed, then the conversion
can be terminated (by pulling CS high) after the 14th
bit has been clocked out.
The architecture of the converter, the semiconductor
fabrication process, and a careful design allow the
ADS8326 to convert at up to a 250kHz rate while
requiring very little power. However, for the absolute
lowest power dissipation, there are several things to
keep in mind.
The power dissipation of the ADS8326 scales directly
with conversion rate. Therefore, the first step to
achieving the lowest power dissipation is to find the
lowest conversion rate that will satisfy the
requirements of the system.
This technique can also be used to lower the power
dissipation (or to increase the conversion rate) in
those applications where an analog signal is being
monitored until some condition becomes true. For
example, if the signal is outside a predetermined
range, the full 16-bit conversion result may not be
needed. If so, the conversion can be terminated after
the first n bits, where n might be as low as 3 or 4.
This results in lower power dissipation in both the
converter and the rest of the system because they
spend more time in Power-Down mode.
In addition, the ADS8326 goes into Power-Down
mode under two conditions: when the conversion is
complete and whenever CS is high (see the Timing
Information section). Ideally, each conversion should
occur as quickly as possible, preferably at a 6.0MHz
clock rate. This way, the converter spends the
longest possible time in Power-Down mode. This is
very important because the converter not only uses
power on each DCLOCK transition (as is typical for
digital CMOS components), but also uses some
current for the analog circuitry, such as the
comparator. The analog section dissipates power
continuously until Power-Down mode is entered.
POWER-ON RESET
The ADS8326 bias circuit is self-starting. There may
be a static current (approximately 1.5mA with VDD
=
5V) after power-on, unless the circuit is powered
down. It is recommended to run a single test
conversion (configured the same as any regular
conversion) after the power supply reaches at least
2.4V to ensure the device is put into power-down
mode.
Figure 17 and Figure 18 (+5V), and Figure 35 and
Figure 36 illustrate the current consumption of the
ADS8326 versus sample rate. For these graphs, the
converter is clocked at maximum speed regardless of
the sample rate. CS is held high during the remaining
sample period.
There is an important distinction between the
power-down mode that is entered after a conversion
is complete and the full power-down mode that is
enabled when CS is high. CS low will only shut down
the analog section. The digital section is completely
shut down only when CS is high. Thus, if CS is left
low at the end of a conversion, and the converter is
continually clocked, the power consumption will not
be as low as when CS is high.
Copyright © 2007–2009, Texas Instruments Incorporated
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Product Folder Link(s): ADS8326
ADS8326
SBAS343C –MAY 2007–REVISED SEPTEMBER 2009.................................................................................................................................................. www.ti.com
LAYOUT
resistor can help in this case). Keep in mind that
while the ADS8326 draws very little current from the
reference on average, there are still instantaneous
current demands placed on the external input and
reference circuitry.
For optimum performance, care should be taken with
the physical layout of the ADS8326 circuitry. This is
particularly true if the reference voltage is low and/or
the conversion rate is high. At a 250kHz conversion
rate, the ADS8326 makes a bit decision every 167ns.
That is, for each subsequent bit decision, the digital
output must be updated with the results of the last bit
decision, the capacitor array appropriately switched
and charged, and the input to the comparator settled
to a 16-bit level, all within one clock cycle.
Texas Instruments' OPA365 op amp provides
optimum performance for buffering the signal inputs;
the OPA350 can be used to effectively buffer the
reference input.
Also, keep in mind that the ADS8326 offers no
inherent rejection of noise or voltage variation in
regards to the reference input. This is of particular
concern when the reference input is tied to the power
supply. Any noise and ripple from the supply will
appear directly in the digital results. While
high-frequency noise can be filtered out, as described
in the previous paragraph, voltage variation resulting
from the line frequency (50Hz or 60Hz) can be
difficult to remove.
The basic SAR architecture is sensitive to spikes on
the power supply, reference, and ground connections
that occur just prior to latching the comparator output.
Thus, during any single conversion for an n-bit SAR
converter, there are n windows in which large
external transient voltages can easily affect the
conversion result. Such spikes might originate from
switching power supplies, digital logic, and
high-power devices, to name a few potential sources.
This particular source of error can be very difficult to
track down if the glitch is almost synchronous to the
converter DCLOCK signal because the phase
difference between the two changes with time and
temperature, causing sporadic misoperation.
The GND pin on the ADS8326 should be placed on a
clean ground point. In many cases, this will be the
analog ground. Avoid connecting the GND pin too
close to the grounding point for a microprocessor,
microcontroller, or digital signal processor. If needed,
run a ground trace directly from the converter to the
power-supply connection point. The ideal layout will
include an analog ground plane for the converter and
associated analog circuitry.
With this in mind, power to the ADS8326 should be
clean and well-bypassed. A 0.1μF ceramic bypass
capacitor should be placed as close as possible to
the ADS8326 package. In addition, a 1μF to 10μF
capacitor and a 5Ω or 10Ω series resistor may be
used to low-pass filter a noisy supply.
The reference should be similarly bypassed with a
47μF capacitor. Again, a series resistor and large
capacitor can be used to low-pass filter the reference
voltage. If the reference voltage originates from an op
amp, make sure that the op amp can drive the
bypass capacitor without oscillation (the series
26
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Product Folder Link(s): ADS8326
ADS8326
www.ti.com.................................................................................................................................................. SBAS343C –MAY 2007–REVISED SEPTEMBER 2009
APPLICATION CIRCUITS
high-frequency noise from the supply itself. The exact
values should be picked such that the filter provides
adequate rejection of noise. Operational amplifiers
and voltage reference are connected to analog power
Figure 44 and Figure 45 show two examples of a
basic data acquisition system. The ADS8326 input
range is connected to 2.5V or 4.096V. The 5Ω
resistor and 1μF to 10μF capacitor filters the
supply, AVDD
.
microcontroller noise on the supply, as well as any
DVDD
2.7V to 3.6V
+
0.1mF
10mF
AVDD
5W
2.7V to 5V
REF3225
REF
OPA350
10W
VDD
+
IN
OUT
47mF
0.1mF
10mF
2.2mF
GND
0.47mF
ADS8326
DSP
10W
TMS320C6xx
or
+IN
OPA365
TMS320C5xx
or
VCM + (0V to 2.5V)
1000pF
CS
TMS320C2xx
1nF
DOUT
DCLOCK
GND
10W
-IN
GND
OPA365
VCM
1000pF
Figure 44. Basic Data Acquisition System: Example 1
DVDD
4.5V to 5.5V
+
0.1mF
10mF
5W
AVDD
4.3V to 5.5V
REF3240
OUT
REF
OPA350
10W
VDD
+
IN
0.1mF
10mF
47mF
2.2mF
GND
0.47mF
ADS8326
10W
Microcontroller
or
DSP
+IN
OPA365
0V to 4.096V
1000pF
CS
DOUT
DCLOCK
GND
-IN
GND
Figure 45. Basic Data Acquisition System: Example 2
Copyright © 2007–2009, Texas Instruments Incorporated
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Product Folder Link(s): ADS8326
ADS8326
SBAS343C –MAY 2007–REVISED SEPTEMBER 2009.................................................................................................................................................. www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May, 2008) to Revision C ..................................................................................................... Page
•
•
•
•
Released SON-8 package; changed statements regarding SON-8 package availability ..................................................... 1
Deleted footnote about SON-8 package availability ............................................................................................................. 2
Deleted footnote about SON-8 package availability ............................................................................................................. 3
Deleted footnote about SON-8 package availability ............................................................................................................. 7
Changes from Revision A (August, 2007) to Revision B ............................................................................................... Page
•
•
•
Changed SON-8 package availability to Q3, 2008 ............................................................................................................... 1
Changed y-axis unit in Figure 35 from μA to mA ............................................................................................................... 18
Added Power-On Reset section ......................................................................................................................................... 25
28
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Product Folder Link(s): ADS8326
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS8326IBDGKR
ADS8326IBDGKT
ADS8326IBDGKTG4
ADS8326IBDRBR
ADS8326IBDRBT
ADS8326IDGKR
ADS8326IDGKT
ADS8326IDRBR
ADS8326IDRBT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
VSSOP
SON
DGK
DGK
DGK
DRB
DRB
DGK
DGK
DRB
DRB
8
8
8
8
8
8
8
8
8
2500 RoHS & Green
Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
D26
D26
D26
D26
D26
D26
D26
D26
D26
250
250
RoHS & Green
RoHS & Green
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
SON
VSSOP
VSSOP
SON
SON
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS8326IBDRBR
ADS8326IDRBR
SON
SON
DRB
DRB
8
8
3000
3000
330.0
330.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS8326IBDRBR
ADS8326IDRBR
SON
SON
DRB
DRB
8
8
3000
3000
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
DRB0008B
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
1.65 0.05
(0.2) TYP
4
5
2X
1.95
2.4 0.05
8
1
6X 0.65
0.35
0.25
8X
PIN 1 ID
0.1
C A B
C
0.5
0.3
8X
(OPTIONAL)
0.05
4218876/A 12/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRB0008B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
SYMM
8X (0.6)
1
8
8X (0.3)
(2.4)
(0.95)
6X (0.65)
4
5
(R0.05) TYP
(0.575)
(2.8)
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218876/A 12/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRB0008B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
METAL
TYP
8X (0.6)
8X (0.3)
1
8
(0.63)
SYMM
(1.06)
6X (0.65)
5
4
(R0.05) TYP
(1.47)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
81% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218876/A 12/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
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Copyright © 2022, Texas Instruments Incorporated
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