ADS8331_15 [TI]
Low-Power, 16-Bit, 500-kSPS, 4-/8-Channel Unipolar Input Analog-to-Digital Converters;
| 型号： | ADS8331_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Low-Power, 16-Bit, 500-kSPS, 4-/8-Channel Unipolar Input Analog-to-Digital Converters |
| 文件： | 总45页 (文件大小：977K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS8331
ADS8332
www.ti.com
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
Low-Power, 16-Bit, 500kSPS, 4-/8-Channel Unipolar Input
ANALOG-TO-DIGITAL CONVERTERS with Serial Interface
Check for Samples: ADS8331, ADS8332
1
FEATURES
DESCRIPTION
234
•
Low-Power, Flexible Supply Range:
The ADS8331 is
a
low-power, 16-bit, 500k
samples-per-second (SPS) analog-to-digital converter
(ADC) with a unipolar, 4-to-1 multiplexer (mux) input.
–
–
2.7V to 5.5V Analog Supply
8.7mW (250kSPS in Auto-Nap Mode,
VA = 2.7V, VBD = 1.65V)
The device includes
a
16-bit capacitor-based
successive approximation register (SAR) ADC with
inherent sample and hold.
–
14.2mW (500kSPS, VA = 2.7V, VBD = 1.65V)
•
Up to 500kSPS Sampling Rate
Excellent DC Performance:
The ADS8332 is based on the same core and
includes a unipolar 8-to-1 input mux. Both devices
offer a high-speed, wide-voltage serial interface and
are capable of daisy-chain operation when multiple
converters are used.
•
–
–
–
±1.2 LSB Typ, ±2 LSB Max INL at 2.7V
±0.6 LSB Typ, –1.0/1.5 LSB Max DNL at 2.7V
16-Bit NMC Over Temperature
These converters are available in 24-pin, 4x4 QFN
and 24-pin TSSOP packages and are fully specified
for operation over the industrial –40°C to +85°C
temperature range.
•
•
Excellent AC Performance at 5V, fIN = 1kHz:
91.5dB SNR, 101dB SFDR, –100dB THD
Flexible Analog Input Arrangement:
–
–
–
On-Chip 4-/8-Channel Mux with Breakout
Auto/Manual Channel Select and Trigger
Low-Power, High-Speed, SAR Converter Family
RESOLUTION/TYPE CHANNELS 500kSPS
1MHz
ADS8329
ADS8330
—
•
Other Hardware Features:
1
2
4
8
1
2
4
8
1
2
ADS8327
ADS8328
ADS8331
ADS8332
—
–
–
–
–
–
–
On-Chip Conversion Clock (CCLK)
Software/Hardware Reset
16-Bit Pseudo-Diff
14-Bit Pseudo-Diff
—
Programmable Status/Polarity EOC/INT
Daisy-Chain Mode
ADS7279
ADS7280
—
—
Global CONVST (Independent of CS)
ADS7231
ADS7232
—
Deep, Nap, and Auto-Nap Powerdown
Modes
—
ADS7229
ADS7230
–
–
–
SPI™/DSP Compatible Serial Interface
Separate I/O Supply: 1.65V to VA
SCLK up to 40MHz (VA = VBD = 5V)
12-Bit Pseudo-Diff
—
BLANKSPACE
•
24-Pin 4x4 QFN and 24-Pin TSSOP Packages
Functional Block Diagram
MUXOUT
ADCIN
Output
Latch
and
3-State
Driver
APPLICATIONS
SDO
SAR
M
U
X
IN[0:3]
or
IN[0:7]
•
•
•
•
•
•
•
Communications
+
_
CDAC
FS/CS
Transducer Interfaces
Medical Instruments
Magnetometers
Industrial Process Control
Data Acquisition Systems
Automatic Test Equipment
Comparator
SCLK
SDI
Conversion
and
Control
Logic
COM
REF+
REF-
CONVST
EOC/INT/CDI
RESET
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
TMS320 is a trademark of Texas Instruments.
SPI is a trademark of Motorola, Inc..
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
ADS8331
ADS8332
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or visit the device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range, unless otherwise noted.(1)
ADS8331, ADS8332
–0.3 to VA + 0.3
–0.3 to 0.3
UNIT
V
INX, MUXOUT, ADCIN, REF+ to AGND
COM, REF– to AGND
VA to AGND
Voltage
V
–0.3 to 7
V
Voltage range
VBD to DGND
–0.3 to 7
V
AGND to DGND
–0.3 to 0.3
V
Digital input voltage to DGND
–0.3 to VBD + 0.3
–0.3 to VBD + 0.3
–40 to +85
V
Digital output voltage to DGND
V
Operating free-air temperature range, (TA)
°C
°C
°C
W
Storage temperature range, (TSTG
Junction temperature (TJ Max)
)
–65 to +150
+150
Power dissipation
(TJMax – TA)/qJA
47
4x4 QFN-24
Package
qJA thermal impedance
Power dissipation
°C/W
W
(TJMax – TA)/qJA
47
TSSOP-24
Package
qJA thermal impedance
°C/W
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2
Submit Documentation Feedback
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
www.ti.com
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
ELECTRICAL CHARACTERISTICS: VA = 2.7V
At TA = –40°C to +85°C, VA = 2.7V, VBD = 1.65V to 2.7V, VREF = 2.5V, and fSAMPLE = 500kSPS, unless otherwise noted.
ADS8331I, ADS8332I
ADS8331IB, ADS8332IB
PARAMETER
ANALOG INPUT
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
(1)
Full-scale input voltage
INX – COM, ADCIN – COM
INX, ADCIN
0
AGND – 0.2
AGND – 0.2
VREF
0
VREF
VA + 0.2
AGND + 0.2
45
V
V
VA + 0.2 AGND – 0.2
AGND + 0.2 AGND – 0.2
45
Absolute input voltage
COM
V
Input capacitance
ADCIN
40
±1
40
±1
pF
nA
Input leakage current
Unselected ADC input
SYSTEM PERFORMANCE
Resolution
16
16
Bits
Bits
LSB(2)
No missing codes
Integral linearity
Differential linearity
Offset error(3)
16
–3
–1
16
INL
DNL
EO
±2
3
2
–2
–1
±1.2
±0.6
2
±0.6
1.5 LSB(2)
–0.5 ±0.15
0.5
–0.5 ±0.15
0.5
mV
PPM/°C
mV
Offset error drift
Offset error matching
Gain error
±1
±1
–0.2
–0.25 –0.06
±0.4
+0.2
0.25
–0.2
–0.25 –0.06
±0.4
+0.2
EG
0.25 %FSR
PPM/°C
Gain error drift
Gain error matching
Transition noise
–0.003
28
0.003
–0.003
28
0.003 %FSR
mV RMS
PSRR
Power-supply rejection ratio
74
74
dB
SAMPLING DYNAMICS
tCONV
Conversion time
Acquisition time
Throughput rate
18
18
CCLK
CCLK
CCLK
tSAMPLE1
tSAMPLE2
Manual-Trigger mode
Auto-Trigger mode
3
3
3
3
500
500
kSPS
DYNAMIC CHARACTERISTICS
VIN = 2.5VPP at 1kHz
VIN = 2.5VPP at 10kHz
VIN = 2.5VPP at 1kHz
VIN = 2.5VPP at 10kHz
VIN = 2.5VPP at 1kHz
VIN = 2.5VPP at 10kHz
VIN = 2.5VPP at 1kHz
VIN = 2.5VPP at 10kHz
VIN = 2.5VPP at 1kHz
VIN = 2.5VPP at 100kHz
–101
–95
88
–101
–95
89
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
(4)
THD
Total harmonic distortion
Signal-to-noise ratio
SNR
86.5
87.5
86
87.5
88.5
87
SINAD
SFDR
Signal-to-noise + distortion
Spurious-free dynamic range
Crosstalk
103
98
103
98
125
108
125
108
INX – COM with MUXOUT
tied to ADCIN
17
30
17
30
MHz
MHz
–3dB small-signal bandwidth
ADCIN – COM
(1) Ideal input span; does not include gain or offset error.
(2) LSB means least significant bit.
(3) Measured relative to an ideal full-scale input (INX – COM) of 2.5V when VA = 2.7V.
(4) Calculated on the first nine harmonics of the input frequency.
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
www.ti.com
ELECTRICAL CHARACTERISTICS: VA = 2.7V (continued)
At TA = –40°C to +85°C, VA = 2.7V, VBD = 1.65V to 2.7V, VREF = 2.5V, and fSAMPLE = 500kSPS, unless otherwise noted.
ADS8331I, ADS8332I
ADS8331IB, ADS8332IB
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
CLOCK
Internal conversion clock
frequency
10.5
11
12.2
25
10.5
11
12.2
25
MHz
MHz
MHz
Used as I/O clock only
SCLK external serial clock
Used as both I/O clock and
conversion clock
1
21
1
21
EXTERNAL VOLTAGE REFERENCE INPUT
Input
(REF+) – (REF–)
(REF–) – AGND
1.2
2.525
0.1
1.2
2.525
0.1
V
V
VREF
reference
range(5)
–0.1
–0.1
(6)
Resistance
Reference input
20
20
kΩ
DIGITAL INPUT/OUTPUT
Logic family
CMOS
CMOS
1.65V < VBD < 2.5V
2.5V ≤ VBD ≤ VA
1.65 < VBD < 2.5V
2.5V ≤ VBD ≤ VA
VIN = VBD or DGND
0.8 × VBD
0.65 × VBD
–0.3
VBD + 0.3
0.8 × VBD
VBD + 0.3
VBD + 0.3
0.1 × VBD
0.25 × VBD
1
V
V
VIH
VIL
High-level input voltage
VBD + 0.3 0.65 × VBD
0.1 × VBD
0.25 × VBD
1
–0.3
–0.3
–1
V
Low-level input voltage
–0.3
V
II
Input current
–1
mA
pF
CI
Input capacitance
5
5
5
5
VA ≥ VBD ≥ 1.65V,
IO = 100mA
VOH
VOL
High-level output voltage
Low-level output voltage
VBD – 0.6
0
VBD
0.4
VBD – 0.6
0
VBD
0.4
V
V
VA ≥ VBD ≥ 1.65V,
IO = –100mA
CO
CL
SDO pin capacitance
Load capacitance
Data format
Hi-Z state
pF
pF
30
30
Straight binary
Straight binary
POWER-SUPPLY REQUIREMENTS
VA
Analog supply voltage(5)
2.7
1.65
3.6
VA + 0.2
6.5
2.7
1.65
3.6
VA + 0.2
6.5
V
V
VBD
Digital I/O supply voltage
fSAMPLE = 500kSPS
5.2
3.2
5.2
3.2
mA
fSAMPLE = 250kSPS in
Auto-Nap mode
mA
IA
Analog supply current
Nap mode, SCLK = VBD or
DGND
325
400
325
400
mA
Deep PD mode, SCLK = VBD
or DGND
50
0.1
250
0.4
50
0.1
250
0.4
nA
mA
mA
fSAMPLE = 500kSPS
IBD
Digital I/O supply current
Power dissipation
fSAMPLE = 250kSPS in
Auto-Nap mode
0.05
0.05
VA = 2.7V, VBD = 1.65V,
fSAMPLE = 500kSPS
14.2
8.72
18.2
14.2
8.72
18.6
mW
mW
VA = 2.7V, VBD = 1.65V,
fSAMPLE = 250kSPS in
Auto-Nap mode
TEMPERATURE RANGE
TA Operating free-air temperature
–40
+85
–40
+85
°C
(5) The ADS8331/32 operates with VA between 2.7V and 5.5V, and VREF between 1.2V and VA. However, the device may not meet the
specifications listed in the Electrical Characteristics when VA is between 3.6V and 4.5V.
(6) Can vary ±30%.
4
Submit Documentation Feedback
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
www.ti.com
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
ELECTRICAL CHARACTERISTICS: VA = 5V
At TA = –40°C to +85°C, VA = 5V, VBD = 1.65V to 5V, VREF = 4.096V, and fSAMPLE = 500kSPS, unless otherwise noted.
ADS8331I, ADS8332I
ADS8331IB, ADS8332IB
PARAMETER
ANALOG INPUT
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
(1)
Full-scale input voltage
INX – COM, ADCIN – COM
INX, ADCIN
0
AGND – 0.2
AGND – 0.2
VREF
0
VREF
VA + 0.2
AGND + 0.2
45
V
V
VA + 0.2 AGND – 0.2
AGND + 0.2 AGND – 0.2
45
Absolute input voltage
COM
V
Input capacitance
ADCIN
40
±1
40
±1
pF
nA
Input leakage current
Unselected ADC input
SYSTEM PERFORMANCE
Resolution
16
16
Bits
Bits
LSB(2)
No missing codes
Integral linearity
Differential linearity
Offset error(3)
16
–3
–1
16
INL
DNL
EO
±2
±1
3
2
1
–2
–1
±1
2
±0.5
1.5 LSB(2)
–1 ±0.23
±1
–1 ±0.23
±1
1
mV
PPM/°C
mV
Offset error drift
Offset error matching
Gain error
–0.125
0.125
0.25
–0.125
0.125
EG
–0.25 –0.06
–0.25 –0.06
0.25 %FSR
PPM/°C
Gain error drift
Gain error matching
Transition noise
±0.02
±0.02
–0.003
30
0.003
–0.003
30
0.003 %FSR
mV RMS
PSRR
Power-supply rejection ratio
78
78
dB
SAMPLING DYNAMICS
tCONV
Conversion time
Acquisition time
Throughput rate
18
18
CCLK
CCLK
CCLK
tSAMPLE1
tSAMPLE2
Manual-Trigger mode
Auto-Trigger mode
3
3
3
3
500
500
kSPS
DYNAMIC CHARACTERISTICS
VIN = 4.096VPP at 1kHz
VIN = 4.096VPP at 10kHz
VIN = 4.096VPP at 1kHz
VIN = 4.096VPP at 10kHz
VIN = 4.096VPP at 1kHz
VIN = 4.096VPP at 10kHz
VIN = 4.096VPP at 1kHz
VIN = 4.096VPP at 10kHz
VIN = 4.096VPP at 1kHz
VIN = 4.096VPP at 100kHz
–100
–94
90.5
88
–100
–95
91.5
88
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
(4)
THD
Total harmonic distortion
Signal-to-noise ratio
SNR
90
91
SINAD
SFDR
Signal-to-noise + distortion
Spurious-free dynamic range
Crosstalk
87
87
101
96
101
96
119
107
119
107
INX – COM with MUXOUT
tied to ADCIN
22
40
22
40
MHz
MHz
–3dB small-signal bandwidth
ADCIN – COM
(1) Ideal input span; does not include gain or offset error.
(2) LSB means least significant bit.
(3) Measured relative to an ideal full-scale input (INX – COM) of 4.096V when VA = 5V.
(4) Calculated on the first nine harmonics of the input frequency.
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
www.ti.com
ELECTRICAL CHARACTERISTICS: VA = 5V (continued)
At TA = –40°C to +85°C, VA = 5V, VBD = 1.65V to 5V, VREF = 4.096V, and fSAMPLE = 500kSPS, unless otherwise noted.
ADS8331I, ADS8332I
ADS8331IB, ADS8332IB
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
CLOCK
Internal conversion clock
frequency
10.9
11.5
12.6
40
10.9
11.5
12.6
40
MHz
MHz
MHz
Used as I/O clock only
SCLK external serial clock
Used as both I/O clock and
conversion clock
1
21
1
21
EXTERNAL VOLTAGE REFERENCE INPUT
Input
(REF+) – (REF–)
(REF–) – AGND
1.2 4.096
–0.1
4.2
0.1
1.2 4.096
–0.1
4.2
0.1
V
V
VREF
reference
range(5)
(6)
Resistance
Reference input
20
20
kΩ
DIGITAL INPUT/OUTPUT
Logic family
CMOS
CMOS
1.65 < VBD < 2.5V
2.5V ≤ VBD ≤ VA
1.65 < VBD < 2.5V
2.5V ≤ VBD ≤ VA
VIN = VBD or DGND
0.8 × VBD
0.65 × VBD
–0.3
VBD + 0.3
0.8 × VBD
VBD + 0.3
VBD + 0.3
0.1 × VBD
0.25 × VBD
1
V
V
VIH
VIL
High-level input voltage
VBD + 0.3 0.65 × VBD
0.1 × VBD
0.25 × VBD
1
–0.3
–0.3
–1
V
Low-level input voltage
–0.3
V
II
Input current
–1
µA
pF
CI
Input capacitance
5
5
5
5
VA ≥ VBD ≥ 1.65V,
IO = 100mA
VOH
VOL
High-level output voltage
Low-level output voltage
VBD – 0.6
0
VBD
0.4
VBD – 0.6
0
VBD
0.4
V
V
VA ≥ VBD ≥ 1.65V,
IO = –100mA
CO
CL
SDO pin capacitance
Load capacitance
Data format
Hi-Z state
pF
pF
30
30
Straight binary
Straight binary
POWER-SUPPLY REQUIREMENTS
VA
Analog supply voltage(5)
4.5
1.65
5
5.5
VA + 0.2
7.75
4.5
1.65
5
5.5
VA + 0.2
7.75
V
V
VBD
Digital I/O supply voltage
fSAMPLE = 500kSPS
6.6
4.2
6.6
4.2
mA
fSAMPLE = 250kSPS in
Auto-Nap mode
mA
IA
Analog supply current
Nap mode, SCLK = VBD or
DGND
390
500
390
500
mA
Deep PD mode, SCLK = VBD
or DGND
80
1.2
0.7
250
2.0
80
1.2
0.7
250
2.0
nA
mA
mA
fSAMPLE = 500kSPS
IBD
Digital I/O supply current
Power dissipation
fSAMPLE = 250kSPS in
Auto-Nap mode
VA = 5.0V, VBD = 5.0V,
fSAMPLE = 500kSPS
39
48.75
39
48.75
mW
mW
VA = 5.0V, VBD = 5.0V,
fSAMPLE = 250kSPS in
Auto-Nap mode
24.5
24.5
TEMPERATURE RANGE
TA Operating free-air temperature
–40
+85
–40
+85
°C
(5) The ADS8331/32 operates with VA between 2.7V and 5.5V, and VREF between 1.2V and VA. However, the device may not meet the
specifications listed in the Electrical Characteristics when VA is between 3.6V and 4.5V.
(6) Can vary ±30%.
6
Submit Documentation Feedback
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
www.ti.com
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
TIMING CHARACTERISTICS: VA = 2.7V
At TA = –40°C to +85°C, VA = 2.7V, and VBD = 1.65V, unless otherwise noted.
(1) (2)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
External, fCCLK = 1/2 fSCLK
Internal
0.5
10.5 MHz
fCCLK
Frequency, conversion clock, CCLK
10.5
1
11
12.2 MHz
tSU1
tH1
Setup time, rising edge of CS to EOC(3)
CS hold time with respect to EOC(3)
Pulse duration, CONVST low
Read while converting
Read while sampling
CCLK
ns
25
40
40
25
25
14
17
12
40
47.6
40
tWL1
tWH1
tSU2
tH2
ns
Pulse duration, CS high
ns
Setup time, rising edge of CS to EOS
CS hold time with respect to EOS
Setup time, falling edge of CS to first falling edge of SCLK
Pulse duration, SCLK low
Read while sampling
Read while converting
ns
ns
tSU3
tWL2
tWH2
ns
tSCLK – tWH2
tSCLK – tWL2
ns
ns
ns
ns
ns
Pulse duration, SCLK high
I/O clock only
I/O and conversion clocks
I/O clock, daisy-chain mode
1000
tSCLK
Cycle time, SCLK
I/O and conversion clocks,
daisy-chain mode
47.6
8
1000
ns
tD1
Delay time, falling edge of SCLK to SDO invalid
Delay time, falling edge of SCLK to SDO valid
10pF load
10pF load
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tD2
35
35
tD3
Delay time, falling edge of CS to SDO valid, SDO MSB output 10pF load
Setup time, SDI to falling edge of SCLK
tSU4
tH3
8
8
Hold time, SDI to falling edge of SCLK
tD4
Delay time, rising edge of CS to SDO 3-state
10pF load
15
40
tSU5
tH4
Setup time, last falling edge of SCLK before rising edge of CS
Hold time, last falling edge of SCLK before rising edge of CS
Setup time, rising edge of SCLK to rising edge of CS
Hold time, rising edge of SCLK to rising edge of CS
Delay time, falling edge of CS to deactivation of INT
15
2
(4)
tSU6
10
2
(4)
tH5
tD5
10pF load
(1) All input signals are specified with tr = tf = 1.5ns (10% to 90% of VBD) and timed from a voltage level of (VIL + VIH)/2.
(2) See the Timing Diagrams section.
(3) The EOC and EOS signals are the inverse of each other.
(4) Applies to the 5th or 17th rising SCLK when sending 4-bit or 16-bit commands, respectively, to the ADS8331/32.
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
www.ti.com
TIMING CHARACTERISTICS: VA = 5V
At TA = –40°C to +85°C, and VA = VBD = 5V, unless otherwise noted.
(1) (2)
PARAMETER
TEST CONDITIONS
External, fCCLK = 1/2 fSCLK
Internal
MIN TYP
MAX UNIT
0.5
10.5 MHz
fCCLK
Frequency, conversion clock, CCLK
10.9 11.5
12.6 MHz
tSU1
tH1
Setup time, rising edge of CS to EOC(3)
CS hold time with respect to EOC(3)
Pulse duration, CONVST low
Read while converting
Read while sampling
1
20
40
40
20
20
8
CCLK
ns
tWL1
tWH1
tSU2
tH2
ns
Pulse duration, CS high
ns
Setup time, rising edge of CS to EOS
CS hold time with respect to EOS
Setup time, falling edge of CS to first falling edge of SCLK
Pulse duration, SCLK low
Read while sampling
Read while converting
ns
ns
tSU3
tWL2
tWH2
ns
12
11
25
47.6
25
tSCLK – tWH2
tSCLK – tWL2
ns
ns
ns
ns
ns
Pulse duration, SCLK high
I/O clock only
I/O and conversion clocks
I/O clock, daisy-chain mode
1000
tSCLK
Cycle time, SCLK
I/O and conversion clocks,
daisy-chain mode
47.6
5
1000
ns
tD1
Delay time, falling edge of SCLK to SDO invalid
Delay time, falling edge of SCLK to SDO valid
10pF load
10pF load
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tD2
20
20
tD3
Delay time, falling edge of CS to SDO valid, SDO MSB output 10pF load
Setup time, SDI to falling edge of SCLK
tSU4
tH3
8
8
Hold time, SDI to falling edge of SCLK
tD4
Delay time, rising edge of CS to SDO 3-state
10pF load
10
20
tSU5
tH4
Setup time, last falling edge of SCLK before rising edge of CS
Hold time, last falling edge of SCLK before rising edge of CS
Setup time, rising edge of SCLK to rising edge of CS
Hold time, rising edge of SCLK to rising edge of CS
Delay time, falling edge of CS to deactivation of INT
10
2
(4)
tSU6
10
2
(4)
tH5
tD5
10pF load
(1) All input signals are specified with tr = tf = 1.5ns (10% to 90% of VBD) and timed from a voltage level of (VIL + VIH)/2.
(2) See the Timing Diagrams section.
(3) The EOC and EOS signals are the inverse of each other.
(4) Applies to the 5th or 17th rising SCLK when sending 4-bit or 16-bit commands, respectively, to the ADS8331/32.
8
Submit Documentation Feedback
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
www.ti.com
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
TIMING DIAGRAMS
tWL1
CONVST
EOC
(active low)
tSU2
tH1
tSU5
CS
tSCLK
SCLK
tD1
tD2
tD4
High-Z
High-Z
MSB
tD3
MSB - 1 MSB - 2 MSB - 3
LSB + 1
LSB
TAG2
X
TAG1
TAG0
X
'0'
'0'
SDO
SDI
tSU4
'1'
'1'
'0'
'1'
X
X
X
X
X
tH3
Figure 1. Read While Sampling (Shown with Manual-Trigger Mode)
CONVST
21 Conversion Clock Cycles
EOC
(active low)
tH2
tSU1
CS
tWL2
tSU3
tH4
SCLK
tWH2
tSU5
High-Z
tD4
High-Z
MSB
'1'
MSB - 1 MSB - 2 MSB - 3
LSB
X
TAG2
TAG1
X
TAG0
SDO
SDI
'1'
'0'
'1'
X
X
X
Figure 2. Read While Converting (Shown with Auto-Trigger Mode at 500 kSPS)
tSU6
CS
tH5
tSU3
SCLK
tH3
MSB - 1
MSB
MSB - 2
LSB + 1
LSB
Don’t Care
tD4
SDI
tD3
tD1
tD2
LSB + 1
LSB
‘0’
SDO
MSB
MSB - 1
MSB - 2
Figure 3. SPI I/O
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
www.ti.com
TIMING DIAGRAMS (continued)
CS
tH1
EOC
(active low)
tD5
INT
(active low)
Figure 4. Relationship among CS, EOC, and INT
PIN ASSIGNMENTS
RGE PACKAGE
4x4 QFN-24
(TOP VIEW)
PW PACKAGE
TSSOP-24
(TOP VIEW)
1
2
3
4
5
6
7
8
9
IN1
IN2
24
23
IN0
COM
IN4/NC(1)
IN5/NC(1)
ADCIN
AGND
1
2
3
4
5
6
18
17
IN3
IN4/NC(3)
IN5/NC(3)
IN6/NC(3)
22
21
20
19
MUXOUT
ADCIN
AGND
REF-
IN6/NC(1)
16 REF-
15 REF+
14 VA
ADS8331
ADS8332
ADS8331
ADS8332
IN7/NC(1)
IN7/NC(3)
RESET
REF+
VA
18
17
16
15
14
13
Thermal Pad(2)
(Bottom Side)
RESET
EOC/INT/CDI
SCLK
VBD
13 VBD
EOC/INT/CDI
10
11
12
CONVST
DGND
SDO
FS/CS
SDI
(3) NC = No internal connection (ADS8331
only).
(1) NC = No internal connection (ADS8331
only).
(2) Connect thermal pad to analog ground.
10
Submit Documentation Feedback
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
www.ti.com
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
ADS8331 PIN DESCRIPTIONS
PIN NO.
NAME
ADCIN
AGND
TSSOP
QFN
18
I/O
DESCRIPTION
21
20
14
23
15
I
–
–
I
ADC input
17
Analog ground
Digital interface ground
DGND
11
COM
20
Common ADC input (usually connected to AGND)
CONVST
12
I
Conversion start. Freezes sample and hold, starts conversion.
Status output. If programmed as end-of-conversion (EOC), this pin is low (default) when a
conversion is in progress. If programmed as an interrupt (INT), this pin is low (default) after
EOC/INT/CDI
9
6
O/O/I the end of conversion and returns high after FS/CS goes low. The polarity of EOC or INT is
programmable.
This pin can also be used as a chain data input (CDI) when operated in daisy-chain mode.
FS/CS
IN[0:3]
11
1-3, 24
4-7
8
21-24
1-4
19
I
I
Frame sync signal for DSP (such as TMS320™ DSP) or chip select input for SPI.
Mux inputs
NC
–
O
I
No connection
Mux output
MUXOUT
REF+
22
18
15
External reference input
External reference ground (connect to AGND through an individual via on the printed circuit
board)
REF–
19
16
–
RESET
SCLK
SDI
8
5
7
I
I
External reset (active low)
SPI clock for serial interface
SPI serial data in
10
12
13
17
16
9
I
SDO
VA
10
14
13
O
–
–
SPI serial data out
Analog supply, +2.7V to +5.5V
Digital interface supply
VBD
ADS8332 PIN DESCRIPTIONS
PIN NO.
NAME
ADCIN
AGND
TSSOP
21
QFN
18
I/O
DESCRIPTION
I
–
–
I
ADC input
20
17
Analog ground
DGND
14
11
Digital interface ground
COM
23
20
Common ADC input (usually connected to AGND)
Conversion start. Freezes sample and hold, starts conversion.
CONVST
15
12
I
Status output. If programmed as end-of-conversion (EOC), this pin is low (default) when a
conversion is in progress. If programmed as an interrupt (INT), this pin is low (default) after
EOC/INT/CDI
9
6
8
O/O/I the end of conversion and returns high after FS/CS goes low. The polarity of EOC or INT is
programmable.
This pin can also be used as a chain data input (CDI) when operated in daisy-chain mode.
FS/CS
IN[0:7]
11
I
I
Frame sync signal for DSP (such as TMS320™ DSP) or chip select input for SPI.
Mux inputs
1-7, 24
1-4,
21-24
MUXOUT
REF+
22
18
19
15
O
I
Mux output
External reference input
External reference ground (connect to AGND through an individual via on the printed circuit
board)
REF–
19
16
–
RESET
SCLK
SDI
8
5
7
I
I
External reset (active low)
SPI clock for serial interface
SPI serial data in
10
12
13
17
16
9
I
SDO
VA
10
14
13
O
–
–
SPI serial data out
Analog supply, +2.7 V to +5.5 V
Digital interface supply
VBD
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS: DC Performance
At TA = +25°C, VREF (REF+ – REF–) = 4.096V when VA = VBD = 5V or VREF (REF+ – REF–) = 2.5V when VA = VBD = 2.7V,
fSCLK = 21MHz, and fSAMPLE = 500kSPS, unless otherwise noted.
INTEGRAL LINEARITY ERROR
vs CODE
INTEGRAL LINEARITY ERROR
vs CODE
3
2
3
2
VA = VBD = 2.7V
VREF = 2.500V
VA = VBD = 5.0V
VREF = 4.096V
1
1
0
0
-1
-2
-3
-1
-2
-3
8000h
8000h
C000h
FFFFh
C000h
FFFFh
0000h
4000h
0000h
4000h
Output Code
Output Code
Figure 5.
Figure 6.
DIFFERENTIAL LINEARITY ERROR
vs CODE
DIFFERENTIAL LINEARITY ERROR
vs CODE
3
2
3
2
VA = VBD = 2.7V
VREF = 2.500V
VA = VBD = 5.0V
VREF = 4.096V
1
1
0
0
-1
-2
-3
-1
-2
-3
8000h
8000h
C000h
FFFFh
C000h
FFFFh
0000h
4000h
0000h
4000h
Output Code
Output Code
Figure 7.
Figure 8.
ANALOG SUPPLY CURRENT
vs ANALOG SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT IN NAP MODE
vs ANALOG SUPPLY VOLTAGE
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
500
450
400
350
300
VREF = 4.096V
VREF = 4.096V
VREF = 2.500V
VREF = 2.500V
VA (V)
VA (V)
Figure 9.
Figure 10.
12
Submit Documentation Feedback
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
www.ti.com
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS: DC Performance (continued)
At TA = +25°C, VREF (REF+ – REF–) = 4.096V when VA = VBD = 5V or VREF (REF+ – REF–) = 2.5V when VA = VBD = 2.7V,
fSCLK = 21MHz, and fSAMPLE = 500kSPS, unless otherwise noted.
ANALOG SUPPLY CURRENT
DEEP POWER-DOWN CURRENT
vs TEMPERATURE
vs SAMPLING RATE IN AUTO-NAP MODE
8
7
6
5
4
3
2
1
0
120
100
80
60
40
20
0
VA = VBD = 5.0V
VREF = 4.096V
VA = VBD = 5.0V
VREF = 4.096V
VA = VBD = 2.7V
VREF = 2.500V
VA = VBD = 2.7V
VREF = 2.500V
0
50
100 150 200 250 300 350 400 450
Sampling Rate (kHz)
-50
-25
0
25
50
75
100
Temperature (°C)
Figure 11.
Figure 12.
INTERNAL CLOCK FREQUENCY
vs ANALOG SUPPLY VOLTAGE
CHANGE IN GAIN
vs TEMPERATURE
4
3
12.2
11.7
11.2
10.7
10.2
VA = VBD = 2.7V
VREF = 2.500V
2
VREF = 4.096V
1
VREF = 2.500V
0
VA = VBD = 5.0V
VREF = 4.096V
-1
-2
-3
-4
-50
-25
0
25
50
75
100
Temperature (°C)
VA (V)
Figure 13.
Figure 14.
CHANGE IN OFFSET
vs TEMPERATURE
CHANGE IN ANALOG SUPPLY CURRENT
vs TEMPERATURE
6
5
1.0
0.8
4
0.6
VA = VBD = 2.7V
VREF = 2.500V
3
0.4
2
0.2
1
VA = VBD = 2.7V
VREF = 2.500V
0
0
-1
-2
-3
-4
-5
-6
-0.2
-0.4
-0.6
-0.8
-1.0
VA = VBD = 5.0V
VREF = 4.096V
VA = VBD = 5.0V
VREF = 4.096V
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
Figure 15.
Figure 16.
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS: DC Performance (continued)
At TA = +25°C, VREF (REF+ – REF–) = 4.096V when VA = VBD = 5V or VREF (REF+ – REF–) = 2.5V when VA = VBD = 2.7V,
fSCLK = 21MHz, and fSAMPLE = 500kSPS, unless otherwise noted.
CHANGE IN DIGITAL SUPPLY CURRENT
vs TEMPERATURE
CHANGE IN INTERNAL CLOCK FREQUENCY
vs TEMPERATURE
1.0
0.8
150
125
100
75
0.6
VA = VBD = 2.7V
VREF = 2.500V
VA = VBD = 2.7V
VREF = 2.500V
0.4
50
0.2
25
0
0
-25
-50
-75
-100
-125
-150
-0.2
-0.4
-0.6
-0.8
-1.0
VA = VBD = 5.0V
VREF = 4.096V
VA = VBD = 5.0V
VREF = 4.096V
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
Figure 17.
Figure 18.
CHANGE IN ANALOG SUPPLY CURRENT IN NAP MODE
vs TEMPERATURE
25
VA = VBD = 2.7V
VREF = 2.500V
20
15
10
5
VA = VBD = 5.0V
VREF = 4.096V
0
-5
-10
-15
-20
-25
-50
-25
0
25
50
75
100
Temperature (°C)
Figure 19.
14
Submit Documentation Feedback
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
www.ti.com
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS: AC Performance
At TA = +25°C, VREF (REF+ – REF–) = 4.096V when VA = VBD = 5V or VREF (REF+ – REF–) = 2.5V when VA = VBD = 2.7V,
fSCLK = 21MHz, fSAMPLE = 500kSPS, and fIN = 10kHz, unless otherwise noted.
OUTPUT CODE HISTOGRAM
OUTPUT CODE HISTOGRAM
FOR A DC INPUT (8192 Conversions)
FOR A DC INPUT (8192 Conversions)
VA = VBD = 2.7V
VA = VBD = 5.0V
VREF = 2.500V
VREF = 4.096V
6336
4791
1665
1643
1088
768
53
7FFD
40
0
0
7FFE
7FFF
Code
8000
8001
7FFD
7FFE
7FFF
Code
8000
8001
Figure 20.
Figure 21.
FREQUENCY SPECTRUM
FREQUENCY SPECTRUM
(8192 Point FFT, fIN = 1.0376kHz, –0.2dB)
(8192 Point FFT, fIN = 1.0376kHz, –0.2dB)
0
-20
0
-20
VA = VBD = 2.7V
VREF = 2.500V
VA = VBD = 5.0V
VREF = 4.096V
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
50
100
150
200
250
0
50
100
150
200
250
Frequency (kHz)
Frequency (kHz)
Figure 22.
Figure 23.
FREQUENCY SPECTRUM
FREQUENCY SPECTRUM
(8192 Point FFT, fIN = 10.0708kHz, –0.2dB)
(8192 Point FFT, fIN = 10.0708kHz, –0.2dB)
0
-20
0
-20
VA = VBD = 2.7V
VREF = 2.500V
VA = VBD = 5.0V
VREF = 4.096V
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
50
100
150
200
250
0
50
100
150
200
250
Frequency (kHz)
Frequency (kHz)
Figure 24.
Figure 25.
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS: AC Performance (continued)
At TA = +25°C, VREF (REF+ – REF–) = 4.096V when VA = VBD = 5V or VREF (REF+ – REF–) = 2.5V when VA = VBD = 2.7V,
fSCLK = 21MHz, fSAMPLE = 500kSPS, and fIN = 10kHz, unless otherwise noted.
SIGNAL-TO-NOISE + DISTORTION
vs TEMPERATURE
SIGNAL-TO-NOISE RATIO
vs INPUT FREQUENCY
93
92
91
90
89
88
87
95
90
85
80
fIN = 1.03760kHz, -0.2dB
VA = VBD = 5.0V
VREF = 4.096V
VA = VBD = 5.0V
VREF = 4.096V
VA = VBD = 2.7V
VREF = 2.500V
VA = VBD = 2.7V
VREF = 2.500V
1
10
fIN (kHz)
100
250
-50
-25
0
25
50
75
100
Temperature (°C)
Figure 26.
Figure 27.
TOTAL HARMONIC DISTORTION
vs INPUT FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE
vs INPUT FREQUENCY
-65
-70
105
100
95
VA = VBD = 2.7V
VREF = 2.500V
-75
-80
90
VA = VBD = 5.0V
VREF = 4.096V
VA = VBD = 5.0V
VREF = 4.096V
-85
85
-90
80
-95
75
VA = VBD = 2.7V
VREF = 2.500V
-100
-105
70
65
1
10
fIN (kHz)
100
250
1
10
fIN (kHz)
100
250
Figure 28.
Figure 29.
SIGNAL-TO-NOISE + DISTORTION
vs INPUT FREQUENCY
95
90
85
80
75
70
65
VA = VBD = 5.0V
VREF = 4.096V
VA = VBD = 2.7V
VREF = 2.500V
1
10
fIN (kHz)
100
250
Figure 30.
16
Submit Documentation Feedback
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
www.ti.com
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS: AC Performance (continued)
At TA = +25°C, VREF (REF+ – REF–) = 4.096V when VA = VBD = 5V or VREF (REF+ – REF–) = 2.5V when VA = VBD = 2.7V,
fSCLK = 21MHz, fSAMPLE = 500kSPS, and fIN = 10kHz, unless otherwise noted.
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
POWER-SUPPLY REJECTION RATIO
vs POWER-SUPPLY RIPPLE FREQUENCY
95
90
85
80
75
70
65
60
55
50
45
40
35
16.0
15.5
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
VRIPPLE = 0.5VPP
VA = VBD = 5.0V
VREF = 4.096V
VA = VBD = 2.7V
VREF = 2.500V
VA = VBD = 5.0V
VREF = 4.096V
VA = VBD = 2.7V
VREF = 2.500V
1
10
100
250
0.1
1
10
100
500
Ripple Frequency (kHz)
fIN (kHz)
Figure 31.
Figure 32.
CROSSTALK
vs INPUT FREQUENCY
-95
-100
-105
-110
-115
-120
-125
VA = VBD = 5.0V
VREF = 4.096V
VA = VBD = 2.7V
VREF = 2.500V
-130
1
10
100
250
fIN (kHz)
Figure 33.
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
www.ti.com
THEORY OF OPERATION
DESCRIPTION
The ADS8331/32 is a high-speed, low-power, successive approximation register (SAR) analog-to-digital
converter (ADC) that uses an external reference. The architecture is based on charge redistribution, which
inherently includes a sample/hold function.
The ADS8331/32 has an internal clock that is used to run the conversion. However, the ADS8331/32 can be
programmed to run the conversion based on the external serial clock (SCLK).
The analog input to the ADS8331/32 is provided to two input pins: one of the INX input channels and the shared
COM pin. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor
array. While a conversion is in progress, both INX and COM inputs are disconnected from any internal function.
The ADS8331 has four analog inputs while the ADS8332 has eight inputs. All inputs share the same common
pin, COM. Both the ADS8331 and ADS8332 can be programmed to select a channel manually or can be
programmed into the auto channel select mode to sweep through the input channels automatically.
SIGNAL CONDITIONING
The ADS8331/32 has the flexibility to add signal conditioning between the MUXOUT and ADCIN pins, such as a
programmable gain amplifier (PGA) or filter. This feature reduces the system component count and cost because
each input channel does not require separate signal conditioning circuits, especially if the source impedance
connected to each channel is similar in value.
ANALOG INPUT
When the converter enters the hold mode, the voltage difference between the INX and COM inputs is captured
on the internal capacitor array. The voltage on the COM pin is limited between (AGND – 0.2V) and (AGND +
0.2V). This limitation allows the ADS8331/32 to reject small signals that are common to both the INX and COM
inputs. The INX inputs have a range of –0.2V to (VA + 0.2V). The input span of (INX – COM) is limited to 0V to
VREF
.
The peak input current through the analog inputs depends upon a number of factors: reference voltage, sample
rate, input voltage, and source impedance. The current flowing into the ADS8331/32 charges the internal
capacitor array during the sample period. After this capacitance has been fully charged, there is no further input
current. The source of the analog input voltage must be able to charge the maximum input capacitance (45pF) to
a 16-bit settling level within the minimum acquisition time (238ns). When the converter goes into hold mode, the
input impedance is greater than 1GΩ.
Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the INX
inputs, the COM input, and the input span of (INX – COM) should be within the limits specified. If these inputs are
outside of these ranges, the linearity of the converter may not meet specifications. To minimize noise,
low-bandwidth input signals with low-pass filters should be used. Care should be taken to ensure that the output
impedance of the sources driving the INX and COM inputs are matched, as shown in Figure 34. If this matching
is not observed, the two inputs could have different settling times, which may result in an offset error, gain error,
and linearity error that change with temperature and input voltage.
MUXOUT ADCIN
Device in Hold Mode; Last Input Sampled from IN0
ESD
40pF
ESD
40W
50W
50W
ESD
IN0
ESD
ESD
4pF
INX
AGND
40pF
55W
VA
COM
ESD
AGND
Figure 34. Input Equivalent Circuit
18
Submit Documentation Feedback
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
www.ti.com
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
Driver Amplifier Choice
In order to take advantage of the high sample rate offered by the ADS8331/32, the analog inputs to the converter
should be driven with low-noise operational amplifiers (op amps), such as the OPA365, OPA211, OPA827, or
THS4031. An RC filter is recommended at each of the input channels to low-pass filter noise generated by the
input driving sources. These channels can accept unipolar signals with voltages between INX and COM in the
range of 0V to VREF. If RC filters are not used between the op amps and the input channels, the minimum –3dB
bandwidth required by the driving op amps for the sampled signals to settle to within 1/2 LSB of the final voltage
can be calculated using Equation 1:
(n + 1) ´ ln(2)
f
³
-3dB
2p ´ tSAMPLE_MIN
(1)
Where:
n = resolution of the converter (n = 16 for the ADS8331/32).
tSAMPLE_MIN = minimum acquisition time.
The minimum value of tSAMPLE in the Electrical Characteristics tables is 238ns (3 CCLKs with the internal
oscillator at 12.6MHz). Substituting these values for n and tSAMPLE_MIN into Equation 1 shows f–3dB must be at
least 7.9MHz. This bandwidth can be relaxed if the acquisition time is increased or an RC filter is added between
the driving op amp and the corresponding input channel (refer to Texas Instruments' Application Report
SBAA173 and associated references for additional information, available for download at www.ti.com). The
OPA365 used in the source-follower (unity-gain) configuration is shown in Figure 35 with recommended values
for the RC filter.
Input Signal
(0V to 4V)
MUXOUT
ADCIN
5V
VA
20W
ADS8331
ADS8332
OPA365
INX
1000pF
COM
Figure 35. Unipolar Input Drive Configuration
Bipolar to Unipolar Driver
In systems where the input signal is bipolar, op amps such as the OPA365 and OPA211 can be used in the
inverting configuration with a dc bias applied to the noninverting input in order to keep the input signal to the
ADS8331/32 within its rated operating voltage range. This configuration is also recommended when the
ADS8331/32 is used in signal-processing applications where good SNR and THD performance is required. The
dc bias can be derived from low-noise reference voltage ICs such as the REF5025 or REF5040. The input
configuration shown in Figure 36 is capable of delivering better than 91dB SNR and –99dB THD at an input
frequency of 1kHz. If bandpass filters are used to filter the input to the driving op amp, the signal swing at the
input of the bandpass filter should be small enough to minimize the distortion introduced by the filter. In these
cases, the gain of the circuit shown in Figure 36 can be increased to maintain a large enough input signal to the
ADS8331/32 to keep the system SNR as high as possible.
MUXOUT
ADCIN
5V
2.048VDC
VA
20W
OPA211
INX
ADS8331
ADS8332
600W
1000pF
Input Signal
(-2V to +2V)
COM
600W
Figure 36. Bipolar Input Drive Configuration
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
www.ti.com
REFERENCE
The ADS8331/32 can operate with an external reference with a range from 1.2V to 4.2V. A clean, low-noise
reference voltage on this pin is required to ensure good converter performance. A low-noise band-gap reference
such as the REF5025 or REF5040 can be used to drive this pin. A 10mF ceramic bypass capacitor is required
between the REF+ and REF– pins of the converter. This capacitor should be placed as close as possible to the
pins of the device. Note that the REF– pin should not be connected to the AGND pin of the converter; instead,
the REF– pin must be connected to the analog ground plane with a separate via.
CONVERTER OPERATION
The ADS8331/32 has an internal oscillator that can be used as the conversion clock (CCLK) source. The
minimum frequency of this oscillator is 10.5MHz. The internal oscillator is only active during the conversion
period unless the converter is using Auto-Trigger and/or Auto-Nap modes. The minimum acquisition/sampling
time for the ADS8331/32 is 3 CCLKs (250ns with a 12MHz conversion clock), while the minimum conversion time
is 18 CCLKs (1500ns with a 12MHz conversion clock).
As shown in Figure 37, the ADS8331/32 can also be programmed to run conversions using the external serial
clock (SCLK). This feature allows system designers to achieve system synchronization. Each rising edge of
SCLK toggles the state of the conversion clock (CCLK), which reduces the frequency of SCLK by a factor of two
before it is used as CCLK. For example, a 21MHz SCLK provides a 10.5MHz CCLK. If the start of a conversion
must occur on a specific rising edge of SCLK when the external serial clock is used for the conversion clock (and
Manual-Trigger mode is enabled), a minimum setup time of 20ns between the falling edge of CONVST and the
rising edge of SCLK must be met. This timing ensures the conversion is completed in 18 CCLKs (36 SCLKs).
The duty cycle of SCLK is not critical, as long as the minimum high and low times (11ns for VA = 5.0V) are
satisfied. Because the ADS8331/32 is designed for high-speed applications, a high-frequency serial clock must
be supplied to maintain the high throughput of the interface. This requirement can be accomplished if the period
of SCLK is at most 1ms when SCLK is used as the conversion clock (CCLK). The 1ms maximum period for SCLK
is also set by the leakage of charge from the capacitors in the capacitive digital-to-analog converter (CDAC)
block in the ADS8331/32. If SCLK is used as the conversion clock, the SCLK source must have minimal rise/fall
times and low jitter to provide the best converter performance.
CFR_D10
Conversion Clock
= 1
= 0
Oscillator
(CCLK)
SPI Serial
Clock (SCLK)
Divide by 2
Figure 37. Conversion Clock Source
Manual Channel Select Mode
Manual Channel Select mode is enabled through the Configuration register (CFR) by setting the CFR_D11 bit to
'0' (see Table 5). The acquisition process starts with selecting an input channel. This selection is done by writing
the desired channel number to the Command register (CMR); see Table 4 for further details. The associated
timing diagram is shown in Figure 38.
CS
SCLK
< 30ns
Mux switch
CHOLD
CHNEW
Figure 38. Manual Channel Select Timing
20
Submit Documentation Feedback
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
www.ti.com
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
Auto Channel Select Mode
Channel selection can also be done automatically if Auto Channel Select mode (default) is enabled (CFR_D11 =
'1'). If the device is programmed for Auto Channel Select mode, then signals from all channels are acquired in a
fixed order. In Auto Channel Select mode, the first conversion after entering this mode is always from the
channel of the last conversion completed before this mode is enabled. The channels are then sequentially
scanned up to and including the last channel (that is, channel 3 for the ADS8331 and channel 7 for the
ADS8332) and then back to the channel that started the sequence. For example, if the last channel used in the
conversion before enabling Auto Channel Select mode was channel 2, the sequence for the ADS8332 would be:
2, 3, 4, 5, 6, 7, 2, etc., as shown in Figure 39. If the last channel in Manual Channel Select mode happened to be
channel 7, the sequence would be: 7, 7, 7, etc. Figure 40 shows when the next channel in the sequence
activates during Auto Channel Select mode. This timing allows the next channel to settle before it is acquired.
This automatic sequencing stops the cycle after CFR_D11 is set to '0'.
Manual Channel Select Channel 2
Enable Auto Channel Select
Conversion Start is Automatic or Manual
Manual- or Auto-Trigger Mode
Ch 2
Ch 7
Ch 3
Ch 6
Ch 4
Ch 5
Figure 39. Auto Channel Select for the ADS8332
CCLK
EOC
(active low)
1 CCLK Minimum
Channel #
N - 1
N
Figure 40. Channel-Number Update in Auto Channel Select Mode Timing
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
www.ti.com
Start of a Conversion
The end of acquisition is the same as the start of a conversion. This process is initiated by bringing the CONVST
pin low for a minimum of 40ns. After the minimum requirement has been met, the CONVST pin can be brought
high. CONVST acts independently of FS/CS so it is possible to use one common CONVST for applications that
require simultaneous sample/hold with multiple converters. The ADS8331/32 switches from sample to hold mode
on the falling edge of the CONVST signal. The ADS8331/32 requires 18 conversion clock (CCLK) cycles to
complete a conversion. The conversion time is equivalent to 1500ns with a 12MHz internal clock. The minimum
time between two consecutive CONVST signals is 21 CCLKs.
A conversion can also be initiated without using CONVST if the ADS8331/32 is programmed for Auto-Trigger
mode (CFR_D9 = '0'). When the converter is configured in this mode, and with CFR_D8 = '0', the next
conversion is automatically started three conversion clocks (CCLK) after the end of a conversion. These three
conversion clocks (CCLK) are used for the acquisition time. In this case, the time to complete one acquisition
and conversion cycle is 21 CCLKs. Table 1 summarizes the different conversion modes.
Table 1. Different Types of Conversion
MODE
SELECT CHANNEL
Auto Channel Select(1)
START CONVERSION
Auto-Trigger Mode
Automatic
No need to write channel number to CMR. Use internal sequencer for
ADS8331/32.
Start a conversion based on conversion
clock CCLK
Manual Channel Select
Manual-Trigger Mode
Manual
Write channel number to CMR
Start a conversion with CONVST
(1) Auto channel select should be used with Auto-Trigger mode and TAG bit output enabled.
Status Output Pin (EOC/INT)
The status output pin is programmable. It can be used as an EOC output (CFR_D[7:6] = '11') where the low time
is equal to the conversion time. When the status pin is programmed as EOC and the polarity is set as active low,
the pin works in the following manner: the EOC output goes low immediately following CONVST going low with
Manual-Trigger mode enabled. EOC stays low throughout the conversion process and returns high when the
conversion has ended. If Auto-Trigger mode is enabled, the EOC output remains high for three conversion clocks
(CCLK) after the previous rising edge of EOC .
This status pin can also be used as an interrupt output, INT (CFR_D[7:6] = '10'), which is set low at the end of a
conversion, and is brought high (cleared) by the next read cycle. The polarity of this pin, whether used as EOC
or INT, is programmable through the CFR_D7 bit.
22
Submit Documentation Feedback
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
www.ti.com
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
Power-Down Modes and Acquisition Time
There are three power-down modes that reduce power dissipation: Nap, Deep, and Auto-Nap. The first two, Nap
and Deep Power-Down modes, are enabled/disabled by bits CFR_D3 and CFR_D2, respectively, in the
Configuration register (see Table 5 for details).
Deep Power-Down mode provides maximum power savings. When this mode is enabled, the analog core in the
converter is shut down, and the analog supply current falls from 6.6mA (VA = 5.0V) to 1mA in 2ms. The wakeup
time from Deep Power-Down mode is 1ms. The device can wake up from Deep Power-Down mode by either
disabling this mode, issuing the wakeup command, loading the default value into the CFR, or performing a reset
(either with the software reset command, CFR_D0 bit, or the external reset). See Table 4 and Table 5 along with
the Reset Function section for further information.
In Nap Power-Down mode, the bias currents for the analog core of the device are significantly reduced. Because
the bias currents are not completely shut off, the ADS8331/32 can wake up from this power-down mode much
faster than from Deep Power-Down mode. After Nap Power-Down mode is enabled, the analog supply current
falls from 6.6mA (VA = 5.0V) to 0.39mA in 200ns. The wakeup time from this mode is three conversion clock
cycles (CCLK). The device can wake up from Nap Power-Down mode in the same manner as waking up from
Deep Power-Down mode.
The third power-down mode, Auto-Nap, is enabled/disabled by bit CFR_D4 in the Configuration register (see
Table 5 for details). Once this mode is enabled, the device is controlled by the digital core logic on the chip. The
device is automatically placed into Nap Power-Down mode after the next end of conversion (EOC). The analog
supply current falls from 6.6mA (VA = 5.0V) to 0.39mA in 200ns. A conversion start wakes up the device in three
conversion clock cycles. Issuing the wake-up command, loading the default value into the CFR, disabling
Auto-Nap Power-Down mode, issuing a manual channel select command, or resetting the device can wake the
ADS8331/32 from Auto-Nap Power-Down mode. A comparison of the three power-down modes is listed in
Table 2.
Table 2. Comparison of Power-Down Modes
POWER
TYPE OF
POWER-DOWN
CONSUMPTION
(VA = 5.0V)
POWER-DOWN
BY:
POWER-DOWN TIME
WAKEUP BY:
WAKEUP TIME
ENABLE
—
Normal operation
Deep power-down
Nap power-down
6.6mA
1mA
—
—
—
—
1ms
Setting CFR_D2
Setting CFR_D3
2ms
Wakeup command 1011b
Set CFR_D2
Set CFR_D3
0.39mA
200ns
Wakeup command 1011b
3 CCLKs
Auto-Nap
power-down
EOC (end of
conversion)
CONVST, any channel select command, default
command 1111b, or wakeup command 1011b.
0.39mA
200ns
3 CCLKs
Set CFR_D4
The default acquisition time is three conversion clock (CCLK) cycles. Figure 41 shows the timing diagram for
CONVST, EOC, and auto-nap power-down signals in Manual-Trigger mode. As shown in the diagram, the device
wakes up after a conversion is triggered by the CONVST pin going low. However, a conversion is not yet started
at this time. The conversion start signal to the analog core of the chip is internally generated no less than six
conversion clock (CCLK) cycles later, to allow at least three CCLKs for wake up and three CCLKs for acquisition.
The ADS8331/32 enters Nap Power-Down mode one conversion cycle after the end of conversion (EOC).
CCLK
CONVST
CONVST_OUT
3 + 3 = 6 Cycles
(internal)
1 Cycle
NAP_ACTIVE
(internal)
EOC
(active low)
Figure 41. Timing for CONVST, EOC, and Auto-Nap Power-Down Signals in Manual-Trigger Mode (Three
Conversion Clock Cycles for Acquisition)
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
www.ti.com
The ADS8331/32 can support sampling rates of up to 500kSPS in Auto-Trigger mode. This rate is selectable by
programming the CFR_D8 bit in the Configuration register. In 500kSPS mode, consecutive conversion start
pulses to the analog core are generated 21 conversion clock cycles apart. In 250kSPS mode, consecutive
conversion-start pulses are 42 conversion clock cycles apart. The Nap and Deep Power-Down modes are
available with either sampling rate; however, Auto-Nap mode is available only with a sampling rate of 250kSPS
when Auto-Trigger mode is enabled. The analog core cannot be powered down when the Auto-Nap mode
sampling rate is 500kSPS because at that rate, there is no period of time when the analog core is not actively
being used.
Figure 42 shows the timing diagram for conversion start and auto-nap power-down signals for a 250kSPS
sampling rate in Auto-Trigger mode. For a 16-bit ADC output word, consecutive new conversion start pulses are
generated 2 × (18 + 3) cycles apart. NAP_ACTIVE (the signal to power down the analog core in Nap and
Auto-Nap modes) goes low six (3 + 3) conversion clock cycles before the conversion start falling edge, thus
powering up the analog core. It takes three conversion clock cycles after NAP_ACTIVE goes low to power up the
analog core. The analog core is powered down a cycle after the end of a conversion. For a 16-bit ADC with a
500kSPS sampling rate and three conversion clock cycle sampling, consecutive conversion start pulses are
generated 21 conversion clock cycles apart.
1
37
2
38
3
19
20
21
42
43
CCLK
CONVST_OUT
(internal)
EOC
(active low)
NAP_ACTIVE
(internal)
Figure 42. Timing for Conversion Start and Auto-Nap Power-Down Signals in Auto-Trigger Mode
(250kSPS Sampling and Three Conversion Clock Cycles for Acquisition)
Timing diagrams for reading from the ADS8331/32 with various trigger and power-down modes are shown in
Figure 43 through Figure 45. The total (acquisition + conversion) times for the different trigger and power-down
modes are listed in Table 3.
Table 3. Total Acquisition + Conversion Times
MODE
ACQUISITION + CONVERSION TIME
Auto-Trigger at 500kSPS
= 21 CCLK
Manual-Trigger
≥ 21 CCLK
Manual-Trigger with Deep Power-Down
Manual-Trigger with Nap Power-Down
≥ 4 SCLK + 1ms + 3 CCLK + 18 CCLK + 16 SCLK + 2ms
≥ 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK + 16 SCLK + 200ns
≥ 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK + 1 CCLK + 200ns (using wakeup to resume)
≥ 3 CCLK + 3 CCLK + 18 CCLK + 1 CCLK + 200ns (using CONVST to resume)
Manual-Trigger with Auto-Nap Power-Down
24
Submit Documentation Feedback
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
www.ti.com
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
(N+1)
N
CONVST
EOC
(active low)
Sample (N + 1)
Conversion N
Conversion (N + 1)
tH2
tSU1
Read While Converting
CS
Read Result (N - 1)
Read While Sampling
tSU2
tH1
CS
Read Result N
Figure 43. Read While Converting vs Read While Sampling (Manual-Trigger Mode)
BLANKSPACE
(N+1)
N
CONVST
Note
(1)
Note
Power-Down
(1)
Wakeup
Sample N
³ 3 CCLK
Conversion N
Power-Down Wakeup
Sample (N + 1)
³ 3 CCLK
Conversion (N + 1)
Converter State
= 18 CCLK
= 18 CCLK
tH2
tH2
Read While Converting
Read Result
(N - 1)
Note
(2)
Note
(3)
Note
(2)
Note
(3)
Read Result
N
CS
tSU2
tSU2
Read While Sampling
Note
(2)
Note
(2)
Note
(3)
Note
(3)
Read Result
(N - 1)
Read Result
N
CS
(1) Converter is in acquisition mode between end of conversion and activation of Nap or Deep Power-Down mode.
(2) Command on SDI pin to wake up converter (minimum of four SCLKs).
(3) Command on SDI pin to place converter into Nap or Deep Power-Down mode (minimum of 16 SCLKs).
Figure 44. Read While Converting vs Read While Sampling with Nap or Deep Power-Down
(Manual-Trigger Mode)
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
25
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
www.ti.com
tWL1
MANUAL TRIGGER CASE 1 (Wakeup Using CONVST):
(N+1)
N
CONVST
EOC
(active low)
Note
(1)
Note
(1)
Wakeup
Sample N
³ 3 CCLK
Conversion N
Power-Down Wakeup
Sample (N + 1)
³ 3 CCLK
Conversion (N + 1)
Power-Down
Converter State
= 18 CCLK
= 18 CCLK
³ 6 CCLK
³ 6 CCLK
tH2
tSU1
tH2
tSU1
Read While Converting
Read Result
(N - 1)
Read Result
N
CS
tSU2
tSU2
Read While Sampling
Read Result
(N - 1)
Read Result
N
CS
tWL1
MANUAL TRIGGER CASE 2 (Wakeup Using Wakeup Command):
(N+1)
N
CONVST
EOC
(active low)
Note
(1)
Note
Power-Down
(1)
Wakeup
Sample N
³ 3 CCLK
Conversion N
Power-Down Wakeup
Sample (N + 1)
³ 3 CCLK
Conversion (N + 1)
Converter State
= 18 CCLK
= 18 CCLK
tH2
tSU1
tH2
tSU1
Read While Converting
Read Result
(N - 1)
Note
(2)
Note
(2)
Read Result
N
CS
tSU2
tSU2
Read While Sampling
Read Result
(N - 1)
Read Result
N
Note
(2)
Note
(2)
CS
(1) Time between end of conversion and Nap Power-Down mode is 1 CCLK.
(2) Command on SDI to wake up converter (minimum of four SCLKs).
Figure 45. Read While Converting vs Read While Sampling with Auto-Nap Power-Down
26
Submit Documentation Feedback
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
www.ti.com
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
DIGITAL INTERFACE
The serial interface is designed to accommodate the latest high-speed processors with an SCLK frequency of up
to 40MHz (VA = VBD = 5.0V). Each cycle starts with the falling edge of FS/CS. The internal data register
content, which is made available to the output register at the end of conversion, is presented on the SDO output
pin on the falling edge of FS/CS. The first bit is the most significant bit (MSB). The output data bits are valid on
the falling edge of SCLK with the tD2 delay (see the Timing Characteristics)so that the host processor can read
the data on the falling edge. Serial data input is also read on the falling edge of SCLK.
The complete serial I/O cycle starts after the falling edge of FS/CS and ends 16 falling edges of SCLK later (see
NOTE). The serial interface works with CPOL = '1', CPHA = '0'. This setting means the falling edge of FS/CS
may fall while SCLK is high. The same timing relaxation applies to the rising edge of FS/CS where SCLK may be
high or low as long as the last SCLK falling edge happens before the rising edge of FS/CS.
NOTE
There are cases where a cycle can be anywhere from 4 SCLKs up to 24 SCLKs,
depending on the read mode combination. See Table 4 for details.
Internal Register
The internal register consists of two parts: four bits for the Command register (CMR) and 12 bits for the
Configuration register (CFR).
Table 4. Command Set Defined by Command Register (CMR)(1)
WAKE UP
FROM
MINIMUM
SCLKs
D[15:12]
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
HEX
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
COMMAND
Select analog input channel 0
Select analog input channel 1
Select analog input channel 2
Select analog input channel 3
Select analog input channel 4(2)
Select analog input channel 5(2)
Select analog input channel 6(2)
Select analog input channel 7(2)
Reserved
D[11:0]
Don't care
Don't care
Don't care
Don't care
Don't care
Don't care
Don't care
Don't care
Reserved
Reserved
Reserved
Don't care
Don't care
Don't care
CFR Value
AUTO-NAP
REQUIRED
R/W
W
W
W
W
W
W
W
W
—
—
—
W
R
Y
Y
4
4
Y
4
Y
4
Y
4
Y
4
Y
4
Y
4
—
—
—
Y
—
—
—
4
Reserved
Reserved
Wake up
Read CFR
—
—
—
16
16
16
Read data
R
Write CFR
W
Default mode
(load CFR with default value)
1111b
Fh
Don't care
Y
4
W
(1) The first four bits from SDO after the falling edge of FS/CS are the four MSBs from the previous conversion result. The next 12 bits from
SDO are the contents of the CFR.
(2) These commands apply only to the ADS8332; they are reserved (not availble) for the ADS8331.
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
27
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
www.ti.com
WRITING TO THE CONVERTER
There are two different types of writes to the register: a 4-bit write to the CMR and a full 16-bit write to the CMR
plus CFR. The command set is listed in Table 4 and the configuration register map is listed in Table 5. A simple
command requires only four SCLKs; the write takes effect on the fourth falling edge of SCLK. A 16-bit write or
read takes at least 16 SCLKs (see Table 7 for exceptions that require more than 16 SCLKs).
Configuring the Converter and Default Mode
The converter can be configured with command 1110b (write to the CFR) or command 1111b (default mode). A
write to the CFR requires a 4-bit command followed by 12 bits of data. A 4-bit command takes effect on the
fourth falling edge of SCLK. A write to the CFR takes effect on the 16th falling edge of SCLK.
The CFR default value for each bit is '1'. The default values are applied to the CFR after issuing command 1111b
or when the device is reset with a power-on reset (POR), software reset, or external reset using the RESET pin
(see the Reset Function section).
The communication protocol of the ADS8331/32 is full duplex. That is, data are transmitted to and from the
device simultaneously. For example, the input mux channel can be changed via the SDI pin while data are being
read via the SDO pin. All commands, except Read CFR, output conversion data on the SDO pin. If a Read CFR
command is issued, the Read Data command can then be used to read back the conversion result.
READING THE CONFIGURATION REGISTER
The host processor can read back the value programmed in the CFR by issuing command 1100b. The timing is
similar to reading a conversion result except CONVST is not used. There is also no activity on the EOC/INT pin.
The CFR value readback contains the first four bits (MSBs) of the previous conversion data plus the 12-bit CFR
contents.
Table 5. Configuration Register (CFR) Map
CFR SDI BIT
(Default = FFFh)
DEFINITION
Channel select mode
BIT = '0'
BIT = '1'
Manual channel select enabled. Use channel Auto channel select enabled. Channels are
D11
D10
select commands to access a desired
channel.
sampled and converted sequentially until the
cycle after this bit is set to 0.
Conversion clock (CCLK) source select
Conversion clock (CCLK) = SCLK/2
Conversion clock (CCLK) = internal OSC
Trigger (conversion start) select: start
conversion at the end of sampling (EOS). If
D9 = '0' and D8 = '0', the D4 setting is
ignored.
Auto-Trigger: conversions automatically start
three conversion clocks after EOC at
500kSPS
Manual-Trigger: conversions manually start
on falling edge of CONVST
D9
D8
D7
D6
D5
Sample rate for Auto-Trigger mode
500kSPS (21 CCLKs)
EOC/INT active high
Pin used as INT
250kSPS (42 CCLKs)
EOC/INT active low
Pin 10 polarity select when used as an
output (EOC/INT)
Pin 10 function select when used as an
output (EOC/INT)
Pin used as EOC
Pin 10 I/O select for daisy-chain mode
operation
Pin 10 is used as CDI input
(daisy-chain mode enabled)
Pin 10 is used as EOC/INT output
Auto-Nap Power-Down enable/disable.
This bit setting is ignored if D9 = '0' and D8
='0'.
Auto-Nap Power-Down mode enabled (not
activated)
D4
Auto-Nap Power-Down mode disabled
Nap Power-Down. This bit is set to 1
automatically by wake-up command.
Nap Power-Down disabled
(resume normal operation)
D3
D2
Nap Power-Down enabled
Deep Power-Down enabled
Deep Power-Down. This bit is set to 1
automatically by wake-up command.
Deep Power-Down disabled
(resume normal operation)
TAG bit output enabled. TAG bits appear
after conversion data
D1
D0
TAG bit output enable
Software reset
TAG bit output disabled
System reset, returns to '1' automatically
Normal operation
28
Submit Documentation Feedback
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
www.ti.com
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
READING THE CONVERSION RESULT
The conversion result is available to the input of the output data register (ODR) at EOC and presented to the
output of the output register at the next falling edge of FS/CS. The host processor can then shift the data out via
the SDO pin at any time except during the quiet zone. This duration is 20ns before and 20ns after the end of
sampling (EOS) period. End of sampling (EOS) is defined as the falling edge of CONVST when Manual-Trigger
mode is used or the end of the third conversion clock (CCLK) after EOC if Auto-Trigger mode is used.
The falling edge of FS/CS should not be placed at the precise moment at the end of a conversion (by default
when EOC goes high). Otherwise, the data could be corrupt. If FS/CS is placed before the end of a conversion,
the previous conversion result is read. If FS/CS is placed after the end of a conversion, the current conversion
result is read.
The conversion result is 16-bit data in straight binary format as shown in Table 6. Generally 16 SCLKs are
necessary, but there are exceptions when more than 16 SCLKs are required (see Table 7). Data output from the
serial output (SDO) is left-adjusted MSB first. The trailing bits are filled with three TAG bits first (if enabled) plus
all '0's. SDO remains low until FS/CS is brought high again.
SDO is active when FS/CS is low. The rising edge of FS/CS 3-states the SDO output.
NOTE
Whenever SDO is not in 3-state (that is, when FS/CS is low and SCLK is running), a
portion of the conversion result is output at the SDO pin. The number of bits depends on
how many SCLKs are supplied. For example, a manual channel select command cycle
requires 4 SCLKs. Therefore, four MSBs of the conversion result are output at SDO. The
exception is when SDO outputs all '1's during the cycle immediately after any reset (POR,
software reset, or external reset).
If SCLK is used as the conversion clock (CCLK) and a continuous SCLK is used, it is not possible to clock out all
16 bits from SDO during the sampling time (6 SCLKs) because of the quiet zone requirement. In this case, it is
better to read the conversion result during the conversion time (36 SCLKs or 48 SCLKs in Auto-Nap mode).
Table 6. Ideal Input Voltages and Output Codes
DESCRIPTION
Full-scale range
ANALOG VALUE
VREF
DIGITAL OUTPUT
STRAIGHT BINARY
Least significant bit (LSB)
Full-scale
VREF/65536
VREF – 1 LSB
VREF/2
BINARY CODE
HEX CODE
FFFF
1111 1111 1111 1111
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
Midscale
8000
Midscale – 1 LSB
Zero
VREF/2– 1 LSB
0 V
7FFF
0000
TAG Mode
The ADS8331/32 includes a TAG feature that can be used to indicate which channel sourced the converted
result. If TAG mode is enabled, three address bits are added after the LSB of the conversion data is read out
from SDO to indicate which channel corresponds to the result. These address bits are '000' for channel 0, '001'
for channel 1, '010' for channel 2, '011' for channel 3, '100' for channel 4, '101' for channel 5, '110' for channel 6,
and '111' for channel 7. The converter requires at least 19 SCLKs when TAG mode is enabled in order to
transfer the 16-bit conversion result and the three TAG bits.
Daisy-Chain Mode
The ADS8331/32 can operate as a single converter or in a system with multiple converters. System designers
can take advantage of the simple, high-speed, SPI-compatible serial interface by cascading converters in a
single chain when multiple converters are used. The CFR_D5 bit in the Configuration register is used to
reconfigure the EOC/INT status pin as the chain data input (CDI) pin, a secondary serial data input, for the
conversion result from an upstream converter. This configuration is called daisy-chain mode operation. A typical
connection of three converters in daisy-chain mode is shown in Figure 46.
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
29
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
www.ti.com
MICROCONTROLLER
CS3
INT
CS1
CS2
SDO SCLK
SDI
SDI
CONVST
CONVST
CONVST
SDO
SCLK
SCLK
SCLK
SDI
CS
SDI
CS
CS
ADS8331/32
#1
ADS8331/32
#2
ADS8331/32
#3
SDO
CDI
SDO
CDI
EOC/INT
Program Device #1: CFR_D5 = ‘1’
Program Devices #2 and #3: CFR_D5 = ‘0’
Figure 46. Multiple Converters Connected Using Daisy-Chain Mode
When multiple converters are used in daisy-chain mode, the first converter is configured in regular mode while
the rest of the converters downstream are configured in daisy-chain mode. When a converter is configured in
daisy-chain mode, the CDI input data go straight to the output register. Therefore, the serial input data passes
through the converter with either a 16 SCLK (if the TAG feature is disabled) or 24 SCLK delay, as long as CS is
active. See Figure 47 for detailed timing. In this timing diagram, the conversion in each converter is performed
simultaneously.
Manual Trigger, Read While Sampling
(Use internal CCLK, EOC active low, and TAG mode disabled)
CONVST #1
CONVST #2
CONVST #3
EOC #1
(active low)
Conversion N
tCONV = 18 CCLK
tSAMPLE1 = 3 CCLK min
tSU2
CS #1
SCLK #1
SCLK #2
SCLK #3
1. . . . . . . . . . . . . .16
1. . . . . . . . . . . . . .16
1. . . . . . . . . . . . . .16
High-Z
tSU2
High-Z
SDO #1
CDI #2
Conversion N
from Device #1
CS #2
CS #3
High-Z
High-Z
High-Z
High-Z
SDO #2
CDI #3
Conversion N
from Device #2
Conversion N
from Device #1
SDO #3
Conversion N
from Device #3
Conversion N
from Device #2
Conversion N
from Device #1
SDI #1
SDI #2
SDI #3
Don't Care
Configure
Read Data
Read Data
Don't Care
Figure 47. Simplified Dasiy-Chain Mode Timing with Shared CONVST and Continuous CS
The multiple CS signals must be handled with care when the converters are operating in daisy-chain mode. The
different chip select signals must be low for the entire data transfer (in this example, 48 bits for three
conversions). The first 16-bit word after the falling chip select is always the data from the chip that received the
chip select signal.
30
Submit Documentation Feedback
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
www.ti.com
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
Case 1: If chip select is not toggled (CS stays low), the next 16 bits of data are from the upstream converter, and
so on. This configuration is shown in Figure 47.
Case 2: If the chip select is toggled during a daisy-chain mode data transfer cycle, as illustrated in Figure 48, the
same data from the converter are read out again and again in all three discrete 16-bit cycles. This state is not a
desired result.
Manual Trigger, Read While Sampling
(Use internal CCLK, EOC active low, and TAG mode disabled)
CONVST #1
CONVST #2
CONVST #3
EOC #1
(active low)
Conversion N
tCONV = 18 CCLK
tSAMPLE1 = 3 CCLK min
tWH1
tSU2
tWH1
CS #1
SCLK #1
SCLK #2
SCLK #3
1. . . . . . . . . . . . . .16
1. . . . . . . . . . . . . .16
1. . . . . . . . . . . . . .16
High-Z
tWH1
High-Z
tWH1
High-Z
tSU2
High-Z
SDO #1
CDI #2
Conversion N
from Device #1
Conversion N
from Device #1
Conversion N
from Device #1
CS #2
CS #3
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
SDO #2
CDI #3
Conversion N
from Device #2
Conversion N
from Device #2
Conversion N
from Device #2
SDO #3
Conversion N
from Device #3
Conversion N
from Device #3
Conversion N
from Device #3
SDI #1
SDI #2
SDI #3
Don't Care
Don't Care
Don't Care
Configure
Read Data
Read Data
Don't Care
Figure 48. Simplified Daisy-Chain Mode Timing with Shared CONVST and Noncontinuous CS
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
31
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
www.ti.com
Figure 49 shows a slightly different scenario where CONVST is not shared with the second converter. Converters
#1 and #3 have the same CONVST signal. In this case, converter #2 simply passes previous conversion data
downstream.
Manual Trigger, Read While Sampling
(Use internal CCLK, EOC active low, and TAG mode disabled)
CONVST #1
CONVST #3
CONVST #2
EOC #1
(active low)
Conversion N
tCONV = 18 CCLK
tSAMPLE1 = 3 CCLK min
tSU2
CS #1
SCLK #1
SCLK #2
SCLK #3
1. . . . . . . . . . . . . .16
1. . . . . . . . . . . . . .16
1. . . . . . . . . . . . . .16
High-Z
tSU2
High-Z
SDO #1
CDI #2
Conversion N
from Device #1
CS #2
CS #3
High-Z
High-Z
High-Z
High-Z
SDO #2
CDI #3
Conversion (N - 1)
from Device #2(1)
Conversion N
from Device #1
SDO #3
Conversion N
Conversion (N - 1)
from Device #2(1)
Conversion N
from Device #3
from Device #1
SDI #1
SDI #2
SDI #3
Don't Care
Configure
Read Data
Read Data
Don't Care
(1) Data from device #2 is from previous converison.
Figure 49. Simplified Daisy-Chain Mode Timing with Separate CONVST and Continuous CS
The number of SCLKs required for a serial read cycle depends on the combination of different read modes, TAG
mode, daisy-chain mode, and the manner in which a channel is selected (for example, Auto Channel Select
mode). The required number of SCLKs for different readout modes are listed in Table 7.
Table 7. Required SCLKs For Different Readout Mode Combinations
DAISY-CHAIN MODE
CFR_D5
TAG MODE
CFR_D1
NUMBER OF SCLK CYCLES
PER SPI READ
TRAILING BITS
1
1
0
0
0
1
0
1
16
≥ 19
16
None
TAG bits plus up to 5 zeros
None
24
TAG bits plus 5 zeros
32
Submit Documentation Feedback
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
www.ti.com
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
SCLK skew between converters in a daisy-chain configuration can affect the maximum frequency of SCLK. The
skew can also be affected by supply voltage and loading. It may be necessary to slow down the SCLK when the
devices are configured in daisy-chain mode.
RESET FUNCTION
The ADS8331/32 can be reset with three different methods: internal POR, software reset, and external reset
using the RESET pin.
The internal POR circuit is activated when power is initially applied to the converter. This internal circuit
eliminates the need for commands to be sent to the converter after power-on in order to set the default mode of
operation (see the Power-On Sequence Timing section for further details).
Software reset can be used to place the converter in the default mode by setting the CFR_D0 bit to '0' in the
Configuration register (see Table 5). This bit is automatically returned to '1' (default) after the converter is reset.
This reset method is useful in systems that cannot dedicate a separate control signal to the RESET pin. In these
situations, the RESET pin must be connected to VBD in order for the ADS8331/32 to operate properly.
If communication in the system becomes corrupted and a software reset cannot be issued, the RESET pin can
be used to reset the device manually. In order to reset the device and return the device to default mode, this pin
must held low for a minimum of 25ns.
After the ADS8331/32 detects a reset condition, the minimum time before the device can be reconfigured by
FS/CS going low and data clocking in on SDI is 2ms.
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
33
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
www.ti.com
APPLICATION INFORMATION
TYPICAL CONFIGURATION EXAMPLE
Figure 50 illustrates a typical circuit configuration using the ADS8331/32.
Analog +5V
4.7mF
External
Reference
Input
AGND
22mF
Analog Input
AGND
REF+ REF- AGND
ADCIN
COM
INX
MUXOUT
VA
Interface
Supply
+1.8V
FS/CS
SDO
SDI
4.7mF
SCLK
DGND
VBD
Host
Processor
ADS8331/32
CONVST
EOC/INT
Figure 50. Typical Circuit Configuration
POWER-ON SEQUENCE TIMING
During power-on of the ADS8331/32, the digital interface supply voltage (VBD) should not exceed the analog
supply voltage (VA). This condition is specified in the Power-Supply Requirements section of the Electrical
Characteristics tables. If the analog and digital interface supplies for the converter are not generated by a single
voltage source, it is recommended to power-on the analog supply and wait for it to reach its final value before the
digital interface supply is activated. Furthermore, the voltages applied to the analog input pins (INX, ADCIN) and
digital input pins (RESET, FS/CS, SCLK, SDI, and CONVST) should not exceed the voltages on VA and VBD,
respectively, during the power-on sequence. This requirement prevents these input pins from powering the
ADS8331/32 through the ESD protection diodes/circuitry, and causing an increase in current consumption, until
both supplies are fully powered (see the Electrical Characteristics and Figure 34 for further details).
Communication with the ADS8331/32, such as initiating a conversion with CONVST or writing to the
Configuration register, should not occur for a minimum of 2ms after the analog and digital interface supplies have
finished the power-on sequence and reached the respective final values in the system. This time is required for
the internal POR to activate and place the digital core of the device into the default mode of operation. This
minimum delay time must also be adhered to whenever a reset condition occurs (see the Reset Function section
for additional information).
34
Submit Documentation Feedback
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
www.ti.com
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
LAYOUT
For optimum performance, care should be taken with the physical layout of the ADS8331/32 circuitry. This
consideration is particularly true if the reference voltage is low and/or the conversion rate is high. With a
conversion clock of 12MHz, the ADS8331/32 makes a bit decision every 83ns. That is, for each subsequent bit
decision, the capacitor array must be switched and charged, and the input to the comparator settled to a 16-bit
level, all within one conversion clock cycle.
The basic SAR architecture is sensitive to spikes on the power supply, reference, and ground connections that
occur just prior to latching the comparator output. Thus, during any single conversion for an n-bit SAR converter,
there are n windows in which large external transient voltages can easily affect the conversion result. Such
spikes might originate from switching power supplies, digital logic, and high-power devices, to name a few
potential sources. This particular source of error can be very difficult to track down if the glitch is almost
synchronous to the converter CCLK signal because the phase difference between the two changes with time and
temperature, causing sporadic misoperation.
With this possibility in mind, power to the ADS8331/32 should be clean and well-bypassed. A 0.1mF ceramic
bypass capacitor should be placed as close as possible to the ADS8331/32 package. In addition, a 1mF to 10mF
capacitor and a 5Ω or 10Ω series resistor may be used to low-pass filter a noisy supply.
The reference should be similarly bypassed with a 22mF capacitor. Again, a series resistor and large capacitor
can be used to low-pass filter the reference voltage. If the reference voltage originates from an op amp, make
sure that the op amp can drive the bypass capacitor without oscillation (the series resistor can help in this case).
Although the ADS8331/32 draws very little current from the reference on average, there can still be
instantaneous current demands placed on the external input and reference circuitry.
The OPA365 or OPA211 from Texas Instrumets provide optimum performance for buffering the signal inputs; the
OPA350 can be used to effectively buffer the reference input.
Also, keep in mind that the ADS8331/32 offers no inherent rejection of noise or voltage variation in regards to the
reference input. This consideration is of particular concern when the reference input is tied to the power supply.
Any noise and ripple from the supply will appear directly in the digital results. While high-frequency noise can be
filtered, voltage variation resulting from the line frequency (50Hz or 60Hz) can be difficult to remove.
The AGND pin on the ADS8331/32 should be placed on a clean ground point. In many cases, this location is the
analog ground. Avoid connecting the AGND pin too close to the grounding point for a microprocessor,
microcontroller, or digital signal processor. If needed, run a ground trace directly from the converter to the
power-supply connection point. The ideal layout includes an analog ground plane for the converter and
associated analog circuitry.
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
35
Product Folder Link(s): ADS8331 ADS8332
ADS8331
ADS8332
SBAS363B –DECEMBER 2009–REVISED DECEMBER 2010
www.ti.com
REVISION HISTORY
NOTE: Page numbers from previous revisions may differ from the page numbers in the current version.
Changes from Revision A (November 2010) to Revision B
Page
•
Deleted Ordering Information table ....................................................................................................................................... 2
Changes from Original (December 2009) to Revision A
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Changed two part numbers for 500kSPS, 14-Bit Pseudo-Diff converter in SAR Converter Family table ............................ 1
Deleted availability date for release of TSSOP package ...................................................................................................... 1
Changed BDGND to DGND in Absolute Maximum Ratings ................................................................................................. 2
Deleted Aperture Delay, Aperture Jitter, Step Response, and Overvoltage Recovery parameters from 2.7V table ........... 3
Changed Input Leakage Current parameter for 2.7V table .................................................................................................. 3
Changed Offset Error Matching parameter for 2.7V table .................................................................................................... 3
Changed High-Level Input Voltage parameter and values for 2.7V table ............................................................................ 4
Changed Low-Level Input Voltage parameter and values for 2.7V table ............................................................................. 4
Changed Input Current parameter values from –50 (min) and 50 (max) to –1 (min) and 1 (max) for 2.7V table ................ 4
Changed Power Dissipation maximum value from 18.2 to 18.6 for 2.7V table .................................................................... 4
Deleted Aperture Delay, Aperture Jitter, Step Response, and Overvoltage Recovery parameters from 5V table .............. 5
Changed Input Leakage Current parameter for 5V table ..................................................................................................... 5
Changed Offset Error Matching parameter for 5V table ....................................................................................................... 5
Changed High-Level Input Voltage parameter and values for 5V table ............................................................................... 6
Changed Low-Level Input Voltage parameters and values for 5V table .............................................................................. 6
Changed Input Current parameter values from –50 (min) and 50 (max) to –1 (min) and 1 (max) for 5V table ................... 6
Changed 2.7V Timing Characteristics table ......................................................................................................................... 7
Changed 5V Timing Characteristics table ............................................................................................................................ 8
Changed Figure 2 ................................................................................................................................................................. 9
Changed Figure 3 ................................................................................................................................................................. 9
Changed Figure 34 ............................................................................................................................................................. 18
Added new paragraph to the end of the Configuring the Converter and Default Mode section ......................................... 28
Deleted Figure 50 and changed text in first paragraph ...................................................................................................... 33
Changed text in last sentence of first paragraph in Power-On Sequence Timing section ................................................. 34
36
Submit Documentation Feedback
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8331 ADS8332
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jan-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ADS8331IBPW
ADS8331IBPWR
ADS8331IBRGER
ADS8331IBRGET
ADS8331IPW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
VQFN
PW
PW
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
2000
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
RGE
RGE
PW
Green (RoHS
& no Sb/Br)
Request Free Samples
VQFN
Green (RoHS
& no Sb/Br)
Contact TI Distributor
or Sales Office
TSSOP
TSSOP
VQFN
60
Green (RoHS
& no Sb/Br)
Request Free Samples
ADS8331IPWR
ADS8331IRGER
ADS8331IRGET
ADS8332IBPW
ADS8332IBPWR
ADS8332IBRGER
ADS8332IBRGET
ADS8332IPW
PW
2000
3000
250
Green (RoHS
& no Sb/Br)
Purchase Samples
RGE
RGE
PW
Green (RoHS
& no Sb/Br)
Request Free Samples
Request Free Samples
Purchase Samples
VQFN
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
VQFN
60
Green (RoHS
& no Sb/Br)
PW
2000
3000
250
Green (RoHS
& no Sb/Br)
Purchase Samples
RGE
RGE
PW
Green (RoHS
& no Sb/Br)
Purchase Samples
VQFN
Green (RoHS
& no Sb/Br)
Request Free Samples
Request Free Samples
Purchase Samples
TSSOP
TSSOP
VQFN
60
Green (RoHS
& no Sb/Br)
ADS8332IPWR
ADS8332IRGER
ADS8332IRGET
PW
2000
3000
250
Green (RoHS
& no Sb/Br)
RGE
RGE
Green (RoHS
& no Sb/Br)
Purchase Samples
VQFN
Green (RoHS
& no Sb/Br)
Request Free Samples
(1) The marketing status values are defined as follows:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jan-2011
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jan-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS8331IBPWR
ADS8331IBRGER
ADS8331IBRGET
ADS8331IPWR
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
PW
RGE
RGE
PW
24
24
24
24
24
24
24
24
24
24
24
24
2000
3000
250
330.0
330.0
180.0
330.0
330.0
180.0
330.0
330.0
180.0
330.0
330.0
180.0
16.4
12.4
12.4
16.4
12.4
12.4
16.4
12.4
12.4
16.4
12.4
12.4
6.95
4.25
4.25
6.95
4.25
4.25
6.95
4.25
4.25
6.95
4.25
4.25
8.3
4.25
4.25
8.3
1.6
1.15
1.15
1.6
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
16.0
12.0
12.0
16.0
12.0
12.0
16.0
12.0
12.0
16.0
12.0
12.0
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q2
Q2
2000
3000
250
ADS8331IRGER
ADS8331IRGET
ADS8332IBPWR
ADS8332IBRGER
ADS8332IBRGET
ADS8332IPWR
RGE
RGE
PW
4.25
4.25
8.3
1.15
1.15
1.6
2000
3000
250
RGE
RGE
PW
4.25
4.25
8.3
1.15
1.15
1.6
2000
3000
250
ADS8332IRGER
ADS8332IRGET
RGE
RGE
4.25
4.25
1.15
1.15
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jan-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS8331IBPWR
ADS8331IBRGER
ADS8331IBRGET
ADS8331IPWR
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
PW
RGE
RGE
PW
24
24
24
24
24
24
24
24
24
24
24
24
2000
3000
250
346.0
346.0
190.5
346.0
346.0
190.5
346.0
346.0
190.5
346.0
346.0
190.5
346.0
346.0
212.7
346.0
346.0
212.7
346.0
346.0
212.7
346.0
346.0
212.7
33.0
29.0
31.8
33.0
29.0
31.8
33.0
29.0
31.8
33.0
29.0
31.8
2000
3000
250
ADS8331IRGER
ADS8331IRGET
ADS8332IBPWR
ADS8332IBRGER
ADS8332IBRGET
ADS8332IPWR
RGE
RGE
PW
2000
3000
250
RGE
RGE
PW
2000
3000
250
ADS8332IRGER
ADS8332IRGET
RGE
RGE
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
www.ti.com/industrial
www.ti.com/medical
www.ti.com/security
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
Medical
Security
Logic
Space, Avionics and Defense www.ti.com/space-avionics-defense
Power Mgmt
power.ti.com
Transportation and
Automotive
www.ti.com/automotive
Microcontrollers
RFID
microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
Wireless
www.ti.com/video
www.ti.com/wireless-apps
RF/IF and ZigBee® Solutions www.ti.com/lprf
TI E2E Community Home Page
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2011, Texas Instruments Incorporated
相关型号：
ADS8332
Low-Power, 16-Bit, 500kSPS, 4-/8-Channel Unipolar Input ANALOG-TO-DIGITAL CONVERTERS with Serial Interface
TI
ADS8332I
Low-Power, 16-Bit, 500kSPS, 4-/8-Channel Unipolar Input ANALOG-TO-DIGITAL CONVERTERS with Serial Interface
TI
ADS8332IB
Low-Power, 16-Bit, 500kSPS, 4-/8-Channel Unipolar Input ANALOG-TO-DIGITAL CONVERTERS with Serial Interface
TI
ADS8332IBPW
Low-Power, 16-Bit, 500kSPS, 4-/8-Channel Unipolar Input ANALOG-TO-DIGITAL CONVERTERS with Serial Interface
TI
ADS8332IBPWR
Low-Power, 16-Bit, 500kSPS, 4-/8-Channel Unipolar Input ANALOG-TO-DIGITAL CONVERTERS with Serial Interface
TI
ADS8332IBPWT
Low-Power, 16-Bit, 500kSPS, 4-/8-Channel Unipolar Input ANALOG-TO-DIGITAL CONVERTERS with Serial Interface
TI
ADS8332IBRGER
Low-Power, 16-Bit, 500kSPS, 4-/8-Channel Unipolar Input ANALOG-TO-DIGITAL CONVERTERS with Serial Interface
TI
ADS8332IBRGET
Low-Power, 16-Bit, 500kSPS, 4-/8-Channel Unipolar Input ANALOG-TO-DIGITAL CONVERTERS with Serial Interface
TI
ADS8332IPW
Low-Power, 16-Bit, 500kSPS, 4-/8-Channel Unipolar Input ANALOG-TO-DIGITAL CONVERTERS with Serial Interface
TI
ADS8332IPWR
Low-Power, 16-Bit, 500kSPS, 4-/8-Channel Unipolar Input ANALOG-TO-DIGITAL CONVERTERS with Serial Interface
TI
ADS8332IPWT
Low-Power, 16-Bit, 500kSPS, 4-/8-Channel Unipolar Input ANALOG-TO-DIGITAL CONVERTERS with Serial Interface
TI
ADS8332IRGER
Low-Power, 16-Bit, 500kSPS, 4-/8-Channel Unipolar Input ANALOG-TO-DIGITAL CONVERTERS with Serial Interface
TI
©2020 ICPDF网 联系我们和版权申明