ADS8372IBRHPT [TI]
具有基准电压和伪双极性、全差分输入的 16 位 600KSPS 串行 ADC | RHP | 28 | -40 to 85;
| 型号： | ADS8372IBRHPT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有基准电压和伪双极性、全差分输入的 16 位 600KSPS 串行 ADC | RHP | 28 | -40 to 85 转换器 |
| 文件： | 总33页 (文件大小：859K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS8372
SLAS451–JUNE 2005
16-BIT, 600-kHz, FULLY DIFFERENTIAL PSEUDO-BIPOLAR INPUT,
MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL INTERFACE AND REFERENCE
FEATURES
•
Pin Compatible With 18-Bit ADS8382
•
•
•
•
•
•
•
•
•
•
•
•
•
600-kHz Sample Rate
APPLICATIONS
±0.35 LSB Typ, ±0.75 LSB Max INL
±0.25 LSB Typ, ±0.5 LSB Max DNL
16-Bit NMC
•
•
•
•
•
Medical Instruments
Optical Networking
Transducer Interface
High Accuracy Data Acquisition Systems
Magnetometers
SINAD 93.5 dB, SFDR 120 dB at fi = 1 kHz
High-Speed Serial Interface up to 40 MHz
Onboard Reference Buffer
Onboard 4.096-V Reference
Pseudo-Bipolar Input, up to ±4.2 V
Onboard Conversion Clock
Zero Latency
Wide Digital Supply
Low Power
– 110 mW at 600 kHz
DESCRIPTION
The ADS8372 is a high performance 16-bit, 600-kHz
A/D converter with fully differential, pseudo-bipolar
input. The device includes an 16-bit capacitor-based
SAR A/D converter with inherent sample and hold.
The ADS8372 offers a high-speed CMOS serial
interface with clock speeds up to 40 MHz.
– 15 mW During Nap Mode
– 10 µW During Power Down
28-Pin 6 × 6 QFN Package
The ADS8372 is available in a 28 lead 6 × 6 QFN
package and is characterized over the industrial
–40°C to 85°C temperature range.
•
High Speed SAR Converter Family
Type/Speed
18-Bit Pseudo-Diff
500 kHz
~ 600 kHz
ADS8381
750 kHZ
1 MHz
1.25 MHz
2 MHz
3 MHz
4 MHz
ADS8383
ADS8380 (S)
ADS8382 (S)
18-Bit Pseudo-Bipolar, Fully Diff
16-Bit Pseudo-Diff
ADS8370 (S) ADS8371
ADS8372 (S)
ADS8401/05 ADS8411
ADS8402/06 ADS8412
ADS7890 (S)
16-Bit Pseudo-Bipolar, Fully Diff
14-Bit Pseudo-Diff
ADS7891
12-Bit Pseudo-Diff
ADS7886
ADS7881
FS
Output
Latches
and
3-State
Drivers
SAR
SCLK
SDO
+
_
+IN
−IN
CDAC
Comparator
Clock
REFIN
CS
CONVST
BUSY
PD
Conversion
and
Control Logic
4.096-V
Internal
Reference
REFOUT
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS8372
www.ti.com
SLAS451–JUNE 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
NO
MISSING
CODES
RESOLUTION
(BIT)
MAXIMUM
INTEGRAL DIFFERENTIAL
LINEARITY
(LSB)
MAXIMUM
TEMPERATUR
TRANSPORT
MEDIA
QUANTITY
PACKAGE
TYPE
PACKAGE
DESIGNATOR
ORDERING
INFORMATION
MODEL
E
LINEARITY
(LSB)
RANGE
Small Tape and
Reel 250
ADS8372IRHPT
ADS8372IRHPR
ADS8372IBRHPT
ADS8372IBRHPR
28 Pin
6×6 QFN
ADS8372I
±1.5
±1
16
16
RHP
RHP
-40°C to 85°C
-40°C to 85°C
Tape and Reel
2500
Small Tape and
Reel 250
28 Pin
6×6 QFN
ADS8372IB
±0.75
±0.5
Tape and
Reel 2500
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
+IN to AGND
–IN to AGND
+VA to AGND
+VBD to BDGND
–0.3 V to +VA + 0.3 V
–0.3 V to +VA + 0.3 V
–0.3 V to 6 V
–0.3 V to 6 V
–0.3 V to +VBD + 0.3 V
+0.3 V
Voltage
Digital input voltage to BDGND
Digital input voltage to +VA
Operating free-air temperature range, TA
Storage temperature range, Tstg
Junction temperature (TJ max)
–40°C to 85°C
–65°C to 150°C
150°C
Power dissipation
(TJ max – TA)/θJA
86°C/W
QFN package
θJA thermal impedance
Vapor phase (60 sec)
Infrared (15 sec)
215°C
Lead temperature, soldering
220°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
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SLAS451–JUNE 2005
SPECIFICATIONS
At –40°C to 85°C, +VA = +5 V, +VBD = +5 V or +VBD = +2.7 V, using internal or external reference, fSAMPLE = 600 kHz,
unless otherwise noted. (All performance parameters are valid only after device has properly resumed from power down,
Table 2.)
ADS8372IB
ADS8372I
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
MAX
ANALOG INPUT
Full-scale
input voltage(1)
+IN – (–IN)
–Vref
Vref
–Vref
Vref
V
+IN
–IN
–0.2
–0.2
Vref + 0.2
Vref + 0.2
–0.2
–0.2
Vref + 0.2
Vref + 0.2
Absolute input voltage
V
V
Input common mode range
(Vref/2) –0.2
(Vref/2) +0.2 (Vref/2) –0.2
(Vref/2) +0.2
Sampling capacitance
(measured between +IN to
AGND and -IN to AGND)
40
1
40
1
pF
nA
Input leakage current
SYSTEM PERFORMANCE
Resolution
16
16
Bits
Bits
No missing codes
16
16
Quiet zones observed
Quiet zones not observed
Quiet zones observed
Quiet zones not observed
0.75
±0.35
±0.75
±0.25
±0.5
0.75
0.5
–1.5
1.5
1
LSB
(16 bit)
INL
Integral linearity(2)(3)(4)
Differential linearity(3)
–0.5
–0.75
–1
LSB
(16 bit)
DNL
EO
Offset error(3)
±0.25
±0.2
0.75
0.075
–1.5
–0.15
1.5
0.15
mV
ppm/°C
%FS
(3)
Offset temperature drift
Gain error(3)(5)
±0.2
EG
–0.075
Gain error temperature
drift(3)(5)
±1.5
80
±1.5
80
ppm/°C
At DC
CMRR Common-mode rejection ratio
dB
[+IN + (–IN)]/2 = 50 mVp-p
at 1 MHz + DC of Vref/2
55
55
Noise
At 00000H output code
At 10000H output code
40
40
µV RMS
DC Power supply rejection
PSRR
ratio
55
55
dB
SAMPLING DYNAMICS
Conversion time
Acquisition time
Throughput rate
Aperture delay
1.0
0.5
1.16
600
1.0
0.5
1.16
600
µs
µs
kHz
ns
10
12
10
12
Aperture jitter
ps RMS
ns
(6)
Step response
400
400
400
400
Overvoltage recovery
ns
(1) Ideal input span; does not include gain or offset error.
(2) LSB means least significant bit.
(3) Measured using analog input circuit in Figure 52 and digital stimulus in Figure 56 and Figure 57 and reference voltage of 4.096 V.
(4) This is endpoint INL, not best fit.
(5) Measured using external reference source so does not include internal reference voltage error or drift.
(6) Defined as sampling time necessary to settle an initial error of 2Vref on the sampling capacitor to a final error of 1 LSB at 16-bit level.
Measured using the input circuit in Figure 52.
3
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SLAS451–JUNE 2005
SPECIFICATIONS (continued)
At –40°C to 85°C, +VA = +5 V, +VBD = +5 V or +VBD = +2.7 V, using internal or external reference, fSAMPLE = 600 kHz,
unless otherwise noted. (All performance parameters are valid only after device has properly resumed from power down,
Table 2.)
ADS8372IB
ADS8372I
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
MAX
DYNAMIC CHARACTERISTICS
VIN = 8 Vp-p at 1 kHz
VIN = 8 Vp-p at 10 kHz
VIN = 8 Vp-p at 100 kHz
VIN = 8 Vp-p at 1 kHz
VIN = 8 Vp-p at 10 kHz
VIN = 8 Vp-p at 100 kHz
VIN = 8 Vp-p at 1 kHz
VIN = 8 Vp-p at 10 kHz
VIN = 8 Vp-p at 100 kHz
VIN = 8 Vp-p at 1 kHz
VIN = 8 Vp-p at 10 kHz
VIN = 8 Vp-p at 100 kHz
–116
–115
–98
93.5
93.5
92
–106
–116
–115
–98
93.5
93.5
92
Total harmonic
THD
dB
dB
dB
distortion(7)(8)
92
92
SNR
Signal-to-noise ratio(7)
93.5
93.5
91
93.5
93.5
91
Signal-to-noise
+ distortion(7)(8)
SINAD
SFDR
120
120
99
120
120
99
Spurious free dynamic
range(7)
dB
–3dB Small signal bandwidth
75
75
MHz
REFERENCE INPUT
Vref Reference voltage input range
Resistance(9)
INTERNAL REFERENCE OUTPUT
2.5
4.096
10
4.2
2.5
4.096
10
4.2
V
MΩ
Vref
Reference voltage range
Source current
Line regulation
Drift
IOUT = 0 A, TA = 30°C
Static load
4.088
4.096
4.104
10
4.088
4.096
4.104
10
V
µA
+VA = 4.75 V to 5.25 V
IOUT = 0 A
2.5
25
2.5
25
mV
ppm/°C
DIGITAL INPUT/OUTPUT
Logic family CMOS
VIH
VIL
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
+VBD – 1
–0.3
+VBD + 0.3
0.8
+VBD – 1
–0.3
+VBD + 0.3
0.8
V
V
V
V
VOH
VOL
IOH = 2 TTL loads
IOL = 2 TTL loads
+VBD –0.6
+VBD –0.6
0.4
0.4
Data format 2's complement (MSB first)
POWER SUPPLY REQUIREMENTS
+VA
4.75
2.7
5
5.25
5.25
4.75
2.7
5
5.25
5.25
V
V
Power supply
voltage
+VBD
3.3
3.3
Supply current, 600-kHz
sample rate(10)
ICC
+VA = 5 V
22
25
22
25
mA
POWER DOWN
ICC(PD)
Supply current, power down
2
3
2
3
µA
NAP MODE
ICC(NAP) Supply current, nap mode
Power-up time from nap
TEMPERATURE RANGE
Specified performance
mA
ns
300
85
300
85
–40
–40
°C
(7) Measured using analog input circuit in Figure 52 and digital stimulus in Figure 56 and Figure 57 and reference voltage of 4.096 V.
(8) Calculated on the first nine harmonics of the input frequency.
(9) Can vary +/-30%.
(10) This includes only +VA current. With +VBD = 5 V, +VBD current is typically 1 mA with a 10-pF load capacitance on the digital output
pins.
4
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SLAS451–JUNE 2005
TIMING REQUIREMENTS(1)(2)(3)(4)(5)(6)
ADS8372I/ADS8372IB
REF
UNIT
PARAMETER
FIGURE
MIN
1000
0.5
TYP
MAX
tconv
tacq1
tacq2
Conversion time
1160
ns
µs
µs
41– 44
41,42,44
43
Acquisition time in normal mode
Acquisition time in nap mode (tacq2 = tacq1 + td18
)
0.8
CONVERSION AND SAMPLING
Quite sampling time (last toggle of interface signals to convert start
command)(6)
40 – 43,
45 – 47
tquiet1
tquiet2
tquiet3
30
10
ns
ns
ns
Quite sampling time (convert start command to first toggle of interface
signals)(6)
Quite conversion time (last toggle of interface signals to fall of BUSY)(6)
40 – 43,
45 – 47
40 – 43
45,47
600
tsu1
tsu2
tsu4
th1
Setup time, CONVST before BUSY fall
15
20
5
ns
ns
ns
ns
ns
ns
ns
ns
41
40,41
41,43,44
41
Setup time, CS before BUSY fall (only for conversion/sampling control)
Setup time, CONVST before CS rise (so CONVST can be recognized)
Hold time, CS after BUSY fall (only for conversion/sampling control)
Hold time, CONVST after CS rise
0
th3
7
43
th4
Hold time, CONVST after CS fall (to ensure width of CONVST_QUAL)(4)
20
20
10
42
tw1
tw2
CONVST pulse duration
43
CS pulse duration
41,42
Pulse duration, time between conversion start command and conversion
abort command to successfully abort the ongoing conversion
tw5
1000
60%
ns
44
DATA READ OPERATION
tcyc
SCLK period
25
40%
10
7
ns
45 – 47
SCLK duty cycle
tsu5
tsu6
tsu7
th5
Setup time, CS fall before first SCLK fall
Setup time, CS fall before FS rise
Setup time, FS fall before first SCLK fall
Hold time, CS fall after SCLK fall
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
46,47
46,47
45
7
3
th6
Hold time, FS fall after SCLK fall
7
46,47
40,45
40,47
40,45
40,47
45
tsu2
tsu3
th2
Setup time, CS fall before BUSY fall (only for read control)
Setup time, FS fall before BUSY fall (only for read control)
Hold time, CS fall after BUSY fall (only for read control)
Hold time, FS fall after BUSY fall (only for read control)
CS pulse duration
20
20
15
15
10
10
th8
tw2
tw3
FS pulse duration
46,47
MISCELLANEOUS
tw4 PD pulse duration for reset and power down
All unspecified pulse durations
60
10
ns
ns
53,54
(1) All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2) All specifications typical at –40°C to 85°C, +VA = +4.75 V to +5.25 V, +VBD = +2.7 V to +5.25 V.
(3) All digital output signals loaded with 10-pF capacitors.
(4) CONVST_QUAL is CONVST latched by a low value on CS (see Figure 39).
(5) Reference figure indicated is only a representative of where the timing is applicable and is not exhaustive.
(6) Quiet time zones are for meeting performance and not functionality.
5
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SLAS451–JUNE 2005
TIMING CHARACTERISTICS(1)(2)(3)(4)
ADS8372I/ADS8372IB
REF
FIGURE
PARAMETER
UNIT
MIN TYP
MAX
CONVERSION AND SAMPLING
td1 Delay time, conversion start command to conversion start (aperture delay)
td2 Delay time, conversion end to BUSY fall
td4 Delay time, conversion start command to BUSY rise
td3 Delay time, CONVST rise to sample start
td5 Delay time, CS fall to sample start
td6 Delay time, conversion abort command to BUSY fall
DATA READ OPERATION
10 ns
ns
20 ns
ns
41,43
41 – 43
41
5
5
43
10 ns
10 ns
43
44
td12 Delay time, CS fall to MSB valid
3
6
15 ns
18 ns
18 ns
10 ns
45
46,47
47
td15 Delay time, FS rise to MSB valid
td7 Delay time, BUSY fall to MSB valid (if FS is high when BUSY falls)
td13 Delay time, SCLK rise to bit valid
2
45 – 47
45
td14 Delay time, CS rise to SDO 3-state
MISCELLANEOUS
6
ns
td10 Delay time, PD rise to SDO 3-state
Nap mode
55 ns
53,54
55
300 ns
Delay time, total
td18 device resume
time
Full power down (external reference used with or without
1-µF||0.1-µF capacitor on REFOUT)
td11 + 2x
conversions
54
53
Full power down (internal reference used with or without
1-µF||0.1-µF capacitor on REFOUT)
25(4) ms
td11 Delay time, untrimmed circuit full power-down resume time
1
4
ms
ns
µs
53,54
55
Delay time, device Nap
power-down time
200
10
td16
Full power down (internal/external reference used)
53,54
Delay time, trimmed internal reference settling (either by turning on supply or
resuming from full power-down mode), with 1-µF||0.1-µF capacitor on REFOUT
td17
ms
53
(1) All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2) All specifications typical at –40°C to 85°C, +VA = +4.75 V to +5.25 V, +VBD = +2.7 V to +5.25 V.
(3) All digital output signals loaded with 10-pF capacitors.
(4) Including td11, two conversions (time to cycle CONVST twice), and td17
.
6
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SLAS451–JUNE 2005
PIN ASSIGNMENTS
TOP VIEW
BDGND
1
2
3
4
5
6
7
21
20
19
18
17
16
15
AGND
AGND
+VA
+VBD
AGND
ADS8372
AGND
AGND
+VA
AGND
+VA
+VA
AGND
REFM
Note: The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
TERMINAL FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
AGND
BDGND
NO.
1, 2, 4, 5, 15, 18, 19
21
–
–
Analog ground pins. AGND must be shorted to analog ground plane below the device.
Digital ground for all digital inputs and outputs. BDGND must be shorted to the analog ground
plane below the device.
BUSY
CONVST
CS
22
25
O
I
Status output. This pin is high when conversion is in progress.
Convert start. This signal is qualified with CS internally.
Chip select
26
I
FS
27
I
Frame sync. This signal is qualified with CS internally.
Noninverting analog input channel
+IN
11
I
–IN
12
I
Inverting analog input channel
NC
10, 13
28
–
I
No connection
PD
Power down. Device resets and powers down when this signal is high.
REFIN
8
I
Reference (positive) input. REFIN must be decoupled with REFM pin using 0.1-µF bypass
capacitor and 1-µF storage capacitor.
REFM
7
9
I
O
I
Reference ground. To be connected to analog ground plane.
REFOUT
SCLK
Internal reference output. Shorted to REFIN pin only when internal reference is used.
24
Serial clock. Data is shifted onto SDO with the rising edge of this clock. This signal is qualified
with CS internally.
SDO
+VA
23
3, 6, 14, 16, 17
20
O
–
Serial data out. All bits except MSB are shifted out at the rising edge of SCLK.
Analog power supplies
+VBD
–
Digital power supply for all digital inputs and outputs.
7
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SLAS451–JUNE 2005
TYPICAL CHARACTERISTICS
SIGNAL-TO-NOISE
AND DISTORTION
vs
SIGNAL-TO-NOISE RATIO
vs
REFERENCE VOLTAGE
REFERENCE VOLTAGE
95
95
94
93
92
91
90
+VA = 5 V,
+VBD = 5 V,
+VA = 5 V,
+VBD = 5 V,
f = 1 kHz,
f = 1 kHz,
94
93
92
91
90
i
i
T
A
= 25°C
T = 25°C
A
2.5
3
3.5
4
2.5
3
3.5
4
V
ref
− Reference Voltage − V
V
ref
− Reference Voltage − V
Figure 1.
Figure 2.
SPURIOUS FREE DYNAMIC RANGE
TOTAL HARMONIC DISTORTION
vs
vs
REFERENCE VOLTAGE
REFERENCE VOLTAGE
−112
127
+VA = 5 V,
+VBD = 5 V,
126
125
124
123
122
121
120
119
118
−113
−114
−115
−116
f = 1 kHz,
i
T
A
= 25°C
+VA = 5 V,
+VBD = 5 V,
−117
−118
f = 1 kHz,
i
T
A
= 25°C
2.5
3
3.5
4
2.5
3
3.5
4
V
ref
− Reference Voltage − V
V
ref
− Reference Voltage − V
Figure 3.
Figure 4.
EFFECTIVE NUMBER OF BITS
vs
EFFECTIVE NUMBER OF BITS
vs
FREE-AIR TEMPERATURE
REFERENCE VOLTAGE
15.4
15.3
15.2
15.1
15
15.5
15.4
15.3
15.2
15.1
+VA = 5 V,
+VBD = 5 V,
f = 1 kHz,
i
T
A
= 25°C
+VA = 5 V,
+VBD = 5 V,
REFIN = 4.096 V,
14.9
14.8
f = 1 kHz,
i
15
−40 −25 −10
5
20 35 50 65 80
2.5
3
3.5
4
V
ref
− Reference Voltage − V
T
A
− Free-Air-Temperature − 5C
Figure 5.
Figure 6.
8
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SLAS451–JUNE 2005
TYPICAL CHARACTERISTICS (continued)
SIGNAL-TO-NOISE
SIGNAL-TO-NOISE RATIO
vs
FREE-AIR TEMPERATURE
AND DISTORTION
vs
FREE-AIR TEMPERATURE
96
95.5
95
96
95.5
95
+VA = 5 V,
+VBD = 5 V,
REFIN = 4.096 V,
+VA = 5 V,
+VBD = 5 V,
REFIN = 4.096 V,
f = 1 kHz,
i
f = 1 kHz,
i
94.5
94
94.5
94
93.5
93
93.5
93
−40 −25 −10
5
20 35 50 65 80
−40 −25 −10
5
20 35 50 65 80
T
A
− Free-Air-Temperature − 5C
T
A
− Free-Air-Temperature − 5C
Figure 7.
Figure 8.
SPURIOUS FREE DYNAMIC RANGE
TOTAL HARMONIC DISTORTION
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
124
−110
−112
−114
−116
−118
−120
−122
+VA = 5 V,
+VBD = 5 V,
REFIN = 4.096 V,
122
120
118
116
114
112
110
f = 1 kHz,
i
+VA = 5 V,
+VBD = 5 V,
REFIN = 4.096 V,
f = 1 kHz,
i
−40 −25 −10
5
20 35 50 65 80
−40 −25 −10
5
20 35 50 65 80
T
A
− Free-Air-Temperature − 5C
T
A
− Free-Air-Temperature − 5C
Figure 9.
Figure 10.
SIGNAL-TO-NOISE
AND DISTORTION
vs
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY
INPUT FREQUENCY
16
95
94
93
92
91
90
89
88
87
15.5
15
14.5
14
+VA = 5 V,
+VBD = 5 V,
REFIN = 4.096 V,
+VA = 5 V,
+VBD = 5 V,
REFIN = 4.096 V,
13.5
13
T
A
= 25°C
T
A
= 25°C
1
10
100
1
10
100
f − Input Frequency − kHz
i
f − Input Frequency − kHz
i
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
SIGNAL-TO-NOISE RATIO
SPURIOUS FREE DYNAMIC RANGE
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
95
94.5
94
140
130
120
110
100
90
93.5
93
+VA = 5 V,
+VBD = 5 V,
REFIN = 4.096 V,
80
+VA = 5 V,
+VBD = 5 V,
REFIN = 4.096 V,
92.5
92
70
T
A
= 25°C
T
A
= 25°C
60
1
10
100
1
10
100
f − Input Frequency − kHz
i
f − Input Frequency − kHz
i
Figure 13.
Figure 14.
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
−84
−94
+VA = 5 V,
+VBD = 5 V,
REFIN = 4.096 V,
T
A
= 25°C
−104
−114
−124
1
10
100
f − Input Frequency − kHz
i
Figure 15.
HISTOGRAM
OF A DC INPUT AT ZERO SCALE (0 V)
HISTOGRAM
OF A DC INPUT CLOSE TO FULL SCALE (4 V)
16000
18000
16000
14000
12000
10000
8000
6000
4000
2000
0
+VA = 5 V,
+VBD = 5 V,
REFIN = 4.096 V,
+VA = 5 V,
+VBD = 5 V,
REFIN = 4.096 V,
14000
12000
10000
8000
T
A
= 25°C
T
A
= 25°C
6000
4000
2000
0
−3
−2
−1
0
1
2
3
Code Out
(2’s Complement Code in Decimal)
Code Out
(2’s Complement Code in Decimal)
Figure 16.
Figure 17.
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TYPICAL CHARACTERISTICS (continued)
GAIN ERROR
GAIN ERROR
vs
ANALOG SUPPLY VOLTAGE
vs
REFERENCE VOLTAGE
6
4
2
1
0.8
0.6
0.4
0.2
+VA = 5 V,
+VBD = 5 V,
+VBD = 5 V,
REFIN = 4.096 V,
T
A
= 25°C
T
A
= 25°C
0
0
−0.2
−0.4
−2
−0.6
−0.8
−1
−4
−6
4.75
5.25
2.5
3
3.5
4
5
V
ref
− Reference Voltage − V
+VA − Analog Supply Voltage − V
Figure 18.
Figure 19.
GAIN ERROR
vs
FREE-AIR TEMPERATURE
OFFSET ERROR
vs
REFERENCE VOLTAGE
1
0.75
0.5
2
1
+VA = 5 V,
+VBD = 5 V,
+VA = 5 V,
+VBD = 5 V,
REFIN = 4.096 V
T
A
= 25°C
0.25
0
−0.25
−0.5
0
−1
−0.75
−1
−2
−40 −25 −10
5
20 35 50 65 80
2.5
3
3.5
4
V
ref
− Reference Voltage − V
T
A
− Free-Air-Temperature − 5C
Figure 20.
Figure 21.
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
OFFSET ERROR
vs
SUPPLY VOLTAGE
0.2
0.1
1
0.75
0.5
+VA = 5 V,
+VBD = 5 V,
REFIN = 4.096 V
0
−0.1
−0.2
−0.3
−0.4
−0.5
0.25
0
−0.25
−0.5
+VBD = 5 V,
REFIN = 4.096 V,
−0.75
−1
T
A
= 25°C
−0.6
4.75
−40 −25 −10
20 35 50 65 80
5
5
5.25
+V − Analog Supply Voltage − V
A
T
A
− Free-Air-Temperature − 5C
Figure 22.
Figure 23.
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TYPICAL CHARACTERISTICS (continued)
POWER DISSIPATION
POWER DISSIPATION
vs
vs
SUPPLY VOLTAGE
SAMPLE RATE
116
114
112
110
108
106
104
102
100
140
120
100
80
+VBD = 5 V,
= 600 KSPS
f
Normal Mode Current
s
T
A
= 25°C
60
NAP Mode Current
40
+VA = 5 .25 V,
+VBD = 5.25 V,
20
T
A
= 25°C
0
0
100
200
300
400
500
600
4.75
5
5.25
f
− Sample Rate − KSPS
s
+VA − Analog Supply Voltage − V
Figure 24.
Figure 25.
POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
DIFFERENTIAL NONLINEARITY
vs
REFERENCE VOLTAGE
1
120
+VA = 5 V,
+VBD = 5 V,
0.8
0.6
0.4
0.2
f
= 600 KSPS
s
115
110
105
100
MAX
MIN
0
−0.2
−0.4
+VA = 5 V,
+VBD = 5 V,
−0.6
−0.8
−1
T
A
= 25°C
2.5
3.5
3
4
−40 −25 −10
5
20 35 50 65 80
V
ref
− Reference Voltage − V
T
A
− Free-Air Temperature − °C
Figure 26.
Figure 27.
INTEGRAL NONLINEARITY
vs
REFERENCE VOLTAGE
DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
1
0.8
0.6
0.4
0.2
1
0.8
MAX
0.6
0.4
0.2
MAX
MIN
0
0
MIN
−0.2
−0.2
−0.4
−0.4
−0.6
−0.8
−1
+VA = 5 V,
+VBD = 5 V,
+VA = 5 V,
+VBD = 5 V,
REFIN = 4.096 V
−0.6
−0.8
−1
T
A
= 25°C
−40 −25 −10
5
20 35 50 65 80
2.5
3
3.5
4
T
A
− Free-Air-Temperature − 5C
V
ref
− Reference Voltage − V
Figure 28.
Figure 29.
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TYPICAL CHARACTERISTICS (continued)
INTEGRAL NONLINEARITY
INTERNAL REFERENCE OUTPUT VOLTAGE
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1
0.8
0.6
0.4
0.2
4.126
4.116
+VA = 5 V,
+VBD = 5 V,
MAX
MIN
4.106
4.096
4.086
0
−0.2
−0.4
−0.6
−0.8
−1
+VA = 5 V,
+VBD = 5 V,
REFIN = 4.096 V
4.076
4.066
−40 −25 −10
5
35 50 65 80
−40 −25 −10
5
20 35 50 65 80
20
T
A
− Free-Air-Temperature − 5C
T
A
− Free-Air Temperature − °C
Figure 30.
Figure 31.
INTERNAL REFERENCE OUTPUT VOLTAGE
DELAY TIME
vs
LOAD CAPACITANCE
vs
SUPPLY VOLTAGE
4.126
9.5
+VA = 5 V,
= 85°C
+VBD = 5 V,
T
9
T
= 25°C
A
A
4.116
4.106
8.5
8
+VBD = 2.7 V
7.5
4.096
4.086
7
+VBD = 5 V
6.5
6
5.5
4.076
4.066
5
4.5
4.75
5
5.25
5
10
15
20
+V − Analog Supply Voltage − V
A
C
L
− Load Capacitance − pF
Figure 32.
Figure 33.
DIFFERENTIAL NONLINEARITY
1
0.8
0.6
0.4
0.2
0
−0.2
−0.4
+VA = 5 V, +VBD = 5 V,
REFIN = 4.096 V,
−0.6
−0.8
−1
f
= 600 KSPS,
S
T
A
= 25°C
−32768
−16384
16384
32768
0
Output Code
(2’s Complement Code in Decimal)
Figure 34.
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TYPICAL CHARACTERISTICS (continued)
INTEGRAL NONLINEARITY
1
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
+VA = 5 V, +VBD = 5 V,
REFIN = 4.096 V,
f
= 600 KSPS,
S
T
A
= 25°C
−1
−32768
−16384
0
16384
32768
Output Code
(2’s Complement Code in Decimal)
Figure 35.
FFT (100 kHz Input)
0
−20
−40
+VA = 5 V, +VBD = 5 V,
REFIN = 4.096 V,
f
= 600 KSPS,
S
T
A
= 25°C
−60
−80
−100
−120
−140
−160
−180
−200
0
50000
100000
150000
200000
250000
300000
f − Frequency − Hz
Figure 36.
FFT (10 kHz Input)
20
+VA = 5 V, +VBD = 5 V,
REFIN = 4.096 V,
0
−20
f
= 600 KSPS,
S
T
A
= 25°C
−40
−60
−80
−100
−120
−140
−160
−180
−200
0
50000
100000
150000
200000
250000
300000
f − Frequency − Hz
Figure 37.
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Power
On
BUSY=0
+VA and +VBD Reach Operation Range
and PD = 0
Sample
BUSY=0
CS = 0 and CONVST = 1
Falling Edge of CONVST_QUAL
CS = 0 and CONVST = 1
SOC
Falling Edge of
CONVST_QUAL
and BUSY = 1
BUSY=0 −> 1
CS = 0 and CONVST = 1
Back to Back Cycle
CONVST_QUAL = 0
CONVERSION
Abort
EOC
BUSY= 1−>0
CONVST_QUAL= 1
and CS = 1
NAP
Wait
BUSY=0
BUSY=0
A. EOC = End of conversion, SOC = Start of conversion, CONVST_QUAL is CONVST latched by CS = 0, see
Figure 39.
Figure 38. Device States and Ideal Transitions
Q
D
CONVST_QUAL
CONVST
CS
LATCH
LATCH
Figure 39. Relationship Between CONVST_QUAL, CS, and CONVST
TIMING DIAGRAMS
In the following descriptions, the signal CONVST_QUAL represents CONVST latched by a low value on CS (see
Figure 39).
To avoid performance degradation, there are three quiet zones to be observed (tquiet1 and tquiet2 are zones before
and after the falling edge of CONVST_QUAL while tquiet3 is a time zone before the falling edge of BUSY) where
there should be no I/O activities. Interface control signals, including the serial clock should remain steady.
Typical degradation in performance if these quiet zones are not observed is depicted in the specifications
section.
To avoid data loss a read operation should not start around the BUSY falling edge. This is constrained by tsu2
,
tsu3, th2, and th8.
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CONVST_QUAL
t
quiet1
t
quiet2
BUSY
t
quiet3
CS
FS
Quiet Zones
t
su3
CS
t
h8
t
su2
BUSY
t
h2
No Read Zone (FS Initiated)
BUSY
No Read Zone (CS Initiated)
Figure 40. Quiet Zones and No-Read Zones
CONVERSION AND SAMPLING
1. Convert start command:
The device enters the conversion phase from the sampling phase when a falling edge is detected on
CONVST_QUAL. This is shown in Figure 41, Figure 42, and Figure 43.
2. Sample (acquisition) start command:
The device starts sampling from the wait/nap state or at the end of a conversion if CONVST is detected as
high and CS as low. This is shown in Figure 41, Figure 42, and Figure 43.
Maintaining this condition (holding CS low) when the device has just finished a conversion (as shown in
Figure 41) takes the device immediately into the sampling phase after the conversion phase (back-to-back
conversion) and hence achieves the maximum throughput. Otherwise, the device enters the wait state or the
nap state.
t
t
w2
t
h1
su2
CS
t
su4
CONVST
t
su1
t
CONVST_QUAL
(Device Internal)
d1
t
quiet2
t
quiet2
t
t
quiet1
quiet1
SAMPLE
CONVERT
CONV
SAMPLE
DEVICE STATE
BUSY
t
t
acq1
t
d2
t
d4
t
quiet3
Figure 41. Back-to-Back Conversion and Sample
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3. Wait/Nap entry stimulus:
The device enters the wait or nap phase at the end of the conversion if the sample start command is not
given. This is shown in Figure 42.
t
w2
t
t
h4
su4
CS
CONVST
CONVST_QUAL
(Device Internal)
t
quiet2
t
quiet2
t
t
quiet1
quiet1
DEVICE STATE
SAMPLE
CONVERT
SAMPLE
WAIT
t
CONV
t
acq1
t
d2
BUSY
t
quiet3
Figure 42. Convert and Sample with Wait
If lower power dissipation is desired and throughput can be compromised, a nap state can be inserted in
between cycles (as shown in Figure 43). The device enters a low power (3 mA) state called nap if the end of
the conversion happens when CONVST_QUAL is low. The cost for using this special wait state is a longer
sampling time (tacq2) plus the nap time.
t
h3
t
d5
CS
t
w1
CONVST
t
t
d1
d3
CONVST_QUAL
(Device Internal)
t
t
quiet2
quiet2
t
t
quiet1
quiet1
DEVICE STATE
NAP
SAMPLE
CONVERT
NAP
SAMPLE
CONVERT
NAP
SAMPLE
t
CONV
t
acq2
t
d2
t
t
quiet3
quiet3
BUSY
t
d4
Figure 43. Convert and Sample with Nap
4. Conversion abort command:
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An ongoing conversion can be aborted by using the conversion abort command. This is done by forcing
another start of conversion (a valid CONVST_QUAL falling edge) onto an ongoing conversion as shown in
Figure 44. The device enters the wait state after an aborted conversion. If the previous conversion was
successfully aborted, the device output reads 0xFF00 on SDO.
t
w5
CS
t
w5
t
su4
CONVST
CONVST_QUAL
(Device Internal)
DEVICE STATE
SAMPLE
CONVERT
WAIT
SAMPLE
CONVERT
WAIT
Incomplete
Conversion
Incomplete
Conversion
t
t
CONV
t
acq1
CONV
BUSY
t
d6
t
d6
Figure 44. Conversion Abort
DATA READ OPERATION
Data read control is independent of conversion control. Data can be read either during conversion or during
sampling. Data that is read during a conversion involves latency of one sample. The start of a new data frame
around the fall of BUSY is constrained by tsu2, tsu3, th2, and th8.
1. SPI interface:
A data read operation in SPI interface mode is shown in Figure 45. FS must be tied high for operating in this
mode. The MSB of the output data is available at the falling edge of CS. MSB – 1 is shifted out at the first
rising edge after the first falling edge of SCLK after CS falling edge. Subsequent bits are shifted at the
subsequent rising edges of SCLK. If another data frame is attempted (by pulling CS high and subsequently
low) during an active data frame, then the ongoing frame is aborted and a new frame is started.
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1
2
3
4
16
17
18
19
SCLK
t
t
cyc
su5
t
h5
t
d14
CS
t
w2
t
quiet2
CONVST
SDO
t
quiet1
t
d13
LSB
D0
MSB
D15
D14 D13 D12 D1
D0
D0
D15 Repeated
If There is 19th SCLK
t
d12
t
Don’t Care
(D0 Repeated)
BUSY
quiet3
Conversion N
Conversion N+1
t
h2
t
su2
CS Fall Before This
Point Reads Data
From Conversion
N−1
CS Fall After This
Point Reads Data
From Conversion
N
No CS
Fall
Zone
Figure 45. Read Frame Controlled via CS (FS = 1)
If another data frame is attempted (by pulling CS high and then low) during an active data frame, then the
ongoing frame is aborted and a new frame is started.
2. Serial interface using FS:
A data read operation in this mode is shown in Figure 46 and Figure 47. The MSB of the output data is
available at the rising edge of FS. MSB – 1 is shifted out at the first rising edge after the first falling edge of
SCLK after the FS falling edge. Subsequent bits are shifted at the subsequent rising edges of SCLK.
1
16
17
18
19
3
2
4
SCLK
t
cyc
t
h6
t
su7
CS
t
t
w3
su6
FS
CONVST
t
t
quiet1
quiet2
t
d13
t
d15
MSB of Conversion N
LSB
D0
SDO
D14
D13 D12 D1
D0
D0
D15
D15 Repeated
If There is 19th SCLK
Don’t Care
(D0 Repeated)
Conversion N+1
BUSY
Conversion N
Figure 46. Read Frame Controlled via FS (FS is Low When BUSY Falls)
If FS is high when BUSY falls, the SDO is updated again with the new MSB when BUSY falls. This is shown
in Figure 47.
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1
16
17
18
19
2
3
4
SCLK
t
cyc
t
h6
t
su7
CS
t
t
w3
su6
FS
CONVST
MSB of Conversion N−1
MSB of Conversion N
t
t
quiet1
quiet2
t
d15
t
LSB
D0
d13
SDO
D14
D13 D12 D1
D0
D0
D15
D15 Repeated
If There is 19th SCLK
t
d7
Don’t Care
(D0 Repeated)
t
quiet3
Conversion N+1
BUSY
Conversion N
t
h8
t
su3
No FS
Fall
Zone
FS Fall Before This
Point Reads Data
From Conversion
N−1
FS Fall After This
Point Reads Data
From Conversion
N
Figure 47. Read Frame Controlled via FS (FS is High When BUSY Falls)
If another data frame is attempted by pulling up FS during an active data frame, then the ongoing frame is
aborted and a new frame is started.
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THEORY OF OPERATION
The ADS8372 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The
architecture is based on charge redistribution, which inherently includes a sample/hold function.
The device includes a built-in conversion clock, internal reference, and 40-MHz SPI compatible serial interface.
The maximum conversion time is 1.1 µs which is capable of sustaining a 600-kHz throughput.
The analog input is provided to the two input pins: +IN and –IN. When a conversion is initiated, the differential
input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are
disconnected from any internal function.
REFERENCE
The ADS8372 has a built-in 4.096-V (nominal value) reference but can operate with an external reference also.
When the internal reference is used, pin 9 (REFOUT) should be shorted to pin 8 (REFIN) and a 0.1-µF
decoupling capacitor and a 1-µF storage capacitor must be connected between pin 8 (REFIN) and pin 7 (REFM)
(see Figure 48). The internal reference of the converter is buffered.
ADS8372
REFOUT
REFIN
1 mF
0.1 mF
REFM
AGND
Figure 48. ADS8372 Using Internal Reference
The REFIN pin is also internally buffered. This eliminates the need to put a high bandwidth buffer on the board
to drive the ADC reference and saves system area and power. When an external reference is used, the
reference must be of low noise, which may be achieved by the addition of bypass capacitors from the REFIN pin
to the REFM pin. See Figure 49 for operation of the ADS8372 with an external reference. REFM must be
connected to the analog ground plane.
ADS8372
REFOUT
50 W
REF3240
REFIN
REFM
0.1 mF
22 mF
1 mF
AGND
AGND
Figure 49. ADS8372 Using External Reference
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THEORY OF OPERATION (continued)
+VA
ADS8372
53 W
+IN
−IN
+
_
53 W
40 pF
40 pF
AGND
AGND
Figure 50. Simplified Analog Input
ANALOG INPUT
When the converter enters hold mode, the voltage difference between the +IN and –IN inputs is captured on the
internal capacitor array. Both the +IN and –IN inputs have a range of –0.2 V to (+VREF + 0.2 V). The input span
(+IN – (–IN)) is limited from –VREF to VREF
.
The input current on the analog inputs depends upon throughput and the frequency content of the analog input
signals. Essentially, the current into the ADS8372 charges the internal capacitor array during the sampling
(acquisition) time. After this capacitance has been fully charged, there is no further input current. The source of
the analog input voltage must be able to charge the device sampling capacitance (40 pF each from +IN/–IN to
AGND) to an 16-bit settling level within the sampling (acquisition) time of the device. When the converter goes
into hold mode, the input resistance is greater than 1 GΩ.
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the
+IN, –IN inputs and the span (+IN – (–IN)) should be within the limits specified. Outside of these ranges, the
converter's linearity may not meet specifications.
Care should be taken to ensure that the output impedance of the sources driving +IN and –IN inputs are
matched. If this is not observed, the two inputs can have different settling times. This can result in offset error,
gain error, and linearity error which vary with temperature and input voltage.
A typical input circuit using TI's THS4031 is shown in Figure 51. In the figure, input from a single-ended source
is converted into a differential signal for the ADS8372. In the case where the source is differential, the circuit in
Figure 52 may be used. Most of the specified performance figure were measured using the circuit in Figure 52.
Input
Signal
(0 to 4 V)
20 W
THS4031
ADS8372
50 W
+IN
4 V
PP
1.5 nF
600 W
−IN
600 W
20 W
THS4031
2 V
AGND
Figure 51. Single-Ended Input, Differential Output Configuration
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THEORY OF OPERATION (continued)
Input
Signal
(V+)
20 W
THS4031
ADS8372
8 V , 2 V
50 W
PP
+IN
−IN
Common
Mode
1.5 nF
50 W
20 W
THS4031
Input
Signal
(V−)
Figure 52. Differential Input, Differential Output Configuration
DIGITAL INTERFACE
TIMING AND CONTROL
Conversion and sampling are controlled by the CONVST and CS pins. See the timing diagrams for detailed
information on timing signals and their requirements. The ADS8372 uses an internally generated clock to control
the conversion rate and in turn the throughput of the converter. SCLK is used for reading converted data only. A
clean and low jitter conversion start command is important for the performance of the converter. There is a
minimal quiet zone requirement around the conversion start command as mentioned in the timing requirements
table.
READING DATA
The ADS8372 offers a high speed serial interface that is compatible with the SPI protocol. The device outputs
the data in 2's complement format. Refer to Table 1 for the ideal output codes.
Table 1. Input Voltages and Ideal Output Codes
DESCRIPTION
Full-scale range
Least significant bit (LSB) 2(+VREF)/216
ANALOG VALUE +IN – (–IN)
DIGITAL OUTPUT (HEXADECIMAL)
2(+VREF
)
2's Complement
Full scale
VREF – 1 LSB
0
7FFF
0000
FFFF
8000
Mid scale
Mid scale – 1 LSB
–Full scale
0 V – 1 LSB
–VREF
To avoid performance degradation due to the toggling of device buffers, read operation must not be performed
in the specified quiet zones (tquiet1, tquiet2, and tquiet3). Internal to the device, the previously converted data is
updated with the new data near the fall of BUSY. Hence, the fall of CS and the fall of FS around the fall of BUSY
is constrained. This is specified by tsu2, tsu3, th2, and th8 in the timing requirements table.
POWER SAVING
The converter provides two power saving modes, full power down and nap. Refer to Table 2 for information on
activation/deactivation and resumption time for both modes.
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Table 2. Power Save
POWER
CONSUMPTION
ACTIVATION
TIME (td16
RESUME
POWER BY
TYPE OF POWER DOWN
SDO
ACTIVATED BY
NA
)
Normal operation
Not 3 stated
22 mA
NA
NA
Full power down
(Int Ref, 1-µF capacitor on REFOUT pin)
3 Stated (td10 timing)
2 µA
2 µA
PD = 1
PD = 1
10 µs
10 µs
PD = 0
Full power down
(Ext Ref, 1-µF capacitor on REFOUT pin)
3 Stated (td10 timing)
Not 3 stated
PD = 0
At EOC and
CONVST_QUAL =
0
Sample Start
command
Nap power down
3 mA
200 ns
FULL POWER-DOWN MODE
Full power-down mode is activated by turning off the supply or by asserting PD to 1. See Figure 53 and
Figure 54. The device can be resumed from full power down by either turning on the power supply or by
de-asserting the PD pin. The first two conversions produce inaccurate results because during this period the
device loads its trim values to ensure the specified accuracy.
If an internal reference is used (with a 1-µF capacitor installed between the REFOUT and REFM pins), the total
resume time (td18) is 25 ms. After the first two conversions, td17 (4 ms) is required for the trimmed internal
reference voltage to settle to the specified accuracy. Only then the converted results match the specified
accuracy.
PD
t
w4
Valid Data
t
d10
Invalid Data
SDO
t
d18
1
2
3
t
d11
BUSY
REFOUT
t
d17
td16
I
PD
CC
I
Full I
Full I
CC
CC
CC
Figure 53. Device Full Power Down/Resume (Internal Reference Used)
PD
t
w4
t
d10
Invalid Data
Valid Data
SDO
t
d18
1
2
3
t
d11
BUSY
t
acq1
t
d16
I
PD
CC
I
Full I
Full I
CC
CC
CC
Figure 54. Device Full Power Down/Resume (External Reference Used)
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NAP MODE
Nap mode is automatically inserted at the end of a conversion if CONVST_QUAL is held low at EOC. The
device can be operated in nap mode at the end of every conversion for saving power at lower throughputs.
Another way to use this mode is to convert multiple times and then enter nap mode. The minimum sampling
time after a nap state is tacq1 + td18 = tacq2
.
PD = 0
CONVST
CS
CONVST_QUAL
DEVICE
SAMPLE
CONVERT
NAP
SAMPLE
MSB
STATE
Hi−Z
LSB+1
LSB
MSB−1
SDO
t
CONV
BUSY
REFIN
(or REFOUT)
t
d18
t
d16
I
NAP
I
CC
CC
Full I
Full I
CC
CC
Figure 55. Device Nap Power Down/Resume
LAYOUT
For optimum performance, care should be taken with the physical layout of the ADS8372 circuitry.
Since the ADS8372 offers single-supply operation, it is often used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal processors. The more the digital logic in the design and the
higher the switching speed, the greater the need for better layout and isolation of the critical analog signals from
these switching digital signals.
The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground
connections and digital inputs that occur just prior to the end of sampling and just prior to the latching of the
analog comparator. Such glitches might originate from switching power supplies, nearby digital logic, or high
power devices. Noise during the end of sampling and the latter half of the conversion must be kept to a
minimum (the former half of the conversion is not very sensitive since the device uses a proprietary error
correction algorithm to correct for the transient errors made here).
The degree of error in the digital output depends on the reference voltage, layout, and the exact timing and
degree of the external event.
On average, the ADS8372 draws very little current from an external reference as the reference voltage is
internally buffered. If the reference voltage is external, it must be ensured that the reference source can drive
the bypass capacitor without oscillation. A 0.1-µF bypass capacitor is recommended from pin 8 directly to pin 7
(REFM).
The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the
analog ground. Avoid connections that are too close to the grounding point of a microcontroller or digital signal
processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal
layout consists of an analog ground plane dedicated to the converter and associated analog circuitry.
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LAYOUT (continued)
As with the AGND connections, +VA should be connected to a +5-V power-supply plane or trace that is
separate from the connection for digital logic until they are connected at the power entry point. Power to the
ADS8372 should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to
the device as possible. See Table 3 for the placement of these capacitors. In addition, a 1-µF capacitor is
recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor
or even a Pi filter made up of inductors and capacitors—all designed to essentially low-pass filter the +5-V
supply, removing the high frequency noise.
Table 3. Power Supply Decoupling Capacitor Placement
SUPPLY PINS
CONVERTER ANALOG SIDE
CONVERTER DIGITAL SIDE
Pair of pins requiring a shortest
path to decoupling capacitors
(2,3); (5,6); (15,16); (17,18)
(20,21)
Pins requiring no decoupling
1, 4, 14, 19
When using the internal reference, ensure a shortest path from REFOUT (pin 9) to REFIN (pin 8) with the
bypass capacitor directly between pins 8 and 7.
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APPLICATION INFORMATION
EXAMPLE DIGITAL STIMULUS
The use of the ADS8372 is very straightforward. The following timing diagram shows one example of how to
achieve a 600-KSPS throughput using a SPI compatible serial interface.
BUSY
DEVICE STATE
CONVERT
SAMPLE
485 ns
CONVERT
CONVST
Frequency = 600 kHz
15 ns
15 ns
80 ns
50 ns
CS
25 ns
2
3
15
16
SCLK
SDO
12.5 ns
MSB
D15
LSB
D0
D14 D13 D2
D1
Figure 56. Example Stimulus in SPI Mode (FS = 1), Back-To-Back Conversion that Achieves 600 KSPS
It is also possible to use the frame sync signal, FS. The following timing diagram shows how to achieve a
600-KSPS throughput using a modified serial interface with FS active.
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APPLICATION INFORMATION (continued)
BUSY
DEVICE STATE
CONVERT
SAMPLE
485 ns
CONVERT
Frequency = 600 kHz
CONVST
50 ns
CS = 0
15 ns
15 ns
80 ns
FS
25 ns
1
2
3
15 16
SCLK
SDO
12.5 ns
MSB
n
LSB
LSB
D0
n−1
n
D0
D15
D14 D13 D2
D1
Figure 57. Example Stimulus in Serial Interface With FS Active, Back-To-Back Conversion that Achieves
600 KSPS
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PACKAGE OPTION ADDENDUM
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7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS8372IBRHPT
ACTIVE
VQFN
RHP
28
250
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 85
ADS8372I
B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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