ADS8383IPFBT_技术文档

ADS8383

SLAS005B – DECEMBER 2002 – REVISED MAY 2003

18-BIT, 500-kHz, UNIPOLAR INPUT, MICROPOWER SAMPLING

ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE

FEATURES

APPLICATIONS

D

Medical Instruments

D

500-kHz Sample Rate

Optical Networking

Transducer Interface

18-Bit NMC Ensured Over Temperature

Zero Latency

High Accuracy Data Acquisition Systems

Magnetometers

Low Power: 110 mW at 500 kHz

Unipolar Input Range

DESCRIPTION

The ADS8383 is an 18-bit, 500 kHz A/D converter. The

device includes a 18-bit capacitor-based SAR A/D

converter with inherent sample and hold. The ADS8383

offers a full 18-bit interface, a 16-bit option where data is

read using two read cycles or an 8-bit bus option using

three read cycles.

Onboard Reference Buffer

High-Speed Parallel Interface

Wide Digital Supply

TheADS8383isavailableina48-leadTQFPpackageand

is characterized over the industrial –40°C to 85°C

temperature range.

8-/16-/18-Bit Bus Transfer

48-Pin TQFP Package

BUS 18/16

Output

Latches

and

3-State

Drivers

BYTE

SAR

18-/16-/8-Bit

Parallel DATA

Output Bus

+

_

+IN

–IN

CDAC

Comparator

Clock

REFIN

CONVST

Conversion

and

Control Logic

BUSY

CS

RD

Pleasebe aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products

conform to specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all parameters.

ADS8383

www.ti.com

SLAS005B – DECEMBER 2002 – REVISED MAY 2003

Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduring

storageor handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

NO

MISSING

CODES

RESOLU-

TION (BIT)

MAXIMUM

INTEGRAL DIFFERENTIAL

LINEARITY

(LSB)

MAXIMUM

TRANS-

PORT

MEDIA

TEMPER-

ATURE

RANGE

PACKAGE

TYPE

PACKAGE

DESIGNATOR

ORDERING

INFORMATION

MODEL

LINEARITY

(LSB)

QUANTITY

Tape and

reel 250

ADS8383IPFBT

ADS8383IPFBR

ADS8383IBPFBT

ADS8383IBPFBR

48 Pin

TQFP

–40°C to

85°C

ADS8383I

±10

±7

–2~7

17

18

PFB

Tape and

reel1000

Tape and

reel 250

48 Pin

TQFP

–40°C to

85°C

ADS8383IB

–1~2.5

Tape and

reel1000

NOTE:

For the most current specifications and package information, refer to our website at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

overoperating free-air temperature range unless otherwise noted

(1)

UNIT

+IN to AGND

+VA + 0.1 V

0.5 V

Voltage

–IN to AGND

+VA to AGND

–0.3 V to 7 V

+VBD to BDGND

+VA to +VBD

Voltagerange

–0.3 V to 2.5 V

–0.3 V to +VBD + 0.3 V

–40°C to 85°C

Digital input voltage to BDGND

Digital output voltage to BDGND

Operating free-air temperature range, T

A

Storage temperature range, T

stg

–65°C to 150°C

150°C

Junctiontemperature(T max)

J

Powerdissipation

thermalimpedance

(T Max – T )/θ

J

A

JA

TQFP package

θ

86°C/W

JA

Vapor phase (60 sec)

Infrared (15 sec)

215°C

220°C

Leadtemperature,soldering

(1)

Stressesbeyondthoselistedunder“absolutemaximumratings”maycausepermanentdamagetothedevice. Thesearestressratingsonly,and

functionaloperation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2

ADS8383

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SLAS005B– DECEMBER 2002 – REVISED MAY 2003

SPECIFICATIONS

A

T

= –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, V = 4.096 V, f

= 500 kHz (unless otherwise noted)

ref

SAMPLE

TEST CONDITIONS

PARAMETER

MIN

TYP

MAX

UNIT

Analog Input

Full-scale input voltage (see Note 1)

+IN – –IN

0

–0.2

V

ref

+IN

V

ref

+ 0.2

0.2

Absoluteinputvoltage

–IN

Inputcapacitance

Input leakage current

SystemPerformance

Resolution

45

1

pF

nA

18

Bits

(+IN – –IN) < 0.5 FS

(+IN – –IN) ≥ 0.5 FS

18

17

ADS8383I

No missing codes

ADS8383IB

18

(+IN – –IN) < 0.125 FS

(+IN – –IN) < 0.5 FS

(+IN – –IN) ≥ 0.5 FS

–4

4

6

–6

ADS8383I

LSB

(18 bit)

Integral linearity (see Notes 2 and 3)

–10

–7

10

7

ADS8383IB

–2/3

(+IN – –IN) < 0.125 FS

(+IN – –IN) < 0.5 FS

(+IN – –IN) ≥ 0.5 FS

–1

2

–1

3

ADS8383I

Differentiallinearity

LSB (18 bit)

mV

–2

7

ADS8383IB

ADS8383I

ADS8383IB

ADS8383I

ADS8383IB

–1

–1/1.4

±0.5

2.5

1

–1

Offset error (see Note 4)

Gain error (see Note 4)

–0.75

–0.1

–0.06

±0.25

0.75

0.1

0.06

V

ref

= 4.096 V

%FS

V

ref

Noise

60

75

µV RMS

dB

Power supply rejection ratio

SamplingDynamics

Conversiontime

Acquisitiontime

Throughputrate

Aperturedelay

At 3FFFFh output code

1.5

µs

0.4

500

kHz

ns

4

15

Aperturejitter

ps

Stepresponse

150

ns

Over voltage recovery

ns

(1)

Ideal input span, does not include gain or offset error.

LSB means least significant bit

This is endpoint INL, not best fit.

(2)

(3)

(4)

Measured relative to an ideal full-scale input (+IN – –IN) of 4.096 V

3

ADS8383

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SLAS005B – DECEMBER 2002 – REVISED MAY 2003

SPECIFICATIONS (CONTINUED)

A

T

= –40°C to 85°C, +VA = +5 V, +VBD = 3 V or 5 V, V = 4.096 V, f

= 500 kHz (unless otherwise noted)

ref

SAMPLE

TEST CONDITIONS

PARAMETER

MIN

TYP

MAX

UNIT

DynamicCharacteristics

ADS8383I

ADS8383IB

ADS8383I

ADS8383IB

ADS8383I

ADS8383IB

ADS8383I

ADS8383IB

ADS8383I

ADS8383IB

ADS8383I

ADS8383IB

ADS8383I

ADS8383IB

ADS8383I

ADS8383IB

ADS8383I

ADS8383IB

ADS8383I

ADS8383IB

ADS8383I

ADS8383IB

ADS8383I

ADS8383IB

ADS8383I

ADS8383IB

ADS8383I

ADS8383IB

ADS8383I

ADS8383IB

ADS8383I

ADS8383IB

–110

–112

–98

–108

–98

–99

–90

–91

87

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

= 4 V at 1 kHz

pp

= 4 V at 10 kHz

pp

Total harmonic distortion (THD)

(see Note 1)

dB

= 4 V at 50 kHz

pp

= 4 V at 100 kHz

pp

= 4 V at 1 kHz

pp

88

87

= 4 V at 10 kHz

pp

87

Signal to noise ratio (SNR) (see Note 1)

87

= 4 V at 50 kHz

pp

87

= 4 V at 100 kHz

pp

87

86

= 4 V at 1 kHz

pp

87

86

= 4 V at 10 kHz

pp

86

Signal to noise + distortion (SINAD)

(see Note 1)

86

= 4 V at 50 kHz

pp

86

85

= 4 V at 100 kHz

pp

85

110

112

98

= 4 V at 1 kHz

pp

= 4 V at 10 kHz

pp

108

98

Spurious free dynamic range (SFDR)

(see Note 1)

dB

= 4 V at 50 kHz

pp

98

90

= 4 V at 100 kHz

pp

94

–3dB Small signal bandwidth

3

MHz

Voltage Reference Input

Reference voltage at REFIN, V

ref

2.5

4.096

500

4.2

1

V

Reference resistance (see Note 2)

Reference current drain

Bias Input

kΩ

mA

f = 500 kHz

s

Bias input range

2

2.048

2.1

V

Bias input drift

±5

%FS

µA

Bias input current, sink

–150

–100

(1)

(2)

Calculated on the first nine harmonics of the input frequency

Can vary ±20%

4

ADS8383

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SLAS005B– DECEMBER 2002 – REVISED MAY 2003

SPECIFICATIONS (CONTINUED)

A

T

= –40°C to 85°C, +VA = +5 V, +VBD = 3 V or 5 V, V = 4.096 V, f

= 500 kHz (unless otherwise noted)

SAMPLE

ref

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DigitalInput/Output

Logicfamily

CMOS

V

I

= 5 µA

+VBD–1

–0.3

+V

BD

+ 0.3

0.8

IH

IL

Logic level

V

= 2 TTL loads

+V

BD

– 0.6

OH

OL

OH

OL

0.4

Straight

Binary

Dataformat

PowerSupplyRequirements

+VBD (see Notes 1 and 2)

+VA (see Note 2)

2.95

4.75

3.3

5

5.25

26

V

Power supply voltage

Supply current, 500-kHz sample rate (see Note 3)

Power dissipation, 500-kHz sample rate (see Note 3)

TemperatureRange

22

110

mA

mW

130

Operatingfree-air

–40

85

°C

(1)

(2)

(3)

The difference between +VA and +VBD should be no less than 2.3 V, i.e. if +VA is 5.5 V, +VBD should be at least 2.95 V.

+VBD ≥ +VA – 2.3 V

This includes only +VA current. +VBD current is typical 1 mA with 5 pF load capacitance on all output pins.

5

ADS8383

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SLAS005B– DECEMBER 2002 – REVISED MAY 2003

TIMING CHARACTERISTICS

All specifications typical at –40°C to 85°C, +VA = +VBD = 5 V (see Notes 1, 2, and 3)

PARAMETER

MIN

TYP

MAX

UNIT

t

Conversiontime

1.5

µs

ns

ps

µs

CONV

ACQ

pd1

pd2

w1

Acquisitiontime

0.4

10

40

20

CONVST low to conversion started (BUSY high)

Propagation delay time, End of conversion to BUSY low

Pulse duration, CONVST low

50

20

Setup time, CS low to CONVST low

Pulse duration, CONVST high

CONVST falling edge jitter

su1

w2

10

1

t

Pulse duration, BUSY signal low

Pulse duration, BUSY signal high

Min(t )

ACQ

w3

1.52

w4

Hold time, First data bus data transition (RD low, or CS low for read cycle, or BYTE or

BUS18/16input changes) after CONVST low

t

h1

40

ns

t

Delay time, CS low to RD low

0

ns

d1

Setup time, RD high to CS high

su2

w5

en

Pulse duration, RD low time

50

Enable time, RD low (or CS low for read cycle) to data valid

Delay time, data hold from RD high

20

5

10

d2

Delay time, BUS18/16 or BYTE rising edge or falling edge to data valid

RD high

d3

20

w6

h2

Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge

Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge

Delay time, BYTE edge to BUS18/16 edge skew

Setup time, BYTE or BUS18/16 rising edge to RD falling edge

Hold time, BYTE or BUS18/16 falling edge to RD falling edge

125

Max(t

)

d5

pd4

d4

0

10

su3

h3

t

Disable time, RD High (CS high for read cycle) to 3-stated data bus

Delay time, BUSY low to MSB data valid

20

30

20

ns

µs

dis

d5

Setup time, BYTE or BUS18/16 change before BUSY falling edge

10

su4

(1)

(2)

(3)

All input signals are specified with t = t = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (V + V )/2.

IL IH

r

f

Seetimingdiagrams.

All timing are measured with 20 pF equivalent loads on all data bits and BUSY pins.

6

ADS8383

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SLAS005B– DECEMBER 2002 – REVISED MAY 2003

TIMING CHARACTERISTICS

All specifications typical at –40°C to 85°C, +VA = 5 V, +VBD = 3 V (see Notes 1, 2, and 3)

PARAMETER

MIN

TYP

MAX

UNIT

µs

ns

t

Conversiontime

1.5

CONV

ACQ

pd1

pd2

w1

Acquisitiontime

0.4

10

40

20

CONVST low to conversion started (BUSY high)

Propagation delay time, end of conversion to BUSY low

Pulse duration, CONVST low

50

20

ns

Setup time, CS low to CONVST low

Pulse duration, CONVST high

CONVST falling edge jitter

ns

su1

ns

w2

10

1

ps

t

Pulse duration, BUSY signal low

Pulse duration, BUSY signal high

Min(t

ACQ

)

µs

ns

w3

w4

h1

1.52

Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE or BUS

18/16input changes) after CONVST low

40

t

Delay time, CS low to RD low

0

ns

d1

Setup time, RD high to CS high

su2

w5

en

Pulse duration, RD low

50

Enable time, RD low (or CS low for read cycle) to data valid

Delay time, data hold from RD high

30

10

d2

Delay time, BUS18/16 or BYTE rising edge or falling edge to data valid

Pulse duration, RD high time

d3

20

w6

h2

Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge

Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge

Delay time, BYTE edge to BUS18/16 edge skew

Setup time, BYTE or BUS18/16 rising edge to RD falling edge

Hold time, BYTE or BUS18/16 falling edge to RD falling edge

125

Max(td5)

pd4

d4

0

10

su3

h3

t

Disable time, RD High (CS high for read cycle) to 3-stated data bus

Delay time, BUSY low to MSB data valid delay time

30

40

30

ns

µs

dis

d5

Setup time, BYTE or BUS18/16 change before BUSY falling edge

10

su4

(1)

(2)

(3)

All input signals are specified with t = t = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (V + V )/2.

IL IH

r

f

Seetimingdiagrams.

All timing are measured with 10 pF equivalent loads on all data bits and BUSY pins.

7

ADS8383

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SLAS005B– DECEMBER 2002 – REVISED MAY 2003

PIN ASSIGNMENTS

PFB PACKAGE

(TOP VIEW)

36 35 34 33 32 31 30 29 28 27 26 25

+VBD

BUS18/16

BYTE

CONVST

RD

+VBD

DB10

DB11

DB12

DB13

DB14

DB15

DB16

DB17

AGND

+VA

37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

19

18

17

16

15

14

13

CS

+VA

AGND

+VA

REFM

1

2

3

4

5

6

7

8

9 10 11 12

NC – No connection.

8

ADS8383

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NAME

SLAS005B– DECEMBER 2002 – REVISED MAY 2003

TERMINAL FUNCTIONS

NO.

I/O

DESCRIPTION

AGND

5, 8, 11,

12, 14, 15,

44, 45

–

Analogground

BDGND

BIAS

25

2

–

I

Digital ground for bus interface digital supply

Bias to internal circuit

BUSY

36

38

O

I

Status output. High when a conversion is in progress.

BUS18/16

Bus size select input. Used for selecting 18-bit or 16-bit wide bus transfer.

0: Data bits output on the 18-bit data bus pins DB[17:0].

1: Last two data bits D[1:0] from 18-bit wide bus output on:

a) the low byte pins DB[9:2] if BYTE = 0

b) the high byte pins DB[17:10] if BYTE = 1

BYTE

39

I

Byte select input. Used for 8-bit bus reading.

0: No fold back

1: Low byte D[9:2] of the 16 most significant bits is folded back to high byte of the 16 most significant

pinsDB[17:10].

CONVST

CS

40

42

I

Convert start

Chip select

8-Bit Bus

BYTE = 1

16-Bit Bus

BYTE = 0 BYTE = 0

18-Bit Bus

BYTE = 0

BYTE = 1

Data Bus

BUS18/16 = 0 BUS18/16 = 0 BUS18/16 = 1 BUS18/16 = 0 BUS18/16 = 1 BUS18/16 = 0

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

16

17

18

19

20

21

22

23

26

27

28

29

30

31

32

33

34

35

O

D17 (MSB)

D16

D15

D14

D13

D12

D11

D10

D9

All ones

D1

D17 (MSB)

D16

D15

D14

D13

D12

D11

D10

D9

All ones

D1

D17 (MSB)

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D0(LSB)

All ones

DB8

D8

DB7

D7

DB6

D6

DB5

D5

DB4

D4

DB3

D3

DB2

D2

D0 (LSB)

All ones

D2

DB1

D1

DB0

D0 (LSB)

–IN

7

I

Invertinginputchannel

Noninvertinginputchannel

Noconnection

+IN

6

3

NC

–

I

REFIN

REFM

RD

1

Referenceinput.

47, 48

41

I

Referenceground.

I

Synchronization pulse for the parallel output.

Analog power supplies, 5-V dc

+VA

4, 9, 10,

–

13, 43, 46

+VBD

24, 37

–

Digital power supply for bus

9

ADS8383

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SLAS005B– DECEMBER 2002 – REVISED MAY 2003

TIMING DIAGRAMS

t

w2

w1

CONVST

t

pd2

pd1

t

w4

t

w3

BUSY

t

su1

CS

†

CONVERT

t

(CONV)

t

(CONV)

†

SAMPLING

(When CS Toggle)

t

(ACQ)

BYTE

t

h1

BUS 18/16

t

su2

t

pd4

t

h2

t

d1

RD

t

en

dis

Hi–Z

MSB

D[17:12] D[9:4]

DB[17:12]

Hi–Z

DB[11:10]

DB[9:0]

D[11:10]

D[9:0]

D[3:2] D[1:0]

†

Signal internal to device

Figure 1. Timing for Conversion and Acquisition Cycles With CS and RD Toggling

10

ADS8383

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CONVST

SLAS005B– DECEMBER 2002 – REVISED MAY 2003

t

w1

t

w2

t

pd2

pd1

t

w4

t

w3

BUSY

t

su1

CS

†

CONVERT

t

(CONV)

t

(CONV)

†

SAMPLING

(When CS Toggle)

t

(ACQ)

BYTE

t

h1

BUS 18/16

t

pd4

t

h2

RD = 0

t

en

t

dis

Hi–Z

MSB

D[17:12] D[9:4]

DB[17:12]

Hi–Z

DB[11:10]

DB[9:0]

D[11:10]

D[9:0]

D[3:2] D[1:0]

†

Signal internal to device

NOTE:

RD cannot be tied to BDGND. Three read cycles are required at power on.

Figure 2. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Held at BDGND After

Power-On Initialization

11

ADS8383

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SLAS005B– DECEMBER 2002 – REVISED MAY 2003

t

w1

t

w2

CONVST

t

pd1

pd2

t

w4

t

w3

BUSY

CS = 0

†

CONVERT

t

(CONV)

t

(CONV)

t

(ACQ)

†

SAMPLING

(When CS = 0)

BYTE

t

h1

BUS 18/16

t

pd4

t

h2

RD

t

en

dis

Hi–Z

MSB

D[17:12] D[9:4]

DB[17:12]

Hi–Z

DB[11:10]

DB[9:0]

D[11:10]

D[9:0]

D[3:2] D[1:0]

†

Signal internal to device

Figure 3. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling

12

ADS8383

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SLAS005B– DECEMBER 2002 – REVISED MAY 2003

t

w2

t

w1

CONVST

t

pd2

pd1

t

w4

t

w3

BUSY

CS = 0

†

CONVERT

t

(CONV)

t

(ACQ)

†

SAMPLING

(When CS = 0)

BYTE

BUS 18/16

t

h1

t

h1

RD = 0

t

d5

D[9:4]

DB[17:12]

DB[11:10]

NextD[17:12]

D[17:12]

D[3:2]

D[11:10]

D[9:0]

D[1:0]

Next D[11:10]

Next D[9:0]

DB[9:0]

†

Signal internal to device

NOTE:

RD cannot be tied to BDGND. Three read cycles are required at power on.

Figure 4. Timing for Conversion and Acquisition Cycles With CS and RD Held at BDGND After Power-On

Initialization - Auto Read

13

ADS8383

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SLAS005B– DECEMBER 2002 – REVISED MAY 2003

CS

RD

BYTE

BUS 18/16

t

en

t

d3

t

en

t

d3

dis

t

dis

Hi–Z

Valid

DB[17:0]

Figure 5. Detailed Timing for Read Cycles

14

ADS8383

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SLAS005B– DECEMBER 2002 – REVISED MAY 2003

TYPICAL CHARACTERISTICS^†

SIGNAL-TO-NOISE RATIO

vs

HISTOGRAM (DC Code Spread)

FREE-AIR TEMPERATURE

HALF SCALE 131071 CONVERSIONS

18000

16000

14000

12000

10000

8000

6000

4000

2000

0

87.9

87.8

87.7

87.6

87.5

87.4

87.3

87.2

+VA = 5 V,

+VBD = 3 V

Code = 131046

+VA = 5 V,

+VBD = 3 V

–40 –25 –10

5

20

35

50

65

80

T

A

– Free-Air Temperature – °C

Figure 7

Figure 6

SIGNAL-TO-NOISE + DISTORTION

vs

SPURIOUS FREE DYNAMIC RANGE

vs

FREE-AIR TEMPERATURE

87.9

116

115

114

113

112

111

110

109

108

107

106

+VA = 5 V,

+VBD = 3 V

+VA = 5 V,

+VBD = 3 V

87.8

87.7

87.6

87.5

87.4

87.3

87.2

–40 –25 –10

5

20

35

50

65

80

–40 –25 –10

5

20

35

50

65

80

T

A

– Free-Air Temperature – °C

T

A

– Free-Air Temperature – °C

Figure 9

Figure 8

†

At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V and f

= 500 kHz (unless otherwise noted)

sample

15

ADS8383

www.ti.com

SLAS005B– DECEMBER 2002 – REVISED MAY 2003

EFFECTIVE NUMBER OF BITS

vs

FREE-AIR TEMPERATURE

TOTAL HARMONIC DISTORTION

vs

FREE-AIR TEMPERATURE

14.31

14.30

14.29

14.28

14.27

14.26

14.25

14.24

14.23

14.22

14.21

14.20

–104

+VA = 5 V,

+VBD = 3 V

+VA = 5 V,

+VBD = 3 V

–105

–106

–107

–108

–109

–110

–111

–40 –25 –10

5

20

35

50

65

80

–40 –25 –10

5

20

35

50

65

80

T

A

– Free-Air Temperature – °C

T

A

– Free-Air Temperature – °C

Figure 11

Figure 10

SIGNAL-TO-NOISE RATIO

vs

SIGNAL-TO-NOISE + DISTORTION

vs

INPUT FREQUENCY

87.26

87.25

87.24

87.23

87.22

87.21

87.20

87.19

87.18

87.17

87.16

87.15

89.0

88.5

88.0

87.5

87.0

86.5

86.0

85.5

85.0

+VA = 5 V,

+VBD = 3 V

+VA = 5 V,

+VBD = 3 V

0

20

40

60

80

100

0

20

40

60

80

100

f – Input Frequency – kHz

i

f – Input Frequency – kHz

i

Figure 12

Figure 13

†

At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V and f

= 500 kHz (unless otherwise noted)

sample

16

ADS8383

www.ti.com

SLAS005B– DECEMBER 2002 – REVISED MAY 2003

SPURIOUS FREE DYNAMIC RANGE

EFFECTIVE NUMBER OF BITS

vs

INPUT FREQUENCY

120

115

110

105

100

95

14.25

14.20

14.15

14.10

14.05

14.00

13.95

13.90

+VA = 5 V,

+VBD = 3 V

+VA = 5 V,

+VBD = 3 V

90

13.85

0

20

40

60

80

100

20

40

60

80

100

f – Input Frequency – kHz

i

f – Input Frequency – kHz

i

Figure 15

Figure 14

TOTAL HARMONIC DISTORTION

SUPPLY CURRENT

vs

INPUT FREQUENCY

SAMPLE RATE

–80

–85

19

18

17

16

15

14

+VA = 5 V,

+VBD = 3 V

+VA = 5 V,

Current of +VA only

–90

–95

–100

–105

–110

–115

0

20

40

60

80

100

125

250

375

500

Sample Rate – KSPS

f – Input Frequency – kHZ

i

Figure 16

Figure 17

†

At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V and f

= 500 kHz (unless otherwise noted)

sample

17

ADS8383

www.ti.com

SLAS005B– DECEMBER 2002 – REVISED MAY 2003

INTEGRAL NONLINEARITY

DIFFERENTIAL NONLINEARITY

vs

SAMPLE RATE

3.0

2.5

2.0

1.50

1.25

Max

1.00

+VA = 5 V,

= 25 °C

1.5

Max

T

A

1.0

0.75

0.5

+VA = 5 V,

0.50

0.0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

T

A

= 25 °C

0.25

0.00

–0.25

–0.50

–0.75

–1.00

Min

350

125

200

275

350

425

500

125

200

275

425

500

Sample Rate – KSPS

Figure 18

Figure 19

OFFSET VOLTAGE

vs

SUPPLY VOLTAGE

GAIN ERROR

vs

SUPPLY VOLTAGE

–0.30

–0.32

–0.34

–0.36

–0.38

–0.40

–0.42

–0.44

–0.46

–0.48

0

T

A

= 25 °C

–2

–0.002

–0.004

–4

–0.006

–6

–0.008

–8

–0.010

–10

–0.012

–12

4.75

5.00

5.25

4.75

5.00

5.25

+V – Supply Voltage – V

A

+V – Supply Voltage – V

A

Figure 21

Figure 20

†

At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V and f

= 500 kHz (unless otherwise noted)

sample

18

ADS8383

www.ti.com

SLAS005B– DECEMBER 2002 – REVISED MAY 2003

GAIN ERROR

vs

SUPPLY CURRENT

vs

FREE-AIR TEMPERATURE

SUPPLY VOLTAGE

–0.01

–0.02

–0.03

20.0

19.5

19.0

18.5

18.0

17.5

T

= 25 °C,

A

Current of +VA only

V

= 4.1 V

ref

V

ref

= 2.5 V

17.0

4.75

–40

–20

0

20

40

60

80

5.00

5.25

+V – Supply Voltage – V

A

T

A

– Free-Air Temperature – °C

Figure 23

Figure 22

OFFSET VOLTAGE

vs

TEMPERATURE

SUPPLY CURRENT

vs

FREE-AIR TEMPERATURE

–0.20

–0.22

–0.24

–0.26

–0.28

–0.30

–0.32

18.14

V

ref

= 4.096 V

+VA = 5 V,

+VA = 5 V

18.12

18.10

18.08

18.06

18.04

18.02

18.00

17.98

17.96

T

A

= 25 °C

V

= 2.5 V

ref

–40 –25 –10

5

20

35

50

65

80

–40

–20

0

T

A

20

40

60

80

T

A

– Temperature – °C

Figure 24

Figure 25

†

At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V and f

= 500 kHz (unless otherwise noted)

sample

19

ADS8383

www.ti.com

SLAS005B– DECEMBER 2002 – REVISED MAY 2003

DIFFERENTIAL NONLINEARITY (Min)

DIFFERENTIAL NONLINEARITY (Max)

vs

TEMPERATURE

–0.60

–0.65

–0.70

–0.75

–0.80

–0.85

–0.90

–0.95

–1.00

1.8

1.7

1.6

1.5

1.4

1.3

1.2

+VA = 5 V,

= 25 °C

+VA = 5 V,

= 25 °C

T

A

T

A

Max

Min

–40 –25 –10

5

20

35

50

65

80

–40 –25 –10

5

20

35

50

65

80

T

A

– Temperature – °C

T

A

– Temperature – °C

Figure 27

Figure 26

INTEGRAL NONLINEARITY (Max)

INTEGRAL NONLINEARITY (Min)

vs

TEMPERATURE

4.5

4.0

3.5

3.0

2.5

2.0

–2.0

–2.2

–2.4

–2.6

–2.8

–3.0

–3.2

–3.4

–3.6

+VA = 5 V,

T = 25 °C

A

T

= 25 °C

A

Max

Min

–40 –25 –10

5

20

35

50

65

80

–40 –25 –10

5

20

T – Temperature – °C

A

35

50

65

80

T

– Temperature – °C

A

Figure 28

Figure 29

†

At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V and f

= 500 kHz (unless otherwise noted)

sample

20

ADS8383

www.ti.com

SLAS005B– DECEMBER 2002 – REVISED MAY 2003

OFFSET VOLTAGE

vs

REFERENCE VOLTAGE

INTEGRAL NONLINEARITY

vs

REFERENCE VOLTAGE

–0.20

–0.22

–0.24

–0.26

–0.28

–0.30

–0.32

–0.34

–0.36

–0.38

–0.40

5

4

+VA = 5 V,

T

A

= 25 °C

Max

3

2

1

+VA = 5 V

Min

0

–1

–2

–3

–4

–5

–6

2.5

3.0

3.5

4.0

2.0

2.5

3.0

3.5

4.0

4.5

V

ref

– Reference Voltage – V

V

ref

– Reference Voltage – V

Figure 30

Figure 31

DIFFERENTIAL NONLINEARITY

vs

REFERENCE VOLTAGE

5

4

+VA = 5 V

Max

3

2

1

0

Min

–1

–2

2.0

2.5

3.0

3.5

4.0

4.5

V

ref

– Reference Voltage – V

Figure 32

†

At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V and f

= 500 kHz (unless otherwise noted)

sample

21

ADS8383

www.ti.com

SLAS005B– DECEMBER 2002 – REVISED MAY 2003

DIFFERENTIAL LINEARITY ERROR

vs

CODE

3

2.5

2

1.5

1

0.5

0

–0.5

–1

–1.5

–2

–2.5

–3

0

65536

131072

Code

196605

262144

Figure 33

INTEGRAL LINEARITY ERROR

vs

CODE

7

5

3

1

–1

–3

–5

–7

0

65536

131072

Code

196608

262144

Figure 34

FFT SPECTRAL RESPONSE (100 kHz Input)

0

–20

–40

–60

16384Points, f = 500 kHz,

s

(+IN – –IN) = 4 V

P-P

–80

–100

–120

–140

–160

–180

0

50000

100000

150000

200000

250000

f – Frequency – Hz

Figure 35

†

At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V and f

= 500 kHz (unless otherwise noted)

sample

22

ADS8383

www.ti.com

SLAS005B– DECEMBER 2002 – REVISED MAY 2003

FFT SPECTRAL RESPONSE (50 kHz Input)

0

–20

–40

16384Points, f = 500 kHz,

s

(+IN – –IN) = 4 V

P-P

–60

–80

–100

–120

–140

–160

–180

0

50000

100000

150000

200000

250000

f – Frequency – Hz

Figure 36

†

At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V and f

= 500 kHz (unless otherwise noted)

sample

23

ADS8383

www.ti.com

SLAS005B– DECEMBER 2002 – REVISED MAY 2003

APPLICATION INFORMATION

MICROCONTROLLER INTERFACING

ADS8383 to 8-Bit Microcontroller Interface

Figure 37 shows a parallel interface between the ADS8383 and a typical microcontroller using the 8-bit data bus.

The BUSY signal is used as a falling-edge interrupt to the microprocessor.

Analog 5 V

0.1 µF

AGND

10 µF

Ext Ref Input

0.1 µF

Analog Input

Ext Bias Voltage

BIAS

Micro

Controller

1 µF

Digital 3 V

AGND

GPIO

CS

BYTE

BUS18/16

CONVST

RD

AD8383

0.1 µF

GPIO

BDGND

+VBD

BDGND

RD

AD[7:0]

DB[17:10]

Data Bus D[17:0]

Figure 37. ADS8383 Application Circuitry

24

ADS8383

www.ti.com

SLAS005B– DECEMBER 2002 – REVISED MAY 2003

PRINCIPLES OF OPERATION

The ADS8383 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The

architecture is based on charge redistribution which inherently includes a sample/hold function. See Figure 37 for

the application circuit for the ADS8383.

The conversion clock is generated internally. The conversion time of 1.6 µs is capable of sustaining a 500-kHz

throughput.

The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input on

these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected

from any internal function.

REFERENCE

The ADS8383 can operate with an external 4.096-V reference for a corresponding full-scale range of 4.096 V.

BIASING THE ADS8383

The ADS8383 requires an external 2.048-V bandgap reference to generate the bias currents for internal circuitry.

Figure 38 shows the internal circuitry used to generate the bias currents. The bias generation circuit also pumps

100 µA (150 µA max) out from the BIAS pin. The bandgap used should be capable of sinking 100 µA (150 µA max)

while holding the voltage on the pin steady. Table 1 shows the specification of the bandgap used to drive the BIAS

pin of the ADS8383.

5 V

+V

A

ADS8383

100 µA

BIAS_INT

BIAS

AGND

Figure 38. Bias Current Generation

Table 1. Bias Specifications

PARAMETER

MIN

TYP

2.048

100

MAX

2.1

UNITS

Output Voltage

2

V

I

150

µA

sink

Any common bandgap like REF3020 can be used to drive the BIAS pin of the ADS8383. Figure 39 shows how

REF3020 can be used with the ADS8383. A 1 µF decoupling capacitor is recommended between pins 2 and AGND

of the ADS8383 for optimal performance.

5 V

1

2

50 Ω

REF3020

3

2

0.47 µF

ADS8383

22 µF

AGND

Figure 39. Using the REF3020 to Drive the ADS8383 BIAS Pin

25

ADS8383

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SLAS005B– DECEMBER 2002 – REVISED MAY 2003

ANALOG INPUT

When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs is captured on the

internal capacitor array. The voltage on the –IN input is limited between –0.2 V and 0.2 V, allowing the input to reject

small signals which are common to both the +IN and –IN inputs. The +IN input has a range of –0.2 V to V + 0.2 V.

ref

The input span (+IN – (–IN)) is limited to 0 V to V

.

ref

The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source

impedance. Essentially, the current into the ADS8383 charges the internal capacitor array during the sample period.

After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage

must be able to charge the input capacitance (45 pF) to an 18-bit settling level within the acquisition time (400 ns)

of the device. When the converter goes into the hold mode, the input impedance is greater than 1 GΩ.

Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the +IN

and –IN inputs and the span (+IN – (–IN)) should be within the limits specified. Outside of these ranges, the

converter’s linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters

should be used.

Care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are matched.

If this is not observed, the two inputs could have different setting times. This may result in offset error, gain error, and

linearity error which changes with temperature and input voltage.

DIGITAL INTERFACE

Timing And Control

Seethetimingdiagramsinthespecificationssectionfordetailedinformationontimingsignalsandtheirrequirements.

The ADS8383 uses an internal oscillator generated clock which controls the conversion rate and in turn the

throughput of the converter. No external clock input is required.

Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum

requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8383 switches from the

sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of this signal

is important to the performance of the converter. The BUSY output is brought high immediately following CONVST

going low. BUSY stays high through the conversion process and returns low when the conversion has ended.

Sampling starts with the falling edge of the BUSY signal when CS is tied low or starts with the falling edge of CS when

BUSY is low.

Both RD and CS can be high during and before a conversion with one exception (CS must be low when CONVST

goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the parallel output bus

with the conversion.

Reading Data

The ADS8383outputsfullparalleldatainstraightbinaryformatasshowninTable 2. The parallel output is activewhen

CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of CONVST. This is 125

ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should be attempted within this

zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE and BUS18/16 are used for

multiword read operations. BYTE is used whenever lower bits on the bus are output on the higher byte of the bus.

BUS18/16 is used whenever the last two bits on the 18-bit bus is output on either bytes of the higher 16-bit bus. Refer

to Table 2 for ideal output codes.

26

ADS8383

www.ti.com

SLAS005B– DECEMBER 2002 – REVISED MAY 2003

Table 2. Ideal Input Voltages and Output Codes

DESCRIPTION

FULL SCALE RANGE

Least significant bit (LSB)

Full scale

ANALOG VALUE

DIGITAL OUTPUT STRAIGHT BINARY

V

ref

V

/262144

– 1 LSB

/2

BINARY CODE

HEX CODE

3FFFF

ref

V

11 1111 1111 1111 1111

10 0000 0000 0000 0000

01 1111 1111 1111 1111

00 0000 0000 0000 0000

ref

Midscale

V

20000

ref

Midscale – 1 LSB

Zero

V

/2 – 1 LSB

ref

0 V

1FFFF

00000

The output data is a full 18-bit word (D17–D0) on DB17–DB0 pins (MSB–LSB) if both BUS18/16 and BYTE are low.

The result may also be read on a 16-bit bus by using only pins DB17–DB2. In this case two reads are necessary:

the first as before, leaving both BUS18/16 and BYTE low and reading the 16 most significant bits (D17–D2) on pins

DB17–DB2, then bringing BUS18/16 high while holding BYTE low. When BUS18/16 is high, the lower two bits

(D1–D0) appear on pins DB3–DB2.

The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB17–DB10. In this

case three reads are necessary: the first as before, leaving both BUS18/16 and BYTE low and reading the 8 most

significant bits on pins DB17–DB10, then bringing BYTE high while holding BUS18/16 low. When BYTE is high, the

medium bits (D9–D2) appear on pins DB17–DB10. The last read is done by bringing BUS18/16 high while holding

BYTE high. When BUS18/16 is high, the lower two bits (D1–D0) appear on pins DB11–DB10. The last read cycle

is not necessary if only the first 16 most significant bits are of interest.

All of these multiword read operations can be performed with multiple active RD (toggling) or with RD held low for

simplicity. This is referred to as the AUTO READ operation. Note that RD may not be tied to BDGND permanently

due to the requirement of power-on initialization.

Table 3. Conversion Data Read Out

DATA READ OUT

BYTE

BUS18/16

High

DB17–DB12 DB11–DB10

DB9–DB4

All One’s

D9–D4

DB3–DB2

All One’s

D1–D0

DB1–DB0

All One’s

D1–D0

High

Low

High

Low

All One’s

D9–D4

D1–D0

High

Low

All One’s

D3–D2

All One’s

D3–D2

D17–D12

D11–D10

POWER-ON INITIALIZATION

At first power on there are three read cycles required (RD must be toggled three times). If conversion cycle is

attempted before these intialization read cycles, the first three conversion cycles will not produce valid results. This

is used to load factory trimming data for a specific device to assure high accuracy of the converter. Because of this

requirement, the RD pin cannot be tied permanently to BDGND. System designers can still achieve the AUTO READ

function if the power-on requirement is satisfied.

LAYOUT

For optimum performance, care should be taken with the physical layout of the ADS8383 circuitry.

As the ADS8383 offers single-supply operation, it will often be used in close proximity with digital logic,

microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the

higher the switching speed, the more difficult it is to achieve good performance from the converter.

The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground

connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving any

single conversion for an n-bit SAR converter, there are at least n windows in which large external transient voltages

can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic,

or high power devices.

The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external

event.

27

ADS8383

www.ti.com

SLAS005B – DECEMBER 2002 – REVISED MAY 2003

On average, the ADS8383 draws very little current from an external reference as the reference voltage is internally

buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass

capacitor or capacitors without oscillation. A 0.1-µF bypass capacitor is recommended from pin 1 (REFIN) directly

to pin 48 (REFM). REFM and AGND should be shorted on the same ground plane under the device.

The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the analog

ground. Avoid connections which are too close to the grounding point of a microcontroller or digital signal processor.

If required, run a ground trace directly from the converter to the power supply entry point. The ideal layout consists

of an analog ground plane dedicated to the converter and associated analog circuitry.

As with the AGND connections, +VA should be connected to a 5-V power supply plane or trace that is separate from

the connection for digital logic until they are connected at the power entry point. Power to the ADS8383 should be

clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device as possible.

See Table 4 for the placement of the capacitor. In addition, a 1-µF to 10-µF capacitor is recommended. In some

situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor or even a Pi filter made up

of inductors and capacitors—all designed to essentially low-pass filter the 5-V supply, removing the high frequency

noise.

Table 4. Power Supply Decoupling Capacitor Placement

POWER SUPPLY PLANE

CONVERTER ANALOG SIDE

CONVERTER DIGITAL SIDE

SUPPLY PINS

Pin pairs that require shortest path to decoupling capacitors

Pins that require no decoupling

(4,5), (8,9), (10,11), (13,15),

(43,44),(45,46)

(24,25)

37

12, 14

28

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

copyright, maskworkright, orotherTIintellectualpropertyrightrelatingtoanycombination, machine, orprocess

in which TI products or services are used. Information published by TI regarding third–party products or services

does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.

Use of such information may require a license from a third party under the patents or other intellectual property

of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

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Mailing Address:

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Post Office Box 655303

Dallas, Texas 75265


型号：	ADS8383IPFBT
厂家：	TEXAS INSTRUMENTS
描述：	18-BIT, 500-kHz, UNIPOLAR INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE 18位， 500千赫，单极性输入，并行接口微功耗采样模拟数字转换器转换器输入元件
文件：	总29页 (文件大小：164K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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ADS8401IBPFBRG4

ADS8401IBPFBT

ADS8401IBPFBTG4

ADS8401IPFBR

ADS8401IPFBR

ADS8401IPFBT

ADS8401IPFBT