ADS8557 [TI]
16-14-12-Bit Six-Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTERS; 16-14-12位六通道同时采样的模拟数字转换器
| 型号： | ADS8557 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-14-12-Bit Six-Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTERS |
| 文件： | 总40页 (文件大小：870K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS8556
ADS8557
ADS8558
www.ti.com ............................................................................................................................................... SBAS404A–OCTOBER 2006–REVISED AUGUST 2009
16-, 14-, 12-Bit, Six-Channel, Simultaneous Sampling
ANALOG-TO-DIGITAL CONVERTERS
1
FEATURES
DESCRIPTION
2
•
Family of 16-, 14-, 12-Bit, Pin- and
Software-Compatible ADCs
The ADS8556/7/8 contain six low-power, 16-, 14-, or
12-bit, successive approximation register (SAR)
based analog-to-digital converters (ADCs) with true
•
•
Six SAR ADCs Grouped in Three Pairs
bipolar
inputs.
Each
channel
contains
a
Maximum Data Rate Per Channel with Internal
Conversion Clock and Reference:
ADS8556: 630kSPS (PAR) or 450kSPS (SER)
ADS8557: 670kSPS (PAR) or 470kSPS (SER)
ADS8558: 730kSPS (PAR) or 500kSPS (SER)
sample-and-hold circuit that allows simultaneous
high-speed multi-channel signal acquisition.
The ADS8556/7/8 support data rates of up to
730kSPS in parallel interface mode or up to 500kSPS
if the serial interface is used. The bus width of the
parallel interface can be set to eight or 16 bits. In
serial mode, up to three output channels can be
activated.
•
Maximum Data Rate with External Conversion
Clock and Reference:
800kSPS (PAR) or 530kSPS (SER)
•
•
Pin-Selectable or Programmable Input Voltage
Ranges: Up to ±12V
The ADS8556/7/8 is specified over the full industrial
temperature range of –40°C to +125°C and is
available in an LQFP-64 package.
Excellent Signal-to-Noise Performance:
91.5dB (ADS8556)
85dB (ADS8557)
ADS8556
Clock
Generator
ADS8557
ADS8558
73.9dB (ADS8558)
CONVST_A
CH_A0
Comparator
•
•
Programmable and Buffered Internal
Reference: 0.5V to 2.5V and 0.5V to 3.0V
CDAC 1
S/H
AGND
BUSY/INT
RANGE/XCLK
HW/SW
Buffer
Control
Logic
Comprehensive Power-Down Modes:
Deep Power-Down (Standby Mode)
Partial Power-Down
SAR Register 1/2
REF /WR
EN
STBY
RESET
REFC_A
CH_A1
CDAC 2
S/H
AGND
Auto-Nap Power-Down
Comparator
Comparator
•
•
Selectable Parallel or Serial Interface
CONVST_B
CH_B0
CDAC 3
S/H
Operating Temperature Range:
–40°C to +125°C
AGND
Buffer
Config
Register
SAR Register 3/4
•
LQFP-64 Package
REFC_B
CH_B1
CDAC 4
S/H
AGND
APPLICATIONS
Comparator
Comparator
•
•
•
•
•
Power Quality Measurement
Protection Relays
Multi-Axis Motor Control
Programmable Logic Controllers
Industrial Data Acquisition
CONVST_C
CH_C0
CDAC 5
S/H
AGND
Buffer
CS/FS
SAR Register 5/6
RD
I/O
DB[15:0]
WORD/BYTE
PAR/SER
REFC_C
CH_C1
CDAC 6
S/H
AGND
Comparator
Buffer
BVDD
BGND
Internal 2.5V
Reference
String DAC
REF_IO
AVDD
AGND
HVDD
HVSS
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2009, Texas Instruments Incorporated
ADS8556
ADS8557
ADS8558
SBAS404A–OCTOBER 2006–REVISED AUGUST 2009 ............................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
RESOLUTION
(Bits)
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
ADS8556IPM
ADS8556IPMR
ADS8557IPM
ADS8557IPMR
ADS8558IPM
ADS8558IPMR
Tray, 160
Tape and Reel, 1000
Tray, 160
ADS8556I
16
14
12
LQFP-64
LQFP-64
LQFP-64
PM
PM
PM
ADS8557I
ADS8558I
Tape and Reel, 1000
Tray, 160
Tape and Reel, 1000
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
ADS8556, ADS8557, ADS8558
–0.3 to +18
UNIT
V
Supply voltage, HVDD to AGND
Supply voltage, HVSS to AGND
Supply voltage, AVDD to AGND
Supply voltage, BVDD to BGND
Analog input voltage
–18 to +0.3
V
–0.3 to +6
V
–0.3 to +6
V
HVSS – 0.3 to HVDD + 0.3
AGND – 0.3 to AVDD + 0.3
BGND – 0.3 to BVDD + 0.3
±0.3
V
Reference input voltage with respect to AGND
Digital input voltage with respect to BGND
Ground voltage difference AGND to BGND
Input current to all pins except supply
Maximum virtual junction temperature, TJ
Human body model (HBM)
V
V
V
–10 to +10
mA
°C
+150
±2000
±500
V
V
JEDEC standard 22, test method A114-C.01, all pins
ESD ratings
Charged device model (CDM)
JEDEC standard 22, test method C101, all pins
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
Copyright © 2006–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8556 ADS8557 ADS8558
ADS8556
ADS8557
ADS8558
www.ti.com ............................................................................................................................................... SBAS404A–OCTOBER 2006–REVISED AUGUST 2009
RECOMMENDED OPERATING CONDITIONS
MIN
4.5
TYP
5
MAX
5.5
UNIT
V
Supply voltage, AVDD to AGND
Supply voltage, BVDD to BGND
Low-voltage levels
5V logic levels
2.7
3.0
5
3.6
V
4.5
5.5
V
Range 1 (±2 × VREF
Range 2 (±4 × VREF
Range 1 (±2 × VREF
Range 2 (±4 × VREF
)
)
)
)
2 × VREF
4 × VREF
–16.5
–16.5
0.5
16.5
V
Input supply voltage, HVDD to AGND
Input supply voltage, HVSS to AGND
16.5
V
–2 × VREF
–4 × VREF
3.0
V
V
Reference input voltage (VREF
Analog inputs
)
2.5
V
Range 1 (±2 × VREF
Range 1 (±4 × VREF
)
)
–2 × VREF
–4 × VREF
–40
+2 × VREF
+4 × VREF
+125
V
(also see the Analog Inputs section)
V
Operating ambient temperature range, TA
°C
DISSIPATION RATINGS(1)
DERATING FACTOR
ABOVE TA = +25°C
T
A ≤ +25°C
TA = +70°C
POWER RATING
TA = +85°C
POWER RATING
TA = +125°C
POWER RATING
PACKAGE
POWER RATING
LQFP-64
20.8mW/°C
2.60W
1.66W
1.35W
0.52W
(1) Based on High-K θJA
.
THERMAL CHARACTERISTICS
Over recommended operating conditions, unless otherwise noted.
ADS8556, ADS8557, ADS8558
PARAMETER
TEST CONDITIONS
MIN
TYP
74
MAX
UNIT
°C/W
°C/W
Low-K thermal resistance(1)
High-K thermal resistance(1)
θJA
Junction-to-air thermal resistance
48
Junction-to-case thermal
resistance
θJC
16
°C/W
mW
mW
mW
ADS8556, HVDD = +15V, HVSS = –15V, AVDD = 5V,
BVDD = 3V, and fDATA = maximum
251.7
253.2
262.2
298.5
303.0
318.0
ADS8557, HVDD = +15V, HVSS = –15V, AVDD = 5V,
BVDD = 3V, and fDATA = maximum
PD
Device power dissipation
ADS8558, HVDD = +15V, HVSS = –15V, AVDD = 5V,
BVDD = 3V, and fDATA = maximum
(1) Modeled in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3.
Copyright © 2006–2009, Texas Instruments Incorporated
3
Product Folder Link(s): ADS8556 ADS8557 ADS8558
ADS8556
ADS8557
ADS8558
SBAS404A–OCTOBER 2006–REVISED AUGUST 2009 ............................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS: ADS8556
Over recommended operating free-air temperature range of –40°C to +125°C, AVDD = 4.5V to 5V, BVDD = 2.7V to 5.5V,
HVDD = 10V to 15V, HVSS = –15V to –10V, VREF = 2.5V (internal), and fDATA = 630kSPS in parallel mode or 450kSPS in
serial mode, unless otherwise noted.
ADS8556
PARAMETER
CONDITIONS
MIN
TYP(1)
MAX
UNIT
DC ACCURACY
Resolution
16
Bits
Bits
No missing codes
16
–3
At TA = –40°C to +85°C
±1.5
±1.5
±0.75
±0.75
±0.8
±3.5
±0.25
±6
3
4
LSB
Integral linearity error
INL
At TA = –40°C to +125°C
At TA = –40°C to +85°C
At TA = –40°C to +125°C
–4
LSB
–1
1.5
2
LSB
Differential linearity error
DNL
–1
LSB
Offset error
–4.0
4.0
mV
Offset error drift
µV/°C
%FSR
ppm/°C
dB
Gain error
Referenced to voltage at REFIO
Referenced to voltage at REFIO
–0.75
280
0.75
Gain error drift
Power-supply rejection ratio
SAMPLING DYNAMICS
Acquisition time
PSRR At output code FFFFh, related to AVDD
60
tACQ
ns
µs
Conversion time per ADC
tCONV
1.26
18.5
68.0
tCCLK
ns
Internal conversion clock period
Throughput rate
tCCLK
Parallel interface,
internal clock and reference
630
450
kSPS
kSPS
fDATA
Serial interface,
internal clock and reference
AC ACCURACY
At fIN = 10kHz, TA = –40°C to +85°C
SNR
90
89
91.5
91.5
89.5
89.5
–94
–94
95
dB
dB
dB
dB
dB
Signal-to-noise ratio
At fIN = 10kHz, TA = –40°C to +125°C
At fIN = 10kHz, TA = –40°C to +85°C
SINAD
87
Signal-to-noise ratio + distortion
Total harmonic distortion(2)
At fIN = 10kHz, TA = –40°C to +125°C
86.5
At fIN = 10kHz, TA = –40°C to +85°C
THD
–90
At fIN = 10kHz, TA = –40°C to +125°C
–89.5
At fIN = 10kHz, TA = –40°C to +85°C
SFDR
90
dB
dB
Spurious-free dynamic range
Channel-to-channel isolation
–3dB small-signal bandwidth
At fIN = 10kHz, TA = –40°C to +125°C
89.5
95
At fIN = 10kHz
100
48
dB
In 4 × VREF mode
In 2 × VREF mode
MHz
MHz
24
(1) All values are at TA = +25°C.
(2) Calculated on the first nine harmonics of the input frequency.
4
Copyright © 2006–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8556 ADS8557 ADS8558
ADS8556
ADS8557
ADS8558
www.ti.com ............................................................................................................................................... SBAS404A–OCTOBER 2006–REVISED AUGUST 2009
ELECTRICAL CHARACTERISTICS: ADS8557
Over recommended operating free-air temperature range of –40°C to +125°C, AVDD = 4.5V to 5.5V, BVDD = 2.7V to 5.5V,
HVDD = 10V to 15V, HVSS = –15V to –10V, VREF = 2.5V (internal), and fDATA = 670kSPS in parallel mode or 470kSPS in
serial mode, unless otherwise noted.
ADS8557
PARAMETER
CONDITIONS
MIN
TYP(1)
MAX
UNIT
DC ACCURACY
Resolution
14
Bits
Bits
No missing codes
Integral linearity error
14
–1
–1
–4
INL
±0.4
±0.25
±0.8
±3.5
±0.25
±6
1
1
4
LSB
Differential linearity error
Offset error
DNL
LSB
mV
Offset error drift
µV/°C
%FSR
ppm/°C
dB
Gain error
Referenced to voltage at REFIO
Referenced to voltage at REFIO
–0.75
0.75
Gain error drift
Power-supply rejection ratio
SAMPLING DYNAMICS
Acquisition time
PSRR At output code FFFFh, related to AVDD
60
tACQ
280
ns
µs
Conversion time per ADC
tCONV
1.19
18.5
64.1
tCCLK
ns
Internal conversion clock period
Throughput rate
tCCLK
Parallel interface,
internal clock and reference
670
470
kSPS
kSPS
fDATA
Serial interface,
internal clock and reference
AC ACCURACY
Signal-to-noise ratio
SNR At fIN = 10kHz
SINAD At fIN = 10kHz
THD At fIN = 10kHz
SFDR At fIN = 10kHz
At fIN = 10kHz
84
83
85
84
dB
dB
Signal-to-noise ratio + distortion
Total harmonic distortion(2)
Spurious-free dynamic range
Channel-to-channel isolation
–91
92
–86
dB
86
dB
100
48
dB
In 4 × VREF mode
MHz
MHz
–3dB small-signal bandwidth
In 2 × VREF mode
24
(1) All values are at TA = +25°C.
(2) Calculated on the first nine harmonics of the input frequency.
Copyright © 2006–2009, Texas Instruments Incorporated
5
Product Folder Link(s): ADS8556 ADS8557 ADS8558
ADS8556
ADS8557
ADS8558
SBAS404A–OCTOBER 2006–REVISED AUGUST 2009 ............................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS: ADS8558
Over recommended operating free-air temperature range of –40°C to +125°C, AVDD = 4.5V to 5V, BVDD = 2.7V to 5.5V,
HVDD = 10V to 15V, HVSS = –15V to –10V, VREF = 2.5V (internal), and fDATA = 730kSPS in parallel mode or 500kSPS in
serial mode, unless otherwise noted.
ADS8558
PARAMETER
CONDITIONS
MIN
TYP(1)
MAX
UNIT
DC ACCURACY
Resolution
12
Bits
Bits
No missing codes
Integral linearity error
12
INL
–0.75
–0.5
–4
±0.2
±0.2
±0.8
±3.5
±0.25
±6
0.75
LSB
Differential linearity error
Offset error
DNL
0.5
4
LSB
mV
Offset error drift
µV/°C
%FSR
ppm/°C
dB
Gain error
Referenced to voltage at REFIO
Referenced to voltage at REFIO
–0.75
0.75
Gain error drift
Power-supply rejection ratio
SAMPLING DYNAMICS
Acquisition time
PSRR At output code FFFFh, related to AVDD
60
tACQ
280
ns
µs
Conversion time per ADC
tCONV
1.09
18.5
58.8
tCCLK
ns
Internal conversion clock period
Throughput rate
tCCLK
Parallel interface,
internal clock and reference
730
500
kSPS
kSPS
fDATA
Serial interface,
internal clock and reference
AC ACCURACY
Signal-to-noise ratio
SNR At fIN = 10kHz
SINAD At fIN = 10kHz
THD At fIN = 10kHz
SFDR At fIN = 10kHz
At fIN = 10kHz
73
73
73.9
73.8
–89
92
dB
dB
Signal-to-noise ratio + distortion
Total harmonic distortion(2)
Spurious-free dynamic range
Channel-to-channel isolation
–84
dB
84
dB
100
48
dB
In 4 × VREF mode
MHz
MHz
–3dB small-signal bandwidth
In 2 × VREF mode
24
(1) All values are at TA = +25°C.
(2) Calculated on the first nine harmonics of the input frequency.
6
Copyright © 2006–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8556 ADS8557 ADS8558
ADS8556
ADS8557
ADS8558
www.ti.com ............................................................................................................................................... SBAS404A–OCTOBER 2006–REVISED AUGUST 2009
ELECTRICAL CHARACTERISTICS: GENERAL
Over recommended operating free-air temperature range of –40°C to +125°C, AVDD = 4.5V to 5.5V, BVDD = 2.7V to 5.5V,
HVDD = 10V to 15V, HVSS = –15V to –10V, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted.
ADS8556, ADS8557, ADS8558
PARAMETER
ANALOG INPUT
CONDITIONS
MIN
TYP(1)
MAX
UNIT
RANGE pin/RANGE bit = 0
–4 × VREF
–2 × VREF
+4 × VREF
+2 × VREF
V
V
Bipolar full-scale range
Input capacitance
CHXX
RANGE pin/RANGE bit = 1
Input range = ±4 × VREF
Input range = ±2 × VREF
No ongoing conversion
10
20
pF
pF
µA
ns
ps
ps
Input leakage current
±1
Aperture delay
5
Aperture delay matching
Aperture jitter
Common CONVST for all channels
250
50
EXTERNAL CLOCK INPUT (XCLK)
External clock frequency
External clock duty cycle
REFERENCE VOLTAGE OUTPUT (REFOUT
fXCLK An external reference must be used for fXCLK > fCCLK
1
18
20
55
MHz
%
45
)
2.5V operation, REFDAC = 0x3FF
2.485
2.496
2.985
2.995
2.5
2.5
3.0
3.0
±10
73
2.515
2.504
3.015
3.005
V
V
2.5V operation, REFDAC = 0x3FF at +25°C
VREF
Reference voltage
3.0V operation, REFDAC = 0x3FF
V
3.0V operation, REFDAC = 0x3FF at +25°C
V
Reference voltage drift
Power-supply rejection ratio
Output current
dVREF/dT
ppm/°C
dB
PSRR
IREFOUT DC current
–2
2
mA
mA
ms
µF
Short-circuit current(2)
IREFSC
50
10
Turn-on settling time
tREFON
At CREF_x pins
4.7
10
External load capacitance
At REFIO pins
100
470
nF
Tuning range
REFDAC Internal reference output voltage range
0.2 × VREF
VREF
V
REFDAC resolution
10
–1
–2
–4
Bits
LSB
LSB
LSB
REFDAC differential nonlinearity
REFDAC integral nonlinearity
REFDAC offset error
DNLDAC
±0.1
±0.1
1
2
4
INLDAC
VOSDAC VREF = 0.5V (DAC = 0x0CC)
±0.65
REFERENCE VOLTAGE INPUT (REFIN
Reference input voltage
Input resistance
)
VREFIN
0.5
2.5
100
5
3.025
1
V
MΩ
pF
Input capacitance
Reference input current
SERIAL CLOCK INPUT (SCLK)
Serial clock input frequency
Serial clock period
µA
fSCLK
tSCLK
0.1
0.0278
40
36
10
60
MHz
µs
Serial clock duty cycle
DIGITAL INPUTS(3)
%
Logic family
CMOS with Schmitt-Trigger
High-level input voltage
Low-level input voltage
Input current
0.7 × BVDD
BVDD + 0.3
0.3 × BVDD
+50
V
V
BGND – 0.3
–50
VI = BVDD to BGND
nA
pF
Input capacitance
5
(1) All values are at TA = +25°C.
(2) Reference output current is not limited internally.
(3) Specified by design.
Copyright © 2006–2009, Texas Instruments Incorporated
7
Product Folder Link(s): ADS8556 ADS8557 ADS8558
ADS8556
ADS8557
ADS8558
SBAS404A–OCTOBER 2006–REVISED AUGUST 2009 ............................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS: GENERAL (continued)
Over recommended operating free-air temperature range of –40°C to +125°C, AVDD = 4.5V to 5.5V, BVDD = 2.7V to 5.5V,
HVDD = 10V to 15V, HVSS = –15V to –10V, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted.
ADS8556, ADS8557, ADS8558
PARAMETER
DIGITAL OUTPUTS(4)
CONDITIONS
MIN
TYP(1)
MAX
UNIT
Logic family
CMOS
High-level output voltage
Low-level output voltage
High-impedance-state output current
Output capacitance
IOH = 100µA
IOH = –100µA
BVDD – 0.6
BGND
BVDD
V
V
BGND + 0.4
50
–50
nA
pF
pF
5
Load capacitance
30
POWER-SUPPLY REQUIREMENTS
Analog supply voltage
AVDD
BVDD
HVDD
HVSS
4.5
2.7
5.0
3.0
5.5
5.5
V
V
Buffer I/O supply voltage
Input positive supply voltage
Input negative supply voltage
5.0
10.0
–10.0
30.0
14.0
14.0
14.0
16.5
–5.0
36.0
16.5
17.0
18.0
V
–16.5
V
fDATA = maximum
mA
mA
mA
mA
ADS8556, fDATA = 250kSPS (auto-NAP mode)
ADS8557, fDATA = 250kSPS (auto-NAP mode)
ADS8558, fDATA = 250kSPS (auto-NAP mode)
Analog supply current(5)
IAVDD
IBVDD
IHVDD
Auto-NAP mode, no ongoing conversion,
internal conversion clock
4.0
6.0
mA
Power-down mode
0.1
0.9
0.5
50.0
2.0
µA
mA
mA
fDATA = maximum
fDATA = 250kSPS (auto-NAP mode)
1.5
Buffer I/O supply current(6)
Auto-NAP mode, no ongoing conversion,
internal conversion clock
0.1
10.0
µA
Power-down mode
0.1
3.0
3.1
3.3
1.6
10.0
3.5
3.6
4.0
2.0
µA
mA
mA
mA
mA
ADS8556, fDATA = maximum
ADS8557, fDATA = maximum
ADS8558, fDATA = maximum
fDATA = 250kSPS (auto-NAP mode)
Input positive supply current(7)
Auto-NAP mode, no ongoing conversion,
internal conversion clock
0.2
0.3
µA
Power-down mode
0.1
3.6
3.6
4.0
1.8
10.0
4.0
4.2
4.8
2.2
µA
mA
mA
mA
mA
ADS8556, fDATA = maximum
ADS8557, fDATA = maximum
ADS8558, fDATA = maximum
fDATA = 250kSPS (auto-NAP mode)
Input negative supply current(8)
IHVSS
Auto-NAP mode, no ongoing conversion,
internal conversion clock
0.2
0.1
0.25
10.0
µA
µA
Power-down mode
(4) Specified by design.
(5) At AVDD = 5V.
(6) At BVDD = 3V, parallel mode, load capacitance = 6pF/pin.
(7) At HVDD = 15V.
(8) At HVSS = –15V.
8
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ELECTRICAL CHARACTERISTICS: GENERAL (continued)
Over recommended operating free-air temperature range of –40°C to +125°C, AVDD = 4.5V to 5.5V, BVDD = 2.7V to 5.5V,
HVDD = 10V to 15V, HVSS = –15V to –10V, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted.
ADS8556, ADS8557, ADS8558
PARAMETER
CONDITIONS
MIN
TYP(1)
MAX
UNIT
POWER-SUPPLY REQUIREMENTS (continued)
ADS8556, fDATA = maximum
251.7
298.5
mW
mW
mW
mW
mW
mW
ADS8557, fDATA = maximum
253.2
262.2
122.5
122.5
122.5
303.0
318.0
150.0
152.5
157.5
ADS8558, fDATA = maximum
ADS8556, fDATA = 250kSPS (auto-NAP mode)
ADS8557, fDATA = 250kSPS (auto-NAP mode)
ADS8558, fDATA = 250kSPS (auto-NAP mode)
Power dissipation(9)
Auto-NAP mode, no ongoing conversion,
internal conversion clock
26.0
3.8
38.3
mW
Power-down mode
580.0
µW
(9) At AVDD = 5V, BVDD = 3V, HVDD = 15V, and HVSS = –15V.
EQUIVALENT INPUT CIRCUITS
Input range: ±2VREF
Input range: ±4VREF
RSER = 200W RSW = 130W
RSER = 200W RSW = 130W
CH_XX
CH_XX
CS = 20pF
CS = 20pF
CS = 10pF
VDC
VDC
CPAR = 5pF
CPAR = 5pF
CS = 10pF
AGND
AGND
RSER = 200W RSW = 130W
RSER = 200W RSW = 130W
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PIN CONFIGURATION
PM PACKAGE
LQFP-64
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DB14/REFBUFEN
CH_C1
48
1
2
DB13/SDI
DB12
47 AVDD
46 AVDD
3
CH_C0
45
DB11
4
DB10/SDO_C
DB9/SDO_B
DB8/SDO_A
5
44 AGND
43 AGND
6
CH_B1
42
7
ADS8556
ADS8557
ADS8558
BGND
BVDD
8
41 AVDD
40 AVDD
9
DB7/HBEN/DCEN
CH_B0
39
10
11
12
13
14
15
16
DB6/SCLK
DB5/DCIN_A
DB4/DCIN_B
DB3/DCIN_C
DB2/SEL_C
DB1/SEL_B
38 AGND
37 AGND
CH_A1
36
35 AVDD
34 AVDD
CH_A0
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
10
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TERMINAL FUNCTIONS
DESCRIPTION
NAME
PIN #
TYPE(1)
PARALLEL INTERFACE (PAR/SER = 0)
SERIAL INTERFACE (PAR/SER = 1)
Hardware mode (HW/SW = 0):
Reference buffers enable input.
When low, all reference buffers are enabled (mandatory if
internal reference is used). When high, all reference buffers
are disabled.
Data bit 14 input/output
Output is '0' for the ADS8557/8
DB14/REFBUFEN
1
DIO/DI
Software mode (HW/SW = 1):Connect to BGND or BVDD.
The reference buffers are controlled by bit C24 (REFBUF) in
control register (CR).
Data bit 13 input/output
Output is MSB for the ADS8557 and '0' for the
ADS8558
Hardware mode (HW/SW = 0): Connect to BGND
Software mode (HW/SW = 1): Serial data input
DB13/SDI
2
DIO/DI
Data bit 12 input/output
Output is '0' for the ADS8558
DB12
DB11
3
4
5
DIO
DIO
Connect to BGND
Connect to BGND
Data bit 11 input/output
Output is MSB for the ADS8558
When SEL_C = 1, data output for channel C
When SEL_C = 0, this pin should be tied to BGND
DB10/SDO_C
DIO/DO
Data bit 10 input/output
Data bit 9 input/output
When SEL_B = 1, data output for channel B
When SEL_B = 0, this pin should be tied to BGND
When SEL_C = 0, data from channel C1 are also available
on this output
DB9/SDO_B
DB8/SDO_A
6
7
DIO/DO
DIO/DO
Data output for channel A
When SEL_C = 0, data from channel C0 are also available
on this output
Data bit 8 input/output
When SEL_C = 0 and SEL_B = 0, SDO_A acts as the single
data output for all channels
BGND
BVDD
8
9
P
P
Buffer IO ground, connect to digital ground plane
Buffer IO supply, connect to digital supply (2.7V to 5.5V). Decouple with a 1µF ceramic capacitor or a combination
of 100nF and 10µF ceramic capacitors to BGND.
Word mode (WORD/BYTE = 0):
Data bit 7 input/output
Daisy-chain enable input.
When high, DB[5:3] serve as daisy-chain inputs DCIN[A:C].
If daisy-chain mode is not used, connect to BGND.
When high, the high byte is output first on
Byte mode (WORD/BYTE = 1):
High byte enable input.
DB7/HBEN/DCEN
10
DIO/DI/DI
DB[15:8]. When low, the low byte is output first on
DB[15:8].
Word mode (WORD/BYTE = 0):
Data bit 6 input/output
DB6/SCLK
DB5/DCIN_A
DB4/DCIN_B
DB3/DCIN_C
DB2/SEL_C
DB1/SEL_B
11
12
13
14
15
16
DIO/DI
DIO/DI
DIO/DI
DIO/DI
DIO/DI
DIO/DI
Serial interface clock input (36MHz max)
Byte mode (WORD/BYTE = 1):
Connect to BGND or BVDD
Word mode (WORD/BYTE = 0):
Data bit 5 input/output
When DCEN = 1, daisy-chain data input for channel A
When DCEN = 0, connect to BGND
Byte mode (WORD/BYTE = 1):
Connect to BGND or BVDD
Word mode (WORD/BYTE = 0):
Data bit 4 input/output
When SEL_B = 1 and DCEN = 1, daisy-chain data input for
channel B
When DCEN = 0, connect to BGND
Byte mode (WORD/BYTE = 1):
Connect to BGND or BVDD
Word mode (WORD/BYTE = 0):
Data bit 3 input/output
When SEL_C = 1 and DCEN = 1, daisy-chain data input for
channel C
When DCEN = 0, connect to BGND
Byte mode (WORD/BYTE = 1):
Connect to BGND or BVDD
Word mode (WORD/BYTE = 0):
Data bit 2 input/output
Select SDO_C input.
When high, SDO_C is active. When low, SDO_C is disabled.
Byte mode (WORD/BYTE = 1):
Connect to BGND or BVDD
Word mode (WORD/BYTE = 0):
Data bit 1 input/output
Select SDO_B input.
When high, SDO_B is active. When low, SDO_B is disabled.
Byte mode (WORD/BYTE = 1):
Connect to BGND or BVDD
(1) AI = analog input; AIO = analog input/output; DI = digital input; DO = digital output; DIO = digital input/output; and P = power supply.
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TERMINAL FUNCTIONS (continued)
DESCRIPTION
NAME
PIN #
TYPE(1)
PARALLEL INTERFACE (PAR/SER = 0)
SERIAL INTERFACE (PAR/SER = 1)
Word mode (WORD/BYTE = 0):
Data bit 0 (LSB) input/output
Select SDO_A input.
When high, SDO_A is active. When low, SDO_A is disabled.
Should always be high.
DB0/SEL_A
17
DIO/DI
Byte mode (WORD/BYTE = 1):
Connect to BGND or BVDD
When CR bit C21 = 0 (BUSY/INT), converter busy status output. Transitions high when a conversion has been
started and remains high during the entire process. Transitions low when the conversion data of all six channels
are latched to the output register and remains low thereafter.
In sequential mode (SEQ = 1 in the CR), the BUSY output transitions high when a conversion has been started
and goes low for a single conversion clock cycle (tCCLK) whenever a channel pair conversion is completed.
When bit C21 = 1 (BUSY/INT in CR), interrupt output. This bit transitions high after a conversion has been
completed and remains high until the conversion result has been read.
BUSY/INT
18
DO
The polarity of BUSY/INT output can be changed using bit C20 (BUSY L/H) in the control register.
Chip select input.
Frame synchronization.
CS/FS
RD
19
20
DI/DI
DI
When low, the parallel interface is enabled. When
The falling edge of FS controls the frame transfer.
high, the interface is disabled.
Read data input.
When low, the parallel data output is enabled.
When high, the data output is disabled.
Connect to BGND
Hardware mode (HW/SW = 0): Conversion start of channel pair C.
The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_C[1:0]. CONVST_C
should remain high during the entire conversion cycle, otherwise both ADCs of channel C are put in partial
power-down mode (see the Reset and Power-down Modes sections).
CONVST_C
CONVST_B
CONVST_A
21
22
DI
DI
DI
Software mode (HW/SW = 1): Conversion start of channel pair C in sequential mode (CR bit C23 = 1) only;
connect to BGND or BVDD otherwise
Hardware mode (HW/SW = 0): Conversion start of channel pair B.
The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_B[1:0]. CONVST_B
should remain high during the entire conversion cycle; otherwise, both ADCs of channel B are put into partial
power-down mode (see the Reset and Power-down Modes sections).
Software mode (HW/SW = 1): Conversion start of channel pair B in sequential mode (CR bit C23 = 1) only;
connect to BGND or BVDD otherwise
Hardware mode (HW/SW = 0): Conversion start of channel pair A.
The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_A[1:0]. CONVST_A
should remain high during the entire conversion cycle; otherwise, both ADCs of channel A are put into partial
power-down mode (see the Reset and Power-down Modes sections).
23
24
Software mode (HW/SW = 1): Conversion start of all selected channels except in sequential mode
(CR bit C23 = 1): Conversion start of channel pair A only
Standby mode input. When low, the entire device is powered-down (including the internal clock and reference).
When high, the device operates in normal mode.
STBY
DI
P
25, 32,
37, 38,
43, 44,
49, 52,
53, 55,
57, 59
Analog ground, connect to analog ground plane
Pin 25 may have a dedicated ground if the difference between its potential and AGND is always kept within
±300mV.
AGND
26, 34,
35, 40,
41, 46,
47, 50,
60
Analog power supply (4.5V to 5.5V). Decouple each pin with a 100nF ceramic capacitor to AGND. Use an
additional 10µF capacitor to AGND close to the device but without compromising the placement of the smaller
capacitor. Pin 26 may have a dedicated power supply if the difference between its potential and AVDD is always
kept within ±300mV.
AVDD
P
Hardware mode (HW/SW = 0): Input voltage range select input.
When low, the analog input range is ±4VREF. When high, the analog input range is ±2VREF
.
RANGE/XCLK
RESET
27
28
DI/DIO
DI
Software mode (HW/SW = 1): External conversion clock input, if CR bit C11 (CLKSEL) is set high or internal
conversion clock output, if CR bit C10 (CLKOUT_EN) is set high. If not used, connect to BVDD or BGND.
Reset input, active high. Aborts any ongoing conversions. Resets the internal control register to 0x000003FF. The
RESET pulse should be at least 50ns long.
Output mode selection input.
When low, data are transferred in word mode using
DB[15:0]. When high, data are transferred in byte
mode using DB[15:8] with the byte order controlled
by HBEN pin while two accesses are required for a
complete 16-bit transfer.
WORD/BYTE
HVSS
29
30
DI
P
Connect to BGND
Negative supply voltage for the analog inputs (–16.5V to –5V).
Decouple with a 100nF ceramic capacitor to AGND placed next to the device and a 10µF capacitor to AGND close
to the device but without compromising the placement of the smaller capacitor.
12
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TERMINAL FUNCTIONS (continued)
DESCRIPTION
NAME
PIN #
TYPE(1)
PARALLEL INTERFACE (PAR/SER = 0)
SERIAL INTERFACE (PAR/SER = 1)
Positive supply voltage for the analog inputs (5V to 16.5V). Decouple with a 100nF ceramic capacitor to AGND
placed next to the device and a 10µF capacitor to AGND close to the device but without compromising the
placement of the smaller capacitor.
HVDD
31
P
Analog input of channel A0. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C26
(RANGE_A) in software mode.
CH_A0
CH_A1
CH_B0
CH_B1
CH_C0
CH_C1
33
36
39
42
45
48
AI
AI
AI
AI
AI
AI
Analog input of channel A1. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C26
(RANGE_A) in software mode.
Analog input of channel B0. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C27
(RANGE_B) in software mode.
Analog input of channel B1. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C27
(RANGE_B) in software mode.
Analog input of channel C0. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C28
(RANGE_C) in software mode.
Analog input of channel C1. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C28
(RANGE_C) in software mode.
Reference voltage input/output (0.5V to 3.025V).
The internal reference is enabled via REFEN/WR pin in hardware mode or CR bit C25 (REFEN) in software mode.
The output value is controlled by the internal DAC (CR bits C[9:0]). Connect a 470nF ceramic decoupling
capacitor between this pin and pin 52.
REFIO
51
AIO
Decoupling capacitor for reference of channels A.
Connect a 10µF ceramic decoupling capacitor between this pin and pin 53.
REFC_A
REFC_B
REFC_C
PAR/SER
54
56
58
61
AI
AI
AI
DI
Decoupling capacitor for reference of channels B.
Connect a 10µF ceramic decoupling capacitor between this pin and pin 55.
Decoupling capacitor for reference of channels C.
Connect a 10µF ceramic decoupling capacitor between this pin and pin 57.
Interface mode selection input.
When low, the parallel interface is selected. When high, the serial interface is enabled.
Mode selection input.
HW/SW
62
DI
When low, the hardware mode is selected and part works according to the settings of external pins. When high,
the software mode is selected in which the device is configured by writing into the control register.
Hardware mode (HW/SW = 0):
Hardware mode (HW/SW = 0):
Internal reference enable input.
Internal reference enable input.
When high, the internal reference is enabled (the
reference buffers are to be enabled). When low,
the internal reference is disabled and an external
reference is applied at REFIO.
When high, the internal reference is enabled (the reference
buffers are to be enabled). When low, the internal reference
is disabled and an external reference should be applied at
REFIO.
REFEN/WR
63
64
DI
Software mode (HW/SW = 1): Write input.
The parallel data input is enabled, when CS and
WR are low. The internal reference is enabled by
the CR bit C25 (REFEN).
Software mode (HW/SW = 1): Connect to BGND or BVDD.
The internal reference is enabled by CR bit C25 (REFEN).
Data bit 15 (MSB) input/output
Output is '0' for the ADS8557/8
DB15
DIO
Connect to BGND
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TIMING CHARACTERISTICS
t1
CONVST_x
tCONV
tD1
tACQ
BUSY
(C20 = C21 = 0)
t3
t2
FS
tSCLK
SCLK
1
32
tD3
tD4
tD2
tH2
ADS8556
SDO_x
CH_x0
MSB
CH_x1
D3
CH_x1
D2
tH1
CH_x1
D1
CH_x1
LSB
tS1
SDI or
DCIN_x
Don’t
Care
Don’t Care
D31
D3
D2
D1
D0
Figure 1. Serial Operation Timing Diagram (All Three SDOs Active)
Serial Interface Timing Requirements(1)
Over recommended operating free-air temperature range at –40°C to +125°C, AVDD = 5V, and BVDD = 2.7V to 5.5V, unless
otherwise noted.
ADS8556, ADS8557, ADS8558
TEST
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
tACQ
Acquisition time
280
ADS8556
ADS8557
ADS8558
1.26
1.19
1.09
tCONV
Conversion time
t1
t2
CONVST_x low time
20
0
BUSY low to FS low time
ADS8556
ADS8557
ADS8558
40
20
0
Bus access finished to next conversion
start time
t3
tD1
tD2
tD3
tD4
tH1
tH2
tS1
CONVST_x high to BUSY high delay
FS low to SDO_x active delay
5
20
12
15
10
5
SCLK rising edge to new data valid delay
FS high to SDO_x 3-state delay
Input data to SCLK falling edge hold time
Output data to SCLK rising edge hold time
Input data to SCLK falling edge setup time
Serial clock period
5
5
3
tSCLK
0.0278
10
(1) All input signals are specified with tR = tF = 1.5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2.
14
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t1
CONVST_A
CONVST_B
CONVST_C
tCONV
tACQ
tD1
BUSY
(C20 = C21 = 0)
t3
t2
CS
t6
t7
t4
t5
RD
tD5
tD5
tH3
CH
A0
CH
A1
CH
B0
CH
B1
CH
C0
CH
C1
DB[15:0]
Figure 2. Parallel Read Access Timing Diagram
Parallel Interface Timing Requirements (Read Access)(1)
Over recommended operating free-air temperature range at –40°C to +125°C, AVDD = 5V, and BVDD = 2.7V to 5.5V, unless
otherwise noted.
ADS8556, ADS8557, ADS8558
TEST
PARAMETER
tACQ
CONDITION
MIN
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Acquisition time
Conversion time
280
ADS8556
ADS8557
ADS8558
1.26
1.19
1.09
tCONV
t1
t2
CONVST_x low time
20
0
BUSY low to CS low time
ADS8556
ADS8557
ADS8558
40
20
0
Bus access finished to next conversion
start time(2)
t3
t4
CS low to RD low time
0
t5
RD high to CS high time
0
t6
RD pulse width
30
10
5
t7
Minimum time between two read accesses
CONVST_x high to BUSY high delay
RD falling edge to output data valid delay
Output data to RD rising edge hold time
tD1
tD5
tH3
20
20
5
(1) All input signals are specified with tR = tF = 1.5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2.
(2) Refer to CS signal or RD, whichever occurs first.
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CS
t10
t9
t8
t11
WR
tS2
tH4
C
[31:16]
C
[15:0]
Don’t C
Care [31:24]
C
[23:16]
C
[15:8]
C
[7:0]
DB[15:0]
Word Mode
(WORD/BYTE = 0)
Byte Mode
(WORD/BYTE = 1)
Figure 3. Parallel Write Access Timing Diagram
Parallel Interface Timing Requirements (Write Access)(1)
Over recommended operating free-air temperature range at –40°C to +125°C, AVDD = 5V, and BVDD = 2.7V to 5.5V, unless
otherwise noted.
ADS8556, ADS8557, ADS8558
PARAMETER
MIN
0
TYP
MAX
UNIT
ns
t8
CS low to WR low time
t9
WR low pulse width
15
10
0
ns
t10
t11
tS2
tH4
WR high pulse width
ns
WR high to CS high time
ns
Output data to WR rising edge setup time
Data output to WR rising edge hold time
5
ns
5
ns
(1) All input signals are specified with tR = tF = 1.5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2.
16
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TYPICAL CHARACTERISTICS
At +25°C, over entire supply voltage range, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted.
INL vs CODE
(ADS8556 ±10VIN Range)
INL vs CODE
(ADS8556 ±5VIN Range)
3.0
2.5
3.0
2.5
AVDD = BVDD = 5V
AVDD = BVDD = 5V
HVSS = -15V
HVDD = 15V
fDATA = Max
HVSS = -15V
HVDD = 15V
fDATA = Max
2.0
2.0
1.5
1.5
Internal Reference
Internal Reference
1.0
1.0
0.5
0.5
0
0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
0
0
0
8190 16380 24570 32760 40950 49140 57330 65520
0
0
0
8190 16380 24570 32760 40950 49140 57330 65520
Code
Code
Figure 4.
Figure 5.
DNL vs CODE
(ADS8556 ±10VIN Range)
DNL vs CODE
(ADS8556 ±5VIN Range)
1.5
1.0
0.5
0
1.5
1.0
0.5
0
AVDD = BVDD = 5V
HVSS = -15V
HVDD = 15V
AVDD = BVDD = 5V
HVSS = -15V
HVDD = 15V
fDATA = Max
fDATA = Max
Internal Reference
Internal Reference
-0.5
-1.0
-0.5
-1.0
8190 16380 24570 32760 40950 49140 57330 65520
8190 16380 24570 32760 40950 49140 57330 65520
Code
Code
Figure 6.
Figure 7.
INL vs CODE
(ADS8557 ±10VIN Range)
INL vs CODE
(ADS8557 ±5VIN Range)
1.0
0.8
1.0
0.8
AVDD = BVDD = 5V
HVSS = -15V
HVDD = 15V
AVDD = BVDD = 5V
HVSS = -15V
HVDD = 15V
0.6
0.6
fDATA = Max
fDATA = Max
0.4
0.4
Internal Reference
Internal Reference
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
2000 4000 6000 8000 10000 12000 14000 16000
2000 4000 6000 8000 10000 12000 14000 16000
Code
Code
Figure 8.
Figure 9.
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TYPICAL CHARACTERISTICS (continued)
At +25°C, over entire supply voltage range, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted.
DNL vs CODE
(ADS8557 ±10VIN Range)
DNL vs CODE
(ADS8557 ±5VIN Range)
1.0
0.8
1.0
0.8
AVDD = BVDD = 5V
AVDD = BVDD = 5V
HVSS = -15V
HVDD = 15V
fDATA = Max
HVSS = -15V
HVDD = 15V
fDATA = Max
0.6
0.6
0.4
0.4
Internal Reference
Internal Reference
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
2000 4000 6000 8000 10000 12000 14000 16000
0
2000 4000 6000 8000 10000 12000 14000 16000
Code
Code
Figure 10.
Figure 11.
INL vs CODE
(ADS8558)
DNL vs CODE
(ADS8558)
0.75
0.5
0.4
AVDD = BVDD = 5V
HVSS = -15V
HVDD = 15V
AVDD = BVDD = 5V
HVSS = -15V
HVDD = 15V
0.50
0.25
0
0.3
fDATA = Max
fDATA = Max
0.2
Internal Reference
Internal Reference
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.25
-0.50
-0.75
0
500 1000 1500 2000 2500 3000 3500 4000
0
500 1000 1500 2000 2500 3000 3500 4000
Code
Code
Figure 12.
Figure 13.
OFFSET ERROR vs TEMPERATURE
GAIN ERROR vs TEMPERATURE
4
3
0.75
0.50
0.25
0
2
1
0
-1
-2
-3
-4
-0.25
-0.50
-0.75
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Figure 14.
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
At +25°C, over entire supply voltage range, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted.
PSRR vs AVDD NOISE FREQUENCY
CONVERSION TIME vs TEMPERATURE
-30
-40
-50
-60
-70
-80
-90
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
CSUPPLY = 100nF on AVDD
ADS8556
ADS8557
ADS8558
0
20
40
60
80 100 120 140 160 180 200
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
AVDD Noise Frequency (kHz)
Figure 16.
Figure 17.
CODE HISTOGRAM
(8192 Hits)
SNR vs TEMPERATURE
94
92
90
88
86
84
82
80
78
76
74
72
70
5500
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
AVDD = BVDD = 5V
HVSS = -15V
HVDD = 15V
8192 Samples
Range = +4 ´ VREF
ADS8556
ADS8557
Internal Reference
T = +25°C
AVDD = BVDD = 5V
HVSS = -15V, HVDD = 15V
fSIGNAL = 10kHz, fDATA = Max
Range = ±4 ´ VREF
Internal Reference
ADS8558
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-3
-2
-1
0
1
2
Code
Figure 18.
Figure 19.
SINAD vs TEMPERATURE
THD vs TEMPERATURE
94
92
90
88
86
84
82
80
78
76
74
72
70
-86
-88
-90
-92
-94
-96
-98
AVDD = BVDD = 5V, HVSS = -15V, HVDD = 15V
fSIGNAL = 10kHz, fDATA = Max, Range = ±4 ´ VREF
ADS8556
Internal Reference
ADS8558
ADS8557
ADS8557
AVDD = BVDD = 5V
HVSS = -15V, HVDD = 15V
fSIGNAL = 10kHz, fDATA = Max
Range = ±4 ´ VREF
ADS8556
Internal Reference
ADS8558
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Figure 20.
Figure 21.
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TYPICAL CHARACTERISTICS (continued)
At +25°C, over entire supply voltage range, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted.
FREQUENCY SPECTRUM
(2048-Point FFT, fIN = 10kHz, ±10VIN Range)
SFDR vs TEMPERATURE
100
98
96
94
92
90
88
86
0
-20
AVDD = BVDD = 5V
HVSS = -15V
HVDD = 15V
-40
fSAMPLE = 500kSPS
fSIGNAL = 10kHz
-60
ADS8556
Range = ±4 ´ VREF
-80
Internal Reference
T = +25°C
ADS8557
-100
-120
-140
-160
-180
AVDD = BVDD = 5V
HVSS = -15V, HVDD = 15V
fSIGNAL = 10kHz, fDATA = Max
ADS8558
Range = ±4 ´ VREF
Internal Reference
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
0
25
50
75 100 125 150 175 200 225 250
Frequency (kHz)
Figure 22.
Figure 23.
FREQUENCY SPECTRUM
(2048-Point FFT, fIN = 10kHz, ±5VIN Range)
CHANNEL-TO-CHANNEL ISOLATION vs
INPUT NOISE FREQUENCY
0
120
115
110
105
100
95
AVDD = BVDD = 5V
HVSS = -15V, HVDD = 15V
fSAMPLE = 500kSPS
AVDD = BVDD = 5V
HVSS = -15V
HVDD = 15V
-20
-40
fDATA = Max
fSIGNAL = 10kHz
Range = ±2 ´ VREF
-60
Range = ±2 ´ VREF
Internal Reference
Internal Reference
T = +25°C
-80
-100
-120
-140
-160
-180
90
85
80
0
25
50
75 100 125 150 175 200 225 250
Frequency (kHz)
0
30
60
90 120 150 180 210 240 270 300
Noise Frequency (kHz)
Figure 24.
Figure 25.
INTERNAL REFERENCE VOLTAGE vs
ANALOG SUPPLY VOLTAGE (2.5V Mode)
INTERNAL REFERENCE VOLTAGE vs TEMPERATURE
(2.5V Mode)
2.504
2.503
2.502
2.501
2.500
2.499
2.498
2.497
2.496
2.504
2.503
2.502
2.501
2.500
2.499
2.498
2.497
2.496
VREF
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
AVDD (V)
Figure 26.
Figure 27.
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TYPICAL CHARACTERISTICS (continued)
At +25°C, over entire supply voltage range, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted.
INTERNAL REFERENCE VOLTAGE vs TEMPERATURE
(3.0V Mode)
ANALOG SUPPLY CURRENT vs TEMPERATURE
3.005
3.004
3.003
3.002
3.001
3.000
2.999
2.998
2.997
2.996
2.995
36
34
32
30
28
26
24
22
20
18
16
14
12
10
fDATA = Max
AVDD = 5V
Internal Reference
fDATA = 250kSPS (A-NAP)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Figure 28.
Figure 29.
ADS8556
ANALOG SUPPLY CURRENT vs DATA RATE
BUFFER I/O SUPPLY CURRENT vs TEMPERATURE
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
BVDD = 5V
Normal Operation
fDATA = Max
AVDD = 5V
Internal Reference
A-NAP Mode
fDATA = 250kSPS (A-NAP)
6
4
2
0
45 90 135 180 225 270 315 360 405 450 495 540 585 630
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Sample Rate (kSPS)
Figure 30.
Figure 31.
ADS8556
ADS8556
INPUT SUPPLY CURRENT vs TEMPERATURE
INPUT SUPPLY CURRENT vs INPUT SUPPLY VOLTAGE
4.5
4.00
3.75
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
IHVSS (fDATA = Max)
4.0
IHVSS (fDATA = Max)
3.5
IHVDD (fDATA = Max)
3.0
IHVDD (fDATA = Max)
HVSS = -15V
HVDD = 15V
Range = ±4 ´ VREF
2.5
2.0
1.5
Internal Reference
IHVSS (250kSPS A-NAP)
1.0
IHVSS (250kSPS A-NAP)
IHVDD (250kSPS A-NAP)
0.5
IHVDD (250kSPS A-NAP)
0
5
6
7
8
9
10
11 12
13
14
15
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
HVDD, |HVSS| (V)
Figure 32.
Figure 33.
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TYPICAL CHARACTERISTICS (continued)
At +25°C, over entire supply voltage range, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted.
ADS8556
INPUT SUPPLY CURRENT vs DATA RATE
3.6
IHVSS
3.3
3.0
IHVSS (A-NAP)
2.7
2.4
2.1
IHVDD (A-NAP)
1.8
1.5
IHVDD
1.2
0.9
HVSS = -15V
HVDD = 15V
0.6
0.3
0
Range = ±4 ´ VREF
450 540 630
0
90
180
270
360
Data Rate (kSPS)
Figure 34.
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GENERAL DESCRIPTION
period, there is no further input current flow and the
input impedance is greater than 1MΩ. To ensure a
defined start condition, the sampling capacitors of the
ADS8556/7/8 are pre-charged to a fixed internal
voltage, before switching into sampling mode.
The ADS8556/7/8 series include six 16-, 14-, and
12-bit
analog-to-digital
converters
(ADCs)
respectively that operate based on the successive
approximation register (SAR) principle. The
architecture is designed on the charge redistribution
principle,
which
inherently
includes
a
To maintain the linearity of the converter, the inputs
should always remain within the specified range of
HVSS – 0.2V to HVDD + 0.2V.
sample-and-hold function. The six analog inputs are
grouped into three channel pairs. These channel
pairs can be sampled and converted simultaneously,
preserving the relative phase information of the
signals of each pair. Separate conversion start
signals allow simultaneous sampling on each channel
pair: on four channels or on all six channels.
The minimum –3dB bandwidth of the driving
operational amplifier can be calculated using
Equation 1:
ln(2) ´ (n + 1)
f
=
-3dB
2p ´ tACQ
(1)
These devices accept single-ended, bipolar analog
input signals in the selectable ranges of ±4VREF or
±2VREF with an absolute value of up to ±12V; see the
Analog Inputs section.
where:
n = 16, 14, or 12; n is the resolution of the
ADS8556/7/8
The devices offer an internal 2.5V/3V reference
source followed by a 10-bit digital-to-analog converter
(DAC) that allows the reference voltage VREF to be
adjusted in 2.44mV or 2.93mV steps, respectively.
With a minimum acquisition time of tACQ = 280ns, the
required minimum bandwidth of the driving amplifier
is 6.7MHz for the ADS8556, 6MHz for the ADS8557,
or 5.2MHz for the ADS8558. The required bandwidth
can be lower if the application allows a longer
acquisition time. A gain error occurs if a given
application does not fulfill the bandwidth requirement
shown in Equation 1.
The ADS8556/7/8 also offer a selectable parallel or
serial interface that can be used in hardware or
software mode; see the Device Configuration section
for details.
A driving operational amplifier may not be required, if
the impedance of the signal source (RSOURCE) fulfills
the requirement of Equation 2:
ANALOG
This section addresses the analog input circuit, the
ADCs and control signals, and the reference design
of the device.
tACQ
RSOURCE
<
- (RSER + RSW)
CS ln(2) ´ (n + 1)
(2)
Analog Inputs
where:
n = 16, 14, or 12; n is the resolution of the ADC,
CS = 10pF is the sample capacitor value for VIN
±4 × VREF mode,
RSER = 200Ω is the input resistor value,
and RSW = 130Ω is the switch resistance value
The inputs and the converters are of single-ended,
bipolar type. The absolute voltage range can be
selected using the RANGE pin (in hardware mode) or
RANGE_x bits (in software mode) in the control
register (CR) to either ±4VREF or ±2VREF. With the
reference set to 2.5V (CR bit C18 = 0), the input
voltage range can be ±10V or ±5V. With the
reference source set to 3V (CR bit C18 = 1), an input
voltage range of ±12V or ±6V can be configured. The
logic state of the RANGE pin is latched with the
falling edge of BUSY (if CR bit C20 = 0).
=
With tACQ = 280ns, the maximum source impedance
should be less than 2.0kΩ for the ADS8556, 2.3kΩ
for the ADS8557, and 2.7kΩ for the ADS8558 in VIN
= ±4VREF mode or less than 0.8kΩ for the ADS8556,
1.0kΩ for the ADS8557, and 1.2kΩ for the ADS8558
in VIN = ±2VREF mode. The source impedance can be
higher if the application allows longer acquisition time.
The input current on the analog inputs depends on
the actual sample rate, input voltage, and signal
source impedance. Essentially, the current into the
analog inputs charges the internal capacitor array
only during the sampling period (tACQ). The source of
the analog input voltage must be able to charge the
input capacitance of 10pF in ±4VREF mode or 20pF in
±2VREF to a 12-, 14-, 16-bit accuracy level within the
acquisition time of 280ns at maximum data rate; see
the Equivalent Input Circuit. During the conversion
Analog-to-Digital Converter (ADC)
The devices include six ADCs that operate with either
an internal or an external conversion clock. The
conversion time can be as low as 1.09µs with internal
conversion clock (ADS8558). When an external clock
and reference are used, the minimum conversion
time is 925ns.
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Conversion Clock
remain high during the entire conversion cycle; this is
while the BUSY signal remains active. A falling edge
during an ongoing conversion puts the related ADC
pair into partial power-down mode (see the Reset and
Power-Down Modes section for more details).
The device uses either an internally-generated or an
external (XCLK) conversion clock signal (in software
mode only). In default mode, the device generates an
internal clock. When the CLKSEL bit is set high (bit
C11 in the CR), an external conversion clock of up to
20MHz (max) can be applied on pin 27. In both
cases, 18.5 clock cycles are required for a complete
conversion including the pre-charging of the sample
capacitors. The external clock can remain low
between conversions.
A conversion start must not be issued during an
ongoing conversion on the same channel pair. It is
allowed to initiate conversions on the other input
pairs, however (see the Sequential Mode section for
more details).
If a parallel interface is used, the behavior of the
output port depends on which CONVST_x signals
have been issued. Figure 35 shows examples of
different scenarios.
The conversion clock duty cycle should be 50%.
However, the ADS8556/7/8 function properly with a
duty cycle between 45% and 55%.
CONVST_x
The analog inputs of each channel pair (CH_x0/1) are
held with the rising edge of the corresponding
CONVST_x signal. Only in software mode (except
sequential mode), CONVST_A is used for all six
ADCs. The conversion automatically starts with the
next edge of the conversion clock. CONVST_x should
BUSY
(C20 = C21 = 0)
CS
CONVST_A
CONVST_C
CONVST_B
RD
CH
A0
CH
A1
CH
C0
CH
C1
CH
A0
CH
A1
CH
C0
DB[15:0]
CONVST_B
CONVST_A
CONVST_B
RD
CH
B0
CH
B1
CH
B0
CH
B1
CH
B0
CH
B1
CH
B0
DB[15:0]
NOTE: Boxed areas indicate the minimum required frame to acquire all data.
Figure 35. Data Output versus CONVST_x
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BUSY/INT
Table 1 lists some examples of internal reference
DAC settings with a reference range set to 2.5V.
However, to ensure proper performance, the DAC
output voltage should not be programmed below
0.5V.
The BUSY signal indicates if a conversion is in
progress. It goes high with a rising edge of any
CONVST_x signal and goes low when the output
data of the last channel pair are available in the
respective output register. The readout of the data
can be initiated immediately after the falling edge of
BUSY. A falling edge of a CONVST_x input during an
ongoing conversion (when BUSY is high) powers
down the corresponding ADC pair.
The buffered output of the DAC should be decoupled
with
a
100nF capacitor (minimum); for best
performance, a 470nF capacitor is recommended. If
the internal reference is placed into power-down
(default), an external reference voltage can drive the
REFIO pin.
In sequential mode, the BUSY signal goes low only
for one clock cycle. See the Sequential Mode section
for more details.
The voltage at the REFIO pin is buffered with three
internal amplifiers, one for each ADC pair. The output
of each buffer needs to be decoupled with a 10µF
capacitor between pin pairs 53 and 54, 55 and 56,
and 57 and 58. The 10µF capacitors are available as
ceramic 0805-SMD components and in X5R quality.
The polarity of the BUSY/INT signal can be changed
using CR bit C20.
Reference
The internal reference buffers can be powered down
to decrease the power dissipation of the device. In
this case, external reference drivers can be
connected to REFC_A, REFC_B, and REFC_C pins.
With 10µF decoupling capacitors, the minimum
required bandwidth can be calculated using
Equation 4:
The ADS8556/7/8 provides an internal, low-drift 2.5V
reference source. To increase the input voltage
range, the reference voltage can be switched to 3V
mode using the VREF bit (bit C18 in the CR). The
reference feeds a 10-bit string-DAC controlled by bits
C[9:0] in the control register. The buffered DAC
output is connected to the REFIO pin. In this way, the
voltage at this pin is programmable in 2.44mV
(2.92mV in 3V mode) steps and adjustable to the
application needs without additional external
components. The actual output voltage can be
calculated using Equation 3:
ln(2)
f
=
-3dB
2p ´ tCONV
(4)
With the minimum tCONV of 1.09µs, the external
reference buffers require a minimum bandwidth of
1.02kHz.
Range ´ (Code + 1)
VREF
=
1024
(3)
Table 1. DAC Setting Examples (2.5V Operation)
where:
DECIMAL
CODE
BINARY
CODE
HEXADECIMAL
CODE
VREF OUT (V)
Range = the chosen maximum reference voltage
output range (2.5V or 3V),
Code = the decimal value of the DAC register
content
0.500
1.25
204
511
00 1100 1100
01 1111 1111
11 1111 1111
CC
1FF
3FF
2.500
1023
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DIGITAL
significant bit (MSB), the output data are changed at
the rising edge of SCLK, so that the host processor
can read it at the following falling edge. Output data
of the ADS8557 and ADS8558 maintain the 16-bit
format with leading zeros.
This section describes the digital control and the
timing of the device in detail.
Device Configuration
Serial data input SDI are latched at the falling edge of
SCLK.
Depending on the desired mode of operation, the
ADS8556/7/8 can be configured using the external
pins and/or the control register (CR), as shown in
Table 2.
The serial interface can be used with one, two, or
three output ports. These ports are enabled with pins
SEL_A, SEL_B, and SEL_C. If all three serial data
output ports (SDO_A, SDO_B, and SDO_C) are
selected, the data can be read with either two 16-bit
data transfers or with one 32-bit data transfer. The
data of channels CH_x0 are available first, followed
by data from channels CH_x1. The maximum
achievable data throughput rate is 450kSPS for the
ADS8556, 470kSPS for the ADS8557, and 500kSPS
for the ADS8558 in this case.
Parallel Interface
To use the device with the parallel interface, the
PAR/SER pin should be held low. The maximum
achievable data throughput rate using the internal
clock is 630kSPS for the ADS8556, 670kSPS for the
ADS8557, and 730kSPS for the ADS8558 in this
case.
Access to the ADS8556/7/8 is controlled as illustrated
in Figure 2 and Figure 3.
If the application allows a data transfer using two
ports only, SDO_A and SDO_B outputs are used.
The device outputs data from channel CH_A0
followed by CH_A1 and CH_C0 on SDO_A, while
data from channel CH_B0 followed by CH_B1 and
CH_C1 occurs on SDO_B. In this case, a data
transfer of three consecutive 16-bit words or one
continuous 48-bit word is supported. The maximum
achievable data throughput rate is 375kSPS for the
ADS8556, 390kSPS for the ADS8557, and 400kSPS
for the ADS8558.
The device can either operate with
a
16-bit
(WORD/BYTE pin set low) or an 8-bit (WORD/BYTE
pin set high) parallel interface. If 8-bit operation is
used, the HBEN pin selects if the low-byte (DB7 low)
or the high-byte (DB7 high) is available on the data
output DB[15:8] first.
Serial Interface
The serial interface mode is selected by setting the
PAR/SER pin high. In this case, each data transfer
starts with the falling edge of the frame
synchronization input (FS). The conversion results
are presented on the serial data output pins SDO_A,
SDO_B, and SDO_C depending on the selections
made using the SEL_x pins. Starting with the most
The output SDO_A is selected if only one serial data
port is used in the application. The data are available
in the following order: CH_A0, CH_A1, CH_B0,
CH_B1, CH_C0, and, finally CH_C1. Data can be
read using six 16-bit transfers, three 32-bit transfers,
or a single 96-bit transfer. The maximum achievable
data throughput rate is 250kSPS for the ADS8556/7
and 260kSPS for the ADS8558 in this case.
Figure 1 (the serial operation timing diagram) and
Figure 36 show all possible scenarios in more detail.
Table 2. ADS8556/7/8 Configuration Settings
HARDWARE MODE (HW/SW = 0)
SOFTWARE MODE (HW/SW = 1)
CONVERSION START CONTROLLED BY SEPARATE CONVERSION START CONTROLLED BY CONVST_A
INTERFACE MODE
CONVST_x PINS
PIN ONLY, EXCEPT IN SEQUENTIAL MODE
Configuration using control register bits C[31:0] only;
status of pins 27 (only if used as RANGE input) and 63 is
disregarded
Parallel
(PAR/SER = 0)
Configuration using pins, optionally, control bits C[22:18],
C[15:13], and C[9:0]
Configuration using control register bits C[31:0] only;
status of pins 1, 27 (only if used as RANGE input), and
63 is disregarded; each access requires a control register
update via SDI (see the Serial Interface section for
details)
Serial
(PAR/SER = 1)
Configuration using pins, optionally, control bits C[22:18],
C[15:13], and C[9:0]; bits C[31:24] are disregarded
26
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CONVST_A
CONVST_B
CONVST_C
BUSY
(C20 = C21 = 0)
48 SCLKs
SEL_A = SEL_B = 1, SEL_C = 0
FS
SDO_A
CHA0
CHB0
CHA1
CHB1
CHC0
CHC1
SDO_B
SEL_A = 1, SEL_B = SEL_C = 0
FS
96 SCLKs
SDO_A
CHA0
CHA1
CHB0
CHB1
CHC0
CHC1
Figure 36. Serial Interface: Data Output with One or Two Active SDOs
word and byte modes. In word mode, the first write
Hardware Mode
access updates only the upper eight bits and stores
the lower eight bits (C[23:16]) for an update that
takes place with the second write access along with
C[15:0].
With the HW/SW input (pin 62) set low, the device
functions are controlled via the pins and, optionally,
control register bits C[22:18], C[15:13], and C[9:0].
If the serial interface is used, input data containing
control register contents are required with each read
access to the device in this mode (combined
read/write access). For initialization purposes, all 32
bits of the register should be set (bit C16 must be set
to '1' during that access to allow the update of the
entire register content). To minimize switching noise
on the interface, an update of the first eight bits
(C[31:24]) with the remaining bits held low can be
performed thereafter.
It is possible to generally use the part in hardware
mode but to switch it into software mode to initialize
or adjust the control register settings (for example,
the internal reference DAC) and back to hardware
mode thereafter.
Software Mode
When the HW/SW input is set high, the device
operates in software mode with functionality set only
by the control register bits (corresponding pin settings
are ignored).
Figure 37 illustrates the different control register
update options.
If parallel interface is used, an update of all control
register settings is performed by issuing two 16-bit
write accesses on pins DB[15:0] in word mode or four
8-bit accesses on pins DB[15:8] in byte mode (to
avoid losing data, the entire sequence must be
finished before starting a new conversion). CS should
be held low during the two or four write accesses to
completely update the configuration register. It is also
possible to update only the upper eight bits (C[31:24])
using a single write access and pins DB[15:8] in both
Control Register (CR);
Default Value = 0x000003FF
The control register settings can only be changed in
software mode and are not affected when switching
to hardware mode thereafter. The register values are
independent from input pin settings. Changes are
active with the rising edge of WR in parallel interface
mode or with the 32nd falling SCLK edge of the
access in which the register content has been
updated in serial mode. Optionally, the register can
also be partially updated by writing only the upper
eight bits (C[31:24]). The CR content is defined in
Table 3.
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RESET
(or Power-Up)
BUSY
(C20 = C21 = 0)
PAR/SER = 1
FS
Continuous Update
Continuous Update
C
[31:24]
C
[31:24]
C[31:0]
Initialization Data
SDI
PAR/SER = 0; WORD/BYTE = 0
CS
WR
Initialization Data
Update
C
[31:16]
C
[15:0]
C
[31:24]
C
[15:0]
DB[15:0]
PAR/SER = 0; WORD/BYTE = 1
WR
Initialization Data
Update
C
[31:24]
C
[23:16]
C
[15:8]
C
[7:0]
C
[31:24]
C
[23:16]
DB[15:8]
Figure 37. Control Register Update Options
28
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Table 3. Control Register (CR)
ACTIVE IN
BIT
NAME
DESCRIPTION
HARDWARE MODE
0 = Channel pair C disabled for next conversion (default)
1 = Channel pair C enabled
C31
CH_C
No
0 = Channel pair B disabled for next conversion (default)
1 = Channel pair B enabled
C30
C29
C28
C27
C26
C25
C24
C23
C22
C21
CH_B
CH_A
No
No
No
No
No
No
No
No
Yes
Yes
0 = Channel pair A disabled for next conversion (default)
1 = Channel pair A enabled
0 = Input voltage range selection for channel pair C: 4VREF (default)
1 = Input voltage range selection for channel pair C: 2VREF
RANGE_C
RANGE_B
RANGE_A
REFEN
0 = Input voltage range selection for channel pair B: 4VREF (default)
1 = Input voltage range selection for channel pair B: 2VREF
0 = Input voltage range selection for channel pair A: 4VREF (default)
1 = Input voltage range selection for channel pair A: 2VREF
0 = Internal reference source disabled (default)
1 = Internal reference source enabled
0 = Internal reference buffers enabled (default)
1 = Internal reference buffers disabled
REFBUF
SEQ
0 = Sequential convert start mode disabled (default)
1 = Sequential convert start mode enabled (bit 11 must be '1' in this case)
0 = Normal operation (default)
1 = Auto-NAP feature enabled
A-NAP
0 = BUSY/INT pin in normal mode (BUSY) (default)
1 = BUSY/INT pin in interrupt mode (INT)
BUSY/INT
0 = BUSY active high while INT active low (default)
1 = BUSY active low while INT active high
C20
C19
C18
BUSY L/H
Don’t use
VREF
Yes
—
This bit is always set to '0'
0 = Internal reference voltage: 2.5V (default)
1 = Internal reference voltage: 3V
Yes
0 = Normal operation (conversion results available on SDO_x) (default)
1 = Control register contents output on SDO_x with next access
C17
C16
C15
C14
READ_EN
C23:0_EN
PD_C
Yes
Yes
Yes
Yes
0 = Control register bits C[31:24] update only (serial mode only) (default)
1 = Entire control register update enabled (serial mode only)
0 = Normal operation (default)
1 = Power-down for channel pair C enabled (bit 31 must be '0' in this case)
0 = Normal operation (default)
1 = Power-down for channel pair B enabled (bit 30 must be '0' in this case)
PD_B
0 = Normal operation (default)
1 = Power-down for channel pair A enabled (bit 29 must be '0' in this case)
C13
C12
C11
PD_A
Yes
—
Don't use
CLKSEL
This bit is always '0'
0 = Normal operation with internal conversion clock (mandatory in hardware mode) (default)
1 = External conversion clock (applied through pin 27) used
No
0 = Normal operation (default)
1 = Internal conversion clock available at pin 27
C10
CLKOUT_EN
No
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
REFDAC[9]
REFDAC[8]
REFDAC[7]
REFDAC[6]
REFDAC[5]
REFDAC[4]
REFDAC[3]
REFDAC[2]
REFDAC[1]
REFDAC[0]
Bit 9 (MSB) of reference DAC value; default = 1
Bit 8 of reference DAC value; default = 1
Bit 7 of reference DAC value; default = 1
Bit 6 of reference DAC value; default = 1
Bit 5 of reference DAC value; default = 1
Bit 4 of reference DAC value; default = 1
Bit 3 of reference DAC value; default = 1
Bit 2 of reference DAC value; default = 1
Bit 1 of reference DAC value; default = 1
Bit 0 (LSB) of reference DAC value; default = 1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
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Daisy-Chain Mode (in Serial Mode Only)
XCLK
The serial interface of the ADS8556/7/8 supports a
daisy-chain feature that allows cascading of multiple
CONVST_A
devices to minimize the board space requirements
and simplify routing of the data and control lines. In
this case, pins DB5/DCIN_A, DB4/DCIN_B, and
CONVST_B
DB3/DCIN_C are used as serial data inputs for
channels A, B, and C, respectively. Figure 39 shows
CONVST_C
an example of a daisy-chain connection of three
tCCLK
devices sharing a common CONVST line to allow
simultaneous sampling of 18 analog channels along
BUSY
(C20 = 0)
with the corresponding timing diagram. To activate
the daisy-chain mode, the DCEN pin must be pulled
CS
high. As a result of the time specifications tS1, tH1, and
tD3, the maximum SCLK frequency that may be used
in daisy-chain mode is 27.78MHz (assuming 50%
duty cycle).
RD
CH
A0
CH
A1
CH
B0
CH
B1
CH
C0
CH
C1
D[15:0]
Sequential Mode (in Software Mode with External
Conversion clock Only)
(1) EOC = end of conversion (internal signal).
Figure 38. Sequential Mode Timing
The three channel pairs of the ADS8556/7/8 can be
run in sequential mode, with the corresponding
CONVST_x signals interleaved, when an external
clock is used. To activate the device in sequential
mode, CR bits C11 (CLKSEL) and C23 (SEQ) must
be asserted. In this case, the BUSY output indicates
a finished conversion by going low (when C20 = 0) or
high (when C20 = 1) for only a single conversion
clock cycle in case of ongoing conversions of any
other channel pairs. Figure 38 shows the behavior of
the BUSY output in this mode. Each conversion start
should be initiated during the high phase of the
external clock, as shown in Figure 38. The minimum
time required between two CONVST_x pulses in the
time required to read the conversion result of a
channel (pair).
Output Data Format
The data output format of the ADS8556/7/8 is binary
twos complement, as shown in Table 4.
For the ADS8557, which delivers 14-bit conversion
results, the leading two bits of the 16-bit frame are '0'
in the serial interface mode. In parallel interface
mode, the output pins DB[15:14] are held low.
Respectively, as the ADS8558 outputs 12 bits of
data, the first four bits of a serial 16-bit frame are
zeros, in parallel interface mode the output pins
DB[15:12] are held low.
Table 4. Output Data Format
BINARY CODE (HEXADECIMAL CODE)
ADS8557
DESCRIPTION
INPUT VOLTAGE VALUE
ADS8556
ADS8558
0111 1111 1111 1111
(7FFF)
0001 1111 1111 1111
(1FFF)
0000 0111 1111 1111
(7FF)
Positive full-scale
+4VREF or +2VREF
0000 0000 0000 0000
(0000)
0000 0000 0000 0000
(0000)
0000 0000 0000 0000
(0000)
Midscale + 0.5LSB
Midscale – 0.5LSB
Negative full-scale
VREF/(2 × resolution)
–VREF/(2 × resolution)
–4VREF or –2VREF
1111 1111 1111 1111
(FFFF)
0011 1111 1111 1111
(3FFF)
0000 1111 1111 1111
(FFF)
1000 0000 0000 0000
(8000)
0010 0000 0000 0000
(2000)
0000 1000 0000 0000
(800)
30
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CONVST
FS
SCLK
ADS8556
ADS8556
ADS8556
#1
#2
#3
CONVST_A
CONVST_A
CONVST_A
FS
SCLK
FS
SCLK
FS
SCLK
SDO_A
SDO_B
SDO_C
DCIN_A
DCIN_B
DCIN_C
SDO_A
SDO_B
SDO_C
DCIN_A
DCIN_B
DCIN_C
SDO_A
SDO_B
SDO_C
To
Processing
Unit
DCEN = 1
CONVST
BUSY
(C20 = C21 = 0)
FS
16-Bit Data CHx0
ADS8556 #3
16-Bit Data CHx1
ADS8556 #3
16-Bit Data CHx0
ADS8556 #2
16-Bit Data CHx1
ADS8556 #2
16-Bit Data CHx0
ADS8556 #1
16-Bit Data CHx1
ADS8556 #1
SDO_x #3
Don’t Care
Figure 39. Example of Daisy-Chaining Three ADS8556s
Reset and Power-Down Modes
AVDD (V)
5.500
The device supports two reset mechanisms:
a
power-on reset (POR) and a pin-controlled reset
(RESET) that can be issued using pin 28. Both the
POR and RESET act as a master reset that causes
any ongoing conversion to be interrupted, the control
register content to be set to the default value, and all
channels to be switched into sample mode.
Specified Supply
Voltage Range
5.000
4.500
4.000
3.000
When the device is powered up, the POR sets the
device in default mode when AVDD reaches 1.5V.
When the device is powered down, the POR circuit
requires AVDD to remain below 125mV at least
350ms to ensure proper discharging of internal
capacitors and to ensure correct behavior of the
device when powered up again. If the AVDD drops
below 400mV but remains above 125mV (see the
undefined zone in Figure 40), the internal POR
capacitor does not discharge fully and the device
requires a pin-controlled reset to perform correctly
after the recovery of AVDD.
2.000
1.500
1.000
POR
Trigger Level
0.400
0.125
Undefined Zone
0
0.350
t (s)
Figure 40. POR: Relevant Voltage Levels
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The entire device, except the digital interface, can be
powered down by pulling the STBY pin low (pin 24).
As the digital interface section remains active, data
can be retrieved while in stand-by mode. To power
the part on again, the STBY pin must be brought
high. The device is ready to start a new conversion
after 10ms required to activate and settle the internal
circuitry. This user-controlled approach can be used
in applications that require lower data throughput
rates and lowest power dissipation. The content of
CR is not changed during standby mode. It is not
results). The next rising edge of the CONVST_x
signal should be issued at least six conversion cycle
periods after the reset pulse and starts a new
conversion, as shown in Figure 41. The internal
reference remains active during the partial
power-down mode.
The auto-NAP power-down mode is enabled by
asserting the A-NAP bit (C22) in the control register.
If the auto-NAP mode is enabled, the ADS8556/7/8
automatically reduce the current requirement to 6mA
after finishing
a conversion; thus, the end of
required to perform
a pin-controlled reset after
conversion actually activates the power-down mode.
Triggering a new conversion by applying a positive
CONVST_x edge puts the device back into normal
operation, starts the acquisition of the analog input,
returning to normal operation.
While the standby mode impacts the entire device,
each device channel pair can also be individually
switched off by setting control register bits C[15:13]
(PD_x). When reactivated, the relevant channel pair
requires 10ms to fully settle before starting a new
conversion. The internal reference remains active,
except all channels are powered down at the same
time.
and automatically starts
a new conversion six
conversion clock cycles later. Therefore, a complete
conversion cycle takes 24.5 conversion clock cycles;
thus, the maximum throughput rate in auto-NAP
power-down mode is reduced to a maximum of
380kSPS for the ADS8556, 395kSPS for the
ADS8557, and 420kSPS for the ADS8558 in serial
mode. In parallel mode, the maximum data rates are
500kSPS for the ADS8556, 530kSPS for the
ADS8557, and 580kSPS for the ADS8558. The
internal reference remains active during the auto-NAP
In partial power-down mode, each of the three
channel pairs of the ADS8556/7/8 can be individually
put into a power-saving condition that reduces the
current requirement to 2mA per channel pair by
bringing the corresponding CONVST_x signal low
during an ongoing conversion when BUSY is high.
The relevant channel pair is activated again by
issuing a RESET pulse (to avoid loss of data from the
active channels, this RESET pulse should be
generated after retrieving the latest conversion
mode. Table
5
compares the analog current
requirements of the devices in the different modes.
BUSY
CONVST_A/C
ADC CH_Ax/Cx
CONVST_B
ACQ
CONV
ACQ
CONV
ACQ
6 ´ tCCLK Min
RESET
ADC CH_Bx
ACQ CONV Power-Down
ACQ
CONV
ACQ
Figure 41. Partial Power-Down
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Table 5. Maximum Analog Current (IAVDD) Demand of the ADS8556/7/8
NORMAL
OPERATION
POWER-UP
TO NORMAL
POWER-UP
TO NEXT
ANALOG
TO
OPERATIONAL
MODE
CURRENT
ACTIVATED
BY
POWER-
DOWN DELAY RESUMED BY
OPERATION CONVERSION
(IAVDD
)
ENABLED BY
DELAY
START TIME DISABLED BY
12mA/channel
Normal operation pair (maximum
data rate)
Power on
CONVST_x
—
—
—
—
Power off
Power off
Partial
CONVST_x
low while
BUSY is high
2mA (channel
power-down of
pair x)
At falling edge
of BUSY
Power on
RESET pulse
CONVST_x
Immediate
Immediate
6 × tCCLK
channel pair x
A-NAP = 1 (CR
bit)
Each end of
conversion
At falling edge
of BUSY
A-NAP = 0 (CR
bit)
Auto-NAP
6mA
6 × tCCLK
Immediate after
completing
register update
Power-down of
channel pair x
16µA (channel
PD_x = 1 (CR
bit)
PD_x = 0 (CR
bit)
HW/SW = 1
Power on
Immediate
10ms
10ms
HW/SW = 0
pair x)
Stand-by
50µA
STBY = 0
Immediate
STBY = 1
Immediate
Power off
The AVDD supply provides power to the internal
circuitry of the ADC. It can be set in the range of 4.5V
to 5.5V. Because the supply current of the device is
typically 30mA, it is not possible to use a passive
filter between the digital board supply of the
application and the AVDD pin. A linear regulator is
recommended to generate the analog supply voltage.
Each AVDD pin should be decoupled to AGND with a
100nF capacitor. In addition, a single 10µF capacitor
should be placed close to the device but without
compromising the placement of the smaller capacitor.
Optionally, each supply pin can be decoupled using a
1µF ceramic capacitor without the requirement for a
10µF capacitor.
GROUNDING
All GND pins should be connected to a clean ground
reference. This connection should be kept as short as
possible to minimize the inductance of this path. It is
recommended to use vias connecting the pads
directly to the ground plane. In designs without
ground planes, the ground trace should be kept as
wide as possible. Avoid connections that are too
close to the grounding point of a microcontroller or
digital signal processor.
Depending on the circuit density on the board,
placement of the analog and digital components, and
the related current loops, a single solid ground plane
for the entire printed circuit board (PCB) or a
dedicated analog ground area may be used. In case
The BVDD supply is only used to drive the digital I/O
buffers and can be set in the range of 2.7V to 5.5V.
This range allows the device to interface with most
state-of-the-art processors and controllers. To limit
the noise energy from the external digital circuitry to
the device, BVDD should be filtered. A 10Ω resistor
can be placed between the external digital circuitry
and the device, because the current drawn is typically
below 2mA (depending on the external loads). A
bypass ceramic capacitor of 1µF (or alternatively, a
pair of 100nF and 10µF capacitors) should be placed
between the BVDD pin and pin 8.
of a separated analog ground area, ensure
a
low-impedance connection between the analog and
digital ground of the ADC by placing a bridge
underneath (or next) to the ADC. Otherwise, even
short undershoots on the digital interface lower than
–300mV lead to the conduction of ESD diodes
causing current flow through the substrate and
degrading the analog performance.
During PCB layout, care should be taken to avoid any
return currents crossing sensitive analog areas or
signals.
The high-voltage supplies (HVSS and HVDD) are
connected to the analog inputs. Noise and glitches on
these supplies directly couple into the input signals.
Place a 100nF ceramic decoupling capacitor, located
as close to the device as possible, between each of
pins 30, 31, and AGND. An additional 10µF capacitor
is used that should be placed close to the device but
without compromising the placement of the smaller
capacitor.
SUPPLY
The ADS8556/7/8 require four separate supplies: the
analog supply for the ADC (AVDD), the buffer I/O
supply for the digital interface (BVDD), and the
high-voltage supplies driving the analog input circuitry
(HVDD and HVSS). Generally, there are no specific
requirements with regard to the power sequencing of
the device. However, when HVDD is supplied before
AVDD, the internal ESD structure conducts,
increasing IHVDD beyond the specified value.
Figure 42 shows a layout recommendation for the
ADS8556/7/8 along with the proper decoupling and
reference capacitor placement and connections.
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ADS8556/7/8
Top View
To AVDD
To AVDD
To DUT
AVDD Source
10
mF
0.1mF
10mF
10mF
10mF
0.47mF 0.1mF
64 63 62 61
58
56
54
51
0.1
mF
1
2
48
AVDD
AVDD
45
3
To AVDD
0.1
mF
4
5
AGND
AGND
42
6
0.1
mF
7
BGND
BVDD
10
11
12
13
14
15
16
AVDD
AVDD
39
1
mF
To
BVDD
To AVDD
0.1
mF
AGND
AGND
36
0.1
mF
To AVDD
AVDD
AVDD
33
0.1
mF
17 18 19 20 21 22 23 24
27 28 29
0.1mF
0.1mF
0.1mF
10mF
10mF
To
AVDD
To
HVSS/HVDD
LEGEND
TOP layer; copper pour and traces
Lower layer; AGND area
Lower layer; BGND area
Via
(1) All 0.1µF, 0.47µF, and 1µF capacitors should be placed as close to the ADS8556/7/8 as possible.
(2) All 10µF capacitors should be close to the device but without compromising the placement of the smaller capacitors.
Figure 42. Layout Recommendation
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APPLICATION INFORMATION
The actual values of the resistors and capacitors
depend on the bandwidth and performance
requirements of the application. For highest data rate,
it is recommended to use a filter capacitor value of
1nF and a series resistor of 22Ω to fulfill the settling
requirements to an accuracy level of 16 bits within the
acquisition time of 280ns.
The minimum configuration of the ADS8556/7/8 in
parallel mode is shown in Figure 43. In this case, the
BUSY signal is not used while the SW generates the
required signals in a timely manner. TI’s OPA2211 is
used as an input driver, supporting bandwidth that
allows running the device at the maximum data rate.
R1
R2
AVDD
AGND
ADS8556
RF
CH_A0
CH_A1
Input #1
CF
CF
BVDD
OPA2211
AGND
STBY
RF
Input #2
RANGE
REFEN/WR
AGND
R1
R2
REFC_A
REFC_B
10mF
AGND
R1
AGND
CONVST_A
CONVST_B
CONVST_C
RESET
10mF
R2
AVDD
AGND
Host
Controller
CS
RF
RD
CH_B0
CH_B1
Input #3
Input #4
CF
DB[15:0]
OPA2211
AGND
CF
RF
AGND
R1
R2
REFIO
0.47mF
10mF
AGND
R1
AGND
R2
REFC_C
AVDD
ADS8556
AGND
AVDD
AVDD
AVDD
AVDD
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
RF
HW/SW
PAR/SER
BVDD
CH_C0
CH_C1
Input #5
Input #6
CF
CF
WORD/BYTE
BVDD
BGND
OPA2211
AGND
BGND
1mF
RF
BGND
AGND
R1
R2
HVSS
HVSS
AGND
AGND
AGND
0.1mF
0.1mF
10mF
0.1mF
0.1mF
0.1mF
0.1mF
0.1mF
0.1mF
0.1mF
10mF
0.1mF
10mF
AGND
AGND
HVDD
HVSS
AVDD
Figure 43. Minimum Configuration in Parallel Interface Mode
Copyright © 2006–2009, Texas Instruments Incorporated
35
Product Folder Link(s): ADS8556 ADS8557 ADS8558
PACKAGE OPTION ADDENDUM
www.ti.com
31-Aug-2009
PACKAGING INFORMATION
Orderable Device
ADS8556IPM
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
LQFP
PM
64
64
64
64
64
64
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
ADS8556IPMR
ADS8557IPM
LQFP
LQFP
LQFP
LQFP
LQFP
PM
PM
PM
PM
PM
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
ADS8557IPMR
ADS8558IPM
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
ADS8558IPMR
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Sep-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS8556IPMR
ADS8557IPMR
ADS8558IPMR
LQFP
LQFP
LQFP
PM
PM
PM
64
64
64
1000
1000
1000
330.0
330.0
330.0
24.4
24.4
24.4
12.3
12.3
12.3
12.3
12.3
12.3
2.5
2.5
2.5
16.0
16.0
16.0
24.0
24.0
24.0
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Sep-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS8556IPMR
ADS8557IPMR
ADS8558IPMR
LQFP
LQFP
LQFP
PM
PM
PM
64
64
64
1000
1000
1000
346.0
346.0
346.0
346.0
346.0
346.0
41.0
41.0
41.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
0,25
12,20
SQ
0,05 MIN
0°–7°
11,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040152/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. May also be thermally enhanced plastic with leads connected to the die pads.
1
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