ADS8584SIPMR [TI]
在单电源上具有双极性输入的 16 位、高速 4 通道同步采样 ADC | PM | 64 | -40 to 125;型号: | ADS8584SIPMR |
厂家: | TEXAS INSTRUMENTS |
描述: | 在单电源上具有双极性输入的 16 位、高速 4 通道同步采样 ADC | PM | 64 | -40 to 125 转换器 |
文件: | 总63页 (文件大小:1842K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ADS8584S
ZHCSG85A –APRIL 2017–REVISED APRIL 2017
ADS8584S在单电源上具有双极性输入的 ADS8588S 16 位、高速 4 通
道、同步采样 ADC
1 特性
3 说明
1
•
具有集成式模拟前端的 16 位 ADC
同步采样:4 通道
ADS8584S 器件是一款基于集成式数据采集 (DAQ) 系
统的 4 通道、16 位、逐次逼近型 (SAR) 同步采样模数
转换器 (ADC),每通道的最大采样频率为 330kSPS。
该器件 每个 通道都有一个完整的模拟前端,其中包含
输入阻抗高达 1MΩ 的可编程增益放大器 (PGA)、输入
钳位、低通滤波器和 ADC 输入驱动器。此外,该器件
还 具备 带缓冲器的低漂移、高精度基准电压,以用于
驱动 ADC。凭借灵活的数字接口,该器件支持串行、
并行和并行字节通信,适用于各种主机控制器。的前两
个句子
•
•
•
•
•
•
•
可通过引脚编程设定的双极输入:±10V 和 ±5V
高输入阻抗:1MΩ
5V 模拟电源:2.3V 到 5V 数字 电源
7kV 静电放电 (ESD) 过压输入钳位
低漂移片上基准 (2.5V) 和缓冲器
出色的性能:
–
–
330kSPS 的最大吞吐量每通道
差分非线性 (DNL):±0.35 最低有效位 (LSB);
积分非线性 (INL):±0.45 LSB
ADS8584S 采用单一 5V 电源,并且可配置为接受
±10V 或 ±5V 真正双极输入。高输入阻抗特性允许直连
传感器和变压器,因此无需使用外部驱动器电路。此器
件能够实现高性能、高精度以及零延迟转换,因此
ADS8584S 同样非常适用于工业自动化和控制 IC。
–
信噪比 (SNR):96.4dB;总谐波失真 (THD):-
114dB
•
过热性能:
–
–
最大偏移漂移:3ppm/°C
增益漂移:6ppm/°C
•
•
•
•
用于过采样的片上数字滤波器
灵活的并行、字节和串行接口
温度范围:-40°C 至 +125°C
封装:64 引脚 LQFP
器件信息(1)
器件型号
封装
封装尺寸(标称值)
ADS8584S
LQFP (64)
10.00mm x 10.00mm
(1) 如需了解所有可用封装,请见数据表末尾的可订购产品附录。
2 应用
•
•
•
•
•
电网监控
保护中继器
多相电机控制
工业自动化和控制
多通道数据采集系统
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBAS834
ADS8584S
ZHCSG85A –APRIL 2017–REVISED APRIL 2017
www.ti.com.cn
简化框图
DVDD
AVDD
BUSY
ADS8584S
FRSTDATA
STBY
1 MW
CONVSTA, CONVSTB
RESET
AIN_1P
Clamp
Clamp
16-Bit
SAR
ADC
3rd-Order
LPF
ADC
Driver
PGA
AIN_1GND
RANGE
1 MW
CS
RD/SCLK
SAR
Logic
and
PAR/SER
DB[15:0]
1 MW
1 MW
SER/PAR
Interface
16-Bit
SAR
ADC
AIN_2P
Clamp
Clamp
3rd-Order
LPF
ADC
Driver
PGA
AIN_2GND
Digital Control
DOUTA
DOUTB
OS0
OS1
OS2
1 MW
1 MW
Digital Filter
AIN_3P
16-Bit
SAR
ADC
Clamp
Clamp
3rd-Order
LPF
ADC
Driver
PGA
AIN_3GND
REFCAPA
REFCAPB
1 MW
1 MW
16-Bit
SAR
ADC
AIN_4P
Clamp
Clamp
3rd-Order
LPF
ADC
Driver
PGA
AIN_4GND
REFIN/REFOUT
REFSEL
2.5 VREF
AGND
REFGND
Copyright © 2017, Texas Instruments Incorporated
2
版权 © 2017, Texas Instruments Incorporated
ADS8584S
www.ti.com.cn
ZHCSG85A –APRIL 2017–REVISED APRIL 2017
目录
7.17 Switching Characteristics: Parallel Data Read
Operation, CS and RD Separate ............................. 14
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 3
Device Family Comparison Table ........................ 4
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 7
7.4 Thermal Information.................................................. 7
7.5 Electrical Characteristics........................................... 8
7.6 Timing Requirements: CONVST Control ................ 11
7.7 Timing Requirements: Data Read Operation.......... 11
7.18 Switching Characteristics: Serial Data Read
Operation ................................................................. 14
7.19 Switching Characteristics: Byte Mode Data Read
Operation ................................................................. 14
7.20 Typical Characteristics.......................................... 18
Detailed Description ............................................ 25
8.1 Overview ................................................................. 25
8.2 Functional Block Diagram ....................................... 25
8.3 Feature Description................................................. 26
8.4 Device Functional Modes........................................ 34
Application and Implementation ........................ 47
9.1 Application Information............................................ 47
9.2 Typical Application .................................................. 47
8
9
7.8 Timing Requirements: Parallel Data Read Operation,
CS and RD Tied Together ....................................... 11
10 Power Supply Recommendations ..................... 51
11 Layout................................................................... 52
11.1 Layout Guidelines ................................................. 52
11.2 Layout Example .................................................... 52
12 器件和文档支持 ..................................................... 54
12.1 文档支持................................................................ 54
12.2 接收文档更新通知 ................................................. 54
12.3 社区资源................................................................ 54
12.4 商标....................................................................... 54
12.5 静电放电警告......................................................... 54
12.6 Glossary................................................................ 54
13 机械、封装和可订购信息....................................... 54
7.9 Timing Requirements: Parallel Data Read Operation,
CS and RD Separate ............................................... 12
7.10 Timing Requirements: Serial Data Read
Operation ................................................................. 12
7.11 Timing Requirements: Byte Mode Data Read
Operation ................................................................. 12
7.12 Timing Requirements: Oversampling Mode.......... 12
7.13 Timing Requirements: Exit Standby Mode............ 12
7.14 Timing Requirements: Exit Shutdown Mode......... 13
7.15 Switching Characteristics: CONVST Control ........ 13
7.16 Switching Characteristics: Parallel Data Read
Operation, CS and RD Tied Together ..................... 13
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Original (April 2017) to Revision A
Page
•
•
已更改 将文档状态从“预告信息”更改成了“生产数据”;拆分了文档 ADS8588S (SBAS642)................................................... 1
Changed minimum specification from –96 to –64 in last row of external reference for EG parameter ................................. 8
Copyright © 2017, Texas Instruments Incorporated
3
ADS8584S
ZHCSG85A –APRIL 2017–REVISED APRIL 2017
www.ti.com.cn
5 Device Family Comparison Table
PRODUCT
ADS8588S
ADS8586S
ADS8584S
ADS8578S
RESOLUTION (Bits)
CHANNELS
8, single-ended
6, single-ended
4, single-ended
8, single-ended
SAMPLE RATE (kSPS)
16
16
16
14
200
250
330
200
6 Pin Configuration and Functions
PM Package: ADS8584S
64-Pin LQFP
Top View
AVDD
AGND
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AVDD
2
AGND
OS0
3
REFGND
REFCAPB
REFCAPA
REFGND
REFIN/REFOUT
AGND
OS1
4
OS2
5
PAR/SER/BYTE SEL
STBY
6
7
RANGE
8
CONVSTA
CONVSTB
RESET
9
AGND
10
11
12
13
14
15
16
REGCAP2
AVDD
RD/SCLK
CS
AVDD
REGCAP1
AGND
BUSY
FRSTDATA
DB0
REFSEL
DB15/BYTE SEL
Not to scale
4
Copyright © 2017, Texas Instruments Incorporated
ADS8584S
www.ti.com.cn
ZHCSG85A –APRIL 2017–REVISED APRIL 2017
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
2, 26, 35, 40, 41, 47
P
Analog ground pins
Analog ground pins
AGND
53, 54, 55, 56, 61,
62, 63, 64
AI
AIN_1GND
AIN_1P
50
49
52
51
58
57
60
59
AI
AI
AI
AI
AI
AI
AI
AI
Analog input channel 1: negative input
Analog input channel 1: positive input
Analog input channel 2: negative input
Analog input channel 2: positive input
Analog input channel 3: negative input
Analog input channel 3: positive input
Analog input channel 4: negative input
Analog input channel 4: positive input
AIN_2GND
AIN_2P
AIN_3GND
AIN_3P
AIN_4GND
AIN_4P
Analog supply pins. Decouple these pins to the closest AGND pins
(see the Power Supply Recommendations section)
AVDD
1, 37, 38, 48
P
DO
DI
Active high digital output indicating ongoing conversion
(see the BUSY (Output) section)
BUSY
14
9
Active high logic input to control start of conversion for first half count of device input
channels (see the CONVSTA, CONVSTB (Input) section)
CONVSTA
CONVSTB
Active high logic input to control start of conversion for second half count of device input
channels (see the CONVSTA, CONVSTB (Input) section)
10
DI
CS
13
16
17
18
19
20
21
22
DI
Active low logic input chip-select signal (see the CS (Input) section)
Data output DB0 (LSB) in parallel interface mode (see the DB[6:0] section)
Data output DB1 in parallel interface mode (see the DB[6:0] section)
Data output DB2 in parallel interface mode (see the DB[6:0] section)
Data output DB3 in parallel interface mode (see the DB[6:0] section)
Data output DB4 in parallel interface mode (see the DB[6:0] section)
Data output DB5 in parallel interface mode (see the DB[6:0] section)
Data output DB6 in parallel interface mode (see the DB[6:0] section)
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DO
DO
DO
DO
DO
DO
DO
Multi-function logic output pin (see the DB7/DOUTA section):
this pin is data output DB7 in parallel and parallel byte interface mode;
this pin is a data output pin in serial interface mode.
DB7/DOUTA
DB8/DOUTB
24
25
DO
DO
Multi-function logic output pin (see the DB8/DOUTB section):
this pin is data output DB8 in parallel interface mode;
this pin is a data output pin in serial interface mode.
DB9
27
28
29
30
31
DO
DO
DO
DO
DO
Data output DB9 in parallel interface mode (see the DB[13:9] section)
Data output DB10 in parallel interface mode (see the DB[13:9] section)
Data output DB11 in parallel interface mode (see the DB[13:9] section)
Data output DB12 in parallel interface mode (see the DB[13:9] section)
Data output DB13 in parallel interface mode (see the DB[13:9] section)
DB10
DB11
DB12
DB13
Multi-function logic input or output pin (see the DB14/HBEN section):
this pin is data output DB14 in parallel interface mode;
this pin is a control input pin for byte selection (high or low) in parallel byte interface mode
DB14/HBEN
32
33
DIO
DIO
Multi-function logic input or output pin (see the DB15/BYTE SEL section):
this pin is data output DB15 (MSB) in parallel interface mode;
DB15/BYTE SEL
this pin is an active high control input pin to enable parallel byte interface mode.
DVDD
23
15
P
Digital supply pin; decouple with AGND on pin 26.
Active high digital output indicating data read back from channel 1 of the device (see the
FRSTDATA (Output) section)
FRSTDATA
DO
Oversampling mode control pin
(see the Oversampling Mode of Operation section)
OS0
3
4
5
6
DI
DI
DI
DI
Oversampling mode control pin
(see the Oversampling Mode of Operation section)
OS1
Oversampling mode control pin
(see the Oversampling Mode of Operation section)
OS2
Logic input pin to select between parallel, serial, or parallel byte interface mode (see the
Data Read Operation section)
PAR/SER/BYTE SEL
(1) AI = analog input; AO = analog output; AIO = analog input/output; DI = digital input; DO = digital output; DIO = digital input/output; P =
power supply; and NC = no connect.
Copyright © 2017, Texas Instruments Incorporated
5
ADS8584S
ZHCSG85A –APRIL 2017–REVISED APRIL 2017
www.ti.com.cn
Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
Multi-function logic input pin (see the RANGE (Input) section):
RANGE
8
DI
DI
when STBY pin is high, this pin selects the input range of the device (±10 V or ±5 V); when
STBY pin is low, this pin selects between the standby and shutdown modes.
Multi-function logic input pin (see the RD/SCLK (Input) section):
this pin is an active-low ready input pin in parallel and parallel byte interface;
this pin is a clock input pin in serial interface mode.
RD/SCLK
12
Reference amplifier output pins. This pin must be shorted to REFCAPB and decoupled to
AGND using a low ESR, 10-µF ceramic capacitor.
REFCAPA
REFCAPB
REFGND
44
45
AO
AO
P
Reference amplifier output pins. This pin must be shorted to REFCAPA and decoupled to
AGND using a low ESR, 10-µF ceramic capacitor.
Reference GND pin. This pin must be shorted to the analog GND plane and decoupled with
REFIN/REFOUT on pin 42 using a 10-µF capacitor.
43, 46
This pin acts as an internal reference output when REFSEL is high;
this pin functions as input pin for the external reference when REFSEL is low;
decouple with REFGND on pin 43 using a 10-µF capacitor.
REFIN/REFOUT
42
AIO
Active high logic input to enable the internal reference
(see the REFSEL (Input) section)
REFSEL
REGCAP1
REGCAP2
RESET
34
36
39
11
7
DI
AO
AO
DI
Output pin 1 for the internal voltage regulator; decouple separately to AGND using a 1-µF
capacitor.
Output pin 2 for the internal voltage regulator; decouple separately to AGND using a 1-µF
capacitor.
Active high logic input to reset the device digital logic
(see the RESET (Input) section)
Active low logic input to enter the device into one of the two power-down modes: standby or
shutdown (see the Power-Down Modes section)
STBY
DI
7 Specifications
7.1 Absolute Maximum Ratings
at TA = 25°C (unless otherwise noted)(1)
MIN
–0.3
–0.3
–15
MAX
UNIT
V
AVDD to AGND
7.0
DVDD to AGND
Analog input voltage to AGND(2)
7.0
15
V
V
Digital input to AGND
–0.3
–0.3
–10
DVDD + 0.3
AVDD + 0.3
10
V
REFIN to AGND
Input current to any pin except supplies(2)
V
mA
Operating
–40
125
Temperature
Junction, TJ
Storage, Tstg
150
°C
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Transient currents of up to 100 mA do not cause SCR latch-up.
7.2 ESD Ratings
VALUE
±2000
±7000
UNIT
All pins except analog inputs
Analog input pins only
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC
specification JESD22-C101(2)
All pins
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6
Copyright © 2017, Texas Instruments Incorporated
ADS8584S
www.ti.com.cn
ZHCSG85A –APRIL 2017–REVISED APRIL 2017
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.75
2.3
NOM
5
MAX
5.25
UNIT
V
AVDD
DVDD
Analog supply voltage
Digital supply voltage
3.3
AVDD
V
7.4 Thermal Information
ADS8584S
THERMAL METRIC(1)
PM (LQFP)
64 PINS
46.0
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
7.8
20.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
19.6
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2017, Texas Instruments Incorporated
7
ADS8584S
ZHCSG85A –APRIL 2017–REVISED APRIL 2017
www.ti.com.cn
7.5 Electrical Characteristics
minimum and maximum specifications are at TA = –40°C to +125°C, AVDD = 4.75 V to 5.25 V; typical specifications are at TA
= 25°C; AVDD = 5 V, DVDD = 3 V, VREF = 2.5 V (internal), and fSAMPLE = 330 kSPS (unless otherwise noted)
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
ANALOG INPUTS
Full-scale input span(2)
(AIN_nP to AIN_nGND)
RANGE pin = 1
–10
–5
10
5
A
A
A
A
V
V
RANGE pin = 0
RANGE pin = 1
RANGE pin = 0
–10
–5
10
5
Operating input range,
positive input
AIN_nP
Operating input range,
negative input
AIN_nGND
All input ranges
–0.3
0
0.3
V
B
RIN
Input impedance
At TA = 25°C
0.85
–25
1
1.15
MΩ
B
B
Input impedance drift
All input ranges
±7
25 ppm/°C
µA
With voltage at AIN_nP = VIN
all input ranges
,
IIkg(in)
Input leakage current
(VIN – 2) / RIN
A
SYSTEM PERFORMANCE
Resolution
16
16
Bits
Bits
LSB(3)
A
A
A
A
NMC
DNL
INL
No missing codes
Differential nonlinearity
Integral nonlinearity(4)
All input ranges
All input ranges
–0.5
–1.5
±0.35
±0.45
0.5
1.5
LSB
TA = –40°C to
+85°C
All input
ranges,
external
reference
–64
–64
±4
±4
64
96
A
A
A
A
A
B
B
TA = –40°C to
+125°C
EG
Gain error(5)
LSB
LSB
All input ranges,
internal reference
±4
Input range = ±10 V,
external and internal reference
10
60
60
14
Gain error matching
(channel-to-channel)
Input range = ±5 V,
external and internal reference
12
All input ranges,
–14
±6
external reference
Gain error temperature drift
Offset error
ppm/°C
mV
All input ranges,
internal reference
±10
Input range = ±10 V
Input range = ±5 V
–1.8
–1.8
±0.15
±0.15
1.8
1.8
B
B
EO
Offset error matching
(channel-to-channel)
All input ranges
All input ranges
0.3
2.4
3
mV
B
B
Offset error temperature drift
–3
1
±0.3
ppm/°C
SAMPLING DYNAMICS
tACQ Acquisition time
µs
A
A
Maximum throughput rate per channel
without latency
fS
All four channels included
330
kSPS
(1) Test Levels: (A) Tested at final test. Overtemperature limits are set by characterization and simulation. (B) Limits set by characterization
and simulation, across temperature range. (C) Typical value only for information, provided by design simulation.
(2) Ideal input span, does not include gain or offset error.
(3) LSB = least significant bit.
(4) This parameter is the endpoint INL, not best-fit INL.
(5) Gain error is calculated after adjusting for offset error, which implies that positive full-scale error = negative full-scale error = gain error ÷
2.
8
Copyright © 2017, Texas Instruments Incorporated
ADS8584S
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ZHCSG85A –APRIL 2017–REVISED APRIL 2017
Electrical Characteristics (continued)
minimum and maximum specifications are at TA = –40°C to +125°C, AVDD = 4.75 V to 5.25 V; typical specifications are at TA
= 25°C; AVDD = 5 V, DVDD = 3 V, VREF = 2.5 V (internal), and fSAMPLE = 330 kSPS (unless otherwise noted)
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
DYNAMIC CHARACTERISTICS
Signal-to-noise ratio,
no oversampling
(VIN – 0.5 dBFS at 1 kHz)
Input range = ±10 V
91
90.4
95.5
94.4
92.7
92.2
96.4
95.5
A
A
A
A
SNR
dB
Input range = ±5 V
Input range = ±10 V
Input range = ±5 V
Signal-to-noise ratio,
oversampling = 16x
(VIN – 0.5 dBFS at 130 Hz)
Total harmonic distortion(6)
(VIN – 0.5 dBFS at 1 kHz)
SNROSR
THD
dB
dB
dB
All input ranges
–114
–95
B
Signal-to-noise + distortion ratio,
no oversampling
(VIN – 0.5 dBFS at 1 kHz)
Input range = ±10 V
Input range = ±5 V
Input range = ±10 V
Input range = ±5 V
90.7
90.2
95
92.7
92.1
96.4
95.4
A
A
A
A
SINAD
Signal-to-noise + distortion ratio,
oversampling = 16x
(VIN – 0.5 dBFS at 130 Hz)
SINADOSR
SFDR
dB
94
Spurious-free dynamic range
(VIN – 0.5 dBFS at 1 kHz)
Crosstalk isolation(7)
All input ranges
–118
–95
24
dB
dB
B
A
B
At TA = 25°C,
input range = ±10 V
BW(–3 dB)
–3 dB
kHz
At TA = 25°C,
input range = ±5 V
16
14
B
B
B
Small-signal
bandwidth
At TA = 25°C,
input range = ±10 V
BW(–0.1 dB)
–0.1 dB
kHz
µs
At TA = 25°C,
input range = ±5 V
9.5
Input range = ±10 V
Input range = ±5 V
13
19
C
C
tGROUP
Group delay
INTERNAL REFERENCE OUTPUT (REFSEL = 1)
Voltage on the REFIN/REFOUT pin
(configured as output)
(8)
VREF
At TA = 25°C
2.4975
3.996
2.5
7.5
10
2.5025
V
ppm/°C
µF
A
B
B
Internal reference temperature drift
Decoupling capacitor on
C(REFIN_ REFOUT)
REFIN/REFOUT(9)
Reference voltage to the ADC
V(REFCAP)
At TA = 25°C
4.0
0.5
5
4.004
1
V
Ω
A
C
B
(on the REFCAPA, REFCAPB pin)
Reference buffer output impedance
Reference buffer output temperature
drift
ppm/°C
Decoupling capacitor on REFCAPA,
REFCAPB
C(REFCAP)
10
25
µF
B
B
C(REFCAP) = 10 µF,
C(REFIN_REFOUT) = 10 µF
Turn-on time
ms
EXTERNAL REFERENCE INPUT (REFSEL = 0)
External reference voltage on REFIO
(configured as input)
VREFIO_EXT
2.475
2.5
2.525
V
B
Reference input impedance
Reference input capacitance
100
10
MΩ
C
C
pF
(6) Calculated on the first nine harmonics of the input frequency.
(7) Isolation crosstalk is measured by applying a full-scale sinusoidal signal up to 160 kHz to a channel, not selected in the multiplexing
sequence, and measuring the effect on the output of any selected channel.
(8) Does not include the variation in voltage resulting from solder shift effects.
(9) Recommended to use an X7R-grade, 0603-size ceramic capacitor for optimum performance (see the Layout Guidelines section).
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Electrical Characteristics (continued)
minimum and maximum specifications are at TA = –40°C to +125°C, AVDD = 4.75 V to 5.25 V; typical specifications are at TA
= 25°C; AVDD = 5 V, DVDD = 3 V, VREF = 2.5 V (internal), and fSAMPLE = 330 kSPS (unless otherwise noted)
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
POWER-SUPPLY REQUIREMENTS
AVDD
DVDD
Analog power-supply voltage
Analog supply
4.75
2.3
5
5.25
V
V
A
A
Digital power-supply voltage
Digital supply range
3.3
AVDD
For ADS8584S, AVDD = 5 V,
fS = 330 kSPS,
internal reference
10.9
10.4
8.0
14.8
14.1
10.9
10.2
4.2
A
A
A
A
A
A
Analog supply current
(operational)
IAVDD_DYN
IAVDD_STC
IAVDD_STDBY
mA
mA
mA
For ADS8584S, AVDD = 5 V,
fS = 330 kSPS,
external reference
For ADS8584S, AVDD = 5 V,
internal reference,
device not converting
Analog supply current
(static)
For ADS8584S, AVDD = 5 V,
external reference,
device not converting
7.5
At AVDD = 5 V, device in STDBY
mode,
internal reference
3.2
AVDD supply
STANDBY current
At AVDD = 5 V, device in STDBY
mode,
2.7
3.6
external reference
At AVDD = 5 V, device in
PWR_DN, internal or
external reference,
AVDD supply
power-down current
IAVDD_PWR_ DN
0.2
6
µA
A
A
TA = –40°C to +85°C
For ADS8584S,
DVDD = 3.3 V,
fS = 330 kSPS
IDVDD_DYN
Digital supply current
0.15
0.3
mA
At AVDD = 5 V, device in STDBY
mode
IDVDD_STDBY
DVDD supply STANDBY current
DVDD supply power-down current
0.05
0.05
1.5
1.5
µA
µA
A
A
At AVDD = 5 V, device in
PWR_DN mode
IDVDD_PWR-DN
DIGITAL INPUTS (CMOS)
VIH
VIL
Digital high input voltage logic level
DVDD > 2.3 V
DVDD > 2.3 V
0.7 × DVDD
–0.3
DVDD + 0.3
0.3 × DVDD
V
V
A
A
A
A
Digital low input voltage logic level
Input leakage current
100
5
nA
pF
Input pin capacitance
DIGITAL OUTPUTS (CMOS)
VOH
VOL
Digital high output voltage logic level
IO = 100-µA source
IO = 100-µA sink
Only for SDO
0.8 × DVDD
0
DVDD
V
V
A
A
A
A
Digital low output voltage logic level
Floating state leakage current
Internal pin capacitance
0.2 × DVDD
1
5
µA
pF
TEMPERATURE RANGE
TA
Operating free-air temperature
–40
125
°C
A
10
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7.6 Timing Requirements: CONVST Control
minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,
2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), BUSY load = 20 pF, VIL and VIH at datasheet limits, and fSAMPLE = 330 kSPS
(unless otherwise noted) (see Figure 1)
MIN
NOM
MAX
UNIT
Acquisition time:
tACQ
1
µs
BUSY falling edge to rising edge of trailing CONVSTA or CONVSTB
tPH_CN
tPL_CN
CONVSTA, CONVSTB pulse high time
CONVSTA, CONVSTB pulse low time
25
25
0
ns
ns
ns
ns
ns
µs
tSU_BSYCS Setup time: BUSY falling to CS falling
tSU_RSTCN Setup time: RESET falling to first rising edge of CONVSTA or CONVSTB
25
50
tPH_RST
tD_CNAB
RESET pulse high time
Delay between rising edges of CONVSTA and CONVSTB
500
7.7 Timing Requirements: Data Read Operation
minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,
2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), BUSY load = 20 pF, VIL and VIH at datasheet limits, and fSAMPLE = 330 kSPS
(unless otherwise noted) (see Figure 2)
MIN
NOM
MAX
UNIT
Delay between CONVSTA, CONVSTB rising edge to CS falling edge, start of
data read operation during conversion
tDZ_CNCS
tDZ_CSBSY
tSU_BSYCS
tD_CSCN
10
ns
Delay between CS rising edge to BUSY falling edge, end of data read
operation during conversion
40
0
ns
ns
ns
Setup time: BUSY falling edge to CS falling edge, start of data read operation
after conversion
Delay between CS rising edge to CONVSTA, CONVSTB rising edge, end of
data read operation after conversion
10
7.8 Timing Requirements: Parallel Data Read Operation, CS and RD Tied Together
minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,
2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, VIL and VIH at datasheet limits,
and fSAMPLE = 330 kSPS (unless otherwise noted) (see Figure 3)
MIN
NOM
MAX UNIT
tPH_CS
tPH_RD
,
CS and RD high time
15
ns
tPL_CS
tPL_RD
,
CS and RD low time
15
ns
ns
tHT_RDDB
tHT_CSDB
,
Hold time: RD and CS rising edge to DB[15:0] invalid
2.5
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7.9 Timing Requirements: Parallel Data Read Operation, CS and RD Separate
minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,
2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, VIL and VIH at datasheet limits,
and fSAMPLE = 330 kSPS (unless otherwise noted) (see Figure 4)
MIN
0
NOM
MAX UNIT
tSU_CSRD Setup time: CS falling edge to RD falling edge
tHT_RDCS Hold time: RD rising edge to CS rising edge
ns
ns
ns
ns
ns
ns
0
tPL_RD
tPH_RD
RD low time
RD high time
15
15
6
tHT_CSDB Hold time: CS rising edge to DB[15:0] becoming invalid
tHT_RDDB Hold time: RD rising edge to DB[15:0] becoming invalid
2.5
7.10 Timing Requirements: Serial Data Read Operation
minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,
2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DOUTA, DOUTB, and FRSTDATA = 20 pF, VIL and VIH at datasheet
limits, and fSAMPLE = 330 kSPS (unless otherwise noted) (see Figure 5)
MIN
50
NOM
MAX UNIT
tSCLK
tPH_SCLK SCLK high time
tPL_SCLK SCLK low time
SCLK time period
ns
0.45
0.45
7
0.55 tSCLK
0.55 tSCLK
tHT_CKDO Hold time: SCLK rising edge to DOUTA, DOUTB invalid
tSU_CSCK Setup time: CS falling to first SCLK edge
ns
ns
ns
8
tHT_CKCS Hold time: last SCLK active edge to CS high
10
7.11 Timing Requirements: Byte Mode Data Read Operation
minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,
2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DB[7:0] and FRSTDATA = 20 pF, VIL and VIH at datasheet limits, and
fSAMPLE = 330 kSPS (unless otherwise noted) (see Figure 6)
MIN
0
NOM
MAX UNIT
tSU_CSRD Setup time: CS falling edge to RD falling edge
tHT_RDCS Hold time: RD rising edge to CS rising edge
ns
ns
ns
ns
ns
ns
0
tPL_RD
tPH_RD
RD low time
RD high time
15
15
6
tHT_CSDB Hold time: CS rising edge to DB[15:0] becoming invalid
tHT_RDDB Hold time: RD rising edge to DB[15:0] becoming invalid
2.5
7.12 Timing Requirements: Oversampling Mode
MIN
20
NOM
MAX
UNIT
ns
tHT_OS
tSU_OS
Hold time: BUSY falling to OSx
Setup time: BUSY falling to OSx
20
ns
7.13 Timing Requirements: Exit Standby Mode
minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C, AVDD = 5 V,
2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), VIL and VIH at datasheet limits, and fSAMPLE = 330 kSPS (unless otherwise
noted) (see Figure 8)
MIN
NOM
MAX
UNIT
tD_STBYCN Delay between STBY rising edge to CONVSTA or CONVSTB rising edge(1)
100
µs
(1) First conversion data must be discarded or RESET must be issued if the maximum timing is exceeded.
12
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7.14 Timing Requirements: Exit Shutdown Mode
minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,
2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), VIL and VIH at datasheet limits, and fSAMPLE = 330 kSPS (unless otherwise
noted) (see Figure 9)
MIN
50
NOM
MAX UNIT
Internal reference mode
External reference mode(1)
tD_SDRST Delay between STBY rising edge to RESET rising edge
tPH_RST RESET high time
ms
13
50
ns
µs
tD_RSTCN Delay between RESET falling edge to CONVSTA or CONVSTB rising edge
(1) Excludes wake-up time for external reference device.
25
7.15 Switching Characteristics: CONVST Control
minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,
2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), BUSY load = 20 pF, VIL and VIH at datasheet limits, and fSAMPLE = 330 kSPS
(unless otherwise noted) (see Figure 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
No oversampling, parallel read, serial
read with both DOUTA and DOUTB
during conversion
3
No oversampling, serial read after
conversion with both DOUTA and
DOUTB
tCYC
ADC cycle time period
3.8
5.5
µs
No oversampling, serial read after
conversion with only DOUTA or
DOUTB
No oversampling
2
5
Oversampling by 2
Oversampling by 4
Oversampling by 8
Oversampling by 16
Oversampling by 32
Oversampling by 64
11
23
47
95
191
tCONV
Conversion time: BUSY high time
µs
ns
Delay between trailing rising edges of
CONVSTA or CONVSTB and BUSY
rising
tD_CNBSY
15
7.16 Switching Characteristics: Parallel Data Read Operation, CS and RD Tied Together
minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,
2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, VIL and VIH at datasheet limits,
and fSAMPLE = 330 kSPS (unless otherwise noted) (see Figure 3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Delay time: CS falling edge to DB[15:0]
becoming valid
(out of tri-state)
tD_CSDB
12
17
10
ns
ns
ns
Delay time: RD falling edge to new
data on DB[15:0]
tD_RDDB
Delay time: CS and RD falling edge to
FRSTDATA going high or low out of tri-
state
tD_CSFD
,
tD_RDFD
tDHZ_CSDB
,
Delay time: CS and RD rising edge to
DB[15:0] tri-state
12
10
ns
ns
tDHZ_RDDB
tDHZ_CSFD
tDHZ_RDFD
,
Delay time: CS and RD rising edge to
FRSTDATA tri-state
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7.17 Switching Characteristics: Parallel Data Read Operation, CS and RD Separate
minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,
2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, VIL and VIH at datasheet limits,
and fSAMPLE = 330 kSPS (unless otherwise noted) (see Figure 4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delay time: CS falling edge to DB[15:0]
becoming valid
tD_CSDB
12
ns
(out of tri-state)
Delay time: RD falling edge to new data
on DB[15:0]
tD_RDDB
17
12
15
10
15
ns
ns
ns
ns
ns
Delay time: CS rising edge to DB[15:0]
becoming tri-state
tDHZ_CSDB
tD_CSFD
tDHZ_CSFD
tD_RDFD
Delay time: CS falling edge to
FRSTDATA going low out of tri-state
Delay time: CS rising edge to
FRSTDATA going to tri-state
Delay time: RD falling edge to
FRSTDATA going high or low
7.18 Switching Characteristics: Serial Data Read Operation
minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,
2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DOUTA, DOUTB, and FRSTDATA = 20 pF, VIL and VIH at datasheet
limits, and fSAMPLE = 330 kSPS (unless otherwise noted) (see Figure 5)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delay time: CS falling edge to DOUTA,
DOUTB enable
tD_CSDO
12
ns
(out of tri-state)
Delay time: SCLK rising edge to valid
data on DOUTA, DOUTB
tD_CKDO
tDZ_CSDO
tD_CSFD
15
12
10
15
10
ns
ns
ns
ns
ns
Delay time: CS rising edge to DOUTA,
DOUTB going to tri-state
Delay time: CS falling edge to
FRSTDATA from tri-state to high or low
Delay time: 16th SCLK falling edge to
FRSTDATA falling edge
tDZ_CKFD
tDHZ_CSFD
Delay time: CS rising edge to
FRSTDATA going to tri-state
7.19 Switching Characteristics: Byte Mode Data Read Operation
minimum and maximum specifications are at TA = –40°C to +125°C, typical specifications are at TA = 25°C; AVDD = 5 V,
2.3 V ≤ DVDD ≤ 5.25 V, VREF = 2.5 V (internal), load on DB[7:0] and FRSTDATA = 20 pF, VIL and VIH at datasheet limits, and
fSAMPLE = 330 kSPS (unless otherwise noted) (see Figure 6)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delay time: CS falling edge to DB[7:0]
becoming valid
tD_CSDB
12
ns
(out of tri-state)
Delay time: RD falling edge to new data
on DB[7:0]
tD_RDDB
17
12
10
15
10
ns
ns
ns
ns
ns
Delay time: CS rising edge to DB[7:0]
becoming tri-state
tDHZ_CSDB
tD_CSFD
Delay time: CS falling edge to
FRSTDATA going low out of tri-state
Delay time: RD falling edge to
FRSTDATA going low or high state
tD_RDFD
Delay time: CS rising edge to
FRSTDATA going to tri-state
tDHZ_CSFD
14
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tCYC
CONVSTA
tD_CNAB
tACQ
tPL_CN
tPH_CN
CONVSTB
BUSY
tD_CNBSY
tCONV
tSU_BSYCS
CS
tSU_RSTCN
RESET
tPH_RST
Figure 1. CONVST Control Timing Diagram
CONVSTA
CONVSTB
tD_CSCN
tSU_BSYCS
BUSY
tDZ_CNCS
tDZ_CSBSY
CS
Read During Conversion
Read After Conversion
tSU_RSTCN
RESET
tPH_RST
Figure 2. Data Read Operation Timing Diagram
tPH_CS
tPL_CS
tPL_RD
tPH_RD
tHT_CSDB
tHT_RDDB
RD
CS
,
tD_CSDB
tD_RDDB
tDHZ_CSDB
tDHZ_RDDB
AIN_1
Data
AIN_2
Data
AIN_4
Data
AIN_3
Data
DB[15:0]
tD_CSFD
tD_RDFD
tDHZ_CSFD
tDHZ_RDFD
FRSTDATA
Figure 3. Parallel Data Read Operation, CS and RD Tied Together
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CS
tHT_RDCS
tPH_RD
tSU_CSRD
tPL_RD
RD
tHT_CSDB
tDHZ_CSDB
tD_CSDB
tD_RDDB
tHT_RDDB
AIN_1
Data
AIN_2
Data
AIN_3
Data
AIN_4
Data
DB[15:0]
Invalid
tD_CSFD
tD_RDFD
tDHZ_CSFD
FRSTDATA
Figure 4. Parallel Data Read Operation, CS and RD Separate
tSU_CSCK
tSCLK
CS
tPH_SCLK
tHT_CKCS
tPL_SCLK
SCLK
tD_CSDO
tHT_CKDO
tDZ_CSDO
tD_CKDO
DOUTA
DOUTB
DB15 DB14 DB13
DB1
DB0
tDZ_CKFD
tD_CSFD
tDHZ_CSFD
FRSTDATA
Figure 5. Serial Data Read Operation Timing Diagram
CS
tPH_RD
tHT_RDCS
tSU_CSRD
tPL_RD
RD
tHT_CSDB
tDHZ_CSDB
tD_CSDB
tD_RDDB
tHT_RDDB
High Byte
AIN_1
Low Byte
AIN_1
High Byte
AIN_2
Low Byte
AIN_2
Low Byte
AIN_3
High Byte
AIN_4
Low Byte
AIN_4
High Byte
AIN_3
DB[7:0]
Invalid
tD_CSFD
tD_RDFD
tDHZ_CSFD
FRSTDATA
Figure 6. Byte Mode Data Read Operation Timing Diagram
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CONVSTA
CONVSTB
OSR latched for
Conversion (N+1)
Conversion
N
Conversion
N+1
BUSY
OSR x
tHT_OS
tSU_OS
Figure 7. Oversampling Mode Timing Diagram
STBY
RANGE
tD_STBYCN
CONVSTA
CONVSTB
Figure 8. Exit Standby Mode Timing Diagram
STBY
RANGE
tD_SDRST
RESET
tPH_RST
CONVSTA
tD_RSTCN
CONVSTB
Figure 9. Exit Shutdown Mode Timing Diagram
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7.20 Typical Characteristics
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 2.5 V, and fS = 330 kSPS per channel (unless otherwise
noted)
9
6
15
9
25 C
-40 C
125 C
25 C
-40 C
125 C
3
3
0
-3
-9
-15
-3
-6
-9
-10
-6
-2
2
6
10
-5
-3
-1
1
3
5
Input Voltage (V)
Input Voltage (V)
D002
D003
Figure 10. Analog Input Current vs Input Voltage Over
Temperature (±10 V)
Figure 11. Analog Input Current vs Input Voltage Over
Temperature (±5 V)
3000
1.05
± 10 V
± 5 V
2500
2000
1500
1000
500
1.03
1.01
0.99
0.97
0.95
0
-40
-7
26
59
92
125
-3
-2
-1
0
1
2
3
Free-Air Temperature (èC)
Output Codes
D004
D010
Mean = –0.14, sigma = 0.51, number of hits = 4096, VIN = 0 V
Figure 12. Input Impedance vs Temperature
Figure 13. DC Histogram of Codes (±10 V)
2100
1800
1500
1200
900
600
300
0
0.5
0.3
0.1
-0.1
-0.3
-0.5
-3
-2
-1
0
1
2
3
-32768
-16384
0
16384
32767
Output Codes
Codes (LSB) 2's Complement
D009
D011
Mean = –0.02, sigma = 0.54, number of hits = 4096, VIN = 0 V
Figure 14. DC Histogram of Codes (±5 V)
Figure 15. DNL for All Codes
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 2.5 V, and fS = 330 kSPS per channel (unless otherwise
noted)
0.5
1.5
1
0.3
0.5
0
0.1
-0.1
-0.3
-0.5
-0.5
-1
Maximum
-7
Minimum
26
-1.5
-32768
-40
59
92
125
-16384
0
16384
32767
Free-Air Temperature (èC)
Codes (LSB) 2's Complement
D012
D013
Figure 16. DNL vs Temperature
Figure 17. INL vs All Codes (±10 V)
1.5
1
1.5
1
Maximum
Minimum
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-1.5
-32768
-16384
0
16384
32767
-40
-7
26
59
92
125
Codes (LSB) 2's Complement
Free-Air Temperature (èC)
D014
D015
Figure 18. INL vs All Codes (±5 V)
Figure 19. INL vs Temperature (±10 V)
1.5
1
1.8
1.08
0.36
-0.36
-1.08
-1.8
Maximum
Minimum
± 10 V
± 5 V
0.5
0
-0.5
-1
-1.5
-40
-7
26
59
92
125
-40
-7
26
59
92
125
Free-Air Temperature (èC)
Free-Air Temperature (èC)
D016
D017
Figure 20. INL vs Temperature (±5 V)
Figure 21. Offset Error vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 2.5 V, and fS = 330 kSPS per channel (unless otherwise
noted)
130
120
110
100
90
1.8
1.08
0.36
-0.36
-1.08
-1.8
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
80
70
60
50
40
30
20
10
0
0
0.355 0.76 1.165 1.57 1.975 2.38 2.785 3
-40
-7
26
59
92
125
Offset Drift (ppm/èC)
Free-Air Temperature (èC)
D018
D019
Figure 22. Offset Drift Histogram Distribution (±10 V)
Figure 23. Offset Error Across Channels vs Temperature
(±10 V)
130
1.8
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
120
110
100
90
80
70
60
50
40
30
20
10
0
1.08
0.36
-0.36
-1.08
-1.8
0
0.22 0.49 0.76 1.03 1.3 1.57 1.84 2.11 2.38 2.65
3
-40
-7
26
59
92
125
Offset Drift (ppm/èC)
Free-Air Temperature (èC)
D020
D021
Figure 24. Offset Drift Histogram Distribution (±5 V)
Figure 25. Offset Error Across Channels vs Temperature
(±5 V)
64
38.4
12.8
-12.8
-38.4
-64
80
70
60
50
40
30
20
10
0
± 10 V
± 5 V
-40
-7
26
59
92
125
0
1.76 4.21 5.595 6.98 8.365 9.75 11.13512.52 14
Free-Air Temperature (èC)
Gain Drift (ppm/èC)
D022
D023
External reference
External reference
Figure 26. Gain Error vs Temperature
Figure 27. Gain Error Drift Histogram Distribution (±10 V)
20
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 2.5 V, and fS = 330 kSPS per channel (unless otherwise
noted)
80
70
60
50
40
30
20
10
0
80
60
40
20
0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
-20
-40
-60
-40
-7
26
59
92
125
0
1.76 4.21 5.595 6.98 8.365 9.75 11.13512.52 14
Free-Air Temperature (èC)
Gain Drift (ppm/èC)
D024
D025
External reference
External reference
Figure 28. Gain Error Across Channels vs Temperature
(±10 V)
Figure 29. Gain Error Drift Histogram Distribution (±5 V)
80
60
40
20
0
25
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
± 5 V
± 10 V
20
15
10
5
-20
-40
-60
0
-5
-40
-7
26
59
92
125
0
50
100
150
200
Free-Air Temperature (èC)
Source Resistance (kW)
D026
D027
External reference
Figure 30. Gain Error Across Channels vs Temperature
(±5 V)
Figure 31. Gain Error as a Function of External Source
Resistance
0
0
-50
-50
-100
-100
-150
-200
-150
-200
0
33
66
99
132
165
0
33
66
99
132
165
Frequency (kHz)
Frequency (kHz)
D028
D029
Number of points = 32k, SNR = 92.61 dB,
Number of points = 32k, SNR = 92.25 dB,
SINAD = 92.53 dB, THD = –110.64 dB, SFDR = 113.89 dB
SINAD = 92.12 dB, THD = –110.78 dB, SFDR = 114.02 dB
Figure 32. Typical FFT Plot (±10 V)
Figure 33. Typical FFT Plot (±5 V)
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 2.5 V, and fS = 330 kSPS per channel (unless otherwise
noted)
0
0
-50
-50
-100
-150
-200
-100
-150
-200
0
2.05
4.1
6.15
8.2
10.25
0
2.05
4.1
6.15
8.2
10.25
Frequency (kHz)
Frequency (kHz)
D030
D031
Number of points = 32k, SNR = 96.31 dB,
Number of points = 32k, SNR = 95.54 dB,
SINAD = 95.9 dB, THD = –111.23 dB, SFDR = 115.01 dB
SINAD = 95.01 dB, THD = –110.08 dB, SFDR = 114.67 dB
Figure 34. Typical FFT Plot for OSR 16x (±10 V)
Figure 35. Typical FFT Plot for OSR 16x (±5 V)
94
95
± 10 V
± 5 V
93
92
91
90
89
94
93
92
91
90
88
± 5 V
± 10 V
87
10
100
1k
10k
100k
-40
-7
26
59
92
125
Input Frequency (Hz)
Free-Air Temperature (èC)
D032
D033
OSR = 0
OSR = 0
Figure 36. SNR vs Input Frequency for Different Input
Ranges
Figure 37. SNR vs Temperature for Different Input Ranges
100
98
96
94
92
90
98
96
94
92
90
88
86
84
82
OSR-0
OSR-2
OSR-4
OSR-8
OSR-16
OSR-32
OSR-64
88
OSR-0
OSR-2
OSR-4
OSR-8
OSR-16
OSR-32
OSR-64
86
10
100
1k
Input Frequency (Hz)
10k
100k
10
100
1k
Input Frequency (Hz)
10k
100k
D034
D035
Figure 38. SNR vs Input Frequency for Different OSR
(±10 V)
Figure 39. SNR vs Input Frequency for Different OSR
(±5 V)
22
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 2.5 V, and fS = 330 kSPS per channel (unless otherwise
noted)
95
94
93
92
91
90
93
92
91
90
89
88
87
± 10 V
± 5 V
± 10 V
± 5 V
-40
-7
26
59
92
125
10
100
1k
10k
100k
Free-AirTemperature (èC)
Input Frequency (Hz)
D037
D036
OSR = 0
OSR = 0
Figure 41. SINAD vs Temperature for Different Input Ranges
Figure 40. SINAD vs Input Frequency for Different Input
Ranges
-80
-100
± 10 V
± 5 V
± 10 V
± 5 V
-85
-105
-90
-95
-110
-115
-120
-125
-130
-100
-105
-110
-115
-120
-125
-130
10
100
1k
10k
100k
-40
-7
26
59
92
125
Input Frequency (Hz)
Free-Air Temperature (èC)
D038
D039
Figure 42. THD vs Input Frequency for Different Input
Ranges
Figure 43. THD vs Temperature for Different Input Ranges
-60
-60
0 kW
0 kW
10 kW
10 kW
20 kW
30 kW
40 kW
50 kW
61 kW
68.1 kW
82.5 kW
90.9 kW
100 kW
-70
-80
-70
20 kW
30 kW
40 kW
-80
50 kW
61 kW
68.1 kW
-90
-90
82.5 kW
90.9 kW
100 kW
-100
-110
-120
-100
-110
-120
1k
10k
100k
1k
10k
100k
Input Frequency (Hz)
Input Frequency (Hz)
D040
D041
Figure 44. THD vs Input Frequency for Different Source
Impedances (±10 V)
Figure 45. THD vs Input Frequency for Different Source
Impedances (±5 V)
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 2.5 V, and fS = 330 kSPS per channel (unless otherwise
noted)
-90
-100
-110
-120
-130
-140
-90
-100
-110
-120
-130
-140
-150
±5 V
±10 V
± 5 V
± 10 V
100m
1
10
100
100m
1
10
100
Frequency (kHz)
Frequency (kHz)
D043
D042
Figure 47. Isolation Crosstalk vs Noise Frequency
(Saturated Inputs)
Figure 46. Isolation Crosstalk vs Noise Frequency
(Inputs Within Range)
11.2
11.1
11
8.1
8.05
8
± 10 V
± 5 V
10.9
10.8
10.7
10.6
7.95
7.9
7.85
-40
-7
26
59
92
125
-40
-7
26
59
92
125
Free-Air Temperature (èC)
Free-Air Temperature (èC)
D053
D055
Figure 48. Analog Supply Current (Operational) vs
Temperature
Figure 49. Analog Supply Current (Static) vs Temperature
(Sampling)
4.26
4.24
4.22
4.2
6
5
4
3
4.18
4.16
4.14
4.12
2
1
0
-1
-40
-40
-7
26
59
92
125
-7
26
59
92
125
Free-Air Temperature (èC)
Free-Air Temperature (èC)
D056
D057
Figure 50. Analog Supply Current vs Temperature
(Standby)
Figure 51. Analog Supply Current vs Temperature
(Shutdown)
24
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8 Detailed Description
8.1 Overview
The ADS8584S is a 16-bit data acquisition (DAQ) system with 4-channel analog inputs. Each analog input
channel consists of an input clamp protection circuit, a programmable gain amplifier (PGA), a third-order, low-
pass filter, and a track-and-hold circuit that facilitates simultaneous sampling of the signals on all input channels.
The sampled signal is digitized using a 16-bit analog-to-digital converter (ADC), based on the successive
approximation register (SAR) architecture. This overall system can achieve a maximum throughput of 330 kSPS
per channel. The device features a 2.5-V internal reference with a fast-settling buffer, a programmable digital
averaging filter to improve noise performance, and high speed serial and parallel interfaces for communication
with a wide variety of digital hosts.
The device operates from a single 5-V analog supply and can accommodate true bipolar input signals of ±10 V
and ±5 V. The input clamp protection circuitry can tolerate voltages up to ±15 V. The device offers a constant
1-MΩ resistive input impedance irrespective of the sampling frequency or the selected input range. The
integration of multiple, simultaneously sampling precision ADC inputs and analog front-end circuits with high
input impedance operating from a single 5-V supply offers a simplified end solution without requiring external
high-voltage bipolar supplies and complicated driver circuits.
8.2 Functional Block Diagram
AVDD
DVDD
BUSY
1 Mꢀ
1 Mꢀ
FRSTDATA
AIN_1P
16-Bit
SAR
ADC
Clamp
Clamp
ADC
Driver
3rd-Order
LPF
PGA
STBY
AIN_1GND
CONVSTA, CONVSTB
RESET
RANGE
CS
RD/SCLK
1 Mꢀ
1 Mꢀ
AIN_2P
Clamp
Clamp
PAR/SER
DB[15:0]
SAR
Logic and
Digital Control
16-Bit
SAR
ADC
ADC
Driver
3rd-Order
LPF
SER/PAR
Interface
PGA
AIN_2GND
DOUTA
DOUTB
OS0
OS1
OS2
1 Mꢀ
1 Mꢀ
AIN_3P
Clamp
Clamp
16-Bit
SAR
ADC
ADC
Driver
3rd-Order
LPF
Digital Filter
PGA
AIN_3GND
REFCAPA
REFCAPB
1 Mꢀ
1 Mꢀ
AIN_4P
Clamp
Clamp
16-Bit
SAR
ADC
ADC
Driver
3rd-Order
LPF
PGA
AIN_4GND
REFIN/REFOUT
REFSEL
2.5-V V
REF
ADS8584S
AGND
REFGND
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8.3 Feature Description
8.3.1 Analog Inputs
The ADS8584S has 4 analog input channels, such that the positive inputs AIN_nP (n = 1 to 4) are the single-
ended analog inputs and the negative inputs AIN_nGND are tied to GND. Figure 52 shows the simplified circuit
schematic for each analog input channel, including the input clamp protection circuit, PGA, low-pass filter, high-
speed ADC driver, and a precision 16-bit SAR ADC.
1 MW
AIN_nP
Clamp
Clamp
16-Bit
SAR
ADC
3rd-Order
LPF
ADC
Driver
PGA
AIN_nGND
1 MW
Figure 52. Front-End Circuit Schematic for Each Analog Input Channel
The device can support two bipolar, single-ended input voltage ranges based on the logic level of the RANGE
input pin. As explained in the RANGE (Input) section, the input voltage range for all analog channels can be
configured to bipolar ±10 V or ±5 V. The device samples the voltage difference (AIN_nP – AIN_nGND) between
the selected analog input channel and the AIN_nGND pin. The device allows a ±0.3-V range on the AIN_nGND
pin for all analog input channels. Use this feature in modular systems where the sensor or signal conditioning
block is further away from the ADC on the board and when a difference in the ground potential of the sensor or
signal conditioner from the ADC ground is possible. In such cases, running separate wires from the AIN_nGND
pin of the device to the sensor or signal conditioning ground is recommended.
8.3.2 Analog Input Impedance
Each analog input channel in the device presents a constant resistive impedance of 1 MΩ. The input impedance
for each channel is independent of either the input signal frequency, the configured range of the ADC, or the
oversampling mode. The primary advantage of such high-impedance inputs is the ease of driving the ADC inputs
without requiring driving amplifiers with low output impedance. Bipolar, high-voltage power supplies are not
required in the system because this ADC does not require any high-voltage, front-end drivers. In most
applications, the signal sources or sensor outputs can be directly connected to the ADC input, thus significantly
simplifying the design of the signal chain.
In order to maintain the dc accuracy of the system, matching the external source impedance on the AIN_nP input
pin with an equivalent resistance on the AIN_nGND pin is recommended (see Figure 54). This matching helps to
cancel any additional offset error contributed by the external resistance.
8.3.3 Input Clamp Protection Circuit
As shown in Figure 52, the ADS8584S features an internal clamp protection circuit on each of the 4 analog input
channels. Use of external protection circuits is recommended as a secondary protection scheme to protect the
device. Using external protection devices helps with protection against surges, electrostatic discharge (ESD), and
electrical fast transient (EFT) conditions.
The input clamp protection circuit on the ADS8584S allows each analog input to swing up to a maximum voltage
of ±15 V. Beyond an input voltage of ±15 V, the input clamp circuit turns on, still operating off the single 5-V
supply. Figure 53 illustrates a typical current versus voltage characteristic curve for the input clamp. There is no
current flow in the clamp circuit for input voltages up to ±15 V. Beyond this voltage, the input clamp circuit turns
on.
26
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Feature Description (continued)
50
40
30
20
10
0
-10
-20
-30
-40
-50
-20
-15
-10
-5
0
5
10
15
20
Input Voltage (V)
D007
Figure 53. I-V Curve for an Input Clamp Protection Circuit (AVDD = 5 V)
For input voltages above the clamp threshold, make sure that input current never exceeds the absolute
maximum rating (see the Absolute Maximum Ratings table) of ±10 mA to prevent any damage to the device.
Figure 54 shows that a small series resistor placed in series with the analog inputs is an effective way to limit the
input current. In addition to limiting the input current, this resistor can also provide an antialiasing, low-pass filter
when coupled with a capacitor. In order to maintain the dc accuracy of the system, matching the external source
impedance on the AIN_nP input pin with an equivalent resistance on the AIN_nGND pin is recommended. This
matching helps to cancel any additional offset error contributed by the external resistance.
1 Mꢀ
1 Mꢀ
R
EXT
EXT
AIN_nP
Clamp
Clamp
Input
Signal
C
PGA
AIN_nGND
R
Figure 54. Matching Input Resistors on the Analog Inputs of Devices
The input overvoltage protection clamp on the ADS8584S is intended to control transient excursions on the input
pins. Leaving the device in a state such that the clamp circuit is activated for extended periods of time in normal
or power-down mode is not recommended because this fault condition can degrade device performance and
reliability.
8.3.4 Programmable Gain Amplifier (PGA)
The device offers a programmable gain amplifier (PGA) at each individual analog input channel that converts the
original single-ended input signal into a fully-differential signal to drive the internal 16-bit ADC. The PGA also
adjusts the common-mode level of the input signal before being fed into the ADC to ensure maximum usage of
the ADC input dynamic range. Depending on the range of the input signal, the PGA gain can be accordingly
adjusted by configuring the RANGE pin of the ADC (see the RANGE (Input) section).
The PGA uses a very highly matched network of resistors for multiple gain configurations. Matching between
these resistors and the amplifiers across all channels is accurately trimmed to keep the overall gain error low
across all channels and input ranges.
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Feature Description (continued)
8.3.5 Third-Order, Low-Pass Filter (LPF)
In order to mitigate the noise of the front-end amplifiers and gain resistors of the PGA, each analog input channel
of the ADS8584S features a third-order, Butterworth, antialiasing, low-pass filter (LPF) at the output of the PGA.
Figure 55 and Figure 56, respectively, show the magnitude and phase response of the analog antialiasing filter.
For maximum performance, the –3-dB cutoff frequency for the antialiasing filter is designed to be equal to 24 kHz
for ±10-V range and 16 kHz for ±5-V range.
30
25
20
15
10
5
0
-2
± 5 V
± 10 V
-4
-6
-8
± 5 V
± 10 V
-10
0
100
1k
10k
100k
1
10
100
1k
10k
100k
Input Frequency (Hz)
Input Frequency (Hz)
D046
D047
Figure 55. Third-Order LPF Magnitude Response
Figure 56. Third-Order LPF Phase Response
8.3.6 ADC Driver
In order to meet the performance of a 16-bit, SAR ADC at the maximum sampling rate (330 kSPS per channel),
the capacitors at the input of the ADC must be successfully charged and discharged during the acquisition time
window. The inputs of the ADC must settle to better than 16-bit accuracy before any sampled analog voltage
gets converted. This drive requirement at the inputs of the ADC necessitates the use of a high-bandwidth, low-
noise, and stable amplifier buffer. The ADS8584S features an integrated input driver as part of the signal chain
for each analog input. This integrated input driver eliminates the need for any external amplifier, thus simplifying
the signal chain design for the user.
8.3.7 Digital Filter and Noise
The ADS8584S features an optional digital averaging filter that can be used in slower throughput applications
requiring lower noise and higher dynamic range. As explained in Table 1, the oversampling ratio of the digital
filter is determined by the configuration of the OS[2:0] pins. The overall throughput of the ADC decreases
proportionally with increase in the oversampling ratio.
Table 1. Oversampling Bit Decoding
SNR
±10-V INPUT
(dB)
SNR
±5-V INPUT
(dB)
3-dB BANDWIDTH
±10-V INPUT
(kHz)
3-dB BANDWIDTH MAX THROUGHPUT
OS
RATIO
OS[2:0]
±5-V INPUT
(kHz)
PER CHANNEL
(kSPS)
000
001
010
011
100
101
110
111
No OS
92.7
93.5
94.5
95.6
96.4
96.8
97.1
—
92.2
92.5
93.4
94.3
95.5
96.4
96.9
—
24
23
16
15.7
14.5
10.6
5.6
330
165
2
4
19.2
11.2
5.6
2.8
1.4
—
82.5
8
41.25
20.625
10.3125
5.156
—
16
32
2.8
64
1.4
Invalid
—
28
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In oversampling mode (see the Oversampling Mode of Operation section), the ADC takes the first sample for
each channel at the rising edge of the CONVSTA, CONVSTB signals. After converting the first sample, the
subsequent samples are taken by an internally generated sampling control signal. The samples are then
averaged to reduce the noise of the signal chain as well as to improve the SNR of the ADC. The final output is
also decimated to provide a 16-bit output for each channel. Table 1 lists the typical SNR performance for both
the ±10-V and ±5-V input ranges, including the –3-dB bandwidth and proportional maximum throughput per
channel. When the oversampling ratio increases, there is a proportional improvement in the SNR performance
and decrease in the bandwidth of the input filter.
8.3.8 Reference
The ADS8584S can operate with either an internal voltage reference or an external voltage reference using an
internal gain amplifier. The internal or external reference selection is determined by an external REFSEL pin, as
explained in the REFSEL (Input) section. The REFIN/REFOUT pin outputs the internal band-gap voltage (in
internal reference mode) or functions as an input to the external reference voltage (in external reference mode).
In both cases, the on-chip amplifier is always enabled. Use this internal amplifier to gain the reference voltage
and drive the actual reference input of the internal ADC core for maximizing performance. The REFCAPA (pin
45) and REFCAPB (pin 44) pins must be shorted together externally and a ceramic capacitor of 10 µF (minimum)
must be connected between this node and REFGND (pin 43) to ensure that the internal reference buffer is
operating as closed loop.
8.3.8.1 Internal Reference
The device has an internal 2.5-V (nominal value) band-gap reference. In order to select the internal reference,
the REFSEL pin must be tied high or connected to DVDD. When the internal reference is used, REFIN/REFOUT
(pin 42) becomes an output pin with the internal reference value. A 10-μF (minimum) decoupling capacitor, as
shown in Figure 57, is recommended to be placed between the REFIN/REFOUT pin and REFGND (pin 43). The
capacitor must be placed as close to the REFIN/REFOUT pin as possible. The output impedance of the internal
band-gap creates a low-pass filter with this capacitor to band-limit the noise of the band-gap output. The use of a
smaller capacitor increases the reference noise in the system, thus degrading SNR and SINAD performance. Do
not use the REFIN/REFOUT pin to drive external ac or dc loads because of the limited current output capability
of the pin. The REFIN/REFOUT pin can be used as a reference source if followed by a suitable op amp buffer.
AVDD
2.5-V VREF
DVDD
REFSEL
REFIN/REFOUT
10 mF
REFCAPB
REFCAPA
10 mF
REFGND
ADC
AGND
Figure 57. Device Connections for Using an Internal 2.5-V Reference
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The device internal reference is factory trimmed to a maximum initial accuracy of ±2.5 mV. The histogram in
Figure 58 shows the distribution of the internal voltage reference output taken from more than 2100 production
devices.
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
-2.5 -2.2 -1.6
-1
-0.4 0.2
0.8
1.4
2
2.5
REFIO Initial Acuuracy (mV)
D048
Figure 58. Internal Reference Accuracy at Room Temperature Histogram
The initial accuracy specification for the internal reference can be degraded if the die is exposed to any
mechanical, thermal, or environmental stress (such as humidity). Heating the device when being soldered to a
printed circuit board (PCB) and any subsequent solder reflow is a primary cause for shifts in the VREF value. The
main cause of thermal hysteresis is a change in die stress and therefore is a function of the package, die-attach
material, and molding compound, as well as the layout of the device itself.
In order to illustrate this effect, 80 devices were soldered using lead-free solder paste with the suggested
manufacturer reflow profile, as explained in the AN-2029 Handling & Process Recommendations application
report. The internal voltage reference output is measured before and after the reflow process and Figure 59
shows the typical shift in value. Although all tested units exhibit a positive shift in the output voltages, negative
shifts are also possible. The histogram in Figure 59 shows the typical shift for exposure to a single reflow profile.
Exposure to multiple reflows, which is common on PCBs with surface-mount components on both sides, causes
additional shifts in the output voltage. If the PCB is to be exposed to multiple reflows, solder the ADS8584S in
the second pass to minimize device exposure to thermal stress.
30
25
20
15
10
5
0
-4
-3
-2
-1
0
1
Error in REFIO Voltage (mV)
C065
Figure 59. Solder Heat Shift Distribution Histogram
The internal reference is also temperature compensated to provide excellent temperature drift over an extended
industrial temperature range of –40°C to 125°C. Figure 60 illustrates the variation of the internal reference
voltage across temperature for different values of the AVDD supply voltage. The typical specified value of the
reference voltage drift over temperature is 7.5 ppm/°C.
30
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2.505
2.503
2.501
2.499
2.497
2.495
AVDD = 4.75 V
AVDD = 5 V
AVDD = 5.25 V
-40
-7
26
59
92
125
Free-Air Temperature (èC)
D049
Figure 60. Variation of Internal Reference Output (REFIN/REFOUT) vs Supply and Temperature
8.3.8.2 External Reference
For applications that require a reference voltage with lower temperature drift or a common reference voltage for
multiple devices, the ADS8584S offers a provision to use an external reference, using the internal buffer to drive
the ADC reference pin. In order to select the external reference mode, either tie the REFSEL pin low or connect
this pin to AGND. In this mode, an external 2.5-V reference must be applied at REFIN/REFOUT (pin 42), which
becomes a high-impedance input pin. Any low-drift, small-size external reference can be used in this mode
because the internal buffer is optimally designed to handle the dynamic loading on the ADC reference input. The
output of the external reference must be filtered to minimize the resulting effect of the reference noise on system
performance. Figure 61 shows a typical connection diagram for this mode.
AVDD
2.5-V VREF
REFSEL
AVDD
REF5025
OUT
(Refer to Device
Datasheet for Detailed Pin
Configuration)
REFIN/REFOUT
CREF
REFCAPB
REFCAPA
10 mF
REFGND
AGND
ADC
Copyright © 2017, Texas Instruments Incorporated
Figure 61. Device Connections for Using an External 2.5-V Reference
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For closed-loop operation of the internal reference buffer, the REFCAPA and REFCAPB pins must be externally
shorted together. The output of the internal reference buffer appears at the REFCAP pin. A minimum
capacitance of 10 μF must be placed between the REFCAPA, REFCAPB pins and REFGND (pin 43). Do not use
this internal reference buffer to drive external ac or dc loads due to it's limited current output capability.
Figure 62 shows that the performance of the internal buffer output is very stable across the entire operating
temperature range of –40°C to +125°C. Figure 63 shows that the typical specified value of the reference buffer
drift over temperature is 5 ppm/°C.
8
7
6
5
4
3
2
1
0
4.01
4.005
4
AVDD = 4.75 V
AVDD = 5 V
AVDD = 5.25 V
3.995
3.99
0
0.665
1.325
1.985
2.645
3.305
4
-40
-7
26
59
92
125
REFCAP Drift (ppm/èC)
Free-Air Temperature (èC)
D052
D051
Number of samples = 30
Figure 63. Reference Buffer Temperature Drift Histogram
Figure 62. Variation of Reference Buffer Output
(REFCAPA, REFCAPB) Across Supply and Temperature
8.3.8.3 Supplying One VREF to Multiple Devices
For applications that require multiple ADS8584S devices, using the same reference voltage source for all the
ADCs helps eliminate any potential errors in the system resulting from mismatch between multiple reference
sources.
Figure 64 shows the recommended connection diagram for an application that uses one device in internal
reference mode and provides the reference source for other devices. The device used as source of the voltage
reference is bypassed by a 10-μF capacitor on the REFIN/REFOUT pin, whereas the other devices are bypassed
with a 100-nF capacitor.
DVDD
TI Device
TI Device
TI Device
REFSEL
REFSEL
REFSEL
AGND
AGND
REFIN/REFOUT
REFIN/REFOUT
REFIN/REFOUT
Configured as Output
Configured as Input
Configured as Input
10 mF
100 nF
100 nF
REFGND
REFGND
Copyright © 2017, Texas Instruments Incorporated
REFGND
Figure 64. Multiple Devices Connected With an Internal Reference From One Device
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Figure 65 shows the recommended connection diagram for an application that uses an external voltage
reference (such as the REF5025) to provide the reference source for multiple devices.
TI Device
TI Device
TI Device
REFSEL
REFSEL
REFSEL
AGND
AGND
AGND
REFIN/REFOUT
REFIN/REFOUT
REFIN/REFOUT
100 nF
REFGND
100 nF
REFGND
100 nF
REFGND
AVDD
REF5025
OUT
(Refer to Device
Datasheet for Detailed
Pin Configuration)
CREF
Copyright © 2017, Texas Instruments Incorporated
Figure 65. Multiple Devices Connected Using an External Reference
8.3.9 ADC Transfer Function
The ADS8584S is a multichannel device that supports two single-ended, bipolar input ranges of ±10 V and ±5 V
on all input channels. The device outputs 16 bits of conversion data in binary twos complement format for both
bipolar input ranges. The format for the output codes is the same across all analog channels.
Figure 66 shows the ideal transfer characteristic for each ADC channel for all input ranges. The full-scale range
(FSR) for each input signal is equal to the difference between the positive full-scale (PFS) input voltage and the
negative full-scale (NFS) input voltage. The LSB size is equal to FSR / 216 = FSR / 65536 because the resolution
of the ADC is 16 bits. Table 2 lists the LSB values corresponding to the different input ranges.
0111 … … 1111
(7FFFh)
0000 … … 0000
(0000h)
PFS œ 1.5 LSB
1000 … … 0000
(8000h)
NFS + 0.5 LSB
0 V œ 0.5 LSB
NFS
PFS
FSR = PFS œ NFS
Analog Input (AIN_nP t AIN_nGND)
Figure 66. 16-Bit ADC Transfer Function (Twos Complement Binary Format)
Table 2. ADC LSB Values for Different Input Ranges
INPUT RANGE (V)
POSITIVE FULL-SCALE (V) NEGATIVE FULL-SCALE (V)
FULL-SCALE RANGE (V)
LSB (µV)
305.18
±10
±5
10
5
–10
–5
20
10
152.59
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8.4 Device Functional Modes
8.4.1 Device Interface: Pin Description
8.4.1.1 REFSEL (Input)
The REFSEL pin is a digital input pin that enables selection between the internal and external reference mode of
operation for the device. If the REFSEL pin is set to logic high, then the internal reference is enabled and
selected. If this pin is set to logic low, then the internal band-gap reference circuit is disabled and powered down.
In this mode, an external reference voltage must be provided to the REFIN/REFOUT pin. Under both conditions,
the internal reference buffer is always enabled.
The REFSEL pin is an asynchronous logic input. The device output on the REFIN/REFOUT pin starts changing
immediately with a change in state of the REFSEL input pin. During power-up, the device wakes up in internal or
external reference mode depending on the state of the REFSEL input pin.
8.4.1.2 RANGE (Input)
The RANGE pin is a digital input pin that allows the input range to be selected for all analog input channels. If
this pin is set to logic high, the device is configured to operate in the ±10-V input range for all input channels. If
this pin is set to logic low, then all input channels operate in the ±5-V input range.
In applications where the input range remains the same for all input channels, the RANGE pin is recommended
to be hardwired to the appropriate signal. However, some applications can require an on-the-fly change in the
input range by the digital host. For such cases, the RANGE pin functions as an asynchronous input, meaning
that any change in the logic input results in an immediate change in the input range configuration of the device.
An additional 80 µs must typically be allowed in addition to the device acquisition time for the internal active
circuitry to settle to the required accuracy before initiating the next conversion.
The RANGE pin is also used to put the device in standby or shutdown mode depending on the state of the STBY
input pin, as explained in the Power-Down Modes section.
8.4.1.3 STBY (Input)
The STBY pin is a digital input pin used to put the device into one of the two power-down modes: standby or shut
down. Set the STBY pin to logic high for normal device operation. If this pin is set to logic low, the device enters
either standby mode or shutdown mode depending on the state of the RANGE input pin. Both of these modes
are low-power modes supported by the device. In shutdown mode, all internal circuitry is powered down, but in
standby mode the internal reference and regulators remain powered to enable a relatively quicker recovery to
normal operation.
The STBY pin functions as an asynchronous input, meaning that this pin can be pulled low at anytime during
device operation to put the device into one of the two power-down modes. However, if the STBY input is set high
to bring the device out of power-down mode, then wait for the specified recovery time, as specified in the Timing
Requirements: Exit Standby Mode table for proper operation. See the Power-Down Modes section for more
details on device operation in the two power-down modes.
8.4.1.4 PAR/SER/BYTE SEL (Input)
The PAR/SER/BYTE SEL pin is a digital input pin that selects between the parallel, serial, or parallel byte
interface for reading the data output from the device. If this pin is tied to logic low, then the device operates in the
parallel interface mode (see the Parallel Data Read section). If this pin is tied to logic high, then the serial or
parallel byte interface mode is selected depending on the state of the DB15/BYTE SEL pin. If the DB15/BYTE
SEL is tied low, then serial mode is selected (see the Serial Data Read section) and the parallel byte interface is
selected if this pin is tied high (see the Parallel Byte Data Read section).
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Device Functional Modes (continued)
8.4.1.5 CONVSTA, CONVSTB (Input)
Conversion start A (CONVSTA) and conversion start B (CONVSTB) are active-high, conversion control digital
input signals. CONVSTA can be used to simultaneously sample and initiate the conversion process for the first
half count of device input channels (channels 1-2 for the ADS8584S), whereas CONVSTB can be used to
simultaneously sample and initiate the conversion process for the latter half count of device input channels
(channels 3-4 for the ADS8584S). For simultaneous sampling of all input channels, both pins can be shorted
together and a single CONVST signal can be used to control the conversion on all input channels. However, in
the oversampling mode of operation (see the Oversampling Mode of Operation section), both the CONVSTA and
CONVSTB signals must be tied together.
On the rising edge of the CONVSTA, CONVSTB signals, the internal track-and-hold circuits for each analog input
channel are placed into hold mode and the sampled input signal is converted using an internal clock. The
CONVSTA, CONVSTB signals can be pulled low when the internal conversion is over, as indicated by the BUSY
signal (see the BUSY (Output) section). At this point, the front-end circuit for all analog input channels acquires
the respective input signals and the internal ADC is not converting. The output data can be read from the device
irrespective of the status of the CONVSTA, CONVSTB pins, as there is no degradation in device performance,
as explained in the Data Read Operation section.
8.4.1.6 RESET (Input)
The RESET pin is an active-high digital input. A dedicated reset pin allows the device to be reset at any time in
an asynchronous manner. All digital circuitry in the device is reset when the RESET pin is set to logic high and
this condition remains active until the pin returns low. The device must always be reset after power-up as well as
after recovery from shut-down mode when all the supplies and references have settled to the required accuracy.
If the RESET is issued during an ongoing conversion process, then the device aborts the conversion and output
data are invalid. If the reset signal is applied during a data read operation, then the output data registers are all
reset to zero.
In order to initiate the next conversion cycle after deactivating a reset condition, allow for a minimum time delay
between the falling edge of the RESET input and the rising edge of the CONVSTA, CONVSTB inputs (see the
Timing Requirements: CONVST Control table). Any violation in this timing requirement can result in corrupting
the results from the next conversion.
8.4.1.7 RD/SCLK (Input)
RD/SCLK is a dual-function pin. Table 3 explains the usage of this pin under different operating conditions of the
device.
Table 3. RD/SCLK Pin Functionality
DEVICE OPERATING CONDITION
FUNCTIONALITY OF THE RD/SCLK INPUT
PAR/SER/BYTE SEL = 0
DB15/BYTE SEL = 0
Functions as an active-low digital input pin to read the output data from the device.
In parallel or parallel byte interface mode, the output bus is enabled when both the
CS and RD inputs are tied to a logic low input (see the Data Read Operation
section).
Parallel interface
PAR/SER/BYTE SEL = 1
DB15/BYTE SEL = 1
Parallel byte interface
Serial interface
Functions as an external clock input for the serial data interface. In serial mode, all
synchronous accesses to the device are timed with respect to the rising edge of
the SCLK signal (see the Serial Data Read section).
PAR/SER/BYTE SEL = 1
DB15/BYTE SEL = 0
8.4.1.8 CS (Input)
The CS pin indicates an active-low, chip-select signal. A rising edge on the CS signal outputs all the data lines in
tri-state mode. This function allows multiple devices to share the same output data lines. The falling edge of the
CS signal marks the beginning of the output data transfer frame in any interface mode of operation for the
device. In the parallel and parallel byte interface modes, both the CS and RD input pins must be driven low to
enable the digital output bus for reading the conversion data (DB[15:0] for parallel and DB[7:0] for parallel byte
interface). In serial mode, the falling edge of the CS signal takes the DOUTA, DOUTB serial data output lines out
of tri-state mode and outputs the MSB of the previous conversion result.
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8.4.1.9 OS[2:0]
The OS[2:0] pins are active-high digital input pins used to configure the oversampling ratio for the internal digital
filter on the device. OS2 is the MSB control bit and OS0 is the LSB control bit. Table 1 provides the decoding of
the OS[2:0] bits for different oversampling rates. As described in Table 1, an increase in the OSR mode improves
the typical SNR performance for both input ranges and reduces the 3-dB input bandwidth as well as the
maximum-allowed throughput per channel.
8.4.1.10 BUSY (Output)
BUSY is an active-high digital output signal. This pin goes to logic high after the rising edges of both the
CONVSTA and CONVSTB signals, indicating that the front-end, track-and-hold circuits for all input channels are
in hold mode and that the ADC conversion has started. When the BUSY signal goes high, any activity on the
CONVSTA or CONVSTB inputs has no effect on the device. The BUSY output remains high until the conversion
process for all channels is completed and the conversion data are latched into the output data registers for read
out. If the conversion data is read for the previous conversion when BUSY is high, ensure that the data read
operation is complete before the falling edge of the BUSY output.
8.4.1.11 FRSTDATA (Output)
FRSTDATA is an active-high digital output signal that indicates if the conversion data output for the first analog
input channel of the ADC (AIN_1P and AIN_1GND) is being read out in either of the interface modes. The
FRSTDATA output pin comes out of tri-state when the CS input is pulled from a high to a low logic level. Table 4
indicates the functionality of the FRSTDATA output in different interface modes of the device.
Table 4. FRSTDATA Pin Functionality
DEVICE OPERATING CONDITION
FUNCTIONALITY OF THE FRSTDATA OUTPUT
The first falling edge of the RD signal corresponding to the output result of channel
1 sets the FRSTDATA output to a logic high level. This setting indicates that the
data output from channel 1 is being read on the parallel output bus (DB[15:0]). The
FRSTDATA output goes low at the next falling edge of the RD signal and remains
low until the conversion data output from all other channels is read.
PAR/SER/BYTE SEL = 0,
DB15/BYTE SEL = 0
Parallel mode
Parallel byte mode
Serial mode
The first falling edge of the RD signal corresponding to one byte of the output of
channel 1 sets the FRSTDATA output to a logic high level. This setting indicates
that one byte of the data output from channel 1 is being read on the parallel output
bus (DB[7:0]). The FRSTDATA output remains high at the next falling edge of the
RD signal to read the second byte of the channel 1 output. This pin goes low on
the third falling edge of the RD signal and remains low until the conversion data
output from all other channels is read.
PAR/SER/BYTE SEL = 1,
DB15/BYTE SEL = 1
The FRSTDATA output goes to a logic high state on the falling edge of the CS
signal when the MSB of the channel 1 conversion result is output on DOUTA at
this instant. The FRSTDATA pin goes low at the 16th falling edge of the SCLK
input, indicating that all 16 bits of the channel 1 output has been read. This pin
remains low until the conversion data output from all other channels is read.
PAR/SER/BYTE SEL = 1,
DB15/BYTE SEL = 0
8.4.1.12 DB15/BYTE SEL
DB15/BYTE SEL is a dual-function, digital input, output pin.
When the device operates in parallel interface mode (PAR/SER/BYTE SEL = 0), this pin functions as a digital
output. In this mode, this pin outputs the MSB of the conversion data when both the CS and RD signals are
pulled low.
When the device does not operate in parallel interface mode (PAR/SER/BYTE SEL = 1), this pin functions as a
digital control input pin to select between the serial and parallel byte interface modes. The device operates in the
serial interface mode when the DB15/BYTE SEL pin is tied low and the device operates in the parallel byte
interface mode when this pin is tied to a logic high input.
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8.4.1.13 DB14/HBEN
DB14/HBEN is a dual-function, digital input, output pin
When the device operates in parallel interface mode (PAR/SER/BYTE SEL = 0), this pin functions as a digital
output. In this mode, this pin outputs the (MSB-1) bit or bit 14 of the conversion data when both the CS and RD
signals are pulled low.
When the device operates in parallel byte interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1),
this pin functions as a digital control input pin that selects if the MSB byte or the LSB byte is output first. If the
DB14/HBEN pin is tied to logic high, then the MSB byte is output first followed by the LSB byte and vice-versa if
this pin is tied to logic low.
When the device operates in serial interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 0), this pin
must be tied to AGND or to a logic low input.
8.4.1.14 DB[13:9]
DB[13:9] are digital output pins. In parallel interface mode (PAR/SER/BYTE SEL = 0), these pins output bit 13 to
bit 9 of the conversion result for each analog channel when both the CS and RD signals are pulled low. When
the device is not in parallel interface mode (PAR/SER/BYTE SEL = 1), these pins must be tied to AGND or to a
logic low input.
8.4.1.15 DB8/DOUTB
DB8/DOUTB is a dual-function digital output pin.
In parallel interface mode (PAR/SER/BYTE SEL = 0), use this pin to output bit 8 of the conversion result for each
analog channel when both the CS and RD signals are pulled low.
When the device operates in parallel byte interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1),
this pin remains in a tri-state mode.
In serial interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 0), this pin outputs the conversion
data for the second half count of device input channels (channels 3-4 for the ADS8584S).
8.4.1.16 DB7/DOUTA
DB7/DOUTA is a dual-function digital output pin.
In parallel interface mode (PAR/SER/BYTE SEL = 0), use this pin to output bit 7 of the conversion result for each
analog channel when both the CS and RD signals are pulled low.
When the device operates in parallel byte interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1),
this pin outputs the MSB of the output byte of the conversion data.
In serial interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 0), use this pin to output conversion
data for the first half count of device input channels (channels 1-2 for the ADS8584S).
8.4.1.17 DB[6:0]
DB[6:0] are digital output pins.
In parallel interface mode (PAR/SER/BYTE SEL = 0), these pins output bit 6 to bit 0 (LSB) of the conversion
result for each analog channel when both the CS and RD signals are pulled low.
When the device operates in parallel byte interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1),
these pins along with the DB7 pin output the 16-bit conversion result in MSB-first fashion in two consecutive RD
operations.
When the device operates in serial interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 0), these
pins must be tied to AGND or to a logic low input.
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8.4.2 Device Modes of Operation
The ADS8584S supports multiple modes of operation that can be programmed using the hardware pins. This
functionality allows the device to be easily configured without any complicated software programming. This
section provides details about the normal, power-down (standby and shutdown), and oversampling modes of
operation of the device.
8.4.2.1 Power-Down Modes
For applications that are sensitive to power consumption, the ADS8584S offers a built-in, power-down feature.
The device supports two power-down modes: standby mode and shutdown mode. As shown in Table 5, the
device can enter either power-down mode by pulling the STBY pin to a logic low level. Additionally, the selection
between these two power-down modes is done by the state of the RANGE pin.
Table 5. Power-Down Mode Selection
POWER-DOWN MODE
Standby
STBY
RANGE
0
0
1
0
Shutdown
8.4.2.1.1 Standby Mode
The device supports a low-power standby mode in which only part of the circuit is powered down. The analog
front-end, signal-conditioning circuit for each channel remains powered down in this mode, but the internal
reference and regulator are not powered down. In standby mode, the total power consumption of the device is
typically equal to 19 mW.
In order to enter standby mode, the STBY input pin must be set to logic low and the RANGE input pin must be
set to a logic high value. The device can be asynchronously put into this mode by configuring the STBY and
RANGE inputs at anytime during device operation.
The device exits standby mode when a logic high input is applied to the STBY pin. At this time, the internal
circuitry starts powering up and takes a minimum time of 100 µs to settle before the next conversion can be
initiated. See the Timing Requirements: Exit Standby Mode table and Figure 8 for timing details.
8.4.2.1.2 Shutdown Mode
The device supports a low-power shutdown mode in which the entire internal circuitry is powered down. In
shutdown mode, the total power consumption of the device is typically equal to 1 µW.
In order to enter shutdown mode, the STBY input pin must be set to logic low and the RANGE input pin must be
set to a logic low value. The device can be asynchronously put into this mode by configuring the STBY and
RANGE inputs at anytime during device operation.
The device exits shutdown mode when a logic high input is applied to the STBY pin. At this time, the internal
circuitry starts powering up and takes a minimum time of 13 ms to settle in external reference mode before the
next conversion can be initiated. After recovery from shutdown mode, a RESET signal must be applied before
the next conversion can be initiated. See the Timing Requirements: Exit Shutdown Mode table and Figure 9 for
timing details.
8.4.2.2 Conversion Control
The ADS8584S offers easy and precise control to simultaneously sample all analog input channels or pairs of
input channels. The sampling instant can be user-controlled through the digital pins, CONVSTA and CONVSTB.
Simultaneously capturing the input signal on all analog input channels is extremely useful in certain applications
that are sensitive to additional phase delay between input channels caused by sequential sampling. This section
describes the methodology to simultaneously sample all input channels or pairs of input channels for the device.
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8.4.2.2.1 Simultaneous Sampling on All Input Channels
The ADS8584S allows all the analog input channels to be simultaneously sampled. In order to do so, the
CONVSTA and CONVSTB signals (as shown in Figure 67) must be tied together and a single CONVST signal
must be used to control the sampling of all analog input channels of the device. Figure 67 also shows the
sequence of events described in this section.
CONVSTA
CONVSTB
BUSY
CS and RD
DB[15:0]
AIN_1
AIN_2
AIN_3
AIN_4
FRSTDATA
1
2
3
4
Figure 67. Simultaneous Sampling of All Input Channels in Parallel Interface Timing Diagram
There are four events that describe the internal operation of the device when all input channels are
simultaneously sampled and the data are read back. These events are:
•
Event 1: Simultaneous sampling of all analog input channels is initiated with the rising edge of the CONVST
signal. The input signals on all channels are sampled at this same instant because both the CONVSTA and
CONVSTB inputs are tied together. The sampled signals are then converted by the ADC using a precise on-
chip oscillator clock. At the beginning of the conversion phase of the ADC, the BUSY output goes high and
remains high through a maximum-specified conversion time of tCONV (see the Timing Requirements: CONVST
Control table).
•
•
Event 2: At this instant, the ADC has completed the conversion for all input channels and the BUSY output
goes to logic low. The falling edge of the BUSY signal indicates end of conversion and that the internal
registers are updated with the conversion data. At this instant, the device is ready to output the correct
conversion results for all channels on the parallel output bus (DB[15:0]), serial output lines (DOUTA, DOUTB),
or parallel byte bus (DB[7:0]).
Event 3: This example shows the data read operation in parallel interface mode with both CS and RD tied
together. After BUSY goes low, the first falling edges of CS and RD output the conversion result of channel 1
(AIN_1) on the parallel output bus. Similarly, the conversion results for the remaining channels are output on
the parallel bus on subsequent falling edges of the CS and RD signals in a sequential manner. If all channels
are not used in the conversion process, tie the unused channels to AGND or any known voltage within the
selected input range. The ADC always converts all analog input channels and the results for unused channels
are included in the output data stream, thus all unused channels must be tied. The FRSTDATA output goes
high on the first falling edges of the CS and RD signals, indicating that the parallel bus is carrying the output
result from channel 1. On the next falling edges of the CS and RD signals, FRSTDATA goes low and stays
low if the CS and RD inputs are low.
•
Event 4: After the conversion results for all analog channels are output from the device, the data frame can
be terminated by pulling the CS and RD signals to logic high. The parallel bus and FRSTDATA output go to
tri-state until the entire sequence is repeated beginning from event 1.
Events 1 and 2 are common to all interface modes of operation (parallel, serial, or parallel byte).
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8.4.2.2.2 Simultaneous Sampling Two Sets of Input Channels
The ADS8584S allows two sets of analog input channels to be simultaneously sampled. In order to do so, the
CONVSTA and CONVSTB signals must be separate control inputs (as shown in Figure 68) and the device must
not operate in any oversampling mode. Electrical grid relay protection is an application that can benefit from
being able to sample the inputs in two groups. The delay of the signal through the voltage channels is often
different from the delay on the channels measuring current. The difference in delay created by the voltage and
current signal paths can be corrected by adjusting the sampling of the two groups of inputs (voltage and current)
to the device.
The timing diagram of Figure 68 shows the sequence of events described in this section.
CONVSTA
CONVSTB
BUSY
CS and RD
AIN_1
AIN_2
AIN_3
AIN_4
DB[15:0]
FRSTDATA
1a
1b
2
3
4
Figure 68. Simultaneous Sampling of All Input Channels in Parallel Interface Timing Diagram
There are four events that describe the internal operation of the device when pairs of input channels are
simultaneously sampled and the data are read back. These events are:
•
Event 1(a): A rising edge on the CONVSTA signal initiates simultaneous sampling of the first set of analog
input channels (channels 1-2 for the ADS8584S). The sampling circuits on the first set of analog input
channels enter hold mode and the input signals on these channels are sampled at the same instant. The
ADC does not begin conversion until the input signals on the second set of channels are sampled.
•
Event 1(b): A rising edge on the CONVSTB signal initiates simultaneous sampling of the second set of
analog input channels (channels 3-4 for the ADS8584S). The sampling circuits for the second set of analog
input channels enter hold mode and the input signals on these channels are sampled at the same instant.
When the rising edges of both the CONVSTA and CONVSTB signals have occurred, the ADC converts all
sampled signals using a precise, on-chip oscillator clock. At the beginning of the conversion phase of the
ADC, the BUSY output goes high and remains high through a maximum-specified conversion time of tCONV
(see the Timing Requirements: CONVST Control table).
•
•
•
Event 2: Same as event 2 in the Simultaneous Sampling on All Input Channels section.
Event 3: Same as event 3 in the Simultaneous Sampling on All Input Channels section.
Event 4: Same as event 4 in the Simultaneous Sampling on All Input Channels section.
Events 1(a), 1(b), and 2 are common to all interface modes of operation (parallel, serial, or parallel byte).
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8.4.2.3 Data Read Operation
The ADS8584S updates the internal data registers with the conversion data for all analog channels at the end of
every conversion phase (when BUSY goes low). As described in the Timing Requirements: Data Read Operation
table, if the output data are read after BUSY goes low, then the device outputs the conversion results for the
current sample. However, if the output data are read when BUSY is high, then the device outputs conversion
results for the previous sample. Under both conditions, the device supports three interface options depending on
the status of the PAR/SER/BYTE SEL and DB15/BYTE SEL pins, as explained in Table 6.
Table 6. Data Read Back Interface Mode Selection
SELECTED INTERFACE MODE
Parallel interface
PAR/SER/BYTE SEL
DB15/BYTE SEL
0
1
1
0
1
0
Parallel byte interface
Serial interface
8.4.2.3.1 Parallel Data Read
The ADS8584S supports a parallel interface mode for reading the device output data using the control inputs (CS
and RD) the parallel output bus (DB[15:0]), and the BUSY indicator. This interface mode is selected by applying
a logic low input on the PAR/SER/BYTE SEL input pin. Depending on the application requirements, the CS and
RD control inputs can be tied together or used as separate control inputs in the parallel interface mode.
For applications that use only one device in the system and does not share the parallel output bus with any other
devices, the CS and RD input signals can be tied together. Alternatively, the CS signal can be permanently tied
low and the RD signal can be used to clock the data out of the device. The timing diagram for this mode of
operation is described in the Timing Requirements: Parallel Data Read Operation, CS and RD Tied Together
table. In this mode the parallel output bus, DB[15:0], is activated (comes out of tri-state) on the falling edge of the
CS/RD signal. At the first falling edge of the CS/RD signal, the output data of channel 1 becomes available on
the parallel bus to be read by the digital host. At this instant the FRSTDATA output also goes high, indicating
channel 1 data are ready to be read back. The output data for the remaining channels are clocked out on the
parallel bus on subsequent falling edges of the CS and RD signal in a sequential manner.
For applications that use multiple devices in the system, the CS and RD input signals must be driven separately.
The timing diagram for this mode of operation is described in the Timing Requirements: Parallel Data Read
Operation, CS and RD Separate table. A falling edge of the CS input can be used to activate the parallel bus for
a particular device in the system. The RD signal clocks the conversion data out of the device. At the first falling
edge of the RD signal, the output data of channel 1 become available on the parallel bus to be read by the digital
host. At this instant the FRSTDATA output also goes, high indicating channel 1 data are ready to be read back.
On subsequent falling edges of the RD signal, the output data for the remaining channels are clocked out on the
parallel bus in a sequential manner. At the second falling edge of the RD signal, the FRSTDATA output goes low
and remains low until going to tri-state at the next rising edge of the CS signal.
8.4.2.3.2 Parallel Byte Data Read
The ADS8584S supports a parallel byte interface mode for reading the device output data using the control
inputs (CS and RD) the parallel output bus (DB[15:0]), and the BUSY indicator. This interface mode is selected
by applying a logic high input on the PAR/SER/BYTE SEL input pin and a logic high input on the DB15/BYTE
SEL input pin. The parallel byte interface mode is very similar to the parallel interface mode, except that the
output data for each channel is read in two data transfers of 8-bit byte sizes.
The order of most significant byte (MSB byte) and least significant byte (LSB byte) is decided by the logic input
state of the DB14/HBEN pin. In parallel byte mode, the DB14/HBEN pin functions as a control input. When
DB14/HBEN pin is tied high, the MSB byte of the conversion results is output first followed by the LSB byte. This
order is reversed when DB14/HBEN is tied to logic low.
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The Timing Requirements: Byte Mode Data Read Operation table describes the data read back operation during
parallel byte mode when the DB14/HBEN pin is tied high. A falling edge of the CS input is used to activate the
parallel bus, DB[7:0] for the device. The RD signal is then used to clock the conversion data out of the device. In
this mode, two RD pulses are required to read the full data output for each analog channel. At the first falling
edge of the RD signal, the first byte of the channel 1 conversion result becomes available on DB[7:0]. This byte
is followed by the second byte of conversion data on the next falling edge of the RD signal. On subsequent
falling edges of the RD signal, the output data for the remaining channels are clocked out in chunks of 8-bit bytes
on DB[7:0] in a sequential manner. Thus, a total of 8 RD pulses are required to read the output from all input
channels of the ADS8584S.
In this mode, the FRSTDATA output goes high at the first falling of the RD signal. FRSTDATA remains high for
two RD pulses until both bytes of the channel 1 conversion result are output. At the third falling edge of the RD
signal, the FRSTDATA output goes low and remains low throughout the data read operation until going to tri-
state at the next rising edge of the CS signal.
8.4.2.3.3 Serial Data Read
The ADS8584S also supports a serial interface mode for reading the device output data. This interface mode is
selected by applying a logic high input on the PAR/SER/BYTE SEL input pin and a logic low input on the
DB15/BYTE SEL input pin. This interface mode uses a CS control input, a communication clock input (SCLK),
BUSY and FRSTDATA output indicators, and serial data output lines DOUTA and DOUTB.
Figure 5 illustrates the timing diagram for data read in serial mode for one channel of the ADC, framed by the CS
signal. When the CS input is high, the serial data output and FRSTDATA output lines are in tri-state and the
SCLK input is ignored. On the falling edge of the CS signal, the output lines become active and the MSB of the
conversion result comes out on DOUTA, DOUTB. The MSB can be read by the host processor on the next falling
edge of the SCLK signal. The remaining 15 bits of the conversion result are output on the subsequent rising
edges of the SCLK signal and can be read by the host processor on the corresponding falling edges. Thus, a
total of 16 SCLK cycles are required to clock out 16 bits of conversion result for each channel and the same
process can be repeated for the remaining channels in an ascending order. The CS input can be left at a logic
low level for the entire data retrieval process for all analog channels or used to frame the retrieval of the 16-bit
output data for each analog channel.
The ADS8584S can output the conversion results on one or both of the serial data output lines, DOUTA and
DOUTB. The conversion results from the first set of channels (channels 1-2 for the ADS8584S) appear first on
DOUTA, followed by the second set of channels (channels 3-4 for the ADS8584S) if only DOUTA is used for
reading data. This order is reversed for DOUTB, in which the second set of channels appear first followed by the
first set of channels. The use of both data output lines reduces the time needed for data retrieval and a higher
throughput can therefore be achieved in this mode.
The FRSTDATA output is in tri-state when the CS signal is high. As illustrated in Figure 5, FRSTDATA goes high
on the first falling edge of the CS signal when the MSB of channel 1 is output on DOUTA. The FRSTDATA
output remains high for the next 16 SCLK cycles until all data bits of channel 1 are read from the device. The
FRSTDATA output returns to a logic low level at the 16th falling edge of the SCLK signal. If data are also read on
DOUTB in the serial mode, then FRSTDATA remains high when the first channel of the second set of channels
is read from the device. The high state of FRSTDATA corresponds to channel 3 for the ADS8584S.
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Based on the previous description of the different pins in serial interface mode, conversion data can be read out
of the device in several different ways. Some example recommendations are provided as follows:
•
The conversion data can be read out of the device using only one of the two serial output lines, DOUTA or
DOUTB. In this case, using DOUTA for output data read back is recommended because channel 1 data
appear first on DOUTA followed by the data for other channels in ascending order. To read the data for all
channels, provide a total of 16 × 4 = 64 SCLK cycles for the ADS8584S. This entire data frame can be
created within a single CS pulse or each group of 16 SCLK cycles can be individually framed by the CS
signal. The primary disadvantage of using just one data line for reading conversion data is that the throughput
is reduced if a data read operation is performed after conversion. Figure 69 shows this operation.
•
Alternatively, only DOUTB can be used for reading the conversion data from all channels. In this case,
everything else remains the same and the output bit stream contains data for all channels in the following
order: channels 3, 4, 1, and 2 for the ADS8584S. Figure 69 shows this operation.
CS
SCLK
Channel 1
Channel 3
Channel 2
Channel 4
Channel 3
Channel 1
Channel 4
Channel 2
DOUTA
DOUTB
FRSTDATA
Figure 69. Data Read Back in the Serial Interface Using Either DOUTA or DOUTB Timing Diagram
•
In order to minimize the time for the data read operation in serial mode, both DOUTA and DOUTB can be
used to read data out of the device. In this case, the conversion results from the first set of channels
(channels 1-2 for the ADS8584S) appear on DOUTA and the conversion results from the second set of
channels (channels 3-4 for the ADS8584S) appear first on DOUTB. To read the data for all channels, provide
a total of 16 × 2 = 32 SCLK cycles for the ADS8584S. This entire data frame can be created within a single
CS pulse or each group of 16 SCLK cycles can be individually framed by the CS signal. Figure 70 shows an
example timing diagram.
CS
SCLK
DOUTA
Channel 1
Channel 3
Channel 2
Channel 4
DOUTB
FRSTDATA
Figure 70. Data Read Back in the Serial Interface Using Both DOUTA and DOUTB Timing Diagram
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8.4.2.3.4 Data Read During Conversion
The ADS8584S supports data read operation when the BUSY output is high and the internal ADC is converting.
The ADC outputs conversion results for previous samples if data read back is performed during an ongoing
conversion. Any of the three interface modes (parallel, parallel byte, or serial) in any combination of oversampling
modes can be used to read the device output during an ongoing conversion. The data read back during
conversion mode allows faster throughput to be achieved from the device. There is no degradation in
performance if the data is read from the device during the conversion process, using any of the three interface
modes.
The Timing Requirements: Data Read Operation table describes the timing diagram for data read back during
conversion. The timing specification tDZ_CSBSY (the delay between the rising edge of the CS signal and the falling
edge of the BUSY signal) must be met because the output data registers are updated with the current conversion
results just before the falling edge of the BUSY signal and any read operation during this time can corrupt the
register update.
8.4.2.4 Oversampling Mode of Operation
The ADS8584S supports the oversampling mode of operation using an on-chip averaging digital filter, as
explained in the Digital Filter and Noise section. The device can be configured in oversampling mode by the
OS[2:0] pins (see the OS[2:0] section). Figure 71 shows a typical timing diagram for the oversampling mode of
operation. The input on the OS pins is latched on the falling edge of the BUSY signal to configure the
oversampling rate for the next conversion.
tCONV
CONVSTA,
CONVSTB
11 µs
5 µs
2 µs
OS = OS = OS =
BUSY
0
2
4
CS, RD
DB[15:0]
AIN_1
AIN_2
AIN_3
AIN_4
Figure 71. OSR Mode Operation Timing Diagram
In the oversampling mode of operation, both the CONVST A and CONVST B signals must be tied together or
driven together. As shown in Figure 71, the BUSY signal duration varies with the OSR setting because the
conversion time increases with increases in OSR, The high time for the BUSY signal increases with the OSR
setting, as listed in the Timing Requirements: CONVST Control table.
For any particular OSR setting, the maximum achievable throughput per channel is specified in Table 1. If the
application is running at a lower throughput, then a higher OSR setting can be selected for further noise
reduction and SNR improvement. To maximize the throughput per channel, perform a data read when BUSY is
high and a conversion is ongoing in OSR mode. This process enables data read for the previous conversion (see
the Data Read During Conversion section). At the falling edge of the BUSY signal, the internal data registers are
updated with the new conversion data; thus the read operation must complete and CS must be pulled high for at
least tSU_CSBSY before BUSY goes low (see the Timing Requirements: Data Read Operation table).
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Oversampling the input signal reduces noise during the conversion process, thus reducing the histogram code
spread for a dc input signal to the ADC. Figure 72 to Figure 77 show the effect of oversampling on the output
code spread in a dc histogram plot.
1200
1000
800
600
400
200
0
1400
1200
1000
800
600
400
200
0
-4
-3
-3
-3
-2
-1
0
1
2
3
3
-3
-3
-3
-2
-1
0
1
2
3
3
3
Output Codes
Output Codes
D062
D064
D066
D063
D065
D067
Mean = –0.52, sigma = 0.47
Figure 72. DC Histogram for OSR2
Mean = –0.33, sigma = 0.41
Figure 73. DC Histogram for OSR4
1200
1000
800
600
400
200
0
1750
1500
1250
1000
750
500
250
0
-2
-1
0
1
2
-2
-1
0
1
2
Output Codes
Output Codes
Mean = –0.49, sigma = 0.36
Figure 74. DC Histogram for OSR8
Mean = –0.16, sigma = 0.33
Figure 75. DC Histogram for OSR16
2000
1750
1500
1250
1000
750
2000
1750
1500
1250
1000
750
500
500
250
250
0
0
-2
-1
0
1
2
-2
-1
0
1
2
Output Codes
Output Codes
Mean = –0.11, sigma = 0.32
Figure 76. DC Histogram for OSR32
Mean = –0.03, sigma = 0.31
Figure 77. DC Histogram for OSR64
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In OSR modes, the device adds a digital filter at the output of the ADC. The digital filter affects the frequency
response of the entire data acquisition system including the internal low-pass analog filter and the oversampling
digital filter. Figure 78 to Figure 83 show the frequency response curves for different OSR settings in the ±10-V
range.
50
0
50
0
-50
-50
-100
-150
-200
-250
-100
-150
-200
-250
1
10
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
D068
D069
AVDD = 5 V, DVDD = 5 V, TA = 25°C, input range = ±10 V
AVDD = 5 V, DVDD = 5 V, TA = 25°C, input range = ±10 V
Figure 78. Digital Filter Response for OSR = 2
Figure 79. Digital Filter Response for OSR = 4
50
50
0
-50
0
-50
-100
-150
-200
-250
-100
-150
-200
-250
1
10
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
D070
D071
AVDD = 5 V, DVDD = 5 V, TA = 25°C, input range = ±10 V
AVDD = 5 V, DVDD = 5 V, TA = 25°C, input range = ±10 V
Figure 80. Digital Filter Response for OSR = 8
Figure 81. Digital Filter Response for OSR = 16
50
50
0
-50
0
-50
-100
-150
-200
-250
-100
-150
-200
-250
1
10
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
D072
D073
AVDD = 5 V, DVDD = 5 V, TA = 25°C, input range = ±10 V
AVDD = 5 V, DVDD = 5 V, TA = 25°C, input range = ±10 V
Figure 82. Digital Filter Response for OSR = 32
Figure 83. Digital Filter Response for OSR = 64
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ADS8584S enables high-precision measurement of up to four analog signals simultaneously. The device is
a fully-integrated data acquisition system based on a 16-bit data acquisition (DAQ) system based on a 16-bit
successive approximation (SAR) analog-to-digital converter (ADC). The device includes an integrated analog
front-end for each input channel and an integrated voltage reference with a precision reference buffer. As such,
this device does not require any additional active circuits for driving the reference analog input pins of the ADC.
9.2 Typical Application
9.2.1 4-Channel, Data Acquisition System (DAQ) for Power Automation
PT Input
CT Input
±10-V Amplitude
f = 50 Hz, 60 Hz
∆ꢀ
∆ꢀ = Measured Phase Difference
Between Signals
AVDD = 5 V(1)
DVDD = 3.3 V
1µF
0.1µF
0.1µF
REGCAP1, REGCAP2(2)
AVDD
DVDD
R1P
AIN_1P
1 MW
ADS8584S
16-Bit
SAR
ADC
3rd-Order
LPF
PGA
C1
REFCAPA
1 MW
AIN_1GND
R1M
10 µF
REFCAPB
REFGND
REFIN/REFOUT
2.5-V
VREF
10 µF
R4P
AIN_4P
1 MW
REFGND
DVDD
16-Bit
SAR
ADC
3rd-Order
LPF
PGA
C4
1 MW
AIN_4GND
R4M
REFSEL
AGND
Copyright © 2017, Texas Instruments Incorporated
Typical 50-Hz, 60-Hz
Sine-Wave from PT, CT
Balanced RC Filter
on Each Input
(1) Decoupling the AVDD capacitor applies to each AVDD pin.
(2) REGCAP1 and REGCAP2: each pin requires separate decoupling capacitors.
(3) PT: Potential transformer.
(4) CT: Current transformer.
Figure 84. 4-Channel DAQ for Power Automation Using the ADS8584S
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Typical Application (continued)
This application example involves the measurement of electrical variables in a power system. The accurate
measurement of electrical variables in a power grid is extremely critical because this measurement helps to
determine the operating status and running quality of the grid. Such accurate measurements also help to
diagnose potential problems with the power network so that these problems can be resolved quickly without
having any significant service impact. The key electrical parameters include amplitude, frequency, and phase
measurement of the voltage and current on the power lines. These parameters are important to enable metrology
in the power automation system to perform harmonic analysis, power factor calculation, power quality
assessment, and so forth.
9.2.1.1 Design Requirements
To begin the design process, a few parameters must be decided upon. The designer must know the following:
•
•
•
•
•
•
Output range of the potential transformers (elements labeled PT in Figure 84)
Output range of the current transformers (elements labeled CT in Figure 84)
Input impedance required from the analog front-end for each channel
Fundamental frequency of the power system
Number of harmonics that must be acquired
Type of signal conditioning required from the analog front end for each channel
9.2.1.2 Detailed Design Procedure
For the ADS8584S, each channel incorporates an analog front end composed of a programmable gain amplifier
(PGA), analog low-pass filter, and ADC input driver. The analog input for each channel presents a constant
resistive impedance of 1 MΩ independent of the ADC sampling frequency and range setting. The high input
impedance of the analog front end circuit allows direct connection to potential transformers (PT) and current
transformers (CT). The ADC inputs can support up to ±10-V or ± 5-V bipolar inputs and the integrated signal
conditioning eliminates the need for external amplifiers or ADC driver circuits.
The PT and CT used in the system, as illustrated in Figure 84, have a ±10-V output range. Although the PT and
CT provide isolation from the power system, a series resistor must be placed on the analog input channels. The
series resistor helps limit the input current to ±10 mA if the input voltages exceed ±15 V. For applications that
require protection against overvoltage or fast transient events beyond the specified absolute maximum ratings of
the device, an external protection clamp circuit using transient voltage suppressors (TVS) and ESD diodes is
recommended.
A low-pass filter is used on each analog input channel to eliminate high-frequency noise pickup and minimize
aliasing. Figure 85 shows an example of the recommended configuration for an input RC filter. A balanced RC
filter configuration matches the external source resistance on the positive path (AIN_nP) with an equal resistance
on the negative path (AIN_nGND). Matching the source impedance in the positive and negative path allows for
better common-mode noise rejection and helps in maintaining the DC accuracy of the system by canceling any
additional offset error contributed by the external series resistance.
10 V
0 V
ADS8584S
ESD
-10 V
1 MW
4.3 kΩ
4.3 kΩ
AIN_nP
16-Bit
SAR
ADC
5.6 nF
COG
3rd-Order
LPF
PGA
AIN_nGND
1 MW
Low-Pass Filter with
Matched Source
Resistance
Signal from PT, CT
50 Hz, 60 Hz
ESD
Copyright © 2017, Texas Instruments Incorporated
Figure 85. Input RC Low-Pass Filter
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Typical Application (continued)
The primary goal of the data acquisition system illustrated in Figure 84 is to measure up to 20 harmonics in a 60-
Hz power network. Thus, the analog front-end must have sufficient bandwidth to detect signals up to 1260 Hz, as
shown in Equation 1.
fMIN
=
20 +1 ì60Hz =1260Hz
(1)
Based on the bandwidth calculated in Equation 1, the ADS8584S is set to simultaneously sample all four
channels at 20 kSPS, which is sufficient throughput to clearly resolve the highest harmonic component of the
input signal. The pass band of the low-pass filter configuration shown in Figure 85 is determined by the –3-dB
frequency, calculated according to Equation 2.
1
1
f-3dB
=
=
= 3.3kHz
2pì
R1+R2
ìCf 2pì
4.3kW + 4.3kW ì5.6nF
(2)
The value of CF is selected as 5.6 nF, a standard capacitance value available in 0603-size surface-mount
components. In combination with the resistor RF, this low-pass filter provides sufficient bandwidth to
accommodate the required 20 harmonics for the input signal of 60 Hz.
The ADS8584S can operate with either the internal voltage reference or an external reference. The Internal
Reference section describes the electrical connections and recommended bypass capacitors when using the
internal reference. Alternatively for applications that require a higher precision voltage reference, Figure 86
shows an example of an external reference circuit. The REF5025 provides a very low drift, and very accurate
external 2.5-V reference. The resistor RFILT and capacitor CFILT form a low-pass filter to reduce the broadband
noise and minimize the resulting effect of the reference noise on the system performance.
AVDD = 5 V
RFILT
VIN
VREF
REFIN/REFOUT
100 ꢀ
CFILT
1 µF
REF5025
10 µF
0.220 ꢀ
REFCAPA
REFCAPB
TRIM/NR
GND
10 µF
10 µF
REFGND
AGND
REFSEL
Copyright © 2017, Texas Instruments Incorporated
Figure 86. External Reference Circuit for the ADS8584S
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Typical Application (continued)
9.2.1.3 Application Curve
Figure 87 shows the frequency spectrum of the data acquired by the ADS8584S for a sinusoidal, ±10-V input at
60 Hz.
The ac performance parameters measured by this design are:
•
•
SNR = 92.75 dB; SINAD = 92.6 dB
THD = –107 dB; SFDR = 110.7 dB
Figure 87. Frequency Spectrum for a Sinusoidal ±10-V Signal at 50 Hz
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10 Power Supply Recommendations
The ADS8584S uses two separate power supplies: AVDD and DVDD. The AVDD supply provides power to the
ADC and internal circuits, and DVDD is used for the digital interface. AVDD and DVDD can be set independently
to voltages within the permissible range.
The AVDD supply can be set in the range of 4.75 V to 5.25 V. A low-noise, linear regulator is recommended to
generate the analog supply voltage. The device has four AVDD pins. Each AVDD pin must be decoupled with
respect to AGND using a 1-µF capacitor. Place the 1-µF capacitor as close to the supply pins as possible.
The DVDD supply is used to drive the digital I/O buffers and can be set in the range of 2.3 V to a maximum value
equal to the AVDD voltage. This range allows the device to interface with most state-of-the-art processors and
controllers. Place a 1-µF (minimum 100-nF) decoupling capacitor in close proximity to the DVDD supply to
provide the high-frequency digital switching current.
There are no specific requirements with regard to the power-supply sequencing of the device. However, issue a
reset after the supplies are powered up and are stable to ensure the device is properly configured.
The typical PSRR curve with the decoupling capacitors is as shown in Figure 88.
-70
± 5 V
± 10 V
-80
-90
-100
-110
-120
-130
-140
-150
1
10
100
Input Frequency (kHz)
D044
Figure 88. PSRR Across Frequency (With Decoupling Capacitor)
Copyright © 2017, Texas Instruments Incorporated
51
ADS8584S
ZHCSG85A –APRIL 2017–REVISED APRIL 2017
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
Figure 89 and Figure 90 illustrate a PCB layout example for the ADS8584S.
•
Partition the PCB into analog and digital sections. Care must be taken to ensure that the analog signals are
kept away from the digital lines. This layout helps keep the analog input and reference input signals away
from the digital noise. In this layout example, the analog input and reference signals are routed on the left
side of the board and the digital connections are routed on the right side of the board.
•
•
Using a single common ground plane is strongly recommended. For designs requiring a split analog and
digital ground planes, the analog and digital ground planes must be at the same potential joined together in
close proximity to the device.
Power sources to the ADS8584S must be clean and well-bypassed. As a result of dynamic currents during
conversion, each AVDD must have a decoupling capacitor to keep the supply voltage stable. Use wide traces
or a dedicated analog supply plane to minimize trace inductance and reduce glitches. Using a 1-μF, X7R-
grade, 0603-size ceramic capacitor is recommended in close proximity to each analog (AVDD) supply pins.
Bypass capacitors for AVDD pins 1 and 48 are located on the top layer; see Figure 89. AVDD supply pins 37
and 38 are connected to bypass capacitors in the bottom layer using an isolated via (1); see Figure 90. A
separate via (2) is used to connect the bypass capacitor to the AVDD plane.
•
•
For decoupling the digital (DVDD) supply pin, a 1-μF, X7R-grade, 0603-size ceramic capacitor is
recommended. The DVDD bypass capacitor is located in the bottom layer; see Figure 90.
REFCAPA and REFCAPB must be shorted together and decoupled to REFGND using a 10-μF, X7R-grade,
0603-size ceramic capacitor placed in close proximity to the pins of the device. This capacitor is placed on
the top layer and directly connected to the pins of the device. Avoid placing vias between the REFCAPA,
REFCAPB pins and the decoupling capacitor.
•
The REFIN/REFOUT pin also must be decoupled to REFGND with a 10-μF, X7R-grade, 0603-size ceramic
capacitor if the internal reference of the device is used. The capacitor must be placed on the top layer in
close to the device pin. Avoid placing vias between the REFIN/REFOUT pin and the decoupling capacitor.
•
•
•
The REGCAP1 and REGCAP2 pins must be decoupled to GND using a separate 1-μF, X7R-grade, 0603-size
ceramic capacitor on each pin.
All ground pins (AGND) must be connected to the ground plane using short, low-impedance paths and
independent vias to the ground plane. Connect REFGND to the common GND plane.
For the optional channel input low-pass filters, ceramic surface-mount capacitors, COG (NPO) ceramic
capacitors provide the best capacitance precision. The type of dielectric used in COG (NPO) ceramic
capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes.
11.2 Layout Example
Figure 89 and Figure 90 illustrate a recommended layout for the ADS8584S along with proper decoupling and
reference capacitor placement and connections.
52
Copyright © 2017, Texas Instruments Incorporated
ADS8584S
www.ti.com.cn
ZHCSG85A –APRIL 2017–REVISED APRIL 2017
Layout Example (continued)
!ë55 ꢀlane
5ë55 ꢀlane
AIN_1P
AIN_1GND
AIN_2P
GND
AGND AGND
AGND
AIN_2GND
AGND
Lsolated
ëia (1)
AVDD (2)
AGND
AGND
5igital
Lnputs and
hutputs
AGND
DVDD (2)
AIN_3P
AIN_3GND
AIN_4P
5ë55
5ë55
AIN_4GND
Lsolated
ëia
AGND
AVDD
AGND
Figure 89. Top Layer Layout
GND
GND
AVDD
AVDD
!ë55 tlane
5ë55 tlane
AVDD (2)
Lsolaꢀed
ëia (1)
DVDD
AGND
AGND
AGND
Lsolaꢀed
ëia
AGND
Figure 90. Bottom Layer Layout
版权 © 2017, Texas Instruments Incorporated
53
ADS8584S
ZHCSG85A –APRIL 2017–REVISED APRIL 2017
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档:
•
•
•
具有关断功能的 OPAx320 高精度 20MHz、0.9pA、低噪声、RRIO、CMOS 运算放大器
AN-2029 操作和处理相关建议应用报告
《REF50xx 低噪声、极低漂移、高精度电压基准》
12.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。请单击右上角的通知我进行注册,即可收到任意产品
信息更改每周摘要。有关更改的详细信息,请查看任意已修订文档中包含的修订历史记录。
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时,我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本,请参见左侧的导航栏。
54
版权 © 2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS8584SIPM
ACTIVE
ACTIVE
LQFP
LQFP
PM
PM
64
64
160
RoHS & Green
NIPDAU-DCC
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
ADS8584S
ADS8584S
ADS8584SIPMR
1000 RoHS & Green
NIPDAU-DCC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS8584SIPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
LQFP PM 64
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
ADS8584SIPMR
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2022
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
ADS8584SIPM
PM
LQFP
64
160
8 X 20
150
315 135.9 7620 15.2
13.1
13
Pack Materials-Page 3
PACKAGE OUTLINE
PM0064A
LQFP - 1.6 mm max height
SCALE 1.400
PLASTIC QUAD FLATPACK
10.2
9.8
B
NOTE 3
64
49
PIN 1 ID
1
48
10.2
9.8
12.2
TYP
11.8
NOTE 3
33
16
32
17
A
0.27
0.17
64X
60X 0.5
4X 7.5
0.08
C A B
C
(0.13) TYP
SEATING PLANE
0.08
SEE DETAIL A
0.25
GAGE PLANE
(1.4)
1.6 MAX
0.05 MIN
0.75
0.45
0 -7
DETAIL
SCALE: 14
A
DETAIL A
TYPICAL
4215162/A 03/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MS-026.
www.ti.com
EXAMPLE BOARD LAYOUT
PM0064A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
49
64
64X (1.5)
1
48
64X (0.3)
SYMM
(11.4)
60X (0.5)
(R0.05) TYP
33
16
17
32
(11.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
0.05 MAX
ALL AROUND
EXPOSED METAL
METAL
0.05 MIN
ALL AROUND
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4215162/A 03/2017
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).
www.ti.com
EXAMPLE STENCIL DESIGN
PM0064A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
64
49
64X (1.5)
1
48
64X (0.3)
SYMM
(11.4)
60X (0.5)
(R0.05) TYP
16
33
17
32
(11.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:8X
4215162/A 03/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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