ADS8598S_技术文档

Support &

Community

Product

Folder

Order

Now

Tools &

Software

Technical

Documents

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

在单电源上具有双极性输入的 ADS8598S 18 位、

200kSPS、8 通道、同步采样 ADC

1 特性

3 说明

1

•

具有集成模拟前端的 18 位 ADC

ADS8598S 器件是一款基于 18 位逐次逼近型 (SAR)

模数转换器 (ADC) 的 8 通道集成数据采集 (DAQ) 系

统。所有输入通道均同时采样，以实现每通道

200kSPS 的最大吞吐量。该器件的每个通道都有一

个完整的模拟前端 (AFE)，其中包含输入阻抗高达

1MΩ 的可编程增益放大器 (PGA)、输入钳位、低通滤

波器和 ADC 输入驱动器。此外，该器件还具有带缓

冲器的低漂移、高精度基准电压，以用于驱动 ADC。

凭借灵活的数字接口，该器件支持串行、并行和并行字

节通信，适用于各种主机控制器。

同步采样：8 通道

可通过引脚编程设定的双极输入：±10V 和 ±5V

高输入阻抗：1MΩ

5V 模拟电源：2.3V 到 5V I/O 电源

9kV 静电放电 (ESD) 过压输入钳位

低温漂片上基准 (2.5V) 和缓冲器

出色的性能：

–

所有通道上的最大吞吐量为 200kSPS

DNL：±0.5LSB（典型值）；INL：±2.0LSB

（典型值）

ADS8598S 采用单一 5V 电源，并且可配置为接受

±10V 或 ±5V 真正双极输入。高输入阻抗特性允许直连

传感器和变压器，因此无需使用外部驱动器电路。此器

件能够实现高性能、高精度以及零延迟转换，因此

ADS8598S 同样非常适用于工业自动化和控制应用。

–

SNR：94dB（典型值）；THD：−109dB（典型

值）

•

过热性能：

–

最大偏移漂移：3ppm/°C

增益漂移：6ppm/°C

•

用于过采样的片上数字滤波器

灵活的并行、字节和串行接口

温度范围：-40°C 至 +125°C

封装：薄型四方扁平 (LQFP)-64

器件信息⁽¹⁾

器件型号

封装

封装尺寸（标称值）

ADS8598S

LQFP (64)

10.00mm x 10.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

•

电网监控

保护中继器

多相电机控制

工业自动化和控制

多通道数据采集系统

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBAS827

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

简化框图

DVDD

AVDD

BUSY

ADS8598S

FRSTDATA

STBY

1 MW

CONVSTA, CONVSTB

RESET

AIN_1P

Clamp

18-Bit

SAR

ADC

3rd-Order

LPF

ADC

Driver

PGA

AIN_1GND

Clamp

RANGE

1 MW

CS

1 MW

RD / SCLK

18-Bit

SAR

ADC

AIN_2P

Clamp

3rd-Order

LPF

ADC

Driver

SAR

Logic

and

PAR/SER

DB[15:0]

AIN_2GND

SER/PAR

Interface

Clamp

1 MW

Digital Control

DOUTA

DOUTB

OS0

OS1

OS2

Digital Filter

1 MW

AIN_7P

18-Bit

SAR

ADC

Clamp

3rd-Order

LPF

ADC

Driver

REFCAPA

PGA

AIN_7GND

Clamp

1 MW

REFCAPB

1 MW

18-Bit

SAR

ADC

AIN_8P

Clamp

3rd-Order

LPF

ADC

Driver

AIN_8GND

Clamp

REFIN/REFOUT

REFSEL

2.5 V_REF

1 MW

AGND

REFGND

2

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

6.17 Switching Characteristics: Parallel Data Read

Operation, CS and RD Separate ............................. 14

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 6

6.1 Absolute Maximum Ratings ...................................... 6

6.2 ESD Ratings.............................................................. 6

6.3 Recommended Operating Conditions....................... 7

6.4 Thermal Information.................................................. 7

6.5 Electrical Characteristics........................................... 8

6.6 Timing Requirements: CONVST Control ................ 11

6.7 Timing Requirements: Data Read Operation.......... 11

6.18 Switching Characteristics: Serial Data Read

Operation ................................................................. 14

6.19 Switching Characteristics: Byte Mode Data Read

Operation ................................................................. 15

6.20 Typical Characteristics.......................................... 19

Detailed Description ............................................ 26

7.1 Overview ................................................................. 26

7.2 Functional Block Diagram ....................................... 26

7.3 Feature Description................................................. 27

7.4 Device Functional Modes........................................ 36

Application and Implementation ........................ 49

8.1 Application Information............................................ 49

8.2 Typical Applications ................................................ 49

Power Supply Recommendations...................... 54

7

8

9

6.8 Timing Requirements: Parallel Data Read Operation,

CS and RD Tied Together ....................................... 11

6.9 Timing Requirements: Parallel Data Read Operation,

CS and RD Separate ............................................... 12

10 Layout................................................................... 55

10.1 Layout Guidelines ................................................. 55

10.2 Layout Example .................................................... 55

11 器件和文档支持 ..................................................... 57

11.1 文档支持................................................................ 57

11.2 接收文档更新通知 ................................................. 57

11.3 社区资源................................................................ 57

11.4 商标....................................................................... 57

11.5 静电放电警告......................................................... 57

11.6 Glossary................................................................ 57

12 机械、封装和可订购信息....................................... 57

6.10 Timing Requirements: Serial Data Read

Operation ................................................................. 12

6.11 Timing Requirements: Byte Mode Data Read

Operation ................................................................. 12

6.12 Timing Requirements: Oversampling Mode.......... 12

6.13 Timing Requirements: Exit Standby Mode............ 12

6.14 Timing Requirements: Exit Shutdown Mode......... 13

6.15 Switching Characteristics: CONVST Control ........ 13

6.16 Switching Characteristics: Parallel Data Read

Operation, CS and RD Tied Together ..................... 13

4 修订历史记录

日期

修订版本

说明

2017 年 9 月

*

初始发行版。

3

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

5 Pin Configuration and Functions

PM Package

64-Pin LQFP

Top View

AVDD

AGND

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

AVDD

2

AGND

OS0

3

REFGND

REFCAPB

REFCAPA

REFGND

REFIN/REFOUT

AGND

OS1

4

OS2

5

PAR/SER/BYTE_SEL

STBY

6

7

RANGE

8

CONVSTA

CONVSTB

RESET

9

AGND

10

11

12

13

14

15

16

REGCAP2

AVDD

RD/SCLK

CS

AVDD

REGCAP1

AGND

BUSY

FRSTDATA

DB0

REFSEL

DB15/BYTE_SEL

Not to scale

Pin Functions

TYPE DESCRIPTION

NAME

NO.

2, 26, 35, 40,

41, 47

AGND

P

Analog ground pin.

AIN_1GND

AIN_1P

50

49

52

51

54

53

AI

Analog input channel 1: negative input.

Analog input channel 1: positive input.

Analog input channel 2: negative input.

Analog input channel 2: positive input.

Analog input channel 3: negative input.

Analog input channel 3: positive input.

AIN_2GND

AIN_2P

AIN_3GND

AIN_3P

4

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

Pin Functions (continued)

TYPE DESCRIPTION

NAME

AIN_4GND

AIN_4P

NO.

56

55

58

57

60

59

62

61

64

63

AI

Analog input channel 4: negative input.

Analog input channel 4: positive input.

Analog input channel 5: negative input.

Analog input channel 5: positive input.

Analog input channel 6: negative input.

Analog input channel 6: positive input.

Analog input channel 7: negative input.

Analog input channel 7: positive input.

Analog input channel 8: negative input.

Analog input channel 8: positive input.

AIN_5GND

AIN_5P

AIN_6GND

AIN_6P

AIN_7GND

AIN_7P

AIN_8GND

AIN_8P

Analog supply pin. Decouple this pin to the closest AGND pins

(see the Power Supply Recommendations section).

AVDD

1, 37, 38, 48

P

DO

DI

Active high digital output indicating ongoing conversion

(see the BUSY (Output) section).

BUSY

14

9

Active high logic input to control start of conversion for first half count of device input channels (see the

CONVSTA, CONVSTB (Input) section).

CONVSTA

CONVSTB

Active high logic input to control start of conversion for second half count of device input channels (see

the CONVSTA, CONVSTB (Input) section).

10

DI

CS

13

16

17

18

19

20

21

22

DI

Active low logic input chip-select signal (see the CS (Input) section).

Data output DB0 (LSB) in parallel interface mode (see the DB[6:0] section).

Data output DB1 in parallel interface mode (see the DB[6:0] section).

Data output DB2 in parallel interface mode (see the DB[6:0] section).

Data output DB3 in parallel interface mode (see the DB[6:0] section).

Data output DB4 in parallel interface mode (see the DB[6:0] section).

Data output DB5 in parallel interface mode (see the DB[6:0] section).

Data output DB6 in parallel interface mode (see the DB[6:0] section).

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DO

Multi-function logic output pin (see the DB7/DOUTA section):

this pin is data output DB7 in parallel and parallel byte interface mode;

this pin is a data output pin in serial interface mode.

DB7/DOUTA

DB8/DOUTB

24

25

DO

Multi-function logic output pin (see the DB8/DOUTB section):

this pin is data output DB8 in parallel interface mode;

this pin is a data output pin in serial interface mode.

DB9

27

28

29

30

31

DO

Data output DB9 in parallel interface mode (see the DB[13:9] section).

Data output DB10 in parallel interface mode (see the DB[13:9] section).

Data output DB11 in parallel interface mode (see the DB[13:9] section).

Data output DB12 in parallel interface mode (see the DB[13:9] section).

Data output DB13 in parallel interface mode (see the DB[13:9] section).

DB10

DB11

DB12

DB13

Multi-function logic input or output pin (see the DB14/HBEN section):

this pin is data output DB14 in parallel interface mode;

this pin is a control input pin for byte selection (high or low) in parallel byte interface mode.

DB14/HBEN

32

33

DIO

Multi-function logic input or output pin (see the DB15/BYTE SEL section):

this pin is data output DB15 (MSB) in parallel interface mode;

DB15/BYTE SEL

this pin is an active high control input pin to enable parallel byte interface mode.

DVDD

23

15

P

Digital supply pin; decouple with AGND on pin 26.

Active high digital output indicating data read back from channel 1 of the device (see the FRSTDATA

(Output) section).

FRSTDATA

DO

Oversampling mode control pin

(see the Oversampling Mode of Operation section).

OS0

OS1

OS2

3

4

5

6

DI

Oversampling mode control pin

(see the Oversampling Mode of Operation section).

Oversampling mode control pin

(see the Oversampling Mode of Operation section).

Logic input pin to select between parallel, serial, or parallel byte interface mode (see the Data Read

Operation section).

PAR/SER/BYTE SEL

RANGE

Multi-function logic input pin (see the RANGE (Input) section):

when STBY pin is high, this pin selects the input range of the device (±10 V or ±5 V); when the STBY pin

is low, this pin selects between the standby and shutdown modes.

8

DI

5

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

Pin Functions (continued)

TYPE DESCRIPTION

NAME

NO.

Multi-function logic input pin (see the RD/SCLK (Input) section):

this pin is an active-low ready input pin in parallel and parallel byte interface;

this pin is a clock input pin in serial interface mode.

RD/SCLK

12

DI

Reference amplifier output pin. This pin must be shorted to REFCAPB and decoupled to AGND using a

low ESR, 10-µF ceramic capacitor.

REFCAPA

REFCAPB

REFGND

44

45

AO

P

Reference amplifier output pin. This pin must be shorted to REFCAPA and decoupled to AGND using a

low ESR, 10-µF ceramic capacitor.

Reference GND pin. This pin must be shorted to the analog GND plane and decoupled with

REFIN/REFOUT on pin 42 using a 10-µF capacitor.

43, 46

This pin acts as an internal reference output when REFSEL is high;

this pin functions as input pin for the external reference when REFSEL is low;

decouple with REFGND on pin 43 using a 10-µF capacitor.

REFIN/REFOUT

REFSEL

42

34

AIO

DI

Active high logic input to enable the internal reference

(see the REFSEL (Input) section).

REGCAP1

REGCAP2

36

39

AO

Output pin 1 for the internal voltage regulator; decouple separately to AGND using a 1-µF capacitor.

Output pin 2 for the internal voltage regulator; decouple separately to AGND using a 1-µF capacitor.

Active high logic input to reset the device digital logic

(see the RESET (Input) section).

RESET

STBY

11

7

DI

Active low logic input to enter the device into one of the two power-down modes: standby or shutdown

(see the Power-Down Modes section).

6 Specifications

6.1 Absolute Maximum Ratings

at T_A= 25°C (unless otherwise noted)⁽¹⁾

MIN

–0.3

–15

MAX

UNIT

V

AVDD to AGND

7.0

DVDD to AGND

Analog input voltage to AGND⁽²⁾

7.0

15

V

Digital input to AGND

–0.3

–10

DVDD + 0.3

AVDD + 0.3

10

V

REFIN to AGND

Input current to any pin except supplies⁽²⁾

V

mA

Operating

–40

125

Temperature

Junction, T_J

Storage, T_stg

150

°C

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Transient currents of up to 100 mA do not cause SCR latch-up.

6.2 ESD Ratings

VALUE

±2000

±9000

UNIT

All pins except analog inputs

Analog input pins only

Human-body model (HBM),

per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM),

±500

per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.75

2.3

NOM

5

MAX

5.25

UNIT

V

AVDD

DVDD

Analog supply voltage

Digital supply voltage

3.3

AVDD

V

6.4 Thermal Information

ADS8598S

THERMAL METRIC⁽¹⁾

PM (LQFP)

64 PINS

46.0

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

7.8

20.1

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

ψ_JB

19.6

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

6.5 Electrical Characteristics

minimum and maximum specifications are at T_A= –40°C to +125°C, AVDD = 4.75 V to 5.25 V; typical specifications are at T_A

= 25°C; AVDD = 5 V, DVDD = 3 V, V_REF= 2.5 V (internal), and f_SAMPLE= 200 kSPS (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUTS

Full-scale input span⁽¹⁾

(AIN_nP to AIN_nGND)

RANGE pin = 1

–10

–5

10

5

V

RANGE pin = 0

RANGE pin = 1

RANGE pin = 0

–10

–5

10

5

Operating input range,

positive input

AIN_nP

Operating input range,

negative input

AIN_nGND

All input ranges

–0.3

0

0.3

V

R_IN

Input impedance

At T_A= 25°C

0.85

–25

1

1.15

MΩ

Input impedance drift

All input ranges

±7

25 ppm/°C

µA

With voltage at AIN_nP = V_IN

all input ranges

,

I_Ikg(in)

Input leakage current

(V_IN– 2) / R_IN

SYSTEM PERFORMANCE

Resolution

18

Bits

LSB⁽²⁾

NMC

DNL

INL

No missing codes

Differential nonlinearity

Integral nonlinearity⁽³⁾

All input ranges

–0.9

–5.5

±0.5

±2

0.9

5.5

LSB

T_A= –40°C to

+85°C

–256

±10

32

256

300

All input ranges,

external

reference

T_A= –40°C to

+125°C

E_G

Gain error⁽⁴⁾

LSB

All input ranges,

internal reference

Input range = ±10 V,

external and internal reference

170

14

Gain error matching

(channel-to-channel)

Input range = ±5 V,

34

external and internal reference

All input ranges,

external reference

–14

±6

Gain error temperature drift

Offset error

ppm/°C

mV

All input ranges,

internal reference

±10

Input range = ±10 V

Input range = ±5 V

–1.8

±0.3

1.8

E_O

Offset error matching

(channel-to-channel)

All input ranges

0.5

5

3

mV

Offset error temperature drift

–3

1

±0.3

ppm/°C

SAMPLING DYNAMICS

t_ACQAcquisition time

µs

Maximum throughput rate per channel

without latency

f_S

All eight channels included

200

kSPS

(1) Ideal input span, does not include gain or offset error.

(2) LSB = least significant bit.

(3) This parameter is the endpoint INL, not best-fit INL.

(4) Gain error is calculated after adjusting for offset error, which implies that positive full scale error = negative full scale error = gain error ÷

2.

8

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

Electrical Characteristics (continued)

minimum and maximum specifications are at T_A= –40°C to +125°C, AVDD = 4.75 V to 5.25 V; typical specifications are at T_A

= 25°C; AVDD = 5 V, DVDD = 3 V, V_REF= 2.5 V (internal), and f_SAMPLE= 200 kSPS (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DYNAMIC CHARACTERISTICS

Signal-to-noise ratio,

no oversampling

(V_IN– 0.5 dBFS at 1 kHz)

Input range = ±10 V

92

90.25

99.6

94

93.2

SNR

dB

Input range = ±5 V

Input range = ±10 V

Input range = ±5 V

Signal-to-noise ratio,

oversampling = 16x

(V_IN– 0.5 dBFS at 130 Hz)

Total harmonic distortion⁽⁵⁾

(V_IN– 0.5 dBFS at 1 kHz)

101.8

99.2

SNR_OSR

THD

dB

97.4

All input ranges

–109.2

–95

Signal-to-noise + distortion ratio,

no oversampling

(V_IN– 0.5 dBFS at 1 kHz)

Input range = ±10 V

Input range = ±5 V

Input range = ±10 V

Input range = ±5 V

91.75

90

93.9

93.1

101

SINAD

Signal-to-noise + distortion ratio,

oversampling = 16x

(V_IN– 0.5 dBFS at 130 Hz)

98.5

96.6

SINAD_OSR

SFDR

dB

98.9

Spurious-free dynamic range

(V_IN– 0.5 dBFS at 1 kHz)

Crosstalk isolation⁽⁶⁾

All input ranges

109

–95

24

dB

At T_A= 25°C,

input range = ±10 V

BW_{(–3 dB)}

Small-signal bandwidth, –3 dB

kHz

At T_A= 25°C,

input range = ±5 V

16

14

At T_A= 25°C,

input range = ±10 V

BW_{(–0.1 dB)}

Small-signal bandwidth, –0.1 dB

Group delay

kHz

µs

At T_A= 25°C,

input range = ±5 V

9.5

Input range = ±10 V

Input range = ±5 V

13

19

t_GROUP

INTERNAL REFERENCE OUTPUT (REFSEL = 1)

Voltage on the REFIN/REFOUT pin

(configured as output)

(7)

V_REF

At T_A= 25°C

2.4975

3.996

2.5

7.5

10

2.5025

V

ppm/°C

µF

Internal reference temperature drift

Decoupling capacitor on the

C_{(REFIN_ REFOUT)}

REFIN/REFOUT pin⁽⁸⁾

Reference voltage to the ADC

V_(REFCAP)

At T_A= 25°C

4.0

4.004

1

V

(on the REFCAPA, REFCAPB pin)

Reference buffer output impedance

0.5

5

Ω

Reference buffer output temperature drift

ppm/°C

Decoupling capacitor on REFCAPA,

REFCAPB

C_(REFCAP)

10

25

µF

C_(REFCAP)= 10 µF,

C_{(REFIN_REFOUT)}= 10 µF

Turn-on time

ms

EXTERNAL REFERENCE INPUT (REFSEL = 0)

External reference voltage on REFIO

(configured as input)

V_{REFIO_EXT}

2.475

2.5

2.525

V

Reference input impedance

Reference input capacitance

100

10

MΩ

pF

(5) Calculated on the first nine harmonics of the input frequency.

(6) Isolation crosstalk is measured by applying a full-scale sinusoidal signal up to 160 kHz to a channel, not selected in the multiplexing

sequence, and measuring the effect on the output of any selected channel.

(7) Does not include the variation in voltage resulting from solder shift effects.

(8) Recommended to use an X7R-grade, 0603-size ceramic capacitor for optimum performance (see the Layout Guidelines section).

9

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

Electrical Characteristics (continued)

minimum and maximum specifications are at T_A= –40°C to +125°C, AVDD = 4.75 V to 5.25 V; typical specifications are at T_A

= 25°C; AVDD = 5 V, DVDD = 3 V, V_REF= 2.5 V (internal), and f_SAMPLE= 200 kSPS (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER-SUPPLY REQUIREMENTS

AVDD

DVDD

Analog power-supply voltage

Analog supply

4.75

2.3

5

5.25

V

Digital power-supply voltage

Digital supply range

3.3

AVDD

AVDD = 5 V,

f_S= 200 kSPS,

internal reference

17.7

17.1

24

Analog supply current

(operational)

I_{AVDD_DYN}

mA

AVDD = 5 V,

f_S= 200 kSPS,

external reference

AVDD = 5 V, internal reference,

device not converting

12.4

12

17

Analog supply current

(static)

I_{AVDD_STC}

AVDD = 5 V, external reference,

device not converting

At AVDD = 5 V, device in STDBY

mode, internal reference

4.2

3.8

5.5

5.0

AVDD supply

STANDBY current

I_{AVDD_STDBY}

mA

µA

At AVDD = 5 V, device in STDBY

mode, external reference

At AVDD = 5 V, device in PWR_DN,

internal or

external reference,

AVDD supply

power-down current

I_{AVDD_PWR_ DN}

0.2

6

T_A= –40°C to +85°C

DVDD = 3.3 V,

f_S= 200 kSPS

I_{DVDD_DYN}

Digital supply current

0.15

0.05

0.3

1.5

mA

µA

At AVDD = 5 V, device in STDBY

mode

I_{DVDD_STDBY}

I_{DVDD_PWR-DN}

DVDD supply STANDBY current

DVDD supply power-down current

At AVDD = 5 V, device in PWR_DN

mode

DIGITAL INPUTS (CMOS)

V_IH

V_IL

Digital high input voltage logic level

DVDD > 2.3 V

0.7 × DVDD

–0.3

DVDD + 0.3

0.3 × DVDD

V

Digital low input voltage logic level

Input leakage current

100

5

nA

pF

Input pin capacitance

DIGITAL OUTPUTS (CMOS)

V_OH

V_OL

Digital high output voltage logic level

I_O= 100-µA source

I_O= 100-µA sink

Only for SDO

0.8 × DVDD

0

DVDD

V

Digital low output voltage logic level

Floating state leakage current

Internal pin capacitance

0.2 × DVDD

1

5

µA

pF

TEMPERATURE RANGE

T_A

Operating free-air temperature

–40

125

°C

10

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

6.6 Timing Requirements: CONVST Control

minimum and maximum specifications are at T_A= –40°C to +125°C, typical specifications are at T_A= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V_REF= 2.5 V (internal), BUSY load = 20 pF, V_ILand V_IHat specified limits, and f_SAMPLE= 200 kSPS

(unless otherwise noted) (see 图 1)

MIN

NOM

MAX

UNIT

Acquisition time:

t_ACQ

1

µs

BUSY falling edge to rising edge of trailing CONVSTA or CONVSTB

t_{PH_CN}

t_{PL_CN}

CONVSTA, CONVSTB pulse high time

CONVSTA, CONVSTB pulse low time

25

0

ns

µs

t_{SU_BSYCS}Setup time: BUSY falling to CS falling

t_{SU_RSTCN}Setup time: RESET falling to first rising edge of CONVSTA or CONVSTB

25

50

t_{PH_RST}

t_{D_CNAB}

RESET pulse high time

Delay between rising edges of CONVSTA and CONVSTB

500

6.7 Timing Requirements: Data Read Operation

minimum and maximum specifications are at T_A= –40°C to +125°C, typical specifications are at T_A= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V_REF= 2.5 V (internal), BUSY load = 20 pF, V_ILand V_IHat specified limits, and f_SAMPLE= 200 kSPS

(unless otherwise noted) (see 图 2)

MIN

NOM

MAX

UNIT

Delay between CONVSTA, CONVSTB rising edge to CS falling edge, start of

data read operation during conversion

t_{DZ_CNCS}

t_{DZ_CSBSY}

t_{SU_BSYCS}

t_{D_CSCN}

10

ns

Delay between CS rising edge to BUSY falling edge, end of data read

operation during conversion

40

0

ns

Setup time: BUSY falling edge to CS falling edge, start of data read operation

after conversion

Delay between CS rising edge to CONVSTA, CONVSTB rising edge, end of

data read operation after conversion

10

6.8 Timing Requirements: Parallel Data Read Operation, CS and RD Tied Together

minimum and maximum specifications are at T_A= –40°C to +125°C, typical specifications are at T_A= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V_REF= 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, V_ILand V_IHat specified limits, and

f_SAMPLE= 200 kSPS (unless otherwise noted) (see 图 3)

MIN

NOM

MAX UNIT

t_{PH_CS}

t_{PH_RD}

,

CS and RD high time

15

ns

t_{PL_CS}

t_{PL_RD}

,

CS and RD low time

15

ns

t_{HT_RDDB}

t_{HT_CSDB}

,

Hold time: RD and CS rising edge to DB[15:0] invalid

2.5

11

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

6.9 Timing Requirements: Parallel Data Read Operation, CS and RD Separate

minimum and maximum specifications are at T_A= –40°C to +125°C, typical specifications are at T_A= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V_REF= 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, V_ILand V_IHat specified limits, and

f_SAMPLE= 200 kSPS (unless otherwise noted) (see 图 4)

MIN

0

NOM

MAX UNIT

t_{SU_CSRD}Set-up time: CS falling edge to RD falling edge

t_{HT_RDCS}Hold time: RD rising edge to CS rising edge

ns

0

t_{PL_RD}

t_{PH_RD}

RD low time

RD high time

15

6

t_{HT_CSDB}Hold time: CS rising edge to DB[15:0] becoming invalid

t_{HT_RDDB}Hold time: RD rising edge to DB[15:0] becoming invalid

2.5

6.10 Timing Requirements: Serial Data Read Operation

minimum and maximum specifications are at T_A= –40°C to +125°C, typical specifications are at T_A= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V_REF= 2.5 V (internal), load on DOUTA, DOUTB, and FRSTDATA = 20 pF, V_ILand V_IHat specified

limits, and f_SAMPLE= 200 kSPS (unless otherwise noted) (see 图 5)

MIN

50

NOM

MAX UNIT

t_SCLK

t_{PH_SCLK}SCLK high time

t_{PL_SCLK}SCLK low time

SCLK time period

ns

0.45

7

0.55 t_SCLK

t_{HT_CKDO}Hold time: SCLK rising edge to DOUTA, DOUTB invalid

t_{SU_CSCK}Setup time: CS falling to first SCLK edge

ns

8

t_{HT_CKCS}Hold time: last SCLK active edge to CS high

10

6.11 Timing Requirements: Byte Mode Data Read Operation

minimum and maximum specifications are at T_A= –40°C to +125°C, typical specifications are at T_A= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V_REF= 2.5 V (internal), load on DB[7:0] and FRSTDATA = 20 pF, V_ILand V_IHat specified limits, and

f_SAMPLE= 200 kSPS (unless otherwise noted) (see 图 6)

MIN

0

NOM

MAX UNIT

t_{SU_CSRD}Setup time: CS falling edge to RD falling edge

t_{HT_RDCS}Hold time: RD rising edge to CS rising edge

ns

0

t_{PL_RD}

t_{PH_RD}

RD low time

RD high time

15

6

t_{HT_CSDB}Hold time: CS rising edge to DB[15:0] becoming invalid

t_{HT_RDDB}Hold time: RD rising edge to DB[15:0] becoming invalid

2.5

6.12 Timing Requirements: Oversampling Mode

minimum and maximum specifications are at T_A= –40°C to +125°C, typical specifications are at T_A= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V_REF= 2.5 V (internal), V_ILand V_IHat specified limits, and f_SAMPLE= 200 kSPS (unless otherwise

noted) (see 图 7)

MIN

20

NOM

MAX

UNIT

ns

t_{HT_OS}

t_{SU_OS}

Hold time: BUSY falling to OSx

Setup time: BUSY falling to OSx

20

ns

6.13 Timing Requirements: Exit Standby Mode

minimum and maximum specifications are at T_A= –40°C to +125°C, typical specifications are at T_A= 25°C, AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V_REF= 2.5 V (internal), V_ILand V_IHat specified limits, and f_SAMPLE= 200 kSPS (unless otherwise

noted) (see 图 8)

MIN

NOM

MAX

UNIT

t_{D_STBYCN}Delay between STBY rising edge to CONVSTA or CONVSTB rising edge⁽¹⁾

100

µs

(1) First conversion data must be discarded or RESET must be issued if the maximum timing is exceeded.

12

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

6.14 Timing Requirements: Exit Shutdown Mode

minimum and maximum specifications are at T_A= –40°C to +125°C, typical specifications are at T_A= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V_REF= 2.5 V (internal), V_ILand V_IHat specified limits, and f_SAMPLE= 200 kSPS (unless otherwise

noted) (see 图 9)

MIN

50

NOM

MAX UNIT

Internal reference mode

External reference mode⁽¹⁾

t_{D_SDRST}Delay between STBY rising edge to RESET rising edge

t_{PH_RST}RESET high time

ms

13

50

ns

µs

t_{D_RSTCN}Delay between RESET falling edge to CONVSTA or CONVSTB rising edge

(1) Excludes wake-up time for external reference device.

25

6.15 Switching Characteristics: CONVST Control

minimum and maximum specifications are at T_A= –40°C to +125°C, typical specifications are at T_A= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V_REF= 2.5 V (internal), BUSY load = 20 pF, V_ILand V_IHat specified limits, and f_SAMPLE= 200 kSPS

(unless otherwise noted) (see 图 1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

No oversampling, parallel read, serial

read with both DOUTA and DOUTB

during conversion

5

No oversampling, serial read after

conversion with both DOUTA and

DOUTB

t_CYC

ADC cycle time period

9.7

15

µs

No oversampling, serial read after

conversion with only DOUTA or

DOUTB

No oversampling

3.7

8.4

17

3.8

3.9

8.8

18

Oversampling by 2

Oversampling by 4

Oversampling by 8

Oversampling by 16

Oversampling by 32

Oversampling by 64

t_CONV

Conversion time: BUSY high time

34

36

µs

ns

68

72

136

272

144

288

Delay between trailing rising edges of

CONVSTA or CONVSTB and BUSY

rising

t_{D_CNBSY}

15

6.16 Switching Characteristics: Parallel Data Read Operation, CS and RD Tied Together

minimum and maximum specifications are at T_A= –40°C to +125°C, typical specifications are at T_A= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V_REF= 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, V_ILand V_IHat specified limits, and

f_SAMPLE= 200 kSPS (unless otherwise noted) (see 图 3)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Delay time: CS and RD falling edge to

DB[15:0] becoming valid

(out of tri-state)

t_{D_CSDB}

t_{D_RDDB}

,

12

10

ns

Delay time: CS and RD falling edge to

FRSTDATA going high or low out of tri-

state

t_{D_CSFD}

,

t_{D_RDFD}

t_{DHZ_CSDB}

,

Delay time: CS and RD rising edge to

DB[15:0] tri-state

12

10

ns

t_{DHZ_RDDB}

t_{DHZ_CSFD}

t_{DHZ_RDFD}

,

Delay time: CS and RD rising edge to

FRSTDATA tri-state

13

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

6.17 Switching Characteristics: Parallel Data Read Operation, CS and RD Separate

minimum and maximum specifications are at T_A= –40°C to +125°C, typical specifications are at T_A= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V_REF= 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, V_ILand V_IHat specified limits, and

f_SAMPLE= 200 kSPS (unless otherwise noted) (see 图 4)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Delay time: CS falling edge to DB[15:0]

becoming valid

t_{D_CSDB}

12

ns

(out of tri-state)

Delay time: RD falling edge to new data

on DB[15:0]

t_{D_RDDB}

17

12

15

10

15

ns

Delay time: CS rising edge to DB[15:0]

becoming tri-state

t_{DHZ_CSDB}

t_{D_CSFD}

t_{DHZ_CSFD}

t_{D_RDFD}

Delay time: CS falling edge to

FRSTDATA going low out of tri-state

Delay time: CS rising edge to

FRSTDATA going to tri-state

Delay time: RD falling edge to

FRSTDATA going high or low

6.18 Switching Characteristics: Serial Data Read Operation

minimum and maximum specifications are at T_A= –40°C to +125°C, typical specifications are at T_A= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V_REF= 2.5 V (internal), load on DOUTA, DOUTB, and FRSTDATA = 20 pF, V_ILand V_IHat specified

limits, and f_SAMPLE= 200 kSPS (unless otherwise noted) (see 图 5)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Delay time: CS falling edge to DOUTA,

DOUTB enable

t_{D_CSDO}

12

ns

(out of tri-state)

Delay time: SCLK rising edge to valid

data on DOUTA, DOUTB

t_{D_CKDO}

t_{DZ_CSDO}

t_{D_CSFD}

15

12

10

15

10

ns

Delay time: CS rising edge to DOUTA,

DOUTB going to tri-state

Delay time: CS falling edge to

FRSTDATA from tri-state to high or low

Delay time: 18th SCLK falling edge to

FRSTDATA falling edge

t_{DZ_CKFD}

t_{DHZ_CSFD}

Delay time: CS rising edge to

FRSTDATA going to tri-state

14

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

6.19 Switching Characteristics: Byte Mode Data Read Operation

minimum and maximum specifications are at T_A= –40°C to +125°C, typical specifications are at T_A= 25°C; AVDD = 5 V,

2.3 V ≤ DVDD ≤ 5.25 V, V_REF= 2.5 V (internal), load on DB[7:0] and FRSTDATA = 20 pF, V_ILand V_IHat specified limits, and

f_SAMPLE= 200 kSPS (unless otherwise noted) (see 图 6)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Delay time: CS falling edge to

DB[7:0] becoming valid

(out of tri-state)

t_{D_CSDB}

12

ns

Delay time: RD falling edge to

new data on DB[7:0]

t_{D_RDDB}

17

12

ns

t_{DHZ_CSD}Delay time: CS rising edge to

DB[7:0] becoming tri-state

B

Delay time: CS falling edge to

t_{D_CSFD}

FRSTDATA going low out of tri-

state

10

ns

Delay time: RD falling edge to

FRSTDATA going low or high

state

t_{D_RDFD}

15

10

ns

Delay time: CS rising edge to

FRSTDATA going to tri-state

t_{DHZ_CSFD}

t_CYC

CONVSTA

t_{D_CNAB}

t_ACQ

t_{PL_CN}

t_{PH_CN}

CONVSTB

BUSY

t_{D_CNBSY}

t_CONV

t_{SU_BSYCS}

CS

t_{SU_RSTCN}

RESET

t_{PH_RST}

图 1. CONVST Control Timing Diagram

15

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

CONVSTA

CONVSTB

t_{D_CSCN}

t_{SU_BSYCS}

BUSY

t_{DZ_CNCS}

t_{DZ_CSBSY}

CS

Read During Conversion

Read After Conversion

t_{SU_RSTCN}

RESET

t_{PH_RST}

图 2. Data Read Operation Timing Diagram

t_{PH_CS}

t_{PH_RD}

t_{PL_CS}

t_{PL_RD}

t_{HT_CSDB}

t_{HT_RDDB}

CS , RD

t_{D_CSDB}

t_{D_RDDB}

t_{DHZ_CSDB}

t_{DHZ_RDDB}

AIN_1

[17:2]

AIN_1

[1:0]

AIN_2

[1:0]

AIN_7

[17:2]

AIN_7

[1:0]

AIN_8

[1:0]

AIN_2

[17:2]

AIN_8

[17:2]

DB[15:0]

t_{D_CSFD}

t_{D_RDFD}

t_{DHZ_CSFD}

t_{DHZ_RDFD}

FRSTDATA

图 3. Parallel Data Read Operation, CS and RD Tied Together

CS

t_{PH_RD}

t_{HT_RDCS}

t_{SU_CSRD}

t_{PL_RD}

RD

t_{HT_CSDB}

t_{DHZ_CSDB}

t_{D_CSDB}

t_{D_RDDB}

t_{HT_RDDB}

AIN_1

[17:2]

AIN_1

[1:0]

AIN_2

[17:2]

AIN_2

[1:0]

AIN_3

[17:2]

AIN_8

[17:2]

AIN_8

[1:0]

DB[15:0]

Invalid

t_{D_CSFD}

t_{D_RDFD}

t_{DHZ_CSFD}

FRSTDATA

图 4. Parallel Data Read Operation, CS and RD Separate

16

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

t_{SU_CSCK}

t_SCLK

CS

t_{PH_SCLK}

t_{HT_CKCS}

t_{PL_SCLK}

SCLK

t_{D_CSDO}

t_{DZ_CSDO}

t_{D_CKDO}

t_{HT_CKDO}

DB16

DOUTA

DOUTB

DB17

DB15

DB1

DB0

t_{DZ_CKFD}

t_{D_CSFD}

t_{DHZ_CSFD}

FRSTDATA

图 5. Serial Data Read Operation Timing Diagram

CS

t_{PH_RD}

t_{HT_RDCS}

t_{SU_CSRD}

t_{PL_RD}

RD

t_{HT_CSDB}

t_{DHZ_CSDB}

t_{D_CSDB}

t_{D_RDDB}

t_{HT_RDDB}

High Byte

AIN_1

Mid Byte

AIN_1

Low Byte

AIN_1

High Byte

AIN_2

Mid Byte

AIN_8

Low Byte

AIN_8

DB[7:0]

Invalid

t_{D_CSFD}

t_{D_RDFD}

t_{DHZ_CSFD}

FRSTDATA

图 6. Byte Mode Data Read Operation Timing Diagram

CONVSTA

CONVSTB

OSR latched for

Conversion (N+1)

Conversion

N

Conversion

N+1

BUSY

OSR x

t_{HT_OS}

t_{SU_OS}

图 7. Oversampling Mode Timing Diagram

17

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

STBY

RANGE

t_{D_STBYCN}

CONVSTA

CONVSTB

图 8. Exit Standby Mode Timing Diagram

STBY

RANGE

t_{D_SDRST}

RESET

t_{PH_RST}

CONVSTA

t_{D_RSTCN}

CONVSTB

图 9. Exit Shutdown Mode Timing Diagram

18

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

6.20 Typical Characteristics

at T_A= 25°C, AVDD = 5 V, DVDD = 3 V, internal reference V_REF= 2.5 V, and f_S= 200 kSPS per channel (unless otherwise

noted)

9

6

15

9

25 C

-40 C

125 C

25 C

-40 C

125 C

3

0

-3

-9

-15

-3

-6

-9

-10

-6

-2

2

6

10

-5

-3

-1

1

3

5

Input Voltage (V)

D002

D003

图 10. Analog Input Current vs Input Voltage and

图 11. Analog Input Current vs Input Voltage and

Temperature (±10 V)

Temperature (±5 V)

700

600

500

400

300

200

100

0

1.05

1.03

1.01

0.99

0.97

0.95

± 10 V

± 5 V

-40

-7

26

59

92

125

-9 -8 -7 -6 -5 -4 -3 -2 -1 0

1 2 3 4 5 6 7 8 9 10

Free-Air Temperature (èC)

Output Codes

D004

D009

Mean = 0.71, sigma = 1.83, number of hits = 4096, V_IN= 0 V

图 12. Input Impedance vs Free-Air Temperature

图 13. DC Histogram of Codes (±10 V)

800

700

600

500

400

300

200

100

0

1.5

1

0.5

0

-0.5

-1

-1.5

-6 -5 -4 -3 -2 -1

0

1

2

3

4

5

6

7

8

9

10 11

-131072

-65536

0

65536

131071

Output Codes

Codes (LSB) 2's Complement

D010

D011

Mean = 0.86, sigma = 2.1, number of hits = 4096, V_IN= 0 V

图 14. DC Histogram of Codes (±5 V)

图 15. DNL for All Codes

19

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

Typical Characteristics (接下页)

at T_A= 25°C, AVDD = 5 V, DVDD = 3 V, internal reference V_REF= 2.5 V, and f_S= 200 kSPS per channel (unless otherwise

noted)

5

1.5

0.75

0

Maximum

Minimum

3

1

-1

-3

-0.75

-1.5

-5

-40

-7

26

59

92

125

-131072

-65536

0

65536

131071

Free-Air Temperature (èC)

Codes (LSB) 2's Complement

D012

D013

图 16. DNL vs Free-Air Temperature

图 17. INL vs All Codes (±10 V)

5

3

10

6

Maximum

Minimum

1

2

-1

-3

-2

-6

-5

-10

-40

-131072

-65536

0

65536

131071

-7

26

59

92

125

Codes (LSB) 2's Complement

Free-Air Temperature (èC)

D014

D015

图 18. INL vs All Codes (±5 V)

图 19. INL vs Free-Air Temperature (±10 V)

10

6

1.8

1.08

Maximum

Minimum

± 10 V

± 5 V

2

0.36

-2

-6

-0.36

-1.08

-10

-40

-1.8

-40

-7

26

59

92

125

-7

26

59

92

125

Free-Air Temperature (èC)

D016

D017

图 20. INL vs Free-Air Temperature (±5 V)

图 21. Offset Error vs Free-Air Temperature

20

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

Typical Characteristics (接下页)

at T_A= 25°C, AVDD = 5 V, DVDD = 3 V, internal reference V_REF= 2.5 V, and f_S= 200 kSPS per channel (unless otherwise

noted)

130

120

110

100

90

1.8

1.08

0.36

-0.36

-1.08

-1.8

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

Channel 8

80

70

60

50

40

30

20

10

0

0.355 0.76 1.165 1.57 1.975 2.38 2.785 3

-40

-7

26

59

92

125

Offset Drift (ppm/èC)

Free-Air Temperature (èC)

D018

D019

图 22. Offset Drift Histogram Distribution (±10 V)

图 23. Offset Error Across Channels vs Free-Air

Temperature (±10 V)

130

120

110

100

90

1.8

1.08

0.36

-0.36

-1.08

-1.8

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

Channel 8

80

70

60

50

40

30

20

10

0

0.22 0.49 0.76 1.03 1.3 1.57 1.84 2.11 2.38 2.65

3

-40

-7

26

59

92

125

Offset Drift (ppm/èC)

Free-Air Temperature (èC)

D020

D021

图 24. Offset Drift Histogram Distribution (±5 V)

图 25. Offset Error Across Channels vs Free-Air

Temperature (±5 V)

80

70

60

50

40

30

20

10

0

200

100

0

-100

± 10 V

± 5 V

-200

0

1.76 4.21 5.595 6.98 8.365 9.75 11.13512.52 14

-40

-7

26

59

92

125

Gain Drift (ppm/èC)

Free-Air Temperature (èC)

D023

D022

External reference

图 27. Gain Error Drift Histogram Distribution (±10 V)

图 26. Gain Error vs Temperature

21

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

Typical Characteristics (接下页)

at T_A= 25°C, AVDD = 5 V, DVDD = 3 V, internal reference V_REF= 2.5 V, and f_S= 200 kSPS per channel (unless otherwise

noted)

80

70

60

50

40

30

20

10

0

400

250

100

-50

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

Channel 8

-200

-350

-500

0

1.76 4.21 5.595 6.98 8.365 9.75 11.13512.52 14

-40

-7

26

59

92

125

Gain Drift (ppm/èC)

Free-Air Temperature (èC)

D025

D024

External reference

图 29. Gain Error Drift Histogram Distribution (±5 V)

图 28. Gain Error Across Channels vs Free-Air Temperature

(±10 V)

250

150

100

80

60

40

20

0

50

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

-50

-150

Channel 6

Channel 7

± 10 V

± 5 V

Channel 8

-250

-40

-20

-7

26

59

92 125

0

50

100

150

200

Free-Air Temperature (èC)

Source Resistance (kW)

D026

D027

External reference

图 30. Gain Error Across Channels vs Free-Air Temperature

图 31. Gain Error as a Function of External Source

(±5 V)

Resistance

0

-50

-100

-150

-200

-100

-150

-200

0

25

50

75

100

0

25

50

75

100

Frequency (kHz)

D028

D029

Number of points = 256k, SNR = 93.77 dB,

Number of points = 256k, SNR = 92.45 dB,

SINAD = 93.52 dB, THD = –105.93, SFDR = 106.98 dB

SINAD = 92.26 dB, THD = –105.85 dB, SFDR = 107.12 dB

图 32. Typical FFT Plot (±10 V)

图 33. Typical FFT Plot (±5 V)

22

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

Typical Characteristics (接下页)

at T_A= 25°C, AVDD = 5 V, DVDD = 3 V, internal reference V_REF= 2.5 V, and f_S= 200 kSPS per channel (unless otherwise

noted)

0

-50

-100

-150

-200

-100

-150

-200

0

1.25

2.5

3.75

5

6.25

0

1.25

2.5

3.75

5

6.25

Frequency (kHz)

D030

D031

Number of points = 256k, SNR = 100.48 dB,

Number of points = 256k, SNR = 99.26 dB,

SINAD = 99.9 dB, THD = –105.93 dB, SFDR = 106.21 dB

SINAD = 98.63 dB, THD = –105.84 dB, SFDR = 105.94 dB

图 34. Typical FFT Plot for OSR 16x (±10 V)

图 35. Typical FFT Plot for OSR 16x (±5 V)

95

± 10 V

± 5 V

± 10 V

± 5 V

94

93

92

91

90

93

92

91

90

89

100

1k

10k

100k

-40

-7

26

59

92

125

Input Frequency (Hz)

Free-Air Temperature è(C)

D032

D033

OSR = 0

图 36. SNR vs Input Frequency for Different Input Ranges

图 37. SNR vs Free-Air Temperature for Different Input

Ranges

105

103

OSR-0

OSR-2

OSR-4

OSR-8

OSR-16

OSR-32

OSR-64

101

97

100

97

94

91

88

93

OSR-0

OSR-2

OSR-4

OSR-8

OSR-16

OSR-32

OSR-64

89

85

10

100

1k

Input Frequency (Hz)

10k

100k

10

100

1k

10k

100k

Input Frequency (Hz)

D034

D035

图 38. SNR vs Input Frequency for Different OSR

图 39. SNR vs Input Frequency for Different OSR

(±10 V)

(±5 V)

23

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

Typical Characteristics (接下页)

at T_A= 25°C, AVDD = 5 V, DVDD = 3 V, internal reference V_REF= 2.5 V, and f_S= 200 kSPS per channel (unless otherwise

noted)

95

94

93

92

91

90

95

94

93

92

91

90

89

± 10 V

± 5 V

± 10 V

± 5 V

100

1k

10k

100k

-40

-7

26

59

92

125

Input Frequency (Hz)

Free-Air Temperature (èC)

D036

D037

OSR = 0

图 40. SINAD vs Input Frequency for Different Input Ranges

图 41. SINAD vs Free-Air Temperature for Different Input

Ranges

-80

-100

± 10 V

± 5 V

± 10 V

± 5 V

-85

-90

-95

-105

-110

-115

-120

-100

-105

-110

-115

-120

-125

-130

100

1k

10k

100k

-40

-7

26

59

92

125

Input Frequency (Hz)

Free-Air Temperature (èC)

D038

D039

图 42. THD vs Input Frequency for Different Input Ranges

图 43. THD vs Free-Air Temperature for Different Input

Ranges

-60

0 kW

10 kW

0 kW

10 kW

20 kW

30 kW

40 kW

50 kW

61 kW

68.1 kW

82.5 kW

90.9 kW

100 kW

-70

-80

20 kW

30 kW

40 kW

-80

50 kW

61 kW

68.1 kW

-90

82.5 kW

90.9 kW

100 kW

-100

-110

-120

-100

-110

-120

1k

10k

100k

1k

10k

100k

Input Frequency (Hz)

D040

D041

图 44. THD vs Input Frequency for Different Source

图 45. THD vs Input Frequency for Different Source

Impedances (±10 V)

Impedances (±5 V)

24

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

Typical Characteristics (接下页)

at T_A= 25°C, AVDD = 5 V, DVDD = 3 V, internal reference V_REF= 2.5 V, and f_S= 200 kSPS per channel (unless otherwise

noted)

-90

-100

-110

-120

-130

-140

-90

-100

-110

-120

-130

-140

-150

±5 V

±10 V

± 5 V

± 10 V

100m

1

10

100

100m

1

10

100

Frequency (kHz)

D043

D042

图 47. Isolation Crosstalk vs Frequency (Saturated Inputs)

图 46. Isolation Crosstalk vs Frequency

(Inputs Within Range)

19.5

19

13.6

± 10 V

± 5 V

13.4

13.2

13

18.5

18

12.8

12.6

12.4

12.2

17.5

17

± 10 V

± 5 V

16.5

-40

-7

26

59

92

125

-40

-7

26

59

92

125

Free-Air Temperature (èC)

D053

D055

图 48. Analog Supply Current (Operational) vs Free-Air

图 49. Analog Supply Current (Static) vs Free-Air

Temperature

Temperature (Sampling)

4.26

6

5

4.24

4.22

4.2

4

3

4.18

4.16

4.14

4.12

2

1

0

-1

-40

-7

26

59

92

125

-7

26

59

92

125

Free-Air Temperature (èC)

D056

D057

图 50. Analog Supply Current vs Free-Air Temperature

图 51. Analog Supply Current vs Free-Air Temperature

(Standby)

(Shutdown)

25

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

7 Detailed Description

7.1 Overview

The ADS8598S is an 18-bit data acquisition (DAQ) system with 8-channel analog inputs. Each analog input

channel consists of an input clamp protection circuit, a programmable gain amplifier (PGA), a third-order, low-

pass filter, and a track-and-hold circuit that facilitates simultaneous sampling of the signals on all input channels.

The sampled signal is digitized using an 18-bit analog-to-digital converter (ADC), based on the successive

approximation register (SAR) architecture. This overall system can achieve a maximum throughput of 200 kSPS

for each channel. The device features a 2.5-V internal reference with a fast-settling buffer, a programmable

digital averaging filter to improve noise performance, and high speed serial and parallel interfaces for

communication with a wide variety of digital hosts.

The device operates from a single 5-V analog supply and can accommodate true bipolar input signals of ±10 V

and ±5 V. The input clamp protection circuitry can tolerate voltages up to ±15 V. The device offers a constant

1-MΩ resistive input impedance irrespective of the sampling frequency or the selected input range. The

integration of multiple, simultaneously sampling precision ADC inputs and analog front-end circuits with high

input impedance operating from a single 5-V supply offers a simplified end solution without requiring external

high-voltage bipolar supplies and complicated driver circuits.

7.2 Functional Block Diagram

AVDD

DVDD

BUSY

1 Mꢀ

AIN_1P

18-bit

SAR

ADC

Clamp

FRSTDATA

3^rd-Order

LPF

ADC

Driver

PGA

AIN_1GND

STBY

CONVSTA/B

RESET

RANGE

1 Mꢀ

AIN_2P

Clamp

18-bit

SAR

ADC

3^rd-Order

LPF

ADC

Driver

CS

PGA

AIN_2GND

RD/SCLK

PAR/ SER

DB[15:0]

SAR

Logic and

Digital Control

SER / PAR

Interface

1 Mꢀ

AIN_3P

Clamp

18-bit

SAR

ADC

Driver

3^rd-Order

LPF

DOUTA

DOUTB

AIN_3GND

1 Mꢀ

AIN_4P

Clamp

18-bit

SAR

ADC

Driver

3^rd-Order

LPF

OS0

OS1

OS2

PGA

AIN_4GND

Digital Filter

1 Mꢀ

18-bit

SAR

ADC

AIN_5P

Clamp

3^rd-Order

LPF

ADC

Driver

REFCAPA

REFCAPB

AIN_5GND

1 Mꢀ

AIN_6P

18-bit

SAR

ADC

Clamp

3^rd-Order

LPF

ADC

Driver

PGA

AIN_6GND

REFIN / REFOUT

REFSEL

2.5 V V

REF

1 Mꢀ

AIN_7P

Clamp

18-bit

SAR

ADC

Driver

3^rd-Order

LPF

AIN_7GND

1 Mꢀ

18-bit

SAR

ADC

AIN_8P

Clamp

3^rd-Order

LPF

ADC

Driver

AIN_8GND

ADS8598S

AGND

REFGND

26

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

7.3 Feature Description

7.3.1 Analog Inputs

The ADS8598S has 8 analog input channels, such that the positive inputs AIN_nP (n = 1 to 8) are the single-

ended analog inputs and the negative inputs AIN_nGND are tied to GND. 图 52 shows the simplified circuit

schematic for each analog input channel, including the input clamp protection circuit, PGA, low-pass filter, high-

speed ADC driver, and a precision 18-bit SAR ADC.

1 MW

AIN_nP

Clamp

3^rd-Order

LPF

18-bit

SAR

ADC

Driver

PGA

AIN_nGND

1 MW

图 52. Front-End Circuit Schematic for Each Analog Input Channel

The device can support two bipolar, single-ended input voltage ranges based on the logic level of the RANGE

input pin. As explained in the RANGE (Input) section, the input voltage range for all analog channels can be

configured to bipolar ±10 V or ±5 V. The device samples the voltage difference (AIN_nP – AIN_nGND) between

the selected analog input channel and the AIN_nGND pin. The device allows a ±0.3-V range on the AIN_nGND

pin for all analog input channels. Use this feature in modular systems where the sensor or signal conditioning

block is further away from the ADC on the board and when a difference in the ground potential of the sensor or

signal conditioner from the ADC ground is possible. In such cases, running separate wires from the AIN_nGND

pin of the device to the sensor or signal conditioning ground is recommended.

7.3.2 Analog Input Impedance

Each analog input channel in the device presents a constant resistive impedance of 1 MΩ. The input impedance

for each channel is independent of either the input signal frequency, the configured range of the ADC, or the

oversampling mode. The primary advantage of such high-impedance inputs is the ease of driving the ADC inputs

without requiring driving amplifiers with low output impedance. Bipolar, high-voltage power supplies are not

required in the system because this ADC does not require any high-voltage, front-end drivers. In most

applications, the signal sources or sensor outputs can be directly connected to the ADC input, thus significantly

simplifying the design of the signal chain.

In order to maintain the dc accuracy of the system, matching the external source impedance on the AIN_nP input

pin with an equivalent resistance on the AIN_nGND pin is recommended (see 图 54). This matching helps to

cancel any additional offset error contributed by the external resistance.

7.3.3 Input Clamp Protection Circuit

As illustrated in 图 52, the ADS8598S features an internal clamp protection circuit on each of the 8 analog input

channels. Use of external protection circuits is recommended as a secondary protection scheme to protect the

device. Using external protection devices helps with protection against surges, electrostatic discharge (ESD), and

electrical fast transient (EFT) conditions.

The input clamp protection circuit on the ADS8598S allows each analog input to swing up to a maximum voltage

of ±15 V. Beyond an input voltage of ±15 V, the input clamp circuit turns on, still operating off the single 5-V

supply. 图 53 illustrates a typical current versus voltage characteristic curve for the input clamp. There is no

current flow in the clamp circuit for input voltages up to ±15 V. Beyond this voltage, the input clamp circuit turns

on.

27

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

Feature Description (接下页)

50

40

30

20

10

0

-10

-20

-30

-40

-50

-20

-15

-10

-5

0

5

10

15

20

Input Voltage (V)

D007

图 53. I-V Curve for an Input Clamp Protection Circuit (AVDD = 5 V)

For input voltages above the clamp threshold, make sure that input current never exceeds the absolute

maximum rating (see the Absolute Maximum Ratings table) of ±10 mA to prevent any damage to the device. 图

54 shows that a small series resistor placed in series with the analog inputs is an effective way to limit the input

current. In addition to limiting the input current, this resistor can also provide an antialiasing, low-pass filter when

coupled with a capacitor. In order to maintain the dc accuracy of the system, matching the external source

impedance on the AIN_nP input pin with an equivalent resistance on the AIN_nGND pin is recommended. This

matching helps to cancel any additional offset error contributed by the external resistance.

1 Mꢀ

R

EXT

AIN_nP

Clamp

Input

Signal

C

PGA

AIN_nGND

R

图 54. Matching Input Resistors on the Analog Inputs of Device

The input overvoltage protection clamp on the ADS8598S is intended to control transient excursions on the input

pins. Leaving the device in a state such that the clamp circuit is activated for extended periods of time in normal

or power-down mode is not recommended because this fault condition can degrade device performance and

reliability.

7.3.4 Programmable Gain Amplifier (PGA)

The device offers a programmable gain amplifier (PGA) at each individual analog input channel that converts the

original single-ended input signal into a fully-differential signal to drive the internal 18-bit SAR ADC. The PGA

also adjusts the common-mode level of the input signal before being fed into the ADC to ensure maximum usage

of the ADC input dynamic range. Depending on the range of the input signal, the PGA gain can be accordingly

adjusted by configuring the RANGE pin of the ADC (see the RANGE (Input) section).

The PGA uses a very highly matched network of resistors for programmable gain configurations. Matching

between these resistors and the amplifiers across all channels is accurately trimmed to keep the overall gain

error low across all channels and input ranges.

28

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

Feature Description (接下页)

7.3.5 Third-Order, Low-Pass Filter (LPF)

In order to mitigate the noise of the front-end amplifiers and gain resistors of the PGA, each analog input channel

of the ADS8598S features a third-order, Butterworth antialiasing, low-pass filter (LPF) at the output of the PGA.

图 55 and 图 56 (respectively) show the magnitude and phase response of the analog antialiasing filter. For

maximum performance, the –3-dB cutoff frequency for the antialiasing filter is designed to be equal to 24 kHz for

the ±10-V range and 16 kHz for the ±5-V range.

30

25

20

15

10

5

0

-2

± 5 V

± 10 V

-4

-6

-8

± 5 V

± 10 V

-10

0

100

1k

10k

100k

1

10

100

1k

10k

100k

Input Frequency (Hz)

D046

D047

图 55. Third-Order LPF Magnitude Response

图 56. Third-Order LPF Phase Response

7.3.6 ADC Driver

In order to meet the performance of an 18-bit, SAR ADC at the maximum sampling rate (200 kSPS per channel),

the capacitors at the input of the ADC must be successfully charged and discharged during the acquisition time

window. The inputs of the ADC must settle to better than 18-bit accuracy before any sampled analog voltage

gets converted. This drive requirement at the inputs of the ADC necessitates the use of a high-bandwidth, low-

noise, and stable amplifier buffer. The ADS8598S features an integrated input driver as part of the signal chain

for each analog input. This integrated input driver eliminates the need for any external amplifier, thus simplifying

the signal chain design.

29

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

Feature Description (接下页)

7.3.7 Digital Filter and Noise

The ADS8598S features an optional digital averaging filter that can be used in slower throughput applications

requiring lower noise and higher dynamic range. As explained in 表 1, the oversampling ratio of the digital filter is

determined by the configuration of the OS[2:0] pins. The overall throughput of the ADC decreases proportionally

with increase in the oversampling ratio.

表 1. Oversampling Bit Decoding

SNR

±10-V INPUT

(dB)

SNR

±5-V INPUT

(dB)

3-dB BANDWIDTH

±10-V INPUT

(kHz)

3-dB BANDWIDTH MAX THROUGHPUT

OS

RATIO

OS[2:0]

±5-V INPUT

(kHz)

PER CHANNEL

(kSPS)

000

001

010

011

100

101

110

111

No OS

94.04

95.95

96.93

99.04

101.41

103.5

104.53

—

93.25

94.91

95.7

24

23

16

15.7

14.5

10.6

5.6

200

100

50

2

4

19.2

11.2

5.6

2.8

1.4

—

8

97.35

99.03

100.76

101.76

—

25

16

12.5

6.25

3.125

—

32

2.8

64

1.4

Invalid

—

In oversampling mode (see the Oversampling Mode of Operation section), the ADC takes the first sample for

each channel at the rising edge of the CONVSTA, CONVSTB signals. After converting the first sample, the

subsequent samples are taken by an internally generated sampling control signal. The samples are then

averaged to reduce the noise of the signal chain as well as to improve the SNR of the ADC. The final output is

also decimated to provide a 18-bit output for each channel. 表 1 lists the typical SNR performance for both the

±10-V and ±5-V input ranges, including the –3-dB bandwidth and proportional maximum throughput per channel.

When the oversampling ratio increases, there is a proportional improvement in the SNR performance and

decrease in the bandwidth of the input filter.

7.3.8 Reference

The ADS8598S can operate with either an internal voltage reference or an external voltage reference using an

internal gain amplifier. The internal or external reference selection is determined by an external REFSEL pin, as

explained in the REFSEL (Input) section. The REFIN/REFOUT pin outputs the internal band-gap voltage (in

internal reference mode) or functions as an input for the external reference voltage (in external reference mode).

In both cases, the on-chip amplifier is always enabled. Use this internal amplifier to gain the reference voltage

and drive the actual reference input of the internal ADC core for maximizing performance. The REFCAPA (pin

45) and REFCAPB (pin 44) pins must be shorted together externally and a ceramic capacitor of 10 µF (minimum)

must be connected between this node and REFGND (pin 43) to ensure that the internal reference buffer is

operating as closed loop. Place this capacitor as close as possible to the device to achieve rated performance.

30

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

7.3.8.1 Internal Reference

The device has an internal 2.5-V (nominal value) band-gap reference. In order to select the internal reference,

the REFSEL pin must be tied high or connected to DVDD. When the internal reference is used, REFIN/REFOUT

(pin 42) becomes an output pin with the internal reference value. A 10-μF (minimum) decoupling capacitor, as

shown in 图 57, is recommended to be placed between the REFIN/REFOUT pin and REFGND (pin 43). The

capacitor must be placed as close to the REFIN/REFOUT pin as possible. The output impedance of the internal

band-gap creates a low-pass filter with this capacitor to band-limit the noise of the band-gap output. The use of a

smaller capacitor increases the reference noise in the system, thus degrading SNR and SINAD performance. Do

not use the REFIN/REFOUT pin to drive external ac or dc loads because of the limited current output capability

of the pin. The REFIN/REFOUT pin can be used as a reference source if followed by a suitable op amp buffer.

AVDD

2.5-V V_REF

DVDD

REFSEL

REFIN/REFOUT

10 mF

REFCAPB

REFCAPA

10 mF

REFGND

ADC

AGND

图 57. Device Connections for Using an Internal 2.5-V Reference

The device internal reference is factory trimmed to a maximum initial accuracy of ±2.5 mV. The histogram in 图

58 shows the distribution of the internal voltage reference output taken from more than 2100 devices.

700

650

600

550

500

450

400

350

300

250

200

150

100

50

0

-2.5 -2.2 -1.6

-1

-0.4 0.2

0.8

1.4

2

2.5

REFIO Initial Acuuracy (mV)

D048

图 58. Internal Reference Accuracy at Room Temperature Histogram

The initial accuracy specification for the internal reference can be degraded if the die is exposed to any

mechanical, thermal, or environmental stress (such as humidity). Heating the device when being soldered to a

printed circuit board (PCB) and any subsequent solder reflow is a primary cause for shifts in the V_REFvalue. The

main cause of thermal hysteresis is a change in die stress and therefore is a function of the package, die-attach

material, and molding compound, as well as the layout of the device itself.

31

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

In order to illustrate this effect, 80 devices were soldered using lead-free solder paste with the suggested

manufacturer reflow profile, as explained in the AN-2029 Handling & Process Recommendations application

report. The internal voltage reference output is measured before and after the reflow process and 图 59 shows

the typical shift in value. Although all tested units exhibit a positive shift in the output voltages, negative shifts are

also possible. The histogram in 图 59 shows the typical shift for exposure to a single reflow profile. Exposure to

multiple reflows, which is common on PCBs with surface-mount components on both sides, causes additional

shifts in the output voltage. If the PCB is to be exposed to multiple reflows, solder the ADS8598S in the last pass

to minimize device exposure to thermal stress.

30

25

20

15

10

5

0

-4

-3

-2

-1

0

1

Error in REFIO Voltage (mV)

C065

图 59. Solder Heat Shift Distribution Histogram

The internal reference is also temperature compensated to provide excellent temperature drift over an extended

industrial temperature range of –40°C to +125°C. 图 60 shows the variation of the internal reference voltage

across temperature for different values of the AVDD supply voltage. The typical specified value of the reference

voltage drift over temperature is 7.5 ppm/°C.

2.505

AVDD = 4.75 V

AVDD = 5 V

AVDD = 5.25 V

2.503

2.501

2.499

2.497

2.495

-40

-7

26

59

92

125

Free-Air Temperature (èC)

D049

图 60. Variation of Internal Reference Output (REFIN/REFOUT) vs Free-Air Temperature and Supply

7.3.8.2 External Reference

For applications that require a reference voltage with lower temperature drift or a common reference voltage for

multiple devices, the ADS8598S offers a provision to use an external reference, using the internal buffer to drive

the ADC reference pin. In order to select the external reference mode, either tie the REFSEL pin low or connect

this pin to AGND. In this mode, an external 2.5-V reference must be applied at REFIN/REFOUT (pin 42), which

becomes a high-impedance input pin. Any low-drift, small-size external reference can be used in this mode

because the internal buffer is optimally designed to handle the dynamic loading on the ADC reference input. The

output of the external reference must be filtered to minimize the resulting effect of the reference noise on system

performance. 图 61 illustrates a typical connection diagram for this mode.

32

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

AVDD

2.5-V V_REF

REFSEL

AVDD

REF5025

OUT

(Refer to Device

Datasheet for Detailed Pin

Configuration)

REFIN/REFOUT

C_REF

REFCAPB

REFCAPA

10 mF

REFGND

AGND

ADC

图 61. Device Connections for Using an External 2.5-V Reference

For closed-loop operation of the internal reference buffer, the REFCAPA and REFCAPB pins must be externally

shorted together. The output of the internal reference buffer appears at the REFCAP pin. A minimum

capacitance of 10 µF must be placed between the REFCAPA, REFCAPB pins and REFGND (pin 43). Place this

capacitor as close as possible to the REFCAPA and REFCAPB pins. Do not use this internal reference buffer to

drive external ac or dc loads because of the limited current output capability.

图 62 shows that the performance of the internal buffer output is very stable across the entire operating

temperature range of –40°C to +125°C. 图 63 shows that the typical specified value of the reference buffer drift

over temperature is 5 ppm/°C.

8

7

6

5

4

3

2

1

0

4.01

4.005

4

AVDD = 4.75 V

AVDD = 5 V

AVDD = 5.25 V

3.995

3.99

0

0.665

1.325

1.985

2.645

3.305

4

-40

-7

26

59

92

125

REFCAP Drift (ppm/èC)

Free-Air Temperature (èC)

D052

D051

Number of samples = 30

图 62. Variation of Reference Buffer Output (REFCAPA,

REFCAPB) vs Free-Air Temperature and Supply

图 63. Reference Buffer Temperature Drift Histogram

7.3.8.3 Supplying One V_REFto Multiple Devices

For applications that require multiple ADS8598S devices, using the same reference voltage source for all ADCs

helps eliminate any potential errors in the system resulting from mismatch between multiple reference sources.

图 64 illustrates the recommended connection diagram for an application that uses one device in internal

reference mode and provides the reference source for other devices. The device used as source of the voltage

reference is bypassed by a 10-µF capacitor on the REFIN/REFOUT pin, whereas the other devices are bypassed

with a 100-nF capacitor.

33

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

DVDD

ADS8598S

REFSEL

REFIN / REFOUT

Configured as Output

Configured as Input

10mF

100nF

REFGND

图 64. Multiple Devices Connected With an Internal Reference From one Device

图 65 shows the recommended connection diagram for an application that uses an external voltage reference

(such as the REF5025) to provide the reference source for multiple devices.

ADS8598S

REFSEL

REFIN / REFOUT

100 nF

REFGND

100 nF

REFGND

AVDD

REF5025

REFGND

OUT

(Refer to Device

Datasheet for Detailed

Pin Configuration)

C_REF

图 65. Multiple Devices Connected Using an External Reference

7.3.9 ADC Transfer Function

The ADS8598S is a multichannel device that supports two single-ended, bipolar input ranges of ±10 V and ±5 V

on all input channels. The device outputs 18 bits of conversion data in binary two's complement format for both

bipolar input ranges. The format for the output codes is the same across all analog channels.

图 66 depicts the ideal transfer characteristic for each ADC channel for all input ranges. The full-scale range

(FSR) for each input signal is equal to the difference between the positive full-scale (PFS) input voltage and the

negative full-scale (NFS) input voltage. The LSB size is equal to FSR / 2¹⁸= FSR / 262144 because the

resolution of the ADC is 18 bits. 表 2 lists the LSB values corresponding to the different input ranges.

34

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

0111 … … 1111

(1FFFFh)

0000 … … 0000

(00000h)

PFS œ 1.5LSB

1000 … … 0000

(20000h)

NFS+0.5LSB

0V-0.5LSB

NFS

PFS

FSR = PFS - NFS

Analog Input (AIN_nP t AIN_nGND)

图 66. 18-Bit ADC Transfer Function (Two's Complement Binary Format)

表 2. ADC LSB Values for Different Input Ranges

POSITIVE FULL-SCALE NEGATIVE FULL-SCALE

INPUT RANGE (V)

FULL-SCALE RANGE (V)

LSB (µV)

(V)

10

5

(V)

–10

–5

±10

±5

20

10

76.295

38.1475

7.3.10 ADS8598S Device Family Comparison

The ADS8598S belongs to a family of pin-compatible devices. 表 3 lists the devices from this family along with

their features.

表 3. Device Family Comparison

PRODUCT

ADS8598H

ADS8588H

ADS8588S

ADS8586S

ADS8584S

ADS8578S

RESOLUTION (Bits)

CHANNELS

8, single-ended

6, single-ended

4, single-ended

8, single-ended

SAMPLE RATE (kSPS)

18

16

14

500

200

250

330

200

35

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

7.4 Device Functional Modes

7.4.1 Device Interface: Pin Description

7.4.1.1 REFSEL (Input)

The REFSEL pin is a digital input pin that enables selection between the internal and external reference mode of

operation for the device. If the REFSEL pin is set to logic high, then the internal reference is enabled and

selected. If this pin is set to logic low, then the internal band-gap reference circuit is disabled and powered down.

In this mode, an external reference voltage must be provided to the REFIN/REFOUT pin. Under both conditions,

the internal reference buffer is always enabled.

The REFSEL pin is an asynchronous logic input. The device output on the REFIN/REFOUT pin starts changing

immediately with a change in state of the REFSEL input pin. During power-up, the device wakes up in internal or

external reference mode depending on the state of the REFSEL input pin.

7.4.1.2 RANGE (Input)

The RANGE pin is a digital input pin that allows the input range to be selected for all analog input channels. If

this pin is set to logic high, the device is configured to operate in the ±10-V input range for all input channels. If

this pin is set to logic low, then all input channels operate in the ±5-V input range.

In applications where the input range remains the same for all input channels, the RANGE pin is recommended

to be hardwired to the appropriate signal. However, some applications can require an on-the-fly change in the

input range by the digital host. For such cases, the RANGE pin functions as an asynchronous input, meaning

that any change in the logic input results in an immediate change in the input range configuration of the device.

An additional 80 µs must typically be allowed in addition to the device acquisition time for the internal active

circuitry to settle to the required accuracy before initiating the next conversion.

The RANGE pin is also used to put the device in standby or shutdown mode depending on the state of the STBY

input pin, as explained in the Power-Down Modes section.

7.4.1.3 STBY (Input)

The STBY pin is a digital input pin used to put the device into one of the two power-down modes: standby and

shut down. Set the STBY pin to logic high for normal device operation. If this pin is set to logic low, the device

enters either standby mode or shutdown mode depending on the state of the RANGE input pin. Both of these

modes are low-power modes supported by the device. In shutdown mode, all internal circuitry is powered down,

but in standby mode the internal reference and regulators remain powered to enable a relatively quicker recovery

to normal operation.

The STBY pin functions as an asynchronous input, meaning that this pin can be pulled low at anytime during

device operation to put the device into one of the two power-down modes. However, if the STBY input is set high

to bring the device out of power-down mode, then wait for the specified recovery time, as specified in the Timing

Requirements: Exit Standby Mode table for proper operation. See the Power-Down Modes section for more

details on device operation in the two power-down modes.

7.4.1.4 PAR/SER/BYTE SEL (Input)

The PAR/SER/BYTE SEL pin is a digital input pin that selects between the parallel, serial, or parallel byte

interface for reading the data output from the device. If this pin is tied to logic low, then the device operates in the

parallel interface mode (see the Parallel Data Read section). If this pin is tied to logic high, then the serial or

parallel byte interface mode is selected depending on the state of the DB15/BYTE SEL pin. If the DB15/BYTE

SEL is tied low, then serial mode is selected (see the Serial Data Read section) and the parallel byte interface is

selected if this pin is tied high (see the Parallel Byte Data Read section).

36

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

Device Functional Modes (接下页)

7.4.1.5 CONVSTA, CONVSTB (Input)

Conversion start A (CONVSTA) and conversion start B (CONVSTB) are active-high, conversion control digital

input signals. CONVSTA can be used to simultaneously sample and initiate the conversion process for the first

half count of device input channels (channels 1-4), whereas CONVSTB can be used to simultaneously sample

and initiate the conversion process for the latter half count of device input channels (channels 5-8). For

simultaneous sampling of all input channels, both pins can be shorted together and a single CONVST signal can

be used to control the conversion on all input channels. However, in the oversampling mode of operation (see

the Oversampling Mode of Operation section), both the CONVSTA and CONVSTB signals must be tied together.

On the rising edge of the CONVSTA, CONVSTB signals, the internal track-and-hold circuits for each analog input

channel are placed into hold mode and the sampled input signal is converted using an internal clock. The

CONVSTA, CONVSTB signals can be pulled low when the internal conversion is over, as indicated by the BUSY

signal (see the BUSY (Output) section). At this point, the front-end circuit for all analog input channels acquire

the respective input signals and the internal ADC is not converting. The output data can be read from the device

irrespective of the status of the CONVSTA, CONVSTB pins, as there is no degradation in device performance,

as explained in the Data Read Operation section.

7.4.1.6 RESET (Input)

The RESET pin is an active-high digital input. A dedicated reset pin allows the device to be reset at any time in

an asynchronous manner. All digital circuitry in the device is reset when the RESET pin is set to logic high and

this condition remains active until the pin returns low. The device must always be reset after power-up as well as

after recovery from shut-down mode when all supplies and references have settled to the required accuracy. If

the RESET is issued during an ongoing conversion process, then the device aborts the conversion and output

data are invalid. If the reset signal is applied during a data read operation, then the output data registers are all

reset to zero.

In order to initiate the next conversion cycle after deactivating a reset condition, allow for a minimum time delay

between the falling edge of the RESET input and the rising edge of the CONVSTA, CONVSTB inputs (see the

Timing Requirements: CONVST Control table). Any violation in this timing requirement can result in corrupting

the results from the next conversion.

7.4.1.7 RD/SCLK (Input)

RD/SCLK is a dual-function pin. 表 4 explains the usage of this pin under different operating conditions of the

device.

表 4. RD/SCLK Pin Functionality

DEVICE OPERATING CONDITION

FUNCTIONALITY OF THE RD/SCLK INPUT

PAR/SER/BYTE SEL = 0

DB15/BYTE SEL = x

Functions as an active-low digital input pin to read the output data from the device.

In parallel or parallel byte interface mode, the output bus is enabled when both the

CS and RD inputs are tied to a logic low input (see the Data Read Operation

section).

Parallel interface

PAR/SER/BYTE SEL = 1

DB15/BYTE SEL = 1

Parallel byte interface

Serial interface

Functions as an external clock input for the serial data interface. In serial mode, all

synchronous accesses to the device are timed with respect to the rising edge of

the SCLK signal (see the Serial Data Read section).

PAR/SER/BYTE SEL = 1

DB15/BYTE SEL = 0

7.4.1.8 CS (Input)

The CS pin indicates an active-low, chip-select signal. A rising edge on the CS signal configures all data lines in

tri-state mode. This function allows multiple devices to share the same output data lines. The falling edge of the

CS signal marks the beginning of the output data transfer frame in any interface mode of operation for the

device. In the parallel and parallel byte interface modes, both the CS and RD input pins must be driven low to

enable the digital output bus for reading the conversion data (DB[15:0] for parallel and DB[7:0] for parallel byte

interface). In serial mode, the falling edge of the CS signal takes the DOUTA, DOUTB serial data output lines out

of tri-state mode and outputs the MSB of the previous conversion result.

37

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

7.4.1.9 OS[2:0]

The OS[2:0] pins are active-high digital input pins used to configure the oversampling ratio for the internal digital

filter on the device. OS2 is the MSB control bit and OS0 is the LSB control bit. 表 1 provides the decoding of the

OS[2:0] bits for different oversampling rates. As described in 表 1, an increase in the OSR mode improves the

typical SNR performance for both input ranges and reduces the 3-dB input bandwidth as well as the maximum-

allowed throughput per channel.

7.4.1.10 BUSY (Output)

BUSY is an active-high digital output signal. This pin goes to logic high after the rising edges of both the

CONVSTA and CONVSTB signals, indicating that the front-end, track-and-hold circuits for all input channels are

in hold mode and that the ADC conversion has started. When the BUSY signal goes high, any activity on the

CONVSTA or CONVSTB inputs has no effect on the device. The BUSY output remains high until the conversion

process for all channels is completed and the conversion data are latched into the output data registers for read

out. If the conversion data are read for the previous conversion when BUSY is high, ensure that the data read

operation is complete before the falling edge of the BUSY output.

7.4.1.11 FRSTDATA (Output)

FRSTDATA is an active-high digital output signal that indicates if the conversion data output for the first analog

input channel of the ADC (AIN_1P and AIN_1GND) is being read out in either of the interface modes. The

FRSTDATA output pin comes out of tri-state when the CS input is pulled from a high to a low logic level. 表 5

indicates the functionality of the FRSTDATA output in different interface modes of the device.

表 5. FRSTDATA Pin Functionality

DEVICE OPERATING CONDITION

FUNCTIONALITY OF THE FRSTDATA OUTPUT

MODE

CONDITIONS

The first falling edge of the RD signal corresponding to the output result of channel

1 sets the FRSTDATA output to a logic high level. This setting indicates that the

data output from channel 1 is being read on the parallel output bus (DB[15:0]). The

FRSTDATA output goes low at the third falling edge of the RD signal and remains

low until the conversion data output from all other channels is read.

PAR/SER/BYTE SEL = 0,

DB15/BYTE SEL = x

Parallel mode

The first falling edge of the RD signal corresponding to one byte of the output of

channel 1 sets the FRSTDATA output to a logic high level. This setting indicates

that one byte of the data output from channel 1 is being read on the parallel output

bus (DB[7:0]). The FRSTDATA output remains high at the next two falling edges of

the RD signal to read the second and third byte of the channel 1 output. This pin

goes low on the fourth falling edge of the RD signal and remains low until the

conversion data output from all other channels is read.

PAR/SER/BYTE SEL = 1,

DB15/BYTE SEL = 1

Parallel byte mode

Serial mode

The FRSTDATA output goes to a logic high state on the falling edge of the CS

signal when the MSB of the channel 1 conversion result is output on DOUTA at

this instant. The FRSTDATA pin goes low at the 18th falling edge of the SCLK

input, indicating that all 18 bits of the channel 1 output have been read. This pin

remains low until the conversion data output from all other channels is read.

PAR/SER/BYTE SEL = 1,

DB15/BYTE SEL = 0

7.4.1.12 DB15/BYTE SEL

DB15/BYTE SEL is a dual-function, digital input, output pin.

When the device operates in parallel interface mode (PAR/SER/BYTE SEL = 0), this pin functions as a digital

output. In this mode, this pin is active when the CS signal is pulled low. This pin outputs bit 17 of the conversion

result during the first RD pulse and bit 1 of the same conversion result during the second RD pulse.

When the device does not operate in parallel interface mode (PAR/SER/BYTE SEL = 1), this pin functions as a

digital control input pin to select between the serial and parallel byte interface modes. The device operates in the

serial interface mode when the DB15/BYTE SEL pin is tied low and the device operates in the parallel byte

interface mode when this pin is tied to a logic high input.

38

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

7.4.1.13 DB14/HBEN

DB14/HBEN is a dual-function, digital input, output pin.

When the device operates in parallel interface mode (PAR/SER/BYTE SEL = 0), this pin functions as a digital

output. In this mode, this pin is active when the CS signal is pulled low. This pin outputs bit 16 of the conversion

result during the first RD pulse and bit 0 of the same conversion result during the second RD pulse.

When the device operates in parallel byte interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1),

this pin functions as a digital control input pin that selects if the MSB byte or the LSB byte is output first. If the

DB14/HBEN pin is tied to logic high, then the MSB byte (bit[17:10]) is output first followed by the mid byte

(bit[9:2]) followed by the LSB byte (bit[1:0] and six zeros) and vice-versa if this pin is tied to logic low.

When the device operates in serial interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 0), this pin

must be tied to AGND or to a logic low input.

7.4.1.14 DB[13:9]

DB[13:9] are digital output pins. In parallel interface mode (PAR/SER/BYTE SEL = 0), these pins output bit 15 to

bit 11 of the conversion result for each analog channel when both the CS and RD signals are pulled low. When

the device is not in parallel interface mode (PAR/SER/BYTE SEL = 1), these pins must be tied to AGND or to a

logic low input.

7.4.1.15 DB8/DOUTB

DB8/DOUTB is a dual-function digital output pin.

In parallel interface mode (PAR/SER/BYTE SEL = 0), use this pin to output bit 10 of the conversion result

followed by a zero for each analog channel when both the CS and RD signals are pulled low.

When the device operates in parallel byte interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1),

this pin remains in a tri-state mode.

In serial interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 0), this pin outputs the conversion

data for the second half count of device input channels (channels 5-8).

7.4.1.16 DB7/DOUTA

DB7/DOUTA is a dual-function digital output pin.

In parallel interface mode (PAR/SER/BYTE SEL = 0), use this pin to output bit 9 of the conversion result followed

by a zero for each analog channel when both the CS and RD signals are pulled low.

When the device operates in parallel byte interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1),

this pin outputs the MSB of the output byte of the conversion data.

In serial interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 0), use this pin to output conversion

data for the first half count of device input channels (channels 1-4).

7.4.1.17 DB[6:0]

DB[6:0] are digital output pins.

In parallel interface mode (PAR/SER/BYTE SEL = 0), these pins output bit 8 to bit 2 of the conversion result

followed by a zero for each analog channel when both the CS and RD signals are pulled low.

When the device operates in parallel byte interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1),

these pins along with the DB7 pin output the 18-bit conversion result in MSB-first fashion in three consecutive

RD operations.

When the device operates in serial interface mode (PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 0), these

pins must be tied to AGND or to a logic low input.

39

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

7.4.2 Device Modes of Operation

The ADS8598S supports multiple modes of operation that can be programmed using the hardware pins. This

functionality allows the device to be easily configured without any complicated software programming. This

section provides details about the normal, power-down (standby and shutdown), and oversampling modes of

operation of the device.

7.4.2.1 Power-Down Modes

For applications that are sensitive to power consumption, the ADS8598S offers a built-in, power-down feature.

The device supports two power-down modes: standby mode and shutdown mode. As shown in 表 6, the device

can enter either power-down mode by pulling the STBY pin to a logic low level. Additionally, the selection

between these two power-down modes is done by the state of the RANGE pin.

表 6. Power-Down Mode Selection

POWER DOWN MODE

Standby

STBY

RANGE

0

1

0

Shutdown

7.4.2.1.1 Standby Mode

The device supports a low-power standby mode in which only part of the circuit is powered down. The analog

front-end, signal-conditioning circuit for each channel remains powered down in this mode, but the internal

reference and regulator are not powered down. In standby mode, the total power consumption of the device is

typically equal to 19 mW.

In order to enter standby mode, the STBY input pin must be set to logic low and the RANGE input pin must be

set to a logic high value. The device can be asynchronously put into this mode by configuring the STBY and

RANGE inputs at anytime during device operation.

The device exits standby mode when a logic high input is applied to the STBY pin. At this time, the internal

circuitry starts powering up and takes a minimum time of 100 µs to settle before the next conversion can be

initiated. See the Timing Requirements: Exit Standby Mode table and 图 8 for timing details.

7.4.2.1.2 Shutdown Mode

The device supports a low-power shutdown mode in which the entire internal circuitry is powered down. In

shutdown mode, the total power consumption of the device is typically equal to 1 µW.

In order to enter shutdown mode, the STBY input pin must be set to logic low and the RANGE input pin must be

set to a logic low value. The device can be asynchronously put into this mode by configuring the STBY and

RANGE inputs at anytime during device operation.

The device exits shutdown mode when a logic high input is applied to the STBY pin. At this time, the internal

circuitry starts powering up and takes a minimum time of 13 ms to settle in external reference mode before the

next conversion can be initiated. After recovery from shutdown mode, a RESET signal must be applied before

the next conversion can be initiated. See the Timing Requirements: Exit Shutdown Mode table and 图 9 for

timing details.

7.4.2.2 Conversion Control

The ADS8598S offers easy and precise control to simultaneously sample all analog input channels or pairs of

input channels. The sampling instant can be user-controlled through the digital pins, CONVSTA and CONVSTB.

Simultaneously capturing the input signal on all analog input channels is extremely useful in certain applications

that are sensitive to additional phase delay between input channels caused by sequential sampling. This section

describes the methodology to simultaneously sample all input channels or pairs of input channels for the device.

7.4.2.2.1 Simultaneous Sampling on All Input Channels

The ADS8598S allows all the analog input channels to be simultaneously sampled. In order to do so, the

CONVSTA and CONVSTB signals must be tied together (see 图 67) and a single CONVST signal must be used

to control the sampling of all analog input channels of the device. 图 67 also provides the sequence of events

described in this section.

40

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

CONVSTA

CONVSTB

BUSY

CS and RD

AIN_1

[17:2]

AIN_1

[1:0]

AIN_8

[17:2]

AIN_8

[1:0]

DB[15:0]

FRSTDATA

1

2

3

4

图 67. Simultaneous Sampling of All Input Channels in Parallel Interface Timing Diagram

There are four events that describe the internal operation of the device when all input channels are

simultaneously sampled and the data are read back. These events are:

•

Event 1: Simultaneous sampling of all analog input channels is initiated with the rising edge of the CONVST

signal. The input signals on all channels are sampled at this same instant because both the CONVSTA and

CONVSTB inputs are tied together. The sampled signals are then converted by the ADC using a precise on-

chip oscillator clock. At the beginning of the conversion phase of the ADC, the BUSY output goes high and

remains high through a maximum-specified conversion time of t_CONV(see the Timing Requirements: CONVST

Control table).

•

Event 2: At this instant, the ADC has completed the conversion for all input channels and the BUSY output

goes to logic low. The falling edge of the BUSY signal indicates the end of conversion and that the internal

registers are updated with the conversion data. At this instant, the device is ready to output the correct

conversion results for all channels on the parallel output bus (DB[15:0]), or serial output lines (DOUTA,

DOUTB), or parallel byte bus (DB[7:0]).

Event 3: This example shows the data read operation in parallel interface mode with both CS and RD tied

together. After BUSY goes low, the first falling edges of CS and RD output the most significant 16 bits

conversion result of channel 1 (AIN_1) on the parallel output bus. The next falling edges of CS and RD output

the two least significant bits on DB1 and DB0 respectively. Similarly, the conversion results for the remaining

channels are output on the parallel bus on subsequent falling edges of the CS and RD signals in a sequential

manner. If all channels are not used in the conversion process, tie the unused channels to AGND or any

known voltage within the selected input range. The ADC always converts all analog input channels and the

results for unused channels are included in the output data stream, thus all unused channels must be tied to

AGND or known voltage within the range. The FRSTDATA output goes high on the first falling edges of the

CS and RD signals, indicating that the parallel bus is carrying the output result from channel 1. The

FRSTDATA output stays high until the AIN_1 data output is read out. On the next falling edges of the CS and

RD signals, FRSTDATA goes low and stays low if the CS and RD inputs are low.

•

Event 4: After the conversion results for all analog channels are output from the device, the data frame can

be terminated by pulling the CS and RD signals to logic high. The parallel bus and FRSTDATA output go to

tri-state until the entire sequence is repeated beginning from event 1.

Events 1 and 2 are common to all interface modes of operation (parallel or serial or parallel byte).

41

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

7.4.2.2.2 Simultaneous Sampling Two Sets of Input Channels

The ADS8598S allows two sets of analog input channels to be simultaneously sampled. In order to do so, the

CONVSTA and CONVSTB signals must be separate control inputs (as shown in 图 68) and the device must not

operate in any oversampling mode. Electrical grid relay protection is an application that can benefit from being

able to sample the inputs in two groups. The delay of the signal through the voltage channels is often different

from the delay on the channels measuring current. The difference in delay created by the voltage and current

signal paths can be corrected by adjusting the sampling of the two groups of inputs (voltage and current) to the

device.

The timing diagram of 图 68 shows the sequence of events described in this section.

CONVSTA

CONVSTB

BUSY

CS and RD

AIN_1

[17:2]

AIN_1

[1:0]

AIN_8

[17:2]

AIN_8

[1:0]

DB[15:0]

FRSTDATA

1a

1b

2

3

4

图 68. Simultaneous Sampling of All Input Channels in Parallel Interface Timing Diagram

There are four events that describe the internal operation of the device when pairs of input channels are

simultaneously sampled and the data are read back. These events are:

•

Event 1(a): A rising edge on the CONVSTA signal initiates simultaneous sampling of the first set of analog

input channels (channels 1-4). The sampling circuits on the first set of analog input channels enter hold mode

and the input signals on these channels are sampled at the same instant. The ADC does not begin

conversion until the input signals on the second set of channels are sampled.

•

Event 1(b): A rising edge on the CONVSTB signal initiates simultaneous sampling of the second set of

analog input channels (channels 5-8). The sampling circuits for the second set of analog input channels enter

hold mode and the input signals on these channels are sampled at the same instant. When the rising edges

of both the CONVSTA and CONVSTB signals have occurred, the ADC converts all sampled signals using a

precise, on-chip oscillator clock. At the beginning of the conversion phase of the ADC, the BUSY output goes

high and remains high through a maximum-specified conversion time of t_CONV(see the Timing Requirements:

CONVST Control table).

•

Event 2: Same as event 2 in the Simultaneous Sampling on All Input Channels section.

Event 3: Same as event 3 in the Simultaneous Sampling on All Input Channels section.

Event 4: Same as event 4 in the Simultaneous Sampling on All Input Channels section.

Events 1(a), 1(b), and 2 are common to all interface modes of operation (parallel, serial, or parallel byte).

42

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

7.4.2.3 Data Read Operation

The ADS8598S updates the internal data registers with the conversion data for all analog channels at the end of

every conversion phase (when BUSY goes low). As described in the Timing Requirements: Data Read Operation

table, if the output data are read after BUSY goes low, then the device outputs the conversion results for the

current sample. However, if the output data are read when BUSY is high, then the device outputs conversion

results for the previous sample. Under both conditions, the device supports three interface options as explained

in 表 7 depending on the status of the PAR/SER/BYTE SEL and DB15/BYTE SEL pins.

表 7. Data Read Back Interface Mode Selection

SELECTED INTERFACE MODE

Parallel interface

PAR/SER/BYTE SEL

DB15/BYTE SEL

0

1

x

1

0

Parallel byte interface

Serial interface

7.4.2.3.1 Parallel Data Read

The ADS8598S supports a parallel interface mode for reading the device output data using the control inputs (CS

and RD) the parallel output bus (DB[15:0]), the FRSTDATA indicator, and the BUSY indicator. This interface

mode is selected by applying a logic low input on the PAR/SER/BYTE SEL input pin. Depending on the

application requirements, the CS and RD control inputs can be tied together or used as separate control inputs in

the parallel interface mode.

For applications that use only one device in the system and does not share the parallel output bus with any other

devices, the CS and RD input signals can be tied together. Alternatively, the CS signal can be permanently tied

low and the RD signal can be used to clock the data out of the device. The timing diagram for this mode of

operation is described in the Timing Requirements: Parallel Data Read Operation, CS and RD Tied Together

table. In this mode the parallel output bus, DB[15:0], is activated (comes out of tri-state) on the falling edge of the

CS/RD signal. At the first falling edge of the CS/RD signal, the most significant 16 bits for output data of channel

1 become available on the parallel bus to be read by the digital host. At the next falling edge of the CS/RD

signal, the least significant two bits for output data of channel 1 become available on DB15 and DB14,

respectively. The DB[13:0] pins are held low in this pulse. The FRSTDATA output is held high during the data

readback of channel 1, indicating channel 1 data are ready to be read back. The output data for the remaining

channels are clocked out on the parallel bus on subsequent falling edges of the CS and RD signal in a

sequential manner. At the third falling edge of the RD signal, the FRSTDATA output goes low and is held low

during this time period when CS and RD are held low.

For applications that use multiple devices in the system, the CS and RD input signals must be driven separately.

The timing diagram for this mode of operation is described in the Timing Requirements: Parallel Data Read

Operation, CS and RD Separate table. A falling edge of the CS input can be used to activate the parallel bus for

a particular device in the system. The RD signal clocks the conversion data out of the device. At the first falling

edge of the RD signal, the most significant 16 bits for output data of channel 1 become available on the parallel

bus to be read by the digital host. At the next falling edge of the RD signal, the least significant two bits for the

output data of channel 1 become available on DB15 and DB14, respectively. The DB[13:0] pins are held low in

this pulse. The FRSTDATA output is held high during the data readback of channel 1, indicating channel 1 data

are ready to be read back. On subsequent falling edges of the RD signal, the output data for the remaining

channels are clocked out on the parallel bus in a sequential manner. At the third falling edge of the RD signal,

the FRSTDATA output goes low and remains low until going to tri-state at the next rising edge of the CS signal.

7.4.2.3.2 Parallel Byte Data Read

The ADS8598S supports a parallel byte interface mode for reading the device output data using the control

inputs (CS and RD), the parallel output bus (DB[15:0]), the FRSTDATA indicator, and the BUSY indicator. This

interface mode is selected by applying a logic high input on the PAR/SER/BYTE SEL input pin and a logic high

input on the DB15/BYTE SEL input pin. The parallel byte interface mode is very similar to the parallel interface

mode, except that the output data for each channel is read in three data transfers of 8-bit byte sizes.

The order of most significant byte (MSB byte) to least significant byte (LSB byte) is decided by the logic input

state of the DB14/HBEN pin. In parallel byte mode, the DB14/HBEN pin functions as a control input. When

DB14/HBEN pin is tied high, the MSB byte of the conversion results is output first followed by the Mid byte

followed by the LSB byte. This order is reversed when DB14/HBEN is tied to logic low.

43

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

The Timing Requirements: Byte Mode Data Read Operation table describes the data read back operation during

parallel byte mode when the DB14/HBEN pin is tied high. A falling edge of the CS input is used to activate the

parallel bus, DB[7:0] for the device. The RD signal is then used to clock the conversion data out of the device. In

this mode, three RD pulses are required to read the full data output for each analog channel. At the first falling

edge of the RD signal, the first byte of the channel 1 conversion result becomes available on DB[7:0]. This byte

is followed by the second and third bytes of conversion data on the next two falling edges of the RD signal. On

subsequent falling edges of the RD signal, the output data for the remaining channels are clocked out in chunks

of 8-bit bytes on DB[7:0] in a sequential manner. Thus, a total of 24 RD pulses are required to read the output

from all input channels of the ADS8598S.

In this mode, the FRSTDATA output goes high at the first falling edge of the RD signal. FRSTDATA remains high

for three RD pulses until channel one conversion result is output. At the fourth falling edge of the RD signal, the

FRSTDATA output goes low and remains low throughout the data read operation until going to tri-state at the

next rising edge of the CS signal.

The ADC internally appends additional zeros to the 18-bit output data to generate 24-bit data. 表 8 describes the

expected output on the three bytes for a given ADC converted code of 34567h for different DB14/HBEN settings.

表 8. Parallel BYTE Data Read Back

ADC OUTPUT CODE

DB14/HBEN

1ST BYTE

D1h

2ND BYTE

59h

3RD BYTE

C0h

1

0

34567h

C0h

59h

D1h

7.4.2.3.3 Serial Data Read

The ADS8598S supports a serial interface mode for reading the device output data. This interface mode is

selected by applying a logic high input on the PAR/SER/BYTE SEL input pin and a logic low input on the

DB15/BYTE SEL input pin. This interface mode uses a CS control input, a communication clock input (SCLK),

BUSY and FRSTDATA output indicators, and serial data output lines DOUTA and DOUTB.

图 5 illustrates the timing diagram for data read in serial mode for one channel of the ADC, framed by the CS

signal. When the CS input is high, the serial data output and FRSTDATA output lines are in tri-state and the

SCLK input is ignored. On the falling edge of the CS signal, the output lines become active and the MSB of the

conversion result comes out on DOUTA, DOUTB. The MSB can be read by the host processor on the next falling

edge of the SCLK signal. The remaining 17 bits of the conversion result are output on the subsequent rising

edges of the SCLK signal and can be read by the host processor on the corresponding falling edges. Thus, a

total of 18 SCLK cycles are required to clock out 18 bits of conversion result for each channel and the same

process can be repeated for the remaining channels in an ascending order. The CS input can be left at a logic

low level for the entire data retrieval process for all analog channels or used to frame the retrieval of the 18-bit

output data for each analog channel.

The ADS8598S can output the conversion results on one or both of the serial data output lines, DOUTA and

DOUTB. The conversion results from the first set of channels (channels 1-4) appear first on DOUTA, followed by

the second set of channels (channels 5-8) if only DOUTA is used for reading data. This order is reversed for

DOUTB, in which the second set of channels appear first followed by the first set of channels. The use of both

data output lines reduces the time needed for data retrieval and a higher throughput can therefore be achieved in

this mode.

The FRSTDATA output is in tri-state when the CS signal is high. As illustrated in 图 5, FRSTDATA goes high on

the first falling edge of the CS signal when the MSB of channel 1 is output on DOUTA. The FRSTDATA output

remains high for the next 18 SCLK cycles until all data bits of channel 1 are read from the device. The

FRSTDATA output returns to a logic low level at the 18th falling edge of the SCLK signal. If data are also read on

DOUTB in serial mode, then FRSTDATA remains high when the first channel of the second set of channels is

read from the device. The high state of FRSTDATA corresponds to channel 5 for the ADS8598S.

Based on the previous description of the different pins in serial interface mode, conversion data can be read out

of the device in several different ways. Some example recommendations are provided below:

•

The conversion data can be read out of the device using only one of the two serial output lines, DOUTA or

DOUTB. In this case, using DOUTA for output data read back is recommended because channel 1 data

appear first on DOUTA followed by the data for other channels in ascending order. To read the data for all

channels, provide a total of 18 × 8 = 144 SCLK cycles. This entire data frame can be created within a single

CS pulse or each group of 18 SCLK cycles can be individually framed by the CS signal. The primary

44

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

disadvantage of using just one data line for reading conversion data is that the throughput is reduced if a data

read operation is performed after conversion. 图 69 shows this operation.

•

Alternatively, only DOUTB can be used for reading the conversion data from all channels. In this case,

everything else remains the same and the output bit stream contains data for all channels in the following

order: channels 5, 6, 7, 8, 1, 2, 3, and 4. 图 69 shows this operation.

CS

SCLK

Channel 1

Channel 5

Channel 2

Channel 6

Channel 3

Channel 7

Channel 4

Channel 8

Channel 5

Channel 1

Channel 6

Channel 2

Channel 7

Channel 3

Channel 8

Channel 4

DOUTA

DOUTB

FRSTDATA

图 69. Data Read Back in the Serial Interface Using Either DOUTA or DOUTB Timing Diagram

•

In order to minimize the time for the data read operation in serial mode, both DOUTA and DOUTB can be

used to read data out of the device. In this case, the conversion results from the first set of channels

(channels 1-4) appear on DOUTA and the conversion results from the second set of channels (channels 5-8)

appear first on DOUTB. To read the data for all channels, provide a total of 18 × 4 = 72 SCLK cycles. This

entire data frame can be created within a single CS pulse or each group of 18 SCLK cycles can be

individually framed by the CS signal. 图 70 shows this operation.

CS

SCLK

DOUTA

Channel 1

Channel 5

Channel 2

Channel 6

Channel 3

Channel 7

Channel 4

Channel 8

DOUTB

FRSTDATA

图 70. Data Read Back in the Serial Interface Using Both DOUTA and DOUTB Timing Diagram

7.4.2.3.4 Data Read During Conversion

The ADS8598S supports data read operation when the BUSY output is high and the internal ADC is converting.

The ADC outputs conversion results for previous sample if data read back is performed during an ongoing

conversion. Any of the three interface modes (parallel, parallel byte, or serial) in any combination of oversampling

modes can be used to read the device output during an ongoing conversion. The data read back during

conversion mode allows faster throughput to be achieved from the device. There is no degradation in

performance if data are read from the device during the conversion process, using any of the three interface

modes. All channel data must be read before the BUSY signal goes low.

45

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

The Timing Requirements: Data Read Operation table describes the timing diagram for data read back during

conversion. The timing specification t_{DZ_CSBSY}(the delay between the rising edge of the CS signal and the falling

edge of the BUSY signal) must be met because the output data registers are updated with the current conversion

results just before the falling edge of the BUSY signal and any read operation during this time can corrupt the

register update.

7.4.2.4 Oversampling Mode of Operation

The ADS8598S supports the oversampling mode of operation using an on-chip averaging digital filter, as

explained in the Digital Filter and Noise section. The device can be configured in oversampling mode by the

OS[2:0] pins (see the OS[2:0] section). 图 71 shows a typical timing diagram for the oversampling mode of

operation. The input on the OS pins is latched on the falling edge of the BUSY signal to configure the

oversampling rate for the next conversion.

t_CONV

CONVSTA

CONVSTB

18µs

8.6µs

3.8µs

BUSY

OS = 0 OS = 2OS = 4

CS RD

&

AIN_1

[17:2]

AIN_1

[1:0]

AIN_8

[17:2]

AIN_8

[1:0]

DB[15:0]

图 71. OSR Mode Operation Timing Diagram

In the oversampling mode of operation, both the CONVSTA and CONVSTB signals must be tied together or

driven together. As shown in 图 71, the BUSY signal duration varies with the OSR setting because the

conversion time increases with increases in OSR. The high time for the BUSY signal increases with the OSR

setting, as listed in the Timing Requirements: CONVST Control table.

For any particular OSR setting, the maximum achievable throughput per channel is specified in 表 1. If the

application is running at a lower throughput, then a higher OSR setting can be selected for further noise

reduction and SNR improvement. To maximize the throughput per channel, perform a data read when BUSY is

high and a conversion is ongoing in OSR mode. This process enables data read for the previous conversion (see

the Data Read During Conversion section). At the falling edge of the BUSY signal, the internal data registers are

updated with the new conversion data; thus the read operation must complete and CS must be pulled high for at

least t_{DZ_CSBSY}before BUSY goes low (see the Timing Requirements: Data Read Operation table).

46

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

Oversampling the input signal reduces noise during the conversion process, thus reducing the histogram code

spread for a dc input signal to the ADC. 图 72 to 图 77 show the effect of oversampling on the output code

spread in a dc histogram plot.

1000

800

600

400

200

0

1100

880

660

440

220

0

-6 -5 -4 -3 -2 -1

0

1

2

3

4

5

6

-6 -5 -4 -3 -2 -1

0

1

2

3

4

5

6

7

Output Codes

D062

D064

D066

D063

D065

D067

Mean = 0.03, sigma = 1.52

图 72. DC Histogram for OSR2

Mean = –0.33, sigma = 1.39

图 73. DC Histogram for OSR4

1200

960

720

480

240

0

1400

1120

840

560

280

0

-5

-4

-3

-2

-1

0

1

2

3

4

5

-5

-4

-3

-2

-1

0

1

2

3

4

5

Output Codes

Mean = –0.25, sigma = 1.09

图 74. DC Histogram for OSR8

Mean = –0.33, sigma = 0.89

图 75. DC Histogram for OSR16

1700

1360

1020

680

340

0

2500

2000

1500

1000

500

0

-3

-2

-1

0

1

2

3

4

-3

-2

-1

0

1

2

3

Output Codes

Mean = –0.44, sigma = 0.75

图 76. DC Histogram for OSR32

Mean = –0.02, sigma = 0.72

图 77. DC Histogram for OSR64

47

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

In OSR modes, the device adds a digital filter at the output of the ADC. The digital filter affects the frequency

response of the entire data acquisition system including the internal low-pass analog filter and the oversampling

digital filter. 图 78 to 图 83 show the frequency response curves for different OSR settings in the ±10-V range.

50

0

50

0

-50

-100

-150

-200

-250

-100

-150

-200

-250

1

10

100

1k

10k

100k

1M

10M

1

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

D068

D069

AVDD = 5 V, DVDD = 5 V, T_A= 25°C, input range = ±10 V

图 78. Digital Filter Response for OSR = 2

图 79. Digital Filter Response for OSR = 4

50

0

-50

0

-50

-100

-150

-200

-250

-100

-150

-200

-250

1

10

100

1k

10k

100k

1M

10M

1

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

D070

D071

AVDD = 5 V, DVDD = 5 V, T_A= 25°C, input range = ±10 V

图 80. Digital Filter Response for OSR = 8

图 81. Digital Filter Response for OSR = 16

50

0

-50

0

-50

-100

-150

-200

-250

-100

-150

-200

-250

1

10

100

1k

10k

100k

1M

10M

1

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

D072

D073

AVDD = 5 V, DVDD = 5 V, T_A= 25°C, input range = ±10 V

图 82. Digital Filter Response for OSR = 32

图 83. Digital Filter Response for OSR = 64

48

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The ADS8598S enables high-precision measurement of up to eight analog signals simultaneously. The device is

a fully-integrated data acquisition systems based on an 18-bit successive approximation (SAR) analog-to-digital

converter (ADC). The device includes an integrated analog front-end for each input channel and an integrated

voltage reference with a precision reference buffer. As such, this device does not require any additional active

circuits for driving the analog input pins of the ADC.

8.2 Typical Applications

8.2.1 8-Channel, Data Acquisition System (DAQ) for Power Automation

PT Input

CT Input

±10-V Amplitude

f = 50 Hz, 60 Hz

∆ꢀ

∆ꢀ = Measured Phase Difference

Between Signals

AVDD = 5 V⁽¹⁾

DVDD = 3.3 V

1µF

0.1µF

REGCAP1, REGCAP2⁽²⁾

AVDD

DVDD

R_1P

AIN_1P

1 MΩ

ADS8598S

18-Bit

SAR

ADC

Driver

3^rd-Order

LPF

PGA

C₁

REFCAPA

1 MΩ

AIN_1GND

R_1M

10 µF

REFCAPB

REFGND

REFIN/REFOUT

2.5-V

V_REF

10 µF

R_8P

AIN_8P

1 MΩ

REFGND

DVDD

18-Bit

SAR

ADC

Driver

3^rd-Order

LPF

PGA

C₈

1 MΩ

AIN_8GND

R_8M

REFSEL

AGND

Typical 50-Hz, 60-Hz

Sine-Wave from PT, CT

Balanced RC Filter

on Each Input

(1) Decoupling the AVDD capacitor applies to each AVDD pin.

(2) REGCAP1 and REGCAP2: each pin requires separate decoupling capacitors.

图 84. 8-Channel DAQ for Power Automation Using the ADS8598S

49

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

Typical Applications (接下页)

This application example involves the measurement of electrical variables in a power system. The accurate

measurement of electrical variables in a power grid is extremely critical because this measurement helps

determine the operating status and running quality of the grid. Such accurate measurements also help diagnose

potential problems with the power network so that these problems can be resolved quickly without having any

significant service impact. The key electrical parameters include amplitude, frequency, and phase measurement

of the voltage and current on the power lines. These parameters are important to enable metrology in the power

automation system to perform harmonic analysis, power factor calculation, power quality assessment, and so

forth.

8.2.1.1 Design Requirements

To begin the design process, a few parameters must be decided upon. The designer must know the following:

•

Output range of the potential transformers (elements labeled PT in 图 84)

Output range of the current transformers (elements labeled CT in 图 84)

Input impedance required from the analog front-end for each channel

Fundamental frequency of the power system

Number of harmonics that must be acquired

Type of signal conditioning required from the analog front-end for each channel

8.2.1.2 Detailed Design Procedure

For the ADS8598S, each channel incorporates an analog front-end composed of a programmable gain amplifier

(PGA), analog low-pass filter, and ADC input driver. The analog input for each channel presents a constant

resistive impedance of 1 MΩ independent of the ADC sampling frequency and range setting. The high input

impedance of the analog front-end circuit allows direct connection to potential transformers (PT) and current

transformers (CT). The ADC inputs can support up to ±10-V or ± 5-V bipolar inputs and the integrated signal

conditioning eliminates the need for external amplifiers or ADC driver circuits.

The PT and CT used in the system, as illustrated in 图 84, have a ±10-V output range. Although PT and CT

provide isolation from the power system, a series resistor must be placed on the analog input channels. The

series resistor helps limit the input current to ±10 mA if the input voltages exceed ±15 V. For applications that

require protection against overvoltage or fast transient events beyond the specified absolute maximum ratings of

the device, an external protection clamp circuit using transient voltage suppressors (TVS) and ESD diodes is

recommended.

A low-pass filter is used on each analog input channel to eliminate high-frequency noise pickup and minimize

aliasing. 图 85 shows an example of the recommended configuration for an input RC filter. A balanced RC filter

configuration matches the external source resistance on the positive path (AIN_nP) with an equal resistance on

the negative path (AIN_nGND). Matching the source impedance in the positive and negative path allows for

better common-mode noise rejection and helps maintain the dc accuracy of the system by canceling any

additional offset error contributed by the external series resistance.

10 V

0 V

ADS8598S

ESD

-10 V

1 MW

4.3 kΩ

AIN_nP

18-Bit

SAR

ADC

3^rd-Order

LPF

5.6 nF

COG

ADC

Driver

PGA

AIN_nGND

1 MW

Low-Pass Filter with

Matched Source

Resistance

Signal from PT, CT

50 Hz, 60 Hz

ESD

图 85. Input RC Low-Pass Filter

50

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

Typical Applications (接下页)

The primary goal of the data acquisition system illustrated in 图 84 is to measure up to 20 harmonics in a 60-Hz

power network. Thus, the analog front-end must have sufficient bandwidth (as shown in 公式 1) to detect signals

up to 1260 Hz.

f_MIN

=

(

20 +1 ì60Hz =1260Hz

)

(1)

Based on the bandwidth calculated in 公式 1, the ADS8598S is set to simultaneously sample all eight channels

at 20 kSPS, which is sufficient throughput to clearly resolve the highest harmonic component of the input signal.

The pass band of the low-pass filter configuration illustrated in 图 85 is determined by the –3-dB frequency,

calculated according to 公式 2.

1

f_-3dB

=

= 3.3kHz

2pì

(

R1+R2

)

ìC_f2pì

(

4.3kW + 4.3kW ì5.6nF

)

(2)

The value of C_Fis selected as 5.6 nF, a standard capacitance value available in 0603-size surface-mount

components. In combination with the resistor R_F, this low-pass filter provides sufficient bandwidth to

accommodate the required 20 harmonics for the input signal of 60 Hz.

The ADS8598S can operate with either the internal voltage reference or an external reference. The Internal

Reference section describes the electrical connections and recommended bypass capacitors when using the

internal reference. Alternatively for applications that require a higher precision voltage reference, 图 86 shows an

example of an external reference circuit. The REF5025 provides a very low drift, and very accurate external 2.5-

V reference. The resistor R_FILTand capacitor C_FILTform a low-pass filter to reduce the broadband noise and

minimize the resulting effect of the reference noise on the system performance.

AVDD=5V

R_FILT

V_IN

V_REF

REFIN/ REFOUT

100 ꢀ

C_FILT

1 µF

REF5025

0.220ꢀ

10 µF

REFCAPA

REFCAPB

TRIM/NR

GND

ADS8598S

10 µF

REFGND

AGND

REFSEL

图 86. External Reference Circuit for the ADS8598S

51

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

Typical Applications (接下页)

8.2.1.3 Application Curve

图 87 shows the frequency spectrum of the data acquired by the ADS8598S for a sinusoidal, ±10-V input at 60

Hz.

The ac performance parameters measured by this design are:

•

SNR = 93.95 dB; SINAD = 93.75 dB

THD = –105 dB; SFDR = 108.7 dB

0

-50

-100

-150

-200

0

500

1000

1500

2000

Frequency (Hz)

D075

图 87. Frequency Spectrum for a Sinusoidal ±10-V Signal at 50 Hz

8.2.2 Extending the Analog Input Voltage Range

Multiple real-world applications require the ADC to acquire input voltages outside the ±10-V range. This

requirement can be achieved by scaling the input signal to match the ADC input voltage range. The existing

solutions achieve this matching by using precision-matched resistors to attenuate the signal and buffering the

attenuated signal using a suitable amplifier to drive the ADC input. This attenuation needs precision resistors,

amplifiers with a required high-voltage supply to buffer the signals. Care must be taken to avoid loading of the

source by the attenuator.

0 V

ESD

1 MΩ

R_S

High Voltage

Input

18-Bit

SAR

ADC

3^rd-Order

LPF

PGA

R_S

1 MΩ

ESD

图 88. High-Voltage DAQ System

8.2.2.1 Design Requirements

To begin the design process, a few parameters must be decided upon. The designer must know the following:

•

Input range of the signal

Allowed error in the measured output

52

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

Typical Applications (接下页)

8.2.2.2 Detailed Design Procedure

For the ADS8598S, each channel incorporates an analog front-end with a constant resistive input impedance of

1 MΩ. The input resistance is independent of the PGA range selection or ADC sampling frequency. The input

impedance along with the feedback resistance of the programmable gain amplifier (PGA) help achieve the

required attenuation for the input high voltage signal to feed the ADC inputs.

As illustrated in 图 88, a series resistance can be added to the AIN_nP and AIN_nGND pins. As shown in 公式 3,

this series resistance increases the input impedance. When using high values of series resistances, avoid using

a parallel capacitor between the AIN_nP and AIN-nGND pins. The leakage current of the capacitor introduces

additional gain error.

R_{eff _imp}=1MW+R_S

(3)

The increased series resistance along with the PGA feedback resistance increases the attenuation offered by the

PGA, thus increasing the allowed input voltage range. 公式 4 calculates the increased input voltage range.

Conversely, 公式 5 can be used to calculate the value of series resistance R_Sbased on the required input

voltage range.

V_{RANGE _ ADC}ìR_{eff _imp}

V_max

=

1MW

(4)

≈

’

V_max

V_{RANGE _ ADC}

R_S=∆

-1÷

MW

∆

÷

«

◊

(5)

The additional series resistance introduces gain error in the system because the external resistors have

mismatch and are not matched to the internal impedance of the ADC. Thus, high-accuracy, low-drift external

resistors must be used. The gain error resulting from mismatch in external resistor and internal resistor must be

calibrated to achieve the required accuracy levels.

8.2.2.2.1 Performance Results

表 9 shows the worst-case accuracy achieved across input range for high-voltage data capture using the design

technique described previously at 25°C and 70°C. The R_Sused for these experiments were chosen to have 0.1%

tolerance and temperature drift of 50 ppm/°C.

表 9. Accuracy With an Extended Input Voltage Range

ACCURACY WITHOUT

CALIBRATION

ACCURACY WITH

CALIBRATION

ADC RANGE

R_S(MΩ)

V_IN(Max)

TEMPERATURE

25°C

70°C

25°C

70°C

25°C

70°C

25°C

70°C

25°C

70°C

0.726%

0.680%

0.577%

0.502%

0.205%

0.128%

0.926%

0.753%

0.709%

0.644%

0.003%

0.009%

0.004%

0.003%

0.001%

0.004%

0.002%

0.006%

0.004%

0.006%

±10 V

3

±40 V

±10 V

±5 V

1

0.2

3

±20 V

±12 V

±20 V

±15 V

±5 V

2

53

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

9 Power Supply Recommendations

The ADS8598S uses two separate power supplies: AVDD and DVDD. The AVDD supply provides power to the

ADC and internal circuits, and DVDD is used for the digital interface. AVDD and DVDD can be set independently

to voltages within the permissible range.

The AVDD supply can be set in the range of 4.75 V to 5.25 V. A low-noise, linear regulator is recommended to

generate the analog supply voltage. The device has four AVDD pins. Each AVDD pin must be decoupled with

respect to AGND using a 1-µF capacitor. Place the 1-µF capacitor as close to the supply pins as possible.

The DVDD supply is used to drive the digital I/O buffers and can be set in the range of 2.3 V to a maximum value

equal to the AVDD voltage. This range allows the device to interface with most state-of-the-art processors and

controllers. Place a 1-µF (minimum 100-nF) decoupling capacitor in close proximity to the DVDD supply to

provide the high-frequency digital switching current.

There are no specific requirements with regard to the power-supply sequencing of the device. However, issue a

reset after the supplies are powered and are stable to ensure the device is properly configured.

图 89 shows a typical PSRR curve with decoupling capacitors.

-70

± 5 V

± 10 V

-80

-90

-100

-110

-120

-130

-140

-150

1

10

100

Input Frequency (kHz)

D044

图 89. PSRR Across Frequency (With Decapacitors)

54

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

10 Layout

10.1 Layout Guidelines

图 90 and 图 91 illustrate a PCB layout example for the ADS8598S.

•

Partition the PCB into analog and digital sections. Care must be taken to ensure that the analog signals are

kept away from the digital lines. This layout helps keep the analog input and reference input signals away

from the digital noise. In this layout example, the analog input and reference signals are routed on the left

side of the board and the digital connections are routed on the right side of the board.

•

Using a single common ground plane is strongly recommended. For designs requiring a split analog and

digital ground planes, the analog and digital ground planes must be at the same potential joined together in

close proximity to the devices.

Power sources to the ADS8598S must be clean and well-bypassed. As a result of dynamic currents during

conversion, each AVDD must have a decoupling capacitor to keep the supply voltage stable. Use wide traces

or a dedicated analog supply plane to minimize trace inductance and reduce glitches. Using a 1-µF, X7R-

grade, 0603-size ceramic capacitor is recommended in close proximity to each analog (AVDD) supply pin.

Bypass capacitors for AVDD pins 1 and 48 are located on the top layer; see 图 90. AVDD supply pins 37 and

38 are connected to bypass capacitors in the bottom layer using an isolated via (1); see 图 91. A separate via

(2) is used to connect the bypass capacitor to the AVDD plane.

•

For decoupling the digital (DVDD) supply pin, a 1-µF, X7R-grade, 0603-size ceramic capacitor is

recommended. The DVDD bypass capacitor is located in the bottom layer; see 图 91.

REFCAPA and REFCAPB must be shorted together and decoupled to REFGND using a 10-µF, X7R-grade,

0603-size ceramic capacitor placed in close proximity to the pins of the device. This capacitor is placed on

the top layer and is directly connected to the device pins. Avoid placing vias between the REFCAPA,

REFCAPB pins and the decoupling capacitor.

•

The REFIN/REFOUT pin also must be decoupled to REFGND with a 10-µF, X7R-grade, 0603-size ceramic

capacitor if the internal reference of the device is used. The capacitor must be placed on the top layer in

close to the device pin. Avoid placing vias between the REFIN/REFOUT pin and the decoupling capacitor.

•

The REGCAP1 and REGCAP2 pins must be decoupled to GND using a separate 1-µF, X7R-grade, 0603-size

ceramic capacitor on each pin.

All ground pins (AGND) must be connected to the ground plane using short, low-impedance paths and

independent vias to the ground plane. Connect REFGND to the common GND plane.

For the optional channel input low-pass filters, ceramic surface-mount capacitors, COG (NPO) ceramic

capacitors provide the best capacitance precision. The type of dielectric used in COG (NPO) ceramic

capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes.

10.2 Layout Example

图 90 and 图 91 illustrate a recommended layout for the ADS8598S along with proper decoupling and reference

capacitor placement and connections.

55

ADS8598S

ZHCSGU4 –SEPTEMBER 2017

www.ti.com.cn

Layout Example (接下页)

!ë55 ꢀlane

5ë55 ꢀlane

AIN_1P

AIN_1GND

AIN_2P

GND

AIN_2GND

AIN_3P

GND

Lsolated

ëia (1)

AVDD (2)

AIN_3GND

AIN_4P

5igital

GND

DVDD (2)

AIN_4GND

AIN_5P

Lnputs and

hutputs

AIN_5GND

AIN_6P

AIN_6GND

AIN_7P

AIN_7GND

AIN_8P

5ë55

Lsolated

ëia (1)

AIN_8GND

AVDD

GND

图 90. Top Layer Layout

GND

AVDD

!ë55 tlane

5ë55 tlane

AVDD

Lsolaꢀed

ëia (1)

DVDD

GND

Lsolaꢀed

ëia

GND

图 91. Bottom Layer Layout

56

ADS8598S

www.ti.com.cn

ZHCSGU4 –SEPTEMBER 2017

11 器件和文档支持

11.1 文档支持

11.1.1 相关文档

请参阅如下相关文档：

•

《使用 16 位 SAR ADC 且具有 ±10V 测量范围的高精度模拟前端参考设计》

《AN-2029 处理和工艺建议》

《REF50xx 低噪声、极低漂移、高精度电压基准》

11.2 接收文档更新通知

要接收文档更新通知，请转至 TI.com 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品信

息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知

和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

57

PACKAGE OUTLINE

PM0064A

LQFP - 1.6 mm max height

SCALE 1.400

PLASTIC QUAD FLATPACK

10.2

9.8

B

NOTE 3

64

49

PIN 1 ID

1

48

10.2

9.8

12.2

TYP

11.8

NOTE 3

33

16

32

17

A

0.27

0.17

64X

60X 0.5

4X 7.5

0.08

C A B

C

(0.13) TYP

SEATING PLANE

0.08

SEE DETAIL A

0.25

GAGE PLANE

(1.4)

1.6 MAX

0.05 MIN

0.75

0.45

0 -7

DETAIL

SCALE: 14

A

DETAIL A

TYPICAL

4215162/A 03/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MS-026.

www.ti.com

EXAMPLE BOARD LAYOUT

PM0064A

LQFP - 1.6 mm max height

PLASTIC QUAD FLATPACK

SYMM

49

64

64X (1.5)

1

48

64X (0.3)

SYMM

(11.4)

60X (0.5)

(R0.05) TYP

33

16

17

32

(11.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

0.05 MAX

ALL AROUND

EXPOSED METAL

METAL

0.05 MIN

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4215162/A 03/2017

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

7. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).

www.ti.com

EXAMPLE STENCIL DESIGN

PM0064A

LQFP - 1.6 mm max height

PLASTIC QUAD FLATPACK

SYMM

64

49

64X (1.5)

1

48

64X (0.3)

SYMM

(11.4)

60X (0.5)

(R0.05) TYP

16

33

17

32

(11.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:8X

4215162/A 03/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	ADS8598S
厂家：	TEXAS INSTRUMENTS
描述：	采用单电源并具有双极性输入的 18 位 200kSPS 8 通道同步采样 ADC
文件：	总66页 (文件大小：1910K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS8598S [TI]

相关型号：

ADS8598SIPM

ADS8598SIPMR

ADS8608A8A

ADS8608A8A-75

ADS8608A8A-75A

ADS8616A8A

ADS8616A8A-75

ADS8616A8A-75A

ADS8634

ADS8634SRGER

ADS8634SRGET

ADS8638