ADS8688IDBTR [TI]
具有双极输入范围的 16 位 500kSPS 8 通道单电源 SAR ADC | DBT | 38 | -40 to 125;
| 型号： | ADS8688IDBTR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有双极输入范围的 16 位 500kSPS 8 通道单电源 SAR ADC | DBT | 38 | -40 to 125 |
| 文件： | 总66页 (文件大小：2606K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS8684, ADS8688
ZHCSCR1B –JULY 2014–REVISED AUGUST 2014
ADS868x 具有双极输入范围的 16 位，500kSPS，4 通道和 8 通道单电源
逐次逼近寄存器 (SAR) 模数转换器 (ADC)
1 特性
2 应用
1
•
•
具有集成模拟前端的 16 位 ADC
•
•
•
电力自动化
支持自动和手动两种扫描模式的 4 通道和 8 通道多
路复用器 (MUX)
保护中继器
PLC 模拟输入模块
•
独立于通道的可编程输入范围：
3 说明
–
–
双极：±10.24V、±5.12V 和 ±2.56V
单极：0V 到 10.24V 和 0V 到 5.12V
ADS8684 和 ADS8688 分别为 4 通道和 8 通道集成数
据采集系统，它们基于 16 位逐次逼近 (SAR) 模数转
换器 (ADC)，工作时的吞吐量可达
•
•
•
•
•
5V 模拟电源：1.65V 到 5V I/O 电源
恒定的阻性输入阻抗：1MΩ
输入过压保护：高达 ±20V
低漂移的片上 4.096V 基准电压
出色的性能：
500kSPS。 这些器件提供了用于各输入通道的集成模
拟前端电路（过压保护高达 ±20V）、支持自动和手动
两种扫描模式的 4 通道或 8 通道多路复用器、以及低
温度漂移的片上 4.096V 基准电压。 采用 5V 单模拟电
源供电时，器件上的各输入通道均可支持 ±10.24V、
±5.12V 和 ±2.56V 的实际双极输入范围以及 0V 到
10.24V 和 0V 到 5.12V 的单极输入范围。模拟前端在
所有输入范围内的增益均经过精确微调，以确保高直流
精度。 输入范围的选择可通过软件进行编程，各通道
输入范围的选择相互独立。 该器件提供了一个
1MΩ 的恒定阻性输入阻抗（无论所选输入范围为
何）。
–
–
500kSPS 的总吞吐量
差分非线性 (DNL)：±0.5 最低有效位 (LSB)；
最大积分非线性 (INL)：±0.75 LSB
–
–
增益误差和偏移误差低漂移
信噪比 (SNR)：92dB；总谐波失真
(THD)：–102dB
–
低功耗：65mW
•
•
•
•
AUX 输入 → 直接连接到 ADC 输入
SPI™- 兼容接口，支持菊花链连接
工业温度范围：-40°C 至 125°C
TSSOP-38 封装 (9.7mm × 4.4mm)
ADS8684 和 ADS8688 提供了用于连接数字主机的简
单 SPI 兼容串行接口，并且支持以菊花链形式连接多
个器件。 数字电源可提供 1.65V 到 5.25V 范围内的电
压，因此可直接连接各种主机控制器。
DVDD
AVDD
1 M:
ADS8688
ADS8684
OVP
OVP
AIN_0P
AIN_0GND
2nd-Order
LPF
ADC
Driver
PGA
1 M:
1 M:
VB0
器件信息(1)
OVP
OVP
AIN_1P
AIN_1GND
2nd-Order
LPF
ADC
Driver
PGA
PGA
PGA
PGA
PGA
PGA
PGA
部件号
ADS868x
封装
封装尺寸（标称值）
1 M:
1 M:
VB1
TSSOP (38)
9.70mm x 4.40mm
OVP
OVP
AIN_2P
AIN_2GND
Digital
Logic
&
2nd-Order
LPF
ADC
Driver
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
1 M:
1 M:
CS
VB2
Interface
SCLK
SDI
OVP
OVP
增益误差与温度的关系曲线
AIN_3P
AIN_3GND
2nd-Order
LPF
ADC
Driver
1 M:
1 M:
0.05
VB3
----- ± 2.5*VREF
----- ± 1.25*VREF
----- ± 0.625*VREF
------ +2.5*VREF
------+1.25*VREF
SDO
OVP
OVP
AIN_4P
AIN_4GND
16-bit
SAR ADC
2nd-Order
LPF
ADC
Driver
0.03
DAISY
REFSEL
RST / PD
1 M:
1 M:
VB4
OVP
OVP
AIN_5P
AIN_5GND
0.01
-0.01
-0.03
-0.05
2nd-Order
LPF
ADC
Driver
Oscillator
1 M:
1 M:
VB5
OVP
OVP
AIN_6P
AIN_6GND
2nd-Order
LPF
ADC
Driver
REFCAP
REFIO
1 M:
1 M:
VB6
OVP
OVP
AIN_7P
AIN_7GND
2nd-Order
LPF
ADC
Driver
4.096V
Reference
1 M:
VB7
26
59
92
125
±40
±7
Free-Air Temperature (oC)
AUX_IN
AUX_GND
C026
AGND
DGND
REFGND
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SBAS582
ADS8684, ADS8688
ZHCSCR1B –JULY 2014–REVISED AUGUST 2014
www.ti.com.cn
目录
8.3 Feature Description................................................. 21
8.4 Device Functional Modes........................................ 31
8.5 Register Map........................................................... 43
Application and Implementation ........................ 50
9.1 Application Information............................................ 50
9.2 Typical Applications ................................................ 50
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 Handling Ratings....................................................... 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Timing Requirements: Serial Interface.................... 10
7.7 Typical Characteristics............................................ 11
Detailed Description ............................................ 20
8.1 Overview ................................................................. 20
8.2 Functional Block Diagram ....................................... 20
9
10 Power-Supply Recommendations ..................... 55
11 Layout................................................................... 55
11.1 Layout Guidelines ................................................. 55
11.2 Layout Example .................................................... 56
12 器件和文档支持 ..................................................... 57
12.1 文档支持................................................................ 57
12.2 相关链接................................................................ 57
12.3 商标....................................................................... 57
12.4 静电放电警告......................................................... 57
12.5 术语表 ................................................................... 57
13 机械封装和可订购信息 .......................................... 57
8
4 修订历史记录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2014) to Revision B
Page
•
更改了产品预览数据表............................................................................................................................................................ 1
Changes from Original (July 2014) to Revision A
Page
•
更改了产品预览数据表............................................................................................................................................................ 1
2
Copyright © 2014, Texas Instruments Incorporated
ADS8684, ADS8688
www.ti.com.cn
ZHCSCR1B –JULY 2014–REVISED AUGUST 2014
5 Device Comparison Table(1)
PRODUCT
ADS8684
ADS8688
RESOLUTION (Bits)
CHANNELS
4, single-ended
8, single-ended
SAMPLE RATE (kSPS)
16
16
500
500
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
6 Pin Configuration and Functions
DBT Package
TSSOP-38
(Top View, Not to Scale)
38
37
36
35
38
37
36
35
SDI
1
2
3
4
5
6
7
8
9
CS
SDI
1
2
3
4
5
6
7
8
9
CS
RST/PD
SCLK
SDO
DNC
RST/PD
SCLK
SDO
DNC
DAISY
REFSEL
REFIO
DAISY
REFSEL
REFIO
34 DVDD
34 DVDD
33
33
REFGND
REFCAP
AGND
REFGND
REFCAP
AGND
DGND
DGND
32
32
AGND
AGND
31 AGND
30 AVDD
31 AGND
30 AVDD
AVDD
AVDD
ADS8684
ADS8688
AUX_IN 10
29
28
27
26
25
24
23
22
21
20
AGND
AGND
NC
AUX_IN 10
29
28
27
26
25
24
23
22
21
20
AGND
11
12
13
14
15
11
12
13
14
15
AUX_GND
NC
AUX_GND
AIN_6P
AGND
AIN_5P
AIN_5GND
NC
NC
AIN_6GND
AIN_7P
NC
NC
NC
AIN_4P
NC
AIN_7GND
AIN_4GND
AIN_3P
AIN_3P
AIN_0P
AIN_0GND
AIN_1P
AIN_0P
AIN_0GND
AIN_1P
16
17
18
19
16
17
18
19
AIN_3GND
AIN_3GND
AIN_2P
AIN_2P
AIN2_GND
AIN2_GND
AIN_1GND
AIN_1GND
Pin Functions
PIN
NAME
I/O
DESCRIPTION
NO.
ADS8684
ADS8688
1
2
3
SDI
Digital input
Data input for serial communication.
Active low logic input.
RST/PD
DAISY
Digital input
Digital input
Dual functionality to reset or power-down the device.
Chain the data input during serial communication in daisy-chain mode.
Active low logic input to enable the internal reference.
When low, the internal reference is enabled; REFIO becomes an output that includes the VREF
4
REFSEL
Digital input
voltage.
When high, the internal reference is disabled; REFIO becomes an input to apply the external
VREF voltage.
Analog input,
output
5
6
REFIO
Internal reference output and external reference input pin. Decouple with REFGND on pin 6.
Reference GND pin; short to the analog GND plane.
Decouple with REFIO on pin 5 and REFCAP on pin 7.
REFGND
Power supply
7
8
9
REFCAP
AGND
Analog output
Power supply
Power supply
ADC reference decoupling capacitor pin. Decouple with REFGND on pin 6.
Analog ground pin. Decouple with AVDD on pin 9.
AVDD
Analog supply pin. Decouple with AGND on pin 8.
Copyright © 2014, Texas Instruments Incorporated
3
ADS8684, ADS8688
ZHCSCR1B –JULY 2014–REVISED AUGUST 2014
www.ti.com.cn
Pin Functions (continued)
PIN
NAME
ADS8688
I/O
DESCRIPTION
NO.
ADS8684
10
11
AUX_IN
Analog input
Analog input
Auxiliary input channel: positive input. Decouple with AUX_GND on pin 11.
Auxiliary input channel: negative input. Decouple with AUX_IN on pin 10.
Analog input channel 6: Positive input. Decouple with AIN_6GND on pin 13.
AUX_GND
12
13
14
15
NC
NC
NC
NC
AIN_6P
Analog input
Analog input
Analog input
Analog input
No connection for the ADS8684: this pin can be left floating or connected to AGND.
Analog input channel 6: negative input. Decouple with AIN_6P on pin 12.
No connection for the ADS8684: this pin can be left floating or connected to AGND.
AIN_6GND
AIN_7P
Analog input channel 7: positive input. Decouple with AIN_7GND on pin 15.
No connection for the ADS8684: this pin can be left floating or connected to AGND.
Analog input channel 7: negative input. Decouple with AIN_7P on pin 14.
No connection for the ADS8684: this pin can be left floating or connected to AGND.
AIN_7GND
16
17
18
19
20
21
22
23
AIN_0P
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input channel 0: positive input. Decouple with AIN_0GND on pin 17.
Analog input channel 0: negative input. Decouple with AIN_0P on pin 16.
Analog input channel 1: positive input. Decouple with AIN_1GND on pin 19.
Analog input channel 1: negative input. Decouple with AIN_1P on pin 18.
Analog input channel 2: positive input. Decouple with AIN_2GND on pin 21.
Analog input channel 2: negative input. Decouple with AIN_2P on pin 20.
Analog input channel 3: positive input. Decouple with AIN_3GND on pin 23.
Analog input channel 3: negative input. Decouple with AIN_3P on pin 22.
AIN_0GND
AIN_1P
AIN_1GND
AIN2_GND
AIN_2P
AIN_3GND
AIN_3P
Analog input channel 4: positive input. Decouple with AIN_4GND on pin 25.
No connection for the ADS8684: this pin can be left floating or connected to AGND.
24
25
26
27
NC
NC
NC
NC
AIN_4GND
Analog input
Analog input
Analog input
Analog input
Analog input channel 4: negative input. Decouple with AIN_4P on pin 24.
No connection for the ADS8684: this pin can be left floating or connected to AGND.
AIN_4P
AIN_5GND
AIN_5P
Analog input channel 5: positive input. Decouple with AIN_5GND on pin 27.
No connection for the ADS8684: this pin can be left floating or connected to AGND.
Analog input channel 5: negative input. Decouple with AIN_5P on pin 26.
No connection for the ADS8684: this pin can be left floating or connected to AGND.
28
29
30
31
32
33
34
35
36
37
38
AGND
Power supply
Power supply
Power supply
Power supply
Power supply
Power supply
Power supply
Do not connect
Digital output
Digital input
Analog ground pin
AGND
AVDD
AGND
AGND
DGND
DVDD
DNC
Analog ground pin
Analog supply pin. Decouple with AGND on pin 31.
Analog ground pin. Decouple with AVDD on pin 30.
Analog ground pin
Digital ground pin. Decouple with DVDD on pin 34.
Digital supply pin. Decouple with DGND on pin 33.
Do not connect this pin to any node; must remain floating.
Data output for serial communication
Clock input for serial communication
Active low logic input; chip-select signal
SDO
SCLK
CS
Digital input
4
Copyright © 2014, Texas Instruments Incorporated
ADS8684, ADS8688
www.ti.com.cn
ZHCSCR1B –JULY 2014–REVISED AUGUST 2014
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–20
MAX
UNIT
V
AIN_nP to AIN_nGND(2)
AIN_nP to AIN_nGND(3)
AIN_nGND to GND
20
–11
11
V
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
0.3
AVDD + 0.3
7
V
AUX_IN to GND
V
AVDD to GND or DVDD to GND
REFCAP to REFGND or REFIO to REFGND
GND to REFGND
V
5.7
V
0.3
V
Digital input pins to GND
Digital output pins to GND
Operating temperature range, TA
DVDD + 0.3
DVDD + 0.3
125
V
V
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) AVDD = 5 V or offers a low impedance of < 30 kΩ.
(3) AVDD = floating with an impedance > 30 kΩ.
7.2 Handling Ratings
MIN
MAX
UNIT
Tstg
Storage temperature range
–65
150
°C
Analog input pins
(AIN_nP; AIN_nGND)
–4000
–2000
–500
4000
2000
500
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001, all pins(1)
Electrostatic
discharge
V(ESD)
All other pins
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.75
1.65
NOM
5
MAX
5.25
UNIT
AVDD
DVDD
Analog supply voltage
Digital supply voltage
V
V
3.3
AVDD
7.4 Thermal Information
ADS8684,
ADS8688
TSSOP (PW)
38 PINS
68.8
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
19.9
30.4
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.3
ψJB
29.8
RθJC(bot)
NA
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2014, Texas Instruments Incorporated
5
ADS8684, ADS8688
ZHCSCR1B –JULY 2014–REVISED AUGUST 2014
www.ti.com.cn
7.5 Electrical Characteristics
Minimum and maximum specifications are at TA = –40°C to 125°C. Typical specifications are at TA = 25°C.
AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and fSAMPLE = 500 kSPS, unless otherwise noted.
TEST(1)
LEVEL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ANALOG INPUTS
Input range = ±2.5 × VREF
Input range = ±1.25 × VREF
Input range = ±0.625 × VREF
Input range = 2.5 × VREF
Input range = 1.25 × VREF
Input range = ±2.5 × VREF
Input range = ±1.25 × VREF
Input range = ±0.625 × VREF
Input range = 2.5 × VREF
Input range = 1.25 × VREF
–2.5 × VREF
2.5 × VREF
1.25 × VREF
0.625 × VREF
2.5 × VREF
V
V
V
V
V
V
V
V
V
V
A
A
A
A
A
A
A
A
A
A
–1.25 × VREF
Full-scale input span(2)
(AIN_nP to AIN_nGND)
–0.625 × VREF
0
0
–2.5 × VREF
–1.25 × VREF
–0.625 × VREF
0
1.25 × VREF
2.5 × VREF
1.25 × VREF
0.625 × VREF
2.5 × VREF
Operating input range,
positive input
AIN_nP
0
1.25 × VREF
Operating input range, negative
input
AIN_nGND
All input ranges
At TA = 25°C
–0.1
0.85
0
0.1
V
B
zi
Input impedance
1
7
1.15
MΩ
B
B
Input impedance drift
25 ppm/°C
VIN – 2.25
————
RIN
With voltage at AIN_nP pin = VIN
input range = ±2.5 × VREF
,
,
,
,
,
µA
A
A
A
A
A
VIN – 2.00
————
RIN
With voltage at AIN_nP pin = VIN
input range = ±1.25 × VREF
µA
µA
µA
µA
VIN – 1.60
————
RIN
With voltage at AIN_nP pin = VIN
input range = ±0.625 × VREF
IIkg(in)
Input leakage current
VIN – 2.50
————
RIN
With voltage at AIN_nP pin = VIN
input range = 2.5 × VREF
VIN – 2.50
————
RIN
With voltage at AIN_nP pin = VIN
input range = 1.25 × VREF
INPUT OVERVOLTAGE PROTECTION
AVDD = 5 V or offers low impedance
< 30 kΩ,
all input ranges
–20
–11
20
11
V
V
B
B
VOVP
Overvoltage protection voltage
AVDD = floating with impedance
> 30 kΩ, all input ranges
(1) Test Levels: (A) Tested at final test. Over temperature limits are set by characterization and simulation. (B) Limits set by characterization
and simulation, across temperature range. (C) Typical value only for information, provided by design simulation.
(2) Ideal input span, does not include gain or offset error.
6
Copyright © 2014, Texas Instruments Incorporated
ADS8684, ADS8688
www.ti.com.cn
ZHCSCR1B –JULY 2014–REVISED AUGUST 2014
Electrical Characteristics (continued)
Minimum and maximum specifications are at TA = –40°C to 125°C. Typical specifications are at TA = 25°C.
AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and fSAMPLE = 500 kSPS, unless otherwise noted.
TEST(1)
LEVEL
PARAMETER
SYSTEM PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX UNIT
Resolution
16
16
Bits
Bits
1.5 LSB(3)
A
A
A
A
NMC
DNL
INL
No missing codes
Differential nonlinearity
Integral nonlinearity(4)
–0.99
–2
±0.5
±0.75
2
LSB
%FSR(
EG
Gain error
At TA = 25°C, all input ranges
±0.02
±0.05
A
5)
Gain error matching
(channel-to-channel)
At TA = 25°C, all input ranges
All input ranges
±0.02
±1
±0.05 %FSR
±4 ppm/°C
A
B
A
Gain error temperature drift
At TA = 25°C,
input range = ±2.5 × VREF
±0.5
±0.75
±1
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
At TA = 25°C,
input range = ±1.25 × VREF
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
A
A
A
A
A
A
A
A
At TA = 25°C,
input range = ±0.625 × VREF
EO
Offset error
±1.5
±2
At TA = 25°C,
input range = 0 to 2.5 × VREF
At TA = 25°C,
input range = 0 to 1.25 × VREF
±2
At TA = 25°C,
input range = ±2.5 × VREF
±0.75
±1
At TA = 25°C,
input range = ±1.25 × VREF
Offset error matching
(channel-to-channel)
At TA = 25°C,
input range = ±0.625 × VREF
±1.5
±2
At TA = 25°C,
input range = 0 to 2.5 × VREF
At TA = 25°C,
input range = 0 to 1.25 × VREF
±0.5
±1
±2
A
B
Offset error temperature drift
All input ranges
±3 ppm/°C
SAMPLING DYNAMICS
tCONV Conversion time
tACQ
850
ns
ns
A
A
Acquisition time
1150
Maximum throughput rate
without latency
fS
500 kSPS
A
(3) LSB = least significant bit.
(4) This parameter is the endpoint INL, not best fit INL.
(5) FSR = full-scale range.
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Electrical Characteristics (continued)
Minimum and maximum specifications are at TA = –40°C to 125°C. Typical specifications are at TA = 25°C.
AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and fSAMPLE = 500 kSPS, unless otherwise noted.
TEST(1)
LEVEL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
Input range = ±2.5 × VREF
Input range = ±1.25 × VREF
Input range = ±0.625 × VREF
Input range = 2.5 × VREF
Input range = 1.25 × VREF
90
89
92
91
dB
dB
dB
dB
dB
A
A
A
A
A
Signal-to-noise ratio
SNR
87.5
88.5
87.5
89
(VIN – 0.5 dBFS at 1 kHz)
90.5
89
Total harmonic distortion(6)
(VIN – 0.5 dBFS at 1 kHz)
THD
All input ranges
–102
dB
B
Input range = ±2.5 × VREF
Input range = ±1.25 × VREF
Input range = ±0.625 × VREF
Input range = 2.5 × VREF
Input range = 1.25 × VREF
89
88.5
87
91.5
91
dB
dB
dB
dB
dB
A
A
A
A
A
Signal-to-noise + distortion
SINAD
89
(VIN – 0.5 dBFS at 1 kHz)
87.5
87
90.5
89
Spurious-free dynamic range
SFDR
All input ranges
103
110
dB
dB
B
B
(VIN – 0.5 dBFS at 1 kHz)
Aggressor channel input is
overdriven to 2 × maximum input
voltage
Crosstalk isolation(7)
Crosstalk memory(8)
Aggressor channel input is
overdriven to 2 × maximum input
voltage
90
dB
B
BW(–3 dB)
–3 dB
At TA = 25°C, all input ranges
At TA = 25°C, all input ranges
15
kHz
kHz
B
B
Small-signal
bandwidth
BW(–0.1 dB)
–0.1 dB
2.5
AUXILIARY CHANNEL
Resolution
16
0
Bits
V
A
A
A
A
C
C
A
A
A
A
A
A
B
A
B
V(AUX_IN)
AUX_IN voltage range
(AUX_IN – AUX_GND)
AUX_IN
VREF
VREF
0
V
Operating input range
AUX_GND
0
75
V
During sampling
During conversion
pF
pF
nA
LSB
LSB
Ci
Input capacitance
5
IIkg(in)
DNL
Input leakage current
Differential nonlinearity
Integral nonlinearity
Gain error
100
±0.6
±1.5
±0.02
–0.99
–4
1.5
4
INL
EG(AUX)
EO(AUX)
SNR
At TA = 25°C
±0.2 % FSR
Offset error
At TA = 25°C
–10
87
10
mV
dB
dB
dB
dB
Signal-to-noise ratio
V(AUX_IN) = –0.5 dBFS at 1 kHz
V(AUX_IN) = –0.5 dBFS at 1 kHz
V(AUX_IN) = –0.5 dBFS at 1 kHz
V(AUX_IN) = –0.5 dBFS at 1 kHz
88
–102
88
THD
Total harmonic distortion(6)
Signal-to-noise + distortion
Spurious-free dynamic range
SINAD
SFDR
86
102
(6) Calculated on the first nine harmonics of the input frequency.
(7) Isolation crosstalk is measured by applying a full-scale sinusoidal signal up to 10 kHz to a channel, not selected in the multiplexing
sequence, and measuring its effect on the output of any selected channel.
(8) Memory crosstalk is measured by applying a full-scale sinusoidal signal up to 10 kHz to a channel, which is selected in the multiplexing
sequence, and measuring its effect on the output of the next selected channel, for all combinations of input channels.
8
Copyright © 2014, Texas Instruments Incorporated
ADS8684, ADS8688
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ZHCSCR1B –JULY 2014–REVISED AUGUST 2014
Electrical Characteristics (continued)
Minimum and maximum specifications are at TA = –40°C to 125°C. Typical specifications are at TA = 25°C.
AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and fSAMPLE = 500 kSPS, unless otherwise noted.
TEST(1)
LEVEL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INTERNAL REFERENCE OUTPUT
Voltage on REFIO pin
(configured as output)
(9)
V(REFIO_INT)
At TA = 25°C
4.095
4.096
4.097
V
A
Internal reference temperature
drift
6
22
10 ppm/°C
µF
B
B
A
C(OUT_REFIO)
V(REFCAP)
Decoupling capacitor on REFIO
10
Reference voltage to ADC
(on REFCAP pin)
At TA = 25°C
4.095
4.096
4.097
V
Reference buffer output
impedance
0.5
1
Ω
B
Reference buffer temperature drift
Decoupling capacitor on REFCAP
0.6
22
1.5 ppm/°C
B
B
C(OUT_REFCAP)
10
μF
C(OUT_REFCAP) = 22 µF
C(OUT_REFIO) = 22 µF
Turn-on time
15
ms
B
EXTERNAL REFERENCE INPUT
External reference voltage on
VREFIO_EXT
4.046
4.096
4.146
V
C
REFIO (configured as input)
POWER-SUPPLY REQUIREMENTS
AVDD
DVDD
Analog power-supply voltage
Analog supply
4.75
1.65
5
5.25
V
V
B
B
Digital supply range
3.3
AVDD
Digital power-supply voltage
Digital supply range for specified
performance
2.7
3.3
13
8.5
10
5.5
3
5.25
16
V
B
A
A
A
A
A
For ADS8688; AVDD = 5 V, fS
maximum and internal reference
=
mA
mA
mA
mA
mA
Dynamic,
AVDD
IAVDD_DYN
For ADS8684; AVDD = 5 V, fS
maximum and internal reference
=
11.5
12
For ADS8688; AVDD = 5 V, device
not converting and internal reference
IAVDD_STC
Analog supply current Static
For ADS8684; AVDD = 5 V, device
not converting and internal reference
8.5
4.5
20
Power-
down
At AVDD = 5 V, device in STDBY
mode and internal reference
ISTDBY
Dynamic,
DVDD
IPWR_DN
At AVDD = 5 V, device in PWR_DN
At DVDD = 3.3 V, output = 0000h
3
μA
B
A
IDVDD_DYN
Digital supply current
0.5
mA
DIGITAL INPUTS (CMOS)
VIH
0.7 × DVDD
–0.3
DVDD + 0.3
0.3 × DVDD
DVDD + 0.3
0.2 × DVDD
V
V
A
A
A
A
A
C
Digital input logic levels
DVDD > 2.1 V
VIL
VIH
VIL
0.8 × DVDD
–0.3
V
Digital input logic levels
DVDD ≤ 2.1 V
V
Input leakage current
Input pin capacitance
100
5
nA
pF
DIGITAL OUTPUTS (CMOS)
VOH
IO = 500-μA source
IO = 500-μA sink
Only for SDO
0.8 × DVDD
0
DVDD
V
V
A
A
A
C
Digital output logic levels
VOL
0.2 × DVDD
Floating state leakage current
Internal pin capacitance
1
5
µA
pF
TEMPERATURE RANGE
TA Operating free-air temperature
–40
125
°C
B
(9) Does not include the variation in voltage resulting from solder shift effects.
Copyright © 2014, Texas Instruments Incorporated
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7.6 Timing Requirements: Serial Interface
Minimum and maximum specifications are at TA = –40°C to 125°C. Typical specifications are at TA = 25°C.
AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), SDO load = 20 pF, and fSAMPLE = 500 kSPS, unless otherwise noted.
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
TIMING SPECIFICATIONS
fS
Sampling frequency
ADC cycle time period
fCLK = max
fCLK = max
fS = max
500 kSPS
µs
tS
2
fSCLK
tSCLK
tCONV
tDV_CSDO
tD_CKCS
tDZ_CSDO
Serial clock frequency
17
MHz
ns
Serial clock time period
fS = max
59
Conversion time
850
10
ns
Delay time: CS falling to data enable
Delay time: last SCLK falling to CS rising
Delay time: CS rising to SDO going to 3-state
ns
10
10
ns
ns
TIMING REQUIREMENTS
tACQ
Acquisition time
1150
0.4
0.4
30
30
10
25
5
ns
tPH_CK
Clock high time
0.6 tSCLK
tPL_CK
Clock low time
0.6 tSCLK
tPH_CS
CS high time
ns
ns
ns
ns
ns
ns
ns
ns
tSU_CSCK
tHT_CKDO
tSU_DOCK
tSU_DICK
tHT_CKDI
tSU_DSYCK
tHT_CKDSY
Setup time: CS falling to SCLK falling
Hold time: SCLK falling to (previous) data valid on SDO
Setup time: SDO data valid to SCLK falling
Setup time: SDI data valid to SCLK falling
Hold time: SCLK falling to (previous) data valid on SDI
Setup time: DAISY data valid to SCLK falling
Hold time: SCLK falling to (previous) data valid on DAISY
5
5
5
Sample
N
Sample
N + 1
tS
tCONV
tACQ
tPH_CS
CS
SCLK
SDO
tSCLK
30
tD_CKCS
31
tDZ_CSDO
tSU_CSCK
2
tDV_CSDO
tPH_CK
18
tPL_CK
23
24
26
1
14
15
16
17
25
27
28
29
7
8
9
32
tHT_CKDO
tSU_DOCK
D14
#2
D6
#2
D5
#2
D4
#2
D3
#2
D2
#2
D1
#2
D0
#2
D15
#2
D9
#2
D8
#2
D7
#2
Data from sample N
tSU_DICK
B2
tHT_CKDI
B14
B10 B9
B8
B7
X
X
X
X
X
B15
B1
B0
X
X
B3
SDI
X
X
X
X
X
tSU_DSYCK
tHT_CKDSY
D14
#1
D6
#1
D5
#1
D4
#1
D3
#1
D2
#1
D1
#1
D0
#1
D15
#1
D9
#1
D8
#1
D7
#1
DAISY
Figure 1. Serial Interface Timing Diagram
10
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ZHCSCR1B –JULY 2014–REVISED AUGUST 2014
7.7 Typical Characteristics
At TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 4.096 V, and fSAMPLE = 500 kSPS, unless otherwise noted.
15
9
15
9
----- 25 C
----- -40 C
------ 125 C
3
3
±3
±9
±15
±3
±9
±15
----- ± 2.5*VREF
----- ± 1.25*VREF
----- ± 0.625*VREF
------ +2.5*VREF
------+1.25*VREF
2
6
10
±10
±6
±2
2
6
10
±10
±6
±2
Input Voltage (V)
C001
C002
Input Voltage (V)
Input range = ±2.5 × VREF
Figure 3. Input Current vs Temperature
Figure 2. Input I-V Characteristic
10
800
640
480
320
160
0
6
2
±2
±6
----- ± 2.5*VREF
----- ± 1.25*VREF
----- ± 0.625*VREF
------ +2.5*VREF
------+1.25*VREF
±10
26
59
92
125
±40
±7
0.85 0.88 0.91 0.94 0.97
1
1.03 1.06 1.09 1.12 1.15
Free- Air Temperature (oC)
C005
Input Impedance (Mohm)
C006
Number of samples = 1160
Figure 4. Input Impedance Variation vs Temperature
Figure 5. Typical Distribution of Input Impedance
20000
20000
16000
12000
8000
4000
0
16000
12000
8000
4000
0
32765 32766 32767 32768 32769 32770 32771
Output Codes
32765 32766 32767 32768 32769 32770 32771
Output Codes
C007
C008
Mean = 32767.8, Sigma = 0.58, Input = 0 V,
Range = ±2.5 × VREF
Mean = 32768.1, Sigma = 0.63, Input = 0 V,
Range = ±1.25 × VREF
Figure 6. DC Histogram for Mid-Scale Inputs (±2.5 × VREF
)
Figure 7. DC Histogram for Mid-Scale Inputs (±1.25 × VREF)
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 4.096 V, and fSAMPLE = 500 kSPS, unless otherwise noted.
20000
16000
12000
8000
4000
0
20000
16000
12000
8000
4000
0
32764
32766
32768
32770
32772
32764
32766
32768
32770
32772
Output Codes
Output Codes
C009
C010
Mean = 32767.932767.9(TBD), Sigma = 0.76, Input = 0 V,
Range = ±0.625 × VREF
Mean = 32767.75, Sigma = 0.65, Input = 1.25 × VREF
,
Range = 2.5 × VREF
Figure 8. DC Histogram for Mid-Scale Inputs (±0.625 × VREF
)
Figure 9. DC Histogram for Mid-Scale Inputs (2.5 × VREF
)
20000
1.4
1
0.6
0.2
-0.2
-0.6
-1
16000
12000
8000
4000
0
32764
32766
32768
32770
32772
0
16384
32768
49152
65536
Output Codes
Codes (LSB)
C012
C011
Mean = 32768.90, Sigma = 0.75, Input = 0.625 × VREF
,
All input ranges
Range = 1.25 × VREF
Figure 10. DC Histogram for Mid-Scale Inputs (1.25 × VREF
)
Figure 11. Typical DNL for All Codes
1.4
2
1.5
1
1
Maximum
0.6
0.5
0
0.2
-0.5
-1
-0.2
Minimum
-0.6
-1
-1.5
-2
26
59
92
125
0
16384
32768
49152
65536
±40
±7
Free-Air Temperature (oC)
Codes (LSB)
C014
C013
All input ranges
Range = ±2.5 × VREF
Figure 12. DNL vs Temperature
Figure 13. Typical INL for All Codes
12
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ZHCSCR1B –JULY 2014–REVISED AUGUST 2014
Typical Characteristics (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 4.096 V, and fSAMPLE = 500 kSPS, unless otherwise noted.
2
1.5
1
2
1.5
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-2
-1.5
-2
0
16384
32768
49152
65536
0
16384
32768
49152
65536
C015
Codes (LSB)
Codes (LSB)
C016
Range = ±1.25 × VREF
Range = ±0.625 × VREF
Figure 14. Typical INL for All Codes
Figure 15. Typical INL for All Codes
2
1.5
1
2
1.5
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-2
-1.5
-2
0
16384
32768
49152
65536
0
16384
32768
49152
65536
Codes (LSB)
Codes (LSB)
C018
C017
Range = 2.5 × VREF
Range = 1.25 × VREF
Figure 16. Typical INL for All Codes
Figure 17. Typical INL for All Codes
2
1
2
1.5
1
Maximum
Minimum
Maximum
Minimum
0.5
0
0
-0.5
-1
-1
-2
-1.5
-2
26
59
92
125
26
59
92
125
±40
±7
±40
±7
Free-Air Temperature (oC)
Free-Air Temperature (oC)
C061
C019
Range = ±2.5 × VREF
Range = ±1.25 × VREF
Figure 19. INL vs Temperature (±1.25 × VREF)
Figure 18. INL vs Temperature (±2.5 × VREF
)
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 4.096 V, and fSAMPLE = 500 kSPS, unless otherwise noted.
2
2
1
1
Maximum
Maximum
0
0
Minimum
Minimum
-1
-1
-2
-2
26
59
92
125
±40
±7
26
59
92
125
±40
±7
Free-Air Temperature (oC)
Free-Air Temperature (oC)
C021
C020
Range = 2.5 × VREF
Range = ±0.625 × VREF
Figure 21. INL vs Temperature (2.5 × VREF
)
Figure 20. INL vs Temperature (±0.625 × VREF
)
2
1
1
0.75
0.5
----- ± 2.5*VREF
----- ± 1.25*VREF
----- ± 0.625*VREF
------ +2.5*VREF
------+1.25*VREF
Maximum
Minimum
0.25
0
0
-0.25
-0.5
-0.75
-1
-1
-2
26
59
92
125
26
59
92
125
±40
±7
±40
±7
Free-Air Temperature (oC)
Free-Air Temperature (oC)
C022
C023
Range = 1.25 × VREF
Figure 22. INL vs Temperature (1.25 × VREF
)
Figure 23. Offset Error vs Temperature Across Input Ranges
80
60
40
20
0
1
------ CH0, ----- CH1, ----- CH2
0.75
0.5
----- CH3, --- CH4, ------ CH5
------ CH6,
----- CH7
0.25
0
-0.25
-0.5
-0.75
-1
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2 2.4 2.6 2.8
3
26
59
92
125
±40
±7
Offset Drift (ppm/ºC)
Free-Air Temperature (oC)
C025
C024
Range = ±2.5 × VREF
Figure 24. Typical Histogram for Offset Drift
Range = ±2.5 × VREF
Figure 25. Offset Error vs Temperature Across Channels
14
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ZHCSCR1B –JULY 2014–REVISED AUGUST 2014
Typical Characteristics (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 4.096 V, and fSAMPLE = 500 kSPS, unless otherwise noted.
0.05
100
80
60
40
20
0
----- ± 2.5*VREF
----- ± 1.25*VREF
----- ± 0.625*VREF
------ +2.5*VREF
------+1.25*VREF
0.03
0.01
-0.01
-0.03
-0.05
26
59
92
125
0
0.5
1
1.5
2
2.5
3
3.5
4
±40
±7
Free-Air Temperature (oC)
Gain Drift (ppm/ºC)
C027
C026
Range = ±2.5 × VREF
Figure 26. Gain Error vs Temperature Across Input Ranges
Figure 27. Typical Histogram for Gain Error Drift
0.05
2
1.5
1
0.03
0.01
-0.01
0.5
0
----- ± 2.5*VREF
----- ± 1.25*VREF
----- ± 0.625*VREF
------ +2.5*VREF
------+1.25*VREF
-0.03
------ CH0, ----- CH1, ----- CH2
----- CH3, --- CH4, ------ CH5
------ CH6,
----- CH7
-0.5
-0.05
0
4
8
12
16
20
26
59
92
125
±40
±7
Free-Air Temperature (oC)
Source Resistance (k Ohm)
C028
C029
Range = ±2.5 × VREF
Figure 28. Gain Error vs Temperature Across Channels
Figure 29. Gain Error vs External Resistance (REXT
)
0
0
±40
±80
±40
±80
±120
±160
±200
±120
±160
±200
0
50000
100000
150000
200000
250000
0
50000
100000
150000
200000
250000
Input Frequency (Hz)
Input Frequency (Hz)
C031
C030
Number of points = 64k, fIN = 1 kHz, SNR = 92.3 dB,
SINAD = 91.9 dB, THD = 101 dB, SFDR = 104 dB
Number of points = 64k, fIN = 1 kHz, SNR = 91.4 dB,
SINAD = 91.2 dB, THD = 105 dB, SFDR = 107 dB
Figure 30. Typical FFT Plot (±2.5 × VREF
)
Figure 31. Typical FFT Plot (±1.25 × VREF)
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 4.096 V, and fSAMPLE = 500 kSPS, unless otherwise noted.
0
0
±40
±40
±80
±80
±120
±160
±200
±120
±160
±200
0
50000
100000
150000
200000
250000
0
50000
100000
150000
200000
250000
C032
Input Frequency (Hz)
Input Frequency (Hz)
C033
Number of points = 64k, fIN = 1 kHz, SNR = 89.6 dB,
SINAD = 89.5 dB, THD = 106 dB, SFDR = 107 dB
Number of points = 64k, fIN = 1 kHz, SNR = 90.93 dB,
SINAD = 90.48 dB, THD = 100 dB, SFDR = 102 dB
Figure 32. Typical FFT Plot (±0.625 × VREF
)
Figure 33. Typical FFT Plot (2.5 × VREF)
0
±40
92.5
92
91.5
91
±80
90.5
90
±120
±160
±200
89.5
89
----- ± 2.5*VREF
----- ± 1.25*VREF
----- ± 0.625*VREF
------ +2.5*VREF
------+1.25*VREF
88.5
88
87.5
0
50000
100000
150000
200000
250000
100
1000
10000
Input Frequency (Hz)
Input Frequency (Hz)
C034
C035
Number of points = 64k, fIN = 1 kHz, SNR = 89.55 dB,
SINAD = 89.4 dB, THD = 104 dB, SFDR = 107 dB
Figure 34. Typical FFT Plot (1.25 × VREF
)
Figure 35. SNR vs Input Frequency
94
93
92
91
90
89
88
94
93
92
91
90
89
88
----- ± 2.5*VREF
----- ± 1.25*VREF
----- ± 0.625*VREF
------ +2.5*VREF
------+1.25*VREF
----- ± 2.5*VREF
----- ± 1.25*VREF
----- ± 0.625*VREF
------ +2.5*VREF
------+1.25*VREF
26
59
92
125
100
1000
10000
±40
±7
Free-Air Temperature (oC)
Input Frequency (Hz)
C036
C037
fIN = 1 kHz
Figure 36. SNR vs Temperature
Figure 37. SINAD vs Input Frequency
16
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 4.096 V, and fSAMPLE = 500 kSPS, unless otherwise noted.
94
93
92
91
90
89
88
±80
----- ± 2.5*VREF
----- ± 1.25*VREF
----- ± 0.625*VREF
------ +2.5*VREF
------+1.25*VREF
±90
±100
±110
±120
----- ± 2.5*VREF
----- ± 1.25*VREF
----- ± 0.625*VREF
------ +2.5*VREF
------+1.25*VREF
26
59
92
125
10
50
50
2010
4010
6010
8010
±40
±40
50
±7
Free-AirTemperature (oC)
Input Frequency (Hz)
C038
C039
fIN = 1 kHz
Figure 38. SINAD vs Temperature
Figure 39. THD vs Input Frequency
±80
±90
±80
±95
----- ± 2.5*VREF
----- ± 1.25*VREF
----- ± 0.625*VREF
------ +2.5*VREF
------+1.25*VREF
±100
±110
±120
±110
±125
±140
----- ± 2.5*VREF
----- ± 1.25*VREF
----- ± 0.625*VREF
------ +2.5*VREF
------+1.25*VREF
26
59
92
125
500
5000
50000
500000 5000000
±7
Free-Air Temperature (oC)
C040
Input Frequency (Hz)
C041
fIN = 1 kHz
Figure 40. THD vs Temperature
Figure 41. Memory Crosstalk vs Frequency
±80
±95
±80
±95
----- ± 2.5*VREF
----- ± 1.25*VREF
----- ± 0.625*VREF
------ +2.5*VREF
------+1.25*VREF
±110
±125
±140
±110
±125
±140
----- ± 2.5*VREF
----- ± 1.25*VREF
----- ± 0.625*VREF
------ +2.5*VREF
------+1.25*VREF
500
5000
50000
500000 5000000
500
5000
50000
500000 5000000
Input Frequency (Hz)
Input Frequency (Hz)
C042
C043
Input = 2 × maximum input voltage
Figure 42. Isolation Crosstalk vs Frequency
Figure 43. Memory Crosstalk vs Frequency for
Overrange Inputs
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 4.096 V, and fSAMPLE = 500 kSPS, unless otherwise noted.
±80
12
11.5
11
----- ± 2.5*VREF
----- ± 1.25*VREF
----- ± 0.625*VREF
------ +2.5*VREF
------+1.25*VREF
±95
±110
±125
±140
10.5
10
50
500
5000
50000
500000 5000000
26
59
92
125
±40
±7
Input Frequency (Hz)
Free-Air Temperature (oC)
C044
C057
Input = 2 × maximum input voltage
Figure 44. Isolation Crosstalk vs Frequency for
Overrange Inputs
Figure 45. AVDD Current vs Temperature for ADS8688
(fS = 500 kSPS)
9
8.75
8.5
9
8.75
8.5
8.25
8
8.25
8
7.75
7.5
7.75
7.5
26
59
92
125
±40
±7
26
59
92
125
±40
±7
Free-Air Temperature (oC)
Free-Air Temperature (oC)
C062
C058
Figure 47. AVDD Current vs Temperature for ADS8684
(fS = 500 kSPS)
Figure 46. AVDD Current vs Temperature for ADS8688
(During Sampling)
6
5.75
5.5
2.3
2.2
2.1
2
5.25
5
4.75
4.5
26
59
92
125
26
59
92
125
±40
±7
±40
±7
Free-Air Temperature (oC)
Free-Air Temperature (oC)
C063
C05
Figure 48. AVDD Current vs Temperature for ADS8684
(During Sampling)
Figure 49. AVDD Current vs Temperature
(STANDBY)
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Typical Characteristics (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 4.096 V, and fSAMPLE = 500 kSPS, unless otherwise noted.
6
5
4
3
2
1
26
59
92
125
±40
±7
Free-Air Temperature (oC)
C060
Figure 50. AVDD Current vs Temperature
(Power Down)
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8 Detailed Description
8.1 Overview
The ADS8684 and ADS8688 are 16-bit data acquisition systems with 4- and 8-channel analog inputs,
respectively. Each analog input channel consists of an overvoltage protection clamp circuit, a programmable gain
amplifier (PGA), and a second-order, antialiasing filter that conditions the input signal before being fed into a 4-
or 8-channel analog multiplexer (MUX). The output of the MUX is digitized using a 16-bit analog-to-digital
converter (ADC), based on the successive approximation register (SAR) architecture. This overall system can
achieve a maximum throughput of 500 kSPS, combined across all channels. The devices feature a 4.096-V
internal reference with a fast-settling buffer and a simple SPI-compatible serial interface with a daisy-chain
(DAISY) feature.
The devices operate from a single 5-V analog supply and can accommodate true bipolar input signals up to
±2.5 × VREF. The devices offer a constant 1-MΩ resistive input impedance irrespective of the sampling frequency
or the selected input range. The integration of multichannel precision analog front-end circuits with high input
impedance and a precision ADC operating from a single 5-V supply offers a simplified end solution without
requiring external high-voltage bipolar supplies and complicated driver circuits.
8.2 Functional Block Diagram
DVDD
AVDD
1 M:
ADS8688
ADS8684
OVP
OVP
AIN_0P
AIN_0GND
2nd-Order
LPF
ADC
Driver
PGA
1 M:
1 M:
VB0
OVP
OVP
AIN_1P
AIN_1GND
2nd-Order
LPF
ADC
Driver
PGA
PGA
PGA
PGA
PGA
PGA
PGA
1 M:
1 M:
VB1
OVP
OVP
AIN_2P
AIN_2GND
Digital
Logic
&
2nd-Order
LPF
ADC
Driver
1 M:
1 M:
CS
VB2
Interface
SCLK
SDI
OVP
OVP
AIN_3P
AIN_3GND
2nd-Order
LPF
ADC
Driver
1 M:
1 M:
VB3
SDO
OVP
OVP
AIN_4P
AIN_4GND
16-bit
SAR ADC
2nd-Order
LPF
ADC
Driver
DAISY
REFSEL
RST / PD
1 M:
1 M:
VB4
OVP
OVP
AIN_5P
AIN_5GND
2nd-Order
LPF
ADC
Driver
Oscillator
1 M:
1 M:
VB5
OVP
OVP
AIN_6P
AIN_6GND
2nd-Order
LPF
ADC
Driver
REFCAP
REFIO
1 M:
1 M:
VB6
OVP
OVP
AIN_7P
AIN_7GND
2nd-Order
LPF
ADC
Driver
4.096V
Reference
1 M:
VB7
AUX_IN
AUX_GND
AGND
DGND
REFGND
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8.3 Feature Description
8.3.1 Analog Inputs
The ADS8684 and ADS8688 have either four or eight analog input channels, respectively, such that the positive
inputs AIN_nP (n = 0 to 3 or 7) are the single-ended analog inputs and the negative inputs AIN_nGND are tied to
GND. Figure 51 shows the simplified circuit schematic for each analog input channel, including the input
overvoltage protection circuit, PGA, low-pass filter (LPF), high-speed ADC driver, and analog multiplexer.
1 M:
CS
SCLK
SDI
SDO
DAISY
OVP
OVP
AIN_nP
2nd-Order
LPF
ADC
Driver
MUX
PGA
ADC
AIN_nGND
1 M:
VB
NOTE: ADS8684: n = 0 to 3. ADS8688: n = 0 to 7.
Figure 51. Front-End Circuit Schematic for Each Analog Input Channel
The devices can support multiple unipolar or bipolar, single-ended input voltage ranges based on the
configuration of the program registers. As explained in the Range Select Registers section, the input voltage
range for each analog channel can be configured to bipolar ±2.5 × VREF, ±1.25 × VREF, and ±0.625 × VREF or
unipolar 0 to 2.5 × VREF and 0 to 1.25 × VREF. With the internal or external reference voltage set to 4.096 V, the
input ranges of the device can be configured to bipolar ranges of ±10.24 V, ±5.12 V, and ±2.56 V or unipolar
ranges of 0 V to 10.24 V and 0 V to 5.12 V. Any of these input ranges can be assigned to any analog input
channel of the device. For instance, the ±2.5 × VREF range can be assigned to AIN_1P, the ±1.25 × VREF range
can be assigned to AIN_2P, the 0 V to 2.5 × VREF range can be assigned to AIN_3P, and so forth.
The devices sample the voltage difference (AIN_nP – AIN_nGND) between the selected analog input channel
and the AIN_nGND pin. The devices allow a ±0.1-V range on the AIN_nGND pin for all analog input channels.
This feature is useful in modular systems where the sensor or signal conditioning block is further away from the
ADC on the board and when a difference in the ground potential of the sensor or signal conditioner from the ADC
ground is possible. In such cases, TI recommends running separate wires from the AIN_nGND pin of the device
to the sensor or signal conditioning ground.
8.3.2 Analog Input Impedance
Each analog input channel in the device presents a constant resistive impedance of 1 MΩ. The input impedance
is independent of either the ADC sampling frequency, the input signal frequency, or range. The primary
advantage of such high-impedance inputs is the ease of driving the ADC inputs without requiring driving
amplifiers with low output impedance. Bipolar, high-voltage power supplies are not required in the system
because this ADC does not require any high-voltage front-end drivers. In most applications, the signal sources or
sensor outputs can be directly connected to the ADC input, which significantly simplifies the design of the signal
chain.
In order to maintain the dc accuracy of the system, matching the external source impedance on the AIN_nP input
pin with an equivalent resistance on the AIN_nGND pin is recommended. This matching helps to cancel any
additional offset error contributed by the external resistance.
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Feature Description (continued)
8.3.3 Input Overvoltage Protection Circuit
The ADS8684 and ADS8688 feature an internal overvoltage protection circuit on each of the four or eight analog
input channels, respectively. Use these protection circuits as a secondary protection scheme to protect the
device. TI highly recommends using external protection devices against surges, electrostatic discharge (ESD),
and electrical fast transient (EFT) conditions. The conceptual block diagram of the internal overvoltage protection
(OVP) circuit is shown in Figure 52.
AVDD
VP+
RFB
0V
ESD
AVDD
VP-
10ꢀ
10ꢀ
RS
RS
D1p
D2p
AIN_nP
V±
V+
AVDD
VOUT
D1n
AIN_nGND
+
D2n
RDC
VB
ESD
GND
Figure 52. Input Overvoltage Protection Circuit Schematic
As shown in Figure 52, the combination of the 1-MΩ input resistors along with the PGA gain-setting resistors
(RFB and RDC) limit the current flowing into the input pins. A combination of antiparallel diodes (D1 and D2) are
added on each input pin to protect the internal circuitry and set the overvoltage protection limits.
Table 1 explains the various operating conditions for the device when the device is powered on. Table 1
indicates that when the AVDD pin of the device is connected to the proper supply voltage (AVDD = 5 V) or offers
a low impedance of < 30 kΩ, the internal overvoltage protection circuit can withstand up to ±20 V on the analog
input pins.
Table 1. Input Overvoltage Protection Limits When AVDD = 5 V or Offers a Low Impedance of < 30 kΩ(1)
TEST
ADC
INPUT CONDITION (VOVP = ±20 V)
COMMENTS
CONDITION OUTPUT
All input
Valid
|VIN| < |VRANGE
|VRANGE| < |VIN| < |VOVP
|VIN| > |VOVP
|
Within operating range
Device functions as per data sheet specifications
ranges
Beyond operating range but
within overvoltage range
All input
Saturated
ranges
ADC output is saturated, but device is internally
protected (not recommended for extended time)
|
All input
Saturated
ranges
This usage condition may cause irreversible damage
to the device
|
Beyond overvoltage range
(1) GND = 0, AIN_nGND = 0 V, |VRANGE| is the maximum input voltage for any selected input range, and |VOVP| is the break-down voltage
for the internal OVP circuit. Assume RS is approximately 0.
The results indicated in Table 1 are based on an assumption that the analog input pins are driven by very low
impedance sources (RS is approximately 0). However, if the sources driving the inputs have higher impedance,
the current flowing through the protection diodes reduces further, thereby increasing the OVP voltage range.
Note that higher source impedance results in gain errors and contributes to overall system noise performance.
22
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Figure 53 shows the voltage versus current response of the internal overvoltage protection circuit when the
device is powered on. According to this current-to-voltage (I-V) response, the current flowing into the device input
pins is limited by the 1-MΩ input impedance. However, for voltages beyond ±20 V, the internal node voltages
surpass the break-down voltage for internal transistors, thus setting the limit for overvoltage protection on the
input pins.
The same overvoltage protection circuit also provides protection to the device when the device is not powered on
and AVDD is floating with an impedance > 30 kΩ. This condition can arise when the input signals are applied
before the ADC is fully powered on. The overvoltage protection limits for this condition are shown in Table 2.
Table 2. Input Overvoltage Protection Limits When AVDD = Floating with Impedance > 30 kΩ(1)
TEST
CONDITION
INPUT CONDITION (VOVP = ±11 V)
ADC OUTPUT
Invalid
COMMENTS
Device is not functional but is protected internally by
the OVP circuit.
|VIN| < |VOVP
|
|
Within overvoltage range
Beyond overvoltage range
All input ranges
This usage condition may cause irreversible damage
to the device.
|VIN| > |VOVP
All input ranges
Invalid
(1) AVDD = floating, GND = 0, AIN_nGND = 0 V, |VRANGE| is the maximum input voltage for any selected input range, and |VOVP| is the
break-down voltage for the internal OVP circuit. Assume RS is approximately 0.
Figure 54 shows the voltage versus current response of the internal overvoltage protection circuit when the
device is not powered on. According to this I-V response, the current flowing into the device input pins is limited
by the 1-MΩ input impedance. However, for voltages beyond ±11 V, the internal node voltages surpass the
break-down voltage for internal transistors, thus setting the limit for overvoltage protection on the input pins.
30
20
20
12
----- ± 2.5*VREF
----- ± 1.25*VREF
----- ± 0.625*VREF
------ +2.5*VREF
------+1.25*VREF
10
4
0
±4
±10
±20
±30
±12
±20
4
12
20
±20
±12
±4
0
10
20
30
±30
±20
±10
Input Voltage (V)
Input Voltage (V)
C003
C004
Figure 53. I-V Curve for an Input OVP Circuit (AVDD = 5 V)
Figure 54. I-V Curve for an Input OVP Circuit
(AVDD = Floating)
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8.3.4 Programmable Gain Amplifier (PGA)
The devices offer a programmable gain amplifier (PGA) at each individual analog input channel, which converts
the original single-ended input signal into a fully-differential signal to drive the internal 16-bit ADC. The PGA also
adjusts the common-mode level of the input signal before being fed into the ADC to ensure maximum usage of
the ADC input dynamic range. Depending on the range of the input signal, the PGA gain can be accordingly
adjusted by setting the Range_CHn[2:0] (n = 0 to 3 or 7) bits in the program register. The default or power-on
state for the Range_CHn[2:0] bits is 000, which corresponds to an input signal range of ±2.5 × VREF. Table 3 lists
the various configurations of the Range_CHn[2:0] bits for the different analog input voltage ranges.
The PGA uses a very highly-matched network of resistors for multiple gain configurations. Matching between
these resistors and the amplifiers across all channels is accurately trimmed to keep the overall gain error low
across all channels and input ranges.
Table 3. Input Range Selection Bits Configuration
Range_CHn[2:0]
ANALOG INPUT RANGE
BIT 2
BIT 1
BIT 0
±2.5 × VREF
±1.25 × VREF
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
±0.625 × VREF
0 to 2.5 × VREF
0 to 1.25 × VREF
8.3.5 Second-Order, Low-Pass Filter (LPF)
In order to mitigate the noise of the front-end amplifiers and gain resistors of the PGA, each analog input channel
of the ADS8684 and ADS8688 features a second-order, antialiasing LPF at the output of the PGA. The
magnitude and phase response of the analog antialiasing filter are shown in Figure 55 and Figure 56,
respectively. For maximum performance, the –3-dB cutoff frequency for the antialiasing filter is typically set to
15 kHz. The performance of the filter is consistent across all input ranges supported by the ADC.
0
±1
±2
±3
±4
±5
±6
0
±15
±30
±45
±60
±75
±90
----- ± 2.5 VREF
----- ± 1.25 VREF
----- ± 0.625 VREF
------ +2.5 VREF
------+1.25VREF
----- ± 2.5*VREF
----- ± 1.25*VREF
----- ± 0.625*VREF
------ +2.5*VREF
------+1.25*VREF
100
1000
10000
100
1000
Input Frequency (Hz)
10000
Input Frequency (Hz)
C047
C048
Figure 55. Second-Order LPF Magnitude Response
Figure 56. Second-Order LPF Phase Response
8.3.6 ADC Driver
In order to meet the performance of a 16-bit, SAR ADC at the maximum sampling rate (500 kSPS), the sample-
and-hold capacitors at the input of the ADC must be successfully charged and discharged during the acquisition
time window. This drive requirement at the inputs of the ADC necessitates the use of a high-bandwidth, low-
noise, and stable amplifier buffer. Such an input driver is integrated in the front-end signal path of each analog
input channel of the device. During transition from one channel of the multiplexer to another channel, the fast
integrated driver ensures that the multiplexer output settles to 16-bit accuracy within the acquisition time of the
ADC, irrespective of the input levels on the respective channels.
24
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8.3.7 Multiplexer (MUX)
The ADS8684 and ADS8688 feature an integrated 4- and 8-channel analog multiplexer, respectively. For each
analog input channel, the voltage difference between the positive analog input AIN_nP and the negative ground
input AIN_nGND is conditioned by the analog front-end circuitry before being fed into the multiplexer. The output
of the multiplexer is directly sampled by the ADC. The multiplexer in the device can scan these analog inputs in
either manual or auto-scan mode, as explained in Channel Sequencing Modes section. In manual mode
(MAN_Ch_n), the channel is selected for every sample via a register write; in auto-scan mode (AUTO_RST), the
channel number is incremented automatically on every CS falling edge after the present channel is sampled. The
analog inputs can be selected for an auto scan with register settings (refer to Auto-Scan Sequencing Control
Registers section). The devices automatically scan only the selected analog inputs in ascending order.
The maximum overall throughput for the ADS8684 and ADS8688 is specified at 500 kSPS across all channels.
The per channel throughput is dependent on the number of channels selected in the multiplexer scanning
sequence. For example, the throughput per channel is equal to 250 kSPS if only two channels are selected, but
is equal to 125 kSPS per channel if four channels are selected (as in the ADS8684), and so forth.
Refer to Table 6 for command register settings to switch between the auto-scan mode and manual mode for
individual analog channels.
8.3.8 Reference
The ADS8684 and ADS8688 can operate with either an internal voltage reference or an external voltage
reference using the internal buffer. The internal or external reference selection is determined by an external
REFSEL pin. The devices have a built-in buffer amplifier to drive the actual reference input of the internal ADC
core for maximizing performance.
8.3.8.1 Internal Reference
The devices have an internal 4.096-V (nominal value) reference. In order to select the internal reference, the
REFSEL pin must be tied low or connected to AGND. When the internal reference is used, REFIO (pin 5)
becomes an output pin with the internal reference value. TI recommends placing a 10-µF (minimum) decoupling
capacitor between the REFIO pin and REFGND (pin 6), as shown in Figure 57. The capacitor must be placed as
close to the REFIO pin as possible. The output impedance of the internal band-gap circuit creates a low-pass
filter with this capacitor to band-limit the noise of the reference. The use of a smaller capacitor value allows
higher reference noise in the system, thus degrading SNR and SINAD performance. Do not use the REFIO pin to
drive external ac or dc loads because REFIO has limited current output capability. The REFIO pin can be used
as a source if followed by a suitable op amp buffer (such as the OPA320).
AVDD
4.096
VREF
REFSEL
REFIO
10PF
REFCAP
22PF
1PF
REFGND
ADC
AGND
Figure 57. Device Connections for Using an Internal 4.096-V Reference
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The device internal reference is factory trimmed to a maximum initial accuracy of ±1 mV. The histogram in
Figure 58 shows the distribution of the internal voltage reference output taken from more than 3300 production
devices.
600
500
400
300
200
100
0
-1
-0.6
-0.2
0.2
0.6
1
C064
Error in REFIO Voltage (mV)
Figure 58. Internal Reference Accuracy at Room Temperature Histogram
The initial accuracy specification for the internal reference can be degraded if the die is exposed to any
mechanical or thermal stress. Heating the device while being soldered to a PCB and any subsequent solder
reflow is a primary cause for shifts in the VREF value. The main cause of thermal hysteresis is a change in die
stress and therefore is a function of the package, die-attach material, and molding compound, as well as the
layout of the device itself.
In order to illustrate this effect, 80 devices were soldered using lead-free solder paste with the manufacturer's
suggested reflow profile, as explained in the Application Report AN-2029 Handling & Process Recommendations
(SNOA550). The internal voltage reference output is measured before and after the reflow process and the
typical shift in value is displayed in Figure 59. Although all tested units exhibit a positive shift in their output
voltages, negative shifts are also possible. Note that the histogram in Figure 59 displays the typical shift for
exposure to a single reflow profile. Exposure to multiple reflows, which is common on PCBs with surface-mount
components on both sides, causes additional shifts in the output voltage. If the PCB is to be exposed to multiple
reflows, solder the ADS8684 and ADS8688 in the second pass to minimize device exposure to thermal stress.
30
25
20
15
10
5
0
-4
-3
-2
-1
0
1
Error in REFIO Voltage (mV)
C065
Figure 59. Solder Heat Shift Distribution Histogram
26
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The internal reference is also temperature compensated to provide excellent temperature drift over an extended
industrial temperature range of –40°C to 125°C. Figure 60 shows the variation of the internal reference voltage
across temperature for different values of the AVDD supply voltage. The typical specified value of the reference
voltage drift over temperature is 6 ppm/°C (Figure 61) and the maximum specified temperature drift is equal to
10 ppm/°C.
4.1
4.099
4.098
4.097
4.096
4.095
4.094
4.093
4.092
4.091
4.09
20
16
12
8
----- AVDD = 5.25 V
------ AVDD = 5 V
------ AVDD = 4.75 V
4
0
26
59
92
125
1
2
3
4
5
6
7
8
9
10
±40
±7
Free-Air Temperature (oC)
REFIO Drift (ppm/ºC)
C054
C053
AVDD = 5 V, Number of Devices = 30, ΔT = –40°C to 125°C
Figure 60. Variation of the Internal Reference Output
(REFIO) Across Supply and Temperature
Figure 61. Internal Reference Temperature Drift Histogram
8.3.8.2 External Reference
For applications that require a better reference voltage or a common reference voltage for multiple devices, the
ADS8684 and ADS8688 offer a provision to use an external reference along with an internal buffer to drive the
ADC reference pin. In order to select the external reference mode, either tie the REFSEL pin high or connect this
pin to the DVDD supply. In this mode, an external 4.096-V reference must be applied at REFIO (pin 5), which
becomes an input pin. Any low-power, low-drift, or small-size external reference can be used in this mode
because the internal buffer is optimally designed to handle the dynamic loading on the REFCAP pin, which is
internally connected to the ADC reference input. The output of the external reference must be appropriately
filtered to minimize the resulting effect of the reference noise on system performance. A typical connection
diagram for this mode is shown in Figure 62.
AVDD
DVDD
4.096
VREF
REFSEL
AVDD
REF5040
OUT
(Refer to Device Datasheet for
REFIO
Detailed Pin Configuration)
CREF
REFCAP
1PF
22 PF
REFGND
AGND
ADC
Figure 62. Device Connections for Using an External 4.096-V Reference
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The output of the internal reference buffer appears at the REFCAP pin. A minimum capacitance of 10 µF must
be placed between REFCAP (pin 7) and REFGND (pin 6). Place another capacitor of 1 µF as close to the
REFCAP pin as possible for decoupling high-frequency signals. Do not use the internal buffer to drive external ac
or dc loads because of the limited current output capability of this buffer.
The performance of the internal buffer output is very stable across the entire operating temperature range of
–40°C to 125°C. Figure 63 shows the variation in the REFCAP output across temperature for different values of
the AVDD supply voltage. The typical specified value of the reference buffer drift over temperature is 1 ppm/°C
(Figure 64) and the maximum specified temperature drift is equal to 1.5 ppm/°C.
4.097
4.0968
4.0966
4.0964
4.0962
4.096
15
12
9
----- AVDD = 5.25 V
------ AVDD = 5 V
------ AVDD = 4.75 V
6
4.0958
4.0956
4.0954
4.0952
4.095
3
0
0
0.2
0.4
0.6
0.8
1
1.2
26
59
92
125
±40
±7
Free-Air Temperature (oC)
C055
REFCAP Drift (ppm/ºC)
C056
AVDD = 5 V, Number of Devices = 30, ΔT = –40°C to 125°C
Figure 63. Variation of the Reference Buffer Output
(REFCAP) Across Supply and Temperature
Figure 64. Reference Buffer Temperature Drift Histogram
8.3.9 Auxiliary Channel
The devices include a single-ended auxiliary input channel (AUX_IN and AUX_GND). The AUX channel provides
direct interface to an internal, high-precision, 16-bit ADC through the multiplexer because this channel does not
include the front-end analog signal conditioning that the other analog input channels have. The AUX channel
supports a single unipolar input range of 0 V to VREF because there is no front-end PGA. The input signal on the
AUX_IN pin can vary from 0 V to VREF, whereas the AUX_GND pin must be tied to GND.
When a conversion is initiated, the voltage between these pins is sampled directly on an internal sampling
capacitor (75 pF, typical). The input current required to charge the sampling capacitor is determined by several
factors, including the sampling rate, input frequency, and source impedance. For slow applications that use a
low-impedance source, the inputs of the AUX channel can be directly driven. When the throughput, input
frequency, or the source impedance increases, a driving amplifier must be used at the input to achieve good ac
performance from the AUX channel. Some key requirements of the driving amplifier are discussed in the Input
Driver for the AUX Channel section.
The AUX channel in the ADS8684 and ADS8688 offers a true 16-bit performance with no missing codes. Some
typical performance characteristics of the AUX channel are illustrated in Figure 65 to Figure 68.
28
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8000
0.2
0.15
0.1
0
-0.002
-0.004
-0.006
-0.008
-0.01
-0.012
6000
4000
2000
0
0.05
0
Gain Error
-0.05
-0.1
-0.15
-0.2
Offset Error
-0.014
32763
32765
32767
32769
32771
26
59
92
125
±40
±7
Free-Air Temperature (oC)
Codes (LSB)
C050
C049
Mean = 32767.15, Sigma = 0.83, Input = 0.5 × VREF
AUX Channel
Figure 65. DC Histogram for Mid-Scale Input
(AUX Channel)
Figure 66. Offset and Gain vs Temperature
(AUX Channel)
0
90
-100
-101
-102
-103
-104
-105
±20
SNR
±40
±60
89
88
87
86
SINAD
±80
±100
±120
±140
±160
THD
0
50000
100000
150000
200000
250000
26
59
92
125
±40
±7
Free-Air Temperature (oC)
Input Frequency (Hz)
C051
C052
fIN = 1 kHz, SNR = 88.2 dB, SINAD = 88.1 dB, THD = –102 dB,
SFDR = 102 dB, Number of points = 64k
fIN = 1 kHz
Figure 68. SNR, SINAD, and THD vs Temperature
(AUX Channel)
Figure 67. Typical FFT Plot
(AUX Channel)
8.3.9.1 Input Driver for the AUX Channel
For applications that use the AUX input channels at high throughput and high input frequency, a driving amplifier
with low output impedance is required to meet the ac performance of the internal 16-bit ADC. Some key
specifications of the input driving amplifier are discussed below:
•
Small-signal bandwidth. The small-signal bandwidth of the input driving amplifier must be much higher than
the bandwidth of the AUX input to ensure that there is no attenuation of the input signal resulting from the
bandwidth limitation of the amplifier. In a typical data acquisition system, a low cut-off frequency, antialiasing
filter is used at the inputs of a high-resolution ADC. The amplifier driving the antialiasing filter must have a low
closed-loop output impedance for stability, which implies a higher gain bandwidth for the amplifier. Higher
small-signal bandwidth also minimizes the harmonic distortion at higher input frequencies. In general, the
amplifier bandwidth requirements can be calculated on the basis of Equation 1.
GBW t 4u fꢀ3dB
where:
•
f–3dB is the 3-dB bandwidth of the RC filter.
(1)
•
Distortion. In order to achieve the distortion performance of the AUX channel, the distortion of the input driver
must be at least 10 dB lower than the specified distortion of the internal ADC, as shown in Equation 2.
THDAMP d THDADC ꢂ 10 dB
(2)
29
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•
Noise. Careful considerations must be made to select a low-noise, front-end amplifier in order to prevent any
degradation in SNR performance of the system. As a rule of thumb, to ensure that the noise performance of
the data acquisition system is not limited by the front-end circuit, keep the total noise contribution from the
front-end circuit below 20% of the input-referred noise of the ADC. Noise from the input driver circuit is band-
limited by the low cut-off frequency of the input antialiasing filter, as explained in Equation 3.
2
SNR
ꢀ
dB
ꢁ
V
§
¨
·
¸
1
NG u
u10ꢂ
_ AMP_PP
VFSR
2 2
S
2
1
5
ꢃ en2 _RMS
u
u fꢂ3dB
d
u
f
20
¨
¨
¸
¸
6.6
©
¹
where:
•
•
•
V1 / f_AMP_PP is the peak-to-peak flicker noise,
en_RMS is the amplifier broadband noise density in nV/√Hz, and
NG is the noise gain of the front-end circuit, which is equal to 1 in a buffer configuration.
(3)
8.3.10 ADC Transfer Function
The ADS8684 and ADS8688 are a family of multichannel devices that support single-ended, bipolar, and
unipolar input ranges on all input channels. The output of the devices is in straight binary format for both bipolar
and unipolar input ranges. The format for the output codes is the same across all analog channels.
The ideal transfer characteristic for each ADC channel for all input ranges is shown in Figure 69. The full-scale
range (FSR) for each input signal is equal to the difference between the positive full-scale (PFS) input voltage
and the negative full-scale (NFS) input voltage. The LSB size is equal to FSR / 216 = FSR / 65536 because the
resolution of the ADC is 16 bits. For a reference voltage of VREF = 4.096 V, the LSB values corresponding to the
different input ranges are listed in Table 4.
FFFFh
8000h
0001h
FSR ± 1LSB
Analog Input (AIN_nP t AIN_nGND)
1LSB
FSR/2
NFS
PFS
Figure 69. 16-Bit ADC Transfer Function (Straight Binary Format)
Table 4. ADC LSB Values for Different Input Ranges (VREF = 4.096 V)
INPUT RANGE
±2.5 × VREF
POSITIVE FULL SCALE NEGATIVE FULL SCALE
FULL-SCALE RANGE
20.48 V
LSB (µV)
312.50
156.25
78.125
156.25
78.125
10.24 V
5.12 V
2.56 V
10.24 V
5.12 V
–10.24 V
–5.12 V
–2.56 V
0 V
±1.25 × VREF
10.24 V
±0.625 × VREF
0 to 2.5 × VREF
0 to 1.25 × VREF
5.12 V
10.24 V
0 V
5.12 V
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8.4 Device Functional Modes
8.4.1 Device Interface
8.4.1.1 Digital Pin Description
The digital data interface for the ADS8684 and ADS8688 is illustrated in Figure 70.
CS
SCLK
SDI
CS
SCLK
SDO
ADS8684
ADS8688
SDO
SDI
RST / PD
DAISY
RST / PD
DGND
Figure 70. Pin Configuration for the Digital Interface
The signals shown in Figure 70 are summarized as follows:
8.4.1.1.1 CS (Input)
CS indicates an active-low, chip-select signal. CS is also used as a control signal to trigger a conversion on the
falling edge. Each data frame begins with the falling edge of the CS signal. The analog input channel to be
converted during a particular frame is selected in the previous frame. On the CS falling edge, the devices sample
the input signal from the selected channel and a conversion is initiated using the internal clock. The device
settings for the next data frame can be input during this conversion process. When the CS signal is high, the
ADC is considered to be in an idle state.
8.4.1.1.2 SCLK (Input)
This pin indicates the external clock input for the data interface. All synchronous accesses to the device are
timed with respect to the falling edges of the SCLK signal.
8.4.1.1.3 SDI (Input)
SDI is the serial data input line. SDI is used by the host processor to program the internal device registers for
device configuration. At the beginning of each data frame, the CS signal goes low and the data on the SDI line
are read by the device at every falling edge of the SCLK signal for the next 16 SCLK cycles. Any changes made
to the device configuration in a particular data frame are applied to the device on the subsequent falling edge of
the CS signal.
8.4.1.1.4 SDO (Output)
SDO is the serial data output line. SDO is used by the device to output conversion data. The size of the data
output frame varies depending on the register setting for the SDO format; see Table 13. A low level on CS
releases the SDO pin from the Hi-Z state. SDO is kept low for the first 15 SCLK falling edges. The MSB of the
output data stream is clocked out on SDO on the 16th SCLK falling edge, followed by the subsequent data bits
on every falling edge thereafter. The SDO line goes low after the entire data frame is output and goes to a Hi-Z
state when CS goes high.
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Device Functional Modes (continued)
8.4.1.1.5 DAISY (Input)
DAISY is a serial input pin. When multiple devices are connected in daisy-chain mode, as illustrated in Figure 73,
the DAISY pin of the first device in the chain is connected to GND. The DAISY pin of every subsequent device is
connected to the SDO output pin of the previous device, and the SDO output of the last device in the chain goes
to the SDI of the host processor. If an application uses a stand-alone device, the DAISY pin is connected to
GND.
8.4.1.1.6 RST/PD (Input)
RST/PD is a dual-function pin. Figure 71 shows the timing of this pin and Table 5 explains the usage of this pin.
RST / PD
tPL_RST_PD
Figure 71. RST/PD Pin Timing
Table 5. RST/PD Pin Functionality
CONDITION
DEVICE MODE
40 ns < tPL_RST_PD ≤ 100 ns
The device is in RST mode and does not enter PWR_DN mode.
The device is in RST mode and may or may not enter PWR_DN
mode.
100 ns < tPL_RST_PD < 400 ns
NOTE: This setting is not recommended.
The device enters PWR_DN mode and the program registers are
reset to default value.
tPL_RST_PD ≥ 400 ns
The devices can be placed into power-down (PWR_DN) mode by pulling the RST/PD pin to a logic low state for
at least 400 ns. The RST/PD pin is asynchronous to the clock; thus, RST/PD can be triggered at any time
regardless of the status of other pins (including the analog input channels). When the device is in power-down
mode, any activity on the digital input pins (apart from the RST/PD pin) is ignored.
The program registers in the device can be reset to their default values (RST) by pulling the RST/PD pin to a
logic low state for no longer than 100 ns. This input is asynchronous to the clock. When RST/PD is pulled back
to a logic high state, the devices are placed in normal mode. One valid write operation must be executed on the
program register in order to configure the device, followed by an appropriate command (AUTO_RST or MAN) to
initiate conversions.
When the RST/PD pin is pulled back to a logic high level, the devices wake-up in a default state in which the
program registers are reset to their default values.
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8.4.1.2 Data Acquisition Example
This section provides an example of how a host processor can use the device interface to configure the device
internal registers as well as convert and acquire data for sampling a particular input channel. The timing diagram
shown in Figure 72 provides further details.
Sample
N
Sample
N + 1
CS
23
24
26
1
2
14
15
16
17
18
25
27
28
29
7
8
9
SCLK
30
31
32
Data from sample N
D14
D6
D5
D4
D3
D2
D1
D0
D15
D9
D8
D7
X
SDO
SDI
B14
B9
B8
B7
B2
B15
B1
B0
B3
X X X X X X X X
B10
1
2
3
4
Figure 72. Device Operation Using the Serial Interface Timing Diagram
There are four events shown in Figure 72. These events are described below:
•
Event 1: The host initiates a data conversion frame through a falling edge of the CS signal. The analog input
signal at the instant of the CS falling edge is sampled by the ADC and conversion is performed using an
internal oscillator clock. The analog input channel converted during this frame is selected in the previous data
frame. The internal register settings of the device for the next conversion can be input during this data frame
using the SDI and SCLK inputs. Initiate SCLK at this instant and latch data on the SDI line into the device on
every SCLK falling edge for the next 16 SCLK cycles. At this instant, SDO goes low because the device does
not output internal conversion data on the SDO line during the first 16 SCLK cycles.
•
•
•
Event 2: During the first 16 SCLK cycles, the device completes the internal conversion process and data are
now ready within the converter. However, the device does not output data bits on SDO until the 16th falling
edge appears on the SCLK input. Because the ADC conversion time is fixed (the maximum value is given in
the Electrical Characteristics table), the 16th SCLK falling edge must appear after the internal conversion is
over, otherwise data output from the device is incorrect. Therefore, the SCLK frequency cannot exceed a
maximum value, as provided in the Timing Requirements: Serial Interface table.
Event 3: At the 16th falling edge of the SCLK signal, the device reads the LSB of the input word on the SDI
line. The device does not read anything from the SDO line for the remaining data frame. On the same edge,
the MSB of the conversion data is output on the SDO line and can be read by the host processor on the
subsequent falling edge of the SCLK signal. For 16 bits of output data, the LSB can be read on the 32nd
SCLK falling edge. The SDO outputs 0 on subsequent SCLK falling edges until the next conversion is
initiated.
Event 4: When the internal data from the device is received, the host terminates the data frame by
deactivating the CS signal to high. The SDO output goes into a Hi-Z state until the next data frame is initiated,
as explained in Event 1.
8.4.1.3 Host-to-Device Connection Topologies
The digital interface of the ADS8684 and ADS8688 offers a lot of flexibility in the ways that a host controller can
exchange data or commands with the device. A typical connection between a host controller and a stand-alone
device is illustrated in Figure 70. However, there are applications that require multiple ADCs but the host
controller has limited interfacing capability. This section describes two connection topologies that can be used to
address the requirements of such applications.
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8.4.1.3.1 Daisy-Chain Topology
A typical connection diagram showing multiple devices in daisy-chain mode is shown in Figure 73. The CS,
SCLK, and SDI inputs of all devices are connected together and controlled by a single CS, SCLK, and SDO pin
of the host controller, respectively. The DAISY1 input pin of the first ADC in the chain is connected to DGND, the
SDO1 output pin is connected to the DAISY2 input of ADC2, and so forth. The SDON pin of the Nth ADC in the
chain is connected to the SDI pin of the host controller. The devices do not require any special hardware or
software configuration to enter daisy-chain mode.
Host Controller
SDI
SDO
CS
SCLK
CS
SCLK SDI
CS
SCLK SDI
CS
SCLK SDI
DAISY2
SDO2
DAISY1
SDO1
DAISYN
SDON
DGND
ADC1
ADC2
ADCN
Figure 73. Daisy-Chain Connection Schematic
A typical timing diagram for three devices connected in daisy-chain mode is shown in Figure 74.
Sample
N
Sample
N + 1
tS
CS
1
2
15
16
17
18
33
34
49
50
31
32
47
48
63
64
SCLK
SDI
X
X
X
X
X
X
X
X
X
X
B14
B2
B1
B0
X
B15
X
SDO1
& DAISY2
{D15}1 {D14}1
{D15}2 {D14}2
{D15}3 {D14}3
{D1}1 {D0}1
SDO2
& DAISY3
{D1}2 {D0}2 {D15}1 {D14}1
{D1}1 {D0}1
{D15}2 {D14}2
{D1}3 {D0}3
{D1}2 {D0}2 {D15}1 {D14}1
{D1}1 {D0}1
SDO3
Data from Sample N
ADC3
Data from Sample N
ADC2
Data from Sample N
ADC1
Figure 74. Three Devices Connected in Daisy-Chain Mode Timing Diagram
At the falling edge of the CS signal, all devices sample the input signal at their respective selected channels and
enter into conversion phase. For the first 16 SCLK cycles, the internal register settings for the next conversion
can be entered using the SDI line, which is common to all devices in the chain. During this time period, the SDO
outputs for all devices remain low. At the end of conversion, every ADC in the chain loads its own conversion
result into an internal 16-bit shift register. At the 16th SCLK falling edge, every ADC in the chain outputs the MSB
bit on its own SDO output pin. On every subsequent SCLK falling edge, the internal shift register of each ADC
latches the data available on its DAISY pin and shifts out the next bit of data on its SDO pin. Therefore, the
digital host receives the data of ADCN, followed by the data of ADCN–1, and so forth (in MSB-first fashion). In
total, a minimum of 16 × N SCLK falling edges are required to capture the outputs of all N devices in the chain.
This example uses three devices in a daisy-chain connection, so 3 × 16 = 48 SCLK cycles are required to
capture the outputs of all devices in the chain along with the 16 SCLK cycles to input the register settings for the
next conversion, resulting in a total of 64 SCLK cycles for the entire data frame. Note that the overall throughput
of the system is proportionally reduced with the number of devices connected in a daisy-chain configuration.
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The following points must be noted about the daisy-chain configuration illustrated in Figure 73:
•
The SDI pins for all devices are connected together so each device operates with the same internal
configuration. This limitation can be overcome by spending additional host controller resources to control the
SDI input of devices with unique configurations.
•
If the number of devices connected in daisy-chain is more than four, loading increases on the shared output
lines from the host controller (CS, SDO, and SCLK). This increased loading may lead to digital timing errors.
This limitation can be overcome by using digital buffers on the shared outputs from the host controller before
feeding the shared digital lines into additional devices.
8.4.1.3.2 Star Topology
A typical connection diagram showing multiple devices in the star topology is shown in Figure 75. The SDI and
SCLK inputs of all devices are connected together and are controlled by a single SDO and SCLK pin of the host
controller, respectively. Similarly, the SDO outputs of all devices are tied together and connected to the SDI input
pin of the host controller. The CS input pin of each device is individually controlled by separate CS control lines
from the host controller.
CS1
CS2
CS
SCLK
CSN
SDO
SDI
ADC1
CS
SCLK
SDI
SDO
SDI
ADC2
CS
SCLK
SDI
SDO
SDO
SCLK
ADCN
Figure 75. Star Topology Connection Schematic
The timing diagram for a typical data frame in the star topology is the same as in a stand-alone device operation,
as illustrated in Figure 72. The data frame for a particular device starts with the falling edge of the CS signal and
ends when the CS signal goes high. Because the host controller provides separate CS control signals for each
device in this topology, the user can select the devices in any order and initiate a conversion by bringing down
the CS signal for that particular device. As explained in Figure 72, when CS goes high at the end of each data
frame, the SDO output of the device is placed into a Hi-Z state. Therefore, the shared SDO line in the star
topology is controlled only by the device with an active data frame (CS is low). In order to avoid any conflict
related to multiple devices driving the SDO line at the same time, ensure that the host controller pulls down the
CS signal for only one device at any particular time.
TI recommends connecting a maximum of four devices in the star topology. Beyond that, loading may increase
on the shared output lines from the host controller (SDO and SCLK). This loading may lead to digital timing
errors. This limitation can be overcome by using digital buffers on the shared outputs from the host controller
before being fed into additional devices.
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8.4.2 Device Modes
The ADS8684 and ADS8688 support multiple modes of operation that are software programmable. After
powering up, the device is placed into idle mode and does not perform any function until a command is received
from the user. Table 6 lists all commands to enter the different modes of the device. After power-up, the program
registers wake up with the default values and require appropriate configuration settings before performing any
conversion. The diagram in Figure 76 explains how to switch the device from one mode of operation to another.
RESET
(RST)
Program Registers
are set to default
values
RST
NO_OP
IDLE
Device waits for a
valid command to
initiate conversion
MAN_Ch_n
NO_OP
NO_OP
MANUAL
Channel n
(MAN_Ch_n)
STANDBY
(STDBY)
MAN_Ch_n / AUTO_RST
STDBY / PWR_DN / PROG
AUTO
Ch. Scan
(AUTO)
POWER
DOWN
(PWR_DN)
PROGRAM
REGISTER
(PROG)
AUTO Seq.
RESET
(AUTO_RST)
PWR_DN
PROG
NO_OP
AUTO_RST
Figure 76. State Transition Diagram
8.4.2.1 Continued Operation in the Selected Mode (NO_OP)
Holding the SDI line low continuously (equivalent to writing a 0 to all 16 bits) during device operation continues
device operation in the last selected mode (STDBY, PWR_DN or AUTO_RST, MAN_Ch_n). In this mode, the
device follows the same settings that are already configured in the program registers (addresses 01h to 3Ch).
8.4.2.2 Frame Abort Condition (FRAME_ABORT)
As explained in the Data Acquisition Example section, the device digital interface is designed such that each data
frame starts with a falling edge of the CS signal. During the first 16 SCLK cycles, the device reads the 16-bit
command word on the SDI line. The device waits to execute the command until the last bit of the command is
received, which is latched on the 16th SCLK falling edge. During this operation, the CS signal must stay low. If
the CS signal goes high for any reason before the data transmission is complete, the device goes into IDLE state
and waits for a proper command to be written. This condition is called the FRAME_ABORT condition. When the
device is operating in IDLE mode, any read operation on the device returns all 1's on the SDO line.
If a FRAME_ABORT condition occurs when the device is performing any read or write operation in the program
register (PROG mode), then the device adopts the previous settings of the program registers until the user
executes a proper command to execute the program register read or write command.
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8.4.2.3 STANDBY Mode (STDBY)
The devices support a low-power standby mode (STDBY) in which only part of the circuit is powered down. The
internal reference and buffer is not powered down, and therefore, the device can be quickly powered up in 20 µs
on exiting the STDBY mode. When the device comes out of STDBY mode, the program registers are not reset to
the default values.
To enter STDBY mode, execute a valid write operation to the command register with a STDBY command of
8200h, as shown in Figure 77. The command is executed and the device enters STDBY mode on the next CS
rising edge following this write operation. The device remains in STDBY mode if no valid conversion command
(AUTO_RST or MAN_Ch_n) is executed and SDI remains low (refer to the Continued Operation in the Selected
Mode section) during the subsequent data frames. When the device operates in STDBY mode the program
register settings can be updated, as explained in Program Register Read/Write Operation section using 16 SCLK
cycles. However, if the user provides complete 32 SCLK cycles, then the SDO line yields all 1's on the last 16
SCLK cycles because there is no ongoing conversion in STDBY mode. The program register read operation can
take place normally during this mode.
Sample N
Enters STDBY on
CS Rising Edge
CS can go high immediately after Standby
command or after reading frame data
CS
16
17
16
1
2
14
15
18
30
31
32
1
2
14
15
SCLK
Stays in STDBY
if SDI is LOW in
a data frame
X
STDBY COMMAND ± 8200h
X
X
X
X
X
X
X
SDI
Data from sample N
B14
B2
B1
B0
B15
B3
SDO
Figure 77. Enter and Remain in STDBY Mode Timing Diagram
In order to exit STDBY mode a valid 16-bit write command must be executed to enter auto (AUTO_RST) or
manual (MAN_CH_n) scan mode, as shown in Figure 78. The device starts exiting STDBY mode on the next CS
rising edge. At the next CS falling edge, the device samples the analog input at the channel selected by the
MAN_CH_n command or the first channel of the AUTO_RST mode sequence. To ensure that the input signal is
sampled correctly, keep the minimum width of the CS signal at 20 µs after exiting STDBY mode so the device
can be fully powered up before taking the sample. The data output for the selected channel can be read during
the same data frame, as explained in Figure 72.
Device exits
STDBY Mode on
CS Rising Edge
CS
Min width of CS HIGH = 20µs
for valid sample
16
1
2
3
4
5
12
13
14
15
6
7
8
9
10
11
SCLK
AUTO_RST Command
MAN_CH_n Command
SDI
SDO
Figure 78. Exit STDBY Mode Timing Diagram
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8.4.2.4 Power-Down Mode (PWR_DN)
The devices support a hardware and software power-down mode (PWR_DN) in which all internal circuitry is
powered down, including the internal reference and buffer. A minimum time of 15 ms is required for the device to
power up and convert the selected analog input channel after exiting PWR_DN mode, if the device is operating
in the internal reference mode (REFSEL = 0). The hardware power mode for the device is explained in the
RST/PD (Input) section. The primary difference between the hardware and software power-down modes is that
the program registers are reset to default values when the devices wake up from hardware power-down, but the
previous settings of the program registers are retained when the devices wake up from software power-down.
To enter PWR_DN mode using software, execute a valid write operation on the command register with a
software PWR_DN command of 8300h, as shown in Figure 79. The command is executed and the device enters
PWR_DN mode on the next CS rising edge following this write operation. The device remains in PWR_DN mode
if no valid conversion command (AUTO_RST or MAN_Ch_n) is executed and SDI remains low (refer to the
Continued Operation in the Selected Mode section) during the subsequent data frames. When the device
operates in PWR_DN mode the program register settings can be updated, as explained in Program Register
Read/Write Operation section using 16 SCLK cycles. However, if the user provides complete 32 SCLK cycles,
then the SDO line yields all 1's on the last 16 SCLK cycles because there is no ongoing conversion in PWR_DN
mode. The program register read operation can take place normally during this mode.
Sample N
Enters PWR_DN on
CS Rising Edge
CS can go high immediately after PWR_DN
command or after reading frame data
CS
16
17
16
1
2
14
15
18
30
31
32
1
2
14
15
SCLK
Stays in PWR_DN
if SDI is LOW in a
data frame
X
PWR_DN COMMAND ± 8300h
X
X
X
X
X
X
X
SDI
Data from sample N
B14
B2
B1
B0
B15
B3
SDO
Figure 79. Enter and Remain in PWR_DN Mode Timing Diagram
In order to exit from PWR_DN mode a valid 16-bit write command must be executed, as shown in Figure 80. The
device comes out of PWR_DN mode on the next CS rising edge. For operation in internal reference mode
(REFSEL = 0), 15 ms are required for the device to power-up the reference and other internal circuits and settle
to the required accuracy before valid conversion data are output for the selected input channel.
First 16-bit accurate data
frame after recovery from
PWR_DN mode
Device exits PWR_DN Mode, but
waits 15ms for 16-bit settling
CS
16
1
2
3
4
5
12
13
14
15
6
7
8
9
10
11
SCLK
AUTO_RST Command
MAN_CH_n Command
SDI
SDO
Invalid
Data
Figure 80. Exit PWR_DN Mode Timing Diagram
38
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8.4.2.5 Auto Channel Enable with Reset (AUTO_RST)
The devices can be programmed to scan the input signal on all analog channels automatically by writing a valid
auto channel sequence with a reset (AUTO_RST, A000h) command in the command register, as explained in
Figure 81. The sequence of channels for the automatic scan can be configured by the AUTO SCAN sequencing
control register (01h to 02h) in the program register; refer to the Program Register Map section. In this mode, the
devices continuously cycle through the selected channels in ascending order, beginning with the lowest channel
and converting all channels selected in the program register. On completion of the sequence, the devices return
to the lowest count channel in the program register and repeat the sequence. The input voltage range for each
channel in the auto-scan sequence can be configured by setting the Range Select Registers of the program
registers.
Samples 2nd Ch. of
Sample N
Enters AUTO_RST Mode on CS Rising Edge
Auto-Ch Sequence
Samples 1st Ch. of Auto-Ch Sequence
CS can go high immediately after AUTO_RST
command or after reading frame data
CS
16
17
16
32
1
2
14
15
18
30
31
32
1
2
14
15
31
SCLK
Stays in AUTO_RST Mode if
SDI is LOW in a data frame
X
AUTO_RST COMMAND ± A000h
X
X
X
X
X
X
X
SDI
Data from sample N
Data from 1st Ch of Seq.
B14
B2
B1
B0
B15
B3
SDO
Figure 81. Enter AUTO_RST Mode Timing Diagram
The devices remain in AUTO_RST mode if no other valid command is executed and SDI is kept low (refer to the
Continued Operation in the Selected Mode (NO_OP) section) during subsequent data frames. If the AUTO_RST
command is executed again at any time during this mode of operation, then the sequence of the scanned
channels is reset. The devices return to the lowest count channel of the auto-scan sequence in the program
register and repeat the sequence. The timing diagram in Figure 82 shows this behavior using an example in
which channels 0 to 3 are selected in the auto sequence. For switching between AUTO_RST mode and
MAN_Ch_n mode, refer to the Channel Sequencing Modes section.
Sample
N
Ch 0
Sample
Ch 1
Sample
Ch 2
Sample
Ch 0
Sample
CS
SCLK
SDI
AUTO_RST
xxxx
0000h
xxxx
0000h
xxxx
AUTO_RST
xxxx
0000h
xxxx
SDO
Sample N Data
Ch 0 Data
Ch 1 Data
Ch 2 Data
Ch 0 Data
Based on Previous
Mode Setting
AUTO_RST Mode
(Channels 0-3 are selected in sequence)
AUTO_RST Mode
(Channel sequence re-started from
lowest count)
Figure 82. Device Operation Example in AUTO_RST Mode
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8.4.2.6 Manual Channel n Select (MAN_Ch_n)
The devices can be programmed to convert a particular analog input channel by operating in manual channel n
scan mode (MAN_Ch_n). This programming is done by writing a valid manual channel n select command
(MAN_Ch_n) in the command register, as shown in Figure 83. Refer to Table 6 for a list of commands to select
individual channels during MAN_Ch_n mode.
2nd Sample of Manual Ch. n
Sample N
Enters MAN_Ch_n mode on CS Rising Edge
1st Sample of Manual Channel N
CS can go high immediately after MAN_Ch_n
command or after reading frame data
CS
16
17
16
32
1
2
14
15
18
30
31
32
1
2
14
15
31
SCLK
Stays in MAN_Ch_n Mode if
SDI is LOW in a data frame
X
MAN_Ch_n COMMAND
X
X
X
X
X
X
X
SDI
Data from sample N
Sample 1 of Channel. n
B14
B2
B1
B0
B15
B3
SDO
Figure 83. Enter MAN_Ch_n Scan Mode Timing Diagram
The manual channel n select command (MAN_Ch_n) is executed and the devices sample the analog input on
the selected channel on the CS falling edge of the next data frame following this write operation. The input
voltage range for each channel in the MAN_Ch_n mode can be configured by setting the Range Select Registers
in the program registers. The device continues to sample the analog input on the same channel if no other valid
command is executed and SDI is kept low (refer to the Continued Operation in the Selected Mode (NO_OP)
section) during subsequent data frames. The timing diagram in Figure 84 illustrates this behavior using an
example in which channel 1 is selected in the manual sequencing mode. For switching between MAN_Ch_n
mode and AUTO_RST mode, refer to the Channel Sequencing Modes section.
Sample
N
Ch 1
Sample
Ch 1
Sample
Ch 1
Sample
Ch 3
Sample
CS
SCLK
SDI
MAN_Ch_1
xxxx
0000h
xxxx
0000h
xxxx
MAN_Ch_3
xxxx
0000h
xxxx
SDO
Sample N Data
Ch 1 Data
Ch 1 Data
Ch 1 Data
Ch 3 Data
Based on Previous
Mode Setting
MAN_Ch_n Mode
(Ch 1 is selected and device continuously converts Ch 1 if NO_OP command is provided)
MAN_Ch_n Mode
(Transition from Ch1 to Ch 3)
Figure 84. Device Operation in MAN_Ch_n Mode
40
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8.4.2.7 Channel Sequencing Modes
The devices offer two channel sequencing modes: AUTO_RST and MAN_Ch_n.
In AUTO_RST mode, the channel number automatically increments in every subsequent frame. As explained in
the Auto-Scan Sequencing Control Registers section, the analog inputs can be selected for an automatic scan
with a register setting. The device automatically scans only the selected analog inputs in ascending order. The
unselected analog input channels can also be powered down for optimizing power consumption in this mode of
operation. The auto-mode sequence can be reset at any time during an automatic scan (using the AUTO_RST
command). When the reset command is received, the ongoing auto-mode sequence is reset and restarts from
the lowest selected channel in the sequence.
In MAN_Ch_n mode, the same input channel is selected during every data conversion frame. The input
command words to select individual analog channels in MAN_Ch_n mode are listed in Table 6. If a particular
input channel is selected during a data frame, then the analog inputs on the same channel are sampled during
the next data frame. Figure 85 shows the SDI command sequence for transitions from AUTO_RST to
MAN_Ch_n mode.
Ch 0
Ch 5
Ch 1
Ch 3
Sample
Sample
Sample
Sample
CS
SCLK
SDI
0000h
xxxx
MAN_Ch_1
xxxx
MAN_Ch_3
xxxx
MAN_Ch_n
xxxx
SDO
Ch 0 Data
Ch 5 Data
Ch 1 Data
Ch 3 Data
AUTO_RST Mode
MAN_Ch_n Mode
Figure 85. Transitioning from AUTO_RST to MAN_Ch_n Mode
(Channels 0 and 5 are Selected for Auto Sequence)
Figure 86 shows the SDI command sequence for transitions from MAN_Ch_n to AUTO_RST mode. Note that
each SDI command is executed on the next CS falling edge. A RST command can be issued at any instant
during any channel sequencing mode, after which the device is placed into a default power-up state in the next
data frame.
Sample
N
Ch 2
Sample
Ch 0
Sample
Ch 5
Sample
CS
SCLK
SDI
MAN_Ch_2
xxxx
AUTO_RST
xxxx
0000h
xxxx
0000h
xxxx
SDO
Sample N Data
Ch 2 Data
Ch 0 Data
Ch 5 Data
Based on Previous
Mode Setting
MAN_Ch_n Mode
AUTO_RST Mode
Figure 86. Transitioning from MAN_Ch_n to AUTO_RST Mode
(Channels 0 and 5 are Selected for Auto Sequence)
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8.4.2.8 Reset Program Registers (RST)
The devices support a hardware and software reset (RST) mode in which all program registers are reset to their
default values. The devices can be put into RST mode using a hardware pin, as explained in the RST/PD (Input)
section.
The device program registers can be reset to their default values during any data frame by executing a valid
write operation on the command register with a RST command of 8500h, as shown in Figure 87. The device
remains in RST mode if no valid conversion command (AUTO_RST or MAN_Ch_n) is executed and SDI remains
low (refer to the Continued Operation in the Selected Mode (NO_OP) section) during the subsequent data
frames. When the device operates in RST mode, the program register settings can be updated, as explained in
Program Register Read/Write Operation section using 16 SCLK cycles. However, if the user provides complete
32 SCLK cycles, then the SDO line yields all 1's on the last 16 SCLK cycles because there is no ongoing
conversion in RST mode. The values of the program register can be read normally during this mode. A valid
AUTO_RST or MAN_CH_n channel selection command must be executed for initiating a conversion on a
particular analog channel using the default program register settings.
All Program
Registers are reset
Sample N
to default value on
CS rising edge
CS can go high immediately after RST
command or after reading frame data
CS
16
17
1
2
13
14
15
18
30
31
32
3
4
5
SCLK
X
Reset Program Registers (RST) ± 8500h
X
X
X
X
X
X
X
SDI
Data from sample N
B14
B2
B1
B0
B15
B3
SDO
Figure 87. Reset Program Registers (RST) Timing Diagram
42
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8.5 Register Map
The internal registers of the ADS8684 and ADS8688 are categorized into two categories: command registers and
program registers.
The command registers are used to select the channel sequencing mode (AUTO_RST or MAN_Ch_n), configure
the device in standby (STDBY) or power-down (PWR_DN) mode, and reset (RST) the program registers to their
default values.
The program registers are used to select the sequence of channels for AUTO_RST mode, select the SDO output
format, and control input range settings for individual channels.
8.5.1 Command Register Description
The command register is a 16-bit, write-only register that is used to set the operating modes of the ADS8684 and
ADS8688. The settings in this register are used to select the channel sequencing mode (AUTO_RST or
MAN_Ch_n), configure the device in standby (STDBY) or power-down (PWR_DN) mode, and reset (RST) the
program registers to their default values. All command settings for this register are listed in Table 6. During
power-up or reset, the default content of the command register is all 0's and the device waits for a command to
be written before being placed into any mode of operation. Refer to Figure 1 for a typical timing diagram for
writing a 16-bit command into the device. The device executes the command at the end of this particular data
frame when the CS signal goes high.
Table 6. Command Register Map
MSB BYTE
LSB BYTE
B[7:0]
COMMAND
(Hex)
REGISTER
OPERATION IN NEXT FRAME
B15
B14
B13
B12
B11
B10
B9
B8
Continued Operation
(NO_OP)
0
0
0
0
0
0
0
0
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000h
8200h
8300h
8500h
A000h
C000h
C400h
C800h
CC00h
D000h
D400h
D800h
DC00h
E000h
Continue operation in previous mode
Device is placed into standby mode
Device is powered down
Standby
(STDBY)
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
Power Down
(PWR_DN)
Reset program registers
(RST)
Program register is reset to default
Auto mode enabled following a reset
Channel 0 input is selected
Channel 1 input is selected
Channel 2 input is selected
Channel 3 input is selected
Channel 4 input is selected
Channel 5 input is selected
Channel 6 input is selected
Channel 7 input is selected
AUX channel input is selected
Auto Ch. Sequence with Reset
(AUTO_RST)
Manual Ch 0 Selection
(MAN_Ch_0)
Manual Ch 1 Selection
(MAN_Ch_1)
Manual Ch 2 Selection
(MAN_Ch_2)
Manual Ch 3 Selection
(MAN_Ch_3)
Manual Ch 4 Selection
(MAN_Ch_4)(1)
Manual Ch 5 Selection
(MAN_Ch_5)
Manual Ch 6 Selection
(MAN_Ch_6)
Manual Ch 7 Selection
(MAN_Ch_7)
Manual AUX Selection
(MAN_AUX)
(1) Shading indicates bits and/or registers not included in the 4-channel version of the device.
8.5.2 Program Register Description
The program register is a 16-bit register used to set the operating modes of the ADS8684 and ADS8688. The
settings in this register are used to select the channel sequence for AUTO_RST mode, configure the device ID in
daisy-chain mode, select the SDO output format, and control the input range settings for individual channels. All
program settings for this register are listed in Table 9. During power-up or reset, the default content of the
program register is all 0's and the device waits for a command to be written before being placed into any mode of
operation.
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8.5.2.1 Program Register Read/Write Operation
The program register is a 16-bit read or write register. There must be a minimum of 16 SCLKs after the CS
falling edge for any read or write operation to the program registers. When CS goes low, the SDO line goes low
as well. The device receives the command (as shown in Table 7 and Table 8) through SDI where the first seven
bits (bits[15:9]) represent the register address and the eighth bit (bit 8) is the write or read instruction.
For a write cycle, the next eight bits (bits[7:0]) on the SDI are the desired data for the addressed register. A
typical timing diagram for a program register write cycle is shown in Figure 88.
Table 7. Write Cycle Command Word
REGISTER ADDRESS
BIT[15:9]
WR/RD
BIT 8
1
DATA
BITS[7:0]
DIN[7:0]
PIN
SDI
ADDR[6:0]
Sample
N
CS
32
16
31
15
17
18
1
2
6
7
8
9
10
SCLK
SDI
DIN [7:0]
X X X X
ADDR [6:0]
WR
Sample N Conversion Data
SDO
Figure 88. Timing Diagram Showing Program Register Write Cycle
For a read cycle, the next eight bits (bits[7:0]) in the SDI are don’t care bits. SDO outputs the 8-bit data from the
addressed register during these eight clocks, in MSB-first fashion. A typical timing diagram for a program register
read cycle is shown in Figure 89.
Table 8. Read Cycle Command Word
REGISTER ADDRESS
BIT[15:9]
WR/RD
DATA
BITS[7:0]
XXXXX
PIN
BIT 8
SDI
ADDR[6:0]
0
0
SDO
0000 000
DOUT[7:0]
CS
24
16
23
15
17
18
1
2
6
7
8
9
10
SCLK
SDI
X X X X X X
ADDR [6:0]
RD
DOUT [7:0]
SDO
Figure 89. Program Register Read Cycle Timing Diagram
44
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8.5.2.2 Program Register Map
This section provides a bit-by-bit description of each program register.
Table 9. Program Register Map
REGISTER
DEFAULT
REGISTER
ADDRESS
BITS[15:9]
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
VALUE(1)
AUTO SCAN SEQUENCING CONTROL
AUTO_SEQ_EN
01h
02h
FFh
00h
CH7_EN(2)
CH7_PD
CH6_EN
CH6_PD
CH5_EN
CH5_PD
CH4_EN
CH4_PD
CH3_EN
CH3_PD
CH2_EN
CH2_PD
CH1_EN
CH1_PD
CH0_EN
CH0_PD
Channel Power Down
DEVICE FEATURES SELECTION CONTROL
Feature Select
RANGE SELECT REGISTERS
Channel 0 Input Range
Channel 1 Input Range
Channel 2 Input Range
Channel 3 Input Range
Channel 4 Input Range
Channel 5 Input Range
Channel 6 Input Range
Channel 7 Input Range
Ch 0 Hysteresis
03h
00h
DEV[1:0]
1
0
1
SDO [2:0]
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
15h
16h
17h
18h
19h
38h
39h
3Ah
3Bh
3Ch
00h
00h
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
00h
00h
00h
FFh
FFh
00h
00h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Range Select Channel 0 [2:0]
Range Select Channel 1 [2:0]
Range Select Channel 2 [2:0]
Range Select Channel 3 [2:0]
Range Select Channel 4 [2:0]
Range Select Channel 5 [2:0]
Range Select Channel 6 [2:0]
Range Select Channel 7 [2:0]
CH0_HYST [7:0]
Ch 0 High Threshold MSB
Ch 0 High Threshold LSB
Ch 0 Low Threshold MSB
Ch 0 Low Threshold LSB
Ch 7 Hysteresis
CH0_HT [15:8]
CH0_HT [7:0]
CH0_LT [15:8]
CH0_LT [7:0]
CH7_HYST [7:0]
CH7_HT [15:8]
CH7_HT [7:0]
CH7_LT [15:8]
CH7_LT [7:0]
Ch 7 High Threshold MSB
Ch 7 High Threshold LSB
Ch 7 Low Threshold MSB
Ch 7 Low Threshold LSB
COMMAND READ BACK (Read-Only)
Command Read Back
3Fh
00h
COMMAND_WORD [7:0]
(1) All registers are reset to the default values at power-on or at device reset using the register settings method.
(2) Shading indicates bits or registers that are not included in the 4-channel version of the device. A write operation on any of these bits or
registers has no effect on device behavior. A read operation on any of these bits or registers outputs all 1's on the SDO line.
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8.5.2.3 Auto-Scan Sequencing Control Registers
In AUTO_RST mode, the device automatically scans the preselected channels in ascending order with a new
channel selected for every conversion. Each individual channel can be selectively included in the auto channel
sequencing. For the channels that are not selected for auto sequencing, the analog front-end circuitry can be
individually powered down.
8.5.2.3.1 Auto-Scan Sequence Enable Register (address = 01h)
This register selects individual channels for sequencing in AUTO_RST mode. The default value for this register is
FFh, which implies that in default condition all channels are included in the auto-scan sequence.
Figure 90. AUTO_SEQ_EN Register
7
6
5
4
3
2
1
0
CH7_EN(1)
CH6_EN
R/W
CH5_EN
R/W
CH4_EN
R/W
CH3_EN
R/W
CH2_EN
R/W
CH1_EN
R/W
CH0_EN
R/W
R/W
LEGEND: R/W = Read/Write
(1) Shading indicates bits or registers that are not included in the 4-channel version of the device. A write operation on any of these bits or
registers has no effect on device behavior. A read operation on any of these bits or registers outputs all 1's on the SDO line.
Table 10. AUTO_SEQ_EN Field Descriptions
Bit
Field
Type
Reset
Description
Channel 7 enable.
7
CH7_EN
R/W
1h
0 = Channel 7 is not selected for sequencing in AUTO_RST mode
1 = Channel 7 is selected for sequencing in AUTO_RST mode
Channel 6 enable.
6
5
4
3
2
1
0
CH6_EN
CH5_EN
CH4_EN
CH3_EN
CH2_EN
CH1_EN
CH0_EN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1h
1h
1h
1h
1h
1h
1h
0 = Channel 6 is not selected for sequencing in AUTO_RST mode
1 = Channel 6 is selected for sequencing in AUTO_RST mode
Channel 5 enable.
0 = Channel 5 is not selected for sequencing in AUTO_RST mode
1 = Channel 5 is selected for sequencing in AUTO_RST mode
Channel 4 enable.
0 = Channel 4 is not selected for sequencing in AUTO_RST mode
1 = Channel 4 is selected for sequencing in AUTO_RST mode
Channel 3 enable.
0 = Channel 3 is not selected for sequencing in AUTO_RST mode
1 = Channel 3 is selected for sequencing in AUTO_RST mode
Channel 2 enable.
0 = Channel 2 is not selected for sequencing in AUTO_RST mode
1 = Channel 2 is selected for sequencing in AUTO_RST mode
Channel 1 enable.
0 = Channel 1 is not selected for sequencing in AUTO_RST mode
1 = Channel 1 is selected for sequencing in AUTO_RST mode
Channel 0 enable.
0 = Channel 0 is not selected for sequencing in AUTO_RST mode
1 = Channel 0 is selected for sequencing in AUTO_RST mode
46
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8.5.2.3.2 Channel Power Down Register (address = 02h)
This register powers down individual channels that are not included for sequencing in AUTO_RST mode. The
default value for this register is 00h, which implies that in default condition all channels are powered up.
Figure 91. Channel Power Down Register
7
6
5
4
3
2
1
0
CH7_PD(1)
CH6_PD
R/W
CH5_PD
R/W
CH4_PD
R/W
CH3_PD
R/W
CH2_PD
R/W
CH1_PD
R/W
CH0_PD
R/W
R/W
LEGEND: R/W = Read/Write
(1) Shading indicates bits or registers that are not included in the 4-channel version of the device. A write operation on any of these bits or
registers has no effect on device behavior. A read operation on any of these bits or registers outputs all 1's on the SDO line.
Table 11. Channel Power Down Register Field Descriptions
Bit
Field
Type
Reset
Description
Channel 7 power-down.
0 = The analog front-end on channel 7 is powered up and channel 7 can be
included in the AUTO_RST sequence
7
CH7_PD
R/W
0h
1 = The analog front-end on channel 7 is powered down and channel 7
cannot be included in the AUTO_RST sequence
Channel 6 power-down.
0 = The analog front-end on channel 6 is powered up and channel 6 can be
included in the AUTO_RST sequence
1 = The analog front-end on channel 6 is powered down and channel 6
cannot be included in the AUTO_RST sequence
6
5
4
3
2
1
0
CH6_PD
CH5_PD
CH4_PD
CH3_PD
CH2_PD
CH1_PD
CH0_PD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
Channel 5 power-down.
0 = The analog front-end on channel 5 is powered up and channel 5 can be
included in the AUTO_RST sequence
1 = The analog front-end on channel 5 is powered down and channel 5
cannot be included in the AUTO_RST sequence
Channel 4 power-down.
0 = The analog front-end on channel 4 is powered up and channel 4 can be
included in the AUTO_RST sequence
1 = The analog front-end on channel 4 is powered down and channel 4
cannot be included in the AUTO_RST sequence
Channel 3 power-down.
0 = The analog front-end on channel 3 is powered up and channel 3 can be
included in the AUTO_RST sequence
1 = The analog front end on channel 3 is powered down and channel 3
cannot be included in the AUTO_RST sequence
Channel 2 power-down.
0 = The analog front end on channel 2 is powered up and channel 2 can be
included in the AUTO_RST sequence
1 = The analog front end on channel 2 is powered down and channel 2
cannot be included in the AUTO_RST sequence
Channel 1 power-down.
0 = The analog front end on channel 1 is powered up and channel 1 can be
included in the AUTO_RST sequence
1 = The analog front end on channel 1 is powered down and channel 1
cannot be included in the AUTO_RST sequence
Channel 0 power-down.
0 = The analog front end on channel 0 is powered up and channel 0 can be
included in the AUTO_RST sequence
1 = The analog front end on channel 0 is powered down and channel 0
cannot be included in the AUTO_RST sequence
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8.5.2.4 Device Features Selection Control Register (address = 03h)
The bits in this register can be used to configure the device ID for daisy-chain operation and configure the output
bit format on SDO.
Figure 92. Feature Select Register
7
6
5
1
4
0
3
1
2
1
0
DEV[1:0]
SDO[2:0]
R/W
R/W
R/W
R
R
R
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only
Table 12. Feature Select Register Field Descriptions
Bit
Field
Type
Reset
Description
Device ID bits.
00 = ID for device 0 in daisy-chain mode
01 = ID for device 1 in daisy-chain mode
10 = ID for device 2 in daisy-chain mode
11 = ID for device 3 in daisy-chain mode
7:6
DEV[1:0]
R/W
0h
5
4
1
R
1h
0h
1h
0h
Must always be set to 1
0
R
Must always be set to 0
3
1
R
Must always be set to 1
2:0
SDO[2:0]
R/W
SDO data format bits (refer to Table 13).
Table 13. Description of Program Register Bits for SDO Data Format
OUTPUT FORMAT
BITS[8:5]
SDO FORMAT
SDO[2:0}
BEGINNING OF THE
OUTPUT BIT STREAM
BITS[24:9]
BITS[4:3]
BITS[2:0]
16th SCLK falling edge;
no latency
Conversion result for selected
channel (MSB-first)
000
001
010
011
SDO pulled low
16th SCLK falling edge;
no latency
Conversion result for selected
channel (MSB-first)
Channel
SDO pulled low
address(1)
16th SCLK falling edge;
no latency
Conversion result for selected
channel (MSB-first)
Channel
Device
SDO pulled
low
address(1)
address(1)
16th SCLK falling edge;
no latency
Conversion result for selected
channel (MSB-first)
Channel
Device
Input range
address(1)
address(1)
(1)
(1) Table 14 lists the bit descriptions for these channel addresses, device addresses, and input range.
Table 14. Bit Description for the SDO Data
BIT
BIT DESCRIPTION
24:9
8:5
16 bits of conversion result for the channel represented in MSB-first format.
Four bits of channel address.
0000 = Channel 0
0001 = Channel 1
0010 = Channel 2
0011 = Channel 3
0100 = Channel 4 (valid only for the ADS8688)
0101 = Channel 5 (valid only for the ADS8688)
0110 = Channel 6 (valid only for the ADS8688)
0111 = Channel 7 (valid only for the ADS8688)
4:3
2:0
Two bits of device address (mainly useful in daisy-chain mode).
Three bits of input voltage range (refer to the Range Select Registers (address = 05h
(channel 0), 06h (channel 1), 07h (channel 2),
08h (channel 3), 09h (channel 4), 0Ah (channel 5), 0Bh (channel 6), 0Ch (channel 7))).
48
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8.5.2.5 Range Select Registers (address = 05h (channel 0), 06h (channel 1), 07h (channel 2),
08h (channel 3), 09h (channel 4), 0Ah (channel 5), 0Bh (channel 6), 0Ch (channel 7))
These registers allow the selection of input ranges for all individual channels (n = 0 to 3 for ADS8684 and n = 0
to 7 for ADS8688). The default value for these registers is 00h.
Figure 93. Channel n Input Range Registers
7
0
6
0
5
0
4
0
3
0
2
1
0
Range_CHn[2:0]
R/W
R
R
R
R
R
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only
Table 15. Channel n Input Range Registers Field Descriptions
Bit
Field
Type
Reset
Description
7:3
0
R
0h
Must always be set to 0
Input range selection bits for channel n (n = 0 to 3 for ADS8684 and n = 0
to 7 for ADS8688).
000 = Input range is set to ±2.5 x VREF
001 = Input range is set to ±1.25 x VREF
010 = Input range is set to ±0.625 x VREF
101 = Input range is set to 0 to 2.5 x VREF
110 = Input range is set to 0 to 1.25 x VREF
2:0
Range_CHn[2:0]
R/W
0h
8.5.3 Command Read-Back Register (address = 3Fh)
This register allows the user to read the device mode of operation. On execution of this command, the device
outputs the command word executed in the previous data frame. The output of the command register appears on
SDO from the 16th falling edge onwards in an MSB-first format. All information regarding the command register
is contained in the first eight bits and the last eight bits are 0 (refer to Table 6) so the user may stop the
command read-back operation after the 24th SCLK cycle.
Figure 94. Command Read-Back Register
7
6
5
4
3
2
1
0
COMMAND_WORD[15:8]
R
R
R
R
R
R
R
R
LEGEND: R = Read only
Table 16. Command Read-Back Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
COMMAND_WORD[15:8]
R
0h
Command executed in previous data frame.
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9 Application and Implementation
9.1 Application Information
The ADS8684 and ADS8688 devices are fully-integrated data acquisition systems based on a 16-bit SAR ADC.
The devices include an integrated analog front-end for each input channel and an integrated precision reference
with a buffer. As such, this device family does not require any additional external circuits for driving the reference
or analog input pins of the ADC.
9.2 Typical Applications
9.2.1 Phase-Compensated, 8-Channel, Multiplexed Data Acquisition System for Power Automation
Ch1 Input, V1
Ch i Input, Vi
Ref. Input, VR
¨ꢀꢀ= Measured Phase Diff.
(i = 1 to 7)
between channels
Angle (ꢀ)
¨ꢀr1
¨ꢀri
(i = 1 to 7)
AVDD = 5V
AIN_0P
R0P
1 M:
1 M:
ADS8688
PGA
LPF
C0
AIN_0GND
R0M
Simple Capture Card
16 bit
ADC
AIN_7P
R7P
1 M:
1 M:
FPGA
SITARA
PGA
LPF
C7
DDR
AIN_7GND
R7M
4.096V
AGND
Typical 50Hz
Sinewave from CT/PT
Balanced RC Filter
on Each Input
Figure 95. 8-Channel, Multiplexed Data Acquisition System for Power Automation
9.2.1.1 Design Requirements
In modern power grids, accurately measuring the electrical parameters of the various areas of the power grid is
extremely critical. This measurement helps determine the operating status and running quality of the grid. Such
accurate measurements also help diagnose potential problems with the power network so that these problems
can be resolved quickly without having any significant service impact. The key electrical parameters include
amplitude, frequency, and phase, which are important for calculating the power factor, power quality, and other
parameters of the power system.
The phase angle of the electrical signal on the power network buses is a special interest to power system
engineers. The primary objective for this design is to accurately measure the phase and phase difference
between the analog input signals in a multichannel data acquisition system. When multiple input channels are
sampled in a sequential manner as in a multiplexed ADC, an additional phase delay is introduced between the
channels. Thus the phase measurements are not accurate. However, this additional phase delay is constant and
can be compensated in application software.
The key design requirements are given below:
•
•
•
Single-ended sinusoidal input signal with a ±10-V amplitude and typical frequency (fIN = 50 Hz).
Design an 8-channel multiplexed data acquisition system using a 16-bit SAR ADC.
Design a software algorithm to compensate for the additional phase difference between the channels.
50
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Typical Applications (continued)
9.2.1.2 Detailed Design Procedure
The application circuit and system diagram for this design is shown in Figure 95. This design includes a complete
hardware and software implementation of a multichannel data acquisition system for power automation
applications.
The system hardware uses the ADS8688, which is a 16-bit, 500-kSPS, 8-channel, multiplexed input, SAR ADC
with integrated precision reference and analog front-end circuitry for each channel. The ADC supports bipolar
input ranges up to ±10.24 V with a single 5-V supply and provides minimum latency in data output resulting from
the SAR architecture. The integration offered by this device makes the ADS8684 and ADS8688 an ideal
selection for such applications, because the integrated signal conditioning helps minimize system components
and avoids the need for generating high-voltage supply rails. The overall system-level dc precision (gain and
offset errors) and low temperature drift offered by this device helps system designers achieve the desired system
accuracy without calibration. In most applications, using passive RC filters or multi-stage filters in front of the
ADC is preferred to reduce the noise of the input signal.
The software algorithm implemented in this design uses the discrete fourier transform (DFT) method to calculate
and track the input signal frequency, get the exact phase angle of the individual signal, calculate the phase
difference, and implement phase compensation. The entire algorithm has four steps:
•
•
•
•
Calculate the theoretical phase difference introduced by the ADC resulting from multiplexing input channels.
Estimate the frequency of the input signal using frequency tracking and DFT techniques.
Calculate the phase angle of all signals in the system based on the estimated frequency.
Compensate the phase difference for all channels using the theoretical value of an additional MUX phase
delay calculated in the first step.
9.2.1.3 Application Curve
The performance summary for this design is summarized in Table 17 and Figure 96. In this example, multiple
sinusoidal input signals of amplitude ±10 V are applied to the inputs of the ADC. The initial phase angle is the
same for all signals, but the input frequency is varied from 45 Hz to 55 Hz. The phase error in the last column of
Table 17 reflects the measurement accuracy of this design.
Table 17. Theoretical and Measured Phase Difference
THEORETICAL PHASE
ERROR(1)
MEASURED PHASE
ERROR(2)
PHASE ERROR AFTER
COMPENSATION(3)
INPUT TEST CONDITION
Phase difference
(consecutive channels)
0.036°
0.252°
0.036145°
0.249964°
0.000145°
0.002036°
Phase difference
(farthest channels, channel 0 to channel 7)
(1) Theoretical phase difference introduced by multiplexing is calculated based on the formula: Δφ = (fIN / fADC) × N × 360°, where N =
integral gap between two channels in the multiplexer sequence; fIN = input signal frequency; and fADC = 500 kSPS, maximum throughput
of the ADC.
(2) Measured phase value (before compensation) includes phase difference between any two channels resulting from multiplexing ADC
inputs.
(3) The algorithm subtracts theoretical phase difference from the measured phase to compensate for the phase difference resulting from the
MUX inputs.
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0.04
0.038
0.036
0.034
0.032
0.03
Measured Phase Difference
Theoretical Phase Difference
45
46
47
48
49
50
51
52
53
54
55
Input Signal Frequency (Hz)
C066
Figure 96. Measured and Theoretical Phase Difference Between Consecutive Channels
For a step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to Phase Compensated 8-Channel, Multiplexed Data Acquisition System for Power Automation
Reference Design (TIDU427).
9.2.2 16-Bit, 8-Channel, Integrated Analog Input Module for Programmable Logic Controllers (PLCs)
24 VDC_LIMIT
+24 VDC
Hot Swap
Protection
LM5069
Power
Isolated
+ 6V VISO
+ 5V VISO, 25mA
LDO
Supply
TPS71501
LM5017
+ 9.3 VDC
+ 5V VISO
3.3 VDC,
15mA
+ 5V VISO
50 Pin
Interface
Connector
(To Base
Board)
LDO
TPS71533
Filter
4 SE Voltage Inputs:
±10 VDC
AVDD
DVDD
Protection
Protection
0 ± 10 VDC
0 ± 5 VDC
1 ± 5 VDC
ADS8688
16 bit, 8-Ch, 500 kSPS
SAR ADC
SPI
4 Current Inputs:
0 ± 20 mA
4 ± 20 mA
3.3 VDC
Filter
Digital Isolator
ISO7141CC
I2C
EEPROM
Figure 97. 16-Bit, 8-Channel, Integrated Analog Input Module for PLCs
52
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9.2.2.1 Design Requirements
This reference design provides a complete solution for a single-supply industrial control analog input module.
The design is suitable for process control end equipment such as programmable logic controllers (PLCs),
distributed control systems (DCS) and data acquisition systems (DAS) modules that must digitize standard
industrial current inputs, and bipolar or unipolar input voltage ranges up to ±10 V. In an industrial environment,
the analog voltage and current ranges typically include ±2.5 V, ±5 V, ±10 V, 0 V to 5 V, 0 V to 10 V, 4 mA to
20 mA, and 0 mA to 20 mA. This reference design can measure all standard industrial voltage and current
inputs. Eight channels are provided on the module, and each channel can be configured as a current or voltage
input with software configuration.
The key design requirements are given below:
•
Up to eight channels of user-programmable inputs:
–
–
Voltage inputs (with a typical ZIN of 1 MΩ): ±10 V, ±5 V, ±2.5 V, 0 V to 10 V and 0 V to 5 V.
Current inputs (with a ZIN of 300 Ω): 0 mA to 20 mA, 4 mA to 20 mA, and ±20 mA.
•
•
•
•
•
•
A 16-bit SAR ADC with SPI.
Accuracy of ≤ 0.2% at 25°C over entire input range of voltage and current inputs.
Onboard isolated Fly-Buck™ power supply with inrush current protection.
Slim-form factor 96 × 50.8 × 10 mm (L × W × H).
LabView-based GUI for signal-chain analysis and functional testing.
Designed to comply with IEC61000-4 standards for ESD, EFT, and surge.
9.2.2.2 Detailed Design Procedure
The application circuit and system diagram for this design is shown in Figure 97.
The module has eight analog input channels, and each channel can be configured as a current or voltage input
with software configuration. The design uses the ADS8688 (16-bit, 8-channel, single-supply SAR ADC) with an
on-chip PGA and reference. The on-chip PGA provides a high-input impedance (typically 1 MΩ) and filters noise
interference. The on-chip, 4.096-V, ultra-low drift voltage reference is used as the reference for the ADC core.
The digital isolation is achieved using an ISO7141CC and ISO1541D. The host microcontroller communicates
with a TCA6408A (an 8-bit, I2C, I/O expander over an I2C bus). The ISO1541D is a bidirectional, I2C isolator that
isolates the I2C lines for the TCA6408A. The TCA6408A controls the low RON opto-switch (TLP3123), which is
used to switch between voltage-to-current input modes. The input channel configuration is done in
microcontroller firmware.
A low-cost, constant, on-time, synchronous buck regulator in fly-buck configuration with an external transformer
(LM5017) generates the isolated power supply. The LM5017 has a wide input supply range, making this device
ideal for accepting a 24-V industrial supply. This transformer can accept up to 100 V, thereby making reliable
transient protection of the input supply more easily achievable. The fly-buck power supply isolates and steps the
input voltage down to 6 V. The supply then provides that voltage to the TPS70950 (the low dropout regulator) to
generate 5 V to power the ADS8688 and other circuitry. The LM5017 also features a number of other safety and
reliability functions, such as undervoltage lockout (UVLO), thermal shutdown, and peak current limit protection.
Input analog signals are protected against high-voltage, fast-transient events often expected in an industrial
environment. The protection circuitry makes use of the transient voltage suppressor (TVS) and ESD diodes. The
RC low-pass mode filters are used on each analog input before the input reaches the ADS8688, which eliminates
any high-frequency noise pickups and minimizes aliasing.
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9.2.2.3 Application Curve
The performance summary for this design is summarized in Table 18.
Table 18. Measurement Results Summary for PLC Analog Input Module Design
ADS8688
SPECIFICATION
SERIAL NUMBER
PARAMETER
INPUT RANGE
MEASURED RESULT
±10 V
0 V 10 V
0 V to 5 V
±10 V
90 dB (min)
90.85 dB
89.52 dB
88.48 dB
14.80
14.58
14.41
1.77
1
SNR (dB)
88.5 dB (min)
87.5 dB (min)
14.66
14.41
14.24
2
2
3
4
ENOB (bits)
0 V 10 V
0 V to 5 V
±10 V
Maximum INL (LSB)
Minimum INL (LSB)
0 V 10 V
0 V to 5 V
±10 V
2
1.64
2
1.35
–2
–1.47
–1.36
–1.37
0 V 10 V
0 V to 5 V
–2
–2
The accuracy performance for this design for the ±10.24-V input range is shown in Figure 98.
0.08
Pre Calibration Error
Post Calibration Error
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
0
10000
20000
30000
40000
50000
60000
Digital Output Code
C067
Figure 98. System Accuracy Performance in ±2.5 × VREF Input Range
For a step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to 16-Bit, 8-Channel, Integrated Analog Input Module for Programmable Logic Controllers (PLCs)
(TIDU365).
54
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10 Power-Supply Recommendations
The device uses two separate power supplies: AVDD and DVDD. The internal circuits of the device operate on
AVDD, while DVDD is used for the digital interface. AVDD and DVDD can be independently set to any value
within the permissible range.
The AVDD supply pins must be decoupled with AGND by using a minimum 10-µF and 1-µF capacitor on each
supply. Place the 1-µF capacitor as close to the supply pins as possible. Place a minimum 10-µF decoupling
capacitor very close to the DVDD supply to provide the high-frequency digital switching current. The effect of
using the decoupling capacitor is illustrated in the difference between the power-supply rejection ratio (PSRR)
performance of the device. Figure 99 shows the PSRR of the device without using a decoupling capacitor. The
PSRR improves when the decoupling capacitors are used, as shown in Figure 100.
140
120
100
80
140
120
100
80
----- ± 2.5*VREF
----- ± 1.25*VREF
----- ± 0.625*VREF
------ +2.5*VREF
------+1.25*VREF
----- ± 2.5*VREF
----- ± 1.25*VREF
----- ± 0.625*VREF
------ +2.5*VREF
------+1.25*VREF
60
60
40
40
100
1000
10000
100000
1000000 10000000
50
500
5000
50000
500000 5000000
Input Frequency (Hz)
Input Frequency (Hz)
C046
C045
Code output near 32,769
Figure 99. PSRR Without a Decoupling Capacitor
Code output near 32,768
Figure 100. PSRR With a Decoupling Capacitor
11 Layout
11.1 Layout Guidelines
Figure 101 illustrates a PCB layout example for the ADS8684 and ADS8688.
•
Partition the PCB into analog and digital sections. Care must be taken to ensure that the analog signals are
kept away from the digital lines. This layout helps keep the analog input and reference input signals away
from the digital noise. In this layout example, the analog input and reference signals are routed on the lower
side of the board while the digital connections are routed on the top side of the board.
•
•
Using a single dedicated ground plane is strongly encouraged.
Power sources to the ADS8684 and ADS8688 must be clean and well-bypassed. TI recommends using a
1-μF, X7R-grade, 0603-size ceramic capacitor with at least a 10-V rating in close proximity to the analog
(AVDD) supply pins. For decoupling the digital (DVDD) supply pin, a 10-μF, X7R-grade, 0805-size ceramic
capacitor with at least a 10-V rating is recommended. Placing vias between the AVDD, DVDD pins and the
bypass capacitors must be avoided. All ground pins must be connected to the ground plane using short, low
impedance paths.
•
There are two decoupling capacitors used for REFCAP pin. The first is a small, 1-μF, X7R-grade, 0603-size
ceramic capacitor placed close to the device pins for decoupling the high-frequency signals and the second is
a 22-µF, X7R-grade, 1210-size ceramic capacitor to provide the charge required by the reference circuit of
the device. Both these capacitors must be directly connected to the device pins without any vias between the
pins and capacitors.
•
•
The REFIO pin also must be decoupled with a 10-µF ceramic capacitor, if the internal reference of the device
is used. The capacitor must be placed close to the device pins.
For the auxiliary channel, the fly-wheel RC filter components must be placed close to the device. Among
ceramic surface-mount capacitors, COG (NPO) ceramic capacitors provide the best capacitance precision.
The type of dielectric used in COG (NPO) ceramic capacitors provides the most stable electrical properties
over voltage, frequency, and temperature changes.
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11.2 Layout Example
Digital Pins
1: SDI
38: CS
37: SCLK
2: RST/PD
3: REFSEL
4: DAISY
5: REFIO
36: SDO
35: NC
DAISY
34: DVDD
10µF
10µF (When using internal VREF
)
6: REFGND
1µF
33: DGND
32: AGND
31: AGND
30: AVDD
GND
22µF
7: REFCAP
8: AGND
1µF
9: AVDD
1µF
10: AUX_IN
11: AUX_GND
12: AIN_6P
29: AGND
28: AGND
27: AIN_5P
26: AIN_5GND
25: AIN_4P
24: AIN_4GND
23: AIN_3P
22: AIN_3GND
21: AIN_2P
20: AIN_2GND
13: AIN_6GND
14: AIN_7P
Optional RC Filter for
Channel AIN_0 to AIN_7
15: AIN_7GND
16: AIN_0P
17: AIN_0GND
18: AIN_1P
19: AIN_1GND
Analog Pins
Figure 101. Board Layout for ADS8684 and ADS8688
56
版权 © 2014, Texas Instruments Incorporated
ADS8684, ADS8688
www.ti.com.cn
ZHCSCR1B –JULY 2014–REVISED AUGUST 2014
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档ꢀ
相关文档如下：
•
•
《TIPD167 验证设计参考指南：针对电力自动化的相位补偿 8 通道多路复用数据采集系统》，TIDU427
《TIDA-00164 验证设计参考指南：针对可编程逻辑控制器 (PLC)
块》，TIDU365
的
16
位
8
通道集成模拟输入模
•
•
•
•
《OPA320 数据表》，SBOS513
《REF5040 数据表》，SBOS410F
《AN-2029 - 处理和工艺建议》，SNOA550B
《LM5017 数据表》，SNVS783
12.2 相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
表 19. 相关链接
部件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
ADS8684
ADS8688
12.3 商标
SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
13 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2014, Texas Instruments Incorporated
57
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS8684IDBT
ADS8684IDBTR
ADS8688IDBT
ADS8688IDBTR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
DBT
DBT
DBT
DBT
38
38
38
38
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
ADS8684
2000 RoHS & Green
50 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
ADS8684
ADS8688
ADS8688
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS8684IDBTR
ADS8688IDBTR
TSSOP
TSSOP
DBT
DBT
38
38
2000
2000
330.0
330.0
16.4
16.4
6.9
6.9
10.2
10.2
1.8
1.8
12.0
12.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS8684IDBTR
ADS8688IDBTR
TSSOP
TSSOP
DBT
DBT
38
38
2000
2000
356.0
356.0
356.0
356.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ADS8684IDBT
ADS8688IDBT
DBT
DBT
TSSOP
TSSOP
38
38
50
50
530
530
10.2
10.2
3600
3600
3.5
3.5
Pack Materials-Page 3
PACKAGE OUTLINE
DBT0038A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SEATING
PLANE
6.55
6.25
TYP
C
A
0.1 C
PIN 1 INDEX AREA
38 X 0.5
38
1
2X
9
9.75
9.65
NOTE 3
19
B
20
0.23
38 X
0.17
4.45
1.2 MAX
0.1
C A B
4.35
NOTE 4
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
4220221/A 05/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DBT0038A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
38 X (1.5)
SYMM
(R0.05) TYP
38
1
38 X (0.3)
38 X (0.5)
SYMM
19
20
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220221/A 05/2020
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBT0038A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
38 X (1.5)
SYMM
(R0.05) TYP
38
1
38 X (0.3)
38 X (0.5)
SYMM
19
20
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220221/A 05/2020
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
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