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ADS9224R

ADS9234R

ZHCSIJ5C –AUGUST 2018–REVISED JUNE 2019

ADS92x4R 双通道低延迟同步采样 SAR ADC

1 特性

2 应用

1

•

高分辨率、高吞吐量：

•

光学编码器：增量和绝对编码器

声纳接收器

–

ADS9224R：16 位、3MSPS、低延迟：333ns

光纤网络：EDFA 增益控制环路

电源质量测量

ADS9234R：14 位、3.5MSPS、低延

迟：285ns

•

两个单极、完全差分同步采样通道

出色的直流和交流性能：

数字电源

I/Q 解调器

–

ADS9224R：

医疗成像：CT 扫描仪、MRI 扫描仪

阻抗分析仪

–

16 位 NMC DNL，±2LSB 最大 INL

94dB SNR、–109dB THD

1MHz 时为 88dB SINAD

3 说明

ADS92x4R 是一款引脚兼容型高速双通道同步采样模

数转换器 (ADC)，具有集成基准电压和基准电压缓冲

器。该器件可由 5V 单电源供电运行，支持单极和全差

分模拟输入信号，具有出色的直流和交流规格。该器件

具有高达 1.5MHz 的模拟输入频率，交流性能出色，

因此适合高带宽数据采集 (DAQ) 系统。

ADS9234R：

–

14 位 NMC DNL，±1LSB 最大 INL

85.6dB SNR、–106dB THD

1MHz 时为 84dB SINAD

•

特性集成：

–

内部基准和基准缓冲器

用于设置共模的内部 REFby2 缓冲器

该器件支持 SPI 兼容串行（增强型 SPI）和字节宽并

行接口，因此易于与多种微控制器、数字信号处理器

(DSP) 和现场可编程门阵列 (FPGA) 搭配使用。此器

件还支持数据平均功能，该功能可提升高噪声环境中的

交流性能。

数据平均

适用于 MCU 和 FPGA 的增强型 SPI 接口：

–

宽读取周期，可借助 MCU 读取数据

用于通过数字隔离器进行数据传输的时钟重计时

器

该器件采用节省空间的 5mm × 5mm VQFN 封装。

ADS92x4R 的额定扩展温度范围为 –40°C 至 +125°

C。

–

适用于 FPGA 的 DDR 模式

并行字节模式，方便对接

•

扩展温度范围：–40°C 至 +125°C

器件信息⁽¹⁾

器件型号

ADS92x4R

封装

VQFN (32)

封装尺寸（标称值）

5.00mm x 5.00mm

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

典型应用图

Absolute/Incremental Encoder

SONAR

Reference

Position

I

ADC

sine

0°

ADC

Baseband

Signal

Host

REF

Host

Encoder

Q

REF

cosine

90°

ADS92x4R

Local Oscillator

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBAS876

ADS9224R

ADS9234R

ZHCSIJ5C –AUGUST 2018–REVISED JUNE 2019

www.ti.com.cn

7.4 Device Functional Modes........................................ 26

7.5 READY/STROBE Output ........................................ 30

7.6 Programming........................................................... 30

7.7 Register Maps......................................................... 43

Application and Implementation ........................ 49

8.1 Application Information............................................ 49

8.2 Typical Application .................................................. 51

Power Supply Recommendations...................... 53

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics: ADS92x4R....................... 6

6.6 Electrical Characteristics: ADS9224R....................... 7

6.7 Electrical Characteristics: ADS9234R....................... 8

6.8 Timing Requirements................................................ 9

6.9 Switching Characteristics........................................ 10

6.10 Typical Characteristics: ADS9224R...................... 15

6.11 Typical Characteristics: ADS9234R...................... 18

Detailed Description ............................................ 21

7.1 Overview ................................................................. 21

7.2 Functional Block Diagram ....................................... 21

7.3 Feature Description................................................. 22

8

9

10 Layout................................................................... 54

10.1 Layout Guidelines ................................................. 54

10.2 Layout Example .................................................... 55

11 器件和文档支持 ..................................................... 56

11.1 器件支持................................................................ 56

11.2 相关文档................................................................ 56

11.3 相关链接................................................................ 56

11.4 接收文档更新通知 ................................................. 56

11.5 社区资源................................................................ 56

11.6 商标....................................................................... 56

11.7 静电放电警告......................................................... 56

11.8 Glossary................................................................ 56

12 机械、封装和可订购信息....................................... 57

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision B (May 2019) to Revision C

Page

•

已更改将文档状态从“预告信息”更改为“生产数据”.................................................................................................................. 1

2

ADS9224R

ADS9234R

www.ti.com.cn

ZHCSIJ5C –AUGUST 2018–REVISED JUNE 2019

5 Pin Configuration and Functions

RHB Package

5-mm × 5-mm, 32-Pin VQFN

Top View

AINP_A

AINM_A

REFby2

GND

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

SDO-0/0A

SDO-1/1A

SDO-2/2A

SDO-3/3A

SDO-4/0B

SDO-5/1B

SDO-6/2B

SDO-7/3B

Thermal

Pad

REFOUT

NC

AINM_B

AINP_B

Not to scale

Pin Functions

NAME

AINM_A

NO.

FUNCTION

Analog input

DESCRIPTION

2

7

1

8

Negative analog input for channel A.

Negative analog input for channel B.

Positive analog input for channel A.

Positive analog input for channel B.

AINM_B

AINP_A

AINP_B

Analog power-supply pin.

AVDD

CONVST

CS

12, 29

13

Power supply

Digital input

Power supply

Connect a 1-µF decoupling capacitor between pin 12 and pin 11.

Connect a 1-µF decoupling capacitor between pin 29 and pin 30.

Conversion start input pin.

A CONVST rising edge starts the conversion for ADC_A and ADC_B.

Chip-select input pin; active low.

The host and device can communicate when CS is low.

The SDO-x pins go to Hi-Z when CS is high.

14

Interface power-supply pin.

Connect a 1-µF decoupling capacitor between pin 27 and pin 28.

DVDD

28

GND

NC

4, 11, 27, 30

6

Power supply

—

Ground

No external connection

Asynchronous reset or power-down input pin.

See the Reset or Power-Down section.

PD/RST

26

25

Digital input

READY/STROBE

Digital output

Indicates data ready or strobe output for data capture.

3

ADS9224R

ADS9234R

ZHCSIJ5C –AUGUST 2018–REVISED JUNE 2019

www.ti.com.cn

Pin Functions (continued)

NAME

REFby2

NO.

FUNCTION

DESCRIPTION

REFby2 buffer output.

3

Analog output

Connect a 1-µF decoupling capacitor between pin 3 and pin 4.

Internal reference output.

REFOUT

REFM_A

5

Connect a 1-µF decoupling capacitor between pin 5 and pin 4.

Negative output of reference buffer A. Negative reference input for

ADC_A.

Externally connect to the device GND.

32

Analog output

Negative output of reference buffer B. Negative reference input for

ADC_B.

Externally connect to the device GND.

REFM_B

REFP_A

REFP_B

9

Positive output of reference buffer A. Positive reference input for

ADC_A.

Connect a 10-µF decoupling capacitor between pin 31 and pin 32.

31

10

Positive output of reference buffer B. Positive reference input for

ADC_B.

Connect a 10-µF decoupling capacitor between pin 9 and pin 10.

SCLK

SDI

16

15

Digital input

Clock input pin for the serial interface.

Serial data input pin.

This pin is used to program the device registers.

SPI mode: data output 0 for channel A.

Parallel byte mode: least significant bit (LSB) from the data byte.

SDO-0/0A

SDO-1/1A

SDO-2/2A

SDO-3/3A

SDO-4/0B

SDO-5/1B

SDO-6/2B

SDO-7/3B

Thermal pad

24

23

22

21

20

19

18

17

Digital output

Power supply

SPI mode: data output 1 for channel A.

Parallel byte mode: LSB+1 from the data byte.

SPI mode: data output 2 for channel A.

Parallel byte mode: LSB+2 from the data byte.

SPI mode: data output 3 for channel A.

Parallel byte mode: LSB+3 from the data byte.

SPI mode: data output 0 for channel B.

Parallel byte mode: LSB+4 from the data byte.

SPI mode: data output 1 for channel B.

Parallel byte mode: LSB+5 from the data byte.

SPI mode: data output 2 for channel B.

Parallel byte mode: LSB+6 from the data byte.

SPI mode: data output 3 for channel B.

Parallel byte mode: most significant bit (MSB) from the data byte.

Exposed thermal pad. TI recommends connecting this pin to the printed

circuit board (PCB) ground.

4

ADS9224R

ADS9234R

www.ti.com.cn

ZHCSIJ5C –AUGUST 2018–REVISED JUNE 2019

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

6

UNIT

V

AVDD to GND

DVDD to GND

–0.3

6

V

Digital input pins

GND – 0.3

–0.3

DVDD + 0.3

AVDD + 0.3

GND + 0.1

AVDD + 0.3

10

V

Digital output pins

V

AINP_A, AINP_B to GND, AINM_A, AINM_B to GND

REFM_A, REFM_B

V

GND – 0.1

GND – 0.3

–10

V

REFP_A, REFP_B, REFOUT, REFby2 to GND

Input or output current to any pin except power-supply pin

Junction temperature, T_J

V

mA

°C

150

Storage temperature, T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per

±2000

ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

NOM

5

MAX

5.5

UNIT

V

AVDD

DVDD

T_A

Analog supply voltage

Digital supply voltage operating range

Digital supply voltage for SCLK > 20 MHz

Ambient temperature

1.65

2.35

–40

3.3

5.5

V

5.5

V

125

°C

6.4 Thermal Information

ADS92x4R

THERMAL METRIC⁽¹⁾

RHB (VQFN)

UNIT

32 PINS

29

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

17.1

9.4

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

Ψ_JB

9.4

R_θJC(bot)

0.8

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

5

ADS9224R

ADS9234R

ZHCSIJ5C –AUGUST 2018–REVISED JUNE 2019

www.ti.com.cn

6.5 Electrical Characteristics: ADS92x4R

at AVDD = 4.5 V to 5.5V, DVDD = 2.35 V to 5.5 V, V_CM= V_{REFP_x/2}, Internal reference and maximum throughput (unless

otherwise noted); minimum and maximum values at T_A= -40℃ to +125℃; typical values at T_A= 25℃, AVDD = 5V, DVDD =

3.3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUT

Full-scale input voltage (AINP_x -

AINM_x)

FSR⁽¹⁾

-4.096

4.096

V

Absolute input voltage (AINP_x or

AINM_x to GND)

V_IN

0

4.096

2.248

V_CM

I_IN

Common-mode input range

Analog input leakage current

1.848

V

±1

16

1

µA

Sample mode

C_i

Input capacitance

pF

Hold mode

-3-dB input signal

-0.1-dB input signal

52

4.2

MHz

BW

Analog input bandwidth

VOLTAGE REFERENCE OUTPUT

(2)

V_REFOUT

REFOUT voltage

V_REFOUTdrift

2.496

2.5

5.5

2.504

15

V

ΔV_REF/ΔT

ppm/°C

ΔV_REFOUT/ΔAVD

D

AVDD variation 4.5 V to

5.5 V

V_REFOUTline regulation

REFOUT output current capability

REFOUT capacitor

200

1.5

1

µV/V

µA

I_REFOUT

|ΔV_REF| < 2 mV

For specified

performance

C_REFOUT

µF

INTERNAL REFERENCE BUFFER

G_REFBUF

Reference buffer Gain

1.6388

±0.2

V/V

mV

E_O-REFBUF

Reference buffer output offset

–1

1

Reference buffer output offset

temperature drift

ΔE_O-REFBUF/ΔT

10

µV/℃

(V_{REFP_A}

V_{REFP_B}

-

Reference buffer output mismatch

–500

7

±50

500

27

µV

)

For specified

performance, between

each pair of REFP_x

and REFM_x

C_{REFP_x}

Reference buffer output capacitor

10

µF

REFby2 OUTPUT

V_REFby2

EN_REFBY2_OFFSET

= 0

2.043

2.133

2.048

2.053

2.163

V

REFby2 output voltage

EN_REFBY2_OFFSET

= 1

2.148

±3

I_REFby2

REFby2 output current capability

REFby2 output capacitor

mA

µF

1

With specified output

capacitor

REFby2 output noise

10

µV_RMS

Digital Outputs

V_OH

High level output voltage

Low level output voltage

I_OH= 500-µA source

I_OL= 500-µA sink

0.8 × DVDD

0

DVDD

V

V_OL

0.2 × DVDD

Digital Inputs

V_IH

V_IL

V_IH

V_IL

High level input voltage

Low level intput voltage

High level input voltage

Low level intput voltage

0.7 × DVDD

–0.3

DVDD +0.3

0.3 × DVDD

DVDD +0.3

0.2 × DVDD

V

DVDD > 2.3 V

0.8 × DVDD

–0.3

DVDD ≤ 2.3 V

(1) Ideal input span; does not include gain or offset error.

(2) Does not include the variation in voltage resulting from solder shift effects.

6

ADS9224R

ADS9234R

www.ti.com.cn

ZHCSIJ5C –AUGUST 2018–REVISED JUNE 2019

Electrical Characteristics: ADS92x4R (continued)

at AVDD = 4.5 V to 5.5V, DVDD = 2.35 V to 5.5 V, V_CM= V_{REFP_x/2}, Internal reference and maximum throughput (unless

otherwise noted); minimum and maximum values at T_A= -40℃ to +125℃; typical values at T_A= 25℃, AVDD = 5V, DVDD =

3.3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power Supply

AVDD

Analog supply voltage

Digital supply voltage

4.5

5

3.3

5.5

V

DVDD

1.65

f_SAMPLE= 3 MSPS

24.3

30.4

mA

AVDD = 5 V, no

conversion

7.8

1

mA

µA

I_AVDD

Analog supply current

Power down (PD/RST

Low)

f_SAMPLE= 3 MSPS,

C_SDO-x/y= 10 pF

I_DVDD

Digital supply current

2.8

mA

100-mV_PPRipple on

AVDD of frequency <

100kHz

PSRR⁽³⁾

Power-supply rejection ratio

70

dB

(3) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-

scale, unless otherwise specified.

6.6 Electrical Characteristics: ADS9224R

at AVDD = 4.5 V to 5.5V, DVDD = 2.35 V to 5.5 V, V_CM= V_{REFP_x/2}, Internal reference and maximum throughput (unless

otherwise noted); minimum and maximum values at T_A= -40℃ to +125℃; typical values at T_A= 25℃, AVDD = 5V, DVDD =

3.3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

DC ACCURACY

Resolution, no missing codes

Differential nonlinearity

Integral nonlinearity

Offset error

16

–0.5

–2

Bits

DNL

INL

E_O

±0.2

±1

0.5

2

LSB

–9

±1

9

Cummulative gain error for ADC_x and

REFBUF_x

G_E

–0.02

±0.01

0.02 %FSR

ΔG_E/ΔT

Gain drift

5

ppm/°C

LSB

Transition noise

Mid-code, PFS-1000, NFS+1000

0.4

AC ACCURACY

f_IN= 2 kHz

91.3

94.5

93

f_IN= 100 kHz, FSR = -3 dBFS

SNR⁽¹⁾

Signal-to-noise ratio

dB

f_IN= 1 MHz, FSR = -3 dBFS, f_SAMPLE

2.9 MSPS

=

89.5

f_IN= 2 kHz

94.3

92.7

87.9

–109

–106

-93

SINAD⁽¹⁾⁽²⁾

Signal-to-noise plus distortion

Total harmonic distortion

f_IN= 100 kHz, FSR = -3 dBFS

f_IN= 1 MHz, FSR = -3 dBFS

f_IN= 2 kHz

dB

THD⁽¹⁾⁽²⁾

f_IN= 100 kHz, FSR = -3 dBFS

f_IN= 1 MHz, FSR = -3 dBFS

f_IN= 2 kHz

112

100

80

SFDR⁽¹⁾

CMRR⁽¹⁾

Spurious-free dynamic range

Common-mode rejection ratio

f_IN= 100 kHz, FSR = -3 dBFS

f_IN= 1 MHz, FSR = -3 dBFS

f_IN= dc to 1-MHz, V_IN= 100-mV_PP

dB

(1) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-

scale, unless otherwise specified.

(2) Calculated on the first nine harmonics of the input frequency.

7

ADS9224R

ADS9234R

ZHCSIJ5C –AUGUST 2018–REVISED JUNE 2019

www.ti.com.cn

Electrical Characteristics: ADS9224R (continued)

at AVDD = 4.5 V to 5.5V, DVDD = 2.35 V to 5.5 V, V_CM= V_{REFP_x/2}, Internal reference and maximum throughput (unless

otherwise noted); minimum and maximum values at T_A= -40℃ to +125℃; typical values at T_A= 25℃, AVDD = 5V, DVDD =

3.3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

f_{IN_ADCA}= 15 kHz at 10% FSR,

f_{IN_ADCB}= 25 kHz at 100% FSR

ISOXT⁽¹⁾

Channel-to-channel isolation

–120

dB

6.7 Electrical Characteristics: ADS9234R

at AVDD = 4.5 V to 5.5V, DVDD = 2.35 V to 5.5 V, V_CM= V_{REFP_x/2}, Internal reference and maximum throughput (unless

otherwise noted); minimum and maximum values at T_A= -40℃ to +125℃; typical values at T_A= 25℃, AVDD = 5V, DVDD =

3.3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

DC ACCURACY

Resolution, no missing codes

Differential nonlinearity

Integral nonlinearity

Offset error

14

–0.5

–1

Bits

DNL

INL

E_O

±0.15

±0.3

±0.8

0.5

1

LSB

–3.5

3.5

Cummulative gain error for ADC_x and

REFBUF_x

G_E

–0.025

±0.01

0.025 %FSR

ΔG_E/ΔT

Gain drift

5

ppm/°C

LSB

Transition noise

Mid-code, PFS-1000, NFS+1000

0.3

AC ACCURACY

f_IN= 2 kHz

84.1

85.6

85.5

85

SNR⁽¹⁾

Signal-to-noise ratio

f_IN= 100 kHz, FSR = -3 dBFS

f_IN= 1 MHz, FSR = -3 dBFS

f_IN= 2 kHz

dB

85.5

85.4

84.4

–106

–94

109

107

101

75

SINAD⁽¹⁾⁽²⁾

THD⁽¹⁾⁽²⁾

SFDR⁽¹⁾

Signal-to-noise plus distortion

Total harmonic distortion

Spurious-free dynamic range

f_IN= 100 kHz, FSR = -3 dBFS

f_IN= 1 MHz, FSR = -3 dBFS

f_IN= 2 kHz

f_IN= 100 kHz, FSR = -3 dBFS

f_IN= 1 MHz, FSR = -3 dBFS

f_IN= 2 kHz

f_IN= 100 kHz, FSR = -3 dBFS

f_IN= 1 MHz, FSR = -3 dBFS

f_IN= dc to 1-MHz, V_IN= 100-mV_PP

CMRR⁽¹⁾

ISOXT⁽¹⁾

Common-mode rejection ratio

Channel-to-channel isolation

dB

f_{IN_ADCA}= 15 kHz at 10% FSR,

f_{IN_ADCB}= 25 kHz at 100% FSR

–115

(1) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-

scale, unless otherwise specified.

(2) Calculated on the first nine harmonics of the input frequency.

8

ADS9224R

ADS9234R

www.ti.com.cn

ZHCSIJ5C –AUGUST 2018–REVISED JUNE 2019

6.8 Timing Requirements

at AVDD = 4.5 V to 5.5V, DVDD = 2.35 V to 5.5 V, V_CM= V_{REFP_x/2}, Internal reference and maximum throughput (unless

otherwise noted); minimum and maximum values at T_A= -40℃ to +125℃; typical values at T_A= 25℃, AVDD = 5V, DVDD =

3.3 V

MIN

NOM

MAX UNIT

CONVERSION CONTROL AND DATA TRANSFER (See 图 1 and 图 2)

Delay time: CONVST high to CS Falling for zero cycle latency (zone

(1)

t_{D_CONVST_CS}

1 transfer)

t_DRDY

ns

Time between two adjacent CONVST rising edges for zero cycle

latency (zone 1 transfer)

(2)

t_DRDY+t_READ

Time between two adjacent CONVST rising edges for zone 2

transfer, ADS9224R

t_CYCLE

333

285

ns

Time between two adjacent CONVST rising edges for zone 2

transfer, ADS9234R

Sampling rate, ADS9224R

f_SAMPLE

3

MSPS

3.5

Sampling rate, ADS9234R

t_ACQ

Acquisition time

140

15

ns

t_{D_CONVST_CS}Delay time: CONVST high to CS falling for zone 2 transfer

180

ns

t_{WL_CONVST}

t_{WH_CONVST}

Pulse duration : CONVST low

Pulse duration : CONVST high

15

SPI-COMPATIBLE AND PARALLEL BYTE PROTOCOL (See 图 3)

t_CLK

Serial clock time period

1/ f_CLK

0.45 × t_CLK

12

t_{PH_CLK}

t_{PL_CLK}

t_{SU_CSCK}

t_{SU_CKDI}

t_{HT_CKDI}

t_{HT_CKCS}

SCLK high time

0.55 × t_CLK

ns

SCLK low time

Setup time: CS faling to first SCLK capture edge

Setup Time: SDI data valid to SCLK capture edge

Hold Time: SCLK capture edge to previous data valid on SDI

Delay Time: last SCLK capture edge to CS rising

Serial clock frequency for SPI protocols with single data rate

Serial clock frequency for SPI protocols with double data rate

Serial clock frequency for parallel byte protocol

2.5

1.5

14

60 MHz

22 MHz

45 MHz

f_CLK

CLOCK RE-TIMER PROTOCOL WITH STROBE = SCLK (EXTERNAL CLOCK)⁽³⁾(See 图 4)

Serial clock frequency with single data rate

60 MHz

22 MHz

f_CLK

Serial clock frequency with double data rate

ASYNCHRONOUS RESET AND POWER-DOWN TIMING (See 图 6)

t_WL-RST

Pulse duration (low) for reset

50

500

ns

t_WL-PD-min

Minimum pulse duration (low) for power-down

1000

(1) See Switching Characteristics

(2) See Protocols for Reading From the Device for t_READ

(3) Other parameters are the same as the SPI-compatible and Parallel Byte Protocols.

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6.9 Switching Characteristics

at AVDD = 4.5 V to 5.5V, DVDD = 2.35 V to 5.5 V, V_CM= V_REF/2, Internal reference and maximum throughput (unless

otherwise noted); minimum and maximum values at T_A= -40℃ to +125℃; typical values at T_A= 25℃, AVDD = 5V, DVDD =

3.3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

CONVERSION CONTROL AND DATA TRANSFER (See 图 1 and 图 2)

Data ready time for present

sample: CONVST high to

READY high

Zero cycle latency (zone 1

transfer) for ADS9224R

315

280

ns

t_DRDY

Data ready time for present

sample: CONVST high to

READY high

Zero cycle latency (zone 1

transfer) for ADS9234R

SPI-COMPATIBLE AND PARALLEL BYTE PROTOCOL (See 图 3)

Delay time: CS falling to

t_{DEN_CSDO}

12

ns

data valid on SDO-x

Delay time: CS rising edge

t_{DZ_CSDO}

to SDO-x tristate

Delay time: SCLK launch

edge to next data valid on

SDO-x

SPI-compatible protocols with

single data rate

t_{D_CKDO}

15.8

21

ns

Delay time: SCLK launch

edge to next data valid on

SDO-x

SPI-compatible protocols with

double data rate

Delay time: SCLK launch

edge to next data valid on

SDO-x

Parallel byte protocol

21

Aperture delay

t_Amismatch

8

40

2

ns

ps

t_A

t_JITTER

Aperture jitter

CLOCK RE-TIMER PROTOCOL WITH STROBE = SCLK (EXTERNAL CLOCK)⁽¹⁾(See 图 4)

Time offset: STROBE edge

t_{OFF_STROBE_DO}

-2.5

2.5

ns

to next data valid on SDO-x

Delay time: CS rising to

t_{D_CS_READY}

READY displaying internal

device state

13.5

Delay time: SCLK rising

edge to STROBE rising

t_{D_CKSTROBE_r}

t_{D_CKSTROBE_f}

21.5

ns

Delay time: SCLK falling

edge to STROBE falling

t_{PH_STROBE}

t_{PL_STROBE}

Strobe output high time

Strobe output low time

0.45 × t_STR

0.55 × t_STR

ns

CLOCK RE-TIMER PROTOCOL WITH STROBE = INTERNAL CLOCK ⁽¹⁾(See 图 5)

Delay time : CS falling to

t_{D_CS_STROBE}

15

50

ns

1^stSTROBE rising

Time offset : STROBE

t_{OFF_STROBE_DO}

edge to next data valid on

SDO-x

-2.5

2.5

Delay time: CS rising to

READY displaying internal

device state

t_{D_CS_READY}

t_INTCLK

13.5

ns

INTCLK period

15

16

30

60

ns

INTCLK

t_STR

STROBE period

INTCLK / 2

INTCLK / 4

t_{WH_STR}

t_{WL_STR}

STROBE high period

STROBE low period

0.45 × t_STR

0.55 × t_STR

(1) Other parameters are the same as the SPI-compatible and Parallel Byte Protocols.

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Switching Characteristics (continued)

at AVDD = 4.5 V to 5.5V, DVDD = 2.35 V to 5.5 V, V_CM= V_REF/2, Internal reference and maximum throughput (unless

otherwise noted); minimum and maximum values at T_A= -40℃ to +125℃; typical values at T_A= 25℃, AVDD = 5V, DVDD =

3.3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

ASYNCHRONOUS RESET AND POWER-DOWN TIMING (See 图 6)

t_RST-WKUP

Wake up time from reset

1

150

140

150

µs

ms

Wake up time from power-

down

(2)

t_PD-WKUP

18

15.6

18

t_WKUP-REFOUT

t_{REFP_x-SETTLE}

REFOUT wake-up time

Reference buffer output

settling time

C_{REFP_x}= 10µF

(2) With C_{REFP_x}= 10µF

Sample

”N+1‘

Sample

”N‘

t_cycle

t_{WH_CONVST}

t_{WL_CONVST}

CONVST

t_{D_CONVST_CS}

t_READ

CS

t_{D_CONVST_CS-min}

READY/STROBE⁽¹⁾

t_DRDY

t_ACQ

ADCST

Acquisition of Sample ”N+1‘

(Internal)

SCLK

Output Data

Sample ”N‘

SDO-xx

Zone 1

(1) The READY output is required for data transfer with zero cycle latency. The STROBE output is required only for clock

re-timer (CRT) protocols.

图 1. Conversion Control and Data Transfer With Zero Cycle Latency (Zone 1 Transfer)

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Sample

”N‘

Sample

”N+1‘

t_CYCLE

t_{WH_CONVST}

t_{WL_CONVST}

CONVST

t_{D_CONVST_CS}

t_READ

CS

t_{D_CONVST_CS-min}

t_{D_CONVST_CS-max}

t_READ-max

ADCST

t_ACQ

Acquisition of

(Internal)

Sample ”N+1‘

SCLK

READY/STROBE⁽¹⁾

SDO-xx

Output Data

Sample ”N-1‘

Zone 2

(1) The READY output is not required for zone 2 data transfer. The STROBE output is required only for clock re-timer

protocols.

图 2. Conversion Control and Data Transfer With Wider Read Cycle (Zone 2 Transfer)

t_CLK

t_{PH_CLK}

t_{PL_CLK}

CS

SCLK⁽¹⁾

t_{SU_CKDI}

t_{HT_CKDI}

t_{SU_CSCK}

t_{HT_CKCS}

SCLK⁽¹⁾

SDI

t_{D_CKDO}

SDO-x

(SDR)

t_{D_CKDO}

t_{DEN_CSDO}

t_{DZ_CSDO}

t_{D_CKDO}

SDO-x

(DDR)

SDO-x

(1) The SCLK polarity, launch edge, and capture edge depend on the SPI protocol selected. DDR is not supported with

the parallel byte protocol.

图 3. SPI-Compatible and Parallel Byte Protocols Timing

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t_CLK

t_{PH_CK}

t_{PL_CK}

CS

SCLK

t_{D_CKSTROBE_f}

t_{D_CKSTROBE_r}

t_{SU_CSCK}

t_{HT_CKCS}

READY/

STROBE

SCLK

t_{OFF_STROBE_DO}

t_{DEN_CSDO}

t_{DZ_CSDO}

t_{OFF_STROBE_DO}

SDO-x

(DDR)

SDO-x

t_{D_CS_READY}

t_{OFF_STROBE_DO}

READY/

STROBE

SDO-x

(SDR)

图 4. Clock Re-Timer Protocol (External Clock) Timing

t_STR

READY/

STROBE

CS

t_{PH_STROBE}

t_{PL_STROBE}

t_{OFF_STROBE_DO}

t_{DEN_CSDO}

t_{DZ_CSDO}

t_{OFF_STROBE_DO}

SDO-x

(DDR)

SDO-x

t_{D_CS_READY}

t_{OFF_STROBE_DO}

SDO-x

(SDR)

READY/

STROBE

t_{D_CS_STROBE}

图 5. Clock Re-Timer Protocol (Internal Clock) Timing

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t_WL-RST-max

t_WL-RST

t_WL-RST-min

t_WL-PD

RST/PD

Device in

Acquisition

Device in

Acquisition

ADCST(internal)

t_RST-WKUP

t_PD-WKUP

Reset

Power Down

图 6. Asynchronous Reset and Power-Down Timing

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6.10 Typical Characteristics: ADS9224R

0

-20

0

-40

-60

-80

-100

-120

-140

-160

-180

-120

-160

-200

0

400000

800000

1200000

1600000

0

300000

600000

900000

1200000

1500000

f_IN, Input Frequency (Hz)

9224

f_IN= 100 kHz, SNR = 93.6 dB, THD = –107 dB

f_IN= 1 MHz, SNR = 90.65 dB, THD = –94.5 dB

图 7. Typical FFT at f_IN= 100 kHz

图 8. Typical FFT at f_IN= 1 MHz

95.5

95

96

94.5

93

SNR (dB)

SINAD (dB)

SNR (dB)

SINAD (dB)

94.5

94

91.5

90

93.5

93

88.5

-60

-30

0

30

60

90

120

150

0

200

400

600

800

1000

1200

1400

Free-Air Temperature (èC)

f_IN, Input Frequency (KHz)

9224

f_IN= 2 kHz

图 9. Noise Performance vs Temperature

图 10. Noise Performance vs Frequency

-104

-90

-95

-106

-108

-110

-112

-114

-100

-105

-110

-115

-60

-30

0

30

60

90

120

150

0

200

400

600

800

1000

1200

1400

Free-Air Temperature (èC)

f_IN, Input Frequency (KHz)

9224

f_IN= 2 kHz

图 11. Distortion Performance vs Temperature

图 12. Distortion Performance vs Frequency

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Typical Characteristics: ADS9224R (接下页)

1.6

0.003

0.0015

0

0.8

0

-0.0015

-0.003

-0.0045

-0.8

-1.6

-2.4

-60

-30

0

30

60

90

120

150

-60

-30

0

30

60

90

120

150

Free- Air Temperature (èC)

Free-Air Temperature (èC)

9224

图 14. Gain Error vs Temperature

图 13. Offset Error vs Temperature

0.75

0.5

64000

56000

48000

40000

32000

24000

16000

8000

48689

0.25

0

16364

-0.25

-0.5

480

0

2

0

32765

32767.5

32770

32772.5

32775

0

13107

26214

ADC output code

39321

52428

65535

9224

Output Codes

9224

Standard deviation = 0.44 LSB

Typical DNL = ±0.2 LSB

图 15. DC Input Histogram

图 16. Typical DNL

1

0.6

0.2

-0.2

-0.6

-1

0.3

0.25

0.2

0.15

0.1

Maximum

Minimum

0.05

0

-0.05

-0.1

-0.15

-0.2

-0.25

-0.3

0

13107

26214

39321

52428

65535

-40

-20

0

20

40

60

80

100 120 140

ADC output code

Free-Air Temperature (èC)

9224

Typical INL = ±0.5 LSB

图 17. Typical INL

图 18. DNL vs Temperature

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Typical Characteristics: ADS9224R (接下页)

3

2.504

2.502

2.5

Maximum

Minimum

2

1

0

2.498

2.496

2.494

-1

-2

-60

-30

0

30

60

90

120

150

-60

-30

0

30

60

90

120

150

Free-Air Temperature (èC)

9224

图 19. INL vs Temperature

图 20. V_REFOUTvs Temperature

26

24

22

20

18

16

14

12

10

8

24.9

24.8

24.7

24.6

24.5

24.4

24.3

24.2

24.1

24

Dynamic I_AVDD(mA)

Static I_AVDD(mA)

6

23.9

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Free-Air Temperature (èC)

9244

9234

图 21. AVDD Current vs Temperature

图 22. AVDD Current vs Temperature

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6.11 Typical Characteristics: ADS9234R

0

-20

0

-40

-60

-80

-100

-120

-140

-160

-180

-120

-160

-200

0

400000

800000

1200000

1600000

0

300000 600000 900000 1200000 1500000 1800000

f_IN, Input Frequency (Hz)

9234

f_IN= 100 kHz, SNR = 85.5 dB, THD = –106 dB

f_IN= 1 MHz, SNR = 85.2 dB, THD = –94 dB

图 23. Typical FFT at f_IN= 100 kHz

图 24. Typical FFT at f_IN= 1 MHz

86.4

86

86.5

86

SNR (dB)

SINAD (dB)

SNR (dB)

SINAD (dB)

85.6

85.2

84.8

84.4

85.5

85

84.5

84

-60

-30

0

30

60

90

120

150

0

200

400

600

800

1000

1200

1400

Free-Air Temperature (èC)

f_IN, Input Frequency (KHz)

9234

f_IN= 2 kHz

图 25. Noise Performance vs Temperature

图 26. Noise Performance vs Frequency

-100

-85

-90

-102.5

-105

-95

-107.5

-110

-100

-105

-110

-112.5

-60

-30

0

30

60

90

120

150

0

200

400

600

800

1000

1200

1400

Free-Air Temperature (èC)

f_IN, Input Frequency (KHz)

9234

f_IN= 2 kHz

图 27. Distortion Performance vs Temperature

图 28. Distortion Performance vs Frequency

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Typical Characteristics: ADS9234R (接下页)

0.4

0.002

0.0015

0.001

0.0005

0

0.3

0.2

0.1

0

-0.0005

-0.1

-60

-30

0

30

60

90

120

150

-60

-30

0

30

60

90

120

150

Free-Air Temperature (èC)

9234

图 30. Gain Error vs Temperature

图 29. Offset Error vs Temperature

0.4

0.2

0

17500

15000

12500

10000

7500

5000

2500

0

-0.2

-0.4

0

15

0

3000

6000

ADC output code

9000

12000

15000

8189

8190

8191

8192

8193

8194

8195

8196

9234

ADC Output Code

Typical DNL = ±0.15 LSB

Standard deviation = 0.44 LSB

图 32. Typical DNL

图 31. DC Input Histogram

0.5

0.3

0.45

0.3

Maximum

Minimum

0.1

0.15

0

-0.1

-0.3

-0.5

-0.15

-0.3

0

3000

6000

9000

12000

15000

-60

-30

0

30

60

90

120

150

ADC Output Code

Free-Air Temperature (èC)

9234

Typical INL = ±0.25 LSB

图 33. Typical INL

图 34. DNL vs Temperature

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Typical Characteristics: ADS9234R (接下页)

0.9

Maximum

Minimum

0.6

0.3

0

-0.3

-0.6

-60

-30

0

30

60

90

120

150

Free-Air Temperature (èC)

9234

图 35. INL vs Temperature

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7 Detailed Description

7.1 Overview

The device belongs to a family of dual, high-speed, simultaneous-sampling, analog-to-digital converters (ADCs).

The device supports fully differential input signals and a full-scale input range equal to 2 × V_{REFP_x}

.

When a conversion is initiated, the difference voltage between the AINP_x and AINM_x pins is sampled on the

internal capacitor array. The device uses an internal clock to perform conversions. During the conversion

process, both analog inputs are disconnected from the sampling capacitors. At the end of conversion process,

the device reconnects the sampling capacitors to the AINP_x and AINM_x pins and enters an acquisition phase.

The device has internal reference and reference buffers to provide the charge required by the ADCs during

conversion. The device includes a reference voltage for the ADCs.

The enhanced serial programming interface (eSPI) digital interface is backward-compatible with traditional SPI

protocols. eSPI configurable features simplify board layout, timing, and firmware and support high throughput at

lower clock speeds, thus allowing an easy interface with a variety of microcontrollers, digital signal processors

(DSPs), and field-programmable gate arrays (FPGAs). The device also provides a byte mode and a wide read

cycle to reduce the clock frequency required for data transfer. The device includes a clock re-timer (CRT) to

ensure data integrity when data are transferred through digital isolators. The device also supports double data

rate (DDR) with SPI-compatible serial interface modes and with a clock re-timer.

7.2 Functional Block Diagram

REFM_A

REFP_A

DVDD

AVDD

REFOUT

REFby2

AVDD

REFby2

AVDD

Reference

Voltage

2.5 V

REFBUF_A

CONVST

CS

AINP_A

AINM_A

ADC_A

SCLK

SDI

AVDD

Serial

Interface

AINP_B

AINM_B

READY/STROBE

ADC_B

SDO-x/y

AVDD

REFBUF_B

REFOUT

REFM_B

REFP_B

GND

PD/RST

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7.3 Feature Description

The device is comprised of seven modules: two converters (ADC_A, ADC_B), two reference buffers

(REFBUF_A, REFBUF_B), the REFby2 buffer, the reference voltage, and the serial interface, as shown in the

Functional Block Diagram section.

The converter module samples and converts the analog input into an equivalent digital output code. The

reference buffers provide the charge required by the converters for the conversion process. The serial interface

module facilitates communication and data transfer between the device and the host controller. The REFby2

buffer provides the common-mode voltage for the amplifiers input driving the analog of the device. The reference

voltage is used by the converters for conversion process.

7.3.1 Converter Modules

As shown in 图 36, both converter modules sample the analog input signal, compare this signal with the

reference voltage (between the pair of REFP_x and REFM_x pins), and generate an equivalent digital output

code. The converter module receives the PD/RST and CONVST inputs from the interface module, and output the

ADCST signal and the conversion result back to the interface module.

REFP_x

DVDD

AVDD

PD/RST

CONVST

CS

OSC

RST

SCLK

AINP_x

AINM_x

CONVST

ADCST

Sample-

and-Hold

Circuit

SDI

Serial

Interface

SDO-x/y

Conversion

Result

SDO-x/y

AGND

READY/STROBE

ADC_A

ADC_B

GND

REFM_x

图 36. Converter Modules

7.3.1.1 Analog Input With Sample-and-Hold

This device supports unipolar, fully differential, analog input signals. 图 37 shows a small-signal equivalent circuit

of the sample-and-hold circuit. Each sampling switch is represented by a resistance (R_S1and R_S2, typically 120

Ω) in series with an ideal switch (SW₁and SW₂). The sampling capacitors, C_S1and C_S2, are typically 16 pF.

R_S1

SW₁

AINP_x

1 pF

C_S1

AVDD

C_S2

GND

R_S2

SW₂

AINM_x

Device in Hold Mode

图 37. Analog Input Structure for Converter Module

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Feature Description (接下页)

During the acquisition process, both inputs are individually sampled on C_S1and C_S2, respectively. During the

conversion process, both converters convert for the respective voltage difference between the sampled values:

V_{AINP_x}– V_{AINM_x}

.

公式 1 and 公式 2 provide the full-scale input range (FSR) and common-mode voltage (V_CM), supported at the

analog inputs for reference voltage (V_REFOUT) on the REFOUT pin.

FSR = ±1.6384 × V_REFOUT= 3.2768 × V_REFOUT

V_CM= 0.8192 × V_REFOUT± 0 .2 V

(1)

(2)

7.3.1.2 ADC Transfer Function

The device output is in two's compliment format. 表 1 and 图 38 show the ideal transfer characteristics for the

device. 公式 3 gives the least significant bit (LSB) for the ADC.

1 LSB = FSR / 2^R

where

•

FSR is defined in 公式 1

R = Resolution of the device

(3)

PFSC

MC

NFSC

A

B

C

V_IN

Analog Input

(AINP_x œ AINM_x)

图 38. Ideal Transfer Characteristics

表 1. Transfer Characteristics

INPUT VOLTAGE

(AINP_x-AINM_x)

IDEAL OUTPUT CODE IDEAL OUTPUT CODE

STEP

CODE

DESCRIPTION

(R = 16)

(R = 14)

A

B

C

≤ –(1.6384 × V_REFOUT– 1 LSB)

0 LSB to 1 LSB

NFSC

MC

Negative full-scale code

Mid code

8000

2000

0000

≥ (1.6384 × V_REFOUT– 1 LSB)

PFSC

Positive full-scale code

7FFF

1FFF

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7.3.2 Internal Reference Voltage

The device features an internal reference source with a nominal output value of 2.5 V. The ADC internal

reference voltage is brought out on the REFOUT pin. A 1-µF decoupling capacitor (C_REFOUT), as shown in 图 39,

is recommended to be placed between the REFOUT pin and GND pin. The capacitor must be placed as close to

the REFOUT pin as possible. The output impedance of the internal band-gap circuit creates a low-pass filter with

this capacitor to band-limit the noise of the reference. The initial accuracy specification for the internal reference

can be degraded if the die is exposed to any mechanical or thermal stress. Heating the device when being

soldered to a printed circuit board (PCB) and any subsequent solder reflow is a primary cause for shifts in the

V_REFvalue.

All performance characteristics of the device are specified with the internal reference buffer and a specified value

of C_{REFP_x}. As shown in 图 39, place a decoupling capacitor C_{REFP_x}between the REFP_x and REFM_x pins as

close to the device as possible.

AVDD

G_REFBUF

Internal

V_REF

2.5 V

œ

REFP_x

REFBUF_x

REFOUT

+

C_REFOUT

C_{REFP_x}

REFM_x

GND

图 39. Connection Diagram for Reference and Reference Buffers

7.3.3 Reference Buffers

On the CONVST rising edge, both converters start converting the sampled value on the analog input, and the

internal capacitors are switched to the REFP_x pins. Most of the switching charge required during the conversion

process is provided by the external decoupling capacitor C_{REFP_x}. If the charge lost from C_{REFP_x}is not

replenished before the next CONVST rising edge, the subsequent conversion occurs with this different reference

voltage and causes a proportional error in the output code. To eliminate these errors, the internal reference

buffers of the device maintains the voltage on the REFP_x pins. The reference buffers have a gain of G_REFBUF

as specified in the Specifications section. The voltage at the REFP_x pins can be calculated as V_{REFP_x}

G_REFBUF× V_REFOUT

,

=

.

7.3.4 REFby2 Buffer

The device includes a REFby2 buffer for setting the common-mode voltage required by the converter modules.

The REFby2 output can be used to drive the V_OCMcommon-mode input pin of the fully differential amplifiers

(similar to the THS4551). The REFby2 output can be increased by 100 mV (for specifications of the REFby2

output, see the Specifications section) for providing headroom from GND for the fully differential amplifier. To

increase the REFby2 output, set the EN_REFby2_OFFSET bit to 1 in the REFby2_OFFSET register. 图 40

depicts a block diagram for the REFby2 buffer.

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AVDD

REFP_A

REFby2 with EN_REFby2_OFFSET = 1

100 mV

œ

R

REFby2

REFby2 with EN_REFby2_OFFSET = 0

+

V_{REFP_A}/2

C_REFby2

EN_REFby2_

OFFSET

REFM_A

GND

图 40. REFby2 Buffer

7.3.5 Data Averaging

The device can be configured to average two or four samples and provide the averaged value as output data. To

configure the data averaging, configure the DATA_AVG_CFG register.

7.3.5.1 Averaging of Two Samples

To enable averaging of two samples, set the EN_DATA_AVG bits in the DATA_AVG_CFG register to 10b. In this

mode, the device averages two samples and provides the average of two samples as output data. The output

data rate reduces by a factor of two. In this mode, the host must provide two pulses separated by a time of t_CYCLE

(see t_CYCLEfor a zone 2 transfer in the Specifications section) on the CONVST pin. The device sets the READY

pin high after a time of t_DRDY(see t_DRDYin the Specifications section) from the second rising edge on the

CONVST pin. After the READY pin is set high, the host can read the data by using one of the protocols for

reading from the device. The host can read the data while providing the two CONVST pulses for acquiring the

next two samples. The host must keep t_READ< [2 × t_CYCLE]. 图 41 provides the timing for the averaging of two

samples.

Sample

”N‘

”N+1‘

”N+3‘

”N+2‘

t_cycle

CONVST

t_{WL_CONVST}

t_DRDY

READY/STROBE

t_READ

CS

SCLK

SDO-xx

Output Data = [Sample ”N‘ + Sample ”N+1‘]/2

图 41. Timing for Averaging of Two Samples

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7.3.5.2 Averaging of Four Samples

To enable averaging of four samples, set the EN_DATA_AVG bits in the DATA_AVG_CFG register to 11b. In

this mode, the device averages four samples and provides the average of four samples as output data. The

output data rate reduces by a factor of four. In this mode, the host must provide four pulses separated by a time

of t_CYCLE(see t_CYCLEfor a zone 2 transfer in the Specifications section) on the CONVST pin. The device sets the

READY pin high after a time of t_DRDY(see t_DRDYin the Specifications section) from the fourth rising edge on the

CONVST pin. After the READY pin is set high, the host can read the data by using one of the protocols for

reading from the device. The host can read the data while providing the four CONVST pulses for acquiring the

next four samples. The host must keep t_READ< [4 × t_CYCLE]. 图 42 provides the timing for the averaging of four

samples.

Sample

”N‘

Sample

”N+1‘

Sample

”N+3‘

Sample

”N+5‘

Sample

”N+6‘

Sample

”N+7‘

Sample

”N+2‘

Sample

”N+4‘

t_cycle

CONVST

t_{WL_CONVST}

t_DRDY

READY/STROBE

t_READ

CS

SCLK

SDO-xx

Output Data = [Sample ”N‘ + Sample ”N+1‘ + Sample ”N+2‘ + Sample ”N+3‘]/4

图 42. Timing for Averaging of Four Samples

7.4 Device Functional Modes

This device supports three functional states: RST or power-down, ACQ, and CNV. The device state is

determined by the status of the CONVST and PD/RST control signals provided by the host controller.

7.4.1 ACQ State

In ACQ state, the device acquires the analog input signal. The device enters ACQ state at power-up, when

coming out of power down, after any asynchronous reset, and by the ADCST signal (internal). A PD/RST falling

edge takes the device from ACQ state to RST state. A CONVST rising edge takes the device from ACQ state to

CNV state.

7.4.2 CNV State

The device moves from ACQ state to CNV state and starts conversion on a rising edge of a CONVST pin. The

conversion process uses an internal clock. The host must provide a minimum time of t_CYCLEbetween two

subsequent start of conversions.

7.4.3 Reset or Power-Down

The PD/RST pin is an asynchronous digital input for the device. The pulse duration (low) on the PD/RST pin

decides the state for the device (reset or power-down). 图 43 provides the timing diagram for these states. On

power-up or after reset the device supports the SPI-00-S protocol for configuring the device and the SPI-00-S-

SDR protocol for reading the data from the device. See the Protocols for Reading From the Device and Protocols

for Configuring the Device sections for details.

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Device Functional Modes (接下页)

t_WL-RST-max

t_WL-RST

t_WL-RST-min

t_WL-PD

RST/PD

Device in

Acquisition

Device in

Acquisition

ADCST(internal)

t_RST-WKUP

t_PD-WKUP

Reset

Power Down

图 43. Reset or Power Down

7.4.3.1 Reset

To enter reset state, the host controller pulls and keeps the PD/RST pin low for a duration of t_{WL_RST}(t_{WL_RST-min}

_{WL_RST}≤ t_{WL_RST-max}).

≤

t

In reset state, the device terminates the ongoing conversion or acquisition process and all configuration registers

(see the Register Maps section) are reset to their default values.

After a delay of t_RST-WKUP, the device enters ACQ state.

7.4.3.2 Power-Down

To enter power-down state, the host controller pulls and keeps the PD/RST pin low for a minimum duration of

t_{WL_PD}

.

In power-down state, all device blocks are powered down and all configuration registers (see the Register Maps

section) are reset to their default values.

To exit power-down state, the host controller pulls the PD/RST pin high. After a delay of t_PD-WKUP, the device

powers up and enters ACQ state.

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Device Functional Modes (接下页)

7.4.4 Conversion Control and Data Transfer Frame

The device supports two modes of conversion control and data transfer, one with zero cycle latency (zone 1

transfer) and another with a wide read cycle (zone 2 transfer).

7.4.4.1 Conversion Control and Data Transfer Frame With Zero Cycle Latency (Zone 1 Transfer)

In this mode of conversion control and data transfer, the device starts conversion on the rising edge of CONVST.

The CONVST pin can be pulled low after a minimum time of t_{WH_CONVST}. After the conversion is finished, the

rising edge of the READY/STROBE pin indicates that the data are ready and the data can be read by the host.

After the READY pin is set high, as shown in 图 44, the host must pull CS low and provide clocks on the SCLK

pin to read the data in zone 1 without cycle latency. For a zone 1 transfer, the host must provide a minimum

delay time of t_{D_CONVST_CS}(= t_DRDY) between the rising edge of CONVST and the falling edge of CS.

The data for the present sample (sample N) is provided by the device on the SDO pins. After all bits are read,

the host can pull the CS pin high to end the data transfer frame. After pulling CS high, the host can pull the

CONVST pin high to start the next conversion. The host must keep the SDI pin low (NOP0) or high (NOP1) for

conversion control and for getting conversion results from the device. In this mode of conversion control, the time

between two adjacent rising edges of the CONVST signal (t_CYCLE) is determined as t_CYCLE= t_DRDY+ t_READ

.

Sample

”N+1‘

Sample

”N‘

t_cycle

t_{WH_CONVST}

t_{WL_CONVST}

CONVST

t_{D_CONVST_CS}

t_READ

CS

t_{D_CONVST_CS-min}

READY/STROBE⁽¹⁾

t_DRDY

t_ACQ

ADCST

Acquisition of Sample ”N+1‘

(Internal)

SCLK

Output Data

Sample ”N‘

SDO-xx

Zone 1

(1) The READY output is required for data transfer with zero cycle latency. The STROBE output is required only for clock

re-timer (CRT) protocols. See the READY/STROBE Output section for details.

(2) For t_READwith different data transfer protocols; see the Protocols for Reading From the Device section.

(3) f_Sample= 1 / t_cycle

.

图 44. Conversion Control and Data Transfer Frame With Zero Cycle Latency (Zone 1 Transfer)

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Device Functional Modes (接下页)

7.4.4.2 Conversion Control and Data Transfer Frame With Wide Read Cycle (Zone 2 Transfer)

In this mode of conversion control and data transfer, the device starts conversion on the rising edge of CONVST.

The CONVST pin can be pulled low after a minimum time of t_{WH_CONVST}. After a time of t_{D_CONVST_CS}(see

t_{D_CONVST_CS}for zone 2 transfer in the Specifications section), the host must pull CS low and provide clocks on

the SCLK pin to read the data in zone 2. As shown in 图 45, a zone 2 transfer provides more read time (t_read).

The read time available for reading data is maximized when t_{D_CONVST_CS}is set to the minimum permissible

value. The data for the previous sample (sample N-1) is provided by the device on the SDO pins. After all bits

are read, the host can pull the CS pin high to end the data transfer frame. After pulling CS high, the host can pull

the CONVST pin high to start the next conversion. In this mode of conversion control, a minimum time of t_CYCLE

(see t_CYCLEfor zone 2 transfer in the Specifications section) is required between two adjacent rising edges of the

CONVST signal. The host must keep the SDI pin low (NOP0) or high (NOP1) for conversion control and for

getting conversion results from the device.

Sample

”N‘

Sample

”N+1‘

t_CYCLE

t_{WH_CONVST}

t_{WL_CONVST}

CONVST

t_{D_CONVST_CS}

t_READ

CS

t_{D_CONVST_CS-min}

t_READ-max

t_{D_CONVST_CS-max}

ADCST

t_ACQ

Acquisition of

(Internal)

Sample ”N+1‘

SCLK

READY/STROBE⁽¹⁾

SDO-xx

Output Data

Sample ”N-1‘

Zone 2

(1) The READY output is not required for zone 2 data transfer. The STROBE output is required only for clock re-timer

(CRT) protocols. See the READY/STROBE Output section for details.

(2) For t_READwith different data transfer protocols; see the Protocols for Reading From the Device section.

(3) f_Sample= 1 / t_cycle

.

图 45. Conversion Control and Data Transfer Frame With Wide Read Cycle (Zone 2 Transfer)

注

For optimum performance with zone 2 transfer, TI recommends masking the READY

output by setting the READY_MASK bit in the OUTPUT_DATA_WORD_CFG register and

using a data transfer protocol with a bus width of more than 2 SDOs or the parallel byte

protocol to keep [t_{D_CONVST_CS}+ t_READ] below 150 ns. See the Protocols for Reading From

the Device section for details on different protocols for reading the data.

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7.5 READY/STROBE Output

The READY/STROBE pin has multiple functions. The READY and STROBE signals are multiplexed to this pin.

When CS is low, STROBE is output and when CS is high, READY is output.

7.5.1 READY Output

After power-up or after exiting power-down (a rising edge on PD/RST), the READY signal is set high. After a time

of 0.9 ms, this signal goes low, indicating that the device is initialized and the registers can be configured.

However, conversions can be performed with the desired accuracy only after a time of t_PD-WKUP(see the

Specifications section). After power-up, for a zone 1 transfer (see 图 44), the device starts conversion on the

CONVST rising edge and the READY pin remains low during the conversion process. After a time of t_DRDY, the

conversion process completes, READY is set high, and data can be read by the host. The host can read data by

bringing CS high and by providing clocks on SCLK. After CS is brought low, READY is set low.

For a zone 2 transfer, TI recommends masking the READY output by setting the READY_MASK bit in the

OUTPUT_DATA_WORD_CFG register.

7.5.2 STROBE Output

In clock re-timer protocols, the device sends out data on the SDO lines with synchronized clock on the STROBE

line. The data are synchronized to the rising edge of the STROBE pulses. In CRT protocols, the host can use the

STROBE output for latching the data. The STROBE for the CRT protocols is either derived from the external

SCLK provided by the host or from the internal oscillator. The STROBE signal is held low for protocols other than

the CRT protocols.

7.6 Programming

7.6.1 Output Data Word

The output data word, as shown in 表 2, consists of a conversion result of N bits, where N is the width of the

output data word. The output data word is provided on data lines (SDO-xx) for each ADC.

表 2. Output Data Word

WIDTH OF

OUTPUT DATA

WORD (N)

MSB OF CONVERSION

RESULT WITH LEFT

ALIGNMENT

MSB OF CONVERSION

RESULT WITH RIGHT

ALIGNMENT

RESOLUTION

OF DEVICE (R)

CONTENT OF OUTPUT

DATA WORD⁽¹⁾⁽²⁾

DEVICE

16-bit conversion in 2's

compliment format

ADS9224R

ADS9234R

16

14

16

D_N-1(= D₁₅

)

D_N-1(= D₁₅

)

14-bit conversion in 2's

compliment format

D_N-1(= D₁₃

D_N-3(= D₁₃

(1) The device provides register data in the output data word during register read operation.

(2) When a fixed pattern data is enabled, the device provides a fixed pattern in the output data word.

For ADS9234R devices with 14-bit resolution, the output data word can be left-aligned or right-aligned by

configuring the DATA_RIGHT_ALIGNED bit. With left alignment, the device appends zeros in the end of the

output data word. With right alignment, the device appends MSBs in the beginning of the output data word. 图 46

shows the data alignment in the data output word.

D₁₃

D₁₂

D₁₁

D₁

D₀

0

Left Aligned Data with Zeros appended at the end

D₁₃

D₁₂

D₂

D₁

D₀

Right Aligned Data with MSBs appended in the beginning (Sign Extension)

图 46. Data Alignment for ADS9234R Devices

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7.6.2 Data Transfer Protocols

This device features an enhanced-SPI digital interface that allows the host controller to operate at slower SCLK

speeds and still achieve the required throughput and response time. The enhanced-SPI digital interface module

offers three options to reduce the SCLK speed required for data transfer:

•

Increase the width of the output data bus (dual SDO, quad SDO, or parallel byte)

Enable double data rate (DDR) transfer

Wider read cycle by extending the data transfer window (zone 2 transfer)

These three options can be combined to achieve further reduction in SCLK speed.

7.6.2.1 Protocols for Reading From the Device

The protocols for the data-read operation can be broadly classified into five categories:

1. Legacy, SPI-compatible protocols (SPI-xy-S-SDR)

2. SPI-compatible protocols with bus width options and single data rate (SPI-xy-D-SDR and SPI-xy-Q-SDR)

3. SPI-compatible protocols with bus width options and double data rate (SPI-x1-S-DDR, SPI-x1-D-DDR, and

SPI-x1-Q-DDR)

4. Clock re-timer (CRT) protocols (CRT-S-SDR, CRT-D-SDR, CRT-Q-SDR, CRT-S-DDR, CRT-D-DDR, and

CRT-Q-DDR)

5. Parallel byte protocol (PB-xy-AB-SDR, PB-xy-AA-SDR)

7.6.2.1.1 Legacy, SPI-Compatible Protocols (SPI-xy-S-SDR)

The device supports legacy, SPI-compatible protocols with all combinations of clock phase and polarity. In this

data transfer protocol, the device provides data from ADC_A on SDO-0A and data from ADC_B on SDO-0B. On

power-up or after reset, the device supports the SPI-00-S-SDR protocol for reading data from the device. 表 3

provides the details of different legacy SPI protocols to read data from the device.

表 3. SPI-xy-S-SDR Protocols for Reading From Device

SCLK POLARITY

(CPOL⁽²⁾

SCLK PHASE

MSB LAUNCH

EDGE

BUS

WIDTH

PROTOCOL⁽¹⁾

t_READ

TIMING DIAGRAM

(5)(6)

(3)(4)

)

(CPHA⁽²⁾

)

SPI-00-S-SDR

SPI-01-S-SDR

SPI-10-S-SDR

SPI-11-S-SDR

Low (CPOL= 0)

High (CPOL= 1)

Rising (CPHA = 0)

Falling (CPHA = 1)

Falling (CPHA = 0)

Rising (CPHA = 1)

CS falling

1^stSCLK rising

CS falling

1

[15.5 × t_CLK+ k]

图 47

图 48

图 47

图 48

1^stSCLK falling

(1) For legacy SPI-compatible protocols, set the SDO_PROTOCOL bits in PROTOCOL_CFG register to 000b.

(2) Configure the SPI_CPOL and SPI_CPHA bits in the PROTOCOL_CFG register for the desired CPOL and CPHA.

(3) With SCLK ≥ 30 MHz, TI recommends data capture on the launch edge for the next bit.

(4) With SCLK < 30 MHz, data can be captured either on the same edge as the SCLK phase or on the launch edge for the next bit.

(5) t_READis the read time for reading the 16-bit output data word. k = (t_{SU_CSCK}+ t_{HT_CKCS}).

(6) For ADS9234R devices, the read time for reading the 14-bit output data word is [13.5 × t_CLK+ k].

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图 47 and 图 48 show timing diagrams for the SPI-00-S-SDR, SPI-10-SDR and SPI-01-S-SDR, SPI-11-SDR

protocols, respectively.

CS

CPOL = 0

CPOL = 1

CPOL = 0

CPOL = 1

SCLK

D₀

A

SDO-0A

SDO-0B

D_N-1

D_N-2

D_N-3

A

B

A

B

A

B

SDO-0A

SDO-0B

D_N-1

D_N-2

D_N-3

D₀

A

B

A

B

A

B

A

B

D_N-1

D_N-2

D_N-3

B

D_N-1

D_N-2

D_N-3

Launch of

1^stBit

Launch of

2^ndBit

End of

Frame

Launch of

1^stBit

Launch of

2^ndBit

End of

Frame

图 48. SPI-01-S-SDR and SPI-11-S-SDR Protocols

图 47. SPI-00-S-SDR and SPI-10-S-SDR Protocols

7.6.2.1.2 SPI-Compatible Protocols With Bus Width Options and Single Data Rate (SPI-xy-D-SDR and SPI-xy-Q-SDR)

In this data transfer protocol, the bus width of reading data from each ADC can be increased to two SDOs or four

SDOs. All combinations of clock phase and polarity are supported. The read time required for reading the output

data word reduces with increases in bus width and, thus, t_CYCLEfor zone 1 transfer reduces. The SDOs that are

not enabled by the BUS_WIDTH register are set to tri-state. 表 4 provides the details of different SPI protocols

with bus width options and single data rate to read data from the device.

表 4. SPI-xy-D-SDR and SPI-xy-Q-SDR Protocols for Reading From Device

SCLK POLARITY

(CPOL)⁽²⁾

SCLK PHASE

(CPHA)⁽³⁾⁽⁴⁾

MSB LAUNCH

EDGE

BUS

PROTOCOL⁽¹⁾

t_READ

TIMING DIAGRAM

(6)(7)

WIDTH⁽⁵⁾

SPI-00-D-SDR

SPI-01-D-SDR

SPI-10-D-SDR

SPI-11-D-SDR

SPI-00-Q-SDR

SPI-01-D-SDR

SPI-10-D-SDR

SPI-11-D-SDR

Low (CPOL = 0)

High (CPOL = 1)

Low (CPOL = 0)

High (CPOL = 1)

Rising (CPHA = 0)

Falling (CPHA = 1)

Falling (CPHA = 0)

Rising (CPHA = 1)

Rising (CPHA = 0)

Falling (CPHA = 1)

Falling (CPHA = 0)

Rising (CPHA = 1)

CS falling

1^stSCLK rising

CS falling

2

4

[7.5 × t_CLK+ k]

[3.5 × t_CLK+ k]

图 49

图 50

图 49

图 50

图 51

图 52

图 51

图 52

1^stSCLK falling

CS falling

1^stSCLK rising

CS falling

1^stSCLK falling

(1) For SPI-compatible protocols with bus width options and SDR, set the SDO_PROTOCOL bits in the PROTOCOL_CFG register to 000b.

(2) Configure the SPI_CPOL and SPI_CPHA bits in the PROTOCOL_CFG register for the desired CPOL and CPHA.

(3) With SCLK ≥ 30 MHz, TI recommends data capture on the launch edge for the next bit.

(4) With SCLK < 30 MHz, data can be captured either on the same edge as the SCLK phase or on the launch edge for the next bit.

(5) For configuring the bus width, configure the BUS_WIDTH register.

(6) t_READis the read time for reading the 16-bit output data word. k = (t_{SU_CSCK}+ t_{HT_CKCS}).

(7) For ADS9234R devices, the read time for reading the 14-bit output data word is [6.5 × t_CLK+ k] for a bus width of 2 and [3.5 × t_CLK+ k]

for a bus width of 4.

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图 49, 图 50, 图 51, and 图 52 show timing diagrams for the SPI-00-D-SDR and SPI-10-D-SDR, SPI-01-D-SDR

and SPI-11-D-SDR, SPI-00-Q-SDR and SPI-10-Q-SDR, and SPI-01-Q-SDR and SPI-11-Q-SDR protocols,

respectively.

CS

CPOL = 0

CPOL = 1

CPOL = 0

CPOL = 1

SCLK

D₁

D₀

SDO-1A

SDO-0A

D_N-1

D_N-3

D_N-5

A

D_1A

A

SDO-1A

SDO-0A

D_N-1

D_N-3

D_N-5

A

D₀

A

D_N-2

D_N-4

D_N-6

A

D_N-2

D_N-4

D_N-6

A

SDO-1B

SDO-0B

D_N-1

D_N-2

D_N-3

D_N-4

D_N-5

D_N-6

D₁

B

SDO-1B

SDO-0B

D_N-1

D_N-3

D_N-5

D₁

D₀

B

D₀

B

D_N-2

D_N-4

D_N-6

End of

Frame

Launch of

2^ndBit

End of

Frame

Launch of

1^stBit

Launch of

1^stBit

Launch of

2^ndBit

图 49. SPI-00-D-SDR and SPI-10-D-SDR Protocols

图 50. SPI-01-D-SDR and SPI-11-D-SDR Protocols

CS

CPOL = 0

CPOL = 1

CPOL = 0

CPOL = 1

SCLK

SDO-3A

SDO-2A

SDO-1A

SDO-0A

D_N-5

D_N-9

D₃

A

D_N-1

A

D₃

D₂

SDO-3A

SDO-2A

SDO-1A

SDO-0A

D_N-9

D_N-1

D_N-2

D_N-3

D_N-4

D_N-5

D_N-6

D_N-7

D_N-8

A

D_N-6

D_N-10

D₂

A

D_N-2

A

D_N-10

A

D_N-7

D_N-12

D₁

A

D_N-3

A

D_1A

D_N-11

A

D_N-8

D_N-13

D₀

A

D_N-4

A

D₀

A

D_N-12

A

SDO-3B

SDO-2B

SDO-1B

SDO-0B

D_N-5

D_N-9

B

D₃

B

D_N-1

B

SDO-3B

SDO-2B

D_N-1

D_N-5

D_N-9

B

D₃

D₂

B

D_N-6

D_N-10

D₂

B

D_N-2

B

D_N-2

D_N-5

D_N-10

B

D_N-7

D_N-12

D₁

B

D_N-3

B

SDO-1B

SDO-0B

D_N-3

D_N-7

D_N-11

D₁

D₀

B

D_N-8

D_N-13

D₀

B

D_N-4

B

D_N-4

D_N-8

D_N-12

Launch of

1^stBit

End of

Frame

Launch of

2^ndBit

Launch of

2^ndBit

Launch of

1^stBit

End of

Frame

图 52. SPI-01-Q-SDR and SPI-11-Q-SDR Protocols

图 51. SPI-00-Q-SDR and SPI-10-Q-SDR Protocols

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7.6.2.1.3 SPI-Compatible Protocols With Bus Width Options and Double Data Rate (SPI-x1-S-DDR, SPI-x1-D-DDR,

SPI-x1-Q-DDR)

In this data transfer protocol, the data rate for data transfer can be increased to double data rate. With double

data rate, the device launches data on both edges (rising and falling) of the SCLK. The device supports both

polarities of the clock and only one phase of clock (CPHA = 1). The read time required for reading the output

data word reduces with increases in bus width and data rate. The SDOs that are not enabled by the

BUS_WIDTH register are set to tri-state. 表 5 provides the details of different SPI protocols with bus width

options and double data rate to read data from the device.

表 5. SPI-x1-S-DDR, SPI-x1-D-DDR, and SPI-x1-Q-DDR Protocols for Reading From Device

SCLK POLARITY

(CPOL)⁽²⁾

MSB LAUNCH

EDGE

BUS

(4)(5)

PROTOCOL⁽¹⁾

SCLK PHASE⁽²⁾

t_READ

TIMING DIAGRAM

WIDTH⁽³⁾

SPI-01-S-DDR

SPI-11-S-DDR

SPI-01-D-DDR

SPI-11-D-DDR

SPI-01-Q-DDR

SPI-11-Q-DDR

Low (CPOL = 0)

High (CPOL = 1)

Low (CPOL = 0)

High (CPOL = 1)

Low (CPOL = 0)

High (CPOL = 1)

Falling (CPHA = 1)

Rising (CPHA = 1)

Falling (CPHA = 1)

Rising (CPHA = 1)

Falling (CPHA = 1)

Rising (CPHA = 1)

1^stSCLK rising

1^stSCLK falling

1^stSCLK rising

1^stSCLK falling

1^stSCLK rising

1^stSCLK falling

1

2

4

[9 × t_CLK+ k]

[5 × t_CLK+ k]

[3 × t_CLK+ k]

图 53

图 54

图 55

(1) For SPI-compatible protocols with bus width options and DDR, set the SDO_PROTOCOL bits in the PROTOCOL_CFG register to 001b.

(2) Configure the SPI_CPOL bits in the PROTOCOL_CFG register for the desired CPOL. The device supports CPHA = 1 only for SPI-

compatible protocols with bus width options and DDR.

(3) For configuring the bus width, configure the BUS_WIDTH register.

(4) t_READis the read time for reading the 16-bit output data word. k = (t_{SU_CSCK}+ t_{HT_CKCS}).

(5) For ADS9234R devices, the read time for reading the 14-bit output data word is [7.5 × t_CLK+ k] for a bus width of 1, [3.5 × t_CLK+ k] for a

bus width of 2, and [3 × t_CLK+ k] for a bus width of 4.

图 53, 图 54, and 图 55 illustrate timing diagrams for the SPI-01-S-DDR and SPI-11-S-DDR, SPI-01-D-DDR and

SPI-11-D-DDR, and SPI-01-Q-DDR and SPI-11-Q-DDR protocols, respectively.

CS

CPOL = 0

CPOL = 1

CPOL = 0

CPOL = 1

SCLK

SDO-1A

D_N-5

D₃

D_N-1

A

D_N-3

D₁

A

SDO-0A

D_N-3

D₁

A

D_N-1

A

D_N-2

D₀

A

SDO-0A

SDO-1B

D_N-6

D₂

D₃

D₂

D_N-2

A

B

A

B

A

B

D_N-4

D_N-3

D_N-4

D₀

D₁

A

B

D_N-5

D_N-1

SDO-0B

B

D_N-3

D₀

B

D_N-1

B

D₁

B

D_N-2

B

SDO-0B

D_N-6

D₀

D_N-2

B

End of

Frame

Launch of

2^ndBit

Launch of

1^stBit

Launch of

1^stBit

Launch of

2^ndBit

End of

Frame

图 53. SPI-01-S-DDR and SPI-11-S-DDR Protocols

图 54. SPI-01-D-DDR and SPI-11-D-DDR Protocols

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CS

CPOL = 0

CPOL = 1

SCLK

SDO-3A

SDO-2A

SDO-1A

SDO-0A

D_{N-5 A}

D_{N-6 A}

D_{N-7 A}

D_{N-8 A}

D_{N-9 A}

D_{3 A}

D_{2 A}

D_{1 A}

D_{0 A}

D_{N-1 A}

D_{N-2 A}

D_{N-3 A}

D_{N-4 A}

D_{N-10 A}

D_{N-12 A}

D_{N-13 A}

SDO-3B

SDO-2B

SDO-1B

SDO-0B

D_{N-5 B}

D_{N-6 B}

D_{N-7 B}

D_{N-8 B}

D_{N-9 B}

D_{3 B}

D_{2 B}

D_{1 B}

D_{0 B}

D_{N-1 B}

D_{N-2 B}

D_{N-3 B}

D_{N-4 B}

D_{N-10 B}

D_{N-12 B}

D_{N-13 B}

Launch of

1^stBit

End of

Frame

Launch of

2^ndBit

图 55. SPI-01-Q-DDR and SPI-11-Q-DDR Protocols

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7.6.2.1.4 Clock Re-Timer (CRT) Protocols (CRT-S-SDR, CRT-D-SDR, CRT-Q-SDR, CRT-S-DDR, CRT-D-DDR, CRT-Q-

DDR)

In clock re-timer (CRT) protocols, the device sends out data on the SDO lines with a synchronized clock on the

STROBE line. The data are synchronized to the rising edges of the STROBE pulses. For CRT protocols with a

single data rate, the host can capture data on the falling edges of the STROBE pulses. For double data rate, the

host must capture data on both edges of STROBE. The clock source for the STROBE output can be selected as

an external clock (SCLK) or an internal clock by configuring the CRT_CLK_SELECT bits in the CRT_CFG

register. For reading data from the device, SCLK is only required when the STROBE output is selected as an

external clock. The SDOs that are not enabled by the BUS_WIDTH register are set to tri-state. 表 6 provides the

details of different CRT protocols to read data from the device.

表 6. CRT-S-SDR, CRT-D-SDR, CRT-Q-SDR, CRT-S-DDR, CRT-D-DDR, and CRT-Q-DDR Protocols for

Reading From Device

MSB LAUNCH

EDGE

1^stSTROBE

rising

1^stSTROBE

rising

1^stSTROBE

rising

1^stSTROBE

rising

1^stSTROBE

rising

1^stSTROBE

rising

BUS

(4)

PROTOCOL⁽¹⁾SCLK POLARITY⁽²⁾

CAPTURE EDGE

STROBE falling

t_READ

TIMING DIAGRAM

WIDTH⁽³⁾

CRT-S-SDR

CRT-D-SDR

CRT-Q-SDR

CRT-S-DDR

CRT-D-DDR

CRT-Q-DDR

Low (CPOL = 0)

1

2

4

1

2

4

[15.5 × t_STROBE+ m]

[7.5 × t_STROBE+ m]

[3.5 × t_STROBE+ m]

[7.5 × t_STROBE+ m]

[3.5× t_STROBE+ m]

[1.5 × t_STROBE+ m]

图 56

图 58

图 60

图 57

图 59

图 61

STROBE rising and

falling

STROBE rising and

falling

STROBE rising and

falling

(1) For CRT protocols with SDR, set the SDO_PROTOCOL bits in the PROTOCOL_CFG register to 010b. For CRT protocols with DDR, set

the SDO_PROTOCOL bits to 011b in the PROTOCOL_CFG register.

(2) The device only supports CPOL = 0 for CRT protocols with an external clock.

(3) For configuring the bus width, configure the BUS_WIDTH register.

(4) t_READis the read time for reading the 16-bit output data word. For an external clock m = (t_{SU_CSCK}+ t_{HT_CKCS}), and for an internal clock

m = t_{D_CS_STROBE}

.

图 56 through 图 61 illustrate timing diagrams for the CRT-S-SDR, CRT-S-DDR, CRT-D-SDR, CRT-D-DDR,

CRT-Q-SDR, and CRT-Q-DDR protocols, respectively.

CS

CPOL = 0

SCLK

CPOL = 0

READY/STROBE

SDO-0A

READY/STROBE

SDO-0A

D_N-2

D₁

D₀

D_N-3

D_N-1

A

B

D₀

A

D_N-1

D_N-2

D_N-3

A

B

A

B

A

B

SDO-0B

D_N-1

D_N-2

D_N-3

D₁

B

SDO-0B

D_N-1

D_N-2

D_N-3

D₀

B

Launch of

1^stBit

Launch of

2^ndBit

End of

Frame

Launch of 1^st

Bit

Launch of

2^ndBit

End of

Frame

图 57. CRT-S-DDR Protocol

图 56. CRT-S-SDR Protocol

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CS

SCLK

CPOL = 0

SCLK

CPOL = 0

READY/STROBE

SDO-1A

READY/STROBE

SDO-1A

D_N-5

D₃

D₂

D_N-1

A

D_N-3

A

D₁

D₀

A

D₁

D₀

A

D_N-1

D_N-3

D_N-5

A

SDO-0A

D_N-2

D_N-4

D_N-6

A

SDO-0A

D_N-2

D_N-4

D_N-6

SDO-1B

SDO-0B

D_N-1

D_N-3

D_N-5

D₃

D₂

D₁

D₀

B

D_N-1

D_N-3

D_N-5

D₁

D₀

B

SDO-1B

SDO-0B

D_N-4

D_N-2

D_N-6

B

D_N-2

D_N-4

D_N-6

Launch of

1^stBit

Launch of

2^ndBit

End of

Frame

Launch of

1^stBit

Launch of

2^ndBit

End of

Frame

图 59. CRT-D-DDR Protocol

图 58. CRT-D-SDR Protocol

CS

CPOL = 0

SCLK

CPOL = 0

READY/STROBE

SDO-3A

READY/STROBE

SDO-3A

D_N-9

D₃

D₂

D_N-1

A

D_N-5

A

D₃

D_N-9

A

D_N-1

D_N-5

A

SDO-2A

D_N-2

D_N-6

D_N-10

A

D₂

D₁

A

D_N-2

D_N-6

D_N-10

A

SDO-2A

SDO-1A

A

SDO-1A

SDO-0A

D_N-11

D₁

D_N-3

D_N-7

D_N-11

D_N-3

A

D_N-7

A

D₀

A

B

D_N-4

D_N-8

D_N-12

A

B

D_N-4

D_N-8

D_N-12

D₀

D₃

SDO-0A

SDO-3B

A

B

A

B

D_N-1

D_N-5

B

D_N-9

SDO-3B

SDO-2B

B

D_N-1

D_N-5

D_N-9

D_N-10

D_N-11

D_N-12

D₃

D₂

D₁

D₀

B

D_N-2

D_N-6

D_N-10

D₂

B

D_N-2

D_N-3

D_N-4

D_N-6

D_N-7

D_N-8

SDO-2B

SDO-1B

B

SDO-1B

SDO-0B

D_N-3

D_N-7

D_N-11

D₁

D₀

B

D_N-4

D_N-8

D_N-12

SDO-0B

B

End of

Frame

Launch of

1^stBit

Launch of

2^ndBit

Launch of

1^stBit

Launch of

2^ndBit

End of

Frame

图 60. CRT-Q-SDR Protocol

图 61. CRT-Q-DDR Protocol

For reading data, SCLK is only required when the STROBE output is selected as SCLK (external clock) in the

CRT_CFG register. However, for configuring registers, SCLK is always required.

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7.6.2.1.5 Parallel Byte Protocols (PB-xy-AB-SDR, PB-xy-AA-SDR)

In parallel byte protocols, the device sends out data from each ADC on all SDO lines in a byte format. The

device supports all combinations of CPOL and CPHA in these protocols. The format of the data byte for these

protocols can be set by the PARALLEL_MODE_DATA_FORMAT bits in the OUTPUT_DATA_WORD_CFG

register. The device only supports a single data rate (SDR) in parallel byte protocols. 表 7 provides the details of

different parallel byte protocols to read data from the device.

表 7. PB-xy-AB-SDR, PB-xy-AA-SDR Protocols for Reading Data

SCLK POLARITY

(CPOL)⁽²⁾

SCLK PHASE

(CPHA)

MSB LAUNCH

EDGE

DATA

TIMING

DIAGRAM

(4)

PROTOCOL⁽¹⁾

t_READ

FORMAT⁽³⁾

PB-00-AB-SDR

PB-01-AB-SDR

PB-10-AB-SDR

Low (CPOL = 0)

High (CPOL = 1)

Rising (CPHA = 0)

Falling (CPHA = 1) 1^stSCLK rising

CS falling

AB

[3.5 × t_CLK+ k]

图 62

图 63

图 62

Falling (CPHA = 1)

Rising (CPHA = 0)

CS falling

1^stSCLK

falling

PB-11-AB-SDR

High (CPOL = 1)

AB

[3.5 × t_CLK+ k]

图 63

PB-00-AA-SDR

PB-01-AA-SDR

PB-10-AA-SDR

Low (CPOL = 0)

High (CPOL = 1)

CS falling

AA

[3.5 × t_CLK+ k]

图 64

图 65

图 64

Falling (CPHA = 1) 1^stSCLK rising

Falling (CPHA = 1)

CS falling

1^stSCLK

falling

PB-11-AA-SDR

High (CPOL = 1)

Rising (CPHA = 0)

AA

[3.5 × t_CLK+ k]

图 65

(1) For parallel byte protocols, set the SDO_PROTOCOL bits in the PROTOCOL_CFG register to 1xxb.

(2) Configure the SPI_CPOL and SPI_CPHA bits in the PROTOCOL_CFG register for the desired CPOL and CPHA.

(3) For selecting the data format for parallel byte protocols, configure the PARALLEL_MODE_DATA_FORMAT bits in the

OUTPUT_DATA_WORD_CFG register.

(4) t_READis the read time for reading the 16-bit output data word. k = (t_{SU_CSCK}+ t_{HT_CKCS}).

图 62, 图 63, 图 64, and 图 65 illustrate timing diagrams for the PB-00-AB-SDR and PB-10-AB-SDR, protocols,

PB-01-AB-SDR and PB-11-AB-SDR, PB-00-AA-SDR and PB-10-AA-SDR, and PB-01-AA-SDR and PB-11-AA-

SDR, respectively.

CS

CPOL = 0

SCLK

CPOL = 1

SDO-7

SDO-6

SDO-5

SDO-4

D_{N-9 A}

D_{N-1 A}

D_{N-2 A}

D_{N-3 A}

D_{N-4 A}

D_{N-9 B}

D_{N-1 B}

SDO-7

SDO-6

SDO-5

SDO-4

D_{N-9 A}

D_{N-1 A}

D_{N-2 A}

D_{N-3 A}

D_{N-4 A}

D_{N-9 B}

D_{N-1 B}

D_{N-10 A}

D_{N-10 B}

D_{N-2 B}

D_{N-10 A}

D_{N-10 B}

D_{N-2 B}

D_{N-11 A}

D_{N-11 B}

D_{N-3 B}

D_{N-11 A}

D_{N-11 B}

D_{N-3 B}

D_{N-12 A}

D_{N-12 B}

D_{N-4 B}

D_{N-12 A}

D_{N-12 B}

D_{N-4 B}

SDO-3

SDO-2

D_{N-5 A}

D_{N-6 A}

D_{N-7 A}

D_{N-8 A}

D_{N-5 B}

D_{3 B}

D_{3 A}

D_{2 A}

D_1A

D_{0 A}

SDO-3

SDO-2

D_{N-5 A}

D_{N-6 A}

D_{N-7 A}

D_{N-8 A}

D_{N-5 B}

D_{3 B}

D_{3 A}

D_{2 A}

D_1A

D_{0 A}

D_{N-5 B}

D_{2 B}

D_{N-5 B}

D_{2 B}

SDO-1

SDO-0

D_{N-7 B}

D_{1 B}

SDO-1

SDO-0

D_{N-7 B}

D_{1 B}

D_{N-8 B}

D_{0 B}

D_{N-8 B}

D_{0 B}

End of

Frame

Launch

End of

Frame

of 1^stBit

of 2^ndBit

of 1^stBit

of 2^ndBit

图 62. PB-00-AB-SDR and PB-10-AB-SDR Protocols

图 63. PB-01-AB-SDR and PB-11-AB-SDR Protocols

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CS

CPOL = 0

CPOL = 1

CPOL = 0

SCLK

CPOL = 1

SDO-7

SDO-6

SDO-5

SDO-4

D_{N-9 A}

SDO-7

SDO-6

SDO-5

SDO-4

D_{N-1 A}

D_{N-2 A}

D_{N-3 A}

D_{N-4 A}

D_{N-9 B}

D_{N-1 A}

D_{N-2 A}

D_{N-3 A}

D_{N-4 A}

D_{N-9 A}

D_{N-9 B}

D_{N-1 B}

D_{N-10 A}

D_{N-10 B}

D_{N-2 B}

D_{N-11 A}

D_{N-11 B}

D_{N-3 B}

D_{N-12 B}

D_{N-12 A}

D_{N-12 B}

D_{N-4 B}

SDO-3

SDO-2

D_{N-5 A}

D_{N-6 A}

D_{N-7 A}

D_{N-8 A}

D_{3 B}

SDO-3

SDO-2

D_{3 A}

D_{2 A}

D_1A

D_{0 A}

D_{N-5 B}

D_{N-5 A}

D_{N-6 A}

D_{N-7 A}

D_{N-8 A}

D_{3 B}

D_{3 A}

D_{2 A}

D_1A

D_{0 A}

D_{2 B}

D_{N-5 B}

D_{2 B}

SDO-1

SDO-0

D_{1 B}

D_{N-7 B}

SDO-1

SDO-0

D_{N-7 B}

D_{1 B}

D_{0 B}

D_{N-8 B}

D_{0 B}

Launch

End of

Frame

Launch

of 1^stBit

Launch

End of

Frame

of 1^stBit

of 2^ndBit

图 64. PB-00-AA-SDR and PB-10-AA-SDR Protocols

图 65. PB-01-AA-SDR and PB-11-AA-SDR Protocols

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7.6.2.2 Device Setup

The enhanced-SPI digital interface and the device configuration registers offer multiple operation modes. This

section describes how to select the hardware connection topology to meet different system requirements.

7.6.2.2.1 Single Device: All Enhanced-SPI Options

图 66 shows the connections between a host controller and a single device in order to exercise all options

provided by the enhanced-SPI digital interface.

DVDD

Isolation

(Optional)

PD/RST

CONVST

CS

SCLK

SDI

Host

Controller

TI Device

SDO-0x

SDO-1x

SDO-2x

SDO-3x

READY/STROBE

图 66. Enhanced-SPI Digital Interface, All Pins

7.6.2.2.2 Single Device: Minimum Pins for a Standard SPI Interface

图 67 shows the minimum-pin interface for applications using a standard SPI protocol.

DVDD

Isolation

(Optional)

PD/RST

(Optional)

CONVST

CS

SCLK

SDI

Host

Controller

TI Device

SDO-0x

SDO-1x

SDO-2x

SDO-3x

(Optional)

READY/STROBE

图 67. SPI Interface, Minimum Pins

The CS, SCLK, SDI, and SDO-0x pins constitute a standard SPI port of the host controller. The CONVST pin is

tied to CS, and the PD/RST pin is tied to DVDD. The SDO-1x, SDO-2x, and SDO-3x pins have no external

connections. The following features are also available:

•

Control the CONVST pin independently to get additional timing flexibility.

Control PD/RST pin independently to add asynchronous reset functionality.

Monitor the READY/STROBE pin for additional timing benefits.

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7.6.2.3 Protocols for Configuring the Device

The device supports an SPI protocol for writing into the device with all combinations of clock polarity and phase.

On power-up or after reset, the device supports the SPI-00-S protocol for configuring the device. of As shown in

表 8, the host controller can use any of the four legacy, SPI-compatible protocols (SPI-00-S, SPI- 01-S, SPI-10-

S, or SPI-11-S) to write data to the device.

表 8. SPI Protocols for Configuring the Device

SCLK

SCLK POLARITY

(2)

PROTOCOL

PHASE

MSB CAPTURE EDGE

t_WRITE

TIMING DIAGRAM

(CPOL)⁽¹⁾

(CPHA)⁽¹⁾

Rising

(CPHA = 0)

SPI-00-S

SPI-01-S

SPI-10-S

SPI-11-S

Low (CPOL= 0)

High (CPOL= 1)

1^stSCLK rising

1^stSCLK falling

1^stSCLK rising

[15.5 × t_CLK+ k]

图 68

图 69

图 68

图 69

Falling

(CPHA = 1)

Falling

(CPHA = 1)

Rising

(CPHA = 0)

(1) Configure the SPI_CPOL and SPI_CPHA bits in the PROTOCOL_CFG register for the desired CPOL and CPHA.

(2) t_WRITEis the write time for writing the 16-bit data word. k = (t_{SU_CSCK}+ t_{HT_CKCS}).

图 68 and 图 69 show timing diagrams for the SPI-00-S, SPI-10-S and SPI-01-S, SPI-11-S protocols,

respectively, for configuring the device.

CS

CPOL = 0

SCLK

CPOL = 0

CPOL = 1

SCLK

SDI

C₁₅

C₁₄

C₁₃

C₀

SDI

C₁₅

C₁₄

C₁₃

C₀

Capture

of 1^stBit

Capture

of 2^ndBit

End of

Frame

Capture

of 1^stBit

Capture

of 2^ndBit

End of

Frame

图 69. SPI-01-S and SPI-11-S Protocols for Configuring the

图 68. SPI-00-S and SPI-10-S Protocols for Configuring the

Device

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7.6.3 Reading and Writing Registers

To read a register or write into a register, the host must provide a 16-bit command frame C[15:0] on SDI. A

command frame consists of an OPCODE[3:0], ADDRESS[3:0], and DATA[7:0]. The host must keep the CONVST

signal high for reading and writing the registers. 图 70 shows the command frame. 表 9 provides the details of

commands for reading and writing registers.

C₁₅

C₁₄

C₁₃

C₁₂

C₁₁

C₁₀

C₉

A₁

C₈

A₀

C₇

D₇

C₆

D₆

C₅

D₅

C₄

D₄

C₃

D₃

C₂

D₂

C₁

D₁

C₀

D₀

OP₃OP₂OP₁OP₀

A₃

A₂

OPCODE

ADDRESS

DATA

图 70. Command Frame C[15:0]

表 9. Commands for Reading and Writing Registers

OPCODE[3:0]

DESCRIPTION

ADDRESS[3:0]

N/A

DATA[7:0]

Command for conversion control and reading conversion

results

0000

0001

0010

NOP0

N/A

4-bit register

address

WRITE

Command for writing registers

Command for reading registers

8-bit register data

00h or FFh

4-bit register

address

READ⁽¹⁾

Bits with values of 1 in DATA

are set and bits with values of 0

in register data are not

changed.

Command for setting specific bits in a register without

changing the other bits

4-bit register

address

0101

Set bit

Bits with values of 1 in DATA

are cleared and bits with values

of 0 in register data are not

changed.

Command for clearing specific bits in a register without

changing the other bits

4-bit register

address

0110

1111

Clear bit

NOP1

Command for conversion control and reading conversion

results

N/A

Remain

ing

combin

ations

These commands are reserved

and are treated by the device

as no operation

xxxxxxxxx

Reserved

(1) Register data for READ command is provided by device in the next frame.

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7.7 Register Maps

7.7.1 ADS92x4R Registers

Table 10 lists the ADS92x4R registers. All register offset addresses not listed in Table 10 should be considered

as reserved locations and the register contents should not be modified.

Table 10. ADS92X4R Registers

Offset

Acronym

Register Name

Section

0h

DEVICE_STATUS

Device status register

DEVICE_STATUS

Register (Offset =

0h) [reset = 0h]

1h

2h

3h

4h

5h

POWER_DOWN_CFG

PROTOCOL_CFG

BUS_WIDTH

Power down configuration register

Protocol configuration register

POWER_DOWN_C

FG Register (Offset

= 1h) [reset = 0h]

PROTOCOL_CFG

Register (Offset =

2h) [reset = 0h]

Bus width configuration register

Clock re-timer configuration register

Output data word configuration register

BUS_WIDTH

Register (Offset =

3h) [reset = 0h]

CRT_CFG

CRT_CFG Register

(Offset = 4h) [reset

= 0h]

OUTPUT_DATA_WORD_CFG

OUTPUT_DATA_W

ORD_CFG Register

(Offset = 5h) [reset

= 0h]

6h

7h

DATA_AVG_CFG

REFBY2_OFFSET

Data averaging configuration register

REFby2 offset selection register

DATA_AVG_CFG

Register (Offset =

6h) [reset = 0h]

REFBY2_OFFSET

Register (Offset =

7h) [reset = 0h]

Complex bit access types are encoded to fit into small table cells. Table 11 shows the codes that are used for

access types in this section.

Table 11. ADS92x4R Access Type Codes

Access Type

Read Type

R

Code

Description

R

Read

Write Type

W

Write

Reset or Default Value

-n

Value after reset or the default

value

Register Array Variables

i,j,k,l,m,n

When these variables are used in

a register name, an offset, or an

address, they refer to the value of

a register array where the register

is part of a group of repeating

registers. The register groups form

a hierarchical structure and the

array is represented with a

formula.

y

When this variable is used in a

register name, an offset, or an

address it refers to the value of a

register array.

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7.7.1.1 DEVICE_STATUS Register (Offset = 0h) [reset = 0h]

DEVICE_STATUS is shown in Figure 71 and described in Table 12.

Return to the Summary Table.

Device status register

Figure 71. DEVICE_STATUS Register

7

6

5

4

3

2

1

0

RESERVED

ZONE2_TRAN AVG_ERROR

SFER

RESERVED

R-00000b

R/W-0b

R-0b

Table 12. DEVICE_STATUS Register Field Descriptions

Bit

Field

Type

R

Reset

00000b

0b

Description

7-3

2

RESERVED

Reserved bits. Do not write to these bits. Read returns 00000b

ZONE2_TRANSFER

R/W

This bit is set when the device operates in zone 2 transfer mode with

a wide read cycle. This bit is a sticky bit. Write 1 to this bit to clear.

1

0

AVG_ERROR

RESERVED

R/W

R

0b

This bit is set when the device receives a falling edge of CS before

the current averaging operation is complete. This bit is a sticky bit.

Write 1 to this bit to clear.

Reserved bits. Do not write to this bit. Read returns 0b.

7.7.1.2 POWER_DOWN_CFG Register (Offset = 1h) [reset = 0h]

POWER_DOWN_CFG is shown in Figure 72 and described in Table 13.

Return to the Summary Table.

Power down configuration register

Figure 72. POWER_DOWN_CFG Register

7

6

5

4

3

2

1

0

RESERVED

R-00b

PD_REFBY2

R/W-0b

RESERVED

R-0b

PD_ADCB

R/W-0b

RESERVED

R-0b

PD_ADCA

R/W-0b

PD_REF

R/W-0b

Table 13. POWER_DOWN_CFG Register Field Descriptions

Bit

Field

Type

R

Reset

00b

0b

Description

7-6

5

RESERVED

PD_REFBY2

Reserved bits. Do not write to these bits. Read returns 00b.

This bit powers down REFby2 output.

R/W

0b = _1 : REFby2 is not powered down.

1b = _2 : REFby2 is powered down.

4

3

RESERVED

PD_ADCB

R

0b

Reserved bits. Do not write to this bit. Read returns 0b.

This bit powers down ADC_B and REFBUF_B.

0b = _1 : ADC_B and REFBUF_B are not powered down.

1b = _2 : ADC_B and REFBUF_B are powered down.

R/W

2

1

RESERVED

PD_ADCA

R

0b

R/W

This bit powers down ADC_A and REFBUF_A.

0b = _1 : ADC_A and REFBUF_A are not powered down.

1b = _2 : ADC_A and REFBUF_A are powered down.

This bit powers down ADC's internal reference.

0

PD_REF

R/W

0b

0b = _1 : ADC internal reference is not powered down.

1b = _2 : ADC internal reference is powered down.

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7.7.1.3 PROTOCOL_CFG Register (Offset = 2h) [reset = 0h]

PROTOCOL_CFG is shown in Figure 73 and described in Table 14.

Return to the Summary Table.

Protocol configuration register

Figure 73. PROTOCOL_CFG Register

7

6

5

4

3

2

1

0

RESERVED

R-0b

SDO_PROTOCOL[2:0]

R/W-000b

RESERVED

R-00b

SPI_CPOL

R/W-0b

SPI_CPHA

R/W-0b

Table 14. PROTOCOL_CFG Register Field Descriptions

Bit

7

Field

Type

R

Reset

0b

Description

Reserved bit. Do not write to this bit. Read returns 0b.

RESERVED

6-4

SDO_PROTOCOL[2:0]

R/W

000b

These bits set the protocol for reading data from the device.

000b = _1 : Legacy, SPI compatible protocols (SPI-xy-S-SDR); SPI

compatible protocols with bus width options and SDR (SPI-xy-D-

SDR and SPI-xy-Q-SDR) protocols.

001b = _2 : SPI compatible protocols with bus width options and

DDR (SPI-x1-S-DDR, SPI-x1-D-DDR, SPI-x1-Q-DDR) protocols.

010b = _3 : Clock re-timer (CRT) protocols with SDR (CRT-S-SDR,

CRT-D-SDR, CRT-Q-SDR).

011b = _4 : CRT protocols with DDR (CRT-S-DDR, CRT-D-DDR,

CRT-Q-DDR).

100b = _5 : Parallel byte protocol. Writing 1xx enables parallel byte

protocol.

101b = _6 : Parallel byte protocol. Writing 1xx enables parallel byte

protocol.

110b = _7 : Parallel byte protocol. Writing 1xx enables parallel byte

protocol.

111b = _8 : Parallel byte protocol. Writing 1xx enables parallel byte

protocol.

3-2

1

RESERVED

SPI_CPOL

R

00b

0b

Reserved bits. Do not write to these bits. Read returns 00b.

R/W

This bit sets the clock polarity for reading data from the device and

writing data into the device.

0b = _1 : CPOL = 0

1b = _2 : CPOL = 1

0

SPI_CPHA

R/W

0b

This bit sets the clock phase for reading data from the device and

writing data into the device.

0b = _1 : CPHA = 0

1b = _2 : CPHA = 1

7.7.1.4 BUS_WIDTH Register (Offset = 3h) [reset = 0h]

BUS_WIDTH is shown in Figure 74 and described in Table 15.

Return to the Summary Table.

Bus width configuration register

Figure 74. BUS_WIDTH Register

7

6

5

4

3

2

1

0

RESERVED

R-000000b

SDO_WIDTH[1:0]

R/W-00b

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Table 15. BUS_WIDTH Register Field Descriptions

Bit

7-2

1-0

Field

Type

R

Reset

000000b

00b

Description

RESERVED

SDO_WIDTH[1:0]

Reserved bits. Do not write to these bits. Read returns 000000b.

R/W

These bits set the number of SDO lines for reading data from the

device. If the device is configured for parallel byte protocol, then

SDO_WIDTH is ignored and the device sends data over all eight

SDO lines as per the parallel byte protocol.

00b = _1 : One SDO per ADC.

01b = _2 : One SDO per ADC.

10b = _3 : Dual SDO per ADC.

11b = _4 : Quad SDO per ADC.

7.7.1.5 CRT_CFG Register (Offset = 4h) [reset = 0h]

CRT_CFG is shown in Figure 75 and described in Table 16.

Return to the Summary Table.

Clock re-timer configuration register

Figure 75. CRT_CFG Register

7

6

5

4

3

2

1

0

RESERVED

R-000000b

CRT_CLK_SELECT[1:0]

R/W-00b

Table 16. CRT_CFG Register Field Descriptions

Bit

Field

Type

R

Reset

000000b

00b

Description

7-2

1-0

RESERVED

Reserved bits. Do not write to these bits. Read returns 000000b.

CRT_CLK_SELECT[1:0]

R/W

These bits select the clock source for the strobe output for CRT

protocols.

00b = _1 : Serial clock (SCLK) is used for STROBE output.

01b = _2 : INTCLK is used for the STROBE output.

10b = _3 : INTCLK/2 is used for the STROBE output.

11b = _4 : INTCLK/4 is used for the STROBE output.

7.7.1.6 OUTPUT_DATA_WORD_CFG Register (Offset = 5h) [reset = 0h]

OUTPUT_DATA_WORD_CFG is shown in Figure 76 and described in Table 17.

Return to the Summary Table.

Output data word configuration register

Figure 76. OUTPUT_DATA_WORD_CFG Register

7

6

5

4

3

2

1

0

RESERVED

R-00b

READY_MASK PARALLEL_M

ODE_DATA_F

RESERVED

R-00b

FIXED_PATTE DATA_RIGHT_

RN_DATA

ALIGNED

ORMAT

R/W-0b

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Table 17. OUTPUT_DATA_WORD_CFG Register Field Descriptions

Bit

7-6

5

Field

Type

R

Reset

00b

0b

Description

RESERVED

READY_MASK

Reserved bits. Do not write to these bits. Read returns 00b.

R/W

This bit masks the READY output. The STROBE output is provided

in CRT protocols even if READY_MASK is set to 1. TI recommends

masking the READY output for the Conversion Control and Data

Transfer Frame With Wide Read Cycle (Zone 2 Transfer) section.

0b = _1 : Does not mask the READY output.

1b = _2 : Masks the READY output.

4

PARALLEL_MODE_DATA R/W

_FORMAT

0b

This bit selects the format for the output data word in the parallel

byte protocol.

0b = _1 : Data format AA: byte from ADC_A followed by byte from

ADC_A (PB-xy-AA-zDR protocol).

1b = _2 : Data format AB: byte from ADC_A followed by byte from

ADC_B (PB-xy-AB-zDR protocol).

3-2

1

RESERVED

R

00b

0b

Reserved bits. Do not write to these bits. Read returns 00b.

This bit enables a fixed pattern in the output data word.

FIXED_PATTERN_DATA R/W

0b = _1 : Device provides the conversion results from the register

data in the output word.

1b = _2 : Device provides a fixed pattern (A55AA55Ah) in the output

data word.

0

DATA_RIGHT_ALIGNED R/W

0b

This bit enables the right alignment in the output data word for

ADS9234R device.

0b = _1 : Data are left-aligned in the output data word.

1b = _2 : Data are right-aligned in the output data word.

7.7.1.7 DATA_AVG_CFG Register (Offset = 6h) [reset = 0h]

DATA_AVG_CFG is shown in Figure 77 and described in Table 18.

Return to the Summary Table.

Data averaging configuration register

Figure 77. DATA_AVG_CFG Register

7

6

5

4

3

2

1

0

RESERVED

R-000000b

EN_DATA_AVG[1:0]

R/W-00b

Table 18. DATA_AVG_CFG Register Field Descriptions

Bit

Field

Type

R

Reset

000000b

00b

Description

7-2

1-0

RESERVED

Reserved bits. Do not write to these bits. Read returns 000000b.

These bits enable averaging of conversion results.

00b = _1 : No averaging.

EN_DATA_AVG[1:0]

R/W

01b = _2 : No averaging.

10b = _3 : Enables averaging of two conversion results.

11b = _4 : Enables averaging of four conversion results.

7.7.1.8 REFBY2_OFFSET Register (Offset = 7h) [reset = 0h]

REFBY2_OFFSET is shown in Figure 78 and described in Table 19.

Return to the Summary Table.

REFby2 offset selection register

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Figure 78. REFBY2_OFFSET Register

7

6

5

4

3

2

1

0

RESERVED

EN_REFBY2_

OFFSET

R-0000000b

R/W-0b

Table 19. REFBY2_OFFSET Register Field Descriptions

Bit

Field

Type

R

Reset

0000000b

0b

Description

7-1

0

RESERVED

Reserved bits. Do not write to these bits. Read returns 0000000b.

This bit enables the offset for the REFby2 output.

EN_REFBY2_OFFSET

R/W

0b = _1 : Offset for the REFby2 output is disabled.

1b = _2 : Offset for the REFby2 output is enabled and the REFby2

output increases by 100 mV.

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

This section presents general principles for designing these circuits, followed by an application circuit designed

using the ADS92x4R.

8.1.1 ADC Input Driver

The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a charge

kickback filter. The amplifier is used for signal conditioning of the input signal and the low output impedance of

the amplifier provides a buffer between the signal source and the switched-capacitor inputs of the ADC. The

charge kickback filter helps attenuate the sampling charge injection from the switched-capacitor input stage of

the ADC, and band-limits the wideband noise contributed by the front-end circuit. Careful design of the front-end

circuit is critical to meet the linearity and noise performance of the ADS92x4R.

8.1.1.1 Charge-Kickback Filter

The charge-kickback filter is an RC filter at the input pins of the ADC that filters the broadband noise from the

front-end drive circuitry, and attenuates the sampling charge injection from the switched-capacitor input stage of

the ADC. A filter capacitor, C_FLT(as shown in 图 79), is connected from each input pin of the ADC to the ground.

This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly charge the

internal sample-and-hold capacitors during the acquisition process. Generally, the value of this capacitor must be

at least 20 times the specified value of the ADC sampling capacitance. For the ADS92x4R, the input sampling

capacitance is equal to 16 pF; therefore, for optimal performance, keep C_FLTgreater than 320 pF. This capacitor

must be a C0G- or NP0-type. The type of dielectric used in C0G or NP0 ceramic capacitors provides the most

stable electrical properties over voltage, frequency, and temperature changes.

R_FLT

C_FLT

Device

R_FLT

C_FLT

图 79. Charge Kickback Filter

Driving capacitive loads can degrade the phase margin of the input amplifier, thus making the amplifier

marginally unstable. To avoid amplifier stability issues, series isolation resistors (R_FLT) are used at the output of

the amplifiers. A higher value of R_FLThelps with amplifier stability, but adds distortion as a result of interactions

with the nonlinear input impedance of the ADC. Distortion increases with source impedance, input signal

frequency, and input signal amplitude. Therefore, the selection of R_FLTrequires balancing the stability of the

driver amplifier and distortion performance of the design. Always verify the stability and settling behavior of the

driving amplifier and charge-kickback filter by TINA-TI™ SPICE simulation. Keep the tolerance of the selected

resistors less than 1% to keep the inputs balanced.

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Application Information (接下页)

8.1.2 Input Amplifier Selection

Selection criteria for the input amplifiers is highly dependent on the input signal type as well as the performance

goals of the data acquisition system. Some key amplifier specifications to consider when selecting an appropriate

amplifier to drive the inputs of the ADC are:

•

Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible

after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance

of the amplifier, thus allowing the amplifier to more easily drive the ADC sample-and-hold capacitor and the

RC filter (the charge-kickback filter) at the inputs of the ADC. Higher bandwidth amplifiers offer faster settling

times when driving the capacitive load of the charge-kickback filter, thus reducing harmonic distortion at

higher input frequencies. 公式 4 describes the unity gain bandwidth (UGB) of the amplifier to be selected in

order to maintain the overall stability of the input driver circuit:

≈

∆

«

’

÷

◊

1

UGB í 4 ì

2p

ì R_FLTì C_FLT

(4)

•

Distortion. Both the ADC and the input driver introduce distortion in a data acquisition block. 公式 5 shows

that to make sure that the distortion performance of the data acquisition system is not limited by the front-end

circuit, the distortion of the input driver must be at least 10 dB less than the distortion of the ADC:

THD_AMPÇ THD_ADC- 10

(

dB

)

(5)

Noise. Noise contribution of the front-end amplifiers must be as low as possible to prevent any degradation in

SNR performance of the system. Generally, to make sure that the noise performance of the data acquisition

system is not limited by the front-end circuit, the total noise contribution from the front-end circuit must be

kept below 20% of the input-referred noise of the ADC. 公式 6 explains that noise from the input driver circuit

is band-limited by designing a low cutoff frequency, charge-kickback filter:

2

SNR

(

dB

)

≈

∆

’

÷

V

≈

∆

’

÷

-

1

_ AMP_PP

p

2

1

5

V_REF

2

20

+ e_n²_{_RMS}

ì

ì f_-3dB

Ç

ì

ì10

f

«

◊

N_Gì 2 ì

∆

÷

6.6

«

◊

where

•

V_{1 / f_AMP_PP}is the peak-to-peak flicker noise in μV

e_{n_RMS}is the amplifier broadband noise density in nV/√Hz

f_–3dBis the 3-dB bandwidth of the charge-kickback filter

N_Gis the noise gain of the front-end circuit that is equal to 1 in a buffer configuration

(6)

•

Settling Time. For DC signals with fast transients that are common in a multiplexed application, the input

signal must settle within an 16-bit accuracy at the device inputs during the acquisition time window. This

condition is critical to maintain the overall linearity performance of the ADC. Typically, amplifier data sheets

specify the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the desired

16-bit accuracy. Therefore, always verify the settling behavior of the input driver by TINA-TI SPICE

simulations before selecting the amplifier.

For additional details on SAR ADC input architecture and SAR ADC driver amplifier design, see the TI Precision

Labs for ADCs.

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8.2 Typical Application

10 µF

1 µF

GND

REFP_A

5

31

32 REFP_M

REFBUF_A

4

REFOUT

11

12

GND

1 kꢀ

GND

Internal

V_REF

1 µF

AVDD

330pF

1 kꢀ

4ꢀ

AVDD

AINP_A

+

-

1

3300 pF

REFby2

29

30

V_OCM

ADC_A

THS4551

1 µF

1 kꢀ

2

-

+

AINM_A

GND

330pF

Serial

Interface

GND

ADS92x4R

1 kꢀ

DVDD

GND

28

27

AVDD

-

330pF

1 µF

1 kꢀ

4ꢀ

AINP_B

8

+

3300 pF

REFby2

THS4551

V_OCM

ADC_B

1 kꢀ

4ꢀ

-

7

+

AINM_B

GND

330pF

Internal

V_REF

REFBUF_B

1 kꢀ

GND

REFby2

3

10

9

REFP_B

GND

REFM_B

4

10 µF

1 µF

图 80. DAQ Circuit for Lowest Distortion and Noise With the ADS92x4R for a 100-kHz Input Signal

8.2.1 Design Requirements

The design parameters are listed in 表 20 for this example.

表 20. Design Parameters

DESIGN PARAMETER

ADC sample rate

Analog input signal

SNR

EXAMPLE VALUE

3 MSPS

100 kHz, 8.192 V_PP, fully differential

> 92 dB

THD

< –105dB

INL

< ±1 LSB

Power supply

5-V analog, 3.3-V digital

8.2.2 Detailed Design Procedure

图 80 shows an application circuit for this example. The device incorporates an internal 2.5-V reference voltage

and independent matched reference buffers for each ADC. The internal reference output (REFOUT) is decoupled

with a 1-µF capacitor. The matched reference buffers provide a gain of 1.6384 V/V and generate a high-

precision, 4.096-V reference voltage for each ADC channel. Decouple the reference buffer outputs (the REFP_A

and REFP_B pins) with the REFM_A and REFM_B pins, respectively, with 10-µF decoupling capacitors. The

circuit in 图 80 shows a fully-differential data acquisition (DAQ) block optimized for low distortion and noise using

the THS4551 and the ADS92x4R. Both differential ADC inputs are driven using a high-bandwidth, low-distortion,

fully differential amplifier (FDA) designed in a gain of 1 V/V and an optimal RC charge-kickback filter before going

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to the ADC. Generally, the distortion from the input driver must be at least 10 dB less than the ADC distortion.

Therefore, these circuits use the low-power THS4551 as an input driver that provides exceptional AC

performance because of its extremely low-distortion and high bandwidth specifications. In addition, the

components of the charge kickback filter are selected to keep the noise from the front-end circuit low without

adding distortion. This front-end circuit configuration requires a differential signal at the input of the FDA and

provides a differential output to drive the ADC inputs. The FDA establishes a fixed common-mode voltage at the

ADC inputs using the VOCM input pin from the FDA. The ADS92x4R incorporates a REFby2 buffer output for

setting the common-mode voltage. The ADS92x4R REFby2 output is decoupled using a 1-µF capacitor and

connected to each FDA VOCM input pin. Each VOCM pin is decoupled using a 0.1-µF capacitor. For a complete

schematic, see the ADS9224REVM-PDK user's guide located in the ADS9224R SAR analog to digital converter

evaluation module tool folder.

8.2.3 Application Curves

图 81 provides the typical FFT for the circuit in 图 80 and 图 82 provides the typical INL for the circuit in 图 80.

2

1.5

1

0

-30

-60

0.5

0

-90

-0.5

-1

-120

-150

-180

-1.5

-2

0

200000

400000

600000

800000

1000000

-35000 -25000 -15000 -5000

5000 15000 25000 35000

Frequency(Hz)

Output Code

D001

D002

SNR = 92.8 dB, THD = –105 dB, ENOB = 14.9 bits

INL = ±0.8 LSB, DNL = ±0.2 LSB

图 82. Typical INL

图 81. Typical FFT With 100-kHz Signal

52

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ADS9234R

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ZHCSIJ5C –AUGUST 2018–REVISED JUNE 2019

9 Power Supply Recommendations

The devices have two separate power supplies: AVDD and DVDD. The reference buffers, internal reference

voltage, and converter modules (ADC_A and ADC_B) operate on AVDD. The serial interface operates on DVDD.

AVDD and DVDD can be independently set to any value within their permissible ranges.

To operate the device with SCLK more than 20-MHz, TI recommends to set the DVDD voltage as: 2.35 V ≤

DVDD ≤ 5.5 V.

As shown in 图 83, connect pins 12 and 29 together and place 1-µF decoupling capacitors between pin 12

(AVDD) and pin11 (GND), and between pin 29 (AVDD) and pin 30 (GND). To decouple the DVDD supply, place

a 1-µF decoupling capacitor between pin 28 (DVDD) and pin 27 (GND).

1 µF

29

11

GND

12

30

GND

AVDD AVDD

AVDD

Internal

V_REF

REFBUF_A

AVDD

DVDD

GND

28

27

AINP_A

1 µF

ADC_A

AINM_A

AINP_B

Serial

Interface

ADC_B

AVDD

AINM_B

Internal

V_REF

REFBUF_B

AVDD

图 83. Power-Supply Decoupling

53

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www.ti.com.cn

10 Layout

10.1 Layout Guidelines

This section provides some layout guidelines for achieving optimum performance with the ADS92x4R.

10.1.1 Signal Path

As illustrated in 图 84, the analog input signals are routed in opposite directions to the digital connections. The

reference decoupling components are kept away from the switching digital signals. This arrangement prevents

noise generated by digital switching activity from coupling to sensitive analog signals.

10.1.2 Grounding and PCB Stack-Up

Low inductance grounding is critical for achieving optimum performance. Grounding inductance is kept below 1

nH with 15-mil grounding vias and a printed circuit board (PCB) layout design that has at least four layers. Place

all critical components of the signal chain on the top layer with a solid analog ground from subsequent inner

layers to minimize via length to ground.

10.1.3 Decoupling of Power Supplies

Place the decoupling capacitors on AVDD and DVDD within 20 mil from the respective pins, and use a 15-mil via

to ground from each capacitor. Avoid placing vias between any supply pin and the respective decoupling

capacitor.

10.1.4 Reference Decoupling

Dynamic currents are present at the REFP_x and REFM_x pins during the conversion phase, and excellent

decoupling is required to achieve optimum performance. Place a 10-µF, X7R-grade, ceramic capacitor with at

least a 10-V rating, as illustrated in 图 84. Select 0603- or 0805-size capacitors to keep equivalent series

inductance (ESL) low. Connect the REFM_x pins to the decoupling capacitor before a ground via. Also place

decoupling capacitors on the REFOUT and REFby2 pins.

10.1.5 Differential Input Decoupling

Dynamic currents are also present at the differential analog inputs of the ADS92x4R. Use C0G- or NPO-type

capacitors to decouple these inputs because with these type of capacitors, capacitance stays almost constant

over the full input voltage range. Lower-quality capacitors (such as X5R and X7R) have large capacitance

changes over the full input-voltage range that may cause degradation in the performance of the device.

54

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ADS9234R

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ZHCSIJ5C –AUGUST 2018–REVISED JUNE 2019

10.2 Layout Example

C_{FLT_A_1}

R_{FLT_A_1}

C_{DIFF_A}

C_{REFP_A}

R_{FLT_A_2}

C_AVDD

C_DVDD

C_{FLT_A_2}

32

25

24

1

C_REFby2

ADS92x4

C_REFOUT

17

16

8

9

C_{FLT_B_2}

C_{REFP_B}

C_AVDD

R_{FLT_B_2}

R_{FLT_B_1}

C_{FLT_B_1}

C_{DIFF_B}

NOTE: Dimensions are in cm.

图 84. Example Layout for the ADS92x4R

55

ADS9224R

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ZHCSIJ5C –AUGUST 2018–REVISED JUNE 2019

www.ti.com.cn

11 器件和文档支持

11.1 器件支持

11.1.1 开发支持

TI 高精度 ADC 实验室

11.2 相关文档

请参阅如下相关文档：

•

德州仪器 (TI)，《THS4551 低噪声、高精度的 150MHz 全差分放大器》数据表

德州仪器 (TI)，《在电机控制应用中用于光学编码器的 12 位 1MSPS 单电源双通道数据采集系统》参考指南

德州仪器 (TI)，《REF50xx 低噪声、极低漂移、精密电压基准》数据表

德州仪器 (TI)，《OPAx350 高速单电源轨至轨运算放大器 MicroAmplifier 系列》数据表

德州仪器 (TI)，《THS452x 极低功耗、负轨输入、轨至轨输出、全差分放大器》数据表

德州仪器 (TI)，《ADS9224REVM-PDK 用户指南》

11.3 相关链接

下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。

表 21. 相关链接

器件

产品文件夹

单击此处

立即订购

单击此处

技术文档

单击此处

工具与软件

单击此处

支持和社区

单击此处

ADS9224R

ADS9234R

11.4 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.5 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.6 商标

TINA-TI, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.7 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.8 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

56

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ZHCSIJ5C –AUGUST 2018–REVISED JUNE 2019

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

57

GENERIC PACKAGE VIEW

RHB 32

5 x 5, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224745/A

www.ti.com

PACKAGE OUTLINE

RHB0032E

VQFN - 1 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

B

A

PIN 1 INDEX AREA

(0.1)

5.1

4.9

SIDE WALL DETAIL

20.000

OPTIONAL METAL THICKNESS

C

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 3.5

(0.2) TYP

3.45 0.1

9

EXPOSED

THERMAL PAD

16

28X 0.5

8

17

SEE SIDE WALL

DETAIL

2X

SYMM

33

3.5

0.3

0.2

32X

24

0.1

C A B

C

1

0.05

32

25

PIN 1 ID

(OPTIONAL)

SYMM

0.5

0.3

32X

4223442/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RHB0032E

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

3.45)

SYMM

32

25

32X (0.6)

1

24

32X (0.25)

(1.475)

28X (0.5)

33

SYMM

(4.8)

(

0.2) TYP

VIA

8

17

(R0.05)

TYP

9

16

(1.475)

(4.8)

LAND PATTERN EXAMPLE

SCALE:18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4223442/B 08/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RHB0032E

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.49)

(0.845)

(R0.05) TYP

32

25

32X (0.6)

1

24

32X (0.25)

28X (0.5)

(0.845)

SYMM

33

(4.8)

17

8

METAL

TYP

16

9

SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4223442/B 08/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

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这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	ADS9234R
厂家：	TEXAS INSTRUMENTS
描述：	具有内部基准电压和增强型 SPI 的 14 位、3.5MSPS、双路、同步采样 SAR ADC
文件：	总64页 (文件大小：2669K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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