ADS930_14 [TI]
8-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER;
| 型号： | ADS930_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总15页 (文件大小：421K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS930
ADS930E
SBAS059A – MARCH 2001
8-Bit, 30MHz Sampling
TM
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
● +3V TO +5V SUPPLY OPERATION
● INTERNAL REFERENCE
● SINGLE-ENDED INPUT RANGE: 1V to 2V
● LOW POWER: 66mW at +3V
● HIGH SNR: 46dB
The ADS930 is a high speed pipelined Analog-to-Digital
Converter (ADC) specified to operate from nominal +3V or
+5V power supplies with tolerances of up to 10%. This
complete converter includes a high bandwidth track/hold, a
8-bit quantizer and an internal reference.
The ADS930 employs digital error correction techniques to
provide excellent differential linearity for demanding im-
aging applications. Its low distortion and high SNR give the
extra margin needed for telecommunications, video and
test instrumentation applications.
● LOW DNL: 0.4LSB
● SSOP-28 PACKAGE
APPLICATIONS
● BATTERY POWERED EQUIPMENT
This high performance ADC is specified for performance at
a 30MHz sampling rate. The ADS930 is available in a
SSOP-28 package.
● CAMCORDERS
● PORTABLE TEST EQUIPMENT
● COMPUTER SCANNERS
● COMMUNICATIONS
CLK
LVDD
ADS930
Timing
Circuitry
2V
IN
8-Bit
Digital
Data
Error
Correction
3-State
Outputs
Pipeline
A/D
1V
T/H
IN
(Opt.)
Internal
Reference
LpBy CM LnBy
1VREF Pwrdn
OE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2001, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
mentsrecommendsthatallintegratedcircuitsbehandledwith
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
+VS ....................................................................................................... +6V
Analog Input ............................................................................... +VS +0.3V
Logic Input .................................................................................+VS +0.3V
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +150°C
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
PRODUCT
PACKAGE
ADS930E
SSOP-28
324
–40°C to +85°C
ADS930E
ADS930E
ADS930E
Rails
"
"
"
"
ADS930E/1K
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of “ADS930E/1K” will get a single 1000-piece Tape and Reel.
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VS = +3V, Single-ended Input and Sampling Rate = 30MHz, unless otherwise specified.
ADS930E
PARAMETER
CONDITIONS
TEMP
MIN
TYP
MAX
UNITS
RESOLUTION
8
Bits
Specified Temperature Range
Ambient Air
–40
+85
°C
ANALOG INPUT
Differential Full Scale Input Range
Single-Ended Full Scale Input Range
Common-mode Voltage
Analog Input Bias Current
Input Impedance
0.5Vp-p
1Vp-p
+1.25
+1.0
+1.75
+2.0
V
V
V
1.5
1
1.25 || 5
µA
MΩ || pF
DIGITAL INPUTS
Logic Family
Full
TTL/HCT Compatible CMOS
2.0 VDD
0.8
High Input Voltage, VIH
Low Input Voltage, VIL
High Input Current, IIH
Low Input Current, IIL
Input Capacitance
V
V
µA
µA
pF
±10
±10
5
CONVERSION CHARACTERISTICS
Start Conversion
Sample Rate
Rising Edge of Convert Clock
10k 30M
Full
Samples/s
Clk Cyc
Data Latency
5
DYNAMIC CHARACTERISTICS
Differential Linearity Error
f = 500kHz
f = 12MHz
No Missing Codes
Largest Code Error
Largest Code Error
Full
Full
Full
±0.4
±0.4
Guaranteed
±1
LSB
LSB
Integral Nonlinearity Error, f = 500kHz
Spurious Free Dynamic Range(1)
f = 500kHz (–1dBFS input)
Full
±1.0
±2.5
LSB
Full
Full
51
50
dBFS(2)
dBFS
f = 12MHz (–1dB input)
46
Two-Tone Intermodulation Distortion(3)
f = 3.4MHz and 3.5MHz (–7dBFS each tone)
Signal-to-Noise Ratio (SNR)
54
dBc
f = 500kHz (–1dBFS input)
f = 12MHz (–1dBFS input)
Full
Full
46
46
dB
dB
44
42
Signal-to-(Noise + Distortion) (SINAD)
f = 500kHz (–1dBFS input)
f = 3.58MHz (–1dBFS input)
f = 12MHz (–1dBFS input)
Full
Full
Full
45
45
45
dB
dB
dB
ADS930
2
SBAS059A
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +3V, Single-ended Input and Sampling Rate = 30MHz, unless otherwise specified.
ADS930E
TYP
PARAMETER
CONDITIONS
TEMP
MIN
MAX
UNITS
Differential Gain Error
Differential Phase Error
Output Noise
Aperture Delay Time
Aperture Jitter
NTSC, PAL
NTSC, PAL
Input Grounded
2.3
1
0.2
2
%
degrees
LSBs rms
ns
7
ps rms
Analog Input Bandwidth
Small Signal
Full Power
Overvoltage Recovery Time(4)
–20dBFS Input
0dBFS Input
350
100
2
MHz
MHz
ns
DIGITAL OUTPUTS
Logic Family
Logic Coding
CL = 15pF
TTL/HCT Compatible CMOS
Straight Offset Binary
High Output Voltage, VOH
Low Output Voltage, VOL
3-State Enable Time
3-State Disable Time
Internal Pull-Down
Power-Down Enable Time
Power-Down Disable Time
Internal Pull-Down
+2.4
LVDD
V
V
0.4
40
10
OE = L
OE = H
20
2
50
133
18
50
ns
ns
kΩ
ns
ns
kΩ
PwrDn = L
PwrDn = H
ACCURACY
fS = 2.5MHz
Gain Error
Input Offset
Power Supply Rejection (Gain)
Power Supply Rejection (Offset)
Internal Positive Reference Voltage
Internal Negative Reference Voltage
Full
Full
Full
Full
Full
Full
5.9
±10
56
56
+1.75
+1.25
10
±60
%FS
mV
dB
dB
V
Referred to Ideal Midscale
∆ VS = +10%
V
POWER SUPPLY REQUIREMENTS
Supply Voltage: +VS
Supply Current: +IS
Operating
Full
Full
Full
Full
Full
Full
+2.7
+3.0
22
66
168
10
15
+5.25
84
V
Operating, +3V
Operating, +3V
Operating, +5V
Operating, +3V
Operating, +5V
mA
mW
mW
mW
mW
Power Dissipation
Power Dissipation (Power Down)
Thermal Resistance, θJA
SSOP-28
89
°C/W
NOTES: (1) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to full scale. (3) Two-tone intermodulation
distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental envelope. (4) No
“Rollover” of bits.
ADS930
SBAS059A
3
PIN CONFIGURATION
PIN DESCRIPTIONS
PIN
DESIGNATOR
DESCRIPTION
Top View
SSOP
1
+VS
LVDD
NC
Analog Supply
2
Output Logic Driver Supply Voltage
No Connection
3
4
NC
No Connection
+VS
LVDD
NC
1
2
3
4
5
6
7
8
9
28 +VS
27 +IN
26 CM
25 LnBy
24 IN
5
Bit 8 (LSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1(MSB)
GND
GND
CLK
Data Bit 8 (D7)
6
Data Bit 7 (D6)
7
Data Bit 6 (D5)
8
Data Bit 5 (D4)
NC
9
Data Bit 4 (D3)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Data Bit 3 (D2)
LSB Bit 8
Bit 7
Data Bit 2 (D1)
Data Bit 1 (D0)
23 1VREF
22 NC
Analog Ground
Bit 6
Analog Ground
ADS930
Convert Clock Input
Output Enable, Active Low
Power Down Pin
Analog Supply
Bit 5
21 LpBy
20 GND
19 GND
18 +VS
17 Pwrdn
16 OE
OE
Bit 4
Pwrdn
+VS
Bit 3 10
Bit 2 11
GND
GND
LpBy
NC
Analog Ground
Analog Ground
Positive Ladder Bypass
No Connection
MSB Bit 1 12
GND 13
1VREF
IN
1V Reference Output
Complementary Input
Negative Ladder Bypass
Common-Mode Voltage Output
Analog Input
GND 14
15 CLK
LnBy
CM
+IN
+VS
Analog Supply
TIMING DIAGRAM
N+2
N+1
N+4
N+3
Analog In
N+7
N+5
N
N+6
tL
tH
tD
tCONV
Clock
5 Clock Cycles
t2
Data Out
N–5
N–4
N–3
N–2
N–1
N
N+1
N+2
Data Invalid
t1
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tCONV
tL
tH
tD
t1
Convert Clock Period
Clock Pulse Low
Clock Pulse High
Aperture Delay
33
15.5
15.5
100µs
ns
ns
ns
ns
ns
ns
16.5
16.5
2
Data Hold Time, CL = 0pF
New Data Delay Time, CL = 15pF max
3.9
t2
12
ADS930
4
SBAS059A
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = +3V, Single-ended Input and Sampling Rate = 30MHz, unless otherwise specified.
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
fIN = 3.58MHz
0
–20
0
–20
fIN = 500kHz
–40
–40
–60
–60
–80
–80
–100
–100
0
5
10
Frequency (MHz)
15
0
0
0
5
10
Frequency (MHz)
15
SPECTRAL PERFORMANCE
fIN = 12MHz
TWO-TONE INTERMODULATION
0
–20
0
–20
f1 = 3.5MHz at –7dBFS
f2 = 3.4MHz at –7dBFS
2f1 –f2 = 54.7dBFS
2f2 –f1 = 54.2dBFS
–40
–40
–60
–60
–80
–80
–100
–100
5
10
Frequency (MHz)
15
0
2
4
6
8
10
Frequency (MHz)
DIFFERENTIAL LINEARITY ERROR
fIN = 500kHz
DIFFERENTIAL LINEARITY ERROR
fIN = 12MHz
2.0
1.0
2.0
1.0
0.0
0.0
–1.0
–2.0
–1.0
–2.0
64
128
192
256
0
64
128
192
256
Output Code
Output Code
ADS930
SBAS059A
5
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +3V, Single-ended Input and Sampling Rate = 30MHz, unless otherwise specified.
INTEGRAL LINEARITY ERROR
SWEPT POWER SFDR
dBFS
4.0
2.0
100
80
60
40
20
0
fIN = 500kHz
0
–2.0
–4.0
dBc
0
64
128
192
256
–50
–40
–30
–20
–10
0
Output Code
Input Amplitude (dBFS)
UNDERSAMPLING (With Differential Input)
fIN = 20MHz
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
0
–20
52
50
48
46
f
S = 16MHz
SFDR
–40
–60
–80
SNR
–100
–120
0
1.6
3.2
4.8
6.4
8.0
0.1
1
10
Frequency (MHz)
100
Frequency (MHz)
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
SPURIOUS FREE DYNAMIC RANGE
vs TEMPERATURE
0.7
0.6
0.5
0.4
0.3
0.2
54
52
50
48
46
fIN = 500kHz
fIN = 12MHz
fIN = 500kHz
f
IN = 10MHz
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
ADS930
6
SBAS059A
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +3V, Single-ended Input and Sampling Rate = 30MHz, unless otherwise specified.
SIGNAL-TO-NOISE RATIO vs TEMPERATURE
POWER DISSIPATION vs TEMPERATURE
48
47
46
45
44
69
68
67
66
65
fIN = 12MHz
fIN = 500kHz
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
GAIN ERROR vs TEMPERATURE
OFFSET ERROR vs TEMPERATURE
6.5
6.0
5.5
5.0
4.5
7
6
5
4
3
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
OUTPUT NOISE HISTOGRAM (DC Input)
12
10
8
6
4
2
0
N–2
N–1
N
N+1
N+2
Output Code
ADS930
SBAS059A
7
THEORY OF OPERATION
Op Amp
Bias
VCM
The ADS930 is a high speed sampling ADC that utilizes a
pipeline architecture. The fully differential topology and
digital error correction guarantee 8-bit resolution. The track/
hold circuit is shown in Figure 1. The switches are con-
trolled by an internal clock which has a non-overlapping two
phase signal, φ1 and φ2. At the sampling time the input
signal is sampled on the bottom plates of the input capaci-
tors. In the next clock phase, φ2, the bottom plates of the
input capacitors are connected together and the feedback
capacitors are switched to the op amp output. At this time the
charge redistributes between CI and CH, completing one
track/hold cycle. The differential output is a held DC repre-
sentation of the analog input at the sample time. In the
normal mode of operation, the complementary input is tied
to the common-mode voltage. In this case, the track/hold
circuit converts a single-ended input signal into a fully
differential signal for the quantizer. Consequently, the input
signal gets amplified by a gain or two, which improves the
signal-to-noise performance. Other parameters such as small-
signal and full-power bandwidth, and wideband noise are
also defined in this stage.
φ
1
φ1
CH
φ
2
CI
CI
IN
OUT
OUT
φ
1
φ2
φ1
IN
φ1
(Opt.)
φ2
CH
φ1
φ1
Input Clock (50%)
Op Amp
Bias
VCM
Internal Non-overlapping Clock
φ1
φ
2
φ1
FIGURE 1. Input Track/Hold Configuration with Timing
Signals.
IN
Input
T/H
Digital Delay
IN
(Opt.)
2-Bit
Flash
2-Bit
DAC
+
STAGE 1
–
Σ
x2
Digital Delay
2-Bit
Flash
2-Bit
DAC
B1 (MSB)
STAGE 2
+
B2
B3
B4
B5
B6
B7
–
Σ
x2
B8 (LSB)
Digital Delay
2-Bit
Flash
2-Bit
DAC
STAGE 6
+
–
Σ
x2
2-Bit
Flash
Digital Delay
STAGE 7
FIGURE 2. Pipeline ADC Architecture.
ADS930
8
SBAS059A
The pipelined quantizer architecture has 7 stages with each
stage containing a two-bit quantizer and a two bit Digital-
to-Analog Converter (DAC), as shown in Figure 2. Each
two-bit quantizer stage converts on the edge of the sub-
clock, which is the same frequency of the externally applied
clock. The output of each quantizer is fed into its own delay
line to time-align it with the data created from the subse-
quent quantizer stages. This aligned data is fed into a digital
error correction circuit which can adjust the output data
based on the information found on the redundant bits. This
technique provides the ADS930 with excellent differential
linearity and guarantees no missing codes at the 8-bit level.
signal. The capacitor C1 and resistor R1 form a high-pass
filter with the –3dB frequency set at
f–3dB = 1/(2 π R1 C1)
(2)
The values for C1 and R1 are not critical in most applications
and can be set freely. The values shown in Figure 3 corre-
spond to a corner frequency of 1.6kHz.
Figure 4 depicts a circuit that can be used in single-supply
applications. The mid-reference biases the op amp up to the
appropriate common-mode voltage, for example VCM
=
+1.5V. With the use of capacitor CG, the DC gain for the
non-inverting op amp input is set to +1V/V. As a result, the
transfer function is modified to
The ADS930 includes an internal reference circuit that
provides the bias voltages for the internal stages (for details
see “Internal Reference”). A midpoint voltage is established
by the built-in resistor ladder which is made available at pin
26 “CM”. This voltage can be used to bias the inputs up to
the recommended common-mode voltage or to level shift
the input driving circuitry. The ADS930 can be used in both
a single-ended or differential input configuration. When
operated in single-ended mode, the reference midpoint (pin
26) should be tied to the inverting input, pin 24.
VOUT = VIN {(1 + RF/RG) + VCM
}
(3)
Again, the input coupling capacitor C1 and resistor R1 form
a high-pass filter. At the same time, the input impedance is
defined by R1. Resistor RS isolates the op amp’s output from
the capacitive load to avoid gain peaking or even oscillation.
It can also be used to establish a defined bandwidth to reduce
the wideband noise. Its value is usually between 10Ω and
100Ω.
To accommodate a bipolar signal swing, the ADS930 oper-
ates with a common-mode voltage (VCM) which is derived
from the internal references. Due to the symmetric resistor
ladder inside the ADS930, VCM is situated between the top
and bottom reference voltage. The following equation can
be used for calculating the common-mode voltage level:
+3V
+5V
C1
0.1µF
VIN
10Ω
OPA650
OPA658
IN
IN
ADS930
VCM = (REFT +REFB)/2
(1)
CM
R1
1kΩ
–5V
402Ω
APPLICATIONS
VCM
0.1µF
DRIVING THE ANALOG INPUTS
402Ω
Figure 3 shows an example of an ac-coupled, single-ended
interface circuit using high-speed op amps which operate on
dual supplies (OPA650, OPA658). The mid-point reference
voltage, (VCM), biases the bipolar, ground-referenced input
FIGURE 3. AC-Coupled Driver.
+3V
+5V
C1
0.1µF
RS
VIN
50Ω
IN
OPA680
ADS930
R1
1kΩ
22pF
VCM
IN
CM
RF
402Ω
0.1µF
RG
402Ω
RP
402Ω
CG
0.1µF
FIGURE 4. Interface Circuit Example Using the Voltage Feedback Amplifier OPA680.
ADS930
SBAS059A
9
DC-COUPLED INTERFACE CIRCUIT
Figure 6, each end of the resistor ladder (REFT and REFB)
are driven by a buffer amplifier. The ladder has a nominal
resistance of 4kΩ (±15%). The two outputs of the buffers are
brought out at pin 21 (LpBy) and pin 25 (LnBy), primarily
to connect external bypass capacitors, typically 0.1µF. They
will shunt the high frequency switching noise that is fed
back into the reference circuit and improve the performance.
The buffers can drive limited external loads, for example
level-shifting of the converter’s interface circuit. However,
the current draw should be limited to approximately 1mA.
Figure 5 illustrates an example of a DC-coupled interface
circuit using one high-speed op amp to level-shift the ground-
referenced input signal. This serves to condition it for the
input requirements of the ADS930. With a +3V supply the
input signal swings 1Vp-p centered around a typical com-
mon-mode voltage of +1.5V. This voltage can be derived
from the internal bottom reference (REFB) and then fed
back through a resistor divider (R1, R2) to level-shift the
driving op amp (A1). A capacitor across R2 will shunt most
of the wideband noise to ground. Depending on the config-
ured gain, the values of resistors R1 and R2 must be adjusted
since the offsetting voltage (VOS) is amplified by the non-
inverting gain, 1 + (RF/RIN). This example assumes the sum
of R1 and R2 to be 5kΩ, drawing only 250µA from the
bottom reference. Considerations for the selection of a
proper op amp should include its output swing, input com-
mon-mode range, and bias current. This circuit can easily be
modified for a +5V operation of the ADC, requiring a higher
common-mode level (+2.5V).
Derived from the top reference of +1.75V is an additional
voltage of +1.0V. Note that this voltage, available on pin 23,
is not buffered and care should be taken when external loads
are applied. In normal operation, this pin is left unconnected
and no bypassing components are required.
CLOCK INPUT
The clock input of the ADS930 is designed to accommodate
either +5V or +3V CMOS logic levels. To drive the clock
input with a minimum amount of duty cycle variation and
support the maximum sampling rate (30MSPS), high speed
or advanced CMOS logic should be used (HC/HCT,
AC/ACT). When digitizing at high sampling rates, a 50%
duty cycle, along with fast rise and fall times (2ns or less),
INTERNAL REFERENCE
The ADS930 features an internal reference that provides
fixed reference voltages for the internal stages. As shown in
+5V
RF
+3V
VCM = 1.5V
RIN
RS
VIN
ADS930
IN
OPA680
REFB
+1.25V
22pF
IN
CM
VOS
0.1µF
0.1µF
R2
R1
0.1µF
I = 250µA
FIGURE 5. Single-supply, DC-coupled Interface Circuit.
ADS930
+1.75V
REFT
21
23
LpBy
0.1µF
2.1kΩ
2.8kΩ
2kΩ
2kΩ
26
+1VREF
CM
0.1µF
+1.25V
REFB
25
LnBy
0.1µF
FIGURE 6. Internal Reference Structure and Recommended Reference Bypassing.
10
ADS930
SBAS059A
are recommended to meet the rated performance specifica-
tions. However, the ADS930 performance is tolerant to duty
cycle variations of as much as ±10%, which should not
affect the performance. For applications operating with
input frequencies up to Nyquist (fCLK/2) or undersampling
applications, special considerations must be made to provide
a clock with very low jitter. Clock jitter leads to aperture
jitter (tA) which can be the ultimate limitation in achieving
good SNR performance. The following equation shows the
relationship between aperture jitter, input frequency and the
signal-to-noise ratio:
LVDD, the digital output levels will vary respectively. It is
recommended to limit the fan-out to one in order to keep the
capacitive loading on the data lines below the specified
15pF. If necessary, external buffers or latches may be used
to provide the added benefit of isolating the ADC from any
digital activities on the bus coupling back high frequency
noise which degrades the performance.
POWER-DOWN MODE
The ADS930’s low power consumption can be reduced even
further by initiating a power-down mode. For this, the Power
Down Pin (Pin 17) must be tied to a logic “High” reducing
the current drawn from the supply by approximately 70%. In
normal operation, the power-down mode is disabled by an
internal pull-down resistor (50kΩ).
SNR = 20log10 [1/(2 π fIN tA)]
(4)
STRAIGHT OFFSET BINARY
(SOB)
PIN 12
FLOATING or LO
SINGLE-ENDED INPUT
(IN = 1.5V DC)
During power-down, the digital outputs are set in 3-state.
With the clock applied, the converter does not accurately
process the sampled signal. After removing the power-down
condition, the output data from the following 5 clock cycles
is invalid (data latency).
+FS (IN = +2V)
+FS –1LSB
+FS –2LSB
+3/4 Full Scale
+1/2 Full Scale
+1/4 Full Scale
+1LSB
Bipolar Zero (IN +1.5V)
–1LSB
–1/4 Full Scale
–1/2 Full Scale
–3/4 Full Scale
–FS +1LSB
11111111
11111111
11111110
11100000
11000000
10100000
10000001
10000000
01111111
01100000
01000000
00100000
00000001
00000000
DECOUPLING AND GROUNDING
CONSIDERATIONS
The ADS930 has several supply pins, one of which is
dedicated to supply only the output driver (LVDD). The
remaining supply pins are not divided into analog and digital
supply pins since they are internally connected on the chip.
For this reason, it is recommended that the converter be
treated as an analog component and to power it from the
analog supply only. Digital supply lines often carry high
levels of noise which can couple back into the converter and
limit performance.
–FS (IN = +1V)
TABLE I. Coding Table for the ADS930.
DIGITAL OUTPUTS
There is a 5.0 clock cycle data latency from the start convert
signal to the valid output data. The standard output coding
is Straight Offset Binary where a full scale input signal
corresponds to all “1’s” at the output. The digital outputs of
the ADS930 can be set to a high impedance state by driving
the OE (pin 16) with a logic “HI”. Normal operation is
achieved with pin 16 “LO” or Floating due to internal pull-
down resistors. This function is provided for testability
purposes but is not recommended to be used dynamically.
Because of the pipeline architecture, the converter also
generates high frequency transients and noise that are fed
back into the supply and reference lines. This requires that
the supply and reference pins be sufficiently bypassed.
Figure 8 shows the recommended decoupling scheme for the
analog supplies. In most cases 0.1µF ceramic chip capacitors
are adequate to keep the impedance low over a wide fre-
quency range. Their effectiveness largely depends on the
proximity to the individual supply pin. Therefore, they
should be located as close as possible to the supply pins.
The digital outputs of the ADS930 are standard CMOS
stages and designed to be compatible to both high speed
TTL and CMOS logic families. The logic thresholds are for
low-voltage CMOS: VOL = 0.4V, VOH = 2.4V, which allows
the ADS930 to directly interface to 3V-logic. The digital
output driver of the ADS930 uses a dedicated digital supply
pin (pin 2, LVDD) see Figure 7. By adjusting the voltage on
ADS930
VS
1
GND
13 14
VS
18
GND
19 20
VS
28
+VS
+LVDD
0.1µF
0.1µF
0.1µF
Digital
Output
Stage
ADS930
FIGURE 8. Recommended Bypassing for Analog Supply
Pins.
FIGURE 7. Independent Supply Connection for Output
Stage.
ADS930
SBAS059A
11
PACKAGE OPTION ADDENDUM
www.ti.com
28-Mar-2008
PACKAGING INFORMATION
Orderable Device
ADS930E
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DB
28
28
28
28
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
ADS930E/1K
ADS930E/1KG4
ADS930EG4
SSOP
SSOP
SSOP
DB
DB
DB
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
ADS930E/1K
SSOP
DB
28
1000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SSOP DB 28
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
ADS930E/1K
1000
Pack Materials-Page 2
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