ADS9817 [TI]
具有集成模拟前端的八通道、18 位、2MSPS/通道、双路同步采样 ADC;
| 型号： | ADS9817 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成模拟前端的八通道、18 位、2MSPS/通道、双路同步采样 ADC |
| 文件： | 总53页 (文件大小：2061K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS9817, ADS9815
ZHCSM18 –JULY 2021 –REVISED JANUARY 2023
ADS981x 具有集成模拟前端的18 位8MSPS 双路
同步采样ADC
1 特性
2 应用
• 具有模拟前端的8 通道18 位ADC：
• 半导体测试
• 电池测试
• 数据采集(DAQ)
– 双路同步采样：4 × 1 个通道
– 恒定的1MΩ输入阻抗前端
• 可编程的低通滤波器带宽：
– 21kHz 和400kHz
• 可编程输入范围：
– ±12V、±10V、±7V、±5V、±3.5V 和±2.5V
– 单端和差动输入
• 输入过压保护：高达±18 V
• 集成低漂移4.096V 精密基准
• 出色的性能：
3 说明
ADS981x 是基于双路同步采样 18 位逐次逼近寄存器
(SAR) 模数转换器 (ADC) 的八通道数据采集 (DAQ) 系
统。ADS981x 的每个通道都具有一个完整的模拟前
端，其中包含输入钳位、1MΩ 输入阻抗、独立的可编
程增益放大器 (PGA)、可编程低通滤波器和 ADC 输入
驱动器。该器件还具有一个低漂移高精度电压基准以及
一个用于驱动 ADC 的缓冲器。凭借支持 1.2V 至 1.8V
操作的高速数字接口，ADS981x 可用于各种主机控制
器。
– DNL：±0.3 LSB，INL：±1.5 LSB
– SNR：92.2 dB，THD：–112 dB
• 电源：
ADS981x 可以配置为接受 ±12V、±10V、±7V、±5V、
±3.5V 和 ±2.5V 双极输入。高输入阻抗允许与传感器
和变压器直接连接，从而无需使用外部驱动器电路。
ADS981x 能够实现高性能、高精度以及零延迟转换，
是多种工业应用的理想之选。
– 模拟和数字：5 V 和1.8 V
– 数字接口：1.2V 至1.8V
• 温度范围：–40°C 至+125°C
AVDD_1V8
DVDD_1V8
AVDD_5V
2.5 V
REFOUT_2V5
1 Mꢀ
封装信息
封装(1)
OVP
OVP
AIN1P
AIN1M
ADC
Driver
Prog. LPF
PGA
PGA
PGA
PGA
PGA
PGA
PGA
PGA
封装尺寸（标称值）
器件型号
ADS981x
1 Mꢀ
1 Mꢀ
4.096 V
VREF
REFIO
REFM
VB0
RSH（VQFN，56） 7.00mm × 7.00mm
OVP
OVP
AIN2P
AIN2M
ADC REF
ADC
Driver
Prog. LPF
Prog. LPF
Prog. LPF
Prog. LPF
Prog. LPF
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
18-Bit, 8-MSPS
SAR ADC
ADC A
1 Mꢀ
1 Mꢀ
VB1
VB2
VB3
VB4
VB5
VB6
VB7
OVP
OVP
AIN3P
AIN3M
IOVDD
RESET
ADC
Driver
器件信息
SPEED
1 Mꢀ
1 Mꢀ
器件型号
ADS9817
ADS9815
总功耗
232 mW
160 mW
PWDN
2Msp/通道
SMPL_CLK
OVP
OVP
AIN4P
AIN4M
ADC
Driver
SMPL_SYNC
DCLKOUT
1MSPS/通道
1 Mꢀ
1 Mꢀ
Digital logic
and
Data Interface
ADC REF
FCLKOUT
D0
OVP
OVP
AIN5P
AIN5M
ADC
Driver
D1
D2
D3
1 Mꢀ
1 Mꢀ
OVP
OVP
AIN6P
AIN6M
ADC
Driver
1 Mꢀ
1 Mꢀ
18-Bit, 8-MSPS
SAR ADC
ADC B
OVP
OVP
AIN7P
AIN7M
ADC
Driver
Prog. LPF
1 Mꢀ
1 Mꢀ
SPI_EN
CS / EXTREF
SCLK
Con gura on
Registers
AIN8P
AIN8M
OVP
OVP
ADC
Driver
Prog. LPF
SDI
1 Mꢀ
SDO
GND
器件框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBASA81
ADS9817, ADS9815
ZHCSM18 –JULY 2021 –REVISED JANUARY 2023
www.ti.com.cn
Table of Contents
7.2 Functional Block Diagram.........................................14
7.3 Feature Description...................................................15
7.4 Programming............................................................ 22
7.5 Register Map.............................................................26
8 Application and Implementation..................................46
8.1 Application Information............................................. 46
8.2 Typical Application.................................................... 46
8.3 Power Supply Recommendations.............................47
8.4 Layout....................................................................... 48
9 Device and Documentation Support............................50
9.1 接收文档更新通知..................................................... 50
9.2 支持资源....................................................................50
9.3 Trademarks...............................................................50
9.4 静电放电警告............................................................ 50
9.5 术语表....................................................................... 50
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................7
6.6 Timing Requirements..................................................9
6.7 Switching Characteristics..........................................10
6.8 Timing Diagrams.......................................................10
6.9 Typical Characteristics..............................................13
7 Detailed Description......................................................14
7.1 Overview...................................................................14
Information.................................................................... 50
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
January 2023
*
Initial Release
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5 Pin Configuration and Functions
42
AIN2P
AIN2M
AIN3P
AIN3M
1
2
3
4
5
6
7
8
IOGND
IOVDD
FCLKOUT
NC
41
40
39
38
37
36
35
AIN4P
AIN4M
GND
NC
D3
D2
D1
Thermal
Pad
REFM
AIN5P
34
33
32
31
30
29
D0
9
AIN5M
AIN6P
10
11
12
13
14
DCLKOUT
PWDN
RESET
AIN6M
AIN7P
AIN7M
IOVDD
IOGND
Not to scale
图5-1. RSH Package, 56-Pin VQFN (Top View)
表5-1. Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
AIN1M
NO.
55
54
2
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
P
Analog input channel 1, negative input.
Analog input channel 1, positive input.
Analog input channel 2, negative input.
Analog input channel 2, positive input.
Analog input channel 3, negative input.
Analog input channel 3, positive input.
Analog input channel 4, negative input.
Analog input channel 4, positive input.
Analog input channel 5, negative input.
Analog input channel 5, positive input.
Analog input channel 6, negative input.
Analog input channel 6, positive input.
Analog input channel 7, negative input.
Analog input channel 7, positive input.
Analog input channel 8, negative input.
Analog input channel 8, positive input.
AIN1P
AIN2M
AIN2P
AIN3M
AIN3P
AIN4M
AIN4P
AIN5M
AIN5P
AIN6M
AIN6P
AIN7M
AIN7P
AIN8M
AIN8P
AVDD_1V8
AVDD_5V
CS
1
4
3
6
5
10
9
12
11
14
13
17
16
21, 49
15, 56
1.8-V analog supply. Connect 1-µF and 0.1-µF decoupling capacitors to AGND.
5-V analog supply. Connect 1-µF and 0.1-µF decoupling capacitor to AGND.
P
Chip-select input for configuration of SPI interface; active low. This pin has an internal 100-
kΩ pullup resistor to the digital interface supply.
25
34
DI
D0
DO
Serial output data lane 0.
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表5-1. Pin Functions (continued)
PIN
I/O(1)
DESCRIPTION
NAME
NO.
35
D1
D2
D3
DO
DO
DO
DO
P
Serial data output lane 1.
36
Serial data output lane 2.
37
Serial data output lane 3.
DCLKOUT
DVDD_1V8
FCLKOUT
GND
33
Clock output for the data interface.
Digital supply pin. Connect 1-µF and 0.1-µF decoupling capacitors to DGND.
Frame synchronization output for data interface.
Ground.
22, 47, 48
40
DO
P
7, 23, 46
29, 42
IOGND
P
Digital interface ground. Connect to GND.
IOVDD
Digital I/O supply for the data interface. Connect 1-µF and 0.1-µF decoupling capacitors to
IOGND.
30, 41
P
NC
20, 38, 39, 50,
51
Not connected. No external connection.
—
PWDN
REFIO
Power-down control; active low. This pin has an internal 100-kΩ pullup resistor to the digital
32
52
DI
interface supply.
This pin acts as an internal reference output when the internal reference is enabled. This pin
AI/AO functions as an input pin for the external reference when internal reference is disabled.
Connect a 10-µF decoupling capacitor to the REFM pins.
REFM
8, 18, 53
19
AI
Reference ground potential. Connect to GND.
REFOUT_2V5
RESET
AO
2.5-V reference output. Connect a decoupling 10-µF capacitor to the REFM pins.
Reset input for the device; active low. This pin has an internal 100-kΩ pullup resistor to the
digital interface supply.
31
26
DI
DI
SCLK
SDI
Serial clock input for the configuration interface. This pin has an internal 100-kΩ pulldown
resistor to the digital interface ground.
This pin is a multifunction logic input; pin function is determined by the SPI_EN pin. This pin
has an internal 100-kΩ pulldown resistor to IOGND.
SPI_EN = 0b: This pin is the logic input to select between the internal or external reference.
Connect this pin to IOGND for the external reference. Connect this pin to IOVDD for the
internal reference.
27
DI
SPI_EN = 1b: Serial data input for the configuration interface.
SDO
28
44
DO
DI
Serial data output for the configuration interface.
SMPL_CLKP
Single-ended ADC sampling clock input. This pin is the positive input for the differential ADC
sampling clock.
SMPL_CLKM
Connect this pin to GND for a single-ended ADC sampling clock input. This pin is the
negative input for the differential ADC sampling clock.
43
45
DI
DI
Logic input to select analog input channel 1 for ADC A and analog input channel 8 for ADC
B.
SMPL_SYNC
SPI_EN
Logic input to enable the configuration SPI interface (CS, SCLK, SDI, and SDO). This pin
has internal 100-kΩ pullup resistor to the digital interface supply.
24
DI
P
Thermal pad
Exposed thermal pad; connect to AGND.
—
(1) I = input, O = output, I/O = input or output, G = ground, and P = power.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
UNIT
V
AVDD_5V to GND
6
AVDD_1V8 to GND
2.1
V
–0.3
DVDD_1V8 to GND
2.1
V
–0.3
IOVDD to GND
2.1
V
–0.3
AINxP and AINxM to GND
REFIO to REFM
18
AVDD_5V + 0.3
GND + 0.3
GND + 0.3
2.1
V
–18
V
REFM –0.3
GND –0.3
GND –0.3
IOGND –0.3
–10
REFM to GND
V
IOGND to GND
V
Digital inputs to IOGND
Input current to any pin except supply pins(2)
Junction temperature, TJ
Storage temperature, Tstg
V
10
mA
°C
°C
150
–40
150
–60
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Pin current must be limited to 10 mA or less.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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MAX UNIT
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
POWER SUPPLY
AVDD_5V
AVDD_1V8
DVDD_1V8
IOVDD
Analog power supply
Analog power supply
Digital power supply
AVDD_5V to GND, 5 V
AVDD_1V8 to GND, 1.8 V
DVDD_1V8 to GND, 1.8 V
IOVDD to IOGND
4.75
1.75
1.75
1.15
5
1.8
1.8
1.8
5.25
1.85
1.85
1.85
V
V
V
V
Digital interface power supply
REFERENCE VOLTAGE
VREF
Reference voltage to the ADC
External reference
4.092
4.096
4.100
V
ANALOG INPUTS
2.5
3.5
5
–2.5
–3.5
–5
VFSR
Full-scale input range
V
7
–7
10
12
–10
–12
Operating input voltage,
positive input
AINxP
AINxM
14
14
V
V
–14
–14
Operating input voltage,
negative input
TEMPERATURE RANGE
TA
Ambient temperature
25
125
°C
–40
6.4 Thermal Information
ADS9817
THERMAL METRIC(1)
RSH (VQFN)
56 PINS
23.2
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
10.5
6.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.1
ΨJT
6.0
ΨJB
RθJC(bot)
0.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at AVDD_5V = 4.75 V to 5.25 V, AVDD_1V8 = 1.75 V to 1.85 V, DVDD_1V8 = 1.75 V to 1.85 V, IOVDD = 1.15 V to 1.85 V,
VREF = 4.096 V (internal or external), and maximum throughput (unless otherwise noted); minimum and maximum values at
TA = -40°C to +125°C; typical values at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
RIN
Input impedance
Input range = ±5 V
0.85
1
10
10
1.15
MΩ
Input impedance thermal drift
Input capacitance
All input ranges
25 ppm/°C
pF
ANALOG INPUT FILTER
Low-noise filter, all input ranges
21
182
240
320
400
385
375
Wide-bandwidth filter, input range = ±2.5 V
Wide-bandwidth filter, input range = ±3.5 V
Wide-bandwidth filter, input range = ±5 V
Wide-bandwidth filter, input range = ±7 V
Wide-bandwidth filter, input range = ±10 V
Wide-bandwidth filter, input range = ±12 V
Analog input LPF bandwidth
–3 dB
BW(-3 dB)
kHz
DC PERFORMANCE
Resolution
No missing codes
TA = 0°C to 70°C
18
Bits
±0.3
±0.3
±1.5
±1.5
±0.5
±0.4
±0.5
±32
±32
1
0.5
–0.5
DNL
INL
Differential nonlinearity
LSB
TA = –40°C to 125°C
TA = 0°C to 70°C
2.5
–2.5
Integral nonlinearity
LSB
TA = –40°C to 125°C
Offset error
mV
mV
Offset error matching
Offset error thermal drift
ppm/°C
External reference, TA = 0°C to 70°C
50
–50
–80
Gain error
LSB
80
External reference, TA = –40°C to 125°C
Gain error thermal drift
External reference
ppm/°C
AC PERFORMANCE
Low-noise filter, fIN = 2 kHz, range = ±2.5 V
Low-noise filter, fIN = 2 kHz, range = ±3.5 V
89.3
90.6
91.5
91.5
91.9
92.2
82.8
89.3
90.6
91.5
91.5
91.9
92.2
82.8
–112
–111
111
Low-noise filter, fIN = 2 kHz, range = ±5 V
SNR
Signal-to-noise ratio
Low-noise filter, fIN = 2 kHz, range = ±7 V
dB
Low-noise filter, fIN = 2 kHz, range = ±10 V
Low-noise filter, fIN = 2 kHz, range = ±12 V
Wide-bandwidth filter, fIN = 2 kHz, all ranges
Low-noise filter, fIN = 2 kHz, range = ±2.5 V
Low-noise filter, fIN = 2 kHz, range = ±3.5 V
Low-noise filter, fIN = 2 kHz, range = ±5 V
SINAD
Signal-to-noise + distortion ratio Low-noise filter, fIN = 2 kHz, range = ±7 V
Low-noise filter, fIN = 2 kHz, range = ±10 V
dB
Low-noise filter, fIN = 2 kHz, range = ±12 V
Wide-bandwidth filter, fIN = 2 kHz, all ranges
Low-noise filter, fIN = 2 kHz, all ranges
Total harmonic distortion
THD
dB
dB
Wide-bandwidth filter, fIN = 2 kHz, all ranges
SFDR
Spurious-free dynamic range
fIN = 2 kHz
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6.5 Electrical Characteristics (continued)
at AVDD_5V = 4.75 V to 5.25 V, AVDD_1V8 = 1.75 V to 1.85 V, DVDD_1V8 = 1.75 V to 1.85 V, IOVDD = 1.15 V to 1.85 V,
VREF = 4.096 V (internal or external), and maximum throughput (unless otherwise noted); minimum and maximum values at
TA = -40°C to +125°C; typical values at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Isolation crosstalk
fIN = 10 kHz on unselected channel
dB
–92
INTERNAL REFERENCE
Voltage on REFIO pin
(1)
VREF
1-µF capacitor on REFIO pin, TA = 25°C
4.092
4.096
7
4.1
V
(configured as output)
Reference temperature drift
DIGITAL INPUTS
20 ppm/°C
VIL
VIH
Input low logic level
Input high logic level
Input current
0.3 IOVDD
V
V
–0.3
0.7 IOVDD
–1
IOVDD
1
0.1
6
µA
pF
Input capacitance
DIGITAL OUTPUTS
VOL
VOH
Output low logic level
Output high logic level
IOL = 500 µA sink
0
0.2 IOVDD
IOVDD
V
V
IOH = 500 µA source
0.8 IOVDD
POWER SUPPLY
Total power dissipation
Maximum throughput
232
26
44
6
mW
mA
mA
mA
mA
IAVDD_5V Supply current from AVDD_5V
IAVDD_1V8 Supply current from AVDD_1V8
IDVDD
Supply current from DVDD_1V8
Supply current from IOVDD
IIOVDD
7
(1) Does not include the variation in voltage resulting from solder shift effects.
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6.6 Timing Requirements
at AVDD_5V = 4.75 V to 5.25 V, AVDD_1V8 = 1.75 V to 1.85 V, DVDD_1V8 = 1.75 V to 1.85 V, IOVDD = 1.15 V to 1.85 V,
and maximum throughput (unless otherwise noted); minimum and maximum values at TA = -40°C to +125°C; typical values
at TA = 25°C.
MIN
MAX
UNIT
CONVERSION CYCLE
fSMPL_CLK
Sampling frequency
TBD
1 / fSMPL_CLK
0.4 tSMPL_CLK
0.4 tSMPL_CLK
10
8
MSPS
ns
tSMPL_CLK
Sampling time interval
tPL_SMPL_CLK
tPH_SMPL_CLK
tWH_SMPL_SYNC
tWL_SMPL_SYNC
SMPL_CLK low time
0.6 tSMPL_CLK
0.6 tSMPL_CLK
ns
SMPL_CLK high time
ns
Pulse duration: SMPL_SYNC low
Pulse duration: SMPL_SYNC high
ns
10
ns
SPI INTERFACE TIMINGS (CONFIGURATION INTERFACE)
fSCLK
Maximum SCLK frequency
20
0.52
0.52
MHz
tCLK
tCLK
ns
tPH_CK
tPL_CK
thi_CS
SCLK high time
0.48
0.48
220
20
SCLK low time
Pulse duration: CS high
td_CSCK
tsu_CKDI
tht_CKDI
tD_CKCS
Delay time: CS falling to the first SCLK capture edge
Setup time: SDI data valid to the SCLK rising edge
Hold time: SCLK rising edge to data valid on SDI
Delay time: last SCLK falling to CS rising
ns
10
ns
5
ns
5
ns
CMOS DATA INTERFACE
tsu_SS Setup time: SMPL_SYNC rising edge to SMPL_CLK falling edge
tht_SS Hold time: SMPL_CLK falling edge to SMPL_SYNC high
10
10
ns
ns
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6.7 Switching Characteristics
at AVDD_5V = 4.75 V to 5.25 V, AVDD_1V8 = 1.75 V to 1.85 V, DVDD_1V8 = 1.75 V to 1.85 V, IOVDD = 1.15 V to 1.85 V,
and maximum throughput (unless otherwise noted); minimum and maximum values at TA = -40°C to +125°C; typical values
at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
RESET
tPU
Power-up time for device
25
ms
SPI INTERFACE TIMINGS (CONFIGURATION INTERFACE)
Delay time: 8th SCLK rising-edge to data
tden_CKDO
enable
22
50
16
ns
ns
ns
ns
Delay time: 24th SCLK rising-edge to SDO
going Hi-Z
tdz_CKDO
Delay time: SCLK falling-edge to
td_CKDO
corresponding data valid on SDO
Delay time: SCLK falling-edge to previous
data valid on SDO
tht_CKDO
2
CMOS DATA INTERFACE
DDR mode
SDR mode
10
20
45
tDCLK
Data clock output
ns
Clock duty cycle
55
%
Time offset: DCLK rising to corresponding
data valid
toff_DCLKDO_r
toff_DCLKDO_f
td_DCLKDO
DDR mode
DDR mode
SDR mode
tDCLK/4 + 3
ns
tDCLK/4 –3
tDCLK/4 –3
–2
Time offset: DCLK falling to corresponding
data valid
tDCLK/4 + 3
2
ns
ns
Time delay: DCLK rising to corresponding
data valid
Time delay: SMPL_CLK falling edge with
SYNC signal to corresponding FCLKOUT
rising edge
td_SYNC_FCLK
3
4 tSMPL_CLK
6.8 Timing Diagrams
thi_CS
CS
td_CKCS
td_CSCK
SCLK
SDI
tsu_CKDI
tht_CKDI
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
D
D
D
D
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
15 14 13 12 11
tden_CKDO
td_CKDO
tht_SDO
tdz_CKDO
Hi-Z
DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO
15 14 13 12 11 10
SDO
9
8
7
6
5
4
3
2
1
0
SDO active only when reading registers; Hi-Z otherwise
图6-1. SPI Configuration Interface
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SMPL_SYNC
tht_SS
tsu_SS
SMPL_CLK
24 DCLKs
td_SYNC_FCLK
DCLKOUT
FCLKOUT
tFCLK
toff_DCLKDO_f
6 DCLK
toff_DCLKDO_r
D
D
D
D
13 11
D
D
9
D
1
D
D
D
D
13 11
D
D
9
D
1
D
D
D
D
13
D
9
D
1
D
D
D
D
13
D
9
D
1
D
D
D
D
13
D
9
D
11
D
11
D
11
D3
D2
23 21 19
23 21 19
23 21 19
23 21 19
23 21 19
Channel 4
Channel 1
Channel 2
Channel 3
Channel 1
D
D
D
D
12 10
D
D
8
D
0
D
D
D
D
12 10
D
D
8
D
0
D
D
D
D
12 10
D
D
8
D
0
D
D
D
D
12 10
D
D
8
D
0
D
D
D
D
12 10
D
D
8
22 20 18
22 20 18
22 20 18
22 20 18
22 20 18
D
D
D
D
13 11
D
D
9
D
1
D
D
D
D
13 11
D
D
9
D
1
D
D
D
D
13
D
9
D
1
D
D
D
D
13
D
9
D
1
D
D
D
D
13
D
9
D
11
D
11
D
11
D1
D0
23 21 19
23 21 19
23 21 19
23 21 19
23 21 19
Channel 5
Channel 8
Channel 7
Channel 6
Channel 8
D
D
D
D
12 10
D
D
8
D
0
D
D
D
D
12 10
D
D
8
D
0
D
D
D
D
12 10
D
D
8
D
0
D
D
D
D
12 10
D
D
8
D
0
D
D
D
D
12 10
D
D
8
22 20 18
22 20 18
22 20 18
22 20 18
22 20 18
图6-2. 4-SDO DDR CMOS Data Interface
SMPL_SYNC
tht_SS
tsu_SS
SMPL_CLK
48 DCLKs
td_SYNC_FCLK
DCLKOUT
FCLKOUT
tFCLK
toff_DCLKDO_r
12 DCLK
toff_DCLKDO_f
D
D
D
D
D
D
D
0
D
D
D
D
D
D
D
0
D
D
D
D
D
D
D
0
D
D
D
D
D
D
D
0
D
D
D
D
D
D
D3
D1
23 22 21
12 11 10
23 22 21
12 11 10
23 22 21
12 11 10
23 22 21
12 11 10
23 22 21
12 11 10
Channel 4
Channel 2
Channel 3
Channel 1
Channel 1
D
D
D
D
D
D
D
0
D
D
D
D
D
D
D
0
D
D
D
D
D
D
D
0
D
D
D
D
D
D
D
0
D
D
D
D
D D
12 11 10
23 22 21
12 11 10
23 22 21
12 11 10
23 22 21
12 11 10
23 22 21
12 11 10
23 22 21
Channel 7
Channel 6
Channel 5
Channel 8
Channel 8
图6-3. 2-SDO DDR CMOS Data Interface
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SMPL_SYNC
tht_SS
tsu_SS
SMPL_CLK
td_SYNC_FCLK
48 DCLKs
DCLKOUT
FCLKOUT
D3
tFCLK
td_DCLKDO
D
23
D
21
D
11
D
1
D
23
D
21
D
11
D
1
D
23
D
21
D
11
D
1
D
23
D
21
D
11
D
1
Channel 3
Channel 1
Channel 2
Channel 4
D
22
D
20
D
10
D
0
D
22
D
20
D
10
D
0
D
22
D
20
D
10
D
0
D
22
D
20
D
10
D
0
D2
D1
D
23
D
21
D
11
D
1
D
23
D
21
D
11
D
1
D
23
D
21
D
11
D
1
D
23
D
21
D
11
D
1
Channel 8
Channel 7
Channel 6
Channel 5
D
22
D
20
D
10
D
0
D
22
D
20
D
10
D
0
D
22
D
20
D
10
D
0
D
22
D
20
D
10
D
0
D0
图6-4. 4-SDO SDR CMOS Data Interface
SMPL_SYNC
SMPL_CLK
tht_SS
tsu_SS
td_SYNC_FCLK
96 DCLKs
DCLKOUT
FCLKOUT
D3
tFCLK
td_DCLKDO
D
23
D
22
D
11
D
0
Channel 3
Channel 1
Channel 2
Channel 4
D
23
D
22
D
11
D
0
D1
Channel 8
Channel 7
Channel 6
Channel 5
图6-5. 2-SDO SDR CMOS Data Interface
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6.9 Typical Characteristics
at TA = 25°C, AVDD_5V = 5 V, AVDD_1V8 = 1.8 V, DVDD_1V8 = 1.8 V, internal VREF = 4.096 V, and maximum throughput
(unless otherwise noted)
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-1.5
0
65536
131072
Output Code
196608
262144
0
65536
131072
Output Code
196608
262144
Typical INL = ±1 LSB
图6-6. Typical INL With Low-Noise LPF
Typical INL = ±1.2 LSB
图6-7. Typical INL With Wide-Bandwidth LPF
0.6
0.3
0
0.6
0.3
0
-0.3
-0.6
-0.3
-0.6
0
65536
131072
Output Code
196608
262143
0
65536
131072
Output Code
196608
262143
Typical DNL = ±0.35 LSB
Typical DNL = ±0.35 LSB
图6-8. Typical DNL With Low-Noise LPF
图6-9. Typical DNL With Wide-Bandwidth LPF
0
0
All input ranges
-6
-12
-18
-24
-30
-36
-42
-48
-6
-12
-18
-24
-30
-36
-42
-48
±2.5 V range
±3.5 V range
±5 V range
±7 V range
±10 V range
±12 V range
1
2
3 4 567 10
20 30 50 70100 200
Frequency (kHz)
500 1000
10
20 30 4050 70 100
200 300 500
Frequency (kHz)
1000 2000
Typical bandwidth (–3 dB) = 21.2 kHz
图6-10. Low-Noise LPF Frequency Response Across Input
图6-11. Wide-Bandwidth LPF Frequency Response Across
Ranges
Input Ranges
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7 Detailed Description
7.1 Overview
The ADS981x is an 18-bit data acquisition (DAQ) system with 8-channel analog inputs that can be configured as
either single-ended or differential. Each analog input channel consists of an input clamp protection circuit, a
programmable gain amplifier (PGA), and a second-order, low-pass filter. The input signals are digitized using an
18-bit analog-to-digital converter (ADC), based on the successive approximation register (SAR) architecture.
This overall system can achieve a maximum throughput of 2 MSPS/channel for all channels. The device features
a 4.096-V internal reference with a fast-settling buffer, a programmable digital averaging filter to improve noise
performance, and high-speed data interface for communication with a wide variety of digital hosts.
The device operates from 5-V and 1.8-V analog supplies and can accommodate true bipolar input signals. The
input clamp protection circuitry can tolerate voltages up to ±18 V. The device offers a constant 1-MΩ resistive
input impedance irrespective of the sampling frequency or the selected input range. The ADS981x offers a
simplified end solution without requiring external high-voltage bipolar supplies and complicated driver circuits
7.2 Functional Block Diagram
AVDD_1V8
DVDD_1V8
AVDD_5V
2.5 V
REFOUT_2V5
1 Mꢀ
OVP
OVP
AIN1P
AIN1M
ADC
Driver
Prog. LPF
PGA
PGA
PGA
PGA
PGA
PGA
PGA
PGA
1 Mꢀ
1 Mꢀ
4.096 V
VREF
REFIO
REFM
VB0
OVP
OVP
AIN2P
AIN2M
ADC REF
ADC
Driver
Prog. LPF
Prog. LPF
Prog. LPF
Prog. LPF
Prog. LPF
18-Bit, 8-MSPS
SAR ADC
ADC A
1 Mꢀ
1 Mꢀ
VB1
VB2
VB3
VB4
VB5
VB6
VB7
OVP
OVP
AIN3P
AIN3M
IOVDD
RESET
ADC
Driver
1 Mꢀ
1 Mꢀ
PWDN
SMPL_CLK
OVP
OVP
AIN4P
AIN4M
ADC
Driver
SMPL_SYNC
DCLKOUT
1 Mꢀ
1 Mꢀ
Digital logic
and
ADC REF
FCLKOUT
D0
Data Interface
OVP
OVP
AIN5P
AIN5M
ADC
Driver
D1
D2
D3
1 Mꢀ
1 Mꢀ
OVP
OVP
AIN6P
AIN6M
ADC
Driver
1 Mꢀ
1 Mꢀ
18-Bit, 8-MSPS
SAR ADC
ADC B
OVP
OVP
AIN7P
AIN7M
ADC
Driver
Prog. LPF
1 Mꢀ
1 Mꢀ
SPI_EN
CS / EXTREF
SCLK
Con gura on
Registers
AIN8P
AIN8M
OVP
OVP
ADC
Driver
Prog. LPF
SDI
1 Mꢀ
SDO
GND
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7.3 Feature Description
7.3.1 Analog Inputs
The ADS981x incorporates dual, simultaneous-sampling, 18-bit successive approximation register (SAR)
analog-to-digital converters (ADCs). Each ADC is connected to four analog input channels through a multiplexer.
The device has a total of eight analog input pairs. The ADC digitizes the voltage difference between the analog
input pairs AINxP – AINxM. 图 7-1 shows the simplified circuit schematic for each analog input channel,
including the input clamp protection circuit, PGA, low-pass filter, multiplexer, high-speed ADC driver, and a
precision 18-bit SAR ADC.
1M
AINxP
AINxM
Clamp
Clamp
18 bit
SAR
ADC
2nd order
Prog. LPF
MUX
PGA
1M
图7-1. Front-End Circuit Schematic for the Selected Analog Input Channel
7.3.1.1 Programmable Gain Amplifier (PGA)
The ADS981x features a PGA at every analog input channel. The PGA supports single-ended and differential
inputs with a bipolar signal swing. 表 7-1 lists the supported analog input ranges. The analog input range can be
configured independently for each channel by using the RANGE_CHx register fields in address 0xC2 and
address 0xC3.
表7-1. Analog Input Ranges
DIFFERENTIAL INPUTS
SINGLE-ENDED INPUTS
±12 V
±10 V
±7 V
±12 V
±10 V
±7 V
±5 V
±5 V
±3.5 V
±2.5 V
±3.5 V
±2.5 V
7.3.1.2 Input Clamp Protection Circuit
The ADS981x features an internal clamp protection circuit on each of the eight analog input channels, see 图
7-1. The input clamp protection circuit allows each analog input to swing up to a maximum voltage of ±18 V.
Beyond an input voltage of ±18 V, the input clamp circuit turns on and still operates from the single 5-V supply.
图7-2 illustrates a typical current versus voltage characteristic curve for the input clamp.
For input voltages above the clamp threshold, make sure that the input current never exceeds ±10 mA. A
resistor placed in series with the analog inputs is an effective way to limit the input current. In addition to limiting
the input current, the series resistor can also provide an antialiasing, low-pass filter (LPF) when coupled with a
capacitor. Matching the external source impedance on the AINxP and AINxM pins cancels any additional offset
error.
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50
40
30
20
10
0
-10
-20
-30
-40
-50
-20
-15
-10
-5
0
5
Input Voltage (V)
10
15
20
D007
图7-2. Input Protection Clamp Profile, Input Clamp Current vs Source Voltage
7.3.1.3 Wide-Common-Mode Voltage Rejection Circuit
The ADS981x features a common-mode (CM) rejection circuit at the analog inputs that supports CM voltages up
to ±12 V. The CM voltage for differential inputs is given by 方程式1.
Voltage on AINP + Voltage on AINM
Common mode voltage =
(1)
2
As shown in 表 7-2, the CM voltage rejection circuit can be optimized for various CM voltages for differential
inputs. The CM voltage rejection setting is common for two groups of four analog inputs. Analog input channels
1, 2, 3, and 4 are configured using CM_ADC_A[1:0] and analog input channels 5, 6, 7, and 8 are configured
using CM_ADC_B[1:0].
表7-2. Wide-Common-Mode Configuration for Differential Inputs
CM_ADC_A[1:0]
CM_ADC_B[1:0]
COMMON-MODE (CM) RANGE
WIDE_CM_EN1
WIDE_CM_EN2[1:0]
1
1
1
1
0
No effect
CM ≤±1 V
CM ≤±RANGE / 2
CM ≤±6 V
0
2
1
1: Only AIN[4:1] are differential
2: Only AIN[8:5] are differential
3: All AIN[8:1] are differential
CM ≤±12 V
表7-3 lists the recommended configuration for single-ended inputs.
表7-3. Wide-Common-Mode Configuration for Single-Ended Inputs
CM_ADC_A[1:0]
CM_ADC_B[1:0]
INPUT RANGE
WIDE_CM_EN1
WIDE_CM_EN2[1:0]
±2.5 V, ±3.5 V, and ±5 V
1
0
No effect
1: Only AIN[4:1] are single-ended
2: Only AIN[8:5] are single-ended
3: All AIN[8:1] are single-ended
±7 V, ±10 V, and ±12 V
1
0
On power-up or after reset, the common-mode voltage range for the analog input channels is ±6 V
(WIDE_CM_EN1 = 0b). Voltage at the analog inputs, in all cases, must be within the Absolute Maximum
Ratings.
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7.3.1.4 Programmable Low-Pass Filter
Each analog input channel features a second-order, programmable, antialiasing, low-pass filter (LPF) at the
output of the PGA. 表 7-4 lists the various programmable LPF options available in the ADS981x. 图 6-10 and 图
6-11 illustrate the frequency responses for low-noise and wide-bandwidth LPF configurations. Analog input
bandwidth can be configured using the ANA_BW[7:0] bits in address 0xC0 of register bank 1.
表7-4. Low-Pass Filter Corner Frequency
LPF
ANALOG INPUT RANGE
CORNER FREQUENCY (–3 dB)
Low-noise
All input ranges
±12 V
21.2 kHz
375 kHz
385 kHz
400 kHz
320 kHz
240 kHz
185 kHz
±10 V
±7 V
Wide-bandwidth
±5 V
±3.5 V
±2.5 V
7.3.1.5 Gain Error Calibration
The ADS981x features calibration logic to minimize gain error from the analog inputs. Gain error calibration can
be enabled by configuring the GE_CAL_EN1 (address = 0xD), GE_CAL_EN2, and GE_CAL_EN3 bits (address
= 0x33). Enable gain error calibration for optimum performance.
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7.3.2 ADC Transfer Function
The ADS981x outputs 18 bits of conversion data in either straight-binary or binary two's complement formats.
The format for the output codes is the same across all analog channels. The format for the output codes can be
selected using the DATA_FORMAT field in address 0xD in register bank 1. 图 7-3 and 表 7-5 show the transfer
characteristics for the ADS981x. The LSB size depends on the analog input range selected.
Twos
Complement
Straight
Binary
0x1FFFF
0x1FFFE
0x3FFFF
0x3FFFE
0x00001
0x00000
0x20001
0x20000
0x3FFFF
0x1FFFF
0x20002
0x20001
0x20000
0x00002
0x00001
0x00000
–FS+(0.5)LSB
0V–(0.5)LSB
ANALOG INPUT
+FS–(1.5)LSB
图7-3. Transfer Characteristics
表7-5. ADC Full-Scale Range and LSB Size
RANGE
±2.5 V
±3.5 V
±5 V
+FS
2.5 V
3.5 V
5 V
MIDSCALE
LSB
–FS
–2.5 V
–3.5 V
–5 V
0 V
19.07 µV
26.70 µV
38.15 µV
53.41 µV
76.29 µV
91.55 µV
0 V
0 V
±7 V
7 V
0 V
–7 V
±10 V
±12 V
10 V
12 V
0 V
–10 V
–12 V
0 V
7.3.3 ADC Sampling Clock Input
Use a low-jitter external clock with a high slew rate to maximize SNR performance. The ADS981x can be
operated using a differential or a single-ended clock input, where the single-ended clock consumes less power
consumption. Clock amplitude impacts the ADC aperture jitter and consequently the SNR. For maximum SNR
performance, provide a large clock signal with fast slew rates.
The sampling clock must be a free-running continuous clock. The ADC generates a valid output data, data clock,
and frame clock tPU_SMPL_CLK, as specified in the Switching Characteristics section after a free-running sampling
clock is applied. The ADC output data, data clock, and frame clock are invalid when the sampling clock is
stopped.
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图 7-4 shows a diagram of the differential sampling clock input. For this configuration, connect the differential
sampling clock input to the SMPL_CLKP and SMPL_CLKM pins. 图 7-5 shows a diagram of the single-ended
sampling clock input. In this configuration, connect the single-ended sampling clock to SMPL_CLKP and connect
SMPL_CLKM to ground.
1.8V
SMPL_CLKP
SMPL_CLKP
0V
5.4 k
+
–
Differential
sampling clock
Bias
ADS92XX
5.4 k
SMPL_CLKM
SMPL_CLKM
GND
图7-4. AC Coupled Differential Sampling Clock
图7-5. Single-Ended Sampling Clock
7.3.4 Reference
The ADS981x has a precision, low-drift voltage reference internal to the device. For best performance, filter the
internal reference noise by connecting a 10-µF ceramic bypass capacitor to the REFIO pin. An external
reference can also be connected at the REFIO pin and the internal reference voltage can be disabled by writing
to PD_REF = 1b in address 0xC1 of register bank 1.
7.3.4.1 Internal Reference Voltage
The ADS981x features an internal reference voltage with a nominal output voltage of 4.096 V. On power-up, the
internal reference is enabled by default. As shown in 图 7-6, place a minimum 10-µF decoupling capacitor
between the REFIO and REFM pins.
AVDD_5V
REFIO
ADC REF
External capacitor
10 μF
for reference
1 k
noise reduction
REFM
GND
PD_REF = 0
GND
User register bit
4.096 V
图7-6. Internal Reference Voltage
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7.3.4.2 External Reference Voltage
An external 4.096-V reference voltage, as shown in 图 7-7, can be connected at the REFIO pin with an
appropriate decoupling capacitor placed between the REFIO and REFM pins. For improved thermal drift
performance, the REF7040 is recommended. To disable the internal reference, set PD_REF = 1b in address
0xC1 in register bank 1. The REFIO pin has ESD protection diodes connected to the AVDD_5V and REFM pins.
5V
VIN
EN
OUTF
OUTS
AVDD_5V
REF7040
GND
REFIO
REFM
ADC REF
10 μF
1 k
PD_REF = 1
User register bit
GND
4.096 V
GND
图7-7. External Reference Voltage
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7.3.5 Test Patterns for Data Interface
The ADS981x features test patterns that can be used by the host for debugging and verifying the data interface.
The test patterns replace the ADC output data with predefined digital data. The test patterns can be enabled by
configuring the corresponding register addresses 0x13 through 0x1B in bank 1.
The ADS981x supports the following test patterns:
• User-defined output: User-defined, 24-bit pattern. Separate patterns for ADC A and ADC B; see the User-
Defined Test Pattern section.
• Ramp output: Digital ramp output with a user-defined increment between two steps. There are separate ramp
outputs for ADC A and ADC B; see the Ramp Test Pattern section.
• Alternate output: User-defined, 24-bit outputs that alternate between ADC A and ADC B user-defined
patterns; see the User-Defined Alternating Test Pattern section.
To disable the test patterns, set TEST_PAT_EN_CHA and TEST_PAT_EN_CHB to 0b.
7.3.5.1 User-Defined Test Pattern
The user-defined test pattern allows the host to specify a fixed 24-bit value that is output by the ADS981x.
Configure the registers in bank 1 to enable the user-defined test pattern:
• Configure the test patterns in TEST_PAT0_CHA (address = 0x14, 0x15) and TEST_PAT0_CHB (address =
0x19, 0x1A)
• Set TEST_PAT_EN_CHA = 1, TEST_PATMODE_CHA = 0 (address = 0x13) and TEST PAT_EN_CHB = 1,
TEST_PATMODE_CHB = 0 (address = 0x18)
The ADS981x outputs the TEST_PAT0_CHA and TEST_PAT0_CHB register values in place of the ADC A and
ADC B data, respectively.
7.3.5.2 User-Defined Alternating Test Pattern
The user-defined alternating test pattern allows the host to specify two fixed 24-bit values that are output by the
ADS981x alternately. Configure the registers in bank 1 to enable the user-defined alternating test pattern:
• Configure the test patterns in TEST_PAT0_CHA (address = 0x14, 0x15), TEST_PAT1_CHA (address = 0x15,
0x16) and TEST_PAT0_CHB (address = 0x19, 0x1A), TEST_PAT1_CHB (address = 0x1A, 0x1B)
• Set TEST_PAT_EN_CHA = 1, TEST_PATMODE_CHA = 3 (address = 0x13) and TEST PAT_EN_CHB = 1,
TEST_PATMODE_CHB = 3 (address = 0x18)
The ADS981x outputs the TEST_PAT0_CHA and TEST_PAT0_CHB register values in place of the ADC A and
ADC B data, respectively, in one output frame and the TEST_PAT1_CHA and TEST_PAT1_CHB register values
in the next frame.
7.3.5.3 Ramp Test Pattern
The ramp test pattern allows the host to specify a digital ramp that is output by the ADS981x. Configure the
registers in bank 1 to enable the ramp test pattern:
• Configure the increment value between two successive steps of the digital ramp in the RAMP_INC_CHA
(address = 0x13) and RAMP_INC_CHB (address = 0x18) registers, respectively. The digital ramp increments
by N + 1, where N is the value configured in these registers.
• Set TEST_PAT_EN_CHA = 1, TEST_PATMODE_CHA = 2 (address = 0x13) and TEST PAT_EN_CHB = 1,
TEST_PATMODE_CHB = 2 (address = 0x18).
The ADS981x outputs digital ramp values in place of the ADC A and ADC B data, respectively.
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7.4 Programming
7.4.1 Register Write
Register write access is enabled by setting SPI_RD_EN = 0b. The 16-bit configuration registers are grouped in
three register banks and are addressable with an 8-bit register address. Register bank 1 and register bank 2 can
be selected for read or write operation by configuring the PAGE_SEL0 and PAGE_SEL1 bits, respectively.
Registers in bank 0 are always accessible, irrespective of the PAGE_SELx bits because the register addresses
are unique and are not used in register banks 1 and 2.
As shown in 图7-8, steps to write to a register are:
1. Frame 1: Write to register address 0x03 in register bank 0 to select either register bank 1 or bank 2 for a
subsequent register write. This frame has no effect when writing to registers in bank 0.
2. Frame 2: Write to a register in the bank selected in frame 1. Repeat this step for writing to multiple registers
in the same register bank.
Frame 1
24-bits
Frame 2
CS
SCLK
SDI
{ addr[23:16] = 0x03, data[15:0] = 0x0002 or
0x0010 }
{ addr[23:16] = REG_ADDR, data[15:0] = DATA }
Register Write
Register Write for Bank Selection (ADDR = 0x03)
Not Required for Register Bank 0
Logic 0 (when SPI_MODE = 0b) and Hi-Z (when SPI_MODE = 1b)
SDO
图7-8. Register Write
7.4.2 Register Read
Select the desired register bank by writing to register address 0x03 in register bank 0. Register read access is
enabled by setting SPI_RD_EN = 1b and SPI_MODE = 1b in register bank 0. As shown in 图 7-9, registers can
be read using two 24-bit SPI frames after SPI_RD_EN and SPI_MODE are set. The first SPI frame selects the
register bank. The ADC returns the 16-bit register value in the second SPI frame corresponding to the 8-bit
register address.
As illustrated in 图7-9, steps to read a register are:
1. Frame 1: With SPI_RD_EN = 0b, write to register address 0x03 in register bank 0 to select the desired
register bank 0 for reading.
2. Frame 2: Set SPI_RD_EN = 1b and SPI_MODE = 1b in register address 0x00 in register bank 0.
3. Frame 3: Read any register in the selected bank using a 24-bit SPI frame containing the desired register
address. Repeat this step with the address of any register in the selected bank to read the corresponding
register.
4. Frame 4: Set SPI_RD_EN = 0 to disable register read and re-enable register writes.
5. Repeat steps 1 through 4 to read registers in a different bank.
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Frame 1
24-bits
Frame 2
Frame 3
Frame 4
CS
SCLK
SDI
{ addr[23:16] = 0x03, data[15:0] = 0x0002 or
0x0010 }
{ addr[23:16] = 0x00, data[15:0] = 0x0006 }
Register Write for Read Enable (ADDR = 0x00)
{ addr[23:16] = REG_ADDR, data[15:0] = 0 }
{ addr[23:16] = 0x00, data[15:0] = 0x0004 }
Register Write for Bank Selection (ADDR = 0x03)
Not Required for Register Bank 0
Register Write for Read Disable (ADDR = 0x00)
Register Read: 8-bit address of register to be read
Hi-Z (when SPI_MODE = 1b)
Logic 0 (when SPI_MODE = 0b)
16-bit Register Data
SDO
图7-9. Register Read
7.4.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
图7-10 shows a typical connection diagram showing multiple devices in a daisy-chain topology.
SCLK
CS
SCLK
ADS98XX
SCLK
ADS98XX
SCLK
ADS98XX
SCLK
ADS98XX
CS
CS
CS
CS
HOST
ADC4
ADC3
ADC2
ADC1
SDO
SDI
SDO
SDI
SDO
SDI
SDO
SDI
24-bit
24-bit
24-bit
24-bit
PICO
POCI
图7-10. Daisy-Chain Connections for SPI Configuration
The CS and SCLK inputs of all ADCs are connected together and controlled by a single CS and SCLK pin of the
controller, respectively. The SDI input pin of the first ADC in the chain (ADC1) is connected to the peripheral IN
controller OUT (PICO) pin of the controller, the SDO output pin of ADC1 is connected to the SDI input pin of
ADC2, and so on. The SDO output pin of the last ADC in the chain (ADC4) is connected to the peripheral OUT
controller IN (POCI) pin of the controller. The data on the PICO pin passes through ADC1 with a 24-SCLK delay,
as long as CS is active.
The daisy-chain mode must be enabled after power-up or after the device is reset. Set the daisy-chain length in
the DAISY_CHAIN_LENGTH register to enable daisy-chain mode. The daisy-chain length is the number of
ADCs in the chain excluding ADC1. In 图7-10, the DAISY_CHAIN_LENGTH = 3.
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7.4.3.1 Register Write With Daisy-Chain
Writing to registers in a daisy-chain configuration requires N × 24-SCLKs in one SPI frame. A register write in a
daisy-chain containing four ADCs, as shown in 图7-11, requires 96 SCLKs.
CS
N x 24 bits
SCLK
DADCN
DADC3
DADC2
DADC1
PICO
POCI
Logic 0 (when SPI_MODE = 0b)
图7-11. Register Write With Daisy-Chain
Daisy-chain mode is enabled on power-up or after device reset. Configure the DAISY_CHAIN_LENGTH field to
enable daisy-chain mode. The waveform shown in 图 7-11 must be repeated N times, where N is the number of
ADCs in the daisy-chain. 图 7-12 provides the SPI waveform, containing N SPI frames, for enabling daisy-chain
mode for N ADCs.
DADC1[23:0] = DADC2[23:0] = DADC3[23:0] = DADCN[23:0] = { 0000 0001, 0000 0000, N-1, 00}
Frame 1
Frame 2
Frame 3
Frame N
CS
N x 24 bits
SCLK
PICO
DADCN
DADC3
DADC2
DADC1
DADCN
DADC3
DADC2
DADC1
DADCN
DADC3
DADC2
DADC1
DADCN
DADC3
DADC2
DADC1
DAISY_CHAIN_LENGTH = 3 {ADC1}
DAISY_CHAIN_LENGTH = 0 {ADC2, ADC3, and ADCN} DAISY_CHAIN_LENGTH = 0 {ADC3, ADCN}
DAISY_CHAIN_LENGTH = 3 {ADC1 and ADC2}
DAISY_CHAIN_LENGTH = 3 {ADC1, ADC2 and ADC3}
DAISY_CHAIN_LENGTH = 0 {ADCN}
DAISY_CHAIN_LENGTH = 3 {ADC1,
ADC2, ADC3 and ADCN}
POCI
Logic 0 (when SPI_MODE = 0b)
图7-12. Register Write to Configure Daisy-Chain Length
7.4.3.2 Register Read With Daisy-Chain
图 7-13 illustrates an SPI waveform for reading registers in a daisy-chain configuration. The steps for reading
registers from N ADCs connected in a daisy-chain are as follows:
1. Register read is enabled by writing to the following registers using the Register Write With Daisy-Chain:
a. Write to PAGE_SEL to select the desired register bank
b. Enable register read by writing SPI_RD_EN = 0b (default on power-up)
2. With the register bank selected and SPI_RD_EN = 0b, the controller can read register data in the following
two steps:
a. N × 24-bit SPI frame containing the 8-bit register address to be read: N-times {0xFE, 0x00, 8-bit register
address}
b. N × 24-bit SPI frame to read out register data: N-times {0xFF, 0xFF, 0xFF}
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The 0xFE in step 2a configures the ADC for register read from the specified 8-bit address. At the end of step 2a,
the output shift register in the ADC is loaded with register data. The ADC returns the 8-bit register address and
corresponding 16-bit register data in step 2b.
CS
N x 24 bits
N x 24 bits
SCLK
24 bits
0x00
24 bits
0xFF
8-bit register
address
0xFE
0xFE
0xFF
0xFF
0xFF
PICO
POCI
8-bit
address
8-bit
address
16-bit register data
图7-13. Register Read With Daisy-Chain
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7.5 Register Map
7.5.1 Register Bank 0
图7-14. Register Bank 0 Map
ADD
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RESERVED
SPI_MO SPI_RD RESET
00h
01h
03h
06h
DE _EN
RESERVED
DAISY_CHAIN_LEN
REG_BANK_SEL
RESERVED
RESERVED
REG_00H_READBACK
7.5.1.1 Register 0h (offset = 0h) [reset = 0h]
图7-15. Register 0h
15
14
13
12
11
10
9
8
RESERVED
W-0h
7
6
5
4
3
2
1
0
RESERVED
W-0h
SPI_MODE
W-0h
SPI_RD_EN
W-0h
RESET
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-16. Register 00 Field Descriptions
Bit
Field
Type
Reset
Description
15-3
RESERVED
W
0h
Reserved. Do not change from the default reset value.
Select between legacy SPI mode and daisy-chain SPI
mode for the configuration interface for register access.
0: Daisy-chain SPI mode
2-2
SPI_MODE
W
0h
1: Legacy SPI mode
Enable register read access in legacy SPI mode. This bit
has no effect in daisy-chain SPI mode.
0: Register read disabled
1-1
0-0
SPI_RD_EN
RESET
W
W
0h
0h
1: Register read enabled
ADC reset control
0: Normal device operation
1: Reset ADC and all registers
7.5.1.2 Register 1h (offset = 1h) [reset = 0h]
图7-17. Register 1h
15
14
13
12
11
10
2
9
8
RESERVED
R/W-0h
7
6
5
4
3
1
0
RESERVED
R/W-0h
DAISY_CHAIN_LEN
R/W-0h
RESERVED
R/W-0h
RESERVED
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
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图7-18. Register 01 Field Descriptions
Bit
Field
Type
Reset
Description
15-7
RESERVED
R/W
0h
Reserved. Do not change from the default reset value.
Configure the number of ADCs connected in daisy-chain for
configuring the SPI interface.
0: 1 ADC
1: 2 ADCs
DAISY_CHAIN_L
EN
6-2
1-0
R/W
R/W
0h
0h
31: 32 ADCs
RESERVED
Reserved. Do not change from the default reset value.
7.5.1.3 Register 3h (offset = 3h) [reset = 2h]
图7-19. Register 3h
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R/W-0h
7
6
5
4
3
REG_BANK_SEL
R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-20. Register 03 Field Descriptions
Bit
Field
Type
Reset
Description
15-8
RESERVED
R/W
0h
Reserved. Do not change from the default reset value.
Register bank selection for read and write operations.
0: Select register bank 0
7-0
REG_BANK_SEL
R/W
2h
1: Select register bank 1
7.5.1.4 Register 6h (offset = 6h) [reset = 5h]
图7-21. Register 6h
15
14
13
12
11
10
2
9
1
8
0
REG_00H_READBACK
R-0h
7
6
5
4
3
REG_00H_READBACK
R-5h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-22. Register 06 Field Descriptions
Bit
Field
Type
Reset
Description
REG_00H_READ
BACK
This register is a copy of the register address 0x00 for
readback. Register address 0x00 is write-only.
15-0
R
5h
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7.5.2 Register Bank 1
图7-23. Register Bank 1 Map
ADD
0Dh
12h
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RESERVED
DATA_F
ORMAT
RESERVED
GE_CAL
_EN1
2
RESERVED
XOR_EN
DATA_WIDTH
DATA_L
ANES
RESERVED
RAMP_INC_ADC_A
TEST_PAT_MODE_ TEST_P
ADC_A AT_EN_ RESERV
ADC_A ED
13h
14h
15h
16h
TEST_PAT0_ADC_A
TEST_PAT1_ADC_A
TEST_PAT1_ADC_A
RESERVED
TEST_PAT0_ADC_A
RAMP_INC_ADC_B
TEST_PAT_MODE_ TEST_P
ADC_B AT_EN_ RESERV
ADC_B ED
18h
19h
1Ah
1Bh
1Ch
TEST_PAT0_ADC_B
TEST_PAT1_ADC_B
TEST_PAT1_ADC_B
USER_BITS_ADC_B
TEST_PAT0_ADC_B
USER_BITS_ADC_A
RESERVED
RESERVED
GE_CAL
_EN3
RESERVED
GE_CAL
_EN2
33h
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
USER_GAIN_CAL_CH1
USER_GAIN_CAL_CH2
USER_GAIN_CAL_CH3
USER_GAIN_CAL_CH4
USER_GAIN_CAL_CH5
USER_GAIN_CAL_CH6
USER_GAIN_CAL_CH7
USER_GAIN_CAL_CH8
RESERVED
USER_GAIN_CAL_CH1
USER_GAIN_CAL_CH2
USER_GAIN_CAL_CH3
USER_GAIN_CAL_CH4
USER_GAIN_CAL_CH5
USER_GAIN_CAL_CH6
USER_GAIN_CAL_CH7
USER_GAIN_CAL_CH8
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERV RD_TEM
RESERVED
90h
91h
C0h
ED
P
RESERVED
DATA_CLK_CFG1
RESERVED
TEMP_SENSE
RESERVED
DATA_CLK_CFG2
ANA_BW
PD_CH
PD_REF
RESERVED
DATA_R
ATE
RESERVED
C1h
C2h
C3h
RANGE_CH4
RANGE_CH8
RANGE_CH3
RANGE_CH7
RANGE_CH2
RANGE_CH6
RANGE_CH1
RANGE_CH5
WIDE_CM_EN2 RESERV PD_CHI
RESERVED
CM_ADC_B
CM_ADC_A
DATA_CLK_CFG3
C4h
C5h
ED
P
RESERVED
WIDE_C
M_EN1
RESERVED
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7.5.2.1 Register Dh (offset = Dh) [reset = 2002h]
图7-24. Register Dh
15
14
13
12
11
10
9
1
8
0
RESERVED
R/W-0h
DATA_FORMAT
R/W-1h
RESERVED
R/W-0h
7
6
5
4
3
2
GE_CAL_EN1
R/W-0h
RESERVED
R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-25. Register 0D Field Descriptions
Bit
Field
Type
Reset
Description
15-14
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Select data format for ADC conversion result
0 : Straight binary
1 : 2's complement
13-13
12-8
7-7
DATA_FORMAT
RESERVED
GE_CAL_EN1
2
R/W
R/W
R/W
R/W
1h
0h
0h
2h
Reserved. Do not change from default reset value.
Global control for gain error calibration.
0 : Gain error calibration disabled for all channels.
1 : Gain error calibration enabled for all channels.
6-0
Reserved. Do not change from default reset value.
7.5.2.2 Register 12h (offset = 12h) [reset = 2h]
图7-26. Register 12h
15
14
13
12
11
10
2
9
1
8
RESERVED
R/W-0h
7
6
5
4
3
0
RESERVED
R/W-0h
XOR_EN
R/W-0h
DATA_WIDTH
R/W-1h
DATA_LANES
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-27. Register 12 Field Descriptions
Bit
Field
Type
Reset
Description
15-4
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Enables XOR operation on ADC conversion result.
0 : XOR operation is disabled.
1 : ADC conversion result is bit-wise XOR with LSB of the
ADC conversion result.
3-3
XOR_EN
R/W
R/W
0h
1h
Select the output data frame width.
0 : 20-bit output frame. Use with 2-lane mode
(DATA_LANES = 0).
1 : 24-bit output frame. Use with 2-lane mode
(DATA_LANES = 0).
2-1
DATA_WIDTH
2 : 40-bit output frame. Use with 1-lane mode
(DATA_LANES = 1).
3 : 48-bit output frame. Use with 1-lane mode
(DATA_LANES = 1).
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图7-27. Register 12 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
Select number of output data lanes per ADC channel.
0 : 2-lane mode. ADC A data is output on pins D3 and D2.
ADC B data is output on pins D1 and D0.
0-0
DATA_LANES
R/W
0h
1 : 1-lane mode. ADC A data is output on pin D3. ADC B
data is output on pin D1.
7.5.2.3 Register 13h (offset = 13h) [reset = 0h]
图7-28. Register 13h
15
14
13
12
11
10
2
9
1
8
RESERVED
R/W-0h
7
6
5
4
3
0
RAMP_INC_ADC_A
R/W-0h
TEST_PAT_MODE_ADC_A
TEST_PAT_EN
_ADC_A
RESERVED
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-29. Register 13 Field Descriptions
Bit
Field
Type
Reset
Description
15-8
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Increment value for the ramp pattern output. The output
ramp will increment by N+1 where N is the value configured
in this register.
RAMP_INC_ADC
_A
7-4
R/W
0h
Select digital test pattern for analog input channels 1, 2, 3,
and 4.
0 : Fixed pattern as configured in TEST_PAT0_ADC_A
register.
1 : Fixed pattern as configured in TEST_PAT1_ADC_A
register.
TEST_PAT_MOD
E_ADC_A
3-2
R/W
0h
2 : Digital ramp output.
3 : Alternate fixed pattern output as configured in
TEST_PAT0_ADC_A and TEST_PAT1_ADC_A registers.
Enable digital test pattern for data for data corresponding to
channel 1, 2, 3, and 4.
TEST_PAT_EN_A
DC_A
0 : ADC conversion result will be launched on the data
interface.
1 : Digital test pattern will be launched corresponding to
channels 1, 2, 3, and 4 on the data interface.
1-1
0-0
R/W
R/W
0h
0h
RESERVED
Reserved. Do not change from default reset value.
7.5.2.4 Register 14h (offset = 14h) [reset = 0h]
图7-30. Register 14h
15
14
13
12
11
10
2
9
1
8
0
TEST_PAT0_ADC_A[23:8]
R/W-0h
7
6
5
4
3
TEST_PAT0_ADC_A[23:8]
R/W-0h
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LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-31. Register 14 Field Descriptions
Bit
Field
Type
Reset
Description
TEST_PAT0_ADC
_A[23:8]
Test pattern 0 for channels 1, 2, 3, and 4 corresponding to
ADC A.
15-0
R/W
0h
7.5.2.5 Register 15h (offset = 15h) [reset = 0h]
图7-32. Register 15h
15
14
13
12
11
10
2
9
1
8
0
TEST_PAT1_ADC_A[23:16]
R/W-0h
7
6
5
4
3
TEST_PAT0_ADC_A[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-33. Register 15 Field Descriptions
Bit
Field
Type
Reset
Description
TEST_PAT1_ADC
_A[23:16]
Test pattern 1 for channels 1, 2, 3, and 4 corresponding to
ADC A.
15-8
R/W
0h
TEST_PAT0_ADC
_A[7:0]
Test pattern 0 for channels 1, 2, 3, and 4 corresponding to
ADC A.
7-0
R/W
0h
7.5.2.6 Register 16h (offset = 16h) [reset = 0h]
图7-34. Register 16h
15
14
13
12
11
10
2
9
1
8
0
TEST_PAT1_ADC_A[15:0]
R/W-0h
7
6
5
4
3
TEST_PAT1_ADC_A[15:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-35. Register 16 Field Descriptions
Bit
Field
Type
Reset
Description
TEST_PAT1_ADC
_A[15:0]
Test pattern 1 for channels 1, 2, 3, and 4 corresponding to
ADC A.
15-0
R/W
0h
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7.5.2.7 Register 18h (offset = 18h) [reset = 0h]
图7-36. Register 18h
15
14
13
12
11
10
2
9
1
8
RESERVED
R/W-0h
7
6
5
4
3
0
RAMP_INC_ADC_B
R/W-0h
TEST_PAT_MODE_ADC_B
TEST_PAT_EN
_ADC_B
RESERVED
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-37. Register 18 Field Descriptions
Bit
Field
Type
Reset
Description
15-8
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Increment value for the ramp pattern output. The output
ramp will increment by N+1 where N is the value configured
in this register.
RAMP_INC_ADC
_B
7-4
R/W
0h
Select digital test pattern for analog input channels 5, 6, 7,
and 8.
0 : Fixed pattern as configured in TEST_PAT0_ADC_B
register.
1 : Fixed pattern as configured in TEST_PAT1_ADC_B
register.
TEST_PAT_MOD
E_ADC_B
3-2
R/W
0h
2 : Digital ramp output.
3 : Alternate fixed pattern output as configured in
TEST_PAT0_ADC_B and TEST_PAT1_ADC_B registers.
Enable digital test pattern for data for data corresponding to
channel 5, 6, 7, and 8.
TEST_PAT_EN_A
DC_B
0 : ADC conversion result will be launched on the data
interface.
1 : Digital test pattern will be launched corresponding to
channels 5, 6, 7, and 8 on the data interface.
1-1
0-0
R/W
R/W
0h
0h
RESERVED
Reserved. Do not change from default reset value.
7.5.2.8 Register 19h (offset = 19h) [reset = 0h]
图7-38. Register 19h
15
14
13
12
11
10
2
9
1
8
0
TEST_PAT0_ADC_B[23:8]
R/W-0h
7
6
5
4
3
TEST_PAT0_ADC_B[23:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-39. Register 19 Field Descriptions
Bit
Field
Type
Reset
Description
TEST_PAT0_ADC
_B[23:8]
Test pattern 0 for channels 5, 6, 7, and 8 corresponding to
ADC B.
15-0
R/W
0h
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7.5.2.9 Register 1Ah (offset = 1Ah) [reset = 0h]
图7-40. Register 1Ah
15
7
14
13
12
11
10
2
9
1
8
0
TEST_PAT1_ADC_B[23:16]
R/W-0h
6
5
4
3
TEST_PAT0_ADC_B[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-41. Register 1A Field Descriptions
Bit
Field
Type
Reset
Description
TEST_PAT1_ADC
_B[23:16]
Test pattern 1 for channels 5, 6, 7, and 8 corresponding to
ADC B.
15-8
R/W
0h
TEST_PAT0_ADC
_B[7:0]
Test pattern 0 for channels 5, 6, 7, and 8 corresponding to
ADC B.
7-0
R/W
0h
7.5.2.10 Register 1Bh (offset = 1Bh) [reset = 0h]
图7-42. Register 1Bh
15
14
13
12
11
10
2
9
1
8
0
TEST_PAT1_ADC_B[15:0]
R/W-0h
7
6
5
4
3
TEST_PAT1_ADC_B[15:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-43. Register 1B Field Descriptions
Bit
Field
Type
Reset
Description
TEST_PAT1_ADC
_B[15:0]
Test pattern 1 for channels 5, 6, 7, and 8 corresponding to
ADC B.
15-0
R/W
0h
7.5.2.11 Register 1Ch (offset = 1Ch) [reset = 0h]
图7-44. Register 1Ch
15
14
13
12
11
10
2
9
1
8
0
USER_BITS_ADC_B
R/W-0h
7
6
5
4
3
USER_BITS_ADC_A
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
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图7-45. Register 1C Field Descriptions
Bit
Field
Type
Reset
Description
User defined bits appended to ADC conversion result from
channels 5, 6, 7, and 8 when DATA_WIDTH ≥ADC
resolution.
USER_BITS_ADC
_B
15-8
R/W
0h
User defined bits appended to ADC conversion result from
channels 1, 2, 3, and 4 when DATA_WIDTH ≥ADC
resolution.
USER_BITS_ADC
_A
7-0
R/W
0h
7.5.2.12 Register 33h (offset = 33h) [reset = 0h]
图7-46. Register 33h
15
14
13
12
11
10
9
1
8
0
RESERVED
R/W-0h
GE_CAL_EN3
R/W-0h
RESERVED
R/W-0h
7
6
5
4
3
2
RESERVED
R/W-0h
GE_CAL_EN2
R/W-0h
RESERVED
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-47. Register 33 Field Descriptions
Bit
Field
Type
Reset
Description
15-14
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Global control for gain error calibration.
13-13
12-7
6-6
GE_CAL_EN3
RESERVED
GE_CAL_EN2
RESERVED
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0 : Gain error calibration disabled for all channels.
1 : Gain error calibration enabled for all channels.
Reserved. Do not change from default reset value.
Global control for gain error calibration.
0 : Gain error calibration disabled for all channels.
1 : Gain error calibration enabled for all channels.
5-0
Reserved. Do not change from default reset value.
7.5.2.13 Register 40h (offset = 40h) [reset = 0h]
图7-48. Register 40h
15
14
13
12
11
10
2
9
1
8
0
USER_GAIN_CAL_CH1[21:6]
R/W-0h
7
6
5
4
3
USER_GAIN_CAL_CH1[21:6]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-49. Register 40 Field Descriptions
Bit
Field
Type
Reset
Description
USER_GAIN_CAL
_CH1[21:6]
15-0
R/W
0h
21-bit gain error correction code for channel 1.
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7.5.2.14 Register 41h (offset = 41h) [reset = 0h]
图7-50. Register 41h
15
7
14
13
12
11
10
2
9
1
8
0
RESERVED
R/W-0h
6
5
4
3
RESERVED
R/W-0h
USER_GAIN_CAL_CH1[5:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-51. Register 41 Field Descriptions
Bit
Field
Type
Reset
Description
15-6
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
21-bit gain error correction code for channel 1.
USER_GAIN_CAL
_CH1[5:0]
5-0
R/W
0h
7.5.2.15 Register 42h (offset = 42h) [reset = 0h]
图7-52. Register 42h
15
14
13
12
11
10
2
9
1
8
0
USER_GAIN_CAL_CH2[21:6]
R/W-0h
7
6
5
4
3
USER_GAIN_CAL_CH2[21:6]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-53. Register 42 Field Descriptions
Bit
Field
Type
Reset
Description
USER_GAIN_CAL
_CH2[21:6]
15-0
R/W
0h
21-bit gain error correction code for channel 2.
7.5.2.16 Register 43h (offset = 43h) [reset = 0h]
图7-54. Register 43h
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R/W-0h
7
6
5
4
3
RESERVED
R/W-0h
USER_GAIN_CAL_CH2[5:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-55. Register 43 Field Descriptions
Bit
Field
Type
Reset
Description
15-6
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
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图7-55. Register 43 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
USER_GAIN_CAL
_CH2[5:0]
5-0
R/W
0h
21-bit gain error correction code for channel 2.
7.5.2.17 Register 44h (offset = 44h) [reset = 0h]
图7-56. Register 44h
15
14
13
12
11
10
2
9
1
8
0
USER_GAIN_CAL_CH3[21:6]
R/W-0h
7
6
5
4
3
USER_GAIN_CAL_CH3[21:6]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-57. Register 44 Field Descriptions
Bit
Field
Type
Reset
Description
USER_GAIN_CAL
_CH3[21:6]
15-0
R/W
0h
21-bit gain error correction code for channel 3.
7.5.2.18 Register 45h (offset = 45h) [reset = 0h]
图7-58. Register 45h
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R/W-0h
7
6
5
4
3
RESERVED
USER_GAIN_CAL_CH3[5:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-59. Register 45 Field Descriptions
Bit
Field
Type
Reset
Description
15-6
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
21-bit gain error correction code for channel 3.
USER_GAIN_CAL
_CH3[5:0]
5-0
R/W
0h
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7.5.2.19 Register 46h (offset = 46h) [reset = 0h]
图7-60. Register 46h
15
7
14
13
12
11
10
2
9
1
8
0
USER_GAIN_CAL_CH4[21:6]
R/W-0h
6
5
4
3
USER_GAIN_CAL_CH4[21:6]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-61. Register 46 Field Descriptions
Bit
Field
Type
Reset
Description
USER_GAIN_CAL
_CH4[21:6]
15-0
R/W
0h
21-bit gain error correction code for channel 4.
7.5.2.20 Register 47h (offset = 47h) [reset = 0h]
图7-62. Register 47h
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R/W-0h
7
6
5
4
3
RESERVED
R/W-0h
USER_GAIN_CAL_CH4[5:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-63. Register 47 Field Descriptions
Bit
Field
Type
Reset
Description
15-6
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
21-bit gain error correction code for channel 4.
USER_GAIN_CAL
_CH4[5:0]
5-0
R/W
0h
7.5.2.21 Register 48h (offset = 48h) [reset = 0h]
图7-64. Register 48h
15
14
13
12
11
10
2
9
1
8
0
USER_GAIN_CAL_CH5[21:6]
R/W-0h
7
6
5
4
3
USER_GAIN_CAL_CH5[21:6]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-65. Register 48 Field Descriptions
Bit
Field
Type
Reset
Description
USER_GAIN_CAL
_CH5[21:6]
15-0
R/W
0h
21-bit gain error correction code for channel 5.
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7.5.2.22 Register 49h (offset = 49h) [reset = 0h]
图7-66. Register 49h
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R/W-0h
7
6
5
4
3
RESERVED
R/W-0h
USER_GAIN_CAL_CH5[5:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-67. Register 49 Field Descriptions
Bit
Field
Type
Reset
Description
15-6
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
21-bit gain error correction code for channel 5.
USER_GAIN_CAL
_CH5[5:0]
5-0
R/W
0h
7.5.2.23 Register 4Ah (offset = 4Ah) [reset = 0h]
图7-68. Register 4Ah
15
14
13
12
11
10
2
9
1
8
0
USER_GAIN_CAL_CH6[21:6]
R/W-0h
7
6
5
4
3
USER_GAIN_CAL_CH6[21:6]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-69. Register 4A Field Descriptions
Bit
Field
Type
Reset
Description
USER_GAIN_CAL
_CH6[21:6]
15-0
R/W
0h
21-bit gain error correction code for channel 6.
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7.5.2.24 Register 4Bh (offset = 4Bh) [reset = 0h]
图7-70. Register 4Bh
15
7
14
13
12
11
10
2
9
1
8
0
RESERVED
R/W-0h
6
5
4
3
RESERVED
R/W-0h
USER_GAIN_CAL_CH6[5:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-71. Register 4B Field Descriptions
Bit
Field
Type
Reset
Description
15-6
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
21-bit gain error correction code for channel 6.
USER_GAIN_CAL
_CH6[5:0]
5-0
R/W
0h
7.5.2.25 Register 4Ch (offset = 4Ch) [reset = 0h]
图7-72. Register 4Ch
15
14
13
12
11
10
2
9
1
8
0
USER_GAIN_CAL_CH7[21:6]
R/W-0h
7
6
5
4
3
USER_GAIN_CAL_CH7[21:6]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-73. Register 4C Field Descriptions
Bit
Field
Type
Reset
Description
USER_GAIN_CAL
_CH7[21:6]
15-0
R/W
0h
21-bit gain error correction code for channel 7.
7.5.2.26 Register 4Dh (offset = 4Dh) [reset = 0h]
图7-74. Register 4Dh
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R/W-0h
7
6
5
4
3
RESERVED
R/W-0h
USER_GAIN_CAL_CH7[5:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-75. Register 4D Field Descriptions
Bit
Field
Type
Reset
Description
15-6
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
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图7-75. Register 4D Field Descriptions (continued)
Bit
Field
Type
Reset
Description
USER_GAIN_CAL
_CH7[5:0]
5-0
R/W
0h
21-bit gain error correction code for channel 7.
7.5.2.27 Register 4Eh (offset = 4Eh) [reset = 0h]
图7-76. Register 4Eh
15
14
13
12
11
10
2
9
1
8
0
USER_GAIN_CAL_CH8[21:6]
R/W-0h
7
6
5
4
3
USER_GAIN_CAL_CH8[21:6]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-77. Register 4E Field Descriptions
Bit
Field
Type
Reset
Description
USER_GAIN_CAL
_CH8[21:6]
15-0
R/W
0h
21-bit gain error correction code for channel 8.
7.5.2.28 Register 4Fh (offset = 4Fh) [reset = 0h]
图7-78. Register 4Fh
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R/W-0h
7
6
5
4
3
RESERVED
R/W-0h
USER_GAIN_CAL_CH8[5:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-79. Register 4F Field Descriptions
Bit
Field
Type
Reset
Description
15-6
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
21-bit gain error correction code for channel 8.
USER_GAIN_CAL
_CH8[5:0]
5-0
R/W
0h
7.5.2.29 Register 90h (offset = 90h) [reset = 0h]
图7-80. Register 90h
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R/W-0h
RD_TEMP
R/W-0h
RESERVED
R/W-0h
7
6
5
4
3
RESERVED
R/W-0h
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LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-81. Register 90 Field Descriptions
Bit
Field
Type
Reset
Description
15-15
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Load temperature sensor digital output in TEMP_SENSE
register. Digital output of temperature sensor is updated
14-14
13-0
RD_TEMP
R/W
R/W
0h
0h
when TEMP_SENSE register everytime this bit is changed
from 0 to 1.
0 :
RESERVED
Reserved. Do not change from default reset value.
7.5.2.30 Register 91h (offset = 91h) [reset = 0h]
图7-82. Register 91h
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R/W-0h
TEMP_SENSE
R-0h
7
6
5
4
3
TEMP_SENSE
R-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-83. Register 91 Field Descriptions
Bit
15-10
9-0
Field
Type
R/W
R
Reset
Description
RESERVED
TEMP_SENSE
0h
Reserved. Do not change from default reset value.
10-bit temperature senor output.
0h
7.5.2.31 Register C0h (offset = C0h) [reset = 0h]
图7-84. Register C0h
15
14
13
12
11
DATA_CLK_CFG2
R/W-0h
10
9
1
8
0
RESERVED
R/W-0h
DATA_CLK_CFG1
ANA_BW
R/W-0h
R/W-0h
7
6
5
4
3
2
ANA_BW
R/W-0h
PD_CH
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-85. Register C0 Field Descriptions
Bit
Field
Type
Reset
Description
15-14
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Data output clock setting based on DATA_LANES
configuration.
0 : DATA_LANES = 0b. Configuration for 2-output lanes per
ADC.
13-12
DATA_CLK_CFG1
R/W
0h
1 : DATA_LANES = 1b. Configuration for 1-output lane per
ADC.
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图7-85. Register C0 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
Data output clock setting based on DATA_LANES and
DATA_WIDTH configuration.
0 : Configuration for 24-bit 2-lane mode.
1 : Configuration for 48-bit 1-lane mode.
11-10
DATA_CLK_CFG2
R/W
0h
Select analog input bandwidth for respective analog input
channels.
MSB = BW control for channel 8.
LSB = BW control for channel 1.
0 : Low-noise mode
9-2
1-0
ANA_BW
PD_CH
R/W
R/W
0h
0h
1 : Wide-bandwidth mode
Power-down control for analog input channels.
0 : Normal operation.
1 : Channels 1, 2, 3, and 4 powered down.
2 : Channels 5, 6, 7, and 8 powered down.
3 : All channels powered down,
7.5.2.32 Register C1h (offset = C1h) [reset = 0h]
图7-86. Register C1h
15
14
13
12
11
10
2
9
1
8
RESERVED
R/W-0h
PD_REF
R/W-0h
RESERVED
R/W-0h
DATA_RATE
R/W-0h
7
6
5
4
3
0
RESERVED
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-87. Register C1 Field Descriptions
Bit
Field
Type
Reset
Description
15-12
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
ADC reference voltage source selection.
0 : Intrenal reference enabled.
1 : Internal reference disabled. Connect external reference
voltage to REFIO pin.
11-11
PD_REF
R/W
0h
10-9
8-8
RESERVED
DATA_RATE
RESERVED
R/W
R/W
R/W
0h
0h
0h
Reserved. Do not change from default reset value.
Select data rate for the data interface.
0 : Double data rate (DDR)
1 : Single data rate (SDR)
7-4
Reserved. Do not change from default reset value.
Data output clock setting based on DATA_LANES and
DATA_WIDTH configuration.
0 : Configuration for 24-bit 2-lane and 48-bit 1-lane modes.
1 : Configuration for 20-bit 2-lane and 40-bit 1-lane modes.
3-0
DATA_CLK_CFG4
R/W
0h
7.5.2.33 Register C2h (offset = C2h) [reset = 0h]
图7-88. Register C2h
15
14
13
12
11
10
2
9
1
8
0
RANGE_CH4
R/W-0h
RANGE_CH3
R/W-0h
7
6
5
4
3
RANGE_CH2
RANGE_CH1
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图7-88. Register C2h (continued)
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-89. Register C2 Field Descriptions
Bit
Field
Type
Reset
Description
Select input voltage range for channel 4.
0 : 10 Vpp
1 : 7 Vpp
2 : 5 Vpp
3 : 14 Vpp
4 : 20 Vpp
5 : 24 Vpp
15-12
RANGE_CH4
R/W
0h
Select input voltage range for channel 3.
0 : 10 Vpp
1 : 7 Vpp
2 : 5 Vpp
3 : 14 Vpp
4 : 20 Vpp
5 : 24 Vpp
11-8
RANGE_CH3
RANGE_CH2
RANGE_CH1
R/W
R/W
R/W
0h
0h
0h
Select input voltage range for channel 2.
0 : 10 Vpp
1 : 7 Vpp
2 : 5 Vpp
3 : 14 Vpp
4 : 20 Vpp
5 : 24 Vpp
7-4
Select input voltage range for channel 1.
0 : 10 Vpp
1 : 7 Vpp
2 : 5 Vpp
3 : 14 Vpp
4 : 20 Vpp
5 : 24 Vpp
3-0
7.5.2.34 Register C3h (offset = C3h) [reset = 0h]
图7-90. Register C3h
15
14
13
12
11
10
2
9
1
8
0
RANGE_CH8
R/W-0h
RANGE_CH7
R/W-0h
7
6
5
4
3
RANGE_CH6
R/W-0h
RANGE_CH5
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-91. Register C3 Field Descriptions
Bit
Field
Type
Reset
Description
Select input voltage range for channel 8.
0 : 10 Vpp
1 : 7 Vpp
2 : 5 Vpp
3 : 14 Vpp
4 : 20 Vpp
5 : 24 Vpp
15-12
RANGE_CH8
R/W
0h
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图7-91. Register C3 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
Select input voltage range for channel 7.
0 : 10 Vpp
1 : 7 Vpp
2 : 5 Vpp
3 : 14 Vpp
4 : 20 Vpp
5 : 24 Vpp
11-8
RANGE_CH7
R/W
0h
Select input voltage range for channel 6.
0 : 10 Vpp
1 : 7 Vpp
2 : 5 Vpp
3 : 14 Vpp
4 : 20 Vpp
5 : 24 Vpp
7-4
3-0
RANGE_CH6
RANGE_CH5
R/W
R/W
0h
0h
Select input voltage range for channel 5.
0 : 10 Vpp
1 : 7 Vpp
2 : 5 Vpp
3 : 14 Vpp
4 : 20 Vpp
5 : 24 Vpp
7.5.2.35 Register C4h (offset = C4h) [reset = 0h]
图7-92. Register C4h
15
14
13
12
11
10
2
9
1
8
RESERVED
R/W-0h
CM_ADC_B
R/W-0h
7
6
5
4
3
0
CM_ADC_A
R/W-0h
DATA_CLK_CFG3
R/W-0h
WIDE_CM_EN2
R/W-0h
RESERVED
R/W-0h
PD_CHIP
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-93. Register C4 Field Descriptions
Bit
Field
Type
Reset
Description
15-10
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Common-mode range for channels 5, 6, 7, and 8.
0 : CM range equal to ±RANGE/2 for respective channels.
1 : CM range equal to ±6 V for channels 5, 6, 7, and 8.
2 : CM range equal to ±12 V for channels 5, 6, 7, and 8.
9-8
7-6
5-4
CM_ADC_B
CM_ADC_A
R/W
R/W
R/W
0h
0h
0h
Common-mode range for channels 1, 2, 3, and 4.
0 : CM range equal to ±RANGE/2 for respective channels.
1 : CM range equal to ±6 V for channels 1, 2, 3, and 4.
2 : CM range equal to ±12 V for channels 1, 2, 3, and 4.
Data output clock setting based on DATA_LANES and
DATA_WIDTH configuration.
0 : Configuration for 24-bit 2-lane mode.
1 : Configuration for 48-bit 1-lane mode.
DATA_CLK_CFG3
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Bit
图7-93. Register C4 Field Descriptions (continued)
Field
Type
Reset
Description
Enable wide-common-mode range control for all analog
input channels.
0 : Wide-common-mode range control disabled for all
channels.
1 : Wide-common-mode range control enabled for channels
1, 2, 3, and 4.
3-2
WIDE_CM_EN2
R/W
0h
2 : Wide-common-mode range control enabled for channels
5, 6, 7 and 8.
3 : Wide-common-mode range control enabled for all
channels.
1-1
0-0
RESERVED
PD_CHIP
R/W
R/W
0h
0h
Reserved. Do not change from default reset value.
Full chip power-down control.
0 : Normal device operation.
1 : Full device powered-down.
7.5.2.36 Register C5h (offset = C5h) [reset = 0h]
图7-94. Register C5h
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R/W-0h
7
6
5
4
3
RESERVED
WIDE_CM_EN1
R/W-0h
RESERVED
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
图7-95. Register C5 Field Descriptions
Bit
Field
Type
Reset
Description
15-5
RESERVED
R/W
0h
Reserved. Do not change from default reset value.
Enable wide-common-mode range control for all analog
input channels.
4-4
3-0
WIDE_CM_EN1
RESERVED
R/W
R/W
0h
0h
0 : CM range for all analg input channels will be ±12 V.
1 : CM range will be user-defined in registers
WIDE_CM_EN2, CM_ADC_A, and CM_ADC_B.
Reserved. Do not change from default reset value.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The following section gives an example circuit and recommendations for using the ADS9817 in a data
acquisition (DAQ) system. The ADS9817 includes an integrated analog front-end for each input channel and an
integrated precision reference with a buffer. As such, this device family does not require any additional external
circuits for driving the reference or analog input pins of the ADC.
8.2 Typical Application
8.2.1 Data Acquisition (DAQ) System
Analog supply
(5 V)
1.8 V Supply
Internal
reference
(4.096 V)
C8
0.1 ꢀF
C2
1 ꢀF
C5
0.1 ꢀF
C7
10 ꢀF
Sync signal to select Ch1 and Ch5
Sampling clock for ADC (8-/4-MHz)
ADC input Ch1
U1
C10
0.1 ꢀF
1
2
3
4
5
6
7
8
42
IOVDD 41
AIN2P
AIN2M
AIN3P
AIN3M
IOGND
ADC input Ch2
IO supply
(1.2 V to 1.8 V)
FCLKOUT
NC
40
39
ADC input Ch3
ADC input Ch4
AIN4P
AIN4M
AGND
NC 38
D3
D2
D1
D0
37
36
35
Data
Interface
Thermal
Pad
REFM
AIN5P
9
34
ADC input Ch5
10
11
12
13
14
DCLKOUT 33
AIN5M
AIN6P
32
31
30
29
Power-down control
Device reset
PWDN
RESET
ADC input Ch6
ADC input Ch7
ADS9817
AIN6M
AIN7P
AIN7M
IO supply
(1.2 V to 1.8 V)
IOVDD
IOGND
C11
0.1 ꢀF
ADC input Ch8
Configuration
SPI
Interface
Enable
configuration SPI
interface
C6
1.8 V Supply
10 ꢀF
2.5 V reference
output
C1
0.1 ꢀF
Analog supply
(5 V)
C4
0.1 ꢀF
C3
1 ꢀF
图8-1. Recommended Schematic
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8.2.2 Design Requirements
The goal of this application is to design an 8-channel data acquisition system (DAQ) based on the ADS9817 and
ADS9818 with internal reference. 表8-1 lists the parameters for this design.
表8-1. Design Parameters
PARAMETER
VALUE
Sampling rate
ADC reference
Up to 2 MSPS/channel
Internal, 4.096 V
ADC analog input type
ADC analog input range
Pseudo-differential
{–1.5 V to +4.5 V} or {–5 V to +5 V}
Up to 200 Ω
Output impedance of the source driving the ADC analog inputs
8.2.3 Detailed Design Procedure
8.2.3.1 CMOS Data Interface
The ADS981x features a high-speed CMOS serial interface for ADC data output. ADC data are launched on
D[3:0] and the corresponding data clock is launched on DCLKOUT. The DCLKOUT frequency is 192 MHz for 2
MSPS/channel sampling rate (24x SMPL_CLK; SMPL_CLK = 8 MHz).
High-speed CMOS switching can create ground bounce that adversely impacts the SNR of the ADC. The ground
bounce increments with increase in PCB trace capacitance. Minimize the PCB trace length for D[3:0] and
DCLKOUT. Place a CMOS buffer, with low input capacitance, close to the ADS981x to minimize the effect of
CMOS switching noise.
8.3 Power Supply Recommendations
The ADS981x has four separate power supplies: AVDD_5V, AVDD_1V8, DVDD_1V8, and IOVDD. There is no
requirement for a specific power-up sequence. The internal analog circuits operate on AVDD_5V and
AVDD_1V8, DVDD_1V8 is used for the digital circuits. The data and configuration digital interfaces are powered
by IOVDD. A common 1.8-V supply powers the AVDD_1V8, DVDD_1V8, and IOVDD pins. 图 8-2 shows the
decoupling capacitor connections for the respective power supplies. Each power supply pin must have separate
decoupling capacitors.
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Analog supply
(5 V)
AVDD_5V
GND
0.1 ꢀF
1 ꢀF
Analog supply
(1.8 V)
AVDD_1V8
DVDD_1V8
IOVDD
IOGND
0.1 ꢀF
1 ꢀF
Digital supply
(1.8 V)
0.1 ꢀF
1 ꢀF
IO supply
(1.2 V to 1.8 V)
0.1 ꢀF
1 ꢀF
图8-2. Power-Supply Decoupling
8.4 Layout
8.4.1 Layout Guidelines
图 8-3 shows a board layout example for the ADS981x. Avoid crossing digital lines with the analog signal path
and keep the analog input signals and the reference signals away from noise sources.
Use 0.1-μF ceramic bypass capacitors in close proximity to the analog (AVDD_5V and AVDD_1V8), digital
(DVDD_1V8), and digital interface (IOVDD) power-supply pins. Avoid placing vias between the power-supply
pins and the bypass capacitors.
Place the reference decoupling capacitor close to the device REFIO and REFM pins. Avoid placing vias between
the REFIO pin and the bypass capacitors. Connect the GND, REFM, and IOGND pins to a ground plane using
short, low-impedance paths.
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8.4.2 Layout Example
图8-3. Example Layout
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9 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
9.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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15-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PADS9817RSHT
ACTIVE
VQFN
RSH
56
250
TBD
Call TI
Call TI
-40 to 125
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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