AFE2124_技术文档

®

AFE2124

For most current data sheet and other product

information, visit www.burr-brown.com

Dual HDSL/SDSL ANALOG FRONT END

FEATURES

● SERIAL DIGITAL INTERFACE

DESCRIPTION

Burr-Brown’s dual Analog Front End chip greatly re-

duces the size and cost of a DSL (Digital Subscriber

Line) system by providing all of the active analog

circuitry needed to connect two digital signal processors

to external compromise hybrids and line transformers.

The AFE2124 is optimized for HDSL (High bit rate

DSL) and for SDSL (symmetrical DSL) applications.

Because the transmit and receive filter responses auto-

matically change with clock frequency, the AFE2124 is

particularly suitable for multiple rate DSL systems. The

device operates over a wide range of data rates from

64kbps to 1168kbps.

● 48-LEAD SSOP PACKAGE

● E1, T1 AND SDSL OPERATION

● 64kbps TO 1168kbps OPERATION

● SCALEABLE DATA RATE

● 250mW POWER DISSIPATION PER

CHANNEL

● TWO COMPLETE HDSL ANALOG INTER-

FACES

● +5V POWER (5V or 3.3V Digital)

Functionally, each half of this unit consists of a transmit

and a receive section. The transmit section generates

analog signals from 2-bit digital symbol data and filters

the analog signals to create 2B1Q symbols. The on-

board differential line driver provides a 13.5dBm signal

to the telephone line. The receive section filters and

digitizes the symbol data received on the telephone line.

This IC operates on a single 5V supply. The digital

circuitry in the unit can be connected to a supply from

3.3V to 5V. It is housed in a 48-lead SSOP package.

txLINE

Pulse Former

txLINE

Line Driver

tx and rx

Control

Registers

tx and rx

Interface

Lines

Difference

Amplifier

rxHYB

rxLINE

Decimation

Filter

∆Σ

Modulator

rxLINE

Programmable

Gain Amp

1/2 of AFE2124

Patents Pending

International Airport Industrial Park

•

Mailing Address: PO Box 11400, Tucson, AZ 85734

•

Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706

• Tel: (520) 746-1111

Twx: 910-952-1111

•

Internet: http://www.burr-brown.com/

•

Cable: BBRCORP Telex: 066-6491

•

FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132

•

PDS-1538A

Printed in U.S.A. April, 1999

SBWS010

SPECIFICATIONS

Typical at 25°C, AV_DD= +5V, DV_DD= +3.3V, and txBaudCLK = 584kHz (E1 rate), unless otherwise noted.Specifications apply to each channel of the AFE2124.

AFE2124E

PARAMETER

RESOLUTION

COMMENTS

MIN

TYP

MAX

UNITS

14

Bits

RECEIVE CHANNEL

Number of Inputs

Input Voltage Range

Common-Mode Voltage

Input Impedance All Inputs

Input Capacitance

Differential

Balanced Differential⁽¹⁾

2

±3.0

AV_DD/2

V

See Typical Performance Curves

10

±2

pF

%

Input Gain Matching

Programmable Gain

Settling Time

Line Input vs Hybrid Input

0dB, 3dB, 6dB, 9dB and 12dB

For Any Change in Gain or txBaud CLK

Tested at Each Gain Range

Two’s Complement

0

+12

dB

6

5

Symbol Periods

%FSR⁽²⁾

Gain + Offset Error

Output Data Coding

Output Symbol Rate, rxSYNC⁽³⁾

Output Bit Rate, rxSYNC⁽³⁾

32

64

584

1168

kHz

kbits/sec

TRANSMIT CHANNEL

Transmit Clock Rate, txBaudCLK

T1 Transmit –3dB Point

T1 Rate Power^{(4, 5)}

E1 Transmit –3dB Point

E1 Transmit Power^{(4, 5)}

Pulse Output

Symbol Rate

ETSI RTR/TM - Compliant

txBoost = 0

ETSI RTR/TM - Compliant

txBoost = 0

32

13

584

14

kHz

dBm

kHz

dBm

196

292

14

See Typical Performance Curves

Common-Mode Voltage, V_CM

Output Resistance⁽⁶⁾

AV_DD/2

1

V

Ω

DC to 1MHz

TRANSCEIVER PERFORMANCE

Uncancelled Echo⁽⁵⁾

rxGAIN = 0dB, Loopback Enabled

rxGAIN = 0dB, Loopback Disabled

rxGAIN = 3dB, Loopback Disabled

rxGAIN = 6dB, Loopback Disabled

rxGAIN = 9dB, Loopback Disabled

rxGAIN = 12dB, Loopback Disabled

–71

–74

–76

–78

–80

–68.5

–71

–73.5

–75.5

–77.5

dB

DIGITAL INTERFACE⁽⁶⁾

Logic Levels

V_IH

V_IL

V_OH

V_OL

|I_IH| < 10µA

|I_IL| < 10µA

I_OH= –20µA

I_OL= 20µA

DV_DD– 1

–0.3

DV_DD– 0.5

DV_DD+ 0.3

+0.8

V

ns

+0.4

14

t_rx1Interface

9

POWER

Analog Power Supply Voltage

Digital Power Supply Voltage

Power Dissipation^{(4, 5)}

Specification

Operating Range

Specification

5

V

4.75

3.15

5.25

3.3

Operating Range

AV_DD= 5V, DV_DD= 3.3V,

AV_DD= DV_DD= 5V

V

250

300

55

mW

dB

Power Dissipation^{(4, 5)}

Power Supply Rejection Ratio (PSRR)

TEMPERATURE RANGE

Operating⁽⁶⁾

–40

+85

°C

NOTES: (1) With a balanced differential signal, the positive input is 180° out of phase with the negative input, therefore, the actual voltage swing about the common-

mode voltage on each pin is ±1.5V to achieve a total input range of ±3.0V or 6Vp-p. (2) FSR is Full-Scale Range. (3) The output data is available at twice the symbol

rate. (4) With a pseudo-random equiprobable sequence of HDSL pulses; 13.5dBm applied to the transformer (16.5dBm output from txLINEP and txLINEN). (5) See

the Discussion of Specifications section of this data sheet for more information. (6) Guaranteed by design and characterization.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN

assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject

to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not

authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

®

AFE2124

2

ABSOLUTE MAXIMUM RATINGS

ELECTROSTATIC

DISCHARGE SENSITIVITY

Analog Inputs: Current .............................................. ±100mA, Momentary

±10mA, Continuous

Voltage.................................. AGND –0.3V to AV_DD+0.3V

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

Analog Outputs Short Circuit to Ground (+25°C) ..................... Continuous

AV_DDto AGND .........................................................................–0.3V to 6V

DV_DDto DGND.........................................................................–0.3V to 6V

Digital Input Voltage to DGND .................................. –0.3V to DV_DD+0.3V

Digital Output Voltage to DGND ............................... –0.3V to DV_DD+0.3V

AGND, DGND, Differential Voltage .................................................... 0.3V

Junction Temperature (T_J) ............................................................. +150°C

Storage Temperature Range .......................................... –40°C to +125°C

Lead Temperature (soldering, 3s).................................................. +260°C

Power Dissipation .......................................................................... 700mW

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

PACKAGE/ORDERING INFORMATION

PACKAGE

DRAWING

NUMBER⁽¹⁾

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER⁽²⁾

TRANSPORT

MEDIA

PRODUCT

PACKAGE

AFE2124E

SSOP-48

333

–40°C to +85°C

AFE2124E

Rails

"

AFE2124E/1K

Tape and Reel

NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are

available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “AFE2124E/1K” will get a single 1000-

piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.

BLOCK DIAGRAM

1/2

AFE2124

txLINE+

txLINE–

Pulse

Former

Filter

Output

Buffer

REF

P

txbaudCLK

tx48xCLK

Data In

Voltage

Reference

V

CM

Transmit

Control

REF

N

rxbaudCLK

rx48xCLK

Data Out

Receive

Control

rxLINE+

rxLINE–

rxHYB+

rxHYB–

∆Σ

Modulator

Decimation

Filter

®

3

AFE2124

PIN CONFIGURATION

PIN DESCRIPTIONS

Top View

SSOP

PIN #

TYPE

NAME

DESCRIPTION

CHANNEL A

1

2

Output

Input

Data OutA

rx48xCLKA

Output Data Word

Receive Clock at 48x Baud Clock

(23.032MHz for E1)

Data OutA

rx48xCLKA

rxbaudCLKA

Data InA

1

2

3

4

5

6

7

8

9

48 Data OutB

3

4

5

6

Input

rxbaudCLKA

Data InA

Receive Baud Clock (584kHz for E1)

Input Data Word

47 rx48xCLKB

46 rxbaudCLKB

45 Data InB

44 tx48xCLKB

43 txbaudCLKB

42 DV_DD

tx48xCLKA

txbaudCLKA

Transmit Clock (584kHz for E1)

Transmit Baud Clock at 48x Baud Clock

(584kHz for E1)

tx48xCLKA

txbaudCLKA

DV_DD

7

Power

Ground

Output

Power

Output

Ground

Power

Output

Ground

Input

DV_DD

DGND

AGND

txLINE+A

AV_DD

Digital Supply (+3.3V to +5V)

Digital Ground

8

9

Analog Ground

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

Transmit Line Driver Output, Positive

Analog Supply (+5V)

DGND

41 DGND

AGND

40 AGND

txLINE–A

AGND

AV_DD

Transmit Line Driver Output, Negative

Analog Ground

txLINE+A 10

AV_DD11

39 txLINE+B

38 AV_DD

Analog Supply (+5V)

REF_NA

Negative Reference Output

Common-Mode Voltage (buffered)

Positive Reference Output

Analog Ground

txLINE–A 12

AGND 13

AV_DD14

37 txLINE–B

36 AGND

AFE2124

Channel A Channel B

V_CM

A

REF_PA

AGND

35 AV_DD

AGND

Analog Ground

REF_NA 15

34 REF_NB

rxLINE+A

rxLINE–A

rxHYB+A

rxHYB–A

AV_DD

Positive Line Input

V

_CMA 16

33

V_CMB

Input

Negative Line Input

REF_PA 17

AGND 18

32 REF_PB

31 AGND

Input

Positive Input from Hybrid Network

Negative Input from Hybrid Network

Analog Supply (+5V)

Input

Power

AGND 19

30 AGND

AV_DD

Analog Supply (+5V)

rxLINE+A 20

rxLINE–A 21

rxHYB+A 22

rxHYB–A 23

AV_DD24

29 rxLINE+B

28 rxLINE–B

27 rxHYB+B

26 rxHYB–B

25 AV_DD

CHANNEL B

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

Input

rxHYB–B

rxHYB+B

rxLINE–B

rxLINE+B

AGND

Negative Input from Hybrid Network

Positive Input from Hybrid Network

Negative Line Input

Input

Postiive Line Input

Ground

Output

Power

Ground

Output

Power

Output

Ground

Power

Input

Analog Ground

AGND

Analog Ground

REF_PB

Positive Reference Output

Common-Mode Voltage (buffered)

Negative Reference Output

Analog Supply (+5V)

V_CM

B

REF_NB

AV_DD

AGND

Analog Ground

txLINE–B

AV_DD

Transmit LIne Driver Output, Negative

Analog Supply (+5V)

txLINE+B

AGND

Transmit Line Driver Output, Positive

Analog Ground

DGND

Digital Ground

DV_DD

Digital Supply (+3.3V to +5V)

Transmit Baud Clock (584kHz for E1)

txbaudCLKB

tx48xCLKB

Input

Transmit Clock at 48x Baud Clock

(28.032MHz for E1)

45

46

47

Input

Data InB

rxbaudCLKB

rx48xCLKB

Input Data Word

Receive Baud Clock (584kHz for E1)

Receive Clock at 48x Baud Clock

(28.032MHz for E1)

48

Output

Data OutB

Output Data Word

®

AFE2124

4

TYPICAL PERFORMANCE CURVES

At Output of HDSL Pulse Transformer

The curves shown below are measured at the line output of the HDSL transformer. Typical at 25°C, AV_DD+ = +5V, DV_DD+ = +3.3V, txBaudCLK = 584kHz (E1),

unless otherwise specified.

POWER SPECTRAL DENSITY LIMIT

–20

–38dBm/Hz for T1

–40

–80dB/decade

T1

–40dBm/Hz for E1

E1

–60

–80

–118dBm/Hz

for T1

196kHz

292kHz

–120dBm/Hz

for E1

–100

–120

1K

10K

100K

Frequency (Hz)

1M

10M

CURVE 1. Upper Bound of Power Spectral Density Measured at Output of HDSL Transformer.

0.4T 0.4T

B = 1.07

C = 1.00

D = 0.93

1.25T

A = 0.01

E = 0.03

A = 0.01

F = –0.01

H = –0.05

14T

F = –0.01

–1.2T

50T

G = –0.16

–0.6T 0.5T

CURVE 2. Transmitted Pulse Template Measured at HDSL Transformer Output.

INPUT IMPEDANCE vs BIT RATE

200

150

100

T1 = 784kbps,

32kΩ

E1 = 1168kbps,

50

0

21kΩ

100

300

500

700

900

1100

1300

Bit Rate (kbps)

CURVE 3. Input Impedance of rxLINE and rxHYB.

®

5

AFE2124

oversampling ratio, produces a 14-bit output at rates up to

584kHz (1.168Mbps).

THEORY OF OPERATION

The AFE2124 has two HDSL Analog Front End (AFE)

circuits on chip (channel A and channel B). Each AFE is

functionally equivalent to an AFE1124. Each AFE consists

of a transmit and a receive channel which interfaces to a

HDSL DSP through a six-wire serial interface—three wires

for the transmit channel and three wires for the receive

channel. It interfaces to the HDSL telephone line trans-

former and external compromise hybrid through transmit

and receive analog connections.

The receive channel operates by summing the two differen-

tial inputs, one from the line (rxLINE) and the other from the

compromise hybrid (rxHYB). The connection of these two

inputs so that the hybrid signal is subtracted from the line

signal is described in the paragraph titled “Echo Cancella-

tion in the AFE.” The equivalent gain for each input in the

difference amp is one. The resulting signal then passes to a

programmable gain amplifier which can be set for gains of

0dB through +12dB. Following the PGA, the ADC converts

the signal to a 14-bit digital word.

The transmit channel consists of a switched-capacitor pulse

forming network followed by a differential line driver. The

pulse-forming network receives 2-bit digital symbol data

and generates a filtered 2B1Q analog output waveform. The

differential line driver uses a composite output stage com-

bining class B operation (for high efficiency driving large

signals) with class AB operation (to minimize crossover

distortion).

The serial interface consists of three wires for transmit and

three wires for receive. The three-wire transmit interface is

transmit baud rate clock, transmit 48x oversampling clock

and Data Out. The three-wire receive interface is receive

baud rate clock, receive 48x oversampling clock and Data

In. The transmit and receive clocks are supplied to the

AFE2124 from the DSP and are completely independent.

The receive channel is designed around a fourth-order delta

sigma analog-to-digital converter. It includes a difference

amplifier designed to be used with an external compromise

hybrid for first-order analog echo cancellation. A program-

mable gain amplifier with gains of 0dB to +12dB is also

included. The delta sigma modulator, operating at a 24x

DIGITAL DATA INTERFACE

Data is received by the AFE2124 from the DSP on the Data

In line. Data is transmitted from the AFE2124 to the DSP on

the Data Out line. The following paragraphs describe the

timing of these signals and data structure.

rxbaudCLK

rx48xCLK

Data Out

txbaudCLK

tx48xCLK

Data In

1/2

AFE2124

HDSL

DSP

FIGURE 1. DSP Interface.

4ns

txbaudCLK

from DSP

A

B

4ns

tx48xCLK

from DSP

48

1

2

3

4

15

16

47

48

1

Data In

from DSP

MSB

Bit 15

LSB

Bit 0

MSB

Bit 15

Transmit Timing Notes: (1) A baud period consists of 48 periods of the tx48xCLK. (2) The falling edge of the txbaudCLK

can occur anywhere in area A. The rising edge can occur anywhere in area B. However, neither edge of the txbaudCLK

can occur within 4ns (on either side) of any rising edge of tx48xCLK. (3) The AFE2124 reads Data In on the rising edge

of the tx48xCLK. Data In must be stable at least 4ns before the rising edge of tx48xCLK and it must remain stable at

least 4ns after the rising edge of tx48xCLK. (4) Symbol data is transferred to the transmit pulse former after the LSB is

read. The output analog symbol data reaches the peak of the symbol approximately 24 tx48xCLK periods later.

FIGURE 2. Transmit Timing Diagram.

®

AFE2124

6

Data is transmitted and received in synchronization with the

48x transmit and receive clocks (tx48xCLK and rx48xCLK).

There are 48-bit times in each baud period. Data In is

received in the first 16 bits of each baud period. The

remaining 32-bit periods are not used for Data In. Data Out

is transmitted during the first 16 bits of the baud period. A

second interpolated value is transmitted in subsequent bits of

the baud period.

and other control bits, as described below. The data should

be clocked out of the DSP on the falling edge and should be

valid on the rising edge of the tx48xCLK. The AFE2124

reads Data In on the rising edge of the tx48xCLK. The bits

are defined in Table I. Data In is read by the AFE2124

during the first 16 bits periods of each baud period. Only the

first 8 bits are used in the AFE2124. The second 8 bits are

reserved for use in the future products. The remaining 32

bits periods of the baud period are not used for Data In.

txbaudCLK: The transmit data baud rate, generated by the

DSP. It is 392kHz for T1 or 584kHz for E1. It may vary from

32kHz (64kbps) to 584kHz (1.168Mbps).

Data In Bits

tx Enable Signal—This bit controls the tx Symbol defini-

tion bits. If this bit is 0, only a 0 symbol is transmitted

regardless of the state of the tx Symbol definition bits. If this

bit is 1, the tx Symbol definition bits determine the output

symbol.

tx48xCLK: The transmit pulse former oversampling sam-

pling clock, generated by the DSP. It is 48x the transmit

symbol rate or 28.032MHz for 584kHz symbol rate. This

clock should run continuously.

Data In: This is a 16-bit output data word sent from the DSP

tx Symbol Definition—These two bits determine the output

to the AFE. The sixteen bits include tx symbol information

2B1Q symbol transmitted.

MSB

LSB

1

2

3

1

8

Reserved

tx Boost

Loopback

rx Gain

tx Symbol

tx Enable

FIGURE 3. Data In Word.

4ns

rxbaudCLK

A

B

from DSP

4ns

14

rx48xCLK

from DSP

48

1

15

16

17

23

24

25

26

39

40

47

48

1

Data Out

from AFE2124

MSB

Bit 15

LSB

Bit 0

MSB

Bit 15

LSB

Bit 0

MSB

Bit 15

t_rx1

Data 1

Interdata 8 Bits

Data 1a

Data 2

Receive Timing Notes: (1) A baud period consists of 48 periods of the tx48xCLK. (2) The falling edge of the rxbaudCLK

can occur anywhere in area A. The rising edge can occur anywhere in area B. However, neither edge of the

rxbaudCLK can occur within 4ns (on either side) of any rising edge of rx48xCLK. (3) For all data bits after the MSB of

Data 1, the AFE2124 transfers Data Out on the falling edge of the rx48xCLK. The time from the falling edge of

rx48xCLK until Data Out is stable is t_rx1

.

min

9ns

max

t_rx1

14ns

(4) The AFE2124 transfers the MSB of Data 1 on the falling edge of rxbaudCLK. If the falling edge of rxbaudCLK is

synchronized with the falling edge of rx48xCLK, all of the Data Out bits will be the same width. In any case, the time

from the falling edge of rxbaudCLK until the MSB of Data 1 is stable is t_rx1

.

FIGURE 4. Receive Timing Diagram.

®

7

AFE2124

DATA OUT PER SYMBOL PERIOD

DATA

BIT

DESCRIPTION BIT STATE

OUTPUT STATE

BITS

15 (MSB) tx Enable Signal

0

1

AFE Transmits a 0 Symbol

AFE Transmits HDSL Symbol

as defined by bits 14 and 13

Data 1

Interdata Bits

16

8

14 and 13

tx Symbol

Definition

00

–3 Transmit Symbol

Data 1a

16

8

01

11

10

–1 Transmit Symbol

+1 Transmit Symbol

+3 Transmit Symbol

Interdata bits

Total Bits/Symbol Period

48

12 - 10

rx Gain Settings

000

001

010

011

100

101

110

111

rx gain in AFE 0dB

rx gain in AFE 3dB

rx gain in AFE 6dB

rx gain in AFE 9dB

MSB

LSB

rx gain in AFE 12dB

rx gain in AFE Reserved

14

2

9

8

Loopback Control

tx Boost

1

0

Loopback Mode

Normal Operation

Reserved

0

1

Normal Transmit Power

+0.5dB Transmit Power Boost

A/D Converter Data

7 - 0

SPARE

NA

FIGURE 5. Data Out Word.

TABLE I. Data In.

ANALOG-TO-DIGITAL CONVERTER DATA

The A/D converter data from the receive channel is coded in

Binary Two’s Complement.

Rx Gain Settings—These bits set the gain of the receive

channel programmable gain amplifier.

Loopback Control—This bit controls the operation of

loopback. When enabled (logic 1), the rxLINE+ and rxLINE–

inputs are disconnected from the AFE. The rxHYB+ and

rxHYB– inputs remain connected. When disabled, the

rxLINE+ and rxLINE– inputs are connected.

ANALOG INPUT

A/D CONVERTER DATA

MSB

LSB

Positive Full Scale

Mid Scale

01111111111111

00000000000000

10000000000000

Negative Full Scale

txBoost—This bit controls the addition of 0.5dB additional

power to the output line driver.

rxbaudCLK: This is the receive data baud rate (symbol

clock), generated by the DSP. It is 392kHz for T1 or 584kHz

for E1. It can vary from 32kHz (64kbps) to 584kHz

(1.168Mbps).

ECHO CANCELLATION IN THE AFE

The rxHYB input is subtracted from the rxLINE input for

first order echo cancellation. For correct operation, be cer-

tain that the rxLINE input is connected to the same polarity

signal at the transformer (+ to + and – to –) while the rxHYB

input is connected to opposite polarity through the compro-

mise hybrid (– to + and + to –) as shown in Figure 6.

rx48xCLK: This is the A/D converter oversampling clock,

generated by the DSP. It is 48x the receive symbol rate or

28.032MHz for 584kHz symbol rate. This clock should run

continuously.

Data Out: This is the 14-bit A/D converter output data (+2

spare bits) sent from the AFE to the DSP. The 14 bits from

the A/D Converter will be the upper bits of the 16-bit word

(bits 15-2). The spare bits (1 and 0) will be always be low.

Eight additional (interdata) bits follow, which are always

high. The data is clocked out on the falling edge of rx48xCLK.

The bandwidth of the A/D converter decimation filter is

equal to one-half of the symbol rate. The nominal output

rate of the A/D converter is one conversion per symbol

period. For more flexible post processing, there is a second

true A/D conversion available in each symbol period. In

Figure 4, the first conversion is shown as Data 1 and the

second conversion is shown as Data 1a. It is suggested that

rxbaudCLK is used with the rx48xCLK to read Data 1

while Data 1a is ignored. However, either or both outputs

may be used for more flexible post-processing.

SCALEABLE TIMING

The AFE2124 scales operation with the clock frequency. All

internal filters and the pulse former change frequency with

the clock speed so that the unit can be used at different

frequencies just by changing the clock speed.

For the receive channel, the digital filtering of the delta

sigma converter scales directly with the clock speed. The

bandwidth of the converter’s decimation filter is always one-

half of the symbol rate. The only receive channel issue in

changing baud rate is the passive single pole anti-alias filter

(see the “rxHYB and rxLINE Input Anti-Aliasing Filters”

section). For systems implementing a broad range of speeds,

selectable cutoff frequencies for the passive anti-alias filter

should be used.

®

AFE2124

8

0.1µF

REF_P

V_CM

REF_N

1:2 Transformer

Tip

13Ω

txLINE+

txLINE–

0.01µF

Ring

–

+

0.01µF

Input Antialias Filter

fc 2 x Symbol Rate

Compromise

Hybrid

–

750Ω

rxbaudCLK

rx48xCLK

Data Out

txbaudCLK

tx48xCLK

Data In

rxHYB+

1/2

AFE2124

100pF

HDSL DSP

750Ω

rxHYB–

rxLINE–

750Ω

100pF

GNDA

750Ω

rxLINE+

DV_DDDV_DD

AV_DDAV_DDAV_DD

5V to 3.3V Digital

0.1µF

5V Analog

0.1µF 0.1µF 0.1µF

1 - 10µF

0.1µF

FIGURE 6. Basic Connection Diagram for Each Channel of the AFE2124.

For the transmit channel, the pulse shape and the power

spectral density scale directly with the clock rate. The power

spectral density shown in Curve 1 and the pulse template

shown in Curve 2 are measured at the output of the trans-

former. The transformer and the RC circuit on the output

provide some smoothing for the output transmission. At

lower bit rates, the amount of smoothing will be less.

differential inputs should be approximately 1MHz for T1

and E1 symbol rates. Suggested values for the filter are

750Ω for each of the two input resistors and 100pF for the

capacitor. Together, the two 750Ω resistors and the 100pF

capacitor result in a 3dB frequency of just over 1MHz. The

750Ω input resistors will result in minimal voltage divider

loss with the input impedance of the AFE2124.

The anti-aliasing filters will give best performance with 3dB

frequency approximately equal to the bit rate. For example,

a 3dB frequency of 320kHz may be used for a single line bit

rate of 320k bits per second.

rxHYB AND rxLINE INPUT

ANTI-ALIASING FILTERS

An external input antialiasing filter is needed on the hybrid

and line inputs as shown in Figure 6. The –3dB frequency of

the input anti-aliasing filter for the rxLINE and rxHYB

®

9

AFE2124

change with clock frequency. However, the power dissipa-

tion in the digital circuitry does decrease with lower clock

frequency. In addition, the power dissipation in the digital

section is decreased when operating from a smaller supply

voltage, such as 3.3V. (The analog supply, AV_DD, must

remain in the range 4.75V to 5.25V).

DISCUSSION OF

SPECIFICATIONS

UNCANCELED ECHO

A key measure of transceiver performance is uncancelled

echo. Uncancelled echo is the summation of all of the errors

in the transmit and receive paths of the AFE2124. It includes

effects of linearity, distortion and noise. Uncancelled echo is

tested in production by Burr-Brown with a circuit that is

similar to the one shown in Figure 7.

The power dissipation listed in the Specifications Table

applies under these normal operating conditions: 5V analog

power supply; 3.3V digital power supply; standard 13.5dBm

delivered to the line; and a pseudo-random equiprobable

sequence of HDSL output pulses. The power dissipation

specifications includes all power dissipated in the AFE2124;

however, it does not include power dissipated in the exter-

nal load. The external power is 16.5dBm, 13.5dBm to the

line, and 13.5dBm to the impedance matching resistors. The

external load power of 16.5dBm is 45mW. The typical

power dissipation for each half of the AFE2124 under

various conditions is shown in Table II.

The measurement of uncancelled echo is made as follows:

The AFE is connected to an output circuit including a typical

1:2 line transformer. The line is simulated by a 135Ω

resistor. Symbol sequences are generated by the tester and

applied both to the AFE and to the input of an adaptive filter.

The output of the adaptive filter is subtracted from the AFE

output to form the uncanceled echo signal. Once the filter

taps have converged, the RMS value of the uncancelled echo

is calculated. Since there is no far-end signal source or

additive line noise, the uncanceled echo contains only noise

and linearity errors generated in the transmit and receive

sections of the AFE2124.

The T1 and E1 power measurements in the Specifications

are made with the output circuit shown in Figure 7. This

circuit uses a 1:2 transformer. The power measurements

shown in Table II use an equivalent resistive load instead of

the transformer to eliminate frequency dependent imped-

ances of the transformer.

The data sheet value for uncancelled echo is the ratio of

the rms uncanceled echo (referred to the receiver input

through the receiver gain) to the nominal transmitted signal

(13.5dBm into 135Ω, or 1.74Vrms). This echo value is

measured under a variety of conditions: with loopback

enabled (line input disconnected); with loopback disabled

under all receiver gain ranges; and with the line shorted (S₁

closed in Figure 7).

TYPICAL POWER DISSIPATION

BIT RATE

(symbols/sec)

DV

(V)

IN THE AFE2124 (per channel)

(mW)

DD

584 (E1)

392 (T1)

146 (E1/4)

+3.3

+5

250

300

240

270

230

245

+3.3

+5

+3.3

+5

POWER DISSIPATION

Approximately 80% of the power dissipation in the AFE2124

is in the analog circuitry, and this component does not

TABLE II. Typical Power Dissipation (per channel).

13Ω

1:2

5.6Ω

Transmit

Data

txDAT_P

txLINE_P

txLINE_N

rxHYB_P

135Ω

S₁

1.5kΩ

1/2

AFE2124

3kΩ

100pF

rxHYB_N

1.5Ω

750Ω

rxLINE_P

rxLINE_N

100pF

750Ω

Uncancelled

Echo

rxD13 - rxD0

FIGURE 7. Uncancelled Echo Test Diagram.

®

AFE2124

10

plane underneath all digital pins is strongly recommended.

LAYOUT

The remaining portion of the AFE2124 should be considered

analog. All AGND pins should be connected directly to a

common analog ground plane and all AV_DDpins should be

connected to an analog 5V power plane. Both of these planes

should have a low impedance path to the power supply. The

analog power supply pins should be decoupled to analog

ground with ceramic 0.1µF capacitors placed as close to the

AFE2124 as possible. One 10µF tantalum capacitor should

also be used with each AFE2124 between the analog supply

and analog ground.

The analog front end of an HDSL system has two conflicting

requirements. It must accept and deliver moderately high

rate digital signals and it must generate, drive, and convert

precision analog signals. To achieve optimal system perfor-

mance with the AFE2124, both the digital and the analog

sections must be treated carefully in board layout design.

The power supply for the digital section of the AFE2124 can

range from 3.3V to 5V. This supply should be decoupled to

digital ground with ceramic 0.1µF capacitors placed as close

to DGND and DV_DDas possible. One capacitor should be

placed between pins 7 and 8 and the second capacitor,

between pins 41 and 42. Ideally, both a digital power supply

plane and a digital ground plane should run up to and

underneath the digital pins of the AFE2124 (pins 1 through

6, and pins 43 through 48). However, DV_DDmay be supplied

by a wide printed circuit board (PCB) trace. A digital ground

Ideally, all ground planes and traces and all power planes

and traces should return to the power supply connector

before being connected together (if necessary). Each ground

and power pair should be routed over each other, should not

overlap any portion of another pair, and the pairs should be

separated by a distance of at least 0.25 inch (6mm). One

exception is that the digital and analog ground planes should

be connected together underneath the AFE2124 by a small

trace.

®

11

AFE2124

PACKAGE OPTION ADDENDUM

www.ti.com

12-Jan-2006

PACKAGING INFORMATION

Orderable Device

AFE2124E

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SSOP

DL

48

30 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

AFE2124E/1K

AFE2124E/1KG4

AFE2124EG4

SSOP

DL

1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

30 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process

in which TI products or services are used. Information published by TI regarding third-party products or services

does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.

Use of such information may require a license from a third party under the patents or other intellectual property

of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction

of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for

such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

product or service voids all express and any implied warranties for the associated TI product or service and

is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	AFE2124
厂家：	TEXAS INSTRUMENTS
描述：	Dual HDSL/SDSL ANALOG FRONT END
文件：	总13页 (文件大小：182K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AFE2124 [TI]

相关型号：

AFE2124E

AFE2124E/1K

AFE2124E/1KG4

AFE2124EG4

AFE2126

AFE2126E

AFE2126E/1K

AFE220

AFE220PS12

AFE220PS19

AFE220PS24

AFE220PS48