AFE4490_14_技术文档

AFE4400

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SBAS601D –DECEMBER 2012–REVISED MAY 2013

Integrated Analog Front-End for

Heart Rate Monitors and Low-Cost Pulse Oximeters

Check for Samples: AFE4400

1

FEATURES

APPLICATIONS

23

•

Fully-Integrated Analog Front-End for

Pulse Oximeter Applications:

•

Low-Cost Medical Pulse Oximeter Applications

Optical HRM

–

Flexible Pulse Sequencing and

Timing Control

Industrial Photometry Applications

•

Transmit:

DESCRIPTION

The AFE4400 is a fully-integrated analog front-end

(AFE) that is ideally suited for pulse oximeter

applications. The device consists of a low-noise

receiver channel with an integrated analog-to-digital

converter (ADC), an LED transmit section, and

diagnostics for sensor and LED fault detection. The

AFE4400 is a very configurable timing controller. This

flexibility enables the user to have complete control of

the device timing characteristics. To ease clocking

requirements and provide a low-jitter clock to the

AFE4400, an oscillator is also integrated that

functions from an external crystal. The device

communicates to an external microcontroller or host

processor using an SPI™ interface.

–

Integrated LED Driver

(H-Bridge or Push/Pull)

95-dB Dynamic Range

LED Current:

–

Programmable to 50 mA with 8-Bit

Current Resolution

–

Low Power:

–

100 µA + Average LED Current

–

Programmable LED On-Time

Independent LED2 and LED1 Current

Reference

•

Receive Channel with High Dynamic Range:

The AFE4400 is a complete AFE solution packaged

in a single, compact QFN-40 package (6 mm ×

–

13 Noise-Free Bits (0.1 Hz to 5 Hz)

Low Power: < 670 µA at 3.3-V Supply

Flexible Receive Sample Time

6

mm) and is specified over the operating

temperature range of 0°C to +70°C.

Supply

(2.2 V to 3.6 V)

Flexible Transimpedance Amplifier with

Programmable LED Settings

AFE4400

–

Integrated Digital Ambient Estimation and

Subtraction

RX

RED

Amb (RED)

AFE

SPI

SPI Interface

TIA

ûꢀ ADC

IR

•

Integrated Fault Diagnostics:

Amb (IR)

Photodiode

–

Photodiode and LED Open and

Short Detection

Diagnostic

PD Open or Short

Timing

Controller

Cable Off

–

Cable On/Off Detection

LED Open or Short

Supplies:

–

Rx = 2.0 V to 3.6 V

Tx = 3.0 V to 3.6 V

LED

Current

Control

DAC

LED

Driver

LED

•

Package: Compact QFN-40 (6 mm × 6 mm)

Specified Temperature Range: 0°C to +70°C

Tx

OSC

AFE

Tx Driver

Supply

5-V Supply

32 kHz

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

SPI is a trademark of Motorola.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

AFE4400

SBAS601D –DECEMBER 2012–REVISED MAY 2013

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

FAMILY AND ORDERING INFORMATION

LED DRIVE

CURRENT

(mA, max)

OPERATING

TEMPERATURE

RANGE

LED DRIVE

CONFIGURATION

POWER SUPPLY

(V)

PRODUCT

PACKAGE-LEAD

AFE4400

QFN-40

Bridge, push-pull

50

3 to 3.6

0°C to +70°C

50, 75, 100,

150, and 200

AFE4490

QFN-40

Bridge, push-pull

3 to 5.25

–40°C to +85°C

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range, unless otherwise noted.

VALUE

UNIT

V

AVDD to AVSS

–0.3 to +7

DVDD to DGND

–0.3 to +7

V

AGND to DGND

–0.3 to +0.3

V

Analog input to AVSS

Digital input to DVDD

Input current to any pin except supply pins⁽²⁾

AVSS – 0.3 to AVDD + 0.3

V

DVSS – 0.3 to DVDD + 0.3

V

±7

±50

mA

°C

Momentary

Input current

Continuous

±7

Operating temperature range

Storage temperature range, T_stg

Maximum junction temperature, T_J

Human body model (HBM)

0 to +70

–60 to +150

+125

±4000

±1500

V

JEDEC standard 22, test method A114-C.01, all pins

Electrostatic discharge

(ESD) ratings

Charged device model (CDM)

JEDEC standard 22, test method C101, all pins

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing beyond the supply rails must be current-limited

to 10 mA or less.

THERMAL INFORMATION

AFE4400

THERMAL METRIC⁽¹⁾

RHA (QFN)

UNITS

40 PINS

35

θ_JA

Junction-to-ambient thermal resistance

θ_JCtop

θ_JB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

31

26

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

ψ_JB

n/a

θ_JCbot

n/a

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

2

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RECOMMENDED OPERATING CONDITIONS

Over operating free-air temperature range, unless otherwise noted.

PARAMETER

SUPPLIES

VALUE

UNIT

RX_ANA_SUP

RX_DIG_SUP

TX_CTRL_SUP

AFE analog supply

2.0 to 3.6

V

AFE digital supply

Transmit controller supply

3.0 to 3.6

(1) (2)

[3.0 or (1.4 + V_LED+ V_CABLE

)

,

H-bridge configuration

V

whichever is greater] to 5.25

LED_DRV_SUP

Transmit LED driver supply

(1) (2)

Common anode

configuration

[3.0 or (1.3 + V_LED+ V_CABLE)

,

V

whichever is greater] to 5.25

Difference between LED_DRV_SUP and TX_CTRL_SUP

–0.3 to +0.3

TEMPERATURE

Specified temperature range

Storage temperature range

0 to +70

°C

–60 to +150

(1) V_LEDrefers to the voltage drop across the external LED connected between the TXP and TXM pins (in H-bridge mode) and from the

TXP and TXM pins to LED_DRV_SUP (in the common anode configuration).

(2) V_CABLErefers to voltage drop across any cable, connector, or any other component in series with the LED.

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ELECTRICAL CHARACTERISTICS

Minimum and maximum specifications are at T_A= –20°C to +85°C. Typical specifications are at +25°C.

All specifications are at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, and f_CLK= 8 MHz,

unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PERFORMANCE (Full-Signal Chain)

R_F= 10 kΩ

R_F= 25 kΩ

R_F= 50 kΩ

R_F= 100 kΩ

R_F= 250 kΩ

R_F= 500 kΩ

R_F= 1 MΩ

50

20

10

5

µA

I_{IN_FS}

Full-scale input current

µA

2

µA

1

µA

0.5

µA

PRF

Pulse repetition frequency

PRF duty cycle

61

5000

25%

SPS

DC_PRF

R_F= 10 kΩ

R_F= 1 MΩ

50

µA

I_{IN_FS}

Full-scale input current

0.5

f_CM= 50 Hz and 60 Hz, LED1 and LED2 with

R_SERIES= 1 MΩ, R_F= 500 kΩ

80

dB

CMRR

PSRR

Common-mode rejection ratio

Power-supply rejection ratio

f_CM= 50 Hz and 60 Hz, LED1-AMB and

LED2-AMB with R_SERIES= 1 MΩ,

R_F= 500 kΩ

100

f_PS= 50 Hz, 60 Hz at PRF = 200 Hz

f_PS= 50 Hz, 60 Hz at PRF = 600 Hz

With respect to ripple on LED_DRV_SUP

With respect to ripple on TX_CTRL_SUP

100

106

75

dB

PSRR_LED

PSRR_Tx

PSRR, transmit LED driver

PSRR, transmit control

60

With respect to ripple on RX_ANA_SUP and

RX_DIG_SUP

PSRR_Rx

PSRR, receiver

60

dB

Total integrated noise current, input-referred

(receiver with transmitter loop back,

0.1-Hz to 5-Hz bandwidth)

R_F= 100 kΩ, PRF = 625 Hz, duty cycle = 5%

R_F= 500 kΩ, PRF = 625 Hz, duty cycle = 5%

36

13

pA_RMS

R_F= 100 kΩ, PRF = 625 Hz, duty cycle = 5%

R_F= 500 kΩ, PRF = 625 Hz, duty cycle = 5%

14.3

13.5

Bits

Noise-free bits (receiver with transmitter loop

back, 0.1-Hz to 5-Hz bandwidth)

N_FB

RECEIVER FUNCTIONAL BLOCK LEVEL SPECIFICATION

R_F= 500 kΩ, ambient cancellation enabled,

stage 2 gain = 4, PRF = 1300 Hz,

LED duty cycle = 25%

1.4

5

pA_RMS

Total integrated noise current, input referred

(receiver alone) over 0.1-Hz to 5-Hz bandwidth

R_F= 500 kΩ, ambient cancellation enabled,

stage 2 gain = 4, PRF = 1300 Hz,

LED duty cycle = 5%

pA_RMS

I-V TRANSIMPEDANCE AMPLIFIER

See the Receiver Channel section

G

Gain

R_F= 10 kΩ to 1 MΩ

V/µA

for details

Gain accuracy

Feedback resistance

±7%

10k, 25k, 50k, 100k, 250k,

500k, and 1M

R_F

Ω

Feedback resistor tolerance

Feedback capacitance

R_F

C_F

±20%

5, 10, 25, 50, 100, and 250

pF

Feedback capacitor tolerance

Full-scale differential output voltage

Common-mode voltage on input pins

±20%

1

V

Set internally

0.9

Includes equivalent capacitance of

photodiode, cables, EMI filter, and so forth

External differential input capacitance

Shield output voltage, V_CM

10

1000

pF

V

With a 1-kΩ series resistor and a 10-nF

decoupling capacitor to ground

0.9

4

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SBAS601D –DECEMBER 2012–REVISED MAY 2013

ELECTRICAL CHARACTERISTICS (continued)

Minimum and maximum specifications are at T_A= –20°C to +85°C. Typical specifications are at +25°C.

All specifications are at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, and f_CLK= 8 MHz,

unless otherwise noted.

PARAMETER

AMBIENT CANCELLATION STAGE

Gain

TEST CONDITIONS

MIN

TYP

MAX

UNIT

1, 1.414, 2, 2.828, and 4

V/V

µA

Current DAC range

0

10

Current DAC step size

LOW-PASS FILTER

1

µA

Low-pass corner frequency

3-dB attenuation

500

0.004

0.041

Hz

dB

Duty cycle = 25%

Duty cycle = 10%

Pass-band attenuation, 2 Hz to 10 Hz

ANALOG-TO-DIGITAL CONVERTER

Resolution

22

Bits

SPS

V

See the ADC Operation and Averaging

Module section

Sample rate

4 × PRF

±1.2

ADC full-scale voltage

ADC conversion time

See the ADC Operation and Averaging

Module section

50

2

PRF / 4

µs

ADC reset time

t_CLK

TRANSMITTER

Selectable, 0 to 50

Output current range

(see the LEDCNTRL: LED Control

Register for details)

mA

LED current DAC error

Output current resolution

±10%

8

Bits

dB

At 5-mA output current

At 25-mA output current

At 50-mA output current

95

Transmitter noise dynamic range,

over 0.1-Hz to 5-Hz bandwidth

95

At 50-mA output current,

H-bridge LED driver configuration

1.4 + (voltage drop across LED,

cable, and so forth) to 5.25

V

Voltage on TXP (or TXM) pin when low-side

switch connected to TXP (or TXM) turns on

At 50-mA output current,

common anode LED driver configuration

1.3 + (voltage drop across LED,

cable, and so forth) to 5.25

Minimum sample time of LED1 and LED2

pulses

50

µs

LED_ON = 0

1

50

µA

LED current DAC leakage current

LED current DAC linearity

LED_ON = 1

Percent of full-scale current

From zero current to 50 mA

From 50 mA to zero current

0.5%

7

µs

Output current settling time

(with resistive load)

7

DIAGNOSTICS

Start of diagnostics after the DIAG_EN

register bit is set.

End of diagnostic is indicated by DIAG_END

going high.

4k cycles

of 4-MHz

clock

Duration of diagnostics state machine

16

Open fault resistance

Short fault resistance

> 100

< 10

kΩ

INTERNAL OSCILLATOR

With an 8-MHz crystal connected to the XIN,

XOUT pins

f_CLKOUT

CLKOUT frequency

4

50%

200

MHz

µs

CLKOUT duty cycle

With an 8-MHz crystal connected to the XIN,

XOUT pins

Crystal oscillator start-up time

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ELECTRICAL CHARACTERISTICS (continued)

Minimum and maximum specifications are at T_A= –20°C to +85°C. Typical specifications are at +25°C.

All specifications are at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, and f_CLK= 8 MHz,

unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

EXTERNAL CLOCK

Maximum allowable external clock jitter

External clock input frequency

50

ps

MHz

V

±10%

8

Voltage input high (V_IH

)

0.75 × RX_DIG_SUP

0.25 × RX_DIG_SUP

External clock input voltage

Voltage input low (V_IL)

V

TIMING

Wake-up time from complete power-down

Wake-up time from Rx power-down

Wake-up time from Tx power-down

Active low RESET pulse duration

1000

100

1000

1

ms

µs

ms

t_RESET

DIAG_END pulse duration at the completion of

diagnostics

CLKOUT

cycles

t_DIAGEND

4

1

CLKOUT

cycle

t_ADCRDY

ADC_RDY pulse duration

DIGITAL SIGNAL CHARACTERISTICS

AFE_PDN, SCLK, SPISIMO, SPISTE,

RESET

DVDD +

0.1

V_IH

Logic high input voltage

0.8 DVDD

> 1.3

V

AFE_PDN, SCLK, SPISIMO, SPISTE,

RESET

V_IL

I_IN

Logic low input voltage

Logic input current

–0.1

–10

< 0.4 0.2 DVDD

10

V

µA

V

0 V < V_DigitalInput< DVDD

DIAG_END, LED_ALM, PD_ALM, SPISOMI,

ADC_RDY, CLKOUT

> (RX_DIG_SUP –

0.2 V)

V_OH

Logic high output voltage

0.9 DVDD

DIAG_END, LED_ALM, PD_ALM, SPISOMI,

ADC_RDY, CLKOUT

V_OL

Logic low output voltage

< 0.4 0.1 DVDD

V

SUPPLY CURRENT

RX_ANA_SUP = 3.0 V, with 8-MHz clock

running, Rx stage 2 disabled

0.6

mA

Receiver analog supply current

RX_ANA_SUP = 3.0 V, with 8-MHz clock

running, Rx stage 2 enabled

0.7

0.27

55

mA

µA

Receiver digital supply current

LED driver supply current

RX_DIG_SUP = 3.0 V

LED_DRV

_SUP

With zero LED current setting

TX_CTRL

_SUP

Transmitter control supply current

15

3

µA

Receiver current only

(RX_ANA_SUP)

Receiver current only

(RX_DIG_SUP)

3

Complete power-down (using AFE_PDN pin)

Transmitter current only

(LED_DRV_SUP)

1

Transmitter current only

(TX_CTRL_SUP)

1

Receiver current only

(RX_ANA_SUP)

220

2

Power-down Rx alone

Power-down Tx alone

Receiver current only

(RX_DIG_SUP)

Transmitter current only

(LED_DRV_SUP)

Transmitter current only

(TX_CTRL_SUP)

2

6

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SBAS601D –DECEMBER 2012–REVISED MAY 2013

ELECTRICAL CHARACTERISTICS (continued)

Minimum and maximum specifications are at T_A= –20°C to +85°C. Typical specifications are at +25°C.

All specifications are at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, and f_CLK= 8 MHz,

unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER DISSIPATION

Normal operation (excluding LEDs)

Power-down

2.84

0.1

mW

Quiescent power dissipation

LED_DRV_SUP current value.

Does not include LED current.

LED_DRV_SUP

1

µA

Power-down with the

AFE_PDN pin

TX_CTRL_SUP

RX_ANA_SUP

RX_DIG_SUP

1

5

µA

0.1

LED_DRV_SUP current value.

Does not include LED current.

LED_DRV_SUP

1

µA

Power-down with the

PDNAFE register bit

TX_CTRL_SUP

RX_ANA_SUP

RX_DIG_SUP

1

15

20

µA

LED_DRV_SUP current value.

Does not include LED current.

LED_DRV_SUP

50

µA

TX_CTRL_SUP

RX_ANA_SUP

RX_DIG_SUP

15

220

µA

Power-down Rx

Power-down Tx

LED_DRV_SUP current value.

Does not include LED current.

LED_DRV_SUP

2

µA

TX_CTRL_SUP

RX_ANA_SUP

RX_DIG_SUP

2

600

230

µA

LED_DRV_SUP current value.

Does not include LED current.

LED_DRV_SUP

55

µA

After reset, with 8-MHz

clock running

TX_CTRL_SUP

RX_ANA_SUP

RX_DIG_SUP

15

600

230

µA

LED_DRV_SUP current value.

Does not include LED current.

LED_DRV_SUP

55

µA

With stage 2 mode

enabled and 8-MHz clock

running

TX_CTRL_SUP

RX_ANA_SUP

RX_DIG_SUP

15

700

270

µA

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PARAMETRIC MEASUREMENT INFORMATION

SERIAL INTERFACE TIMING

t_CLK

XIN

t_STECLK

SPI STE

t_SPICLK

t_CLKSTEH

31

23

7

0

SCLK

t_CLKSTEL

t_SIMOHD

t_SIMOSU

A7

A6

A1

A0

SPI SIMO

t_SOMIHD

t_SOMIPD

D22

D17 D16

D23

D7

D6

D1

D0

SPI SOMI

5}v[š ꢀꢁŒꢂ, can be high or low.

(1) The SPI_READ register bit must be enabled before attempting a register read.

(2) Specify the register address whose contents must be read back on A[7:0].

(3) The AFE outputs the contents of the specified register on the SOMI pin.

Figure 1. Serial Interface Timing Diagram, Read Operation ^(1)(2)(3)

8

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PARAMETRIC MEASUREMENT INFORMATION (continued)

t_STECLK

SPI STE

31

23

0

SCLK

t_SIMOHD

t_SIMOSU

A7

A6

A1

A0

D23

D22

D1

D0

SPI SIMO

Figure 2. Serial Interface Timing Diagram, Write Operation

Table 1. Timing Requirements for Figure 1 and Figure 2

PARAMETER

MIN

TYP

MAX

UNIT

MHz

ns

t_CLK

Clock frequency on XIN pin

8

t_SCLK

Serial shift clock period

62.5

10

t_STECLK

t_CLKSTEH,L

t_SIMOSU

t_SIMOHD

t_SOMIPD

t_SOMIHD

STE low to SCLK rising edge, setup time

SCLK transition to SPI STE high or low

SIMO data to SCLK rising edge, setup time

Valid SIMO data after SCLK rising edge, hold time

SCLK falling edge to valid SOMI, setup time

SCLK rising edge to invalid data, hold time

ns

10

ns

10

ns

10

ns

17

ns

0.5

t_SCLK

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PIN CONFIGURATION

RHA PACKAGE

QFN-40

(Top View)

40 39 38 37 36 35 34 33 32 31

INN

INP

1

2

30

29

28

27

26

25

24

23

22

21

CLKOUT

RESET

RX_ANA_GND

VCM

3

ADC_RDY

SPISTE

4

DNC⁽¹⁾

DNC

5

SPISIMO

SPISOMI

SCLK

6

BG

VSS

7

8

PD_ALM

LED_ALM

DIAG_END

TX_REF

DNC

9

10

11 12 13 14 15 16 17 18 19 20

(1) DNC = Do not connect.

10

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PIN DESCRIPTIONS

NAME

NO.

FUNCTION

DESCRIPTION

Output signal that indicates ADC conversion completion.

Can be connected to the interrupt input pin of an external microcontroller.

ADC_RDY

AFE_PDN

BG

28

Digital

AFE-only power-down input; active low.

Can be connected to the port pin of an external microcontroller.

20

7

Digital

Reference

Digital

Decoupling capacitor for internal band-gap voltage to ground.

(2.2-µF decoupling capacitor to ground)

Buffered 4-MHz output clock output.

Can be connected to the clock input pin of an external microcontroller.

CLKOUT

30

21

Output signal that indicates completion of diagnostics.

Can be connected to the port pin of an external microcontroller.

DIAG_END

Digital

DNC⁽¹⁾

INN

5, 6, 10, 34, 35

—

Do not connect these pins. Leave as open circuit.

1

2

Analog

Supply

Receiver input pin. Connect to photodiode anode.

INP

Receiver input pin. Connect to photodiode cathode.

LED driver ground pin, H-bridge. Connect to common board ground.

LED_DRV_GND

12, 13, 16

LED driver supply pin, H-bridge. Connect to an external power supply capable of supplying the

large LED current, which is drawn by this supply pin.

LED_DRV_SUP

LED_ALM

PD_ALM

17, 18

22

Supply

Digital

Output signal that indicates an LED cable fault.

Can be connected to the port pin of an external microcontroller.

Output signal that indicates a PD sensor or cable fault.

Can be connected to the port pin of an external microcontroller.

23

AFE-only reset input, active low.

Can be connected to the port pin of an external microcontroller

RESET

29

RX_ANA_GND

RX_ANA_SUP

RX_DIG_GND

RX_DIG_SUP

SCLK

3, 36, 40

33, 39

19, 32

31

Supply

SPI

Rx analog ground pin. Connect to common board ground.

Rx analog supply pin; 0.1-µF decoupling capacitor to ground

Rx digital ground pin. Connect to common board ground.

Rx digital supply pin; 0.1-µF decoupling capacitor to ground

SPI clock pin

24

SPISIMO

26

SPI

SPI serial in master out

SPISOMI

25

SPI

SPI serial out master in

SPISTE

27

SPI

SPI serial interface enable

TX_CTRL_SUP

TX_REF

11

Supply

Reference

Analog

Transmit control supply pin (0.1-µF decoupling capacitor to ground)

Tx reference voltage

9

TXN

14

LED driver out B, H-bridge output. Connect to LED.

TXP

15

Input common-mode voltage output.

VCM

VSS

4

8

Reference

Supply

Connect a series resistor (1 kΩ) and a decoupling capacitor (10 nF) to ground.

The voltage across the capacitor can be used to shield (guard) the INP, INM traces.

Substrate ground. Connect to common board ground.

Crystal oscillator pins.

XOUT

37

Digital

Connect an external 8-MHz crystal between these pins with the correct load capacitor

(as specified by vendor) to ground.

Crystal oscillator pins.

XIN

38

Digital

Connect an external 8-MHz crystal between these pins with the correct load capacitor

(as specified by vendor) to ground.

(1) Leave pins as open circuit. Do not connect.

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TYPICAL CHARACTERISTICS

At T_A= +25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, and f_CLK= 8 MHz, unless

otherwise noted.

900

800

700

600

500

400

15.00

14.95

14.90

14.85

14.80

14.75

14.70

14.65

Stage 2 & Amb Cancel Disabled

Stage 2 & Amb Cancel Enabled

PRF = 600Hz

RX_ANA_SUP = RX_DIG_SUP

PRF = 600Hz

Stage 2 Gain = 4

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

2.5

3.0

3.5

4.0

4.5

5.0

C001

RX Supply Voltage (V)

C002

TX_CTRL_SUP Voltage (V)

Figure 3. TOTAL Rx CURRENT vs Rx SUPPLY VOLTAGE

Figure 4. TX_CTRL_SUP CURRENT vs

TX_CTRL_SUP VOLTAGE

48.0

47.8

47.6

47.4

47.2

47.0

46.8

46.6

46.4

600

500

400

300

200

100

0

Duty Cycle = 1%

Duty Cycle = 5%

Duty Cycle = 10%

Duty Cycle = 15%

Duty Cycle = 20%

Duty Cycle = 25%

For each setting RF adjusted for Full-Scale Output.

Amb Cancellation & stage 2 Gain = 4 used for Low

Pleth currents (0.125uA, 0.25uA & 0.5uA).

Noise is calculated in 5Hz B/W.

46.2

With LED Current = 0mA

46.0

2.5

3.0

3.5

4.0

4.5

5.0

0

10

20

30

40

50

C003

C004

LED_DRV_SUP Voltage (V)

Pleth Current (ꢀA)

Figure 5. LED_DRV_SUP CURRENT vs

LED_DRV_SUP VOLTAGE

Figure 6. INPUT-REFERRED NOISE CURRENT vs

PLETH CURRENT (PRF = 100 Hz)

700

600

500

400

300

200

100

0

700

600

500

400

300

200

100

0

Duty Cycle = 1%

Duty Cycle = 5%

Duty Cycle = 10%

Duty Cycle = 15%

Duty Cycle = 20%

Duty Cycle = 25%

Duty cycle 1%

Duty cycle 5%

Duty cycle 10%

Duty cycle 15%

Duty cycle 20%

Duty cycle 25%

For each setting RF adjusted for Full-Scale Output.

Amb Cancellation & stage 2 Gain = 4 used for Low

Pleth currents (0.125uA, 0.25uA & 0.5uA).

Noise is calculated in 5Hz B/W.

For each setting RF adjusted for Full-Scale Output.

Amb Cancellation & stage 2 Gain = 4 used for Low

Pleth currents (0.125uA, 0.25uA & 0.5uA.)

Noise is calculated in 5Hz band.

0

10

20

30

40

50

0

10

20

30

40

50

C005

Pleth Current (ꢀA)

C006

Pleth Current (ꢀA)

Figure 7. INPUT-REFERRED NOISE CURRENT vs

PLETH CURRENT (PRF = 300 Hz)

Figure 8. INPUT-REFERRED NOISE CURRENT vs

PLETH CURRENT (PRF = 600 Hz)

12

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, and f_CLK= 8 MHz, unless

otherwise noted.

800

700

600

500

400

300

200

100

0

1200

1000

800

600

400

200

0

For each setting RF adjustedfor Full-Scale Output.

Amb Cancellation & stage 2 Gain = 4 used for

Low Pleth currents (0.125uA, 0.25uA & 0.5uA).

Noise is calculated in 5Hz band.

Duty Cycle = 1%

Duty Cycle = 5%

Duty Cycle = 10%

Duty Cycle = 15%

Duty Cycle = 20%

Duty Cycle = 25%

Duty cycle 1%

Duty cycle 5%

Duty cycle 10%

Duty cycle 15%

Duty cycle 20%

Duty cycle 25%

For each RF adjusted for Full-Scale Output.

Amb Cancellation & stage 2 Gain = 4 used for Low

Pleth currents (0.125uA, 0.25uA & 0.5uA).

Noise is calculated in 5Hz band.

0

10

20

30

40

50

0

10

20

30

40

50

C007

C008

Pleth Current (ꢀA)

Figure 9. INPUT-REFERRED NOISE CURRENT vs

PLETH CURRENT (PRF = 1200 Hz)

Figure 10. INPUT-REFERRED NOISE CURRENT vs

PLETH CURRENT (PRF = 2500 Hz)

1400

1200

1000

800

600

400

200

0

16

For each setting RF adjusted for Full-Scale Output.

For each setting RF adjustedfor Full-Scale Output.

Amb Cancellation & stage 2 Gain = 4 used for

Low Pleth currents (0.125uA, 0.25uA & 0.5uA).

Noise is calculated in 5Hz band.

Duty cycle 1%

Duty cycle 5%

Duty cycle 10%

Duty cycle 15%

Duty cycle 20%

Duty cycle 25%

Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA).

RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 ì RMS noise.

15

14

13

12

11

10

Duty cycle 1%

Duty cycle 5%

Duty cycle 10%

Duty cycle 15%

Duty cycle 20%

Duty cycle 25%

0

10

20

30

40

50

0

10

20

30

40

50

C009

C010

Pleth Current (ꢀA)

Figure 11. INPUT-REFERRED NOISE CURRENT vs

PLETH CURRENT (PRF = 5000 Hz)

Figure 12. NOISE-FREE BITS vs PLETH CURRENT

(PRF = 100 Hz)

16

For each setting RF adjusted for Full-Scale Output.

Amb Cancellation & stage 2 Gain = 4 used for Low pleth currents (0.125uA, 0.25uA & 0.5uA.)

RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 ì RMS noise.

Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA).

RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 ì RMS noise.

15

14

13

12

11

10

15

14

13

12

11

10

Duty cycle 1%

Duty cycle 5%

Duty cycle 10%

Duty cycle 15%

Duty cycle 20%

Duty cycle 25%

Duty cycle 1%

Duty cycle 5%

Duty cycle 10%

Duty cycle 15%

Duty cycle 20%

Duty cycle 25%

0

10

20

30

40

50

0

10

20

30

40

50

C011

C012

Pleth Current (ꢀA)

Figure 13. NOISE-FREE BITS vs PLETH CURRENT

(PRF = 300 Hz)

Figure 14. NOISE-FREE BITS vs PLETH CURRENT

(PRF = 600 Hz)

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, and f_CLK= 8 MHz, unless

otherwise noted.

16

15

14

13

12

11

10

16

15

14

13

12

11

10

For each setting RF adjusted for Full-Scale Output.

Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA).

RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 ì RMS noise.

Duty Cycle = 1%

Duty Cycle = 5%

Duty Cycle = 10%

Duty Cycle = 15%

Duty Cycle = 20%

Duty Cycle = 25%

Duty Cycle = 1%

Duty Cycle = 5%

Duty Cycle = 10%

Duty Cycle = 15%

Duty Cycle = 20%

Duty Cycle = 25%

For each setting RF adjusted for Full-

Scale Output.

Amb Cancellation & stage 2 Gain = 4

used for Low Pleth currents (0.125uA,

0.25uA & 0.5uA).

RMS noise is calculated in 5Hz B/W &

NFB is calculated using 6.6 ì RMS noise.

0

10

20

30

40

50

0

10

20

30

40

50

C013

C014

Pleth Current (ꢀA)

Pleth Current, uA

Figure 15. NOISE-FREE BITS vs PLETH CURRENT

(PRF = 1200 Hz)

Figure 16. NOISE-FREE BITS vs PLETH CURRENT

(PRF = 2500 Hz)

16

120

110

100

90

15

14

13

12

11

10

80

Duty cycle 1%

Duty cycle 5%

Duty cycle 10%

Duty cycle 15%

Duty cycle 20%

Duty cycle 25%

For each setting RF adjusted for Full-Scale

Output.

Amb Cancellation & stage 2 Gain = 4 used for

Low Pleth currents (0.125uA, 0.25uA & 0.5uA).

RMS noise is calculated in 5Hz B/W & NFB is

calculated using 6.6 ì RMS noise.

70

TX_CTRL_SUP = LED_DRV_SUP = 3V

TX Vref = 0.5V

60

50

0

10

20

30

40

50

0

20

40

60

80

100

C015

C016

Pleth Current, uA

% of Full-Scale LED Current

Figure 17. NOISE-FREE BITS vs PLETH CURRENT

(PRF = 5000 Hz)

Figure 18. TRANSMITTER DYNAMIC RANGE

(5-Hz BW)

500

Expected + 1%

Actual DAC Current

Expected - 1%

50

40

30

20

10

0

400

300

200

100

0

œ100

œ200

œ300

œ400

œ500

TX_REF = 0.5V

50

TX Reference Voltage = 0.5V

0

100

150

200

250

0

50

100

150

200

250

C021

C022

TX LED DAC Setting

Figure 19. TRANSMITTER DAC CURRENT STEP ERROR

(50 mA, Max)

Figure 20. TRANSMITTER CURRENT LINEARITY

(50-mA Range)

14

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, and f_CLK= 8 MHz, unless

otherwise noted.

500

400

300

200

100

0

400

300

200

100

0

TX_RANGE = 50mA,

Data from 2326 devices

TX_RANGE = 50mA,

Data from 2326 devices

LED Current (mA)

C023

C024

Figure 21. LED CURRENT WITH Tx DAC SETTING = 10

(2 mA)

Figure 22. LED CURRENT WITH Tx DAC SETTING = 25

(5 mA)

400

TX_RANGE = 50mA,

Data from 7737 devices

Data from 2326 devices

300

200

100

0

200

100

0

LED Current (mA)

C025

C026

Figure 23. LED CURRENT WITH Tx DAC SETTING = 51

(10 mA)

Figure 24. LED CURRENT WITH Tx DAC SETTING = 102

(20 mA)

800

700

600

400

TX_RANGE = 50mA,

Data from 7737 devices

300

200

100

0

500

400

300

200

100

RX_ANA_SUP = 2V (STG2=DIS)

RX_ANA_SUP = 2V (STG2=EN)

RX_DIG_SUP=2V

RX_ANA_SUP = 3.3V (STG2=DIS)

RX_ANA_SUP = 3.3V (STG2=EN)

RX_DIG_SUP=3.3V

100

300

500

700

900

1100

C028

PRF, Hz

LED Current (mA)

C027

Figure 25. LED CURRENT WITH Tx DAC SETTING = 255

(50 mA)

Figure 26. RECEIVER SUPPLIES vs PRF

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, and f_CLK= 8 MHz, unless

otherwise noted.

100.00

80.00

60.00

40.00

20.00

0.00

700

650

600

550

500

450

400

350

300

250

200

150

100

50

TX_CTRL_SUP = LED_DRV_SUP = 3V TO 3.6V

RX_ANA_SUP (STG2DIS)

RX_ANA_SUP (STG2EN)

RX_DIG_SUP

TX_CTRL_SUP

LED_DRV_SUP

TX_CTRL_SUP

LED_DRV_SUP

0

0.50

0.75

1.00

0

10

20

30

40

50

60

70

C029

C030

TX_VREF, V

Temperature, C

Figure 27. TRANSMITTER SUPPLIES vs TX_REF

Figure 28. POWER SUPPLIES vs TEMPERATURE

100

80

60

40

20

0

PRF = 1200 Hz, Duty cycle = 10%

1) RF = 100K, Stage 2 & ambient cancellation disabled

2) RF = 500K, Stage 2 & ambient cancellation enabled with stage 2 gain = 4

STG2=DIS, 5Hz BW (Note 2)

STG2=EN, 5Hz BW (Note 3)

STG2=DIS, 20Hz BW (Note 2)

STG2=EN, 20Hz BW (Note 3)

15

STG2=DIS, 5Hz BW (Note 2)

STG2=EN, 5Hz BW (Note 3)

STG2=DIS, 20Hz BW (Note 2)

STG2=EN, 20Hz BW (Note 3)

PRF = 1200 Hz, Duty cycle = 10%

1) RF = 100K, Stage 2 & ambient cancellation disabled

2) RF = 500K, Stage 2 & ambient cancellation enabled with stage 2 gain = 4

10

0

10

20

30

40

50

60

70

0

10

20

30

40

50

60

70

C032

Temperature, C

C031

Temperature, C

Figure 29. INPUT-REFERRED NOISE vs TEMPERATURE

Figure 30. NOISE-FREE BITS vs TEMPERATURE

0

œ10

œ20

œ30

œ40

5% Duty cycle

25% Duty cycle

œ50

1

10

100

C033

Input signal frequency, Hz

Figure 31. FILTER RESPONSE vs DUTY CYCLE

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OVERVIEW

The AFE4400 is a complete analog front-end (AFE) solution targeted for pulse oximeter applications. The device

consists of a low-noise receiver channel, an LED transmit section, and diagnostics for sensor and LED fault

detection. To ease clocking requirements and provide the low-jitter clock to the AFE, an oscillator is also

integrated that functions from an external crystal. The device communicates to an external microcontroller or host

processor using an SPI interface. Figure 32 shows a detailed block diagram for the AFE4400. The blocks are

described in more detail in the following sections.

Device

Reference

C_F

SPISTE

SPISIMO

SPISOMI

SCLK

R_F

SPI

+

Digital

Filter

INP

Stage 2

Gain

TIA

Buffer

4G ADC

Filter

C_PD

INN

R_F

C_F

Photodiode

Control

VCM

Timing

AFE_PDN

ADC_RDY

RESET

Controller

C_F

TXN

TXP

LED

Driver

LED Current

Control DAC

DIAG_END

LED_ALM

DNC⁽¹⁾

Diagnostic

Signals

Diagnostics

PD_ALM/ADC Reset

OSC

8 MHz

Figure 32. Detailed Block Diagram

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RECEIVER CHANNEL

This section describes the functionality of the receiver channel.

Receiver Front-End

The receiver consists of a differential current-to-voltage (I-V) transimpedance amplifier that converts the input

photodiode current into an appropriate voltage, as shown in Figure 33. The feedback resistor of the amplifier (R_F)

is programmable to support a wide range of photodiode currents. Available R_Fvalues include: 1 MΩ, 500 kΩ,

250 kΩ, 100 kΩ, 50 kΩ, 25 kΩ, and 10 kΩ.

Rx

S_LED2

CONV_LED2

LED2

C_F

R_F

ADC

ADC Output Rate

PRF Sa/sec

Amb

LED1

+

Stage 2

Gain

S_{LED2_amb}

S_LED1

+

CONV_{LED2_amb}

CONV_LED1

TIA

C_PD

Buffer

ûꢀ ADC

R_F

C_F

ADC Convert

ADC Clock

Amb

Ambient

DAC

CONV_{LED1_amb}

S_{LED1_amb}

I-V Amplifier

Filter

Buffer

ADC

Amb cancellation DAC

Ambient-cancellation current can be set digitally using SPI interface.

Figure 33. Receiver Front-End

The R_Famplifier and the feedback capacitor (C_F) form a low-pass filter for the input signal current. Always ensure

that the low-pass filter has sufficiently high bandwidth (as shown by Equation 1) because the input current

consists of pulses. For this reason, the feedback capacitor is also programmable. Available C_Fvalues include:

5 pF, 10 pF, 25 pF, 50 pF, 100 pF, and 250 pF. Any combination of these capacitors can also be used.

Rx Sample Time

R_F´ C_F£

10

(1)

The output voltage of the I-V amplifier includes the pleth component (the desired signal) and a component

resulting from the ambient light leakage; see . The I-V amplifier is followed by the second stage, which consists

of a current digital-to-analog converter (DAC) that sources the cancellation current and an amplifier that gains up

the pleth component alone. The amplifier has five programmable gain settings: 1, 1.414, 2, 2.828, and 4. The

gained-up pleth signal is then low-pass filtered (500-Hz bandwidth) and buffered before driving a 22-bit ADC. The

current DAC has a cancellation current range of 10 µA with 10 steps (1 µA each). The DAC value can be digitally

specified with the SPI interface.

The output of the ambient cancellation amplifier is separated into LED2 and LED1 channels. When LED2 is on,

the amplifier output is filtered and sampled on capacitor C_R. Similarly, the LED1 signal is sampled on the C_LED1

capacitor when LED1 is ON. In between the LED2 and LED1 pulses, the idle amplifier output is sampled to

estimate the ambient signal on capacitors C_{LED2_amb}and C_{LED1_amb}

.

The sampling duration is termed the Rx sample time and is programmable for each signal, independently. The

sampling can start after the I-V amplifier output is stable (to account for LED and cable settling times). The Rx

sample time is used for all dynamic range calculations; the minimum time supported is 50 µs.

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A single, 22-bit ADC converts the sampled LED2, LED1, and ambient signals sequentially. Each conversion

takes 25% of the pulse repetition period and provides a single digital code at the ADC output. As discussed in

the Receiver Timing section, the conversions are staggered so that the LED2 conversion starts after the end of

the LED2 sample phase, and so on. This configuration also means that the Rx sample time for each signal is no

greater than 25% of the pulse repetition period.

Note that four data streams are available at the ADC output (LED2, LED1, ambient LED2, and ambient LED1) at

the same rate as the pulse repetition frequency. The ADC is followed by a digital ambient subtraction block that

additionally outputs the (LED2 – ambient LED2) and (LED1 – ambient LED1) data values.

Ambient Cancellation Scheme

The receiver provides digital samples corresponding to ambient duration. The host processor (external to the

AFE) can use these ambient values to estimate the amount of ambient light leakage. The processor must then

set the value of the ambient cancellation DAC using the SPI, as shown in Figure 34.

Device

Host Processor

LED2 Data

ADC Output Rate

PRF Samples per Second

Ambient (LED2)

Data

Front End

(LED2 œ Ambient)

Data

Ambient Estimation Block

SPI

Interface

Ambient information is available in the host

processor.

ADC

Rx

SPI

Digital

Block

The processor can:

* Read ambient data

LED1 Data

Ambient (LED1)

Data

* Estimate ambient value to

be cancelled

* Set the value to be used by the ambient

cancellation DAC using the SPI of AFE

(LED1 œ Ambient)

Data

Digital Control for Ambient-Cancellation DAC

Figure 34. Ambient Cancellation Loop (Closed by the Host Processor)

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Using the set value, the ambient cancellation stage subtracts the ambient component and gains up only the pleth

component of the received signal; see Figure 35. The amplifier gain is programmable to 1, 1.5, 2, 3, and 4.

I_CANCEL

Cf

Rg

Rf

I_PLETH+ I_AMB

Ri

Rx

V_DIFF

Ri

Rf

Rg

I_CANCEL

Cf

Value of I_CANCELset using

the SPI interface.

Figure 35. Front-End (I-V Amplifier and Cancellation Stage)

The differential output of the second stage is V_DIFF, as given by Equation 2:

R_F

V_DIFF= 2 ´ I_PLETH

´

+ I_AMB

´

- I_CANCEL´ R_G

R_I

where:

•

R_I= 100 kΩ,

I_PLETH= photodiode current pleth component,

I_AMB= photodiode current ambient component, and

I_CANCEL= the cancellation current DAC value (as estimated by the host processor).

(2)

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Receiver Control Signals

LED2 sample phase (S_LED2): When this signal is high, the amplifier output corresponds to the LED2 on-time.

The amplifier output is filtered and sampled into capacitor C_LED2. To avoid settling effects resulting from the LED

or cable, program S_LED2to start after the LED turns on. This settling delay is programmable.

Ambient sample phase (S_{LED2_amb}): When this signal is high, the amplifier output corresponds to the LED2 off-

time and can be used to estimate the ambient signal (for the LED2 phase). The amplifier output is filtered and

sampled into capacitor C_{LED2_amb}

.

LED1 sample phase (S_LED1): When this signal is high, the amplifier output corresponds to the LED1 on-time.

The amplifier output is filtered and sampled into capacitor C_LED1. To avoid settling effects resulting from the LED

or cable, program S_LED1to start after the LED turns on. This settling delay is programmable.

Ambient sample phase (S_{LED1_amb}): When this signal is high, the amplifier output corresponds to the LED1 off-

time and can be used to estimate the ambient signal (for the LED1 phase). The amplifier output is filtered and

sampled into capacitor C_{LED1_amb}

.

LED2 convert phase (CONV_LED2): When this signal is high, the voltage sampled on C_LED2is buffered and

applied to the ADC for conversion. The conversion time duration is always 25% of the pulse repetition period. At

the end of the conversion, the ADC provides a single digital code corresponding to the LED2 sample.

Ambient convert phases (CONV_{LED2_amb}, CONV_{LED1_amb}): When this signal is high, the voltage sampled on

C_{LED2_amb}(or C_{LED1_amb}) is buffered and applied to the ADC for conversion. The conversion time duration is

always 25% of the pulse repetition period. At the end of the conversion, the ADC provides a single digital code

corresponding to the ambient sample.

LED1 convert phase (CONV_LED1): When this signal is high, the voltage sampled on C_LED1is buffered and

applied to the ADC for conversion. The conversion time duration is always 25% of the pulse repetition period. At

the end of the conversion, the ADC provides a single digital code corresponding to the LED1 sample.

Receiver Timing

See Figure 36 for a timing diagram detailing the control signals related to the LED on-time, Rx sample time, and

the ADC conversion times for each channel.

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N+1

N+2

N+1

Plethysmograph Signal

N

Photodiode Current

Or

I-V Output

Ambient Level

(Dark Level)

S_R,

Sample RED

S_{R_amb}

,

Sample Ambient

(RED Phase)

CONV_R,

RED ADC Converts

(RED œ Ambient)

S_IR,

Sample IR

S_{IR_amb}

,

Sample Ambient

(IR Phase)

CONV_IR,

IR ADC Converts

(IR œ Ambient)

ADCLK_R,

Red ADC

Sample Clock

ADCLK_IR,

IR ADC

Sample Clock

RED

N+1

RED ADC

Output Data

RED

N

IR ADC

IR

Output Data

N-1

N

NOTE: Relationship to the AFE4400 EVM is: LED1 = IR and LED2 = RED.

Figure 36. Rx Timing Diagram

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CLOCKING AND TIMING SIGNAL GENERATION

The crystal oscillator generates a master clock signal using an external 8-MHz crystal. A divide-by-2 block

converts the 8-MHz clock to 4 MHz, which is used by the AFE to operate the timer modules, ADC, and

diagnostics. The 4-MHz clock is buffered and output from the AFE in order to clock an external microcontroller.

The clocking functionality is shown in Figure 37.

Timer

Module

Divide-

by-2

ADC

Diagnostics

Module

Oscillator

XIN

XOUT

CLKOUT

4 MHz

8-MHz Crystal

Figure 37. AFE Clocking

TIMER MODULE

See Figure 38 for a timing diagram detailing the various timing edges that are programmable using the timer

module. The rising and falling edge positions of 11 signals can be controlled. The module uses a single 16-bit

counter (running off of the 4-MHz clock) to set the time-base.

All timing signals are set with reference to the pulse repetition period (PRP). Therefore, a dedicated compare

register compares the 16-bit counter value with the reference value specified in the PRF register. Every time that

the 16-bit counter value is equal to the reference value in the PRF register, the counter is reset to '0'.

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LED2 (RED LED)

On Signal

t_LEDLED on-time

LED1 (IR LED)

On Signal

Ç 0.25 T.

Rx sample time = t_LEDœ settle time.

S_{LED2_amb}

,

Sample Ambient

[LED2 (RED) Phase]

S_LED1

,

Sample LED1 (IR)

S_{LED1_amb}

,

Sample Ambient

[LED1 (IR) Phase]

S_LED2

,

Sample LED2 (RED)

CONV_LED2

,

Convert LED2 (RED) Sample

CONV_{LED2_amb}

,

Convert Ambient Sample

[LED2 (RED) Phase]

CONV_LED1

,

Convert LED1 (IR) Sample

CONV_{LED1_amb}

,

Convert Ambient Sample

[LED1 (IR) Phase]

ADC Conversion

ADC Reset

ADC_RDY Pin

Pulse Repetition Period

T = 1 / PRF

NOTE: Programmable edges are shown in blue and red.

Figure 38. AFE Control Signals

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For the 11 signals in Figure 36, the start and stop edge positions are programmable with respect to the PRF

period. Each signal uses a separate timer compare module that compares the counter value with

preprogrammed reference values for the start and stop edges. All reference values can be set using the SPI

interface.

When the counter value equals the start reference value, the output signal is set. When the counter value equals

the stop reference value, the output signal is reset. Figure 39 shows a diagram of the timer compare register.

With a 4-MHz clock, the edge placement resolution is 0.25 µs. The ADC conversion signal requires four pulses in

each PRF clock period. The 11th timer compare register uses four sets of start and stop registers to control the

ADC conversion signal.

Set

START

STOP

Start Reference Register

Output

Signal

Counter

Input

Reset

Stop Reference Register

Timer Compare Register

Enable

Figure 39. Compare Register

The ADC conversion signal requires four pulses in each PRF clock period. Timer compare register 11 uses four

sets of start and stop registers to control the ADC conversion signal, as shown in Figure 40.

Reset

CLKIN

16-Bit Counter

Reset

Enable

Counter

S

R

Start

Stop

PRF

Pulse

Timer Compare

16-Bit Register 1

Timer Compare

16-Bit PRF Register

RED LED

IR LED

En

S

R

Start

Stop

S

R

Start

Stop

CONV_R,

Convert RED Sample

Timer Compare

16-Bit Register 2

Timer Compare

16-Bit Register 7

S

R

Start

Stop

S

R

S_R

Start

Stop

CONV_IR

,

Timer Compare

16-Bit Register 3

Timer Compare

16-Bit Register 8

Sample RED

Convert IR Sample

En

CONV_{IR_amb}

,

S

R

Start

Stop

S

R

S_IR

Sample IR

Start

Stop

Timer Compare

16-Bit Register 4

Timer Compare

16-Bit Register 9

Convert Ambient Sample

(IR Phase)

En

CONV_{R_amb}

,

S

R

S

R

Start

Stop

Start

Stop

Timer Compare

16-Bit Register 5

Timer Compare

16-Bit Register 10

Convert Ambient Sample

(RED Phase)

S_{R_amb}

,

Sample Ambient

(red phase)

START-A

STOP-A

S

R

Start

Stop

S_{IR_amb}

Sample Ambient

(IR phase)

,

Timer Compare

16-Bit Register 6

En

START-B

STOP-B

ADC

Timer Compare

Conversion

16-Bit Register 11

START-C

STOP-D

START-D

STOP-D

En

Timer Module

Figure 40. Timer Module

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Using the Timer Module

The timer module registers can be used to program the start and end instants in units of 4-MHz clock cycles.

These timing instants and the corresponding registers are listed in Table 2.

Note that the device does not restrict the values in these registers; thus, the start and end edges can be

positioned anywhere within the pulse repetition period. Care must be taken by the user to program suitable

values in these registers to avoid overlapping the signals and to make sure none of the edges exceed the value

programmed in the PRP register. Writing the same value in the start and end registers results in a pulse duration

of one clock cycle. The following steps describe the timer sequencing configuration:

1. With respect to the start of the PRP period (indicated by timing instant t₀in Figure 41), the following

sequence of conversions must be followed in order: convert LED2 → LED2 ambient → LED1 → LED1

ambient.

2. Also, starting from t₀, the sequence of sampling instants must be staggered with respect to the respective

conversions as follows: sample LED2 ambient → LED1 → LED1 ambient → LED2.

3. Finally, align the edges for the two LED pulses with the respective sampling instants.

Table 2. Clock Edge Mapping to SPI Registers

TIME INSTANT

(See Figure 41 and

Figure 42)

EXAMPLE

(Decimal)

DESCRIPTION

Start of pulse repetition period

Start of sample LED2 pulse

End of sample LED2 pulse

Start of LED2 pulse

CORRESPONDING REGISTER ADDRESS AND REGISTER BITS

No register control

t₀

t₁

—

LED2STC[15:0], register 01h

4800

6399

4800

6399

0

t₂

LED2ENDC[15:0], register 02h

LED2LEDSTC[15:0], register 03h

LED2LEDENDC[15:0], register 04h

ALED2STC[15:0], register 05h

t₃

t₄

End of LED2 pulse

t₅

Start of sample LED2 ambient pulse

End of sample LED2 ambient pulse

Start of sample LED1 pulse

End of sample LED1 pulse

Start of LED1 pulse

t₆

ALED2ENDC[15:0], register 06h

LED1STC[15:0], register 07h

1599

1600

3199

1600

3199

3200

4799

2

t₇

t₈

LED1ENDC[15:0], register 08h

LED1LEDSTC[15:0], register 09h

LED1LEDENDC[15:0], register 0Ah

ALED1STC[15:0], register 0Bh

ALED1ENDC[15:0], register 0Ch

LED2CONVST[15:0], register 0Dh

t₉

t₁₀

t₁₁

t₁₂

t₁₃

End of LED1 pulse

Start of sample LED1 ambient pulse

End of sample LED1 ambient pulse

Start of convert LED2 pulse

LED2CONVEND[15:0], register 0Eh

Must start one AFE clock cycle after the ADC reset pulse ends.

t₁₄

End of convert LED2 pulse

1599

ALED2CONVST[15:0], register 0Fh

Must start one AFE clock cycle after the ADC reset pulse ends.

t₁₅

t₁₆

t₁₇

t₁₈

t₁₉

Start of convert LED2 ambient pulse

End of convert LED2 ambient pulse

Start of convert LED1 pulse

1602

3199

3202

4799

4802

ALED2CONVEND[15:0], register 10h

LED1CONVST[15:0], register 11h

Must start one AFE clock cycle after the ADC reset pulse ends.

End of convert LED1 pulse

LED1CONVEND[15:0], register 12h

ALED1CONVST[15:0], register 13h

Must start one AFE clock cycle after the ADC reset pulse ends.

Start of convert LED1 ambient pulse

t₂₀

t₂₁

t₂₂

t₂₃

t₂₄

t₂₅

t₂₆

t₂₇

t₂₈

t₂₉

End of convert LED1 ambient pulse

Start of first ADC conversion reset pulse

End of first ADC conversion reset pulse

ALED1CONVEND[15:0], register 14h

ADCRSTCNT0[15:0], register 15h

ADCRSTENDCT0[15:0], register 16h

6399

0

Start of second ADC conversion reset pulse ADCRSTSTCT1[15:0], register 17h

1600

3200

4800

6399

End of second ADC conversion reset pulse

Start of third ADC conversion reset pulse

End of third ADC conversion reset pulse

Start of fourth ADC conversion reset pulse

End of fourth ADC conversion reset pulse

End of pulse repetition period

ADCRSTENDCT1[15:0], register 18h

ADCRSTSTCT2[15:0], register 19h

ADCRSTENDCT2[15:0], register 1Ah

ADCRSTSTCT3[15:0], register 1Bh

ADCRSTENDCT3[15:0], register 1Ch

PRPCOUNT[15:0], register 1Dh

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LED2 (RED LED)

On Signal

t₃

t₄

LED1 (IR LED)

On Signal

t₉

t₁₀

S_{LED2_amb}

,

Sample Ambient

[LED2 (RED) Phase]

t₆

t₅

S_LED1

,

Sample LED1 (IR)

t₇

t₈

S_{LED1_amb}

,

Sample Ambient

[LED1 (IR) Phase]

t₁₁

t₁₂

S_LED2

,

Sample LED2 (RED)

t₁

t₂

t₁₃

CONV_LED2

,

t₁₄

Convert LED2 (RED) Sample

CONV_{LED2_amb}

,

Convert Ambient Sample

[LED2 (RED) Phase]

t₁₅

t₁₆

CONV_LED1

Convert LED1 (IR) Sample

,

t₁₇

t₁₈

CONV_{LED1_amb}

,

Convert Ambient Sample

[LED1 (IR) Phase]

t₁₉

t₂₀

ADC Conversion

ADC Reset

t₂₃

t₂₅

t₂₇

t₂₁

t₂₈

t₂₂

t₂₄

t₂₆

Pulse Repetition Period,

One Cycle

t₀

t₂₉

(1) RED = LED2, IR = LED1.

Figure 41. Programmable Clock Edges

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CONV_LED2

Convert LED2 (RED) Sample

,

t₁₄

t₁₃

CONV_{LED2_amb}

Convert Ambient Sample

[LED2 (RED) Phase]

,

t₁₆

t₁₅

t₁₈

CONV_LED1

Convert LED1 (IR) Sample

,

t₁₇

CONV_{LED1_amb}

Convert Ambient Sample

[LED1 (IR) Phase]

,

t₂₀

t₁₉

ADC Conversion

One 4-MHz

Clock Cycle

t₂₁

t₂₃

t₂₂

t₂₅

t₂₄

t₂₇

t₂₆

ADC Reset

t₂₈

Pulse Repetition Period,

One Cycle

t₀

t₂₉

(1) RED = LED2, IR = LED1.

Figure 42. Relationship Between the ADC Reset and ADC Conversion Signals

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ADC OPERATION AND AVERAGING MODULE

The ADC reset signal must be positioned at 25% intervals of the pulse repetition period (that is, 0%, 25%, 50%,

and 75%). After the falling edge of the ADC reset signal, the ADC conversion phase starts (refer to Figure 42).

Each ADC conversion takes 50 µs.

The ADC operates with averaging. The averaging module averages multiple ADC samples and reduce noise to

improve dynamic range because the ADC conversion time is usually shorter than 25% of the pulse repetition

period. Figure 43 shows a diagram of the averaging module.

Rx Digital

ADC Reset

22-Bits

ADC Output Rate

PRF Samples per Second

Register

42

LED2 Data

ADC

Register

43

Ambient

(LED2) Data

LED2_Ambient Data

ADC

Averager

Register

44

LED1 Data

Ambient

(LED1) Data

Register

45

LED1_Ambient Data

ADC Reset

ADC Convert

ADC Clock

Register

30

Number of Averages

Figure 43. Averaging Module

Operation With Averaging

In this mode, the ADC digital samples are accumulated and averaged after every 50 µs. At the next rising edge

of the ADC reset signal, the average value (22-bit) is written into the output registers sequentially as follows (see

Figure 44):

•

At the 25% reset signal, the averaged 22-bit word is written to register 2Ah.

At the 50% reset signal, the averaged 22-bit word is written to register 2Bh.

At the 75% reset signal, the averaged 22-bit word is written to register 2Ch.

At the next 0% reset signal, the averaged 22-bit word is written to register 2Dh. The contents of registers 2Ah

and 2Bh are written to register 2Eh and the contents of registers 2Ch and 2Dh are written to register 2Fh.

At the rising edge of the ADC_RDY signal, the contents of all six result registers can be read out.

The number of samples to be used per conversion phase is preset to 3.

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ADC Conversion

ADC Data

2

3

4

6

7

8

10 11 12

14 15 16

18 19 20

1

5

9

13

17

ADC Reset

0%

Average of

ADC data 13 to 15 are written

into register 45.

75%

Average of

ADC data 9 to 11 are

written into

50%

25%

Average of

ADC data 1 to 3 are

written into

0%

Average of

ADC data 5 to 7

are written into

register 43.

register 42.

register 44.

Register 42 and register 43

are written into register 46.

Register 44 and register 45

are written into register 47.

ADC_RDY Pin

Pulse repetition period

T = 1/PRF

0 T

1.0 T

NOTE: This example shows data 3 averages.

Figure 44. ADC Data with Averaging

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RECEIVER SUBSYSTEM POWER PATH

The block diagram in Figure 45 shows the AFE4400 Rx subsystem power routing.

1.8 V

RX_ANA_SUP

(2.0 V to 3.6 V)

RX_ANA_SUP to

1.8-V Regulator

Rx Analog Modules

RX_DIG_SUP to

1.8-V Regulator

1.8 V

RX_DIG_SUP

(2.0 V to 3.6 V)

Rx I/O

Block

I/O

Pins

Rx Digital

Device

Figure 45. Receive Subsystem Power Routing

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TRANSMIT SECTION

The transmit section integrates the LED driver and the LED current control section with 8-bit resolution. This

integration is designed to meet a dynamic range of better than 105 dB (based on a 1-sigma LED current noise).

The LED2 and LED1 reference currents can be independently set. The current source (I_LED) locally regulates and

ensures that the actual LED current tracks the specified reference.

Two LED driver schemes are supported:

•

An H-bridge drive for a two-terminal back-to-back LED package, as shown in Figure 46. The minimum H-

bridge supply voltage must be 2.5 V + (maximum voltage drop across the LED).

•

A push-pull drive for a three-terminal LED package; see Figure 47. The minimum external supply voltage =

2.0 V + (maximum voltage drop across the LED).

3.3-V Supply

H-Bridge Supply

External

Supply

Tx

C_BULK

H-Bridge

LED2_ON

LED1_ON

H-Bridge

Driver

LED2_ON

Or

LED1_ON

LED2 Current

Reference

LED

Current

Control

I_LED

8-Bit Resolution

LED1 Current

Reference

Register

LED2 Current Reference

LED1 Current Reference

Figure 46. Transmit: H-Bridge Drive

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3.3-V Supply

H-Bridge Supply

External

Supply

C_BULK

Tx

LED2_ON

LED1_ON

H-Bridge

Driver

LED2_ON

Or

LED1_ON

LED2 Current

Reference

LED

Current

Control

I_LED

8-Bit Resolution

LED1 Current

Reference

Register

RED Current Reference

IR Current Reference

Figure 47. Transmit: Push-Pull LED Drive for Common Anode LED Configuration

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Transmitter Power Path

The block diagram in Figure 48 shows the AFE4400 Tx subsystem power routing.

TX_CTRL_SUP_3.3V

Tx Reference

and

Control

LED_DRV_SUP_3.3V

LED

Current

Control

DAC

Tx LED

Bridge

Device

Figure 48. Transmit Subsystem Power Routing

LED Power Reduction During Periods of Inactivity

The diagram in Figure 49 shows how LED bias current passes 50 µA whenever LED_ON occurs. In order to

minimize power consumption in periods of inactivity, the LED_ON control must be turned off. Furthermore, the

TIMEREN bit in the CONTROL1 register should be disabled by setting the value to '0'.

Note that depending on the LEDs used, the LED may sometimes appear dimly lit even when the LED current is

set to 0 mA. This appearance is because of the switching leakage currents (as shown in Figure 49) inherent to

the timer function. The dimmed appearance does not effect the ambient light level measurement because during

the ambient cycle, LED_ON is turned off for the duration of the ambient measurement.

0 mA to 50 mA

(See the LEDRANGE bits

in the LEDCNTRL register.)

1 mA

50 mA

LED_ON

Figure 49. LED Bias Current

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DIAGNOSTICS

The device includes diagnostics to detect open or short conditions of the LED and photosensor, LED current

profile feedback, and cable on or off detection.

Photodiode-Side Fault Detection

Figure 50 shows the diagnostic for the photodiode-side fault detection.

Internal

TX_CTRL_SUP

10 kꢀ

1 kꢀ

Cable

Rx On/Off

INM

INP

To Rx Front-End

Rx On/Off

GND Wires

PD Wires

LED Wires

Legend for Cable

Figure 50. Photodiode Diagnostic

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Transmitter-Side Fault Detection

Figure 51 shows the diagnostic for the transmitter-side fault detection.

Internal

TX_CTRL_SUP

10 kꢀ

Cable

TX_OUTP

D

C

TX_OUTM

GND Wires

PD Wires

LED DAC

LED Wires

Legend for Cable

Figure 51. Transmitter Diagnostic

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Figure 52 shows the timing for the diagnostic function.

DIAG_EN Register Bit = 1

Diagnostic State

Machine

Diagnostic State Machine

Diagnostic Starts

Diagnostic Ends

DIAG_END Pin

t_WIDTH= Four 4-MHz

Clock Cycles

t_DIAG

Figure 52. Diagnostic Timing Diagram

By default, the diagnostic function takes t_DIAG= 8 ms to complete.

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SERIAL PROGRAMMING INTERFACE

The SPI-compatible serial interface consists of four signals: SCLK (serial clock), SPISOMI (serial interface data

output), SPISIMO (serial interface data input), and SPISTE (serial interface enable).

The serial clock (SCLK) is the serial peripheral interface (SPI) serial clock. SCLK shifts in commands and shifts

out data from the device. SCLK features a Schmitt-triggered input and clocks data out on the SPISOMI. Data are

clocked in on the SPISIMO pin. Even though the input has hysteresis, TI recommends keeping SCLK as clean

as possible to prevent glitches from accidentally shifting the data. When the serial interface is idle, hold SCLK

low.

The SPI serial out master in (SPISOMI) pin is used with SCLK to clock out the AFE4400 data. The SPI serial in

master out (SPISIMO) pin is used with SCLK to clock in data to the AFE4400. The SPI serial interface enable

(SPISTE) pin enables the serial interface to clock data on the SPISIMO pin in to the device.

READING AND WRITING DATA

The device has a set of internal registers that can be accessed by the serial programming interface formed by

the SPISTE, SCLK, SPISIMO, and SPISOMI pins.

Writing Data

When SPISTE is low,

•

Serially shifting bits into the device is enabled.

Serial data (on the SPISIMO pin) are latched at every SCLK rising edge.

The serial data are loaded into the register at every 32nd SCLK rising edge.

In case the word length exceeds a multiple of 32 bits, the excess bits are ignored. Data can be loaded in

multiples of 32-bit words within a single active SPISTE pulse. The first eight bits form the register address and

the remaining 24 bits form the register data. Figure 53 shows a diagram of the write timing.

SPISTE

SPISIMO

SCLK

A7

A6

A1

A0

D23 D22

D17 D16

D15 D14

D9

D8

D7

D6

D1

D0

Don‘t care, can be high or low.

Figure 53. AFE SPI Write Timing Diagram

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Reading Data

The AFE4400 includes a mode where the contents of the internal registers can be read back on the SPISOMI

pin. This mode may be useful as a diagnostic check to verify the serial interface communication between the

external controller and the AFE. To enable this mode, first set the SPI_READ register bit using the SPI write

command, as described in the Writing Data section. In the next command, specify the SPI register address with

the desired content to be read. Within the same SPI command sequence, the AFE outputs the contents of the

specified register on the SPISOMI pin. Figure 54 shows a timing diagram for the SPI read operation.

SPISTE

SPISIMO

SPISOMI

A7

A6

A1

A0

D23 D22

D17 D16

D15 D14

D9

D8

D7

D6

D1

D0

SCLK

Don‘t care, can be high or low.

(1) The SPI_READ register bit must be enabled before attempting a serial readout from the AFE.

(2) Specify the register address of the content that must be readback on bits A[7:0].

(3) The AFE outputs the contents of the specified register on the SPISOMI pin.

Figure 54. AFE SPI Read Timing Diagram

Register Initialization

After power-up, the internal registers must be initialized to the default values. This initialization can be done in

one of two ways:

•

Through a hardware reset by applying a low-going pulse on the RESET pin, or

By applying a software reset. Using the serial interface, set SW_RESET (bit D3 in register 00h) high. This

setting initializes the internal registers to the default values and then self-resets to '0'. In this case, the RESET

pin is kept high (inactive).

AFE SPI Interface Design Considerations

Note that when the AFE4400 is deselected, the SPISOMI, CLKOUT, ADC_RDY, PD_ALM, LED_ALM, and

DIAG_END digital output pins do not enter a 3-state mode. This condition, therefore, must be taken into account

when connecting multiple devices to the SPI port and for power-management considerations.

AFE REGISTER MAP

The AFE consists of a set of registers that can be used to configure it, such as receiver timings, I-V amplifier

settings, transmit LED currents, and so forth. The registers and their contents are listed in Table 4. These

registers can be accessed using the AFE SPI interface.

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AFE REGISTER DESCRIPTION

CONTROL0: Control Register 0 (Address = 00h, Reset Value = 0000h)

D23

0

D22

0

D21

D20

D19

D18

D17

D16

D15

D14

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

D7

0

D6

0

D5

0

D4

0

D3

D2

D1

D0

TIM_

SPI_

READ

SW_RST DIAG_EN COUNT_

RST

This register is used for AFE software and count timer reset, diagnostics enable, and SPI read functions.

Bits D[23:4]

Bit D3

Must be '0'

SW_RST: Software reset

0 = No action (default after reset)

1 = Software reset applied; resets all internal registers to the default values and self-clears

to '0'

Bit D2

DIAG_EN: Diagnostic enable

0 = No action (default after reset)

1 = Diagnostic mode is enabled and the diagnostics sequence starts when this bit is set.

At the end of the sequence, all fault status are stored in the DIAG: Diagnostics Flag

Register. Afterwards, the DIAG_EN register bit self-clears to '0'.

Bit D1

Bit D0

TIM_CNT_RST: Timer counter reset

0 = Disables timer counter reset, required for normal timer operation (default after reset)

1 = Timer counters are in reset state

SPI READ: SPI read

0 = SPI read is disabled (default after reset)

1 = SPI read is enabled

LED2STC: Sample LED2 Start Count Register (Address = 01h, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D0

0

LED2STC[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

LED2STC[15:0]

This register sets the start timing value for the LED2 signal sample.

Bits D[23:16]

Bits D[15:0]

Must be '0'

LED2STC[15:0]: Sample LED2 start count

The contents of this register can be used to position the start of the sample LED2 signal with

respect to the pulse repetition period (PRP), as specified in the PRPCOUNT register. The

count is specified as the number of

4-MHz clock cycles. Refer to the Using the Timer Module section for details.

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D12

LED2ENDC: Sample LED2 End Count Register (Address = 02h, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

0

LED2ENDC[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

LED2ENDC[15:0]

This register sets the end timing value for the LED2 signal sample.

Bits D[23:16]

Bits D[15:0]

Must be '0'

LED2ENDC[15:0]: Sample LED2 end count

The contents of this register can be used to position the end of the sample LED2 signal with

respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the

number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.

LED2LEDSTC: LED2 LED Start Count Register (Address = 03h, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D3

D14

D13

D12

D0

0

LED2LEDSTC[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D2

D1

LED2LEDSTC[15:0]

This register sets the start timing value for when the LED2 signal turns on.

Bits D[23:16]

Bits D[15:0]

Must be '0'

LED2LEDSTC[15:0]: LED2 start count

The contents of this register can be used to position the start of the LED2 with respect to the

PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-

MHz clock cycles. Refer to the Using the Timer Module section for details.

LED2LEDENDC: LED2 LED End Count Register (Address = 04h, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D3

D14

D13

D12

D0

0

LED2LEDENDC[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D2

D1

LED2LEDENDC[15:0]

This register sets the end timing value for when the LED2 signal turns off.

Bits D[23:16]

Bits D[15:0]

Must be '0'

LED2LEDENDC[15:0]: LED2 end count

The contents of this register can be used to position the end of the LED2 signal with respect

to the PRP, as specified in the PRPCOUNT register. The count is specified as the number

of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.

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ALED2STC: Sample Ambient LED2 Start Count Register (Address = 05h, Reset Value = 0000h)

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

0

ALED2STC[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

ALED2STC[15:0]

This register sets the start timing value for the ambient LED2 signal sample.

Bits D[23:16]

Bits D[15:0]

Must be '0'

ALED2STC[15:0]: Sample ambient LED2 start count

The contents of this register can be used to position the start of the sample ambient LED2

signal with respect to the PRP, as specified in the PRPCOUNT register. The count is

specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section

for details.

ALED2ENDC: Sample Ambient LED2 End Count Register (Address = 06h, Reset Value = 0000h)

D23

D22

D21

D20

D19

D18

D17

D16

D15

D3

D14

D13

D12

D0

0

ALED2ENDC[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D2

D1

ALED2ENDC[15:0]

This register sets the end timing value for the ambient LED2 signal sample.

Bits D[23:16]

Bits D[15:0]

Must be '0'

ALED2ENDC[15:0]: Sample ambient LED2 end count

The contents of this register can be used to position the end of the sample ambient LED2

signal with respect to the PRP, as specified in the PRPCOUNT register. The count is

specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section

for details.

LED1STC: Sample LED1 Start Count Register (Address = 07h, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D3

D14

D13

D12

D0

0

LED1STC[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D2

D1

LED1STC[15:0]

This register sets the start timing value for the LED1 signal sample.

Bits D[23:17]

Bits D[16:0]

Must be '0'

LED1STC[15:0]: Sample LED1 start count

The contents of this register can be used to position the start of the sample LED1 signal with

respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the

number of

4-MHz clock cycles. Refer to the Using the Timer Module section for details.

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LED1ENDC: Sample LED1 End Count (Address = 08h, Reset Value = 0000h)

D23

0

D22

0

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D0

0

LED1ENDC[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

LED1ENDC[15:0]

This register sets the end timing value for the LED1 signal sample.

Bits D[23:17]

Bits D[16:0]

Must be '0'

LED1ENDC[15:0]: Sample LED1 end count

The contents of this register can be used to position the end of the sample LED1 signal with

respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the

number of

4-MHz clock cycles. Refer to the Using the Timer Module section for details.

LED1LEDSTC: LED1 LED Start Count Register (Address = 09h, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D3

D14

D13

D12

D0

0

LED1LEDSTC[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D2

D1

LED1LEDSTC[15:0]

This register sets the start timing value for when the LED1 signal turns on.

Bits D[23:16]

Bits D[15:0]

Must be '0'

LED1LEDSTC[15:0]: LED1 start count

The contents of this register can be used to position the start of the LED1 signal with respect

to the PRP, as specified in the PRPCOUNT register. The count is specified as the number

of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.

LED1LEDENDC: LED1 LED End Count Register (Address = 0Ah, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D3

D14

D13

D12

D0

0

LED1LEDENDC[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D2

D1

LED1LEDENDC[15:0]

This register sets the end timing value for when the LED1 signal turns off.

Bits D[23:16]

Bits D[15:0]

Must be '0'

LED1LEDENDC[15:0]: LED1 end count

The contents of this register can be used to position the end of the LED1 signal with respect

to the PRP, as specified in the PRPCOUNT register. The count is specified as the number

of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.

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ALED1STC: Sample Ambient LED1 Start Count Register (Address = 0Bh, Reset Value = 0000h)

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

0

ALED1STC[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

ALED1STC[15:0]

This register sets the start timing value for the ambient LED1 signal sample.

Bits D[23:16]

Bits D[15:0]

Must be '0'

ALED1STC[15:0]: Sample ambient LED1 start count

The contents of this register can be used to position the start of the sample ambient LED1

signal with respect to the PRP, as specified in the PRPCOUNT register. The count is

specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section

for details.

ALED1ENDC: Sample Ambient LED1 End Count Register (Address = 0Ch, Reset Value = 0000h)

D23

D22

D21

D20

D19

D18

D17

D16

D15

D3

D14

D13

D12

D0

0

ALED1ENDC[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D2

D1

ALED1ENDC[15:0]

This register sets the end timing value for the ambient LED1 signal sample.

Bits D[23:16]

Bits D[15:0]

Must be '0'

ALED1ENDC[15:0]: Sample ambient LED1 end count

The contents of this register can be used to position the end of the sample ambient LED1

signal with respect to the PRP, as specified in the PRPCOUNT register. The count is

specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section

for details.

LED2CONVST: LED2 Convert Start Count Register (Address = 0Dh, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D3

D14

D13

D12

D0

0

LED2CONVST[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D2

D1

LED2CONVST[15:0]

This register sets the start timing value for the LED2 conversion.

Bits D[23:16]

Bits D[15:0]

Must be '0'

LED2CONVST[15:0]: LED2 convert start count

The contents of this register can be used to position the start of the LED2 conversion signal

with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as

the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.

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LED2CONVEND: LED2 Convert End Count Register (Address = 0Eh, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D0

0

LED2CONVEND[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

LED2CONVEND[15:0]

This register sets the end timing value for the LED2 conversion.

Bits D[23:16]

Bits D[15:0]

Must be '0'

LED2CONVEND[15:0]: LED2 convert end count

The contents of this register can be used to position the end of the LED2 conversion signal

with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as

the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.

ALED2CONVST: LED2 Ambient Convert Start Count Register (Address = 0Fh, Reset Value = 0000h)

D23

D22

D21

D20

D19

D18

D17

D16

D15

D3

D14

D13

D12

D0

0

ALED2CONVST[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D2

D1

ALED2CONVST[15:0]

This register sets the start timing value for the ambient LED2 conversion.

Bits D[23:16]

Bits D[15:0]

Must be '0'

ALED2CONVST[15:0]: LED2 ambient convert start count

The contents of this register can be used to position the start of the LED2 ambient

conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The

count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer

Module section for details.

ALED2CONVEND: LED2 Ambient Convert End Count Register (Address = 10h, Reset Value = 0000h)

D23

D22

D21

D20

D19

D18

D17

D16

D15

D3

D14

D13

D12

D0

0

ALED2CONVEND[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D2

D1

ALED2CONVEND[15:0]

This register sets the end timing value for the ambient LED2 conversion.

Bits D[23:16]

Bits D[15:0]

Must be '0'

ALED2CONVEND[15:0]: LED2 ambient convert end count

The contents of this register can be used to position the end of the LED2 ambient

conversion signal with respect to the PRP. The count is specified as the number of 4-MHz

clock cycles. Refer to the Using the Timer Module section for details.

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LED1CONVST: LED1 Convert Start Count Register (Address = 11h, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D0

0

LED1CONVST[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

LED1CONVST[15:0]

This register sets the start timing value for the LED1 conversion.

Bits D[23:16]

Bits D[15:0]

Must be '0'

LED1CONVST[15:0]: LED1 convert start count

The contents of this register can be used to position the start of the LED1 conversion signal

with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as

the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.

LED1CONVEND: LED1 Convert End Count Register (Address = 12h, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D3

D14

D13

D12

D0

0

LED1CONVEND[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D2

D1

LED1CONVEND[15:0]

This register sets the end timing value for the LED1 conversion.

Bits D[23:16]

Bits D[15:0]

Must be '0'

LED1CONVEND[15:0]: LED1 convert end count

The contents of this register can be used to position the end of the LED1 conversion signal

with respect to the PRP. The count is specified as the number of 4-MHz clock cycles. Refer

to the Using the Timer Module section for details.

ALED1CONVST: LED1 Ambient Convert Start Count Register (Address = 13h, Reset Value = 0000h)

D23

D22

D21

D20

D19

D18

D17

D16

D15

D3

D14

D13

D12

D0

0

ALED1CONVST[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D2

D1

ALED1CONVST[15:0]

This register sets the start timing value for the ambient LED1 conversion.

Bits D[23:16]

Bits D[15:0]

Must be '0'

ALED1CONVST[15:0]: LED1 ambient convert start count

The contents of this register can be used to position the start of the LED1 ambient

conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The

count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer

Module section for details.

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ALED1CONVEND: LED1 Ambient Convert End Count Register (Address = 14h, Reset Value = 0000h)

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

0

ALED1CONVEND[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

ALED1CONVEND[15:0]

This register sets the end timing value for the ambient LED1 conversion.

Bits D[23:16]

Bits D[15:0]

Must be '0'

ALED1CONVEND[15:0]: LED1 ambient convert end count

The contents of this register can be used to position the end of the LED1 ambient

conversion signal with respect to the PRP. The count is specified as the number of 4-MHz

clock cycles. Refer to the Using the Timer Module section for details.

ADCRSTCNT0: ADC Reset 0 Start Count Register (Address = 15h, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D3

D14

D13

D12

D0

0

ADCRSTCNT0[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D2

D1

ADCRSTCNT0[15:0]

This register sets the start position of the ADC0 reset conversion signal.

Bits D[23:16]

Bits D[15:0]

Must be '0'

ADCRSTCNT0[15:0]: ADC RESET 0 start count

The contents of this register can be used to position the start of the ADC reset conversion

signal (default value after reset is 0000h). Refer to the Using the Timer Module section for

details.

ADCRSTENDCT0: ADC Reset 0 End Count Register (Address = 16h, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D3

D14

D13

D12

D0

0

ADCRSTENDCT0[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D2

D1

ADCRSTENDCT0[15:0]

This register sets the end position of the ADC0 reset conversion signal.

Bits D[23:16]

Bits D[15:0]

Must be '0'

ADCRSTENDCT0[15:0]: ADC RESET 0 end count

The contents of this register can be used to position the end of the ADC reset conversion

signal (default value after reset is 0000h). Refer to the Using the Timer Module section for

details.

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ADCRSTSTCT1: ADC Reset 1 Start Count Register (Address = 17h, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D0

0

ADCRSTSTCT1[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

ADCRSTSTCT1[15:0]

This register sets the start position of the ADC1 reset conversion signal.

Bits D[23:16]

Bits D[15:0]

Must be '0'

ADCRSTSTCT1[15:0]: ADC RESET 1 start count

The contents of this register can be used to position the start of the ADC reset conversion.

Refer to the Using the Timer Module section for details.

ADCRSTENDCT1: ADC Reset 1 End Count Register (Address = 18h, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D0

0

ADCRSTENDCT1[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

ADCRSTENDCT1[15:0]

This register sets the end position of the ADC1 reset conversion signal.

Bits D[23:16]

Bits D[15:0]

Must be '0'

ADCRSTENDCT1[15:0]: ADC RESET 1 end count

The contents of this register can be used to position the end of the ADC reset conversion.

Refer to the Using the Timer Module section for details.

ADCRSTSTCT2: ADC Reset 2 Start Count Register (Address = 19h, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D0

0

ADCRSTSTCT2[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

ADCRSTSTCT2[15:0]

This register sets the start position of the ADC2 reset conversion signal.

Bits D[23:16]

Bits D[15:0]

Must be '0'

ADCRSTSTCT2[15:0]: ADC RESET 2 start count

The contents of this register can be used to position the start of the ADC reset conversion.

Refer to the Using the Timer Module section for details.

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ADCRSTENDCT2: ADC Reset 2 End Count Register (Address = 1Ah, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D0

0

ADCRSTENDCT2[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

ADCRSTENDCT2[15:0]

This register sets the end position of the ADC2 reset conversion signal.

Bits D[23:16]

Bits D[15:0]

Must be '0'

ADCRSTENDCT2[15:0]: ADC RESET 2 end count

The contents of this register can be used to position the end of the ADC reset conversion.

Refer to the Using the Timer Module section for details.

ADCRSTSTCT3: ADC Reset 3 Start Count Register (Address = 1Bh, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D0

0

ADCRSTSTCT3[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

ADCRSTSTCT3[15:0]

This register sets the start position of the ADC3 reset conversion signal.

Bits D[23:16]

Bits D[15:0]

Must be '0'

ADCRSTSTCT3[15:0]: ADC RESET 3 start count

The contents of this register can be used to position the start of the ADC reset conversion.

Refer to the Using the Timer Module section for details.

ADCRSTENDCT3: ADC Reset 3 End Count Register (Address = 1Ch, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D0

0

ADCRSTENDCT3[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

ADCRSTENDCT3[15:0]

This register sets the end position of the ADC3 reset conversion signal.

Bits D[23:16]

Bits D[15:0]

Must be '0'

ADCRSTENDCT3[15:0]: ADC RESET 3 end count

The contents of this register can be used to position the end of the ADC reset conversion

signal (default value after reset is 0000h). Refer to the Using the Timer Module section for

details.

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PRPCOUNT: Pulse Repetition Period Count Register (Address = 1Dh, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D0

0

PRPCOUNT[15:0]

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

PRPCOUNT[15:0]

This register sets the device pulse repetition period count.

Bits D[23:16]

Bits D[15:0]

Must be '0'

PRPCOUNT[15:0]: Pulse repetition period count

The contents of this register can be used to set the pulse repetition period (in number of

clock cycles of the 4-MHz clock).

CONTROL1: Control Register 1 (Address = 1Eh, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

0

D12

0

D11

D10

D9

D8

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

1

D0

0

CLKALMPIN[2:0]

TIMEREN

This register configures the clock alarm pin and timer.

Bits D[23:12]

Bits D[11:9]

Must be '0'

CLKALMPIN[2:0]: Clocks on ALM pins

Internal clocks can be brought to the PD_ALM and LED_ALM pins for monitoring.

Note that the CLKALMPIN[2:0] register bits must be set before using this register bit.

Table 5 defines the settings for the two alarm pins.

Bit D8

TIMEREN: Timer enable

0 = Timer module is disabled and all internal clocks are off (default after reset)

1 = Timer module is enabled

Bits D[7:2]

Bit D1

Must be '0'

Must be '1'

Must be '0'

Bit D0

Table 5. PD_ALM and LED_ALM Pin Settings

CLKALMPIN[2:0]

PD_ALM PIN SIGNAL

Sample LED2

LED2 pulse

LED_ALM PIN SIGNAL

Sample LED1

LED1 pulse

000

001

010

011

100

101

110

111

Sample LED2

LED2 convert

LED2 ambient

No output

Sample LED1 pulse

LED1 convert

LED1 ambient

No output

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SPARE1: SPARE1 Register For Future Use (Address = 1Fh, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

0

D11

0

D10

0

D9

0

D8

0

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

This register is a spare register and is reserved for future use.

Bits D[23:0] Must be '0'

TIAGAIN: Transimpedance Amplifier Gain Setting Register (Address = 20h, Reset Value = 0000h)

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

0

D11

0

D10

0

D9

0

D8

0

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

This register is reserved for factory use.

Bits D[23:0] Must be '0'

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TIA_AMB_GAIN: Transimpedance Amplifier and Ambient Cancellation Stage Gain Register

(Address = 21h, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

0

STAGE2

EN

0

AMBDAC[3:0]

0

D11

0

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

STG2GAIN[2:0]

CF_LED[4:0]

RF_LED[2:0]

This register configures the ambient light cancellation amplifier gain, cancellation current, and filter corner

frequency.

Bits D[23:20]

Bits D[19:16]

Must be '0'

AMBDAC[3:0]: Ambient DAC value

These bits set the value of the cancellation current.

0000 = 0 µA (default after reset)

0001 = 1 µA

1000 = 8 µA

1001 = 9 µA

0010 = 2 µA

1010 = 10 µA

0011 = 3 µA

0100 = 4 µA

0101 = 5 µA

0110 = 6 µA

1011 = Do not use

1100 = Do not use

1101 = Do not use

1110 = Do not use

1111 = Do not use

0111 = 7 µA

Bit D15

Bit D14

Must be '0'

STAGE2EN: Stage 2 enable

0 = Stage 2 is bypassed (default after reset)

1 = Stage 2 is enabled with the gain value specified by the STG2GAIN[2:0] bits

Must be '0'

Bits D[13:11]

Bits D[10:8]

STG2GAIN[2:0]: Stage 2 gain setting

000 = 0 dB, or linear gain of 1 (default after reset)

001 = 3 dB, or linear gain of 1.414

010 = 6 dB, or linear gain of 2

011 = 9 dB, or linear gain of 2.818

100 = 12 dB, or linear gain of 4

101 = Do not use

110 = Do not use

111 = Do not use

Bits D[7:3]

Bits D[2:0]

CF_LED[4:0]: Program C_Ffor LEDs

00000 = 5 pF (default after reset)

00001 = 5 pF + 5 pF

00010 = 15 pF + 5 pF

00100 = 25 pF + 5 pF

01000 = 50 pF + 5 pF

10000 = 150 pF + 5 pF

Note that any combination of these C_Fsettings is also supported by setting multiple bits to

'1'. For example, to obtain C_F= 100 pF, set D[7:3] = 01111.

RF_LED[2:0]: Program R_Ffor LEDs

000 = 500 kΩ

001 = 250 kΩ

010 = 100 kΩ

011 = 50 kΩ

100 = 25 kΩ

101 = 10 kΩ

110 = 1 MΩ

111 = None

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LEDCNTRL: LED Control Register (Address = 22h, Reset Value = 0000h)

D23

0

D22

0

D21

D20

D19

D18

D17

D16

D15

D14

D13

D1

D12

LEDCUR

OFF

0

1

LED1[7:0]

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D0

LED1[7:0]

LED2[7:0]

This register sets the LED current range and the LED1 and LED2 drive current.

Bits D[23:18]

Bit D17

Must be '0'

LEDCUROFF: Turns the LED current source on or off

0 = On (50 mA)

1 = Off

Bit D16

Must be '1'

Bits D[15:8]

LED1[7:0]: Program LED current for LED1 signal

Use these register bits to specify the LED current setting for LED1 (default after reset is

00h).

The nominal value of the LED current is given by Equation 3, where the full-scale LED

current is 50 mA.

Bits D[7:0]

LED2[7:0]: Program LED current for LED2 signal

Use these register bits to specify the LED current setting for LED2 (default after reset is

00h).

The nominal value of LED current is given by Equation 4, where the full-scale LED current is

50 mA.

LED1[7:0]

´ Full-Scale Current

256

(3)

LED2[7:0]

´ Full-Scale Current

256

(4)

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CONTROL2: Control Register 2 (Address = 23h, Reset Value = 0000h)

D23

0

D22

0

D21

D20

D19

D18

D17

D16

D15

D14

D13

0

D12

0

1

0

D11

D10

0

D9

D8

1

D7

0

D6

0

D5

0

D4

0

D3

0

D2

D1

D0

TXBRG

MOD

XTAL

DIS

PDNTX

PDNRX PDNAFE

This register controls the LED transmitter, crystal, and the AFE, transmitter, and receiver power modes.

Bits D[23:18]

Bit D17

Must be '0'

Must be '1'

Bits D[16:12]

Bit D11

Must be '0'

TXBRGMOD: Tx bridge mode

0 = LED driver is configured as an H-bridge (default after reset)

1 = LED driver is configured as a push-pull

Bit D10

Bit D9

Must be '0'

XTALDIS: Crystal disable mode

0 = The crystal module is enabled; the 8-MHz crystal must be connected to the XIN and

XOUT pins

1 = The crystal module is disabled; an external 8-MHz clock must be applied to the XIN pin

Bit D8

Must be '1'

Bits D[7:3]

Bit D2

Must be '0'

PDN_TX: Tx power-down

0 = The Tx is powered up (default after reset)

1 = Only the Tx module is powered down

Bit D1

Bit D0

PDN_RX: Rx power-down

0 = The Rx is powered up (default after reset)

1 = Only the Rx module is powered down

PDN_AFE: AFE power-down

0 = The AFE is powered up (default after reset)

1 = The entire AFE is powered down (including the Tx, Rx, and diagnostics blocks)

SPARE2: SPARE2 Register For Future Use (Address = 24h, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

0

D11

0

D10

0

D9

0

D8

0

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

This register is a spare register and is reserved for future use.

Bits D[23:0] Must be '0'

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SPARE3: SPARE3 Register For Future Use (Address = 25h, Reset Value = 0000h)

D23

0

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

0

D11

0

D10

0

D9

0

D8

0

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

This register is a spare register and is reserved for future use.

Bits D[23:0] Must be '0'

SPARE4: SPARE4 Register For Future Use (Address = 26h, Reset Value = 0000h)

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

0

D11

0

D10

0

D9

0

D8

0

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

This register is a spare register and is reserved for future use.

Bits D[23:0] Must be '0'

RESERVED1: RESERVED1 Register For Factory Use Only (Address = 27h, Reset Value = XXXXh)

D23

X⁽¹⁾

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

X

D11

X

D10

X

D9

X

D8

X

D7

X

D6

X

D5

X

D4

X

D3

X

D2

X

D1

X

D0

X

(1) X = don't care.

This register is reserved for factory use. Readback values vary between devices.

RESERVED2: RESERVED2 Register For Factory Use Only (Address = 28h, Reset Value = XXXXh)

D23

X⁽¹⁾

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

X

D11

X

D10

X

D9

X

D8

X

D7

X

D6

X

D5

X

D4

X

D3

X

D2

X

D1

X

D0

X

(1) X = don't care.

This register is reserved for factory use. Readback values vary between devices.

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ALARM: Alarm Register (Address = 29h, Reset Value = 0000h)

D23

0

D22

0

D21

D20

D19

D18

D17

D16

D15

D14

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

D7

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

ALMPIN

CLKEN

This register controls the Alarm pin functionality.

Bits D[23:8]

Bit D7

Must be '0'

ALMPINCLKEN: Alarm pin clock enable

0 = Disables the monitoring of internal clocks; the PD_ALM and LED_ALM pins function as

diagnostic fault alarm output pins (default after reset)

1 = Enables the monitoring of internal clocks; these clocks can be brought out on PD_ALM

and LED_ALM selectively (depending on the value of the CLKALMPIN[2:0] register bits).

Bits D[6:0]

Must be '0'

LED2VAL: LED2 Digital Sample Value Register (Address = 2Ah, Reset Value = 0000h)

D23

D11

D22

D21

D9

D20

D8

D19

D18

D17

D16

D15

D14

D13

D12

D0

LED2VAL[23:0]

D10

D7

D6

D5

D4

D3

D2

D1

LED2VAL[23:0]

Bits D[23:0]

LED2VAL[23:0]: LED2 digital value

This register contains the digital value of the latest LED2 sample converted by the ADC. The

ADC_RDY signal goes high each time that the contents of this register are updated. The

host processor must readout this register before the next sample is converted by the AFE.

ALED2VAL: Ambient LED2 Digital Sample Value Register (Address = 2Bh, Reset Value = 0000h)

D23

D22

D21

D9

D20

D8

D19

D7

D18

D17

D16

D4

D15

D3

D14

D2

D13

D1

D12

D0

ALED2VAL[23:0]

D11

D10

D6

D5

ALED2VAL[23:0]

Bits D[23:0]

ALED2VAL[23:0]: LED2 ambient digital value

This register contains the digital value of the latest LED2 ambient sample converted by the

ADC. The ADC_RDY signal goes high each time that the contents of this register are

updated. The host processor must readout this register before the next sample is converted

by the AFE.

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D12

LED1VAL: LED1 Digital Sample Value Register (Address = 2Ch, Reset Value = 0000h)

D23

D11

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

LED1VAL[23:0]

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

LED1VAL[23:0]

Bits D[23:0]

LED1VAL[23:0]: LED1 digital value

This register contains the digital value of the latest LED1 sample converted by the ADC. The

ADC_RDY signal goes high each time that the contents of this register are updated. The

host processor must readout this register before the next sample is converted by the AFE.

ALED1VAL: Ambient LED1 Digital Sample Value Register (Address = 2Dh, Reset Value = 0000h)

D23

D22

D21

D9

D20

D8

D19

D7

D18

D17

D16

D4

D15

D3

D14

D2

D13

D1

D12

D0

ALED1VAL[23:0]

D11

D10

D6

D5

ALED1VAL[23:0]

Bits D[23:0]

ALED1VAL[23:0]: LED1 ambient digital value

This register contains the digital value of the latest LED1 ambient sample converted by the

ADC. The ADC_RDY signal goes high each time that the contents of this register are

updated. The host processor must readout this register before the next sample is converted

by the AFE.

LED2-ALED2VAL: LED2-Ambient LED2 Digital Sample Value Register

(Address = 2Eh, Reset Value = 0000h)

D23

D11

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D1

D12

D0

LED2-ALED2VAL[23:0]

D10

D9

D8

D7

D6

D5

D4

D3

D2

LED2-ALED2VAL[23:0]

Bits D[23:0]

LED2-ALED2VAL[23:0]: (LED2 – LED2 ambient) digital value

This register contains the digital value of the LED2 sample after the LED2 ambient is

subtracted. The host processor must readout this register before the next sample is

converted by the AFE.

Note that this value is inverted when compared to waveforms shown in many publications.

LED1-ALED1VAL: LED1-Ambient LED1 Digital Sample Value Register

(Address = 2Fh, Reset Value = 0000h)

D23

D11

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D1

D12

D0

LED1-ALED1VAL[23:0]

D10

D9

D8

D7

D6

D5

D4

D3

D2

LED1-ALED1VAL[23:0]

Bits D[23:0]

LED1-ALED1VAL[23:0]: (LED1 – LED1 ambient) digital value

This register contains the digital value of the LED1 sample after the LED1 ambient is

subtracted from it. The host processor must readout this register before the next sample is

converted by the AFE.

Note that this value is inverted when compared to waveforms shown in many publications.

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DIAG: Diagnostics Flag Register (Address = 30h, Reset Value = 0000h)

D23

0

D22

0

D21

D20

D19

D18

D17

D16

D15

D14

D13

0

D12

0

PD_ALM

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

LED_

ALM

LED1

OPEN

LED2

OPEN

OUTPSH OUTNSH

GND GND

INNSC

GND

INPSC

GND

INNSC

LED

INPSC

LED

LEDSC

PDOC

PDSC

This register is read only. This register contains the status of all diagnostic flags at the end of the diagnostics

sequence. The end of the diagnostics sequence is indicated by the signal going high on DIAG_END pin.

Bits D[23:13]

Bit D12

Read only

PD_ALM: Power-down alarm status diagnostic flag

This bit indicates the status of PD_ALM (and the PD_ALM pin).

0 = No fault (default after reset)

1 = Fault present

Bit D11

Bit D10

Bit D9

Bit D8

Bit D7

Bit D6

Bit D5

Bit D4

LED_ALM: LED alarm status diagnostic flag

This bit indicates the status of LED_ALM (and the LED_ALM pin).

0 = No fault (default after reset)

1 = Fault present

LED1OPEN: LED1 open diagnostic flag

This bit indicates that LED1 is open.

0 = No fault (default after reset)

1 = Fault present

LED2OPEN: LED2 open diagnostic flag

This bit indicates that LED2 is open.

0 = No fault (default after reset)

1 = Fault present

LEDSC: LED short diagnostic flag

This bit indicates an LED short.

0 = No fault (default after reset)

1 = Fault present

OUTPSHGND: OUTP to GND diagnostic flag

This bit indicates that OUTP is shorted to the GND cable.

0 = No fault (default after reset)

1 = Fault present

OUTNSHGND: OUTN to GND diagnostic flag

This bit indicates that OUTN is shorted to the GND cable.

0 = No fault (default after reset)

1 = Fault present

PDOC: PD open diagnostic flag

This bit indicates that PD is open.

0 = No fault (default after reset)

1 = Fault present

PDSC: PD short diagnostic flag

This bit indicates a PD short.

0 = No fault (default after reset)

1 = Fault present

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Bit D3

Bit D2

Bit D1

Bit D0

INNSCGND: INN to GND diagnostic flag

This bit indicates a short from the INN pin to the GND cable.

0 = No fault (default after reset)

1 = Fault present

INPSCGND: INP to GND diagnostic flag

This bit indicates a short from the INP pin to the GND cable.

0 = No fault (default after reset)

1 = Fault present

INNSCLED: INN to LED diagnostic flag

This bit indicates a short from the INN pin to the LED cable.

0 = No fault (default after reset)

1 = Fault present

INPSCLED: INP to LED diagnostic flag

This bit indicates a short from the INP pin to the LED cable.

0 = No fault (default after reset)

1 = Fault present

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PACKAGE MATERIALS INFORMATION

www.ti.com

29-May-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

AFE4400RHAR

AFE4400RHAT

VQFN

RHA

40

2500

250

330.0

180.0

16.4

6.3

1.5

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

29-May-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

AFE4400RHAR

AFE4400RHAT

VQFN

RHA

40

2500

250

367.0

210.0

367.0

185.0

38.0

35.0

Pack Materials-Page 2

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型号：	AFE4490_14
厂家：	TEXAS INSTRUMENTS
描述：	Integrated Analog Front-End for Pulse Oximeters
文件：	总69页 (文件大小：1728K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AFE4490_14 [TI]

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