AFE5805ZCF [TI]
FULLY-INTEGRATED,8-CHANNEL ANALOG FRONT-END FOR ULTRASOUND 0.85nV/√Hz, 12-Bit, 50MSPS, 122mW/Channel; 完全集成的8通道模拟前端超声0.85nV / √Hz的, 12位, 50MSPS , 122mW /通道型号: | AFE5805ZCF |
厂家: | TEXAS INSTRUMENTS |
描述: | FULLY-INTEGRATED,8-CHANNEL ANALOG FRONT-END FOR ULTRASOUND 0.85nV/√Hz, 12-Bit, 50MSPS, 122mW/Channel |
文件: | 总52页 (文件大小:831K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
AFE5805
www.ti.com
SBOS421D –MARCH 2008–REVISED MARCH 2010
FULLY-INTEGRATED, 8-CHANNEL ANALOG FRONT-END FOR ULTRASOUND
0.85nV/√Hz, 12-Bit, 50MSPS, 122mW/Channel
Check for Samples: AFE5805
1
FEATURES
DESCRIPTION
23
•
8-Channel Complete Analog Front-End:
LNA, VCA, PGA, LPF, and ADC
Ultra-Low, Full-Channel Noise:
The AFE5805 is a complete analog front-end device
specifically designed for ultrasound systems that
require low power and small size.
–
•
•
•
The AFE5805 consists of eight channels, including a
–
–
0.85nV/√Hz (TGC)
1.1nV/√Hz (CW)
low-noise
attenuator (VCA), programmable gain amplifier
(PGA), low-pass filter (LPF), and 12-bit
amplifier
(LNA),
voltage-controlled
Low Power:
a
analog-to-digital converter (ADC) with low voltage
differential signaling (LVDS) data outputs.
–
–
122mW/Channel (40MSPS)
74mW/Channel (CW Mode)
The LNA gain is set for 20dB gain, and has excellent
noise and signal handling capabilities, including fast
overload recovery. VCA gain can vary over a 46dB
range with a 0V to 1.2V control voltage common to all
channels of the AFE5805.
Low-Noise Pre-Amp (LNA):
–
–
–
0.75nV/√Hz
20dB Fixed Gain
250mVPP Linear Input Range
•
Variable-Gain Amplifier:
Gain Control Range: 46dB
The PGA can be programmed for gains of 20dB,
25dB, 27dB, and 30dB. The internal low-pass filter
can also be programmed to 10MHz or 15MHz.
–
•
•
PGA Gain Settings: 20dB, 25dB, 27dB, 30dB
Low-Pass Filter:
The LVDS outputs of the ADC reduce the number of
interface lines to an ASIC or FPGA, thereby enabling
the high system integration densities desired for
portable systems. The ADC can either be operated
with internal or external references. The ADC also
features a signal-to-noise ratio (SNR) enhancement
mode that can be useful at high gains.
–
–
Selectable BW: 10MHz, 15MHz
2nd-Order
•
•
•
•
•
•
Gain Error: ±0.5dB
Channel Matching: ±0.25dB
Distortion, HD2: –65dBFS at 5MHz
Clamping Control
The AFE5805 is available in a 15mm × 9mm,
135-ball
BGA
package
that
is
Pb-free
Fast Overload Recovery: Two Clock Cycles
12-Bit Analog-to-Digital Converter:
(RoHS-compliant) and green. It is specified for
operation from 0°C to +70°C.
–
–
–
10MSPS to 50MSPS
69.5dB SNR at 10MHz
Serial LVDS Interface
Logic/Controls
SPI
LVDS
OUT
•
•
Integrated CW Switch Matrix
IN1
Clamp
and
LPF
.
.
.
.
12-Bit
ADC
15mm × 9mm, 135-BGA Package:
8 Channels
LNA
VCA/PGA
CH1
.
.
CH8
IN8
–
Pb-Free (RoHS-Compliant) and Green
Reference
APPLICATIONS
CW Switch Matrix (8 ´ 10)
•
Medical Imaging, Ultrasound
AFE5805
IOUT (10)
–
Portable Systems
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
Infineon is a registered trademark of Infineon Technologies.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2010, Texas Instruments Incorporated
AFE5805
SBOS421D –MARCH 2008–REVISED MARCH 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION(1) (2)
OPERATING
PACKAGE
PACKAGE-LEAD DESIGNATOR
TEMPERATURE
RANGE
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
ECO STATUS
AFE5805ZCFR Tape and Reel, 1000
AFE5805
mFBGA-135
ZCF
0°C to +70°C
AFE5805ZCFT
AFE5805ZCF
Tape and Reel, 250
Tray, 160
Pb-Free, Green
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) These packages conform to Lead (Pb)-free and green manufacturing specifications. Additional details including specific material content
can be accessed at www.ti.com/leadfree.
GREEN: TI defines Green to mean Lead (Pb)-Free and in addition, uses less package materials that do not contain halogens, including
bromine (Br), or antimony (Sb) above 0.1%of total product weight. N/A: Not yet available Lead (Pb)-Free; for estimated conversion
dates, go to www.ti.com/leadfree. Pb-FREE: TI defines Lead (Pb)-Free to mean RoHS compatible, including a lead concentration that
does not exceed 0.1% of total product weight, and, if designed to be soldered, suitable for use in specified lead-free soldering
processes.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
AFE5805
UNIT
V
Supply voltage range, AVDD1
Supply voltage range, AVDD2
Supply voltage range, AVDD_5V
Supply voltage range, DVDD
Supply voltage range, LVDD
Voltage between AVSS1 and LVSS
Voltage at analog inputs
–0.3 to +3.9
–0.3 to +3.9
V
–0.3 to +6
V
–0.3 to +3.9
V
–0.3 to +2.2
V
–0.3 to +0.3
V
–0.3 to minimum [3.6, (AVDD2 + 0.3)]
V
External voltage applied to REFT-pin
External voltage applied to REFB-pin
Voltage at digital inputs
–0.3 to +3
V
–0.3 to +2
V
–0.3 to minimum [3.9, (AVDD2 + 0.3)]
V
Peak solder temperature(2)
Maximum junction temperature, TJ
Storage temperature range
Operating temperature range
HBM
+260
+125
°C
°C
°C
°C
V
–55 to +150
0 to +70
2000
ESD ratings
CDM
MM
1000
V
100
V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) Device complies with JSTD-020D.
2
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SBOS421D –MARCH 2008–REVISED MARCH 2010
ELECTRICAL CHARACTERISTICS
AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled (1.0mF),
VCNTL = 1.0V, fIN = 5MHz, Clock = 40MSPS, 50% duty cycle, internal reference mode, ISET = 56kΩ, LVDS buffer
setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
AFE5805
PARAMETER
PREAMPLIFIER (LNA)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Gain
A
SE-input to differential output
Linear operation (HD2 ≤ –40dB)
Limited by internal diodes
RS = 0Ω, f = 1MHz
20
250
600
0.75
3
dB
mVPP
mVPP
nV/√Hz
pA/√Hz
V
Input voltage
VIN
blankMaximum input voltage
Input voltage noise (TGC)
Input current noise
Common-mode voltage, input
Bandwidth
Input resistance(1)
Input capacitance(1)
en (RTI)
In (RTI)
VCMI
Internally generated
Small-signal, –3dB
2.4
70
BW
MHz
kΩ
At f = 4MHz
8
Includes internal ESD and clamping diodes
16
pF
FULL-SIGNAL CHANNEL (LNA+VCA+LPF+ADC)
Input voltage noise (TGC)
en
RS = 0Ω, f = 2MHz, PGA = 30dB
RS = 0Ω, f = 2MHz, PGA = 20dB
RS = 200Ω, f = 5MHz
0.85
1.08
1.5
nV/√Hz
nV/√Hz
Noise figure
NF
dB
Low-pass filter bandwidth
Bandwidth tolerance
High-pass filter
LPF
at –3dB, selectable through SPI
10, 15
±10
200
±3
MHz
%
kHz
HPF
(First-order, due to internal ac-coupling)
Group delay variation
Overload recovery
ACCURACY
ns
≤ 6dB overload to within 1%
2
Clock Cycles
Gain (PGA)
Total gain, max(2)
Selectable through SPI
LNA + PGA gain, VCNTL = 1.2V
VCNTL = 0V to 1.2V
20, 25, 27, 30
dB
dB
48
49.5
46
51
Gain range
dB
VCNTL = 0.1V to 1.0V
0V < VCNTL < 0.1V
40
dB
Gain error, absolute(3)
±0.5
±0.5
±0.5
±0.25
dB
0.1V < VCNTL < 1.0V
–1.5
+1.5
dB
1.0V < VCNTL < 1.2V
dB
Gain matching
Offset error
Channel-to-channel
–0.5
–39
+0.5
+39
dB
VCNTL = 1.0V, PGA = 30dB
LSB
ppm/°C
VPP
VPP
Offset error drift (tempco)
Clamp level
±5
1.7
2.8
CL = 0
CL = 1 (clamp disabled)
GAIN CONTROL (VCA)
Input voltage range
Gain slope
VCNTL
Gain range = 46dB
VCNTL = 0.1V to 1.0V
0 to 1.2
44.4
25
V
dB/V
kΩ
Input resistance
Response time
VCNTL = 0V to 1.2V step; to 90% signal
0.5
ms
DYNAMIC PERFORMANCE
Signal-to-noise ratio
SNR
fIN = 2MHz; –1dBFS, PGA = 30dB
fIN = 5MHz; –1dBFS, PGA = 30dB
fIN = 10MHz; –1dBFS, PGA = 30dB
59.8
59.6
58.8
dBFS
dBFS
dBFS
(1) See Figure 33.
(2) Excludes digital gain within ADC.
(3) Excludes error of internal reference.
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SBOS421D –MARCH 2008–REVISED MARCH 2010
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ELECTRICAL CHARACTERISTICS (continued)
AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled (1.0mF),
VCNTL = 1.0V, fIN = 5MHz, Clock = 40MSPS, 50% duty cycle, internal reference mode, ISET = 56kΩ, LVDS buffer
setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
AFE5805
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE (continued)
Second-harmonic distortion
Third-harmonic distortion
HD2
fIN = 2MHz; –1dBFS, PGA = 30dB
fIN = 5MHz; –1dBFS, PGA = 30dB
fIN = 5MHz; –6dBFS, PGA = 20dB
fIN = 2MHz; –1dBFS, PGA = 30dB
fIN = 5MHz; –1dBFS, PGA = 30dB
fIN = 5MHz; –6dBFS, PGA = 20dB
–70
–65
–69
–58
–59
–78
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
–54
–61
HD3
IMD3
en
–51
–56
f1 = 4.99MHz at –6dBFS,
f2 = 5.01MHz at –32dBFS
Intermodulation distortion
58.5
–67
dBc
dBc
Crosstalk
fIN = 5MHz, –1dBFS, PGA = 30dB
CW—SIGNAL CHANNELS
Input voltage noise (CW)
Output noise correlation factor
Output transconductance
RS = 0Ω, f = 1MHz
1.1
0.6
nV/√Hz
Summing of eight channels
dB
At VIN = 100mVPP
14
15.6
18
mA/V
(IOUT/VIN
)
Dynamic CW output current,
maximum
IOUTAC
IOUTDC
VCM
2.9
0.9
2.5
mAPP
mA
V
Static CW output current (sink)
Output common-mode
voltage(4)
Output impedance
Output capacitance
50
10
kΩ
pF
INTERNAL REFERENCE VOLTAGES (ADC)
Reference top
VREFT
VREFB
0.5
2.5
2
V
V
V
Reference bottom
VREFT – VREFB
1.95
2.05
Common-mode voltage
(internal)
VCM
1.425
1.5
±2
1.575
V
VCM output current
mA
EXTERNAL REFERENCE VOLTAGES (ADC)
Reference top
VREFT
VREFB
2.4
0.4
1.9
2.5
0.5
2.6
0.6
2.1
V
V
Reference bottom
VREFT – VREFB
Switching current(5)
V
2.5
mA
(4) CW outputs require an externally applied bias voltage of +2.5V.
(5) Current drawn by the eight ADC channels from the external reference voltages; sourcing for VREFT, sinking for VREFB.
4
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SBOS421D –MARCH 2008–REVISED MARCH 2010
ELECTRICAL CHARACTERISTICS (continued)
AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled (1.0mF),
VCNTL = 1.0V, fIN = 5MHz, Clock = 40MSPS, 50% duty cycle, internal reference mode, ISET = 56kΩ, LVDS buffer
setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
AFE5805
PARAMETER
POWER SUPPLY
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply Voltages
AVDD1, AVDD2, DVDD
AVDD_5V
Operating
Operating
3.15
4.75
1.7
3.3
5
3.47
5.25
1.9
V
V
V
LVDD
1.8
Supply Currents
IAVDD1 (ADC)
IAVDD2 (VCA)
at 40MSPS
TGC mode
CW mode
TGC mode
CW mode
99
146
79
110
156
85
mA
mA
mA
mA
mA
mA
mA
mW
mW
mW
IAVDD_5V (VCA)
8
10
55
61
IDVDD (VCA)
1.5
70
3.0
80
ILVDD (ADC)
At 40MSPS
Power dissipation, total
All channels, TGC mode, no signal
All channels, CW mode , no signal(6)
TGC mode, no clock applied, no signal
980
580
615
1080
620
POWER-DOWN MODES
Power-down dissipation, total
Power-down response time(7)
Power-up response time(7)
Power-down dissipation(7)
THERMAL CHARACTERISTICS
Temperature range
Complete power-down mode
64
1.0
50
85
mW
ms
PD to valid output (90% level)
Partial power-down mode
ms
233
mW
0
+70
°C
Thermal resistance
TJA
TJC
32
°C/W
°C/W
4.2
(6) The ADC section is powered down during CW mode operation.
(7) With VCA_PD and ADC_PD pins = high. The ADC_PD pin is configured for partial power-down (see the Power-Down Modes section).
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DIGITAL CHARACTERISTICS
DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level
'0' or '1'. At CLOAD = 5pF(1), IOUT = 3.5mA(2), RLOAD = 100Ω(2), and no internal termination, unless otherwise noted.
AFE5805
PARAMETER
DIGITAL INPUTS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current(3)
Input capacitance
1.4
0
3.3
0.3
V
V
10
–10
3
mA
mA
pF
LVDS OUTPUTS
High-level output voltage
Low-level output voltage
Output differential voltage, |VOD
VOS output offset voltage(2)
1375
1025
350
mV
mV
mV
mV
|
Common-mode voltage of OUTP and OUTM
1200
Output capacitance inside the device,
from either output to ground
Output capacitance
2
pF
FCLKP and FCLKM
LCLKP and LCLKM
CLOCK
10
60
1x (clock rate)
6x (clock rate)
50
MHz
MHz
300
Clock input rate
Clock duty cycle
10
50
MSPS
%
50
3
Clock input amplitude, differential
(VCLKP – VCLKM)
Sine-wave, ac-coupled
VPP
LVPECL, ac-coupled
LVDS, ac-coupled
1.6
0.7
VPP
VPP
Clock input amplitude, single-ended
(VCLKP)
High-level input voltage, VIH
Low-level input voltage, VIL
CMOS
CMOS
2.2
V
V
0.6
(1) CLOAD is the effective external single-ended load capacitance between each output pin and ground.
(2) IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.
(3) Except pin J3 (INT/EXT), which has an internal pull-up resistor (52kΩ) to 3.3V.
6
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SBOS421D –MARCH 2008–REVISED MARCH 2010
FUNCTIONAL BLOCK DIAGRAM
AFE5805
LCLKP
LCLKM
6x ADCLK
Clock
Buffer
12x ADCLK
PLL
FCLKP
FCLKM
1x ADCLK
OUT1P
Serializer
OUT1M
12-Bit
ADC
IN1
LNA
VCA
PGA
LPF
Digital
Channels
2 to 7
OUT8P
Serializer
OUT8M
12-Bit
ADC
IN8
LNA
VCA
PGA
LPF
Digital
20,25,27
30dB
10,15MHz
VCNTL
Power-
CW Switch Matrix
(8x10)
Down
ADC
Control
Registers
Reference
CW[0:9]
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PIN CONFIGURATION
ZCF PACKAGE
135-BGA
BOTTOM VIEW
OUT4M OUT3M OUT2M OUT1M
LVSS
LVDD
LVSS
OUT5M OUT6M OUT7M OUT8M
R
OUT4P OUT3P OUT2P OUT1P
OUT5P
LVDD
OUT6P OUT7P OUT8P
P
N
M
L
LCLKP LCLKM
LVSS
LVSS
LVDD
AVSS1
AVSS1
FCLKM FCLKP
DNC
DNC
AVSS1 AVSS1
AVSS1 AVSS1
AVSS1 AVSS1
DNC
DNC
AVSS1
AVDD1
CLKP
CLKM
AVDD1
DNC
AVSS1
EN_SM
ISET
AVDD1
DNC
AVSS2
VCA_CS
AVSS2
AVSS2
AVDD1 AVDD1
AVSS2 AVSS2
AVDD1
AVDD1
CS
CM
K
J
INT/EXT
AVSS1 AVDD1
REFT
SDATA
AVDD2
VB6
REFB
ADS_
RESET
ADS_PD
CW5
DNC
DNC
VCM
VB5
RST
SCLK
H
G
F
AVDD2
AVSS2 AVSS2
VREFL
VREFH
CW4
CW3
AVSS2
CW6
VB1
AVSS2
VB3
CW7 AVDD_5V
AVSS2
AVSS2
AVSS2 AVSS2
VB4
AVSS2
AVSS2
VBL7
IN7
AVDD_5V CW2
E
D
C
B
A
AVSS2
CW8
CW9
VBL1
VCNTL
DVDD
DVDD
DNC
AVSS2
AVSS2
VBL8
VB2
AVDD2
VBL6
IN6
CW1
CW0
VBL5
AVDD2 AVSS2 AVSS2
VBL2
IN2
2
VBL3
IN3
VBL4
IN4
VCA_PD
IN1
1
IN8
6
IN5
9
3
4
5
7
8
Columns
8
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SBOS421D –MARCH 2008–REVISED MARCH 2010
ZCF PACKAGE
135-BGA
CONFIGURATION MAP (TOP VIEW)
R
P
N
M
L
OUT8M
OUT8P
FCLKP
DNC
OUT7M
OUT7P
FCLKM
DNC
OUT6M
OUT6P
LVDD
OUT5M
OUT5P
LVDD
LVSS
LVDD
OUT1M
OUT1P
LVSS
OUT2M
OUT2P
LVSS
OUT3M
OUT3P
LCLKM
DNC
OUT4M
OUT4P
LCLKP
DNC
LVSS
AVSS1
AVSS1
AVDD1
AVDD1
CS
AVSS1
AVSS1
AVDD1
AVSS2
SCLK
AVSS1
AVSS1
AVDD1
AVSS2
RST
AVSS1
AVSS1
DNC
AVSS1
AVSS1
AVDD1
INT/EXT
DNC
EN_SM
ISET
AVDD1
CM
AVDD1
DNC
CLKP
CLKM
AVSS1
ADS_PD
CW5
K
J
REFB
REFT
AVSS2
VCA_CS
AVSS2
AVSS2
AVSS2
AVSS2
AVSS2
VBL4
AVDD1
DNC
H
G
F
ADS_RESET
CW4
SDATA
AVDD2
VB6
VREFL
VREFH
VB4
AVSS2
AVSS2
AVSS2
AVSS2
AVSS2
VBL8
AVSS2
AVSS2
AVSS2
DVDD
DVDD
DNC
VCM
AVDD2
VB1
CW3
VB5
CW6
E
D
C
B
A
CW2
AVDD_5V
VB2
VB3
AVDD_5V
VCNTL
AVDD2
VBL2
CW7
CW1
AVSS2
AVSS2
VBL7
AVSS2
AVSS2
VBL3
CW8
CW0
AVDD2
VBL6
CW9
VBL5
VBL1
IN5
IN6
IN7
IN8
VCA_PD
IN4
IN3
IN2
IN1
9
8
7
6
5
4
3
2
1
Legend: AVDD1
AVDD2
+3.3V; Analog
+3.3V; Analog
+3.3V; Analog
+1.8V; Digital
+5V; Analog
DVDD
LVDD
AVDD_5V
AVSS1
AVSS2
LVSS
Analog Ground
Analog Ground
Digital Ground
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Table 1. TERMINAL FUNCTIONS
PIN NO.
H7
PIN NAME
CS
FUNCTION
Input
DESCRIPTION
Chip select for serial interface; active low
H1
ADS_PD
ADS_RESET
SCLK
Input
Power-down pin for ADS; active high. See the Power-Down Modes section for more information.
RESET input for ADS; active low
H9
Input
H6
Input
Serial clock input for serial interface
H8
SDATA
Input
Serial data input for serial interface
J2, L2, K7, J7,
K3, L8, K5, K6
AVDD1
AVSS1
POWER
GND
3.3V analog supply for ADS
Analog ground for ADS
L3, M3, L4, M4,
L5, M5, L6, M6,
L7, M7, J1
P5, N6, N7
N3, N4, N5, R5
C5, D5
LVDD
LVSS
POWER
GND
1.8V digital supply for ADS
Digital ground for ADS
DVDD
POWER
POWER
POWER
3.3V digital supply for the VCA; connect to the 3.3V analog supply (AVDD2).
3.3V analog supply for VCA
C2, C8, G2, G8
E2, E8
AVDD2
AVDD_5V
5V supply for VCA
C3, D3, C4, D4,
E4, F4, G4, E5,
F5, G5, C6, D6,
E6, F6, G6, C7,
D7, J4, J5, J6
AVSS2
GND
Analog ground for VCA
K1
L1
CLKM
CLKP
CM
Input
Input
Negative clock input for ADS (connect to Ground in single-ended clock mode)
Positive clock input for ADS
K8
C9
D9
E9
F9
G9
G1
F1
E1
D1
C1
L9
Input/Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
1.5V common-mode I/O for ADS. Becomes input pin in one of the external reference modes.
CW0
CW output 0
CW1
CW output 1
CW2
CW output 2
CW3
CW output 3
CW4
CW output 4
CW5
CW output 5
CW6
CW output 6
CW7
CW output 7
CW8
CW output 8
CW9
CW output 9
EN_SM
FCLKM
FCLKP
IN1
Enables access to the VCA register. Active high. Connect permanently to 3.3V (AVDD1).
LVDS frame clock (negative output)
LVDS frame clock (positive output)
LNA input Channel 1
N8
N9
A1
A2
A3
A4
A9
A8
A7
A6
J3
Output
Output
Input
IN2
Input
LNA input Channel 2
IN3
Input
LNA input Channel 3
IN4
Input
LNA input Channel 4
IN5
Input
LNA input Channel 5
IN6
Input
LNA input Channel 6
IN7
Input
LNA input Channel 7
IN8
Input
LNA input Channel 8
INT/EXT
ISET
Input
Internal/ external reference mode select for ADS; internal = high (internal pull-up resistor)
Current bias pin for ADS. Requires 56kΩ to ground.
LVDS bit clock (6x); negative output
LVDS bit clock (6x); positive output
LVDS data output (negative), Channel 1
LVDS data output (positive), Channel 1
LVDS data output (negative), Channel 2
LVDS data output (positive), Channel 2
LVDS data output (negative), Channel 3
K9
N2
N1
R4
P4
R3
P3
R2
Input
LCLKM
LCLKP
OUT1M
OUT1P
OUT2M
OUT2P
OUT3M
Output
Output
Output
Output
Output
Output
Output
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SBOS421D –MARCH 2008–REVISED MARCH 2010
Table 1. TERMINAL FUNCTIONS (continued)
PIN NO.
P2
R1
P1
R6
P6
R7
P7
R8
P8
R9
P9
J9
PIN NAME
OUT3P
OUT4M
OUT4P
OUT5M
OUT5P
OUT6M
OUT6P
OUT7M
OUT7P
OUT8M
OUT8P
REFB
REFT
FUNCTION
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input/Output
Input/Output
Input
DESCRIPTION
LVDS data output (positive), Channel 3
LVDS data output (negative), Channel 4
LVDS data output (positive), Channel 4
LVDS data output (negative), Channel 5
LVDS data output (positive), Channel 5
LVDS data output (negative), Channel 6
LVDS data output (positive), Channel 6
LVDS data output (negative), Channel 7
LVDS data output (positive), Channel 7
LVDS data output (negative), Channel 8
LVDS data output (positive), Channel 8
0.5V Negative reference of ADS. Decoupling to ground. Becomes input in external ref mode.
2.5V Positive reference of ADS. Decoupling to ground. Becomes input in external ref mode.
RESET input for VCA. Connect to the VCA_CS pin (H4).
Connect to RST–pin (H5)
J8
H5
H4
F2
RST
VCA_CS
VB1
Output
Output
Output
Output
Output
Output
Output
Input
Internal bias voltage. Bypass to ground with 2.2mF.
D8
E3
E7
F3
VB2
Internal bias voltage. Bypass to ground with 0.1mF.
VB3
Internal bias voltage. Bypass to ground with 0.1mF.
VB4
Internal bias voltage. Bypass to ground with 0.1mF
VB5
Internal bias voltage. Bypass to ground with 0.1mF.
F8
VB6
Internal bias voltage. Bypass to ground with 0.1mF.
B1
B2
B3
B4
B9
B8
B7
B6
A5
G3
D2
F7
VBL1
Complementary LNA input Channel 1; bypass to ground with 0.1mF.
Complementary LNA input Channel 2; bypass to ground with 0.1mF.
Complementary LNA input Channel 3; bypass to ground with 0.1mF.
Complementary LNA input Channel 4; bypass to ground with 0.1mF.
Complementary LNA input Channel 5; bypass to ground with 0.1mF.
Complementary LNA input Channel 6; bypass to ground with 0.1mF.
Complementary LNA input Channel 7; bypass to ground with 0.1mF.
Complementary LNA input Channel 8; bypass to ground with 0.1mF.
Power-down pin for VCA; low = normal mode, high = power-down mode.
VCA reference voltage. Bypass to ground with 0.1mF.
VBL2
Input
VBL3
Input
VBL4
Input
VBL5
Input
VBL6
Input
VBL7
Input
VBL8
Input
VCA_PD
VCM
Input
Output
Input
VCNTL
VREFH
VREFL
VCA control voltage input
Output
Output
Clamp reference voltage (2.7V). Bypass to ground with 0.1mF.
Clamp reference voltage (2.0V). Bypass to ground with 0.1mF.
G7
B5, H2, H3, K2,
K4, M1, M2,
M8, M9
DNC
Do not connect
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LVDS TIMING DIAGRAM
Sample n
Sample n + 12
ADC
Input(1)
tD(A)
Sample n + 13
Clock
Input
tSAMPLE
12 clocks latency
LCLKM
6X FCLK
LCLKP
OUTP
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
SERIAL DATA
OUTM
FCLKM
1X FCLK
FCLKP
tPROP
(1) Referenced to ADC Input (internal node) for illustration purposes only.
DEFINITION OF SETUP AND HOLD TIMES
LCLKM
LCLKP
OUTM
OUTP
tH1
tSU1 tH2
tSU2
tSU = min(tSU1, tSU2
tH = min(tH1, tH2
)
)
TIMING CHARACTERISTICS(1)
AFE5805
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
ns
tD(A)
ADC aperture delay
1.5
4.5
Aperture delay variation Channel-to-channel within the same device (3s)
±20
400
ps
tJ
Aperture jitter
fS, rms
Time to valid data after coming out of
COMPLETE POWER-DOWN mode
50
ms
ms
ms
Time to valid data after coming out of PARTIAL
POWER-DOWN mode (with clock continuing to
run during power-down)
tWAKE
Wake-up time
2
Time to valid data after stopping and restarting
the input clock
40
12
Clock
cycles
Data latency
(1) Timing parameters are ensured by design and characterization; not production tested.
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SBOS421D –MARCH 2008–REVISED MARCH 2010
LVDS OUTPUT TIMING CHARACTERISTICS(1) (2)
Typical values are at +25°C, minimum and maximum values over specified temperature range of TMIN = 0°C to TMAX = +70°C, sampling
frequency = as specified, CLOAD = 5pF(3), IOUT = 3.5mA, RLOAD = 100Ω(4), and no internal termination, unless otherwise noted.
AFE5805
40MSPS
TYP
50MSPS
TYP
PARAMETER
TEST CONDITIONS(5)
MIN
MAX
MIN
MAX
UNIT
tSU
tH
Data setup time(6)
Data valid(7) to zero-crossing of LCLKP
0.67
0.47
ns
Zero-crossing of LCLKP to data becoming
invalid(7)
Data hold time(6)
0.85
10
0.65
10
ns
ns
ADC input clock rising edge cross-over to
output clock (FCLKP) rising edge cross-over
tPROP
Clock propagation delay
LVDS bit clock duty cycle
14
50
16.6
53
12.5
50
14.1
53.5
Duty cycle of differential clock,
(LCLKP – LCLKM)
45.5
45
Bit clock cycle-to-cycle jitter
250
150
250
150
ps, pp
ps, pp
Frame clock cycle-to-cycle jitter
Rise time is from –100mV to +100mV
Fall time is from +100mV to –100mV
tRISE, tFALL
Data rise time, data fall time
0.09
0.09
0.2
0.2
0.4
0.4
0.09
0.09
0.2
0.2
0.4
0.4
ns
ns
tCLKRISE
,
Output clock rise time, output
clock fall time
Rise time is from –100mV to +100mV
Fall time is from +100mV to –100mV
tCLKFALL
(1) All characteristics are at the maximum rated speed for each speed grade.
(2) Timing parameters are ensured by design and characterization; not production tested.
(3) CLOAD is the effective external single-ended load capacitance between each output pin and ground.
(4) IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.
(5) Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load.
(6) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume
that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as
reduced timing margin.
(7) Data valid refers to a logic high of +100mV and a logic low of –100mV.
LVDS OUTPUT TIMING CHARACTERISTICS(1) (2)
Typical values are at +25°C, minimum and maximum values over specified temperature range of TMIN = 0°C to TMAX = +70°C, sampling
frequency = as specified, CLOAD = 5pF(3), IOUT = 3.5mA, RLOAD = 100Ω(4), and no internal termination, unless otherwise noted.
AFE5805
30MSPS
TYP
20MSPS
TYP
10MSPS
TYP
PARAMETER
TEST CONDITIONS(5)
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Data valid(7) to zero-crossing of
LCLKP
tSU
tH
Data setup time(6)
0.8
1.5
3.7
ns
Zero-crossing of LCLKP to data
becoming invalid(7)
Data hold time(6)
1.2
9.5
1.9
9.5
48
3.9
10
49
ns
ns
ADC input clock rising edge
cross-over to output clock (FCLKP)
rising edge cross-over
tPROP
Clock propagation delay
LVDS bit clock duty cycle
13.5
17.3
52
14.5
17.3
51
14.7
17.1
51
Duty cycle of differential clock,
(LCLKP – LCLKM)
46.5
50
250
150
0.2
0.2
50
250
150
0.2
0.2
50
750
500
0.2
0.2
Bit clock cycle-to-cycle
jitter
ps, pp
ps, pp
ns
Frame clock cycle-to-cycle
jitter
tRISE
tFALL
,
Data rise time, data fall
time
Rise time is from –100mV to +100mV
Fall time is from +100mV to –100mV
0.09
0.09
0.4
0.4
0.09
0.09
0.4
0.4
0.09
0.09
0.4
0.4
tCLKRISE
tCLKFALL
,
Output clock rise time,
output clock fall time
Rise time is from –100mV to +100mV
Fall time is from +100mV to –100mV
ns
(1) All characteristics are at the speeds other than the maximum rated speed for each speed grade.
(2) Timing parameters are ensured by design and characterization; not production tested.
(3) CLOAD is the effective external single-ended load capacitance between each output pin and ground.
(4) IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.
(5) Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load.
(6) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume
that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as
reduced timing margin.
(7) Data valid refers to a logic high of +100mV and a logic low of –100mV.
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TYPICAL CHARACTERISTICS
AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1mF,
VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode,
ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
GAIN vs VCNTL
GAIN vs VCNTL vs TEMPERATURE
50
44
38
32
26
20
14
8
55
50
45
40
35
30
25
20
15
10
5
27dB
30dB
+85°C
20dB
+50°C
-40°C
2
25dB
-4
-10
+25°C
0
0
0.2
0.4
0.6
VCNTL (V)
0.8
1.0
1.2
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
VCNTL (V)
Figure 1.
Figure 2.
GAIN MATCH AT VCNTL = 0.1V
GAIN MATCH AT VCNTL = 0.6V
3000
2500
2000
1500
1000
500
3000
2500
2000
1500
1000
500
Channel-to-Channel
Channel-to-Channel
0
0
Gain (dB)
Gain (dB)
Figure 3.
Figure 4.
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SBOS421D –MARCH 2008–REVISED MARCH 2010
TYPICAL CHARACTERISTICS (continued)
AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1mF,
VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode,
ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
GAIN MATCH AT VCNTL = 1.0V
OUTPUT OFFSET
3500
3000
2500
2000
1500
1000
500
4000
3500
3000
2500
2000
1500
1000
500
Channel-to-Channel
0
0
Code
Gain (dB)
Figure 5.
SNR AND SINAD vs VCNTL
Figure 6.
INPUT-REFERRED NOISE vs PGA
67
66
65
64
63
62
61
60
59
58
57
56
55
1.2
1.0
0.8
0.6
0.4
0.2
0
RS = 0W
PGA = 20dB
VCNTL = 1.2V
Input = -45dBm
Frequency = 5MHz
PGA = 30dB
SNR
SINAD
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
VCNTL (V)
25dB
27dB
30dB
20dB
Gain Setting (PGA)
Figure 7.
Figure 8.
INPUT-REFERRED NOISE vs VCNTL
INPUT-REFERRED NOISE vs VCNTL
130
120
110
100
90
130
120
110
100
90
Frequency = 2MHz
Frequency = 5MHz
80
80
70
70
PGA = 20dB
60
60
PGA = 20dB
50
50
40
40
30
30
20
20
10
10
PGA = 30dB
PGA = 30dB
0
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
VCNTL (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
VCNTL (V)
Figure 9.
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1mF,
VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode,
ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
OUTPUT-REFERRED NOISE vs VCNTL
OUTPUT-REFERRED NOISE vs VCNTL
300
250
200
150
100
50
300
250
200
150
100
50
Frequency = 2MHz
Frequency = 5MHz
PGA = 30dB
PGA = 30dB
PGA = 20dB
PGA = 20dB
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
VCNTL (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
VCNTL (V)
Figure 11.
Figure 12.
OUTPUT-REFERRED NOISE vs FREQUENCY vs RS
INPUT-REFERRED NOISE vs FREQUENCY vs RS
1400
1300
7.0
6.5
6.0
5.5
5.0
RS = 1kW
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
RS = 400W
RS = 1kW
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
RS = 400W
RS = 200W
RS = 50W
RS = 200W
VCNTL = 1.2V
VCNTL = 1.2V
RS = 50W
1
10
1
10
Frequency (MHz)
Frequency (MHz)
Figure 13.
Figure 14.
CURRENT NOISE vs FREQUENCY OVER RSOURCE
NOISE FIGURE vs FREQUENCY vs RS
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.0
VCNTL = 1.2V
3.8
RS = 1kW
RS = 1kW
3.6
3.4
RS = 200W
RS = 50W
3.2
3.0
RS = 400W
2.8
2.6
2.4
2.2
2.0
RS = 400W
PGA = 30dB
VCNTL = 1.2V
RS = 200W
1
10
20
10
1
Frequency (MHz)
Frequency (MHz)
Figure 15.
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1mF,
VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode,
ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
CW INPUT-REFERRED NOISE vs FREQUENCY
CW ACCURACY
4000
3500
3000
2500
2000
1500
1000
500
1.30
1.28
1.26
1.24
1.22
1.20
1.18
1.16
1.14
1.12
1.10
0
100k
1M
10M
20M
Frequency (Hz)
Transconductance (mA/V)
Figure 17.
2ND HARMONIC vs VCNTL vs FREQUENCY
Figure 18.
3RD HARMONIC vs VCNTL vs FREQUENCY
-50
-55
-60
-65
-70
-75
-80
-85
-55
-60
-65
-70
-75
-80
-85
PGA = 20dB
Output = -6dBFS
PGA = 20dB
Output = -6dBFS
5MHz
10MHz
2MHz
10MHz
2MHz
5MHz
0.6
0.7
0.8
0.9
VCNTL (V)
1.0
1.1
1.2
0.6
0.7
0.8
0.9
1.0
1.1
1.2
VCNTL (V)
Figure 19.
2ND HARMONIC vs VCNTL vs FREQUENCY
Figure 20.
3RD HARMONIC vs VCNTL vs FREQUENCY
-50
-55
-60
-65
-70
-75
-80
-40
-45
-50
-55
-60
-65
-70
PGA = 30dB
Output = -1dBFS
10MHz
5MHz
10MHz
2MHz
2MHz
5MHz
PGA = 30dB
Output = -1dBFS
0.6
0.7
0.8
0.9
VCNTL (V)
1.0
1.1
1.2
0.6
0.7
0.8
0.9
1.0
1.1
1.2
VCNTL (V)
Figure 21.
Figure 22.
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TYPICAL CHARACTERISTICS (continued)
AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1mF,
VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode,
ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
2ND HARMONIC vs VCNTL vs OUTPUT LEVEL
3RD HARMONIC vs VCNTL vs OUTPUT LEVEL
-30
-30
-40
-50
-60
-70
-80
PGA = 30dB
Frequency = 5MHz
PGA = 30dB
Frequency = 5MHz
VCNTL = 1V
-40
-50
-60
-70
-80
VCNTL = 0.4V
VCNTL = 1V
VCNTL = 0.4V
VCNTL = 0.7V
VCNTL = 0.7V
-40
0.6
0.6
-30
-20
-10
0
-40
0.6
0.6
-30
-20
-10
0
Output Level (dBFS)
Output Level (dBFS)
Figure 23.
Figure 24.
CROSSTALK vs VCNTL
CROSSTALK vs VCNTL
-50
-55
-60
-65
-70
-75
-80
-85
-90
-50
-55
-60
-65
-70
-75
-80
-85
-90
Adjacent Channels
PGA = 20dB
-1dBFS
Adjacent Channels
PGA = 25dB
-1dBFS
10MHz
10MHz
5MHz
2MHz
2MHz
5MHz
0.7
0.8
0.9
1.0
1.1
1.2
0.7
0.8
0.9
1.0
1.1
1.2
VCNTL (V)
VCNTL (V)
Figure 25.
CROSSTALK vs VCNTL
Figure 26.
CROSSTALK vs VCNTL
-50
-55
-60
-65
-70
-75
-80
-85
-90
-50
-55
-60
-65
-70
-75
-80
-85
-90
Adjacent Channels
PGA = 27dB
-1dBFS
Adjacent Channels
PGA = 30dB
-1dBFS
10MHz
10MHz
5MHz
5MHz
2MHz
2MHz
0.7
0.8
0.9
VCNTL (V)
1.0
1.1
1.2
0.7
0.8
0.9
1.0
1.1
1.2
VCNTL (V)
Figure 27.
Figure 28.
18
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TYPICAL CHARACTERISTICS (continued)
AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1mF,
VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode,
ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
10MHz LOW-PASS FILTER RESPONSE
15MHz LOW-PASS FILTER RESPONSE
0
-2
0
-2
-4
-4
-6
-6
-8
-8
-10
-12
-14
-16
-18
-20
-10
-12
-14
-16
-18
-20
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
Frequency (MHz)
Frequency (MHz)
Figure 29.
Figure 30.
INTERMODULATION DISTORTION
(1.99MHz and 2.01MHz)
INTERMODULATION DISTORTION
(4.99MHz and 5.01MHz)
0
-20
0
-20
PGA = 30dB
VCNTL = 1.0V
PGA = 30dB
VCNTL = 1.0V
-6
-6
IMD3 = 54.2dB
IMD3 = 58.5dB
-32
-32
-40
-40
-60
-60
-80
-80
-86.2
-90.5
-100
-100
-120
-120
1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20
Frequency (MHz)
4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20
Frequency (MHz)
Figure 31.
Figure 32.
INPUT IMPEDANCE vs FREQUENCY
LNA OVERLOAD
12k
10k
8k
6k
4k
2k
0
100
80
1.0
60
0.5
0
40
20
0
-20
-40
Magnitude (ZIN
)
Phase
-0.5
-1.0
-60
VIN = 1VPP (+12dBFS)
PGA = 20dB
VCNTL = 0.54V
-80
-100
100k
1M
10M
100M
0
10 20 30 40 50 60 70 80 90 100 110 120
Sample Points
Frequency (Hz)
Figure 33.
Figure 34.
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TYPICAL CHARACTERISTICS (continued)
AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1mF,
VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode,
ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
FULL CHANNEL OVERLOAD
OVERLOAD RECOVERY
1.0
0.5
1.0
0.5
0
0
-0.5
-1.0
-0.5
-1.0
VIN = 0.5VPP (+6dBFS)
PGA = 30dB
VCNTL = 1.0V
PGA = 30dB
VCNTL = 1.0V
VIN = 250mVPP, 0.25mVPP
0
10 20 30 40 50 60 70 80 90 100 110 120
Sample Points
0
5
10 15
Time (ms)
Figure 35.
Figure 36.
VCNTL RESPONSE TIME
POWER-UP/POWER-DOWN RESPONSE TIME
1.0
0.5
1.0
PD
VCNTL
0.5
0
0
-0.5
-1.0
-0.5
-1.0
PGA = 30dB
VCNTL = 0V to 1.2V
PGA = 30dB
VCNTL = 0.4V
0
5
10
15
0
5
10
15
20
25
30
Time (ms)
Time (ms)
Figure 37.
Figure 38.
AVDD1 AND LVDD POWER-SUPPLY CURRENTS
vs CLOCK FREQUENCY
POWER DISSIPATION vs TEMPERATURE
170
995
990
985
980
975
970
965
960
955
950
945
TGC Mode
Zero Input on All Channels
150
130
110
90
IAVDD1
70
ILVDD
50
30
5
15
25
35
45
55
-40
0
25
50
70
85
Clock Frequency (MSPS)
Temperature (°C)
Figure 39.
Figure 40.
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SERIAL INTERFACE
The AFE5805 has a set of internal registers that can be accessed through the serial interface formed by pins CS
(chip select, active low), SCLK (serial interface clock), and SDATA (serial interface data). When CS is low, the
following actions occur:
•
•
•
Serial shift of bits into the device is enabled
SDATA (serial data) is latched at every rising edge of SCLK
SDATA is loaded into the register at every 24th SCLK rising edge
If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of
24-bit words within a single active CS pulse. The first eight bits form the register address and the remaining 16
bits form the register data. The interface can work with SCLK frequencies from 20MHz down to very low speeds
(a few hertz) and also with a non-50% SCLK duty cycle.
Register Initialization
After power-up, the internal registers must be initialized to the respective default values. Initialization can be
done in one of two ways:
1. Through a hardware reset, by applying a low-going pulse on the ADS_RESET pin; or
2. Through a software reset; using the serial interface, set the S_RST bit high. Setting this bit initializes the
internal registers to the respective default values and then self-resets the bit low. In this case, the
ADS_RESET pin stays high (inactive).
It is recommended to program the following registers after the initialization stage. The power-supply ripple and
clock jitter effects can be minimized.
ADDRESS
DATA
0010
0140
0001
0020
0080
0000
01
D1
DA
E1
02
01
Serial Port Interface (SPI) Information
(connect externally)
VCA_CS
[H4]
RST
[H5]
ADS_RESET
[H9]
VCA_SCLK
VCA_SDATA
SDATA
CS
[H8]
[H7]
SCLK
[H6]
ADS_CS
ADS_SCLK
ADS_SDATA
ADS_RESET
Tie to:
+3.3V (AVDD1)
[L9]
EN_SM
AFE5805
Figure 41. Typical Connection Diagram for the SPI Control Lines
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SERIAL INTERFACE TIMING
Start Sequence
End Sequence
CS
t6
t1
t2
t7
Data latched on rising edge of SCLK
SCLK
t3
D15 D14 D13 D12 D11 D10 D9
SDATA
A7 A6 A5 A4 A3 A2 A1 A0
D8 D7 D6 D5 D4 D3 D2 D1 D0
t4
t5
AFE5805
PARAMETER
DESCRIPTION
SCLK period
MIN
TYP
MAX
UNIT
ns
t1
t2
t3
t4
t5
t6
t7
50
20
20
5
SCLK high time
SCLK low time
Data setup time
Data hold time
ns
ns
ns
5
ns
CS fall to SCLK rise
Time between last SCLK rising edge to CS rising edge
8
ns
8
ns
Internally-Generated VCA Control Signals
VCA_SCLK
VCA_SDATA
D0
D39
VCA_SCLK and VCA_SDATA signals are generated if:
•
•
Registers with address 16, 17, or 18 (Hex) are written into, and
EN_SM pin is HIGH
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SERIAL REGISTER MAP
Table 2. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE(1) (2) (3) (4)
ADDRESS
IN HEX
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6
D5
D4 D3 D2 D1 D0
NAME
DESCRIPTION
DEFAULT
00
03
X
S_RST
Self-clearing software RESET.
Inactive
RES_
VCA
0
X
X
0
X
X
0
X
X
0
X
X
0
X
X
0
X
X
0
X
X
0
X
X
0
X
X
X
0
X
X
X
0
X
X
X
0
X
X
X
X
0
X
X
X
X
0
1
0
1
VCA_SDATA
<0:15>
D5 = 1
(TGC mode)
16
17
18
X
X
X
See Table 4 information
See Table 4 information
See Table 4 information
VCA_SDATA
<16:31>
X
X
X
X
X
X
VCA_DATA
<32:39>
Channel-specific ADC
power-down mode.
PDN_CH<1:4>
PDN_CH<8:5>
PDN_PARTIAL
PDN_COMPLETE
PDN_PIN_CFG
Inactive
Inactive
Inactive
Inactive
Channel-specific ADC
power-down mode.
x
X
X
X
X
Partial power-down mode (fast
recovery from power-down).
0F
X
Register mode for complete
power-down (slower recovery).
0
X
0
Configures the PD pin for
partial power-down mode.
Complete
power-down
X
LVDS current drive
X
X
X
ILVDS_LCLK<2:0> programmability for LCLKM
and LCLKP pins.
3.5mA drive
3.5mA drive
LVDS current drive
ILVDS_FRAME
11
X
X
X
programmability for FCLKM
<2:0>
and FCLKP pins.
LVDS current drive
X
X
X
ILVDS_DAT<2:0> programmability for OUTM and 3.5mA drive
OUTP pins.
Enables internal termination
for LVDS buffers.
Termination
disabled
X
1
1
1
EN_LVDS_TERM
TERM_LCLK<2:0>
Programmable termination for
LCLKM and LCLKP buffers.
Termination
disabled
X
X
X
X
X
X
12
TERM_FRAME
<2:0>
Programmable termination for
FCLKM and FCLKP buffers.
Termination
disabled
X
X
X
Programmable termination for
OUTM and OUTP buffers.
Termination
disabled
X
X
X
TERM_DAT<2:0>
LFNS_CH<1:4>
Channel-specific,
low-frequency noise
suppression mode enable.
X
Inactive
14
Channel-specific,
x
X
X
X
0
X
0
X
0
0
LFNS_CH<8:5>
EN_RAMP
low-frequency noise
suppression mode enable.
Inactive
Inactive
Inactive
Enables a repeating full-scale
ramp pattern on the outputs.
Enables the mode wherein the
output toggles between two
defined codes.
DUALCUSTOM_
PAT
X
Enables the mode wherein the
output is a constant specified
code.
SINGLE_CUSTOM
_PAT
0
0
X
Inactive
25
2MSBs for a single custom
pattern (and for the first code
of the dual custom pattern).
<11> is the MSB.
BITS_CUSTOM1
<11:10>
X
X
Inactive
Inactive
Inactive
BITS_CUSTOM2
<11:10>
2MSBs for the second code of
the dual custom pattern.
X
X
10 lower bits for the single
custom pattern (and for the
first code of the dual custom
pattern). <0> is the LSB.
BITS_CUSTOM1
<9:0>
26
27
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
10 lower bits for the second
code of the dual custom
pattern.
BITS_CUSTOM2
<9:0>
Inactive
(1) The unused bits in each register (identified as blank table cells) must be programmed as '0'.
(2) X = Register bit referenced by the corresponding name and description (default setting is listed above).
(3) Bits marked as '0' should be forced to 0, and bits marked as '1' should be forced to 1 when the particular register is programmed.
(4) Multiple functions in a register should be programmed in a single write operation.
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Table 2. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE (1) (2) (3) (4) (continued)
ADDRESS
IN HEX
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6
D5
D4 D3 D2 D1 D0
NAME
DESCRIPTION
DEFAULT
0dB gain
0dB gain
0dB gain
0dB gain
0dB gain
0dB gain
0dB gain
0dB gain
X
X
X
X
GAIN_CH4<3:0>
GAIN_CH3<3:0>
GAIN_CH2<3:0>
GAIN_CH1<3:0>
GAIN_CH5<3:0>
GAIN_CH6<3:0>
GAIN_CH7<3:0>
GAIN_CH8<3:0>
Programmable gain channel 4.
Programmable gain channel 3.
Programmable gain channel 2.
Programmable gain channel 1.
Programmable gain channel 5.
Programmable gain channel 6.
Programmable gain channel 7.
Programmable gain channel 8.
X
X
X
X
2A
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2B
X
X
X
X
X
X
X
X
X
X
X
Single-
ended clock
1
1
1
1
DIFF_CLK
EN_DCC
Differential clock mode.
Enables the duty-cycle
correction circuit.
Disabled
External
reference
drives REFT
and REFB
42
45
Drives the external reference
mode through the VCM pin.
1
1
1
1
EXT_REF_VCM
Controls the phase of LCLK
output relative to data.
X
X
PHASE_DDR<1:0>
90 degrees
0
X
0
PAT_DESKEW
PAT_SYNC
Enables deskew pattern mode.
Enables sync pattern mode.
Inactive
Inactive
X
Binary two's complement
format for ADC output.
Straight
offset binary
1
1
1
1
X
BTC_MODE
MSB_FIRST
Serialized ADC output comes
out MSB-first.
LSB-first
output
X
Enables SDR output mode
(LCLK becomes a 12x input
clock).
DDR output
mode
1
1
1
1
X
1
EN_SDR
46
Controls whether the LCLK
rising or falling edge comes in
the middle of the data window
when operating in SDR output
mode.
Rising edge
of LCLK in
middle of
1
FALL_SDR
data window
SUMMARY OF FEATURES
POWER IMPACT (Relative to Default)
AT fS = 50MSPS
FEATURES
DEFAULT
SELECTION
ANALOG FEATURES
Internal or external reference
(driven on the REFT and REFB pins)
N/A
Pin
Internal reference mode takes approximately 20mW more power on AVDD1
External reference driven on the CM pin
Duty cycle correction circuit
Off
Off
Register 42
Register 42
Approximately 8mW less power on AVDD1
Approximately 7mW more power on AVDD1
With zero input to the ADC, low-frequency noise suppression causes digital switching
at fS/2, thereby increasing LVDD power by approximately 5.5mW/channel
Low-frequency noise suppression
Off
Register 14
Register 42
Single-ended or differential clock
Power-down mode
Single-ended
Off
Differential clock mode takes approximately 7mW more power on AVDD1
Pin and register 0F
Refer to the Power-Down Modes section in the Electrical Characteristics table
DIGITAL FEATURES
Programmable digital gain (0dB to 12dB)
Straight offset or BTC output
LVDS OUTPUT PHYSICAL LAYER
LVDS internal termination
LVDS current programmability
LVDS OUTPUT TIMING
0dB
Registers 2A and 2B
Register 46
No difference
No difference
Straight offset
Off
Register 12
Register 11
Approximately 7mW more power on AVDD1
3.5mA
As per LVDS clock and data buffer current setting
LSB- or MSB-first output
LSB-first
DDR
Register 46
Register 46
Register 42
No difference
SDR mode takes approximately 2mW more power on LVDD (at fS = 30MSPS)
No difference
DDR or SDR output
LCLK phase relative to data output
Refer to Figure 43
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DESCRIPTION OF SERIAL REGISTERS
SOFTWARE RESET
ADDRESS
IN HEX
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NAME
00
X
S_RST
Software reset is applied when the RST bit is set to '1'; setting this bit resets all internal registers and self-clears
to '0'.
Table 3. VCA Register Information
ADDRESS
IN HEX
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RES_V
CA
03
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VCA
D15
VCA
D14
VCA
D13
VCA
D12
VCA
D11
VCA
D10
VCA
D9
VCA
D8
VCA
D7
VCA
D6
VCA
D5
VCA
D4
VCA
D3
VCA
D2
1(1)
D1
1(1)
D0
16
17
18
VCA
D31
VCA
D30
VCA
D29
VCA
D28
VCA
D27
VCA
D26
VCA
D25
VCA
D24
VCA
D23
VCA
D22
VCA
D21
VCA
D20
VCA
D19
VCA
D18
VCA
D17
VCA
D16
VCA
D39
VCA
D38
VCA
D37
VCA
D36
VCA
D35
VCA
D34
VCA
D33
VCA
D32
(1) Bits D0 and D1 of register 16 are forced to '1'.
space
•
•
VCA_SCLK and VCA_SDATA become active only when one of the registers 16, 17, or 18 of the AFE5805
are written into.
The contents of all three registers (total 40 bits) are written on VCA_SDATA even if only one of the above
registers is written into. This condition is only valid if the content of the register has changed because of the
most recent write. Writing contents that are the same as existing contents does not trigger activity on
VCA_SDATA.
•
•
For example, if register 17 is written into after a RESET is applied, then the contents of register 17 as well as
the default values of the bits in registers 16 and 18 are written into VCA_SDATA.
If register 16 is then written to, then the new contents of register 16, the previously written contents of register
17, and the default contents of register 18 are written into VCA_SDATA. Note that regardless of what is
written into D0 and D1 of register 16, the respective outputs on VCA_SDATA are always ‘1’.
•
•
•
Alternatively, all three registers (16, 17 and 18) can also be written within one write cycle of the serial
interface. In that case, there would be 48 consecutive SCLK edges within the same CS active window.
VCA_SCLK is generated using an oscillator (running at approximately 6MHz) inside the AFE5805, but the
oscillator is gated so that it is active only during the write operation of the 40 VCA bits.
To ensure the SDATA transfer reliability, a ≥ 1ms gap is recommended between programming two VCA
registers consecutively.
VCA Reset
•
•
VCA_CS should be permanently connected to the RST-input.
When VCA_CS goes high (either because of an active low pulse on ADS_RESET for more than 10ns or as a
result or setting bit RES_VCA), the following functions are performed inside the AFE5805:
–
–
Bits D0 and D1 of register 16 are forced to ‘1’
All other bits in registers 16, 17 and 18 are RESET to the respective default values (‘0’ for all bits except
D5 of register 16 which is set to a default of ‘1’).
–
No activity on signals VCA_SCLK and VCA_SDATA.
•
If bit RES_VCA has been set to ‘1’, then the state machine is in the RESET state until RES_VCA is set to ‘0’.
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INPUT REGISTER BIT MAPS
Table 4. VCA Register Map
BYTE 1
D0:D7
BYTE 2
D12:D15
BYTE 3
BYTE 4
D24:D27 D28:D31
CH5 CH6
BYTE 5
D8:D11
CH1
D16:D19
CH3
D20:D23
CH4
D32:D35
CH7
D36:D39
CH8
Control
CH2
Table 5. Byte 1—Control Byte Register Map
BIT NUMBER
BIT NAME
1
DESCRIPTION
Start bit; this bit is permanently set high = 1
D0 (LSB)
D1
WR
Write bit; this bit is permanently set high = 1
1= Power-down mode enabled.
D2
PWR
BW
D3
Low-pass filter bandwidth setting (see Table 10)
Clamp level setting (see Table 10)
D4
CL
D5
Mode
PG0
PG1
1 = TGC mode (default) , 0 = CW Doppler mode
LSB of PGA gain control (see Table 11)
MSB of PGA gain control
D6
D7 (MSB)
Table 6. Byte 2—First Data Byte
BIT NUMBER
D8 (LSB)
D9
BIT NAME
DB1:1
DB1:2
DB1:3
DB1:4
DB2:1
DB2:2
DB2:3
DB2:4
DESCRIPTION
Channel 1, LSB of matrix control
Channel 1, matrix control
D10
Channel 1, matrix control
D11
Channel 1, MSB of matrix control
Channel 2, LSB of matrix control
Channel 2, matrix control
D12
D13
D14
Channel 2, matrix control
D15 (MSB)
Channel 2, MSB of matrix control
Table 7. Byte 3—Second Data Byte
BIT NUMBER
D16 (LSB)
D17
BIT NAME
DB3:1
DB3:2
DB3:3
DB3:4
DB4:1
DB4:2
DB4:3
DB4:4
DESCRIPTION
Channel 3, LSB of matrix control
Channel 3, matrix control
D18
Channel 3, matrix control
D19
Channel 3, MSB of matrix control
Channel 4, LSB of matrix control
Channel 4, matrix control
D20
D21
D22
Channel 4, matrix control
D23 (MSB)
Channel 4, MSB of matrix control
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Table 8. Byte 4—Third Data Byte
BIT NUMBER
BIT NAME
DB5:1
DB5:2
DB5:3
DB5:4
DB6:1
DB6:2
DB6:3
DB6:4
DESCRIPTION
D24 (LSB)
D25
Channel 5, LSB of matrix control
Channel 5, matrix control
D26
Channel 5, matrix control
D27
Channel 5, MSB of matrix control
Channel 6, LSB of matrix control
Channel 6, matrix control
D28
D29
D30
Channel 6, matrix control
D31 (MSB)
Channel 6, MSB of matrix control
Table 9. Byte 5—Fourth Data Byte
BIT NUMBER
D32 (LSB)
D33
BIT NAME
DB7:1
DB7:2
DB7:3
DB7:4
DB8:1
DB8:2
DB8:3
DB8:4
DESCRIPTION
Channel 7, LSB of matrix control
Channel 7, matrix control
D34
Channel 7, matrix control
D35
Channel 7, MSB of matrix control
Channel 8, LSB of matrix control
Channel 8, matrix control
D36
D37
D38
Channel 8, matrix control
D39 (MSB)
Channel 8, MSB of matrix control
Table 10. Clamp Level and LPF Bandwidth Setting
FUNCTION
BW
BW
CL
D3 = 0
Bandwidth set to 15MHz (default)
D3 = 1
D4 = 0
D4 = 1
Bandwidth set to 10MHz
Clamps the output signal at approximately –1.4dB below the full-scale of 2VPP
.
CL
Clamp transparent (disabled)
Table 11. PGA Gain Setting
PG1 (D7)
PG0 (D6)
FUNCTION
Sets PGA gain to 20dB (default)
Sets PGA gain to 25dB
0
0
1
1
0
1
0
1
Sets PGA gain to 27dB
Sets PGA gain to 30dB
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Table 12. CW Switch Matrix Control for Each Channel
DBn:4 (MSB)
DBn:3
DBn:2
DBn:1 (LSB)
LNA INPUT CHANNEL n DIRECTED TO
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output CW0
Output CW1
Output CW2
Output CW3
Output CW4
Output CW5
Output CW6
Output CW7
Output CW8
Output CW9
Connected to AVDD_5V
Connected to AVDD_5V
Connected to AVDD_5V
Connected to AVDD_5V
Connected to AVDD_5V
Connected to AVDD_5V
V/I
Converter
Channel 1
Input
CW0
CW1
CW2
CW3
VCA_SDATA
Decode
Logic
CW4
VCA_SCLK
CW5
CW6
CW7
CW8
CW9
AVDD_5V
(To Other Channels)
Figure 42. Basic CW Cross-Point Switch Matrix Configuration
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POWER-DOWN MODES
ADDRESS
IN HEX
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NAME
X
X
X
X
PDN_CH<1:4>
PDN_CH<8:5>
PDN_PARTIAL
PDN_COMPLETE
PDN_PIN_CFG
X
X
X
X
0F
X
0
X
0
X
Each of the eight ADC channels within the AFE5805 can be individually powered down. PDN_CH<N> controls
the power-down mode for the ADC channel <N>.
In addition to channel-specific power-down, the AFE5805 also has two global power-down modes: partial
power-down mode and complete power-down mode.
In addition to programming the device for either of these two power-down modes (through either the
PDN_PARTIAL or PDN_COMPLETE bits, respectively), the ADS_PD pin itself can be configured as either a
partial power-down pin or a complete power-down pin control. For example, if PDN_PIN_CFG = 0 (default), when
the ADS_PD pin is high, the device enters complete power-down mode. However, if PDN_PIN_CFG = 1, when
the ADS_PD pin is high, the device enters partial power-down mode.
The partial power-down mode function allows the AFE5805 to be rapidly placed in a low-power state. In this
mode, most amplifiers in the signal path are powered down, while the internal references remain active. This
configuration ensures that the external bypass capacitors retain the respective charges, minimizing the wake-up
response time. The wake-up response is typically less than 50ms, provided that the clock has been running for at
least 50ms before normal operating mode resumes. The power-down time is instantaneous (less than 1.0ms).
In partial power-down mode, the part typically dissipates only 233mW, representing a 76% power reduction
compared to the normal operating mode. This function is controlled through the ADS_PD and VCA_PD pins,
which are designed to interface with 3.3V low-voltage logic. If separate control of the two PD pins is not desired,
then both can be tied together. In this case, the ADS_PD pin should be configured to operate as a partial
power-down mode pin [see further information (PDN_PIN_CFG) above].
For normal operation the PD pins should be tied to a logic low (0); a high (1) places the AFE5805 into partial
power-down mode.
To achieve the lowest power dissipation of only 64mW, the AFE5805 can be placed in complete power-down
mode. This mode is controlled through the serial interface by setting Register 16 (bit D2) and Register 0F (bit
D9:D10). In complete power-down mode, all circuits (including references) within the AFE5805 are
powered-down, and the bypass capacitors then discharge. Consequently, the wake-up time from complete
power-down mode depends largely on the time needed to recharge the bypass capacitors. Another factor that
affects the wake-up time is the elapsed time that the AFE5805 spends in shutdown mode.
LVDS DRIVE PROGRAMMABILITY
ADDRESS
IN HEX
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NAME
X
X
X
ILVDS_LCLK<2:0>
ILVDS_FRAME<2:0>
ILVDS_DAT<2:0>
11
X
X
X
X
X
X
The LVDS drive strength of the bit clock (LCLKP or LCLKM) and the frame clock (FCLKP or FCLKM) can be
individually programmed. The LVDS drive strengths of all the data outputs OUTP and OUTM can also be
programmed to the same value.
All three drive strengths (bit clock, frame clock, and data) are programmed using sets of three bits. Table 13
details an example of how the drive strength of the bit clock is programmed (the method is similar for the frame
clock and data drive strengths).
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Table 13. Bit Clock Drive Strength(1)
ILVDS_LCLK<2>
ILVDS_LCLK<1>
ILVDS_LCLK<0>
LVDS DRIVE STRENGTH FOR LCLKP AND LCLKM
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3.5mA (default)
2.5mA
1.5mA
0.5mA
7.5mA
6.5mA
5.5mA
4.5mA
(1) Current settings lower than 1.5mA are not recommended.
LVDS INTERNAL TERMINATION PROGRAMMING
ADDRESS
IN HEX
D15
D14
X
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NAME
EN_LVDS_TERM
TERM_LCLK<2:0>
TERM_FRAME<2:0>
TERM_DAT<2:0>
1
X
X
X
12
1
X
X
X
1
X
X
X
The LVDS buffers have high-impedance current sources that drive the outputs. When driving traces with
characteristic impedances that are not perfectly matched with the termination impedance on the receiver side,
there may be reflections back to the LVDS output pins of the AFE5805 that cause degraded signal integrity. By
enabling an internal termination (between the positive and negative outputs) for the LVDS buffers, the signal
integrity can be significantly improved in such scenarios. To set the internal termination mode, the
EN_LVDS_TERM bit should be set to '1'. Once this bit is set, the internal termination values for the bit clock,
frame clock, and data buffers can be independently programmed using sets of three bits. Table 14 shows an
example of how the internal termination of the LVDS buffer driving the bit clock is programmed (the method is
similar for the frame clock and data drive strengths). These termination values are only typical values and can
vary by several percent across temperature and from device to device.
Table 14. Bit Clock Internal Termination
INTERNAL TERMINATION BETWEEN
TERM_LCLK<2>
TERM_LCLK<1>
TERM_LCLK<0>
LCLKP AND LCLKM IN Ω
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None
260
150
94
125
80
66
55
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LOW-FREQUENCY NOISE SUPPRESSION MODE
ADDRESS
IN HEX
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NAME
X
X
X
X
LFNS_CH<1:4>
LFNS_CH<8:5>
14
X
X
X
X
The low-frequency noise suppression mode is especially useful in applications where good noise performance is
desired in the frequency band of 0MHz to 1MHz (around dc). Setting this mode shifts the low-frequency noise of
the AFE5805 to approximately fS/2, thereby moving the noise floor around dc to a much lower value.
LFNS_CH<8:1> enables this mode individually for each channel.
LVDS TEST PATTERNS
ADDRESS
IN HEX
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
X
D5
0
D4
0
D3
D2
D1
D0
NAME
EN_RAMP
0
X
0
DUALCUSTOM_PAT
SINGLE_CUSTOM_PAT
BITS_CUSTOM1<11:10>
BITS_CUSTOM2<11:10>
BITS_CUSTOM1<9:0>
BITS_CUSTOM2<9:0>
PAT_DESKEW
25
0
0
X
X
X
X
X
26
27
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
0
45
X
PAT_SYNC
The AFE5805 can output a variety of test patterns on the LVDS outputs. These test patterns replace the normal
ADC data output. Setting EN_RAMP to '1' causes all the channels to output a repeating full-scale ramp pattern.
The ramp increments from zero code to full-scale code in steps of 1LSB every clock cycle. After hitting the
full-scale code, it returns back to zero code and ramps again.
The device can also be programmed to output a constant code by setting SINGLE_CUSTOM_PAT to '1', and
programming the desired code in BITS_CUSTOM1<11:0>. In this mode, BITS_CUSTOM<11:0> take the place of
the 12-bit ADC data at the output, and are controlled by LSB-first and MSB-first modes in the same way as
normal ADC data are.
The device may also be made to toggle between two consecutive codes by programming DUAL_CUSTOM_PAT
to '1'. The two codes are represented by the contents of BITS_CUSTOM1<11:0> and BITS_CUSTOM2<11:0>.
In addition to custom patterns, the device may also be made to output two preset patterns:
1. Deskew patten: Set using PAT_DESKEW, this mode replaces the 12-bit ADC output D<11:0> with the
010101010101 word.
2. Sync pattern: Set using PAT_SYNC, the normal ADC word is replaced by a fixed 111111000000 word.
Note that only one of the above patterns can be active at any given instant.
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PROGRAMMABLE GAIN
ADDRESS
IN HEX
D15
D14
D13
D12
D11
X
D10
X
D9
X
D8
X
D7
D6
D5
D4
D3
D2
D1
D0
NAME
X
X
X
X
GAIN_CH4<3:0>
GAIN_CH3<3:0>
GAIN_CH2<3:0>
GAIN_CH1<3:0>
GAIN_CH5<3:0>
GAIN_CH6<3:0>
GAIN_CH7<3:0>
GAIN_CH8<3:0>
X
X
X
X
2A
X
X
X
X
X
X
X
X
X
X
X
X
2B
X
X
X
X
X
X
X
X
The AFE5805, through its registers, allows for a digital gain to be programmed for each channel. This
programmable gain can be set to achieve the full-scale output code even with a lower analog input swing. The
programmable gain not only fills the output code range of the ADC, but also enhances the SNR of the device by
using quantization information from some extra internal bits. The programmable gain for each channel can be
individually set using a set of four bits, indicated as GAIN_CHN<3:0> for Channel N. The gain setting is coded in
binary from 0dB to 12dB, as shown in Table 15.
Table 15. Gain Setting for Channel 1
GAIN_CH1<3>
GAIN_CH1<2>
GAIN_CH1<1>
GAIN_CH1<0>
CHANNEL 1 GAIN SETTING
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0dB
1dB
2dB
3dB
4dB
5dB
6dB
7dB
8dB
9dB
10dB
11dB
12dB
Do not use
Do not use
Do not use
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CLOCK, REFERENCE, AND DATA OUTPUT MODES
ADDRESS
IN HEX
D15
1
D14
D13
D12
D11
D10
D9
D8
D7
1
D6
D5
D4
D3
X
D2
D1
D0
NAME
DIFF_CLK
X
1
1
X
EN_DCC
42
1
1
EXT_REF_VCM
PHASE_DDR<1:0>
BTC_MODE
MSB_FIRST
EN_SDR
1
1
X
X
1
1
1
1
1
X
1
X
46
1
X
1
1
1
FALL_SDR
INPUT CLOCK
The AFE5805 is configured by default to operate with a single-ended input clock; CLKP is driven by a CMOS
clock and CLKM is tied to '0'. However, by programming DIFF_CLK to '1', the device can be made to work with a
differential input clock on CLKP and CLKM. Operating with a low-jitter differential clock generally leads to
improved SNR performance.
In cases where the duty cycle of the input clock falls outside the 45% to 55% range, it is recommended to enable
an internal duty cycle correction circuit. Enable this circuit by setting the EN_DCC bit to '1'.
EXTERNAL REFERENCE
The AFE5805 can be made to operate in external reference mode by pulling the INT/EXT pin to '0'. In this mode,
the REFT and REFB pins should be driven with voltage levels of 2.5V and 0.5V, respectively, and must have
enough drive strength to drive the switched capacitance loading of the reference voltages by each ADC. The
advantage of using the external reference mode is that multiple AFE5805 units can be made to operate with the
same external reference, thereby improving parameters such as gain matching across devices. However, in
applications that do not have an available high drive, differential external reference, the AFE5805 can still be
driven with a single external reference voltage on the CM pin. When EXT_REF_VCM is set as '1' (and the
INT/EXT pin is set to '0'), the CM pin is configured as an input pin, and the voltages on REFT and REFB are
generated as shown in Equation 1 and Equation 2.
VCM
VREFT = 1.5V +
1.5V
(1)
VCM
VREFB = 1.5V -
1.5V
(2)
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BIT CLOCK PROGRAMMABILITY
The output interface of the AFE5805 is normally a DDR interface, with the LCLK rising edge and falling edge
transitions in the middle of alternate data windows. Figure 43 shows this default phase.
FCLKP
LCLKP
OUTP
Figure 43. LCLK Default Phase
The phase of LCLK can be programmed relative to the output frame clock and data using bits
PHASE_DDR<1:0>. Figure 44 shows the LCLK phase modes.
PHASE_DDR<1:0> = '00'
PHASE_DDR<1:0> = '10'
FCLKP
FCLKP
LCLKP
OUTP
LCLKP
OUTP
PHASE_DDR<1:0> = '01'
PHASE_DDR<1:0> = '11'
FCLKP
FCLKP
LCLKP
OUTP
LCLKP
OUTP
Figure 44. LCLK Phase Programmability Modes
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In addition to programming the phase of LCLK in the DDR mode, the device can also be made to operate in SDR
mode by setting the EN_SDR bit to '1'. In this mode, the bit clock (LCLK) is output at 12 times the input clock, or
twice the rate as in DDR mode. Depending on the state of FALL_SDR, LCLK may be output in either of the two
manners shown in Figure 45. As Figure 45 illustrates, only the LCLK rising (or falling) edge is used to capture the
output data in SDR mode.
EN_SDR = '1', FALL_SDR = '0'
EN_SDR = '1', FALL_SDR = '1'
FCLKP
FCLKP
LCLKP
OUTP
LCLKP
OUTP
Figure 45. SDR Interface Modes
The SDR mode does not work well beyond 40MSPS because the LCLK frequency becomes very high.
DATA OUTPUT FORMAT MODES
The ADC output, by default, is in straight offset binary mode. Programming the BTC_MODE bit to '1' inverts the
MSB, and the output becomes binary two's complement mode.
Also by default, the first bit of the frame (following the rising edge of FCLKP) is the LSB of the ADC output.
Programming the MSB_FIRST mode inverts the bit order in the word, and the MSB is output as the first bit
following the FCLKP rising edge.
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RECOMMENDED POWER-UP SEQUENCING AND RESET TIMING
t1
(3.3V, 5.0V)
AVDD1
AVDD2
DVDD
AVDD-5V
t2
(1.8V)
t3
LVDD
t4
t7
High-Level RESET
(1.4V to 3.6V)
t5
ADS_RESET
t6
Device Ready for
Serial Register Write
High-Level CS
(1.4V to 3.6V)
CS
Device Ready for
Data Conversion
Start of Clock
FCLK
t8
10ms < t1 < 50ms, 10ms < t2 < 50ms, –10ms < t3 < 10ms, t4 > 10ms, t5 > 100ns, t6 > 100ns, t7 > 10ms, and t8 > 100ms.
The AVDDx and LVDD power-on sequence does not matter as long as –10ms < t3 < 10ms. Similar considerations apply while shutting down
the device.
POWER-DOWN TIMING
(1)
1ms
tWAKE
VCA_PD, ADC_PD(2)
Device Fully
Powers Down
Device Fully
Powers Up
Power-up time shown is based on 1mF bypass capacitors on the reference pins. tWAKE is the time it takes for the device to wake up
completely from power-down mode. The AFE5805 has two power-down modes: complete power-down mode and partial power-down mode.
(1) tWAKE ≤ 50ms for complete power-down mode. tWAKE ≤ 2ms for partial power-down mode (provided the clock is not shut off during
power-down).
(2) The ADS_PD pins can be configured for partial power-down mode through a register setting.
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THEORY OF OPERATION
of 0V to 1.2V. While the LNA is designed to be driven
from a single-ended source, the internal TGC signal
path is designed to be fully differential to maximize
dynamic range while also optimizing for low,
even-order harmonic distortion.
The AFE5805 is an 8-channel, fully integrated analog
front-end device controlling the LNA, attenuator,
PGA, LPF, and ADC, that implements a number of
proprietary circuit design techniques to specifically
address the performance demands of medical
ultrasound systems. It offers unparalleled low-noise
and low-power performance at a high level of
integration. For the TGC signal path, each channel
consists of a 20dB fixed-gain low-noise amplifier
(LNA), a linear-in-dB voltage-controlled attenuator
(VCA), and a programmable gain amplifier (PGA), as
well as a clamping and low-pass filter stage. Digitally
controlled through the logic interface, the PGA gain
can be set to four different settings: 20dB, 25dB,
27dB, and 30dB. At its highest setting, the total
available gain of the AFE5805 is therefore 50dB. To
facilitate the logarithmic time-gain compensation
required for ultrasound systems, the VCA is designed
to provide a 46dB attenuation range. Here, all
channels are simultaneously controlled by an
externally-applied control voltage (VCNTL) in the range
CW doppler signal processing is facilitated by routing
the differential LNA outputs to V/I amplifier stages.
The resulting signal currents of each channel then
connect to an 8×10 switch matrix that is controlled
through the serial interface and a corresponding
register. The CW outputs are typically routed to a
passive delay line that allows coherent summing
(beam forming) of the active channels and additional
off-chip signal processing, as shown in Figure 46.
Applications that do not utilize the CW path can
simply operate the AFE5805 in TGC mode. In this
mode, the CW blocks (V/I amplifiers and switch
matrix) remain powered down, and the CW outputs
can be left unconnected.
AFE5805
CW/IOUT
V/I
CW Switch Matrix
T/R
Switch
CIN
OUT
LPF
Attenuator
(VCA)
LVDS
Serializer
12-Bit
ADC
Clamp
LNA
PGA
OUT
VCNTL
Figure 46. Functional Block Diagram
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LOW-NOISE AMPLIFIER (LNA)
The attenuator is essentially a variable voltage divider
that consists of the series input resistor (RS) and
eight identical shunt FETs placed in parallel and
controlled by sequentially activated clipping amplifiers
(A1 through A8). Each clipping amplifier can be
understood as a specialized voltage comparator with
As with many high-gain systems, the front-end
amplifier is critical to achieve a certain overall
performance level. Using
a
new proprietary
architecture, the LNA of the AFE5805 delivers
exceptional low-noise performance, while operating
a
soft transfer characteristic and well-controlled
on
a very low quiescent current compared to
output limit voltage. Reference voltages V1 through
V8 are equally spaced over the 0V to 1.2V control
voltage range. As the control voltage rises through
the input range of each clipping amplifier, the
amplifier output rises from 0V (FET completely ON) to
VCM – VT (FET nearly OFF), where VCM is the
common source voltage and VT is the threshold
voltage of the FET. As each FET approaches its off
state and the control voltage continues to rise, the
next clipping amplifier/FET combination takes over for
the next portion of the piecewise-linear attenuation
characteristic.
CMOS-based architectures with similar noise
performances.
The LNA performs a single-ended input to differential
output voltage conversion and is configured for a
fixed gain of 20dB (10V/V). The ultralow
input-referred noise of only 0.7nV/√Hz, along with the
linear input range of 250mVPP, results in a wide
dynamic range that supports the high demands of
PW and CW ultrasound imaging modes. Larger input
signals can be accepted by the LNA, but distortion
performance degrades as input signal levels
increase. The LNA input is internally biased to
approximately +2.4V; the signal source should be
ac-coupled to the LNA input by an adequately-sized
capacitor. Internally, the LNA directly drives the VCA,
avoiding the typical drawbacks of ac-coupled
architectures, such as slow overload recovery.
Thus, low control voltages have most of the FETs
turned on, producing maximum signal attenuation.
Similarly, high control voltages turn the FETs off,
leading to minimal signal attenuation. Therefore, each
FET acts to decrease the shunt resistance of the
voltage divider formed by RS and the parallel FET
network.
VOLTAGE-CONTROLLED ATTENUATOR
(VCA)
The VCA is designed to have
a linear-in-dB
attenuation characteristic; that is, the average gain
loss in dB is constant for each equal increment of the
control voltage (VCNTL). Figure 47 shows the
simplified schematic of this VCA stage.
A1-A8 Attenuator Stages
QS
RS
Attenuator
Input
Attenuator
Output
Q1
A2
Q2
A3
Q3
A4
Q4
Q5
Q6
A7
Q7
A8
Q8
VB
A1
A5
A6
C1
C2
C3
C4
C5
C6
C7
C8
V1
V2
V3
V4
V5
V6
V7
V8
VCNTL
Control
Input
C1-C8 Clipping Amplifiers
Figure 47. Voltage-Controlled Attenuator Simplified Schematic
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PROGRAMMABLE POST-GAIN AMPLIFIER
(PGA)
PROGRAMMABLE CLAMPING
Following the VCA is a programmable post-gain
amplifier (PGA). Figure 48 shows
a simplified
To further optimize the overload recovery behavior of
a complete TGC channel, the AFE5805 integrates a
programmable clamping stage, as shown in
Figure 49. This clamping stage precedes the
low-pass filter in order to prevent the filter circuit from
being driven into overload, the result of which would
be an extended recovery time. Programmable
through the serial interface, the clamping level can be
either set to clamp the signal level to approximately
1.7VPP differential, or be disabled. Disabling the
clamp function increases the current consumption on
the 3.3V analog supply (AVDD2) by about 3mA for
the full device. Note that with the clamp function
enabled, the third-harmonic distortion increases.
schematic of the PGA, including the clamping stage.
The gain of this PGA can be configured to four
different gain settings: 20dB, 25dB, 27dB, and 30dB,
programmable through the serial port; see Table 10.
The PGA structure consists of
programmable-gain voltage-to-current
a
differential,
converter
stage followed by transimpedance amplifiers to buffer
each side of the differential output. Low input noise is
also a requirement for the PGA design as a result of
the large amount of signal attenuation that can be
applied in the preceding VCA stage. At minimum
VCA attenuation (used for small input signals), the
LNA noise dominates; at maximum VCA attenuation
(large input signals), the attenuator and PGA noise
dominate.
LOW-PASS FILTER
The AFE5805 integrates an anti-aliasing filter in the
form of a programmable low-pass filter (LPF) for each
channel. The LPF is designed as a differential, active,
A1
second-order filter that approximates
a Bessel
characteristic, with typically 12dB per octave roll-off.
Figure 49 shows the simplified schematic of half the
differential active low-pass filter. Programmable
through the serial interface, the –3dB frequency
corner can be set to either 10MHz or 15MHz. The
filter bandwidth is set for all channels simultaneously.
Gain
Control
Bits
Clamp
Control
Bit
To
Low-Pass
Filter
From
Attenuator
RG
Clamp
A2
Figure 48. Post-Gain Amplifier
(Simplified Schematic)
PGA
To ADC
Inputs
VCM
(+1.65V)
Figure 49. Clamping Stage and Low-Pass Filter (Simplified Schematic)
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ANALOG-TO-DIGITAL CONVERSION
devices without having to externally drive and route
reference lines. The nominal values of REFT and
REFB are 2.5V and 0.5V, respectively. The
references are internally scaled down differentially by
a factor of 2. VCM (the common-mode voltage of
REFT and REFB) is also made available externally
through a pin, and is nominally 1.5V.
The analog-to-digital converter (ADC) of the AFE5805
employs
a pipelined converter architecture that
consists of a combination of multi-bit and single-bit
internal stages. Each stage feeds its data into the
digital error correction logic, ensuring excellent
differential linearity and no missing codes at the
12-bit level.
The ADC output goes to a serializer that operates
from a 12x clock generated by the PLL. The 12 data
bits from each channel are serialized and sent LSB
first. In addition to serializing the data, the serializer
also generates a 1x clock and a 6x clock. These
clocks are generated in the same way the serialized
data are generated, so these clocks maintain perfect
synchronization with the data. The data and clock
outputs of the serializer are buffered externally using
LVDS buffers. Using LVDS buffers to transmit data
The 12 bits given out by each channel are serialized
and sent out on a single pair of pins in LVDS format.
All eight channels of the AFE5805 operate from a
common input clock (CLKP/M). The sampling clocks
for each of the eight channels are generated from the
input clock using a carefully matched clock buffer
tree. The 12x clock required for the serializer is
generated internally from CLKP/M using
a
phase-locked loop (PLL). A 6x and a 1x clock are
also output in LVDS format, along with the data, to
enable easy data capture. The AFE5805 operates
from internally-generated reference voltages that are
trimmed to improve the gain matching across
devices, and provide the option to operate the
externally has multiple advantages, such as
a
reduced number of output pins (saving routing space
on the board), reduced power consumption, and
reduced effects of digital noise coupling to the analog
circuit inside the AFE5805.
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APPLICATION INFORMATION
The LNA closed-loop architecture is internally
compensated for maximum stability without the need
of external compensation components (inductors or
capacitors). At the same time, the total input
capacitance is kept to a minimum with only 16pF.
This architecture minimizes any loading of the signal
ANALOG INPUT AND LNA
While the LNA is designed as a fully differential
amplifier, it is optimized to perform a single-ended
input to differential output conversion. A simplified
schematic of an LNA channel is shown in Figure 50.
A bias voltage (VB) of +2.4V is internally applied to
the LNA inputs through 8kΩ resistors. In addition, the
dedicated signal input (IN pin) includes a pair of
back-to-back diodes that provide a coarse input
clamping function in case the input signal rises to
source
that
may
otherwise
lead
to
a
frequency-dependent voltage divider. Moreover, the
closed-loop design yields very low offsets and offset
drift; this consideration is important because the LNA
directly drives the subsequent voltage-controlled
attenuator.
very large levels, exceeding 0.7VPP
.
This
configuration prevents the LNA from being driven into
a severe overload state, which may otherwise cause
an extended overload recovery time. The integrated
diodes are designed to handle a dc current of up to
approximately 5mA. Depending on the application
requirements, the system overload characteristics
may be improved by adding external Schottky diodes
at the LNA input, as shown in Figure 50.
The LNA of the AFE5805 uses the benefits of a
bipolar process technology to achieve an
exceptionally low-noise voltage of 0.7nV/√Hz, and a
low current noise of only 3pA/√Hz. With these
input-referred noise specifications, the AFE5805
achieves very low noise figure numbers over a wide
range of source resistances and frequencies (see
Figure 16, Noise Figure vs Frequency vs RS in the
Typical Characteristics). The optimal noise power
matching is achieved for source impedances of
around 200Ω. Further details of the AFE5805 input
noise performance are shown in the Typical
Characteristic graphs.
As Figure 50 also shows, the complementary LNA
input (VBL pin) is internally decoupled by a small
capacitor. Furthermore, for each input channel, a
separate VBL pin is brought out for external
bypassing. This bypassing should be done with a
small, 0.1mF (typical) ceramic capacitor placed in
close proximity to each VBL pin. Attention should be
given to provide a low-noise analog ground for this
bypass capacitor. A noisy ground potential may
cause noise to be picked up and injected into the
signal path, leading to higher noise levels.
Table 16. Noise Figure versus Source Resistance
(RS) at 2MHz
RS (Ω)
50
NOISE FIGURE (dB)
2.6
1.0
1.1
2.3
200
400
1000
IN
T/R
A1
CIN
8kW
³ 0.1mF
To
Attenuator
VB
(+2.4V)
8kW
A2
VBL
0.1mF
7pF
AFE5805
Figure 50. LNA Channel (Simplified Schematic)
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OVERLOAD RECOVERY
±0.3V can significantly reduce the overall overload
recovery performance. The T/R switch characteristics
are largely determined by the biasing current of the
diodes, which can be set by adjusting the 3kΩ
resistor values; for example, setting a higher current
level may lead to an improved switching characteristic
and reduced noise contribution. A typical front-end
protection circuitry may add in the order of 2nV/√Hz
of noise to the signal path. The increase in noise also
depends on the value of the termination resistor (RT).
The AFE5805 is designed in particular for ultrasound
applications where the front-end device is required to
recover very quickly from an overload condition. Such
an overload can either be the result of a transmit
pulse feed-through or a strong echo, which can cause
overload of the LNA, PGA, and ADC. As discussed
earlier, the LNA inputs are internally protected by a
pair of back-to-back diodes to prevent severe
overload of the LNA. Figure 51 illustrates an
ultrasound receive channel front-end that includes
typical external overload protection elements. Here,
four high-voltage switching diodes are configured in a
bridge configuration and form the transmit/receive
(T/R) switch. During the transmit period, high voltage
pulses from the pulser are applied to the transducer
elements and the T/R switch isolates the sensitive
LNA input from being damaged by the high voltage
signal. However, it is common that fast transients up
to several volts leak through the T/R switch and
potentially overload the receiver. Therefore, an
additional pair of clamping diodes is placed between
the T/R switch and the LNA input. In order to clamp
the over-voltage to small levels, Schottky diodes
(such as the BAS40 series by Infineon®) are
commonly used. For example, clamping to levels of
As Figure 51 shows, the front-end circuitry should be
capacitively coupled to the LNA signal input (IN). This
coupling ensures that the LNA input bias voltage of
+2.4V is maintained and decoupled from any other
biasing voltage before the LNA.
Within the AFE5805, overload can occur in either the
LNA or the PGA. LNA overload can occur as the
result of T/R switch feed-through; and the PGA can
be driven into an overload condition by a strong echo
in the near-field while the signal gain is high. In any
case, the AFE5805 is optimized for very short
recovery times, as shown in Figure 51.
+5V
3kW
C1
C2
³ 0.1mF
Cable
IN
LNA
VBL
RT
BAS40
0.1mF
AFE5805
3kW
Probe
Transducer
From
Pulser
-5V
Figure 51. Typical Input Overload Protection Circuit of an Ultrasound System
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VCA—GAIN CONTROL
When the AFE5805 operates in CW mode, the
attenuator stage remains connected to the LNA
outputs. Therefore, it is recommended to set the
VCNTL voltage to +1.2V in order to minimize the
internal loading of the LNA outputs. Small
improvements in reduced power dissipation and
improved distortion performance may also be
realized.
The attenuator (VCA) for each of the eight channels
of the AFE5805 is controlled by a single-ended
control signal input, the VCNTL pin. The control voltage
range spans from 0V to 1.2V, referenced to ground.
This control voltage varies the attenuation of the VCA
based on its linear-in-dB characteristic with its
maximum attenuation (minimum gain) at VCNTL = 0V,
and minimum attenuation (maximum gain) at VCNTL
=
1.2V. Table 17 shows the nominal gains for each of
the four PGA gain settings. The total gain range is
typically 46dB and remains constant, independent of
the PGA selected; the Max Gain column reflects the
absolute gain of the full signal path comprised of the
fixed LNA gain of 20dB and the programmable PGA
gain.
AFE5805
Attenuator
RS
To
PGA
IN
LNA
Table 17. Nominal Gain Control Ranges for Each
of the Four PGA Gain Settings
RS
MIN GAIN AT
VCNTL = 0V
MAX GAIN AT
VCNTL = 1.2V
PGA GAIN
20dB
VCNTL
RF
–4.5dB
–0.5dB
1.5dB
41.5dB
45.5dB
47.5dB
49.5dB
25dB
27dB
CF
30dB
3.5dB
As previously discussed, the VCA architecture uses
eight attenuator segments that are equally spaced in
order to approximate the linear-in-dB gain-control
slope. This approximation results in a monotonic
slope; gain ripple is typically less than ±0.5dB.
Figure 52. External Filtering of the VCNTL Input
CW DOPPLER PROCESSING
The AFE5805 gain-control input has
a
–3dB
The AFE5805 integrates many of the elements
necessary to allow for the implementation of a CW
doppler processing circuit, such as a V/I converter for
each channel and a cross-point switch matrix with an
8-input into 10-output (8×10) configuration.
bandwidth of approximately 1.5MHz. This wide
bandwidth, although useful in many applications, can
allow high-frequency noise to modulate the gain
control input. In practice, this modulation can easily
be avoided by additional external filtering (RF and CF)
of the control input, as Figure 52 shows. Stepping the
control voltage from 0V to 1.2V, the gain control
response time is typically less than 500ns to settle
within 10% of the final signal level of 1VPP (–6dBFS)
output.
In order to switch the AFE5805 from the default TGC
mode operation into CW mode, bit D5 of the VCA
control register must be updated to low ('0'); see
Table 5. This setting also enables access to all other
registers that determine the switch matrix
configuration (see the Input Register Bit Map tables).
In order to process CW signals, the LNA internally
feeds into a differential V/I amplifier stage. The
transconductance of the V/I amplifier is typically
15.6mA/V with a 100mVPP input signal. For proper
operation, the CW outputs must be connected to an
external bias voltage of +2.5V. Each CW output is
designed to sink a small dc current of 0.9mA, and
The control voltage input (VCNTL pin) represents a
high-impedance input. Multiple AFE5805 devices can
be connected in parallel with no significant loading
effects using the VCNTL pin of each device. Note that
when the VCNTL pin is left unconnected, it floats up to
a potential of about +3.7V. For any voltage level
above 1.2V and up to 5.0V, the VCA continues to
operate at its minimum attenuation level; however, it
is recommended to limit the voltage to approximately
1.5V or less.
can deliver a signal current of up to 2.9mAPP
.
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The resulting signal current then passes through the
8×10 switch matrix. Depending on the programmed
configuration of the switch matrix, any V/I amplifier
current output can be connected to any of 10 CW
outputs. This design is a simple current-summing
circuit such that each CW output can represent the
sum of any or all of the channel currents. The CW
outputs are typically routed to a passive LC delay
line, allowing coherent summing of the signals.
After summing, the CW signal path further consists of
a high dynamic range mixer for down-conversion to
I/Q base-band signals. The I/Q signals are then
band-limited (that is, low-frequency contents are
removed) in a filter stage that precedes a pair of
high-resolution, low sample rate ADCs.
ADC
Amplifier
VCM0
(+2.5V)
L = 220mH
0
I and Q
Channel
90
CW0
CW1
CW2
CW3
ADC
Passive
Delay
Line
Clock
AFE5805
CW4
CW Out
8 In By 10 Out
CW5
CW6
CW7
CW8
CW9
CW0
CW1
CW2
CW3
CW4
CW5
CW6
CW7
CW8
CW9
AFE5805
CW Out
8 In By 10 Out
Figure 53. Conceptual CW Doppler Signal Path Using Current Summing and a Passive Delay Line for
Beamforming
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CLOCK INPUT
The eight channels on the device operate from a
single clock input. To ensure that the aperture delay
and jitter are the same for all channels, the AFE5805
uses a clock tree network to generate individual
sampling clocks to each channel. The clock paths for
all the channels are matched from the source point to
the sampling circuit. This architecture ensures that
the performance and timing for all channels are
identical. The use of the clock tree for matching
introduces an aperture delay that is defined as the
delay between the rising edge of FCLK and the actual
instant of sampling. The aperture delays for all the
channels are matched to the best possible extent. A
mismatch of ±20ps (±3s) could exist between the
aperture instants of the eight ADCs within the same
chip. However, the aperture delays of ADCs across
two different chips can be several hundred
picoseconds apart.
CM
VCM
5kW
5kW
CLKP
CLKM
Figure 55. Internal Clock Buffer
0.1mF
CLKP
The AFE5805 can operate either in CMOS
single-ended clock mode (default is DIFF_CLK = 0)
or differential clock mode (SINE, LVPECL, or LVDS).
In the single-ended clock mode, CLKM must be
forced to 0VDC, and the single-ended CMOS applied
on the CLKP pin. Figure 54 shows this operation.
Differential Sine-Wave,
PECL, or LVDS Clock Input
0.1mF
CLKM
Figure 56. Differential Clock Driving Circuit
(DIFF_CLK = 1)
CMOS Single-Ended
CLKP
Clock
0.1mF
0V
CLKM
CMOS Clock Input
CLKP
CLKM
0.1mF
Figure 54. Single-Ended Clock Driving Circuit
(DIFF_CLK = 0)
When configured for the differential clock mode
(register bit DIFF_CLK = 1) the AFE5805 clock inputs
can be driven differentially (SINE, LVPECL, or LVDS)
with little or no difference in performance between
Figure 57. Single-Ended Clock Driving Circuit
When DIFF_CLK = 1
them, or with
common-mode voltage of the clock inputs is set to
VCM using internal 5kΩ resistors, as shown in
a single-ended (LVCMOS). The
For best performance, the clock inputs must be
driven differentially, reducing susceptibility to
common-mode noise. For high input frequency
sampling, it is recommended to use a clock source
with very low jitter. Bandpass filtering of the clock
source can help reduce the effect of jitter. If the duty
cycle deviates from 50% by more than 2% or 3%, it is
recommended to enable the DCC through register bit
EN_DCC.
Figure
55.
This
method
allows
using
transformer-coupled drive circuits for a sine wave
clock or ac-coupling for LVPECL and LVDS clock
sources, as shown in Figure 56 and Figure 57. When
operating in the differential clock mode, the
single-ended CMOS clock can be ac-coupled to the
CLKP input, with CLKM connected to ground with a
0.1mF capacitor, as Figure 57 shows.
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REFERENCE CIRCUIT
The device also supports the use of external
reference voltages. There are two methods to force
the references externally. The first method involves
pulling INT/EXT low and forcing externally REFT and
REFB to 2.5V and 0.5V nominally, respectively. In
this mode, the internal reference buffer goes to a
3-state output. The external reference driving circuit
should be designed to provide the required switching
current for the eight ADCs inside the AFE5805. It
should be noted that in this mode, CM and ISET
continue to be generated from the internal bandgap
voltage, as in the internal reference mode. It is
therefore important to ensure that the common-mode
voltage of the externally-forced reference voltages
The digital beam-forming algorithm in an ultrasound
system relies on gain matching across all receiver
channels. A typical system would have about 12 octal
AFEs on the board. In such a case, it is critical to
ensure that the gain is matched, essentially requiring
the reference voltages seen by all the AFEs to be the
same. Matching references within the eight channels
of a chip is done by using a single internal reference
voltage buffer. Trimming the reference voltages on
each chip during production ensures that the
reference voltages are well-matched across different
chips.
matches to within 50mV of VCM
.
All bias currents required for the internal operation of
the device are set using an external resistor to
ground at the ISET pin. Using a 56kΩ resistor on
ISET generates an internal reference current of 20mA.
This current is mirrored internally to generate the bias
current for the internal blocks. Using a larger external
resistor at ISET reduces the reference bias current
and thereby scales down the device operating power.
However, it is recommended that the external resistor
be within 10% of the specified value of 56kΩ so that
the internal bias margins for the various blocks are
proper.
The second method of forcing the reference voltages
externally can be accessed by pulling INT/EXT low,
and programming the serial interface to drive the
external reference mode through the CM pin (register
bit called EXT_REF_VCM). In this mode, CM
becomes configured as an input pin that can be
driven from external circuitry. The internal reference
buffers driving REFT and REFB are active in this
mode. Forcing 1.5V on the CM pin in the mode
results in REFT and REFB coming to 2.5V and 0.5V,
respectively. In general, the voltages on REFT and
REFB in this mode are given by Equation 3 and
Equation 4:
Buffering the internal bandgap voltage also generates
the common-mode voltage VCM, which is set to the
midlevel of REFT and REFB. It is meant as a
reference voltage to derive the input common-mode if
the input is directly coupled. It can also be used to
derive the reference common-mode voltage in the
external reference mode. Figure 58 shows the
suggested decoupling for the reference pins.
VCM
VREFT = 1.5V +
1.5V
(3)
VCM
VREFB = 1.5V -
1.5V
(4)
The state of the reference voltage internal buffers
during various combinations of the ADS_PD,
INT/EXT, and EXT_REF_VCM register bits is
described in Table 18.
AFE5805
ISET
REFT
REFB
56.2kW
+
+
0.1mF
2.2mF
2.2mF
0.1mF
Figure 58. Suggested Decoupling on the Reference Pins
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Table 18. State of Reference Voltages for Various Combinations of ADS_PD and INT/EXT
PIN, REGISTER BIT
INTERNAL BUFFER STATE
ADS_PD pin
INT/EXT pin
EXT_REF_VCM
REFT buffer
REFB buffer
CM pin
0
0
0
1
0
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
1
1
1
3-state
3-state
1.5V
2.5V
0.5V
1.5V
3-state
3-state
1.5V
2.5V(1)
0.5V(1)
1.5V
1.5V + VCM/1.5V
1.5V – VCM/1.5V
Force
Do not use
Do not use
Do not use
2.5V(1)
0.5V(1)
Force
Do not use
Do not use
Do not use
(1) Weakly forced with reduced strength.
Poor RMS jitter (> 100ps), combined with inadequate
power-supply design (for example, supply voltage
drops and ripple increases), can affect LVDS timing.
As a result, occasional glitches might be observed on
the AFE5805 outputs. If this phenomenon is
observed, or if clock jitter and LVDD noise are
concerns in the overall system, the registers
described in Table 19 can be written as part of the
initialization sequence in order to stabilize LVDS
clock timing and SNR performance.
POWER SUPPLIES
The AFE5805 operates on three supply rails: a digital
1.8V supply, and the 3.3V and 5V analog supplies. At
initial power-up, the part is operational in TGC mode,
with the registers in the respective default
configurations (see Table 2).
In TGC mode, only the VCA (attenuator) draws a low
current (typically 8mA) from the 5V supply. Switching
into the CW mode, the internal V/I-amplifiers are then
powered from the 5V rails as well, raising the
operating current on the 5V rail. At the same time, the
post-gain amplifiers (PGA) are being powered down,
thereby reducing the current consumption on the 3.3V
rail (refer to the Electrical Characteristics table for
details on TGC mode and CW mode current
consumption).
Table 19. Address and Data in Hexadecimal
ADDRESS
DATA
0010h
0140h
0001h
0020h
0080h
0000h
01
D1
DA
E1
02
All analog supply rails for the AFE5805 should be low
noise, including the 3.3V digital supply DVDD that
connects to the internal logic blocks of the VCA within
the AFE5805. It is recommended to tie the DVDD
pins to the same 3.3V analog supply as the AVDD1/2
pins, rather than a different 3.3V rail that may also
provide power to other logic device in the system.
Transients and noise generated by those devices can
couple into the AFE5805 and degrade overall device
performance.
01
Writing to these registers has the following additional
effects:
a. Total chip power increases by approximately
8mW—this includes a current increase of about
1.9mA on AVDD1 and about 1.1mA on LVDD.
b. With reference to the LVDS Timing Diagram and
the Definition of Setup and Hold Times,
LCLKP/LCLKM shift by about 100ps to the left
relative to CLK and OUTP/OUTM. This shift
causes the data setup time to reduce by 100ps
and the data hold time to increase by 100ps.
CLOCK JITTER, POWER NOISE, SNR, AND
LVDS TIMING
As explained in application note SLYT075, ADC clock
jitter can degrade ADC performance. Therefore, it is
always preferred to use a low jitter clock to drive the
AFE5805. To ensure the performance of the
AFE5805, a clock with a jitter of 1ps RMS or better is
expected. However, it might not be always possible to
use this clock configuration for practical reasons. With
a higher clock jitter, the SNR of the AFE5805 may be
degraded as well as the LVDS timing stability. In
addition, clean and stable power supplies are always
preferred to maximize device SNR performance and
ensure LVDS timing stability.
c. The clock propagation delay (tPROP) is reduced by
approximately 2ns. The typical and minimum
values for this specification are reduced by 2ns,
and the maximum value is reduced by 1.5ns.
Power-supply noise usually can be minimized if
grounding, bypassing, and printed circuit board (PCB)
layout are well managed. Some guidelines can be
found in the Grounding and Bypassing and Board
Layout sections.
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AFE5805
SBOS421D –MARCH 2008–REVISED MARCH 2010
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GROUNDING AND BYPASSING
High-speed mixed signal devices are sensitive to
various types of noise coupling. One primary source
of noise is the switching noise from the serializer and
the output buffer/drivers. For the AFE5805, care has
been taken to ensure that the interaction between the
analog and digital supplies within the device is kept to
a minimal amount. The extent of noise coupled and
transmitted from the digital and analog sections
depends on the effective inductances of each of the
supply and ground connections. Smaller effective
inductance of the supply and ground pins leads to
improved noise suppression. For this reason, multiple
pins are used to connect each supply and ground
sets. It is important to maintain low inductance
properties throughout the design of the PCB layout by
use of proper planes and layer thickness.
The AFE5805 distinguishes between three different
grounds: AVSS1 and AVSS2 (analog grounds), and
LVSS (digital ground). In most cases, it should be
adequate to lay out the printed circuit board (PCB) to
use a single ground plane for the AFE5805. Care
should be taken that this ground plane is properly
partitioned between various sections within the
system to minimize interactions between analog and
digital circuitry. Alternatively, the digital (LVDS)
supply set consisting of the LVDD and LVSS pins can
be placed on separate power and ground planes. For
this configuration, the AVSS and LVSS grounds
should be tied together at the power connector in a
star layout.
All bypassing and power supplies for the AFE5805
should be referenced to this analog ground plane. All
supply pins should be bypassed with 0.1mF ceramic
chip capacitors (size 0603 or smaller). In order to
minimize the lead and trace inductance, the
capacitors should be located as close to the supply
pins as possible. Where double-sided component
mounting is allowed, these capacitors are best placed
directly under the package. In addition, larger bipolar
decoupling capacitors (2.2mF to 10mF, effective at
lower frequencies) may also be used on the main
supply pins. These components can be placed on the
PCB in proximity (< 0.5in or 12.7mm) to the AFE5805
itself.
BOARD LAYOUT
Proper grounding and bypassing, short lead length,
and the use of ground and power-supply planes are
particularly important for high-frequency designs.
Achieving
optimum
performance
with
a
high-performance device such as the AFE5805
requires careful attention to the PCB layout to
minimize the effects of board parasitics and optimize
component placement. A multilayer PCB usually
ensures best results and allows convenient
component placement.
In order to maintain proper LVDS timing, all LVDS
traces should follow a controlled impedance design
(for example, 100Ω differential). In addition, all LVDS
trace lengths should be equal and symmetrical; it is
recommended to keep trace length variations less
than 150mil (0.150in or 3.81mm).
The AFE5805 internally generates a number of
reference voltages, such as the bias voltages (VB1
through VB6). Note that in order to achieve optimal
low-noise performance, the VB1 pin must be
bypassed with a capacitor value of at least 1mF; the
recommended value for this bypass capacitor is
2.2mF. All other designed reference pins can be
bypassed with smaller capacitor values, typically
0.1mF. For best results choose low-inductance
ceramic chip capacitors (size 402) and place them as
close as possible to the device pins as possible.
Additional details on PCB layout techniques can be
found in the Texas Instruments Application Report
MicroStar BGA Packaging Reference Guide
(SSYZ015B), which can be downloaded from the TI
web site (www.ti.com).
48
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Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): AFE5805
AFE5805
www.ti.com
SBOS421D –MARCH 2008–REVISED MARCH 2010
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October, 2008) to Revision D
Page
•
•
•
•
•
•
•
•
•
•
•
Changed Output transconductance specification notation from V/I to IOUT/VIN ..................................................................... 4
Changed Input clock (FCLK) rising edge to ADC input clock for Clock propagation delay parameter description ............ 13
Changed Input clock (FCLK) rising edge to ADC input clock for Clock propagation delay parameter description ............ 13
Corrected PD polarity and notation in Figure 38 ................................................................................................................ 20
Changed CS input line connection to SPI interface and register block in Figure 41 .......................................................... 21
Changed footnote 2 for Table 2 .......................................................................................................................................... 23
Changed ADC_RESET to ADS_RESET in VCA Reset section ......................................................................................... 25
Changed hyperlink pointer in paragraph five of Power-Down Modes section .................................................................... 29
Changed last sentence of second paragraph in CLOCK JITTER, POWER NOISE, SNR, AND LVDS TIMING ............... 47
Added 02, 0080h to Table 19 ............................................................................................................................................. 47
Changed note a; updated values of current increase from 4mW to 8mW and 0.6mA to 1.9mA ....................................... 47
Changes from Revision B (July, 2008) to Revision C
Page
•
•
•
•
•
•
•
•
•
•
Corrected VCM subscript for common-mode voltage (internal) and VCM output current ........................................................ 4
Changed AVDD2 to AVDD1 in description of pin L9 .......................................................................................................... 10
Added statement about register initialization to Register Initialization section ................................................................... 21
Changed bit D7 for address 42; added values of '1' for all four functions .......................................................................... 24
Changed VCM pin to CM pin .............................................................................................................................................. 24
Revised External Reference section, Equation 1 and Equation 2 to reflect CM pin instead of VCM pin ........................... 33
Corrected second paragraph of Analog-to-Digital Conversion section to change VCM to CM .......................................... 40
Changed total input capacitance description from 30pF to 16pF ....................................................................................... 41
Changed VCM to CM .......................................................................................................................................................... 45
Changed common-mode voltage VCM to VCM and related references to CM pin, including Equation 3 and
Equation 4 ........................................................................................................................................................................... 46
•
•
Changed VCM to VCM ......................................................................................................................................................... 47
Added CLOCK JITTER, POWER NOISE, SNR, AND LVDS TIMING, Clock Jitter, Power Noise, SNR, and LVDS
Timing ................................................................................................................................................................................. 47
Copyright © 2008–2010, Texas Instruments Incorporated
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Product Folder Link(s): AFE5805
PACKAGE OPTION ADDENDUM
www.ti.com
18-Dec-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
AFE5805ZCF
ACTIVE
BGA
ZCF
135
160 Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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