AFE7070_技术文档

AFE7070

www.ti.com.cn

ZHCSA89D – FEBRUARY 2012–REVISED JANUARY 2013

带有集成模拟正交调制器的双路 14 位 65 百万次采样/秒 (MSPS) 数模转换

器

查询样品: AFE7070

1

特性

应用范围

•

最大采样率：65MSPS

•

低功耗、紧凑型软件无线电

低功耗：

飞蜂窝和微蜂窝基站 (BTS)

–

325mW 低压差分信令 (LVDS) 输出模式

334mW 模拟输出模式

时钟频率变换

说明

•

交叉 CMOS 输入，1.8-3.3V IOVDD

AFE7070 是一款双路 14 位 65MSPS 数模转换器

(DAC)，此转换器具有集成的、可编程四阶基带滤波器

和模拟正交调制器。 AFE7070 包括用于频率生成/转

换的数控振荡器和用于提供 LO 和边带抑制功能的正交

调制器校正电路等附加数字信号处理特性。 AFE7070

有一个交叉的 14 位 1.8V 至 3.3V CMOS 输入。

AFE7070 提供 RF 输出频率范围介于 100MHz 至

2.7GHz 之间的 20MHz RF 信号带宽。一个可选

LVDS 输出可被用于将正交调制器输出转换为一个高达

800MHz 的时钟信号。使用 LVDS 输出时，总功耗小

于 350mW；使用模拟 RF 输出时，总功耗小于

334mW。

针对独立数据和数模转换器 (DAC) 时钟的输入

FIFO

•

用于寄存器编程的 3 或 4 个引脚 SPI 接口

复杂数控振荡器 (NCO) (DDS)：32 位频率，16 位

相位

•

正交调制器校正：针对边带和本地振荡 (LO) 抑制

的增益、相位、偏移

支持可编程带宽的模拟基带滤波器：20MHz 最大射

频 (RF) 带宽

•

RF 输出：模拟（线性）或 LVDS（时钟）

RF 频率范围：100MHz 至 2.7GHz

封装：48 引脚四方扁平无引线 (QFN) 封装 (7mm

x 7mm)

AFE7070 采用 7mm x 7mm 48 引脚 QFN 封装。

AFE7070 可在整个工业温度范围（-40°C 至 85°C）内

工作。

AVAILABLE OPTIONS

T_A

ORDER CODE

AFE7070IRGZ25

AFE7070IRGZT

AFE7070IRGZR

PACKAGE DRAWING/TYPE

TRANSPORT MEDIA

QUANTITY

25

–40°C to 85°C

RGZ / 48QFN quad flatpack no-lead

Tape and reel

250

2500

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

English Data Sheet: SLOS761

AFE7070

ZHCSA89D – FEBRUARY 2012–REVISED JANUARY 2013

www.ti.com.cn

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

BLOCK DIAGRAM

RESETB

BG_BYP

SCLK

SDENB

SDIO

SPI/

Registers

1.2-V

REF

Dual

DAC

Quadrature

Modulator

ALARM_SDO

D[13:0]

NCO/

Mixer

(DDS)

RF_OUT

Demux

Clock

QMC

IQ_FLAG

SYNC_SLEEP

Baseband

Filter

¸1,2,4

CLK_IO

LVDS_P/N

¸2

DACCLKP/N

LO_P/N

PIN CONFIGURATION

RGZ Package

(Top View)

48 47 46 45 44 43 42 41 40 39 38 37

DACCLKP

1

ATEST

36

DACCLKN

CLKVDD18

2

35

34

33

32

31

30

29

28

27

26

25

TESTMODE

ALARM_SDO

3

DACVDD33

CLK_IO

4

LO_N

LO_P

5

IQ_FLAG

SDENB

6

AFE7070

SYNC_SLEEP

RESETB

D13 (MSB)

D12

7

SCLK

8

SDIO

D0 (LSB)

9

10

11

12

D1

GND

DVDD18

13 14 15 16 17 18 19 20 21 22 23 24

P0023-25

2

AFE7070

www.ti.com.cn

ZHCSA89D – FEBRUARY 2012–REVISED JANUARY 2013

PIN FUNCTIONS

NAME

I/O

DESCRIPTION

NO.

MISC/SERIAL

CMOS output for ALARM condition, active-low. The ALARM output functionality is defined through the

CONFIG7 registers.

ALARM_SDO

34

O

Optionally, it can be used as the unidirectional data output in 4-pin serial interface mode (CONFIG3

sif_4pin = 1). 1.8-V to 3.3-V CMOS, set by IOVDD.

RESETB

SCLK

8

I

Resets the chip when low. 1.8-V to 3.3-V CMOS, set by IOVDD. Internal pullup

Serial interface clock. 1.8-V to 3.3-V CMOS, set by IOVDD. Internal pulldown

30

31

SDENB

Active-low serial data enable, always an input. 1.8-V to 3.3-V CMOS, set by IOVDD. Internal pullup

Bidirectional serial data in 3-pin mode (default). In 4-pin interface mode (CONFIG3 sif_4pin), the SDIO

pin is an input only. 1.8-V to 3.3-V CMOS, set by IOVDD. Internal pulldown

SDIO

29

I/O

DATA/CLOCK INTERFACE

Single-ended input or output CMOS level clock for latching input data. 1.8-V to 3.3-V CMOS, set by

IOVDD.

CLK_IO

5

I/O

I

9, 10,

14–23,

27, 28

Data bits 0 through 13. D13 is the MSB, D0 is the LSB. For complex data, channel I and channel Q are

multiplexed. For NCO phase data, either 14 bits are transferred at the internal sample clock rate, or 8

MSBs and 8 LSBs are interleaved on D[13:6]. 1.8-V to 3.3-V CMOS, set by IOVDD. Internal pulldown

D[13:0]

DACCLKP,

DACCLKN

1, 2

6

I

Differential input clock for DACs.

When register CONFIG1 iqswap is 0, IQ-FLAG high identifies the DACA sample in dual-input or dual-

output clock modes. 1.8-V or 3.3-V CMOS, set by IOVDD. Internal pulldown

IQ_FLAG

Multi-function. Sync signal for signal processing blocks, TX ENABLE or SLEEP function. Selectable via

SPI. 1.8-V to 3.3-V CMOS, set by IOVDD.

SYNC_SLEEP

RF

7

Local oscillator input. Can be used differentially or single-ended by terminating the unused input

through a capacitor and 50-Ω resistor to GND.

LO_P, LO_N

32, 33

I

LVDS_P,

LVDS_N

45, 44

42

O

Differential LVDS output

Analog RF output

RF_OUT

REFERENCE

ATEST

36

47

35

O

I

Factory use only. Do not connect.

BG_BYP

Reference voltage decoupling – connect 0.1 µF to GND.

Factory use only. Connect to GND.

TESTMODE

POWER

I

IOVDD

13, 24

3

I

1.8-V to 3.3-V supply for CMOS I/Os

CLKVDD18

DVDD18

1.8 V

12, 25

46

1.8 V

LVDSVDD18

DACVDD18

DACVDD33

MODVDD33

FUSEVDD18

1.8 V

37, 48

4

1.8 V

3.3 V

38, 39

40

3.3 V

Connect to 1.8 V to 3.3 V supply (1.8 V is preferred to lower power dissipation).

11, 26,

41, 43

GND

I

Ground

3

AFE7070

ZHCSA89D – FEBRUARY 2012–REVISED JANUARY 2013

www.ti.com.cn

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

VALUE

DACVDD33, MODVDD33, FUSEVDD18, IOVDD⁽²⁾

Supply voltage

DVDD18, CLKVDD18, DACVDD18⁽²⁾

range

–0.5 V to 4 V

–0.5 V to 2.3 V

–0.5 V to 4 V

D[13..0], IQ FLAG, SYNC_SLEEP, SCLK, SDENB, SDIO, ALARM_SDO,

–0.5 V to IOVDD + 0.5 V

RESETB , CLK_IO, TESTMODE

DACCLKP, DACCLKN

LVDS_P, LVDS_N

Supply voltage

range⁽²⁾

–0.5 V to CLKVDD18 + 0.5 V

–0.5 V to LVDSVDD18 + 0.5 V

–0.5 V to DACVDD33 + 0.5 V

–0.5 V to MODVDD33 + 0.5 V

–40°C to 85°C

BG_BYP, ATEST

RFOUT, LO_P, LO_N

Operating free-air temperature range, T_A

Storage temperature range

–65°C to 150°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of these or any other conditions beyond those indicated under Recommended Operating Conditions is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Measured with respect to GND

DC ELECTRICAL CHARACTERISTICS

Typical values at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX= 85°C, DAC sampling rate = 65 MSPS, DVDD18

= 1.8 V, CLKVDD18 = 1.8 V, DACVDD18 = 1.8 V, IOVDD = 3.3 V, DACVDD33 = 3.3 V, MODVDD33 = 3.3 V, analog output

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Bits

V

DC SPECIFICATIONS

DAC resolution

REFERENCE OUTPUT

Reference voltage

POWER SUPPLY

14

1.14

1.2

1.26

IOVDD

I/O supply voltage

Digital supply voltage

1.71

3.15

3.6

1.89

3.6

V

DVDD18

CLKVDD18

DACVDD18

LVDSVDD18

FUSEVDD18

DACVDD33

MODVDD33

I_IOVDD

1.8

3.3

Clock supply voltage

V

DAC 1.8-V analog supply voltage

LVDS analog supply voltage

FUSE analog supply voltage

DAC 3.3-V analog supply voltage

Modulator analog supply voltage

I/O supply current

V

Connect to 1.8-V supply for lower power

V

3.45

V

mA

I_DVDD18

Digital supply current

18

I_CLKVDD18

Clock supply current

I_DACVDD18

DAC 1.8-V supply current

LVDS output supply current

FUSE supply current

I_LVDSVDD18

I_FUSEVDD18

I_DACVDD33

21

DAC 3.3-V supply current

Modulator supply current

I_MODVDD33

68

LVDS output: NCO, QMC active, f_DAC= 40 MHz, IOVDD = 2.5

V

337

380

mW

Analog output: NCO off, QMC active, f_DAC= 65 MHz, IOVDD =

2.5 V

335

80

5

mW

Power dissipation

Sleep mode with clock, internal reference on, IOVDD = 2.5 V

Sleep mode without clock, internal reference off, IOVDD = 2.5

V

25

POWER SUPPLY vs MODE

3.3-V supplies (DACVDD33, MODVDD33, IOVDD)

72

47

mA

mW

1.8-V supplies (DVDD18, CLKVDD18, DACVDD18,

FUSEVD18, LVDSVDD18)

NCO = 1 MHz, LVDS on, RF out off, no input data, 65 MSPS

Power dissipation

322

4

AFE7070

www.ti.com.cn

ZHCSA89D – FEBRUARY 2012–REVISED JANUARY 2013

DC ELECTRICAL CHARACTERISTICS (continued)

Typical values at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX= 85°C, DAC sampling rate = 65 MSPS, DVDD18

= 1.8 V, CLKVDD18 = 1.8 V, DACVDD18 = 1.8 V, IOVDD = 3.3 V, DACVDD33 = 3.3 V, MODVDD33 = 3.3 V, analog output

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

3.3-V supplies (DACVDD33, MODVDD33, IOVDD)

71

mA

NCO = 1 MHz, LVDS on, RF out off,

no input data, 40 MSPS

1.8-V supplies (DVDD18, CLKVDD18, DACVDD18,

FUSEVDD18, LVDSVDD18)

32

mA

Power dissipation

337

102

mW

mA

3.3-V supplies (DACVDD33, MODVDD33, IOVDD)

1 MHz full-scale input, RF out on, LVDS output off,

NCO off, QMC on, 65 MSPS

1.8-V supplies (DVDD18, CLKVDD18, DACVDD18,

FUSEVD18, LVDSVDD18)

36

mA

Power dissipation

334

101

mW

mA

3.3-V supplies (DACVDD33, MODVDD33, IOVDD)

1 MHz full-scale input, RF out on, LVDS output off,

NCO off, QMC off, 32.5 MSPS

1.8-V supplies (DVDD18, CLKVDD18, DACVDD18,

FUSEVD18, LVDSVDD18)

22

mA

Power dissipation

325

mW

5

AFE7070

ZHCSA89D – FEBRUARY 2012–REVISED JANUARY 2013

www.ti.com.cn

ELECTRICAL CHARACTERISTICS

Typical values at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX= 85°C, DAC sampling rate = 65 MSPS, DVDD18

= 1.8 V, CLKVDD18 = 1.8 V, DACVDD18 = 1.8 V, FUSEVDD18 = 1.8 V, IOVDD = 3.3 V, DACVDD33 = 3.3 V, MODVDD33 =

3.3 V, analog output (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS (D[13:0], IQ_FLAG, SDI, SCLK, SDENB, RESETB, SYNC_SLEEP, ALARM_SDO, CLK_IO)

IOVDD = 3.3 V

2.3

1.75

1.25

V_IH

High-level input voltage

Low-level input voltage

IOVDD = 2.5 V

IOVDD = 1.8 V

IOVDD = 3.3 V

IOVDD = 2.5 V

IOVDD = 1.8 V

IOVDD = 3.3 V

V

1

0.75

0.54

80

V_IL

V

I_IH

High-level input current

Low-level input current

Input capacitance

DAC sample rate

–80

µA

I_IL

80

C_i

5

pF

f_DAC

f_INPUT

Interleaved data, f_DAC= 1/2 × f_INPUT

Interleaved data, f_INPUT= 2 × f_DAC

0

65

MSPS

Input data rate

130

DIGITAL OUTPUTS (ALARM_SDO, SDIO, CLK_IO)

I_LOAD= –100 µA

I_LOAD= –2 mA

I_LOAD= 100 µA

I_LOAD= 2 mA

IOVDD – 0.2

0.8 × IOVDD

V

V_OH

High-level output voltage

Low-level output voltage

0.2

V_OL

0.22 × IOVDD

CLOCK INPUT (DACCLKP/DACCLKN)

DACCLKP/N duty cycle

40%

0.4

60%

1

DACCLKP/N differential voltage

V

Timing Parallel Data Input (D[13:0], IQ_FLAG, SYNC_SLEEP) – Dual Input Clock Mode

t_SU

t_H

Input setup time

Relative to CLK_IO rising edge

1

3

ns

Input hold time

t_LPH

Input clock pulse high time

Timing Parallel Data Input (D[13:0], IQ_FLAG, SYNC_SLEEP) – Dual Output Clock Mode

t_SU

t_H

Input setup time

Input hold time

Relative to CLK_IO rising edge

1

0.2

ns

Timing Parallel Data Input (D[13:0], IQ_FLAG, SYNC_SLEEP) – Single Differential DDR and SDR Clock Modes

t_SU

t_H

Input setup time

Input hold time

Relative to DACCLKP/N rising edge

0

2

–0.8

1

ns

Timing – Serial Data Interface

t_S(SDENB)

t_S(SDIO)

t_H(SDIO)

t_SCLK

Setup time, SDENB to rising edge of SCLK

20

10

5

ns

Setup time, SDIO valid to rising edge of SCLK

Hold time, SDIO valid to rising edge of SCLK

Period of SCLK

100

40

10

25

t_SCLKH

t_SCLKL

t_D(DATA)

t_RESET

High time of SCLK

Low time of SCLK

Data output delay after falling edge of SCLK

Minimum RESETB pulse duration

6

AFE7070

www.ti.com.cn

ZHCSA89D – FEBRUARY 2012–REVISED JANUARY 2013

AC ELECTRICAL CHARACTERISTICS

Typical values at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX= 85°C, DAC sampling rate = 65 MSPS, DVDD18

= 1.8 V, CLKVDD18 = 1.8 V, DACVDD18 = 1.8 V, FUSEVDD18 = 1.8 V, IOVDD = 3.3 V, DACVDD33 = 3.3 V, MODVDD33 =

3.3 V, analog output (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

LO INPUT

f_LO

LO frequency range

LO input power

0.1

–5

15

2.7

5

GHz

dBm

P_{LO_IN}

LO port return loss

LVDS OUTPUT

f_{LVDS_OUT}LVDS output frequency

INTEGRATED BASEBAND FILTER

100

800

MHz

dB

2.5 MHz

5 MHz

1

18

42

65

1

Baseband attenuation at setting

Filtertune = 8 relative to low-frequency

signal

10 MHz

20 MHz

10 MHz

20 MHz

40 MHz

55 MHz

Baseband attenuation at setting

Filtertune = 0 relative to low-frequency

signal

18

42

58

dB

RMS phase deviation from linear phase across

minimum or maximum cutoff frequency

Baseband filter phase linearity

Baseband filter amplitude ripple

2

Degrees

dB

Frequency < 0.9 × nominal cutoff frequency

0.5

RF Output Parameters – f_LO= 100 MHz, Analog Output

P_{OUT_FS}Full-scale RF output power Full-scale 50-kHz digital sine wave

–1

63

dBm

dBc

IP2

IP3

Output IP2

Maximum LPF BW setting, f_BB= 4.5, 5.5 MHz

Unadjusted, f_BB= 50 kHz, full scale

Output IP3

18

Carrier feedthrough

Sideband suppression

Output noise floor

Output return loss

45

Unadjusted, f_BB= 50 kHz, full scale

27

dBc

≥ 30 MHz offset, f_BB= 50 kHz, full scale

137

8.5

dBc/Hz

dB

RF Output Parameters – f_LO= 450 MHz, Analog Output

P_{OUT_FS}Full-scale RF output power Full-scale 50-kHz digital sine wave

0.2

67

dBm

dBc

IP2

IP3

Output IP2

Max LPF BW setting, f_BB= 4.5, 5.5 MHz

Unadjusted, f_BB= 50 kHz, full scale

≥ 30 MHz offset, f_BB= 50 kHz, full scale

Output IP3

19

Carrier feedthrough

Sideband Suppression

Output noise floor

Output return loss

45

38

dBc

143

8.5

dBc/Hz

dB

RF Output Parameters – f_LO= 850 MHz, Analog Output

P_{OUT_FS}Full-scale RF output power Full-scale 50-kHz digital sine wave

0.3

64

dBm

dBc

IP2

IP3

Output IP2

Max LPF BW setting, f_BB= 4.5, 5.5 MHz

Unadjusted, f_BB= 50 kHz, full scale

≥ 30 MHz offset, f_BB= 50 kHz, full scale

Output IP3

19

Carrier feedthrough

Sideband suppression

Output noise floor

Output return loss

41

37

dBc

143

8.5

dBc/Hz

dB

1 WCDMA TM1 signal, PAR = 10 dB,

P_OUT= –10 dBFS

65

61

dBc

ACPR

Adjacent-channel power ratio

10-MHz LTE, PAR = 10 dB, P_OUT= –10 dBFS

7

AFE7070

ZHCSA89D – FEBRUARY 2012–REVISED JANUARY 2013

www.ti.com.cn

AC ELECTRICAL CHARACTERISTICS (continued)

Typical values at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX= 85°C, DAC sampling rate = 65 MSPS, DVDD18

= 1.8 V, CLKVDD18 = 1.8 V, DACVDD18 = 1.8 V, FUSEVDD18 = 1.8 V, IOVDD = 3.3 V, DACVDD33 = 3.3 V, MODVDD33 =

3.3 V, analog output (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

1 WCDMA TM1 signal, PAR = 10 dB,

P_OUT= –10 dBFS

ALT1

Alternate-channel power ratio

66

dBc

RF Output Parameters – f_LO= 2.1 GHz, Analog Output

P_{OUT_FS}Fullscale RF output power

–1.5

50

dBm

dBc

IP2

IP3

Output IP2

Output IP3

19

Carrier feedthrough

Sideband suppression

Output noise floor

Output return loss

38

42

dBc

≥ 30 MHz offset, f_BB= 50 kHz, full scale

141

8.5

dBc/Hz

dB

1 WCDMA TM1 signal, PAR = 10 dB,

P_OUT= –10 dBFS

ACPR

ALT1

Adjacent-channel power ratio

65

61

65

dBc

20 MHz LTE, PAR = 10 dB,

P_OUT= - 10 dBFS

1 WCDMA TM1 signal, PAR = 10 dB,

P_OUT= –10 dBFS

Alternate-channel power ratio

RF Output Parameters – f_LO= 2.7 GHz, Analog Output

P_{OUT_FS}Full-scale RF output power

–3.6

48

dBm

dBc

IP2

IP3

Output IP2

Output IP3

17

Carrier feedthrough

Sideband suppression

Output noise floor

Output return loss

36

35

dBc

≥ 30 MHz offset, f_BB= 50 kHz, full scale

139

8.5

dBc/Hz

dB

RF Output Parameters – f_LO= 622 MHz, LVDS Output, ÷4

V_OD

V_OC

Differential output voltage

Common-mode output voltage

Output noise floor

Assumes a 100-Ω differential load

247 350

454

mV

V

1.125 1.25 1.375

≥ 13 MHz offset, f_BB= 1 MHz

Carrier feedthrough

Unadjusted, f_BB= 50 kHz, full scale

Unadjusted, f_BB= 50 kHz, full cale

40

dBc

Sideband suppression

8

AFE7070

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ZHCSA89D – FEBRUARY 2012–REVISED JANUARY 2013

TYPICAL PERFORMANCE PLOTS

T_A= 25°C, DAC sampling rate = 65 MSPS, single-tone IF = 1.1 MHz, two-tone IF = 1 MHz and 2 MHz, DVDD18 = 1.8 V,

CLKVDD18 = 1.8 V, DACVDD18 = 1.8 V, FUSEVDD18 = 1.8 V, IOVDD = 3.3 V, DACVDD33 = 3.3 V, MODVDD33 = 3.3 V,

analog output, unless otherwise noted

2

1

2

1

−5 dBm

0 dBm

8 dBm

−40°C

25°C

85°C

0

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

1000

2000

3000

4000

1000

2000

3000

4000

LO Frequency (MHz)

G000

G001

Figure 1. Output Power vs LO Frequency and LO Power

Figure 2. Output Power vs LO Frequency and Temperature

2

1

3.15V

3.3V

3.45V

0

−1

−2

−3

−4

−5

−6

−7

−8

−9

−10

1000

2000

LO Frequency (MHz)

3000

4000

G002

Figure 3. Output Power vs LO Frequency and Supply Voltage

20

19

18

17

16

15

14

13

12

−5dBm

0dBm

8dBm

−5

−10

−15

−20

Frequency = 1960 MHz

Frequency = 2140 MHz

11

10

−20

−15

−10

−5

1000

2000

3000

4000

CW Digital Input Power (dBFS)

Frequency (MHz)

G003

G004

Figure 4. Output Power vs Input Power and LO Frequency

Figure 5. OIP3 vs LO Frequency and LO Power

9

AFE7070

ZHCSA89D – FEBRUARY 2012–REVISED JANUARY 2013

www.ti.com.cn

TYPICAL PERFORMANCE PLOTS (continued)

T_A= 25°C, DAC sampling rate = 65 MSPS, single-tone IF = 1.1 MHz, two-tone IF = 1 MHz and 2 MHz, DVDD18 = 1.8 V,

CLKVDD18 = 1.8 V, DACVDD18 = 1.8 V, FUSEVDD18 = 1.8 V, IOVDD = 3.3 V, DACVDD33 = 3.3 V, MODVDD33 = 3.3 V,

analog output, unless otherwise noted

22

21

20

19

18

17

16

15

14

13

12

22

21

20

19

18

17

16

15

14

13

12

−40°C

25°C

85°C

3.15V

3.3V

3.45V

1000

2000

3000

4000

1000

2000

3000

4000

Frequency (MHz)

G005

G006

Figure 6. OIP3 vs LO Frequency and Temperature

Figure 7. OIP3 vs LO Frequency and Supply Voltage

75

−5dBm

0dBm

8dBm

−40°C

25°C

85°C

70

65

60

55

50

45

40

35

30

25

70

65

60

55

50

45

40

35

30

25

1000

2000

3000

4000

1000

2000

3000

4000

Frequency (MHz)

G007

G008

Figure 8. OIP2 vs LO Frequency and LO Power

Figure 9. OIP2 vs LO Frequency and Temperature

75

70

65

60

55

50

45

40

35

30

25

−25

3.15V

3.3V

3.45V

−5dBm

0dBm

8dBm

−30

−35

−40

−45

−50

1000

2000

3000

4000

1000

2000

3000

4000

Frequency (MHz)

G009

G010

Figure 10. OIP2 vs LO Frequency and Supply Voltage

Figure 11. Unadjusted Carrier Feethrough vs LO Frequency

and LO Power

10

AFE7070

www.ti.com.cn

ZHCSA89D – FEBRUARY 2012–REVISED JANUARY 2013

TYPICAL PERFORMANCE PLOTS (continued)

T_A= 25°C, DAC sampling rate = 65 MSPS, single-tone IF = 1.1 MHz, two-tone IF = 1 MHz and 2 MHz, DVDD18 = 1.8 V,

CLKVDD18 = 1.8 V, DACVDD18 = 1.8 V, FUSEVDD18 = 1.8 V, IOVDD = 3.3 V, DACVDD33 = 3.3 V, MODVDD33 = 3.3 V,

analog output, unless otherwise noted

−25

−30

−35

−40

−45

−50

−25

−30

−35

−40

−45

−50

−40°C

25°C

85°C

3.15V

3.3V

3.45V

1000

2000

3000

4000

1000

2000

3000

4000

Frequency (MHz)

G011

G012

Figure 12. Unadjusted Carrier Feethrough vs LO Frequency

and Temperature

Figure 13. Unadjusted Carrier Feethrough vs LO Frequency

and Supply Voltage

−50

−40

−40°C

25°C

85°C

−40°C

25°C

85°C

−45

−55

−60

−65

−70

−75

−80

−85

−90

−50

−55

−60

−65

−70

−75

−80

−85

−90

900

920

940

960

980

1920

1940

1960

1980

2000

Frequency (MHz)

G013

G014

Figure 14. Adjusted Carrier Feethrough vs LO Frequency

and Temperature at 940 MHz

Figure 15. Adjusted Carrier Feethrough vs LO Frequency

and Temperature at 1960 MHz

−40

−40°C

25°C

85°C

−40°C

25°C

85°C

−45

−50

−55

−60

−65

−70

−75

−80

−50

−55

−60

−65

−70

−75

−80

−85

−90

2100

2120

2140

2160

2180

2460

2480

2500

2520

2540

Frequency (MHz)

G015

G016

Figure 16. Adjusted Carrier Feethrough vs LO Frequency

and Temperature at 2140 MHz

Figure 17. Adjusted Carrier Feethrough vs LO Frequency

and Temperature at 2500 MHz

11

AFE7070

ZHCSA89D – FEBRUARY 2012–REVISED JANUARY 2013

www.ti.com.cn

TYPICAL PERFORMANCE PLOTS (continued)

T_A= 25°C, DAC sampling rate = 65 MSPS, single-tone IF = 1.1 MHz, two-tone IF = 1 MHz and 2 MHz, DVDD18 = 1.8 V,

CLKVDD18 = 1.8 V, DACVDD18 = 1.8 V, FUSEVDD18 = 1.8 V, IOVDD = 3.3 V, DACVDD33 = 3.3 V, MODVDD33 = 3.3 V,

analog output, unless otherwise noted

−40

−40°C

25°C

85°C

−5dBm

0dBm

8dBm

−45

−50

−55

−60

−65

−70

−75

−80

−85

−90

50

40

30

20

3460

3480

3500

3520

3540

1000

2000

3000

4000

Frequency (MHz)

G017

G029

Figure 18. Adjusted Carrier Feethrough vs LO Frequency

and Temperature at 3500 MHz

Figure 19. Unadjusted Sideband Suppression vs LO

Frequency and LO Power

60

55

−40°C

3.15V

25°C

85°C

3.3V

3.45V

55

50

45

40

35

30

25

50

45

40

35

30

25

1000

2000

3000

4000

1000

2000

3000

4000

Frequency (MHz)

G028

G027

Figure 20. Unadjusted Sideband Suppression vs LO

Frequency and Temperature

Figure 21. Unadjusted Sideband Suppression vs LO

Frequency and Supply Voltage

90

80

−40°C

25°C

85°C

−40°C

25°C

85°C

85

80

75

70

65

60

55

50

75

70

65

60

55

50

45

40

900

920

940

960

980

1920

1940

1960

1980

2000

Frequency (MHz)

G018

G019

Figure 22. Adjusted Sideband Suppression vs LO

Frequency and Temperature at 940 MHz

Figure 23. Adjusted Sideband Suppression vs LO

Frequency and Temperature at 1960 MHz

12

AFE7070

www.ti.com.cn

ZHCSA89D – FEBRUARY 2012–REVISED JANUARY 2013

TYPICAL PERFORMANCE PLOTS (continued)

T_A= 25°C, DAC sampling rate = 65 MSPS, single-tone IF = 1.1 MHz, two-tone IF = 1 MHz and 2 MHz, DVDD18 = 1.8 V,

CLKVDD18 = 1.8 V, DACVDD18 = 1.8 V, FUSEVDD18 = 1.8 V, IOVDD = 3.3 V, DACVDD33 = 3.3 V, MODVDD33 = 3.3 V,

analog output, unless otherwise noted

90

85

80

75

70

65

60

55

50

45

40

90

85

80

75

70

65

60

55

50

45

40

−40°C

25°C

85°C

−40°C

25°C

85°C

2100

2120

2140

2160

2180

2460

2480

2500

2520

2540

Frequency (MHz)

G020

G021

Figure 24. Adjusted Sideband Suppression vs LO

Frequency and Temperature at 2140 MHz

Figure 25. Adjusted Sideband Suppression vs LO

Frequency and Temperature at 2500 MHz

85

70

−40°C

25°C

85°C

−40°C

25°C

85°C

80

75

70

65

60

55

50

45

40

35

65

60

3460

3480

3500

3520

3540

1000

2000

3000

4000

Frequency (MHz)

G022

G023

Figure 26. Adjusted Sideband Suppression vs LO

Frequency and Temperature at 3500 MHz

Figure 27. WCDMA Adjacent-Channel Power Ratio (ACPR)

vs Temperature

70

−40°C

25°C

85°C

3.15V

3.3V

3.45V

65

60

65

60

1000

2000

3000

4000

1000

2000

3000

4000

Frequency (MHz)

G024

G025

Figure 28. WCDMA Adjacent-Channel Power Ratio (Alt-

ACPR) vs Temperature

Figure 29. WCDMA Adjacent-Channel Power Ratio (ACPR)

vs Supply Voltage

13

AFE7070

ZHCSA89D – FEBRUARY 2012–REVISED JANUARY 2013

www.ti.com.cn

TYPICAL PERFORMANCE PLOTS (continued)

T_A= 25°C, DAC sampling rate = 65 MSPS, single-tone IF = 1.1 MHz, two-tone IF = 1 MHz and 2 MHz, DVDD18 = 1.8 V,

CLKVDD18 = 1.8 V, DACVDD18 = 1.8 V, FUSEVDD18 = 1.8 V, IOVDD = 3.3 V, DACVDD33 = 3.3 V, MODVDD33 = 3.3 V,

analog output, unless otherwise noted

70

65

60

−120

−125

−130

−135

−140

−145

3.15V

3.3V

3.45V

6 MHz Offset

30 MHz Offset

1000

2000

3000

4000

−20

−15

−10

−5

Frequency (MHz)

Digital Amplitude (dBFS)

G026

G030

Figure 30. WCDMA Adjacent-Channel Power Ratio (Alt-

ACPR) vs Supply Voltage

Figure 31. Noise Spectral Density (NSD) vs Input Power and

LO Frequency

−130

3.15V

3.3V

−135

−140

3.45V

−135

−140

3.15V

3.3V

3.45V

−145

1000

2000

3000

4000

1000

2000

3000

4000

Frequency (MHz)

G031

G032

Figure 32. Noise Spectral Density (NSD) at 6-MHz Offset vs

LO Frequency and Supply Voltage

Figure 33. Noise Spectral Density (NSD) at 30-MHz Offset vs

LO Frequency and Supply Voltage

−132

−137

−135

−140

−40°C

25°C

85°C

−142

−145

1000

2000

3000

4000

1000

2000

3000

4000

Frequency (MHz)

G033

G034

Figure 34. Noise Spectral Density (NSD) at 6-MHz Offset vs

LO Frequency and Temperature

Figure 35. Noise Spectral Density (NSD) at 30-MHz Offset

vs. LO Frequency and Temperature

14

AFE7070

www.ti.com.cn

ZHCSA89D – FEBRUARY 2012–REVISED JANUARY 2013

TYPICAL PERFORMANCE PLOTS (continued)

T_A= 25°C, DAC sampling rate = 65 MSPS, single-tone IF = 1.1 MHz, two-tone IF = 1 MHz and 2 MHz, DVDD18 = 1.8 V,

CLKVDD18 = 1.8 V, DACVDD18 = 1.8 V, FUSEVDD18 = 1.8 V, IOVDD = 3.3 V, DACVDD33 = 3.3 V, MODVDD33 = 3.3 V,

analog output, unless otherwise noted

−10

−20

−30

−40

−50

Filter tune = 0

Filter tune = 4

−60

Filter tune = 8

5

10

15

20

Baseband Frequency (MHz)

G035

Figure 36. Baseband Filter Response

15

AFE7070

ZHCSA89D – FEBRUARY 2012–REVISED JANUARY 2013

www.ti.com.cn

SERIAL INTERFACE

The serial port of the AFE7070 is a flexible serial interface which communicates with industry-standard

microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the

operating modes of the AFE7070. The serial port is compatible with most synchronous transfer formats and can

be configured as a 3- or 4-pin interface by sif_4pin in CONFIG3 (bit6). In both configurations, SCLK is the serial

interface input clock and SDENB is serial interface enable. For the 3-pin configuration, SDIO is a bidirectional pin

for both data in and data out. For the 4-pin configuration, SDIO is data-in only and ALARM_SDO is data-out

only. Data is input into the device with the rising edge of SCLK. Data is output from the device on the falling

edge of SCLK.

Each read/write operation is framed by signal SDENB (serial data-enable bar) asserted low for 2 to 5 bytes,

depending on the data length to be transferred (1–4 bytes). The first frame byte is the instruction cycle, which

identifies the following data transfer cycle as read or write, how many bytes to transfer, and the address to which

to transfer the data. Table 1 indicates the function of each bit in the instruction cycle and is followed by a detailed

description of each bit. Frame bytes 2 through 5 comprise the data transfer cycle.

Table 1. Instruction Byte of the Serial Interface

MSB

7

LSB

0

Bit

6

5

4

3

2

1

Description

R/W

N1

N0

A4

A3

A2

A1

A0

R/W

Identifies the following data transfer cycle as a read or write operation. A high indicates a read

operation from the AFE7070, and a low indicates a write operation to the AFE7070.

[N1 : N0]

Identifies the number of data bytes to be transferred, as listed in Table 2. Data is transferred MSB

first.

Table 2. Number of Transferred Bytes Within One Communication Frame

N1

0

N0

0

DESCRIPTION

Transfer 1 byte

Transfer 2 bytes

Transfer 3 bytes

Transfer 4 bytes

0

1

0

1

[A4 : A0]

Identifies the address of the register to be accessed during the read or write operation. For multi-

byte transfers, this address is the starting address. Note that the address is written to the

AFE7070 MSB first and counts down for each byte.

Figure 37 shows the serial interface timing diagram for an AFE7070 write operation. SCLK is the serial interface

clock input to AFE7070. Serial data enable SDENB is an active-low input to the AFE7070. SDIO is serial data in.

Input data to the AFE7070 is clocked on the rising edges of SCLK.

16

AFE7070

www.ti.com.cn

ZHCSA89D – FEBRUARY 2012–REVISED JANUARY 2013

Data Transfer Cycle(s)

Instruction Cycle

SDENB

SCLK

SDIO

r/w N1 N0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

(SDENB)

t_s

t _SCLK

SDENB

SCLK

SDIO

(SDIO)

t_h

t_SCLKHt_SCLKL

(SDIO)

t_s

Figure 37. Serial Interface Write Timing Diagram

Figure 38 shows the serial interface timing diagram for an AFE7070 read operation. SCLK is the serial interface

clock input to AFE7070. Serial data enable SDENB is an active-low input to the AFE7070. SDIO is serial data-in

during the instruction cycle. In the 3-pin configuration, SDIO is data-out from the AFE7070 during the data

transfer cycle(s), while ALARM_SDO is in a high-impedance state. In the 4-pin configuration, ALARM_SDO is

data-out from the AFE7070 during the data transfer cycle(s). At the end of the data transfer, ALARM_SDO

outputs low on the final falling edge of SCLK until the rising edge of SDENB, when it enters the high-impedance

state.

Data Transfer Cycle(s)

Instruction Cycle

SDENB

SCLK

SDIO

N1 N0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0

r/w

0

D7 D6 D5 D4 D3 D2 D1 D0

ALARM_SDO

4 pin configuration

output

3 pin configuration

output

SDENB

SCLK

SDIO

Data n

Data n-1

t (Data)

ALARM_SDO

d

Figure 38. Serial Interface Read Timing Diagram

17

AFE7070

ZHCSA89D – FEBRUARY 2012–REVISED JANUARY 2013

www.ti.com.cn

REGISTER DESCRIPTIONS

In the SIF interface there are three types of registers, NORMAL, READ_ONLY, and WRITE_TO_CLEAR. The

NORMAL register type allows data to be written and read from the register. All 8 bits of the data are registered at

the same time, but there is no synchronizing with an internal clock. All register writes are asynchronous with

respect to internal clocks. READ_ONLY registers only allow reading of the registers—writing to them has no

effect. WRITE_TO_CLEAR registers are just like NORMAL registers in that they can be written and read;

however, when the internal signals set a bit high in these registers, that bit stays high until it is written to 0. This

way, interrupts are captured and constant until dealt with and cleared.

Register Map

(MSB)

bit 7

(LSB)

bit 0

Name

Address Default

bit 6

div2_sync_ena

iqswap

bit 5

bit 4

bit 3

bit 2

bit 1

CONFIG0

CONFIG1

0x00

0x01

0x10

div2_dacclk_ena

twos

clkio_sel

clkio_out_ena_n

data_clk_sel

data_type

fifo_ena

sync_IorQ

daca_

complement

dacb_

complement

trim_clk_rc_fltr

lvds_clk_div

Alarm_fifo_

2away

CONFIG2

CONFIG3

0x02

0x03

0xXX

0x10

Unused

sif_4pin

Unused

SLEEP

Unused

SYNC

Unused

Alarm_fifo_1away

msb_out

alarm_or_sdo_

ena

TXENABLE

sync_sleep_txenable_sel

pd_clkrcvr_

mask

CONFIG4

CONFIG5

CONFIG6

0x04

0x05

0x06

0x0F

0x00

fuse_pd

offset_ena

pd_lvds

mixer_gain

qmc_corr_ena

pd_rf_out

pd_clkrcvr

mixer_ena

pd_dac

coarse_dac(3:0)

filter_tune(4:0)

pd_tf_out_

pd_dac_mask

mask

pd_analogout_

mask

pd_analogout

fifo_offset

pd_lvds_mask

alarm2away_

ena

alarm_1away_

ena

CONFIG7

0x07

0x13

mask_2away

mask_1away

fifo_sync_mask

CONFIG8

CONFIG9

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x00

0x7A

0xB6

0xEA

0x45

0x1A

0x16

0xAA

0xC6

0x24

0x02

0x00

0xXX

0x82

qmc_offseta (7:0)

qmc_offsetb (7:0)

CONFIG10

CONFIG11

CONFIG12

CONFIG13

CONFIG14

CONFIG15

CONFIG16

CONFIG17

CONFIG18

CONFIG19

CONFIG20

CONFIG21

CONFIG22

CONFIG23

CONFIG24

CONFIG25

CONFIG26

CONFIG27

CONFIG28

CONFIG29

CONFIG30

CONFIG31

qmc_offseta(12:8)

qmc_offsetb(12:8)

Unused

qmc_gaina (7:0)

qmc_gainb (7:0)

qmc_phase (7:0)

qmc_phase(9:8)

qmc_gaini(10:8)

qmc_gainq(10:8)

freq (7:0)

freq (15:8)

freq (23:16)

freq (31:24)

phase (7:0)

phase (15:8)

Reserved

titest_voh

titest_vol

Version(5:0)

18

AFE7070

www.ti.com.cn

ZHCSA89D – FEBRUARY 2012–REVISED JANUARY 2013

Register name: CONFIG0; Address: 0x00

BIT 7

BIT 0

div2_dacclk_ena

0

div2_sync_ena

0

clkio_sel

0

clkio_out_ena_n data_clk_sel

data_type

0

fifo_ena

0

sync_IorQ

0

1

0

Table 3. Clock Mode Memory Programming

Mode

div2_dacclk_ena

div2_sync_ena

clkio_sel

clkio_out_ena_n

data_clk_sel

Dual input clock(00)

1

0

1

0

1

0

1

0

1

0

1

Dual output clock (01)

Single differential DDR clock (10)

Single differential SDR clock (11)

div2_dacclk_ena: When set to 1, this enables the divide-by-2 in the DAC clock path. This must be set to 1

when in dual-input clock mode or dual-output clock mode.

div2_sync_ena:

When set to 1, the divide-by-2 is synchronized with the iq_flag. It is only useful in the dual-

clock modes when the divide-by-2 is enabled. Care must be take to ensure the input data

and DAC clocks are correctly aligned.

clkio_sel:

This bit is used to determine which clock is used to latch the input data. This should be set

according to Table 3.

clkio_out_ena_n:

data_clk_sel:

data_type:

When set to 0, the clock CLK_IO is an output. Depending on the mode, is should be set

according to Table 3.

This bit is used to determine which clock is used to latch the input data. This should be set

according to Table 3.

When asserted, the phase data is presented at the data interface. The phase data is then

updated with each clock. The phase register then holds the value of the I and Q data to be

used with the mix operation.

fifo_ena:

When asserted, the FIFO is enabled. Used in dual-input clock mode only. In all other

modes, the FIFO is bypassed.

sync_IorQ:

When set to 0, sync is latched on the I phase of the input clock. When set to 1, sync is

detected on the Q phase of the clock and is sent to the rest of the chip when the next I

data is presented.

19

AFE7070

ZHCSA89D – FEBRUARY 2012–REVISED JANUARY 2013

www.ti.com.cn

Register name: CONFIG1; Address: 0x01

BIT 7

BIT 0

twos

0

iqswap

0

trim_clk_rc_fltr

daca_complement

0

dacb_complement

0

lvds_clk_div

0

1

X

twos:

iqswap:

When asserted, the input to the chip is 2s complement, otherwise offset binary.

When asserted, the DACA data is driven onto DACB and reverse.

2 bits to trim the RC filter for LVDS out

trim_clk_rc_fltr:

daca_complement:

When asserted, the output to DACA is complemented. This allows the user of the chip

effectively to change the + and – designations of the PADs.

dacb_complement:

lvds_clk_div:

When asserted, the output to DACB is complemented. This allows the user of the chip

effectively to change the + and – designations of the PADs.

lvds_clk_div

LVDS Clock Division

00

01

10

11

2

4

1

20

AFE7070

www.ti.com.cn

ZHCSA89D – FEBRUARY 2012–REVISED JANUARY 2013

Register name: CONFIG2; Address: 0x02

Write-to-clear register bits remain asserted once set. Each bit must be written to 0 before another 1 can

be captured.

BIT 7

unused

0

BIT 0

unused

0

unused

0

unused

0

unused

0

unused

0

Alarm_fifo_2away

1

Alarm_fifo_1away

1

Alarm_fifo_2away: When asserted, the FIFO pointers are 2 away from collision. (WRITE_TO_CLEAR)

Alarm_fifo_1away: When asserted, the FIFO pointers are 1 away from collision. (WRITE_TO_CLEAR)

Register name: CONFIG3; Address: 0x03 (INTERFACE SELECTION)

BIT 7

BIT 0

alarm_or_sdo_ena

0

sif_4pin

0

SLEEP

0

TXenable

1

SYNC

0

sync_sleep_txenable_sel

msb_out

0

alarm_or_sdo_e When asserted, the output of the ALARM_SDO pin is enabled.

na:

sif_4pin:

When asserted, the part is in 4-pin SPI mode. The data-out is output on the ALARM_SDO

pin. If this bit is not enabled, the alarm signal is output on the ALARM_SDO pin.

sleep:

When asserted, all blocks programmed to go to sleep in CONFIG4 and CONFIG6 registers

labeled pd_***_mask are powered down.

TXenable:

sync:

When 0, the data path is zeroed. When 1, the device transmits.

When written with a 1, the part is synced. To be resynced using the sif register, it must be

reset to 0 by writing a 0 then write a 1 to the sif to sync.

sync_sleep_

txenable_sel:

This is used to define the function of the SYNC_SLEEP pin. This pin can be used for multiple

functions, but only one at a time. When it is set to control any one of the functions, all other

functions are controlled by writing their respective sif register bits.

sync_sleep_txenable

_sel

Pin controls

00

01

10

11

All controlled by sif bit

TXENABLE

SYNC

SLEEP

msb_out:

When set, and alarm_sdo_out_ena is also set, the ALARM_SDO pin outputs the value of

daca bit 13.

21

AFE7070

ZHCSA89D – FEBRUARY 2012–REVISED JANUARY 2013

www.ti.com.cn

Register name: CONFIG4; Address: 0x04

BIT 7

BIT 0

1

fuse_pd

0

mixer_gain

0

pd_clkrcvr

0

pd_clkrcvr_mask

0

coarse_dac(3:0)

1

fuse_pd:

When set to 1, the fuses are powered down. This saves approximately 50 µA at 1.8 V for

every intact fuse. The default value is 0.

mixer_gain:

When asserted, the complex mixer output is multiplied by 2. Only applied when the mixer is

enabled (mixer_ena = 1).

pd_clkrcvr:

When asserted, the clock receiver is powered down.

pd_clkrcvr_mask: When asserted, allows the clock receiver to be powered down with the SYNC_SLEEP pin or

sleep register bit.

coarse_dac:

DAC full-scale current control

Register name: CONFIG5; Address: 0x05

BIT 7

BIT 0

0

offset_ena

0

qmc_corr_ena

0

mixer_ena

0

filter_tune(4:0)

0

offset_ena:

When asserted, the qmc offset blk is enabled.

When asserted, the qmc correction is enabled.

qmc_corr_ena:

mixer_ena:

When asserted, the complex mix is performed. Otherwise, the mixer is bypassed.

Bits used to change the bandwidth of the analog filters

filter_tune(4:0):

Register name: CONFIG6; Address: 0x06

BIT 7

BIT 0

pd_lvds

pd_rf_out

0

pd_dac

0

pd_analogout

1

pd_lvds_mask pd_tf_out_mask pd_dac_mask pd_analogout_

mask

0

1

0

pd_lvds:

When asserted, the LVDS output stage is powered down.

When asserted, the RF output stage is powered down.

When asserted, DACs are powered down.

pd_rf_out:

pd_dac:

pd_analog_out:

When asserted, the entire analog circuit after the DACs (filters, modulator, LO input, RF

output stage, LVDS output) is powered down.

The following are used to determine what blocks are powered down when the SYNC_SLEEP pin is used or the

sleep register bit is set.

pd_lvds_mask:

pd_rf_out_mask: When asserted, allows the RF output to be powered down

pd_dac_mask: When asserted, allows the DACs to be powered down

When asserted, allows the LVDS to be powered down

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Register name: CONFIG7; Address: 0x07

BIT 7

BIT 0

mask_2away

0

mask_1away fifo_sync_mask

fifo_offset

0

alarm_2away_ena

1

alarm_1away_ena

1

0

1

0

mask_2away:

mask_1away:

fifo_sync_mask:

fifo_offset:

When set to 1, the ALARM_SDO pin is not asserted when the FIFO pointers are 2 away

from collision. The alarm still shows up in the CONFIG7 bits.

When set to 1, the ALARM_SDO pin is not asserted when the FIFO pointers are 1 away

from collision. The alarm still shows up in the CONFIG7 bits.

When set to 1, the sync to the FIFO is masked off. Sync does not then reset the pointers.

If the value is 0, when the sync is toggled the FIFO pointers are reset to the offset values.

Used to set the offset pointers in the FIFO. Programs the starting location of the output

side of the FIFO, allows the output pointer to be shifted from –4 to +3 (2s complement)

positions with respect to its default position when synced. The default position for the

output side pointer is 2. The input side pointer defaults to 0.

alarm_2away_ena: When asserted, alarms from the FIFO that represent the pointers being 2 away from

collision are enabled.

alarm_1away_ena: When asserted, alarms from the FIFO that represent the pointers being 1 away from

collision are enabled.

Register name: CONFIG8; Address: 0x08

BIT 7

BIT 0

qmc_offseta (7:0)

0

qmc_offseta(7:0):

Bits 7:0 of qmc_offseta. The complete registers qmc_offseta[12:0] and qmc_offsetb[12:0]

are updated when CONFIG8 is written, so CONFIG9, CONFIG10, and CONFIG11 should

be written before CONFIG8.

Register name: CONFIG9; Address: 0x09

BIT 7

BIT 0

0

qmc_offsetb (7:0)

0

1

0

1

qmc_offsetb(7:0):

Bits 7:0 of qmc_offsetb. The complete registers qmc_offseta[12:0] and qmc_offsetb[12:0]

are updated when CONFIG8 is written, so CONFIG9, CONFIG10, and CONFIG11 should

be written before CONFIG8.

Register name: CONFIG10; Address: 0x0A

BIT 7

BIT 0

Unused

0

qmc_offseta(12:8)

Unused

1

Unused

1

0

1

0

qmc_offsetb(12:8): Bits 12:8 of qmc_offseta. The complete registers qmc_offseta[12:0] and qmc_offsetb[12:0]

are updated when CONFIG8 is written, so CONFIG9, CONFIG10, and CONFIG11 should

be written before CONFIG8.

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Register name: CONFIG11; Address: 0x0B

BIT 7

BIT 0

Unused

0

qmc_offsetb(12:8)

Unused

0

Unused

1

0

1

qmc_offsetb(12:8):

Bits 12:8 of qmc_offsetb. The complete registers qmc_offseta[12:0] and

qmc_offsetb[12:0] are updated when CONFIG8 is written, so CONFIG9, CONFIG10, and

CONFIG11 should be written before CONFIG8.

Register name: CONFIG12; Address: 0x0C

BIT 7

BIT 0

1

qmc_gaina (7:0)

0

1

0

1

0

qmc_gaina(7:0):

Bits 7:0 of qmc_gaina. The complete registers qmc_gaina[10:0], qmc_gainb[10:0] and

qmc_phase[9:0] are updated when CONFIG12 is written, so CONFIG13, CONFIG14, and

CONFIG15 should be written before CONFIG12.

Register name: CONFIG13; Address: 0x0D

BIT 7

BIT 0

0

qmc_gainb (7:0)

0

1

0

qmc_gainb(7:0):

Bits 7:0 of qmc_gainb. The complete registers qmc_gaina[10:0], qmc_gainb[10:0] and

qmc_phase[9:0] are updated when CONFIG12 is written, so CONFIG13, CONFIG14, and

CONFIG15 should be written before CONFIG12.

Register name: CONFIG14; Address: 0x0E

BIT 7

BIT 0

0

qmc_phase (7:0)

0

1

0

1

qmc_phase(7:0)

Bits 7:0 of qmc_phase. The complete registers qmc_gaina[10:0], qmc_gainb[10:0] and

qmc_phase[9:0] are updated when CONFIG12 is written, so CONFIG13, CONFIG14, and

CONFIG15 should be written before CONFIG12.

Register name: CONFIG15; Address: 0x0F

BIT 7

BIT 0

0

qmc_phase(9:8)

qmc_gaina(10:8)

qmc_gainb(10:8)

1

0

1

0

1

0

qmc_phase(9:8):

qmc_gaina(10:8):

qmc_gainb(10:8):

Bits 9:8 of qmc_phase value

Bits 9:8 of qmc_gaina value

Bits 9:8 of qmc_gainb value

The complete registers qmc_gaina[10:0], qmc_gainb[10:0] and qmc_phase[9:0] are updated when CONFIG12

is written, so CONFIG13, CONFIG14, and CONFIG15 should be written before CONFIG12.

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Register name: CONFIG16; Address: 0x10

BIT 7

BIT 0

freq (7:0)

freq (15:8)

freq (23:15)

freq (31:24)

phase (7:0)

phase (15:8)

1

0

1

0

1

0

1

0

freq(7:0):

Bits 7:0 of frequency value

Register name: CONFIG17; Address: 0x11

BIT 7

BIT 0

0

1

freq (15:8):

Bits 15:8 of frequency value

Register name: CONFIG18; Address: 0x12

BIT 7

BIT 0

0

freq (23:15): Bits 23:15 of frequency value

Register name: CONFIG19; Address: 0x13

BIT 7

BIT 0

0

freq (31:24): Bits 31:24 of frequency value

Register name: CONFIG20; Address: 0x14

BIT 7

BIT 0

0

phase (7:0): Bits 7:0 of phase value

Register name: CONFIG21; Address: 0x15

BIT 7

BIT 0

0

phase (15:8):

Bits 15:8 of phase value

Register name: CONFIG22; Address: 0x16

BIT 7

BIT 0

0

nco__sync_sleep(7:0)

0

nco_sync_sleep(7:0):

Set to 11110000 to use the SYNC_SLEEP pin to update the NCO frequency value;

otherwise, set to 00000000. Note that register sync_sleep_txenable_sel in CONFIG3

must be set to 10 to use the SYNC_SLEEP pin as a SYNC input.

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Register name: CONFIG23; Address: 0x17

BIT 7

BIT 0

X

Reserved – Varies from device to device

X

0

X

1

Register name: CONFIG24; Address: 0x18

BIT 7

BIT 0

X

reserved – Varies from device to device

X

Register name: CONFIG25; Address: 0x19

BIT 7

BIT 0

X

Reserved – Varies from device to device

X

Register name: CONFIG26; Address: 0x1A

BIT 7

BIT 0

X

Reserved – Varies from device to device

X

Register name: CONFIG27; Address: 0x1B

BIT 7

BIT 0

X

Reserved – Varies from device to device

X

Register name: CONFIG28; Address: 0x1C

BIT 7

BIT 0

X

Reserved – Varies from device to device

X

Register name: CONFIG29; Address: 0x1D

BIT 7

BIT 0

X

Reserved – Varies from device to device

X

Register name: CONFIG30; Address: 0x1E

BIT 7

BIT 0

X

Reserved – Varies from device to device

X

0

X

0

Register name: CONFIG31; Address: 0x1F

BIT 7

BIT 0

0

titest_voh

1

titest_vol

0

Version(5:0)

0

titest_voh:

version:

Bit held high for sif test purposes

Bit held low for sif test purposes

Version of the chip

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PARALLEL DATA INPUT

The AFE7070 can input either complex I and Q data interleaved on D[13:0] at a data rate 2× the internal output

sample clock frequency, 16-bit NCO phase data interleaved as 8 MSBs and 8 LSBs on pins D[13:6] at a data

rate 2× the internal output sample clock frequency, or 14-bit NCO phase data at a data rate 1× the internal

output sample clock frequency. These modes are described in detail in the CLOCK MODES section.

CLOCK MODES

The AFE7070 has four clock modes for providing the DAC sample clock and data latching clocks.

Clock Mode

CLK_IO

FIFO

DataLatch

DACCLKFreqRatio

DataFormat

Progamming Bits

1× or 2× internal

sample clock

Dual-input clock

Input

Enabled

CLK_IO

IQ or phase (MSB/LSB)

2× internal sample

clock

Dual-output clock

Output

Disabled

Disables

CLK_IO

DACCLK

IQ or phase (MSB/LSB)

14-bit phase-only

See Table 3 in

CONFIG0 decription.

Single differential

DDR clock

1× internal sample

clock

Single differential

SDR clock

1× internal sample

clock

DUAL-INPUT CLOCK MODE

In dual-input clock mode, the user provides both a differential DAC clock at pins DACCLKP/N at 2× the internal

sample clock frequency and a second single-ended CMOS-level clock at CLK_IO for latching input data. The

DACCLK is divided by 2 internally to provide the internal output sample clock, with the phase determined by the

IQ_FLAG input. The IQ_FLAG signal can either be a repetitive high/low signal or a single event that is used to

reset the clock divider phase and identify the I sample.

CLK_IO is an SDR clock at the input data rate, or 2× the internal sample-clock frequency. The DAC clock and

data clock must be frequency locked, and a FIFO is used internally to absorb the phase difference between the

two clock domains. The phase relationship of CLK_IO and DACCLK can be any phase at the initial sync of the

FIFO, and thereafter can move up to ±4 clock cycles before the FIFO input and output pointers overrun and

cause data errors. In dual-input clock mode, the latency from input data to output samples is not controlled

because the FIFO can introduce a one-clock cycle variation in latency, depending on the exact phase

relationship between DACCLK and CLK_IO.

An external sync must be given on the SYNC_SLEEP pin to reset/initialize internal signal processing blocks.

Because the internal processing blocks process I and Q in parallel, the user can provide the sync signal during

either the I or Q input times (or both). Note that the internal sync signal must propagate through the input FIFO,

and therefore the latency of the sync updates of the signal processing blocks is not controlled.

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Dual Input Clock Mode (SDR)

DACCLKP

DACCLKN

Phase unconstrained (max +/- 4 clk after FIFO sync)

CLK_IO

(input)

t_st_h

D[13:0]

I

Q

I

Q

I

Q

IQ_FLAG

IQ

Identification

or

SYNC_SLEEP

or

Sync

(Initialization)

SYNC_SLEEP

Internal sync signal based on SYNC_SLEEP low to high, either I or Q

Internal sample clock phase based on IQ_FLAG

Internal

SYNC

Signal

Internal

Output

Sample

Clock

Output

waveform

Figure 39. Dual-Input Clock Mode

DUAL-OUTPUT CLOCK MODE

In dual-output clock mode, the user provides a differential DAC clock at pins DACCLKP/N at 2× the internal

sample clock frequency. The DACCLK is divided by 2 internally to provide the internal output sample clock, with

the phase determined by the IQ_FLAG input. The IQ_FLAG signal can either be a repetitive high/low signal or a

single event that is used to reset the clock divider phase and identify the I sample.

The AFE7070 outputs a single-ended CMOS-level clock at CLK_IO for latching input data. CLK_IO is an SDR

clock at the input data rate, or 2× the internal sample clock frequency. The CLK_IO clock can be used to drive

the input data source (such as digital upconverter) that sends the data to the DAC. Note that the CLK_IO delay

relative to the input DACCLK rising edge (t_d) in Figure 40) increases with increasing loads.

An external sync can be given on the SYNC_SLEEP pin to reset/initialize internal signal processing blocks.

Because the internal processing blocks process I and Q in parallel, the user can provide the sync signal during

either the I or Q input times (or both).

In the dual-output clock mode, the FIFO is bypassed, so the latency from the data input to the DAC output and

the time from sync input to update of the signal processing block are deterministic.

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DACCLKP

DACCLKN

t_d

CLK_IO

(output)

t_st_h

I

D[13:0]

Q

I

Q

I

Q

IQ_FLAG

or

IQ

Identification

IQ_FLAG

SYNC_SLEEP

or

Sync

(Initialization)

SYNC_SLEEP

Internal sync signal based on SYNC_SLEEP low to high, either I or Q

Internal sample clock phase based on IQ_FLAG

Internal

SYNC

Signal

Internal

Output

Sample

Clock

Output

waveform

Figure 40. Dual-Output Clock Mode Timing Diagram

SINGLE DIFFERENTIAL DDR CLOCK

In single differential DDR clock mode, the user provides a differential clock to DACCLKP/N at the internal output

sample clock frequency. The rising and falling edges of DACCLK are used to latch I and Q data, respectively.

The internal output sample clock is derived from DACCLKP/N.

An external sync can be given on the SYNC_SLEEP pin to reset/initialize internal signal processing blocks.

Because the internal processing blocks process I and Q in parallel, the user can provide the sync signal during

either the I or Q input times (or both).

In the single differential DDR clock mode, the FIFO is bypassed, so the latency from the data input to the DAC

output and the time from sync input to update of the signal processing block are deterministic.

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DACCLKP

DACCLKN

t_st_h

I

I on rising edge, Q on falling edge

D[13:0]

Q

I

Q

I

Q

SYNC_SLEEP

Sync

or

(Initialization)

SYNC_SLEEP

Internal sync signal based on SYNC_SLEEP low to high, either I or Q

Internal sample clock based on DACCLK/C

Internal

SYNC

Signal

Internal

Output

Sample

Clock

Output

waveform

Figure 41. Single Clock Mode Timing Diagram

SINGLE DIFFERENTIAL SDR CLOCK MODE

In single differential SDR clock mode, the user provides a differential clock to DACCLKP/N at 1× the internal

output sample clock frequency. This mode is only used for transferring 14-bit phase data, and therefore only

requires one data latching per internal output sample clock. The internal output sample clock is derived from

DACCLKP/N.

An external sync can be given on the SYNC_SLEEP pin to reset/initialize internal signal processing blocks.

In the single differential SDR clock mode, the FIFO is bypassed, so the latency from the data input to the DAC

output and the time from sync input to update of the signal processing block are deterministic.

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DACCLKP

DACCLKN

t_s

t_h

D[13:0]

P(0)

P(1)

P(2)

SYNC_SLEEP

Internal sample clock based on DACCLK/C

Internal

Output

Sample

Clock

Output

waveform

Figure 42. Single Differential SDR Clock Mode

FIFO ALARMS

The FIFO only operates when the write and read pointers are positioned properly. If either pointer over- or under-

runs the other, samples are duplicated or skipped. To prevent this, register CONFIG2 can be used to track two

FIFO-related alarms:

•

alarm_fifo_2away: Occurs when the pointers are within two addresses of each other

alarm_fifo_1away: Occurs when the pointers are within one address of each other

These two alarm events are generated asynchronously with respect to the clocks and can be accessed through

the ALARM_SDO pin by writing a 1 in register alarm_or_sdo_ena (CONFIG3[7]) and 0 in register sif_4pin

(CONFIG3[6]).

SYNCHRONIZATON

The AFE7070 has a synchonization input pin, SYNC_SLEEP, that is sampled by the same clock mode as the

input data to initialize signal processing blocks and optionally update NCO frequency and phase values. In the

case of dual input clock mode, the sync signal must propagate through the input FIFO, which creates an

uncertainty of ±1 clock cycle for the synchronization of the signal processing. In all other clock modes, the FIFO

is bypassed; therefore the exact time of the SYNC_SLEEP input to sync event is deterministic, and multiple

devices can be exactly synchronized.

The function of the pin SYNC_SLEEP is determined by register sync_sleep_txenable_sel in CONFIG3; setting to

10 configures the SYNC_SLEEP pin as a SYNC input.

QUADRATURE MODULATOR CORRECTION (QMC) BLOCK

The quadrature modulator correction (QMC) block provides a means for changing the phase balance of the

complex signal to compensate for I and Q imbalance present in an analog quadrature modulator. The block

diagram for the QMC block is shown in Figure 43. The QMC block contains three programmable parameters.

Registers qmc_gaina(10:0) and qmc_gainb(10:0) control the I and Q path gains and are 11-bit values with a

range of 0 to approximately 2.0. Register qmc_phase(9:0) controls the phase imbalance between I and Q and is

a 10-bit value with a range of –1/8 to approximately +1/8. LO feedthrough can be minimized by adjusting the

DAC offset feature described below.

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Figure 43. QMC Gain/Phase Block Diagram

The LO feedthrough can be minimized by adjusting the DAC offset. Registers qmc_offseta(12:0) and

qmc_offsetb(12:0) control the I and Q path offsets and are 13-bit values with a range of –4096 to 4095. The

DAC offset value adds a digital offset to the digital data before digital-to-analog conversion. The qmc_gaina and

qmc_gainb registers can be used to back off the signal before the offset to prevent saturation when the offset

value is added to the digital signal.

Figure 44. QMC Offset Block Diagram

NUMERICALLY CONTROLLED OSCILLATOR (NCO)

The AFE7070 contains a numerically controlled oscillator that can be used as either a data generation source or

to provide sin and cos for fully complex mixing with input data. The NCO has a 32-bit frequency register

freq(31:0) and a 16-bit phase register phase(15:0). The NCO tuning frequency is programmed in the CONFIG16

through CONFIG19 registers. Phase offset is programmed in the CONFIG20 and CONFIG21 registers. A block

diagram of the NCO is shown in Figure 45.

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Figure 45. Numerically Controlled Oscillator (NCO)

Synchronization of the NCO occurs by resetting the NCO accumulator to zero, which is described as follows.

Frequency word freq in the frequency register is added to the accumulator every clock cycle, f_DAC. The output

frequency of the NCO is

freq´f_{NCO_CLK}

f_NCO

=

2³²

(1)

With a complex input represented by I_IN(t) and Q_IN(t), the output of FMIX I_OUT(t) and Q_OUT(t) is

(mixer_gain - 1)

é

ù

t + d ´2

NCO

I_OUT(t) = I (t) cos 2pf

t + d - Q (t)sin 2p f

(

)

(

)

IN

NCO

IN

ë

û

(mixer_gain - 1)

é

ù

t + d ´2

NCO

Q_OUT(t) = I (t) sin 2pf

t + d + Q (t)cos 2p f

(

)

(

)

IN

NCO

IN

ë

û

(2)

where t is the time since the last resetting of the NCO accumulator, δ is the phase offset value, and mixer_gain

is either 0 or 1. δ is given by:

16

d = 2π ´ phase (15 : 0)/2

(3)

When register mixer_gain is set to 0, the gain through FMIX is sqrt(2)/2 or –3 dB. This loss in signal power is in

most cases undesirable, and it is recommended that the gain function of the QMC block be used to increase the

signal by 3 dB to compensate. With mixer_gain = 1, the gain through FMIX is sqrt(2) or 3 dB, which can cause

clipping of the signal if I_IN(t) and Q_IN(t) are simultaneously near full-scale amplitude and should therefore be used

with caution.

There are two methods to change the frequency and phase values in the NCO block.

1. Synchronous updating: To update the NCO frequency and phase using the SYNC_SLEEP pin,

sync_sleep_txenable_sel in the CONFIG3 register must be set to 10 and nco_sync_sleep in the CONFIG22

register must be set to 11110000 should be written to the CONFIG22 register. With these settings, the

frequency and phase register values only update the NCO frequency and phase values the pin

SYNC_SLEEP is raised, which allows precise control of when the frequency is updated. The accumulator is

not reset. There is a six-clock cycle latency from the time when the sync is clocked into the part until the new

frequency value is used in the calculation of the accumulator.

2. Non-synchronous updating: If the nco_sync_sleep register in CONFIG22 is set to 00000000, the frequency

register value updates the NCO frequency value when the lowest register bits freq(7:0) in CONFIG16 are

written. To assure updating with a complete frequency value, register bits freq(32:8) in CONFIG17,

CONFIG18, and CONFIG19 should be written before CONFIG16. Likewise, the phase register value updates

the NCO phase value when the lowest register bits phase(7:0) in CONFIG20 are written. To assure updating

with a complete phase value, register bits phase(15:8) in CONFIG21 should be written before CONFIG20.

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ANALOG OUTPUT MODE

The AFE7070 has two output modes. The analog output mode includes an an RF buffer amplifier and covers the

full frequency range of output frequency listed in the AC Electrical Characteristics table. The RF output should be

AC coupled and is intended to drive a 50-Ω load.

LVDS OUTPUT MODE

The AFE7070 provides an output mode where the modulator output is converted from an analog signal by a

comparator to a digital LVDS output signal. The RF output frequency in the LVDS output mode is limited to

frequencies below the specification listed in the AC Electrical Characteristics table.

The output includes options for frequency division of ÷1, ÷2 and ÷4 (Figure 46), set in register lvds_clk_div in

CONFIG1.

/1,2,4

LVDS P/N

Figure 46. LVDS Output Option

CMOS DIGITAL INPUTS

Figure 47 through Figure 50 show schematics of the equivalent CMOS digital inputs and outputs of the AFE7070.

All the CMOS digital inputs and outputs are relative to the IOVDD supply, which can vary from 1.8 V to 3.3 V.

This facilitates the I/O interface and eliminates the need of level translation. See the specification table for logic

thresholds. The pullup and pulldown circuitry is approximately equivalent to 100 kΩ.

IOVDD

25 W

ALARM_SDO

GND

Figure 47. CMOS Digital Equivalent Circuit for ALARM_SDO Output

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ZHCSA89D – FEBRUARY 2012–REVISED JANUARY 2013

IOVDD

800 W

67 kW

SDIO

GND

IOVDD

GND

Figure 48. CMOS Digital Equivalent Circuit for SDIO Bidirectional Input/Output

IOVDD

TESTMODE

DATA(13:0)

SCLK

SYNC_SLEEP

IQFLAG

800 W

67 kW

GND

Figure 49. CMOS Digital Equivalent Circuit for TESTMODE, DATA, SCLK, SYNC_SLEEP and IQFLAG

Inputs

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AFE7070

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IOVDD

67 kW

800 W

RESET

SDENB

GND

Figure 50. CMOS Digital Equivalent Circuit for RESET and SDENB Inputs

spacer

REVISION HISTORY

Changes from Original (February 2012) to Revision A

Page

•

Changed the TYPICAL PERFORMANCE PLOTS of the Product Preview data sheet ........................................................ 9

Changed the SERIAL INTERFACE of the Product Preview data sheet ............................................................................. 16

Changes from Revision A (July 2012) to Revision B

Page

•

Changed the device status From: Product Preview To: Production ..................................................................................... 1

Changes from Revision B (August 2012) to Revision C

Page

•

Added AFE7070IRGZ25 to AVAILABLE OPTIONS ............................................................................................................. 1

Changes from Revision B (October 2012) to Revision D

Page

•

Changed the TYP value of f_LO= 450 MHz, Analog Output noise floor From: 156 To: 143 .................................................. 7

36

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Apr-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

AFE7070IRGZR

VQFN

RGZ

48

2500

330.0

16.4

7.3

1.5

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Apr-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VQFN RGZ 48

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 43.0

AFE7070IRGZR

2500

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RGZ 48

7 x 7, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUADFLAT PACK- NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224671/A

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PACKAGE OUTLINE

RGZ0048D

VQFN - 1 mm max height

S

C

A

L

E

1

.

9

0

PLASTIC QUAD FLATPACK - NO LEAD

7.1

6.9

A

B

0.5

0.3

PIN 1 INDEX AREA

7.1

6.9

0.30

0.18

DETAIL

OPTIONAL TERMINAL

TYPICAL

1.0

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

5.6 0.1

2X 5.5

(0.2) TYP

13

24

44X 0.5

12

25

EXPOSED

THERMAL PAD

2X

49

SYMM

5.5

SEE TERMINAL

DETAIL

1

36

0.30

48X

0.18

37

48

PIN 1 ID

(OPTIONAL)

SYMM

0.1

C A B

0.5

0.3

48X

0.05

4219046/B 11/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RGZ0048D

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

5.6)

SYMM

48

37

48X (0.6)

1

36

48X (0.24)

6X

(1.22)

44X (0.5)

SYMM

10X

(1.33)

49

(6.8)

(R0.05)

TYP

(

0.2) TYP

VIA

25

12

13

24

10X (1.33)

6X (1.22)

(6.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:12X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219046/B 11/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RGZ0048D

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.665 TYP)

(1.33) TYP

16X ( 1.13)

37

48

48X (0.6)

49

36

1

48X (0.24)

44X (0.5)

(1.33)

TYP

(0.665)

TYP

SYMM

(6.8)

(R0.05) TYP

25

12

METAL

TYP

13

24

SYMM

(6.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 49

66% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:15X

4219046/B 11/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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型号：	AFE7070
厂家：	TEXAS INSTRUMENTS
描述：	集成 NCO、双通道 14 位 65MSPS DAC、射频 IQ 调制器和 LVDS 输出选项射频
文件：	总45页 (文件大小：2324K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AFE7070 [TI]

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