AFE88101 [TI]
适用于传感器和现场变送器应用的单通道、低功耗、16 位 DAC;
| 型号： | AFE88101 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于传感器和现场变送器应用的单通道、低功耗、16 位 DAC 传感器 |
| 文件： | 总87页 (文件大小：4365K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AFE78101, AFE88101
ZHCSP80 –DECEMBER 2022
具有电压基准和诊断ADC 的AFEx8101 16 位和14 位低功耗DAC，适用于4mA
至20mA 环路供电应用
1 特性
3 说明
• 提供功能安全
16 位 AFE88101 和 14 位 AFE78101 (AFEx8101) 是
具有电压输出的高度集成、高精度、极低功耗的数模转
换器(DAC)，专为传感器变送器应用而设计。
– 可帮助进行功能安全系统设计的文档：
AFE88101、AFE78101
• 低静态电流：170 µA（典型值）
• 16 位或14 位单调高性能DAC
AFEx8101 器件包含设计 4mA 至 20mA、2 线（环路
供电）传感器变送器所需的大多数元件。除了高精度
DAC 之外，这些器件还包括一个 10ppm/°C 电压基准
和一个诊断模数转换器 (ADC)。为了适应内在和功能
安全问题，需要进行外部电压至电流转换和功率调节。
– 1.8V 电源：0.15V 至1.25V，0.2V 至1.0V
– 5V 电源：0.3V 至2.5V，0.4V 至2.0V
– 16 位时为4-LSB INL
– 40°C 至+125°C 范围内的TUE 为0.07% FSR
（最大值）
内部诊断 ADC 多路复用为多个内部节点，可实现自动
自我运行状况检查。此检查能够检测内部偏置源、电源
稳压器、电压基准、DAC 输出、芯片温度和可选外部
电压源的错误或故障。如果从诊断 ADC、CRC 帧错误
校验或窗口化看门狗计时器检测到任何故障，这些器件
可以选择发出中断，进入与标准 NAMUR 输出值和/或
用户指定的自定义值相对应的失效防护状态。
• 可实现高级诊断的12 位3.84kSPS ADC
• 集成1.25V 基准电压，温漂为10ppm/°C
• 具有时钟输出的内部1.2288MHz 振荡器
• 数字接口：
– 串行外设接口(SPI)
– 通用异步接收器/发送器(UART)
• 故障检测：CRC 位错误检查、窗口式看门狗计时
器、诊断ADC
这些器件采用低至 1.71V 的电源供电，最大静态电流
为210µA。这些器件的额定工作温度范围为 –40°C 至
+125°C，但工作温度范围为–55°C 至+125°C。
• 宽工作温度范围：–55°C 至+125°C
器件信息
2 应用
封装(1)
器件型号
AFE78101
AFE88101
分辨率
• 2 线变送器
14 位
16 位
RRU (UQFN, 24)
4.00mm × 4.00mm
• 4mA 至20mA 环路供电应用
• 过程控制和工业自动化
• 智能发送器
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
• PLC 或DCS I/O 模块
IOVDD
ALARM
Alarm
PVDD
VDD
Internal
Diagnostics
Watchdog
Timer
IRQ (UARTOUT or SDO)
12-Bit ADC
AIN0
MUX
CRC Frame
Error Check
Diagnostics
POL_SEL/AIN1
Temperature
Sensor
CS
SDI
Alarm
Responses
SDO
SCLK
Output Buffer
Range Setting
User
Calibration
16-/14-Bit
DAC
VOUT
MUX
DAC Data
Register
UARTIN
Slew-Rate
Control
VREFIO
REF_EN
Internal
Reference
UARTOUT
RESET
Control Logic
Internal
Oscillator
CLK_OUT
SCLR
GND
REF_GND
功能方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLASF21
AFE78101, AFE88101
ZHCSP80 –DECEMBER 2022
www.ti.com.cn
Table of Contents
7.3 Feature Description...................................................23
7.4 Device Functional Modes..........................................44
7.5 Programming............................................................ 46
7.6 Register Maps...........................................................53
8 Application and Implementation..................................72
8.1 Application Information............................................. 72
8.2 Typical Application.................................................... 73
8.3 Initialization Set Up................................................... 79
8.4 Power Supply Recommendations.............................80
8.5 Layout....................................................................... 80
9 Device and Documentation Support............................82
9.1 Documentation Support ........................................... 82
9.2 接收文档更新通知..................................................... 82
9.3 支持资源....................................................................82
9.4 Trademarks...............................................................82
9.5 Electrostatic Discharge Caution................................82
9.6 术语表....................................................................... 82
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements................................................10
6.7 Timing Diagrams ...................................................... 11
6.8 Typical Characteristics: VOUT DAC......................... 12
6.9 Typical Characteristics: ADC.................................... 18
6.10 Typical Characteristics: Reference......................... 19
6.11 Typical Characteristics: Power Supply....................21
7 Detailed Description......................................................22
7.1 Overview...................................................................22
7.2 Functional Block Diagram.........................................22
Information.................................................................... 82
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
December 2022
*
Initial release.
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5 Pin Configuration and Functions
UARTIN
UARTOUT
NC
1
2
3
4
5
6
18
17
16
15
14
13
VOUT
PVDD
POL_SEL/AIN1
AIN0
SCLR
REF_EN
RESET
GND
VDD
Not to scale
图5-1. RRU (24-pin UQFN) Package, Top View
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
AIN0
15
AI
ADC input voltage. The input range is 0 V to VREF if PVDD = VDD, or 0 V to 2 × VREF if PVDD > 2.7 V.
Alarm notification. Open drain. When alarm condition is asserted, this pin is held to logic low; otherwise,
this pin is in a high-impedance state (Hi-Z).
ALARM
24
11
DO
DO
CLK_OUT
CS
Clock output. This pin can be configured as a clock output for the 1.2288‑MHz internal clock.
SPI chip-select. Data bits are clocked into the serial shift register when CS is logic low. When CS is logic
high, SDO is in a high-impedance state and data on SDI are ignored. Do not leave any digital input pins
floating.
10
14
DI
GND
GND
P
P
Digital and analog ground. Ground reference point for all circuitry on the device.
Digital and analog ground.
21,
22
Interface supply. Supply voltage for digital input and output circuitry. This voltage sets the logical
thresholds for the digital interfaces.
IOVDD
NC
12
P
3, 23
No connection. Leave floating.
–
ADC input voltage if SPECIAL_CFG.AIN1_ENB bit is set to 1. The input range is 0 V to VREF if PVDD =
POL_SEL/AIN1 16
DI/AI VDD, or 0 V to 2 × VREF if PVDD > 2.7 V. Otherwise, this pin acts as ALMV_POL, which sets the polarity
of the VOUT alarm voltage.
Power supply for the internal low-dropout regulator (LDO), ADC input, and VOUT DAC output. When
PVDD
17
5
P
2.7 V to 5.5 V is provided, the internal LDO turns on and drives VDD internally. When 1.71 V to 1.89 V is
provided, the internal LDO is disabled.
Internal VREF enable input. A logic high on this pin enables the internal VREF and the VREFIO pin
outputs 1.25 V. A logic low on this pin disables the internal VREF and the external 1.25-V reference is
required at the VREFIO pin.
REF_EN
DI
REF_GND
RESET
20
6
P
GND reference for VREFIO pin.
Reset. Logic low on this pin places the device into power-down mode and resets the device. Logic high
returns the device to normal operation. Do not leave any digital input pins floating.
DI
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表5-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
SCLK
SCLR
NO.
7
SPI serial clock. Data can be transferred at rates up to 12.5 MHz. SCLK is a Schmitt-trigger logic input.
Connect to GND or logic low if not used. Do not leave any digital input pins floating.
DI
DI
4
DAC clear input pin in SPI mode. A logic high on this pin forces the DAC output into a CLEAR state.
Connect to GND in UBM. Do not leave any digital input pins floating.
SPI data input. Data are clocked into the 24‑bit input shift register on the falling edge of the serial clock
SDI
8
9
DI
input. SDI is a Schmitt-Trigger logic input. Do not leave any digital input pins floating.
SPI data output. Data are output on the rising edge of SCLK when CS is logic low. Interrupt request (IRQ)
pin in the UART break mode (UBM). The output is in a Hi-Z state at power up and must be enabled in the
CONFIG register.
SDO
DO
UARTIN
1
2
DI
UART data input. Connect to IOVDD or logic high if not used. Do not leave any digital input pins floating.
UART data output. This pin can be configured to function as the IRQ pin in SPI only mode.
UARTOUT
DO
Power supply. When 2.7 V to 5.5 V is provided on PVDD pin, the internal LDO drives VDD internally.
Connect a 1‑μF to 10‑μF capacitor to this pin. When 1.71 V to 1.89 V is provided on the PVDD pin, an
external power supply must be provided on this pin.
VDD
13
18
19
P/AO
AO
VOUT
VREFIO
DAC output voltage.
When the internal VREF is enabled by REF_EN pin, this pin outputs the internal VREF voltage. In this
case, a load capacitance of 70-nF to 130-nF is required for stability. When disabled, this pin is the
external 1.25‑V reference input.
AI/AO
(1) AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–10
–55
–65
MAX
5.5
UNIT
V
PVDD, IOVDD to GND
VDD to GND
1.98
V
AIN0, POL_SEL/AIN1, VOUT to GND
PVDD + 0.3
IOVDD + 0.3
VDD + 0.3
0.3
V
Voltage
Digital Input/Output to GND
V
VREFIO to GND
V
REF_GND to GND
V
Input current
Current into any pin
10
mA
TJ
Junction temperature
Storage temperature
150
°C
Tstg
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
MAX
5.5
UNIT
PVDD > 2.7 V, VDD internally generated
PVDD = VDD
V
V
V
V
V
PVDD to GND
1.71
1.71
1.71
1.2
1.89
1.89
5.5
VDD to GND
IOVDD to GND
VREFIO to GND
External VREF
Specified
1.25
1.3
125
125
–40
–55
TA
Ambient temperature
°C
Operating
6.4 Thermal Information
AFEx8101
THERMAL METRIC(1)
RRU (UQFN)
24 PINS
103.1
84.4
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJC(bottom)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-case (bottom) thermal resistance
Junction-to-board thermal resistance
N/A
69.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.4
ΨJT
68.4
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
all minimum and maximum values at TA = –40°C to +125°C and all typical values at TA = 25°C, PVDD = VDD = IOVDD =
1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩto GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or
GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOUT DAC STATIC PERFORMANCE
AFE88101
AFE78101
AFE88101
AFE78101
16
14
Resolution
Bits
4
2
–4
INL
Integral nonlinearity(1)
LSB
LSB
–2
DNL
Differential nonlinearity(1)
1
–1
0.07
0.05
0.04
0.07
0.05
0.03
TA = –40°C to +125°C
TA = –40°C to +85°C
TA = 25°C
–0.07
–0.05
–0.04
–0.07
–0.05
–0.03
TUE
ZCE
Total unadjusted error(1)
Zero code error
%FSR
TA = –40°C to +125°C
TA = –40°C to +85°C
TA = 25°C
%FSR
ppm/°C
ZCE-TC Zero code error temperature coefficient
±3
±3
±3
0.07
0.05
0.03
TA = –40°C to +125°C
TA = –40°C to +85°C
TA = 25°C
–0.07
–0.05
–0.03
OE
Offset error(1)
%FSR
OE-TC
GE
Offset error temperature coefficient (1)
Gain error(1)
ppm/°C
0.04
0.04
0.03
TA = –40°C to +125°C
TA = –40°C to +85°C
TA = 25°C
–0.04
–0.04
–0.03
%FSR
GE-TC
FSE
Gain error temperature coefficient(1)
Full-scale error
ppm FSR/°C
%FSR
0.07
0.06
0.04
TA = –40°C to +125°C
TA = –40°C to +85°C
TA = 25°C
–0.07
–0.06
–0.04
FSE-TC Full-scale error temperature coefficient
±3
65
ppm FSR/°C
VOUT DAC DYNAMIC PERFORMANCE
¼ to ¾ scale and ¾ to ¼ scale settling to ±2 LSB,
PVDD = VDD = 1.8 V, VREFIO = 1.25 V
ts
Output voltage settling time(4)
Slew rate(4)
µs
10-mV step settling to ±2 LSB,
PVDD = VDD = 1.8 V, VREFIO = 1.25 V
30
2
SR
Vn
Fullscale transition measured from 10% to 90%
V/µs
0.1 Hz to 10 Hz, DAC at midscale,
PVDD = VDD = 1.8 V, VREFIO = 1.25 V
0.25
LSBPP
Output noise(4)
100-kHz bandwidth, DAC at midscale,
PVDD = VDD = 1.8 V, VREFIO = 1.25 V
32
180
260
85
µVrms
Measured at 1 kHz, DAC at midscale,
PVDD = VDD = 1.8 V, VREFIO = 1.25 V
Vn
Output noise density
nV/√Hz
Measured at 1 kHz, DAC at midscale,
PVDD = 5 V, VREFIO = 1.25 V
200-mV 50-Hz to 60-Hz sine wave superimposed on
power supply voltage, DAC at midscale.
Power supply rejection ratio (AC)
Code change glitch impulse
dB
Midcode ±1 LSB (including feedthrough)
PVDD = VDD = 1.8 V, VREFIO = 1.25 V
4.5
nV-s
Midcode ±1 LSB (including feedthrough)
PVDD = 5 V, VREFIO = 1.25 V
Code change glitch magnitude
Digital feedthrough
1.5
1
mV
At SCLK = 1 MHz, DAC output at midscale
nV-s
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6.5 Electrical Characteristics (continued)
all minimum and maximum values at TA = –40°C to +125°C and all typical values at TA = 25°C, PVDD = VDD = IOVDD =
1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩto GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or
GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOUT DAC OUTPUT CHARACTERISTICS
RANGE = 0, PVDD = VDD
0.15
0.2
1.25
1.0
RANGE = 1, PVDD = VDD
Output voltage range
V
RANGE = 0, PVDD > 2.7 V, VDD generated
RANGE = 1, PVDD > 2.7 V, VDD generated
PVDD > 2.7 V, VDD internally generated
PVDD = VDD
0.3
2.5
0.4
2.0
2.5
1.25
0.3
+6%
+6%
+5%
+5%
–6%
–6%
–5%
–5%
10
VOUT alarm output high
VOUT alarm output low
V
V
PVDD > 2.7 V, VDD internally generated
PVDD = VDD
0.15
RLOAD
CLOAD
Resistive load(2)
Capacitive load(2)
Load regulation
kΩ
pF
100
10
5
µV/mA
DAC at midscale, –1 mA ≤IOUT ≤+1 mA
Full scale output shorted to GND
Zero output shorted to VDD
Short-circuit current
mA
5
Output voltage headroom to PVDD
Output voltage footroom to GND
DAC at full code, IOUT = 1 mA (sourcing)
DAC at zero code, IOUT = 1 mA (sinking)
DAC at midscale
200
200
mV
mV
10
500
0.1
±5
mΩ
ZO
DC small signal output impedance
Output Hi-Z
kΩ
Power supply rejection ratio (dc)
DAC at midscale; PVDD = 1.8 V ± 10%
TA = 35°C, VOUT = midscale, ideal VREF
mV/V
ppm FSR
Output voltage drift vs time, 1000 hours
DIAGNOSTIC ADC
PVDD = VDD
PVDD > 2.7 V
0
0
1.25
2.5
Input voltage range
V
Resolution
12
±0.2
±1
Bits
LSB
LSB
LSB
%FSR
LSB
pF
DNL
INL
OE
Differential nonlinearity
Integral nonlinearity
Offset error
Specified 12-bit monotonic
After calibration
1
4
–1
–4
±1.6
±0.13
±4
10
0.8
–10
–0.8
GE
Gain error
Noise
Input capacitance
Input bias current
Acquisition time
Conversion time
Conversion rate
Temperature sensor accuracy
6
ADC not converting
50
3.84
nA
–50
52
µs
210
µs
kSPS
°C
5
INTERNAL OSCILLATOR
Frequency
1.2165
1.2288
1.2411
MHz
TA = –40°C to +125°C
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6.5 Electrical Characteristics (continued)
all minimum and maximum values at TA = –40°C to +125°C and all typical values at TA = 25°C, PVDD = VDD = IOVDD =
1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩto GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or
GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE REFERENCE INPUT
RANGE = 0
RANGE = 1
125
180
100
ZVREFIO Reference input impedance (VREFIO)
kΩ
CVREFIO Reference input capacitance (VREFIO)
VOLTAGE REFERENCE OUTPUT
Output (initial accuracy)(3)
Output drift(3)
pF
TA = 25°C
1.248
1.25
1.252
10
V
TA = –40°C to +125°C
ppm/℃
Output impedance(3)
0.1
7.5
200
2.5
Ω
Output noise(3)
0.1 Hz to 10 Hz
µVPP
Output noise density(3)
Measured at 10 kHz, reference load = 100 nF
Sourcing, 0.1% VREF change from nominal
Sinking, 0.1% VREF change from nominal
Sourcing, 0 mA to 2.5 mA
nV/√Hz
Load current(3)
mA
0.3
Load regulation(3)
4
µV/mA
nF
TA = –40°C to +125°C,
ESR from 10 mΩ to 400 mΩ
COUT
Stable output capacitance
70
100
130
Line regulation(3)
80
±100
500
25
µV/V
ppm
µV
Output voltage drift vs time(3)
TA = 35°C, 1000 hours
1st cycle
Thermal hysteresis(3)
Additional cycles
µV
VDD VOLTAGE REGULATOR OUTPUT
Output voltage
1.71
1.8
3
1.89
V
Output impedance(3)
PVDD = 3.3 V, sourcing, 0.5 mA to 2.5 mA
Ω
PVDD = 3.3 V, sourcing, 1% VDD change from
nominal
Load current(3)
4
mA
THERMAL ALARM
Alarm trip point
130
85
12
5
°C
°C
°C
°C
°C
Warning trip point
Hysteresis
Trip point absolute accuracy
Trip point relative accuracy
DIGITAL INPUT CHARACTERISTICS
2
VIH
VIL
High-level input voltage
Low-level input voltage
Hysteresis voltage
Input current
0.7
V/IOVDD
V/IOVDD
V/IOVDD
nA
0.3
0.05
400
–400
Pin capacitance
Per pin
10
10
pF
DIGITAL OUTPUT CHARACTERISTICS
VOH
VOL
VOL
High-level output voltage
Low-level output voltage
ISOURCE = 1 mA
ISINK = 1 mA
ISINK = 2 mA
0.8
V/IOVDD
V/IOVDD
V
0.2
0.3
Open-drain low-level output voltage
Output pin capacitance
pF
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6.5 Electrical Characteristics (continued)
all minimum and maximum values at TA = –40°C to +125°C and all typical values at TA = 25°C, PVDD = VDD = IOVDD =
1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩto GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or
GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER REQUIREMENTS
PVDD only, VDD internally generated, DAC at zero-
scale, ADC and SPI static, internal reference
170
210
45
IPVDD
Current flowing into PVDD
µA
Shared PVDD and VDD connection, DAC at zero-
scale, ADC and SPI static
32
8
ILDO
IVDD
VDD LDO quiescent current
Current flowing into VDD
From PVDD
µA
µA
Shared PVDD and VDD connection, DAC at zero-
scale, ADC and SPI static, internal reference
130
160
70
IREFIO
IADC
Internal reference current consumption
ADC current consumption
From external or internally generated VDD
From PVDD, ADC converting at 3.84 kSPS
52
10
µA
µA
µF
µA
µA
CVDD
IIOVDD
IVREFIO
Recommended VDD decoupling capacitance
Current flowing into IOVDD
1
10
20
SPI static
5
Current flowing into VREFIO
0.15-V to 1.25-V range, midscale code
10
(1) End point fit between code 0 to code 65,535 for 16-bit, code 0 to code 16,383 for 14-bit, DAC output unloaded, performance under
resistive and capacitive load conditions are specified by design and characterization.
(2) Not production tested.
(3) Derived from the characterization data.
(4) Output buffer gain (G) = 2, PVDD > 2.7 V.
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6.6 Timing Requirements
all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2, 2.7 V ≤PVDD ≤5.5 V,
VIH = 1.62 V, VIL = 0.15 V, VREFIO = 1.25 V, and TA = –40°C to +125°C (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
SERIAL INTERFACE - WRITE AND READ OPERATION
fSCLK
Serial clock frequency
12.5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCLKHIGH
tSCLKLOW
tCSHIGH
tCSS
SCLK high time
36
36
80
30
30
30
5
SCLK low time
CS high time
CS to SCLK falling edge setup time
SCLK falling edge to CS rising edge
CS rising edge to SCLK falling edge ignore
SCLK falling edge ignore to CS falling edge
SDI setup time
tCSH
tCSRI
tCSFI
tSDIS
5
tSDIH
SDI hold time
5
tSDOZD
tSDODZ
tSDODLY
UART
tBAUD
CS falling edge to SDO tri-state condition to driven
CS rising edge to SDO driven to tri-state condition
SCLK to SDO output delay
40
40
40
Baud rate = 9600 ± 1%
104
µs
DIGITAL LOGIC
tDACWAIT
tPOR
Sequential DAC update wait time
POR reset delay
2.1
µs
µs
ns
µs
100
tRESET
tRESETWAIT
RESET pulse duration
100
10
Wait time after RESET pulse
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6.7 Timing Diagrams
tCSS
tCSHIGH
tCSH tCSRI
tCSFI
CS
tSCLKHIGH
SCLK
SPI Mode 2
tSCLKLOW
Continuous
SCLK
Clock Mode
SPI Mode 1
tSDIS
tSDIH
Discontinuous
Clock Mode
SDI
Bit N
Bit 0
Bit 1
tSDODLY
tSDODZ
Bit 0
SDO
FSDO = 0
Bit N
tSDOZD
Bit 1
tSDODLY
Bit 1
SDO
FSDO = 1
Bit 0
Bit N
N = 31 for 32-bit frame with CRC
N = 23 for 24-bit frame without CRC
Don’t Care
Hi-Z
Valid Data
图6-1. SPI Timing
tBAUD
11 • tBAUD
S = Start bit, Par = Parity bit, P = Stop bit
S
D0
D1
D2
D3
D4
D5
D6
D7 Par
P
S
D0
D1
D2
D3
D4
D5
D6
D7 Par
P
S
UART Break Character
UART Communication
图6-2. UBM Timing
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6.8 Typical Characteristics: VOUT DAC
at TA = 25°C, PVDD = VDD = IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩto GND, CLOAD = 100 pF
to GND, and digital inputs at IOVDD or GND (unless otherwise noted)
图6-3. DAC DNL vs Digital Input Code
图6-4. DAC DNL vs Digital Input Code
图6-5. DAC INL vs Digital Input Code
图6-6. DAC INL vs Digital Input Code
图6-8. MIN and MAX DAC INL Range vs Temperature
图6-7. MIN and MAX DAC DNL Range vs Temperature
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6.8 Typical Characteristics: VOUT DAC (continued)
at TA = 25°C, PVDD = VDD = IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩto GND, CLOAD = 100 pF
to GND, and digital inputs at IOVDD or GND (unless otherwise noted)
图6-9. DAC TUE vs Digital Input Code
图6-10. DAC TUE vs Digital Input Code
图6-12. DAC RESET Response
图6-11. MIN and MAX DAC TUE vs Temperature
RANGE = 0
RANGE = 1
图6-13. DAC Source and Sink Current Capability
图6-14. DAC Source and Sink Current Capability
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6.8 Typical Characteristics: VOUT DAC (continued)
at TA = 25°C, PVDD = VDD = IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩto GND, CLOAD = 100 pF
to GND, and digital inputs at IOVDD or GND (unless otherwise noted)
图6-15. DAC Gain Error vs Temperature
图6-16. DAC Offset Error vs Temperature
图6-17. DAC Full Scale Error vs Temperature
图6-18. DAC Zero Scale Error vs Temperature
DAC at midcode
DAC at midcode
图6-20. DAC Output Noise Density vs Frequency
图6-19. DAC Output Noise, 0.1 Hz to 10 Hz
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6.8 Typical Characteristics: VOUT DAC (continued)
at TA = 25°C, PVDD = VDD = IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩto GND, CLOAD = 100 pF
to GND, and digital inputs at IOVDD or GND (unless otherwise noted)
图6-21. DAC Settling Time vs Load (Rising Voltage Step)
图6-22. DAC Settling Time vs Load (Falling Voltage Step)
图6-23. DAC Settling Time With Linear Slew Rate Control
图6-24. DAC Settling Time With Sinusoidal Slew Rate Control
图6-25. DAC Glitch Impulse Rising Edge
图6-26. DAC Glitch Impulse Falling Edge
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6.8 Typical Characteristics: VOUT DAC (continued)
at TA = 25°C, PVDD = VDD = IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩto GND, CLOAD = 100 pF
to GND, and digital inputs at IOVDD or GND (unless otherwise noted)
图6-27. DAC Supply Power On, PVDD = 1.8 V
图6-28. DAC Supply Power On, PVDD = 3.3 V
1: 0.4-V to 2-V range, midcode
2: 0.2-V to 1-V range, midcode
3: 0.3-V to 2.2-V range,
zero code
0.15-V to 1.25-V range, midcode
图6-29. DAC PVDD Supply Collapse Response, RANGE = 1
图6-30. DAC PVDD Supply Collapse Response, RANGE = 0
0.15-V to 1.25-V range, midcode
0.4-V to 2-V range, midcode
图6-31. DAC VDD Supply Collapse Response,
图6-32. DAC IOVDD Supply Collapse Response, RANGE = 1
RANGE = 0
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6.8 Typical Characteristics: VOUT DAC (continued)
at TA = 25°C, PVDD = VDD = IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩto GND, CLOAD = 100 pF
to GND, and digital inputs at IOVDD or GND (unless otherwise noted)
Internal Reference
图6-34. DAC AC PSRR vs Frequency
Ideal reference
图6-33. DAC Output Voltage Long-Term Stability
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6.9 Typical Characteristics: ADC
at TA = 25°C, PVDD = VDD = IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩto GND, CLOAD = 100 pF
to GND, and digital inputs at IOVDD or GND (unless otherwise noted)
图6-35. ADC DNL vs Digital Input Code
图6-36. ADC INL vs Digital Input Code
图6-38. ADC INL Range vs Temperature
图6-37. ADC DNL Range vs Temperature
图6-39. ADC Offset Error vs Temperature
图6-40. ADC Gain Error vs Temperature
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6.10 Typical Characteristics: Reference
at TA = 25°C, PVDD = IOVDD = 3.3 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩto GND, CLOAD = 100 pF to
GND, and digital inputs at IOVDD or GND (unless otherwise noted)
Pre-soldered
图6-41. Reference Voltage Temperature Drift
Post-soldered
图6-42. Reference Voltage Temperature Drift
–40°C to +85°C cycles, 60 minutes per cycle
图6-44. Multiple Temperature Cycle Hysteresis
–40°C to +85°C cycles, 60 minutes per cycle
图6-43. Multiple Temperature Cycle Hysteresis
Two minutes after 25°C to 85°C temperature step
图6-45. Ambient Temperature Change Settling
图6-46. Reference Voltage Long-Term Stability
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6.10 Typical Characteristics: Reference (continued)
at TA = 25°C, PVDD = IOVDD = 3.3 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩto GND, CLOAD = 100 pF to
GND, and digital inputs at IOVDD or GND (unless otherwise noted)
图6-47. Reference Output Noise, 0.1 Hz to 10 Hz
图6-48. Reference AC PSRR vs frequency
图6-50. Initial Accuracy Distribution
图6-49. Reference Source and Sink Current Capability
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6.11 Typical Characteristics: Power Supply
at TA = 25°C, PVDD = IOVDD = 3.3 V, internal VREFIO, RLOAD = 50 kΩto GND, CLOAD = 100 pF to GND, and digital inputs
at IOVDD or GND (unless otherwise noted)
图6-51. PVDD Supply Current vs Temperature
图6-52. IOVDD Supply Current vs Temperature
图6-53. VDD Voltage vs Load Current
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7 Detailed Description
7.1 Overview
The AFEx8101 feature a 16-bit (AFE88101) or 14‑bit (AFE78101) string DAC with voltage output buffer. Both
devices are capable of operating from supplies as low as 1.71 V at very low power, and are designed for 4-mA to
20-mA, loop-powered applications. The AFEx8101 have two different DAC output voltage ranges depending on
supply voltage, and two other ranges depending on configuration. The DAC has calibration registers for setting
gain and offset values for adjusting the DAC outputs. The DAC also has different output slewing modes that
allow for a programmable linear slew and a sinusoidal shaped output slew.
The AFEx8101 also feature a 12‑bit SAR ADC that can be multiplexed to measure different inputs, including
external nodes and internal nodes for diagnostic measurements on the device. The ADC is capable of making
direct-mode measurements with on-demand conversions or auto-mode measurements through continuous
conversions using a channel sequencer with a multiplexer. The devices have optional alarm configurations with
fault detection and alarm actions.
Device communication and programming are done through an SPI or through the UART break mode (UBM).
With the SPI, a cyclic redundancy check (CRC) is implemented by default, which can be disabled. Additionally,
communications can be monitored with a watchdog timer (WDT) that alerts the user if the device becomes
unresponsive to periodic communication.
The AFEx8101 feature a 1.25-V, onboard precision voltage reference, and an integrated precision oscillator.
Throughout this data sheet, register and bit names are combined with a period to use the following format:
<register_name>.<bit_name>. For example, the CLR bit in the DAC_CFG register is labeled DAC_CFG.CLR.
7.2 Functional Block Diagram
IOVDD
ALARM
Alarm
PVDD
VDD
Internal
Diagnostics
Watchdog
Timer
IRQ (UARTOUT or SDO)
12-Bit ADC
AIN0
MUX
CRC Frame
Error Check
Diagnostics
POL_SEL/AIN1
Temperature
Sensor
CS
SDI
Alarm
Responses
SDO
SCLK
Output Buffer
Range Setting
User
Calibration
16-/14-Bit
DAC
VOUT
MUX
DAC Data
Register
UARTIN
Slew-Rate
Control
VREFIO
REF_EN
Internal
Reference
UARTOUT
RESET
Control Logic
Internal
Oscillator
CLK_OUT
SCLR
GND
REF_GND
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7.3 Feature Description
7.3.1 Digital-to-Analog Converter (DAC) Overview
The AFEx8101 feature a 16‑bit (AFE88101) or 14-bit (AFE78101) string DAC followed by an output voltage
buffer. The DAC can be configured to support two low PVDD (0.15 V to 1.25 V and 0.2 V to 1 V), or high PVDD
(0.3 V to 2.5 V and 0.4 V to 2 V) output ranges of operation depending on the PVDD supply voltage and the
DAC_CFG.RANGE bit in the device configuration register. Using a voltage-to-current converter stage, these
output voltages can be used to control a 4 mA to 20 mA loop. The narrow range corresponds to a 4-mA to 20-
mA range. The full range allows for currents under and over the 4-mA to 20-mA range.
The devices continuously monitor the PVDD supply to provide proper operation based on the DAC range setting.
表7-1 shows the valid supply ranges and corresponding VOUT DAC voltage ranges for the AFEx8101.
表7-1. VOUT DAC Voltage Ranges
SUPPLY
DAC
CONFIGURATION
VOUT DAC
VOLTAGE RANGE
DAC_CFG.RANGE
NAME
PVDD
VDD
Invalid configuration
NA
0
Alarm condition(1)
Full range
0.15 V or 1.25 V(2)
0.15 V to 1.25 V
0.2 V to 1 V
0 V ≤PVDD < 1.71 V
0 V ≤VDD < 1.71 V
Low PVDD DAC
range
1.71 V ≤PVDD ≤1.89
1.71 V ≤VDD ≤1.89 V
V
1
Narrow range
Alarm condition(1)
Full range
Invalid configuration 1.89 V < PVDD < 2.7 V
VDD > 1.89 V
NA
0
0.15 V or 1.25 V(2)
0.3 V to 2.5 V
High PVDD DAC
2.7 V ≤PVDD ≤5.5 V
range
VDD is internally
generated
1
Narrow range
Alarm condition(1)
0.4 V to 2 V
Invalid configuration
PVDD > 5.5 V
VDD > 1.89 V
NA
0.3 V or 2.5 V(2)
(1) See 表7-7 for details.
(2) See 图7-12 for details.
If PVDD or VDD fall outside the specified threshold values associated with the supply configuration during
operation, an alarm is generated and the DAC output is set according to the ALARM_ACTION setting.
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7.3.1.1 DAC Resistor String
图 7-1 shows that the resistor string structure consists of a series of resistors, each of value R. The code loaded
to the DAC determines the node on the string at which the voltage is tapped off to be fed into the output
amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. The
resistor string architecture has inherent monotonicity, voltage output, and low glitch.
R
R
To Output
Amplifier
R
R
R
图7-1. DAC Resistor String
7.3.1.2 DAC Buffer Amplifier
The VOUT output pin is driven by the DAC output buffer amplifier. The output amplifier default settings are
designed to drive capacitive loads as high as 100 pF without oscillation. The output buffer is able to source and
sink 1 mA. The device implements short-circuit protection for momentary output shorts to ground and VDD
supply. The source and sink short-circuit current thresholds are set to 5 mA.
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7.3.1.3 DAC Transfer Function
The following equation describes the DAC transfer function, which is the relationship between internal signal
DAC_CODE and output voltage VOUT:
DAC_CODE
VOUT =
× FSR + V
(1)
MIN
N
2
where
• DAC_CODE is an internal signal and the decimal equivalent of the gain and offset calibrated binary code
loaded into the DAC_DATA register. DAC_CODE range = 0 to 2N –1.
• N = DAC_CODE resolution in bits (16 for the AFE88101 and 14 for the AFE78101).
• FSR = VOUT full-scale range for the selected output range in 表7-2.
• VMIN = the lowest voltage for the selected DAC output range.
表7-2. FSR and VMIN for all VOUT Ranges
PVDD
1.8 V
DAC_CFG.RANGE
VOUT RANGE
0.15 V to 1.25 V
0.2 V to 1.0 V
0.3 V to 2.5 V
0.4 V to 2.0 V
FSR
1.1 V
0.8 V
2.2 V
1.6 V
VMIN
0.15 V
0.2 V
0.3 V
0.4 V
0
1
0
1
1.8 V
≥2.7 V
≥2.7 V
The VOUT range for the DAC is determined by DAC_CFG.RANGE bit when not in the CLEAR state. In the
CLEAR state, the range is determined by DAC_CFG.CLR_RANGE bit.
7.3.1.4 DAC Gain and Offset Calibration
The AFEx8101 provide DAC gain and offset calibration capability to correct for end-point errors present in the
system. Implement the gain and offset calibration using two registers, DAC_GAIN.GAIN and
DAC_OFFSET.OFFSET. Update DAC_DATA register after gain or offset codes are changed for the new values
to take effect. The DAC_GAIN can be programmed from 0.5 to 1.499985 using 方程式2.
1
2
GAIN
DAC_GAIN =
+
(2)
N
2
where
• N = DAC_GAIN resolution in bits: 16 for the AFE88101 and 14 for the AFE78101.
• GAIN is the decimal value of the DAC_GAIN register setting.
• GAIN data are left justified; the last two LSBs in the DAC_GAIN register are ignored for the AFE78101.
The example DAC_GAIN settings for the AFE88101 are shown in 表7-3.
表7-3. DAC_GAIN Setting vs GAIN Code
DAC_GAIN
0.5
GAIN (HEX)
0x0000
1.0
0x8000
1.499985
0xFFFF
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The DAC_OFFSET is stored in the DAC_OFFSET register using 2's-complement encoding. The DAC_OFFSET
value can be programmed from –2(N–1) to 2(N–1) –1 using 方程式3.
N − 2
i = 0
N − 1
i
DAC_OFFSET = − OFFSET
× 2
+ ∑
OFFSET × 2
(3)
MSB
i
where
• N = DAC_OFFSET resolution in bits: 16 for the AFE88101 and 14 for the AFE78101.
• OFFSETMSB = MSB bit of the DAC_OFFSET register.
• OFFSETi = The rest of the bits of the DAC_OFFSET register.
• i = Position of the bit in the DAC_OFFSET register.
• OFFSET data are left justified; the last two LSBs in the DAC_OFFSET register are ignored for the device.
The most significant bit determines the sign of the number and is called the sign bit. The sign bit has the weight
of –2(N–1) as shown in 方程式3.
The example DAC_OFFSET settings for the AFE88101 are shown in 表7-4.
表7-4. DAC_OFFSET Setting vs OFFSET Code
DAC_OFFSET
OFFSET (HEX)
0x7FFF
32767
1
0
0x0001
0x0000
0xFFFF
–1
0xFFFE
0x8000
–2
–32768
The following transfer function is applied to the DAC_DATA.DATA based on the DAC_GAIN and DAC_OFFSET
values:
DAC_CODE = DATA × DAC_GAIN + DAC_OFFSET
(4)
where
• DAC_CODE is the internal signal applied to the DAC.
• DATA is the decimal value of the DAC_DATA register.
• DAC_GAIN and DAC_OFFSET are the user calibration settings.
• DATA data are left justified; the last two LSBs in the DAC_DATA register are ignored for the AFE78101.
Substituting DAC_GAIN and DAC_OFFSET in 方程式4 with 方程式2 and 方程式3 results in:
N − 2
i = 0
1
2
GAIN
N − 1
i
DAC_CODE = DATA ×
+
− OFFSET
× 2
+ ∑
OFFSET × 2
(5)
MSB
i
N
2
The multiplier is implemented using truncation instead of rounding. This truncation can cause a difference of one
LSB if rounding is expected. 图7-2 shows the DAC calibration path.
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+
DAC_DATA
Register 01h
DAC_CODE
+
DAC_GAIN
Register 04h
DAC_OFFSET
Register 05h
Gain = ½ + DAC_GAIN / 216 Offset in 2’s-complement
< 8000h: Gain < 1
= 8000h: Gain = 1
> 8000h: Gain > 1
< 0000h: Negative offset
0000h: No offset
> 0000h: Positive offset
图7-2. DAC Calibration Path
7.3.1.5 Programmable Slew Rate
The slew rate feature controls the rate at which the output voltage or current changes. This feature is disabled by
default and is enabled by writing a logic 1 to the DAC_CFG.SR_EN bit. With the slew rate control feature
disabled, the output changes smoothly at a rate limited by the output drive circuitry and the attached load.
With this feature enabled, the output does not slew directly between the two values. Instead, the output steps
digitally at a rate defined by DAC_CFG.SR_STEP[2:0] and DAC_CFG.SR_CLK[2:0]. SR_CLK defines the rate at
which the digital slew updates. SR_STEP defines the amount by which the output value changes at each
update. 节7.6.1 shows different settings for SR_STEP and SR_CLK.
The time required for the output to slew is expressed as 方程式6:
Delta Code Change
Slew Step × Slew Clock Rate
Slew Time =
(6)
where
• Slew Time is expressed in seconds
• Slew Step is controlled by DAC_CFG.SR_STEP
• Slew Clock Rate is controlled by DAC_CFG.SR_CLK
When the slew-rate control feature is enabled, the output changes at the programmed slew rate. This
configuration results in a staircase formation at the output. If the clear code is asserted (see 节 7.3.1.6), the
output slews to the DAC_CLR_CODE value at the programmed slew rate. When new DAC data are written, the
output starts slewing to the new value at the slew rate determined by the current DAC code and the new DAC
data. The update clock frequency for any given value is the same for all output ranges. The step size, however,
varies across output ranges for a given value of step size because the LSB size is different for each output
range.
Two slew-rate control modes are available: linear (default) and sinusoidal. 图 7-3 and 图 7-4 show the typical
rising and falling DAC output waveforms, respectively.
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4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω
24 mA (0xF45D) to 4 mA (0x0BA3) measured on 40-Ωshunt
shunt
图7-4. Linear Slew Rate: Falling
图7-3. Linear Slew Rate: Rising
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Sinusoidal mode enables fast DAC settling while improving analog rate of change characteristics. Sinusoidal
mode is selected by the DAC_CFG.SR_MODE bit. 图 7-5 and 图 7-6 show the typical rising and falling DAC
output waveforms with sinusoidal slew-rate control, respectively.
24 mA (0xF45D) to 4 mA (0x0BA3) measured on a 40-Ω
4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω
shunt
shunt
图7-6. Sinusoidal Slew Rate: Falling
图7-5. Sinusoidal Slew Rate: Rising
If the slew-rate feature is disabled while the DAC is executing the slew-rate command, the slew-rate operation is
aborted, and the DAC output goes to the target code.
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7.3.1.6 DAC Register Structure and CLEAR State
The AFE88101 DAC has a 16-bit voltage output, and the AFE78101 DAC has a 14-bit voltage output. 表 7-1
shows four possible VOUT DAC output ranges. With a voltage-to-current converter stage, the narrow range
corresponds to a 4-mA to 20-mA range. The full range allows for undercurrents and overcurrents from 3 mA to
25 mA, and is controlled by DAC_CFG.RANGE.
The AFEx8101 provide the option to quickly set the DAC output to the value set in the DAC_CLR_CODE register
without writing to the DAC_DATA register, referred to as the CLEAR state. Setting the DAC to CLEAR state also
sets the DAC output range according to DAC_CFG.CLR_RANGE. For register details, see 表7-15.
Transitioning from the DAC_DATA to the DAC_CLR_CODE is synchronous to the clock. If slew mode is enabled,
the output slews during the transition. 图 7-7 shows the full AFEx8101 DAC_DATA signal path. The devices
synchronize the DAC_DATA code to the internal clock, causing up to 2.5 internal clock cycles of latency (2 μs)
with respect to the rising edge of CS or the end of a UBM command. Update DAC_GAIN and DAC_OFFSET
values when DAC_CFG.SR_EN = 0 to avoid an IRQ pulse generated by SR_BUSY.
Set the DAC to CLEAR state either by:
1. Setting DAC_CFG.CLR.
2. Configuring the DAC to transition to the CLEAR state in response to an alarm condition.
3. Using the SDI pin in UBM or the SCLR pin in SPI mode as the CLEAR state input pin.
Method 1 is a direct command to the AFEx8101 to set the DAC to CLEAR state. Set the DAC_CFG.CLR bit to
1h to set the DAC to CLEAR state.
Method 2 is controlled by settings of ALARM_ACT register. For details of conditions and other masks required to
use this method, see 表7-24 and 节7.3.3.1.
Method 3 supports setting the DAC to CLEAR state without writing to the AFEx8101. This pin-based DAC
CLEAR state function is available in SPI mode on the SCLR pin, or in UBM on the SDI pin. The SCLR pin must
be tied to GND in UBM. For details of connection options based on communication modes and pins used in each
mode, see 节7.5.1. Set the appropriate pin high to drive the DAC to CLEAR state.
DAC_CFG.CLR Register 03h (Method 1)
ALARM_ACT Register 10h (Method 2)
Slew Enable
Clear Input Pin (Method 3)
DAC_CFG.SR_EN
Register 03h
DAC_DATA
Register 01h
0
1
DAC_CODE
+
0
1
DAC_OUT
+
DAC_CLR_CODE
Register 06h
DAC_CFG.SR_MODE
DAC_CFG.SR_STEP
DAC_CFG.SR_CLK
Register 03h
DAC_GAIN
Register 04h
DAC_OFFSET
Register 05h
Slew Rate: Mode, Step
Size, and Clock Timing
图7-7. DAC Data Path
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7.3.2 Analog-to-Digital Converter (ADC) Overview
The AFEx8101 feature a monitoring system centered on a 12-bit successive approximation register (SAR) ADC
and a highly flexible analog multiplexer. The monitoring system is capable of sensing up to two external inputs,
as well as several internal device signals.
The ADC uses the VREFIO pin voltage as a reference. The ADC timing signals are derived from an on-chip
oscillator. The conversion results are accessed through the device serial interface.
7.3.2.1 ADC Operation
The device ADC supports direct-mode and auto-mode conversions. Both conversion modes use a custom
channel sequencer to determine which of the input channels are converted by the ADC. The sequence order is
fixed. The user selects the start channel and stop channel of the conversion sequence. The conversion method
and channel sequence are specified in the ADC Configuration registers. The default conversion method is auto-
mode. 图7-8 shows the ADC conversion sequence.
START
Set ADC_CFG.BUF_PD = 0,
ADC_CFG.DIRECT_MODE = 0 or 1
ADC idle state
No
TRIGGER.ADC =1?
Yes
Set ADC mux to
ADC_INDEX_CFG.
START
Convert ADC
Increment ADC custom
channel sequencer
Yes
Yes
No
ADC_INDEX.STOP
(last conversion
Completed)?
ADC_CFG.
DIRECT_MODE =1?
No
Yes
TRIGGER_ADC = 0?
No
图7-8. ADC Conversion Sequence
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To use the ADC, first enable the ADC buffer by setting ADC_CFG.BUF_PD = 0. Then wait at least 210 μs
before setting the trigger using the TRIGGER.ADC bit. An internal delay is forced if the trigger signal is sent
before the timer has expired. Make sure the ADC is not converting before setting the ADC_CFG.BUF_PD = 1. If
ADC_CFG.BUF_PD is set to 1 while the ADC is still converting, the internal timer delays this command. When
the timer expires, the enable signal for the ADC is cleared, and the current conversion finishes before powering
down the ADC and the ADC Buffer.
A trigger signal must occur for the ADC to exit the idle state. The ADC trigger is generated through the
TRIGGER.ADC bit. The ADC data registers have the latest available data. Accessing the data registers does not
interfere with the conversion process, and thus provides continuous ADC operation.
In direct-mode conversion, the selected ADC input channels are converted on demand by issuing an ADC trigger
signal. After the last enabled channel is converted, the ADC enters the idle state and waits for a new trigger.
Read the results of the ADC conversion through the register map. Direct-mode conversion is typically used to
gather the ADC data of any of the data channels. In direct-mode, use the ADC_BUSY bit to determine when a
direct-mode conversion is complete and the ADC has returned to the idle state. Direct mode is set by writing
ADC_CFG.DIRECT_MODE = 1.
In auto-mode conversion, the selected ADC input channels are converted continuously. The conversion cycle is
initiated by issuing an ADC trigger. Upon completion of the first conversion sequence, another sequence is
automatically started. Conversion of the selected channels occurs repeatedly until the auto-mode conversion is
stopped by clearing the ADC trigger signal. Auto-mode conversion is not typically used to gather the ADC data.
Instead, auto-mode conversions are used in combination with upper and lower ADC data thresholds to detect
when the data has exceeded the programmable out-of-range alarm thresholds. Auto mode is set by writing
ADC_CFG.DIRECT_MODE = 0.
Regardless of the selected conversion method, update the ADC configuration register only while the ADC is in
the idle state. Do not change the ADC configuration bits while the ADC is converting channels. Before changing
configuration bits, disable the ADC and verify that GEN_STATUS.ADC_BUSY = 0.
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7.3.2.2 ADC Custom Channel Sequencer
The device uses a custom channel sequencer to control the multiplexer of the ADC. The ADC sequencer allows
the user to specify which channels are converted. The sequencer consists of 16 indexed slots with
programmable start and stop index fields to configure the start and stop conversion points.
In direct-mode conversion, the ADC converts from the start index to the stop index once and then stops. In auto-
mode conversion, the ADC converts from the start to stop index repeatedly until the ADC is stopped. 图 7-9
shows the indexed custom channel sequence slots available in the device.
Custom Channel
Sequencer (CCS) Pointer
ADC_INDEX_CFG.START
ADC_INDEX_CFG.STOP
Register 09h
0
1
2
3
4 - 8
9
OFFSET
AIN0
AIN1
TEMP
SD MUX
GND
VREF
PVDD
VDD
4
5
6
7
8
ADC
ZTAT
VOUT
…
15
GND
Self Diagnostic
Multiplexer (SD MUX)
图7-9. ADC MUX Control
表7-5 lists the ADC input channel assignments for the sequencer.
表7-5. Indexed Custom Channel Sequence
CCS POINTER
CHANNEL
CONV_RATE
RANGE
VREF
0
1
2
3
4
5
6
7
8
OFFSET
2560 Hz
AIN0
Programmable
Programmable
2560 Hz
Programmable
Programmable
VREF
AIN1
TEMP
SD0 (VREF)
SD1 (PVDD)
SD2 (VDD)
SD3 (ZTAT)
SD4 (VOUT)
2560 Hz
VREF
2560 Hz
VREF
2560 Hz
VREF
2560 Hz
VREF
2560 Hz
VREF when PVDD = 1.8 V
2 × VREF when PVDD ≥2.7 V
9-15
GND
2560 Hz
VREF
Use the ADC_INDEX_CFG register to select the channels. The order of the channels is fixed and shown in 表
7-5. Then, use ADC_INDEX_CFG.START and ADC_INDEX_CFG.STOP to select the range of indices to
convert. If these two values are the same, then the ADC only converts a single channel. If the START and STOP
values are different, then the ADC cycles through the corresponding indices. By default, all channels are
configured to be converted; START = 0 and STOP = 8. If the AIN1 channel is not configured as an ADC input,
then the result for this channel is 0x000. The minimum time for a conversion is still allotted to AIN1 if the channel
is within the START and STOP range. If START is configured to be greater than STOP, then the device interprets
the conversion sequence as if START = STOP.
In direct mode, each selected channel in the ADC_INDEX_CFG register is converted once per TRIGGER.ADC
command. In auto mode, each channel selected in the ADC_INDEX_CFG register is converted once; after the
last channel, the loop is repeated as long as the ADC is enabled. In auto mode, writing to TRIGGER.ADC = 1
starts the conversions. Writing TRIGGER.ADC = 0 disables the ADC after the current channel being converted
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finishes. In direct mode, writing TRIGGER.ADC = 1 starts the sequence. When the sequence ends, then
TRIGGER.ADC is self-cleared.
A minimum of 20 clock cycles is required to perform one conversion. The ADC clock is derived from the internal
oscillator and divided by 16, which gives an ADC clock frequency of 1.2288 MHz / 16 = 76.8 kHz, for a clock
period = 13.02 μs.
Each of the internal nodes has a fixed conversion rate. Pins AIN0 and AIN1 have programmable conversion
rates (see also the ADC_CFG register). Pins AIN0 and AIN1 also have a configurable range. If PVDD ≥ 2.7 V,
then the input range can be either 0 V to 1.25 V or 0 V to 2.5 V, depending on the ADC_CFG.RANGE bit. If
PVDD = 1.8 V, then only the 0 V to 1.25 V range is allowed. In this case, the ADC_CFG.RANGE bit is prevented
from being set.
If any ADC configuration bits are changed, the following sequence is recommended:
1. Disable the ADC
2. Wait for ADC_BUSY to go low
3. Change the configuration
4. Restart the conversions
ADC_BUSY can be monitored in the GEN_STATUS register.
If the ADC is configured for direct mode (ADC_CFG.DIRECT_MODE = 1), then after setting the desired
channels to convert, write a 1 to TRIGGER.ADC. This bit is self-cleared when the sequence is finished
converting. This command converts all the selected channels once. To initiate another conversion of the
channels, send another TRIGGER.ADC command.
7.3.2.3 ADC Synchronization
The trigger signal must be generated for the ADC to exit the idle state and start conversions. The ADC trigger is
generated through the TRIGGER.ADC bit. The ADC data registers have the latest available data. Accessing the
data registers does not interfere with the conversion process, and thus provides continuous ADC operation.
In direct-mode, use the GEN_STATUS.ADC_BUSY bit to determine when a direct-mode conversion is complete,
and the ADC has returned to the idle state. Similarly, monitor the TRIGGER.ADC bit to see if the ADC has
returned to the idle state.
7.3.2.4 ADC Offset Calibration
Channel 0 of the CCS pointer is named OFFSET. The OFFSET channel is used to calibrate and improve the
ADC offset performance. Convert the OFFSET channel, and use the result as a calibration for the ADC offset in
subsequent measurements.
This ADC channel samples VREF / 2 and compares this result against 7FFh as a measure of the ADC offset.
The data rate for the ADC measuring this channel is 2560 Hz. The ADC conversion for the OFFSET channel is
subtracted from 7FFh and the resulting value is stored in ADC_OFFSET (28h). The offset can be positive or
negative; therefore, the value is stored in 2’s complement notation.
With the subtraction from 7FFh, ADC_OFFSET is the negative of the offset. This value is subtracted from
conversions of the ADC by default. For direct measurements of the ADC, set ADC_BYP.OFST_BYP_EN to 1 to
enable the offset bypass.
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7.3.2.5 External Monitoring Inputs
The AFEx8101 have two analog inputs for external voltage sensing. Channels 1 and 2 for the CCS pointer are
for external monitoring inputs that can be measured by pins AIN0 and AIN1, respectively. The input range for the
analog inputs is configurable to either 0 V to 1.25 V or 0 V to 2.5 V. The analog inputs conversion values are
stored in straight binary format in the ADC registers. The ADC resolution can be computed by 方程式7:
V
RANGE
1 LSB =
(7)
12
2
where
• VRANGE = 2.5 V for the 0‑V to 2.5‑V input range or 1.25 V for the 0‑V to 1.25‑V input range.
图7-10 and 表7-6 detail the transfer characteristics.
PFSC
MC + 1
MC
NFSC+1
NFSC
VIN
1 LSB
VRANGE/2 (VRANGE/2 + 1 LSB)
(VRANGE œ 1 LSB)
图7-10. ADC Transfer Characteristics
表7-6. Transfer Characteristics
INPUT VOLTAGE
≤1 LSB
CODE
DESCRIPTION
IDEAL OUTPUT CODE
NFSC
Negative full-scale code
Negative full-scale code plus 1
Midcode
000
001
800
801
FFF
1 LSB to 2 LSB
NFSC + 1
MC
(VRANGE / 2) to (VRANGE / 2) + 1 LSB
(VRANGE / 2) + 1 LSB to (VRANGE / 2) + 2 LSB
≥VRANGE –1 LSB
MC + 1
PFSC
Midcode plus 1
Positive full-scale code
For these external monitoring inputs, the ADC is configurable for both data rate and voltage range. The data rate
is set to either 640 Hz, 1280 Hz, 2560 Hz, or 3840 Hz with the ADC_CFG.CONV_RATE bits. The range of the
ADC measurement is set with the ADC_CFG.AIN_RANGE bit. The ADC range is 2 × VREF when the bit = 0; the
ADC range is VREF when the bit = 1. ADC_CFG.AIN_RANGE only controls the range if PVDD > 2.7 V. When
PVDD = 1.8 V, the range is VREF regardless of the setting.
When the ADC conversion is completed for AIN0 and AIN1, the resulting ADC data are stored in the
ADC_AIN0.DATA and ADC_AIN1.DATA bits at 24h and 25h of the register map.
If the external monitoring inputs are not used, connect the AIN0 and AIN1 pins to GND through a 1-kΩresistor.
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7.3.2.6 Temperature Sensor
Channel 3 of the CCS is used to measure the die temperature of the device. The ADC measures an internal
temperature sensor that measures a voltage complementary to the absolute temperature (CTAT). This CTAT
voltage has a negative temperature coefficient. The ADC converts this voltage at a data rate of 2560 Hz. When
the ADC conversion is completed, the data are found in the ADC_TEMP.DATA bits (address 26h).
The relationship between the ambient temperature and the ADC code is shown in 方程式8:
ADC Code = 2681 − 11 × T °C
(8)
A
7.3.2.7 Self-Diagnostic Multiplexer
In addition to the ADC offset, the two external monitoring inputs, and the temperature sensor, the ADC of the
AFEx8101 has five other internal inputs to monitor the reference voltage, the power supplies, a static voltage,
and the DAC output. These five voltages measurements are part of the self-diagnostic multiplexer (SD0 to SD4)
measurements of the ADC, and are reported in the ADC_SD_MUX register at 27h; see also 节7.6.
Channel 4 (SD0) measures the reference voltage of the device. The ADC measures the reference voltage
through a resistor divider (divide by two). Be aware that all ADC measurements are a function of the reference;
using SD0 to measure the reference is not revealing as a diagnostic measurement. The data rate for this
conversion is 2560 Hz and the range of the ADC is set to VREF.
Channel 5 (SD1) measures the PVDD power supply of the device. The ADC measures the PVDD voltage
through a resistor divider (divide by six). The data rate for this conversion is 2560 Hz and the range of the ADC
is set to VREF.
Channel 6 (SD2) measures the VDD power supply of the device. When channel 6 is selected, the ADC
measures the VDD voltage through a resistor divider (divide by 2). The data rate for this conversion is 2560 Hz
and the range of the ADC is set to VREF.
Channel 7 (SD3) is a ZTAT (zero temperature coefficient) voltage. This internal voltage is nominally 0.6 V with a
low temperature drift and does not depend on the reference voltage. An ADC measurement of ZTAT voltage can
be useful to determine the state of the reference voltage. The data rate for this conversion is 2560 Hz and the
range of the ADC is set to VREF.
Channel 8 (SD4) measures the VOUT of the DAC. The ADC measures the VOUT voltage through a resistor
divider (divide by two). The data rate for this conversion is 2560 Hz.
The input range for the DAC voltage monitoring input is scaled from either 0-V to 2.5-V or 0-V to 1.25-V,
depending on PVDD voltage. As soon as the PVDD voltage exceeds 2.7 V, the input range for the DAC voltage
monitoring automatically switches to the 0-V to 2.5-V range. The DAC voltage conversion values are stored in
straight-binary format in the ADC registers. The ADC resolution for these channels is computed by 方程式7.
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7.3.2.8 ADC Bypass
To test the offset, modify the ADC data path by programming the bypass data register, ADC_BYP.DATA (2Eh).
This read/write register is used in two different ways.
First, this bypass data register is used as a substitute for the ADC_OFFSET by setting the
ADC_BYP.OFST_BYP_EN to 1.
Second, the ADC_BYP.DATA is used as the readback register for the data for the different settings of the custom
channel sequencer. The data are replaced by setting the ADC_BYP.DATA_BYP_EN bit. When this bit is set to 1,
the ADC conversion is bypassed, and the value of ADC_BYP.DATA is used in the readback channel. This setting
is used to test the alarm settings of the ADC.
When the ADC bypass is unused, set the ADC_BYP.DATA to 000h.
图7-11 shows the ADC bypass data flow.
ADC_BYP.
OFST_BYP_EN
Register 2Eh
ADC_BYP.
DATA_BYP_EN
Register 2Eh
ADC Data
From ADC MUX
07FFh – OFFSET
Stored as 2’s Complement
ADC_AIN0
Register 24h
ADC_OFFSET
Register 28h
0
1
ADC_AIN1
Register 25h
+
ADC.
ADC_OUT
Register 2Dh
+
ADC
MUX
0
1
ADC_TEMP
Register 26h
ADC_SD_MUX
Register 27h
ADC_BYP.DATA
Register 2Eh
Read and Writeable
for Testing
CCS Pointer
图7-11. ADC Bypass Data Flow
7.3.3 Programmable Out-of-Range Alarms
The AFEx8101 are capable of continuously analyzing the supplies, external ADC inputs, DAC output voltage,
reference, internal temperature, and other internal signals for normal operation.
Normal operation for the conversion results is established through the lower- and upper-threshold registers.
When any of the monitored inputs are out of the specified range, the corresponding alarm bit in the alarm status
registers is set.
The alarm bits in the alarm status registers are latched. The alarm bits are referred to as being latched because
the alarm bits remain set until read by software. This design makes sure that out-of-limit events cannot be
missed if the software is polling the device periodically. All bits are cleared when reading the alarm status
registers, and all bits are reasserted if the out-of limit condition still exists on the next monitoring cycle.
All of the alarms can be set to activate the ALARM pin. The ALARM pin works as an interrupt to the host so that
the host can query the alarm status registers to determine the alarm source. Any alarm event activates the pin
as long as the alarm is not masked in the ALARM_STATUS_MASK register. When an alarm event is masked,
the occurrence of the event sets the corresponding status bit in the alarm status registers, but does not activate
the ALARM pin.
In addition, 节 7.3.3.1 describes how the alarm action can be individually configured for each alarm. When the
alarm event is cleared, the DAC is reloaded with the contents of the DAC active registers, which allows the DAC
outputs to return to the previous operating point without any additional commands.
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7.3.3.1 Alarm Action Configuration Register
The AFEx8101 implements an alarm action configuration register (ALARM_ACT, 表7-24). Writing to this register
selects the action that the device automatically takes in case of a specific alarm condition. The ALARM_ACT
register determines how the main DAC responds to an alarm event from conversion on self-diagnostics
channels, AIN0, AIN1, and TEMP, as well as a CRC and WDT fault, a VREF fault, a TEMP_HI fault, and a
TEMP_LO fault. Only these faults can cause a response by the DAC. Other alarm status events can trigger the
ALARM pin. There are four options for alarm action. In case different settings are chosen for different alarm
conditions, the following (low-to-high) priority is considered when taking action:
• 0. →No action
• 1. →DAC CLEAR state
• 2. →VOUT alarm voltage
• 3. →VOUT Hi-Z
If the alarm event occurs and option 1 is selected, then the DAC is forced to the clear code and clear range. This
operation is done by controlling the input code to the DAC and the range of the DAC.
If the alarm event occurs and option 2 is selected, then VOUT is forced to the alarm voltage. The alarm voltage
is controlled by either pin or register bit. If SPECIAL_CFG.AIN1_ENB = 0, then the AIN1 pin controls alarm
polarity. Also, register bit SPECIAL_CFG.ALMV_POL can be used. If either of these signals = 1, then the alarm
voltage is high; otherwise, the alarm voltage is low. The SPECIAL_CFG register is only reset with POR, so the
user setting remains intact through hardware or software resets.
If the alarm event occurs and option 3 is selected, then the VOUT buffer is put into Hi-Z.
If multiple events occur, then the highest setting takes precedence. Option 3 has the highest priority.
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7.3.3.2 Alarm Voltage Generator
图 7-12 shows that the alarm voltage is generated independently from the DAC output voltage. The alarm
polarity control logic selects the output level of the alarm voltage generator. The alarm action control logic selects
between the DAC output and alarm voltage generator output voltages. The alarm action control logic also
controls the output buffer Hi-Z switch.
ALARM_ACT
Register 10h
PVDD =1.8 V: G = 1
PVDD > 2.7 V: G = 2
DAC_DATA
0
1
DAC_CODE
G
DAC
Hi-Z
DAC_CLR_CODE
–
+
0
1
VOUT
ALMV_POL
POL_SEL/
AIN1
OUT = 0.15 V
OUT = 1.25 V
VDD
GND
Alarm
Voltage
Generator
0
1
图7-12. Alarm Voltage Generator Architecture
During normal operation, the expected VOUT voltage depends on the DAC_CODE. The ADC thresholds for the
SD4 (VOUT) diagnostic channel are set around the programmed DAC_CODE. During the alarm condition, if the
alarm action changes the VOUT voltage to the alarm voltage, or switches the VOUT buffer into Hi-Z mode, the
VOUT voltage no longer depends on the DAC_CODE. In this case, the SD4 (VOUT) diagnostic channel also
reports the alarm. To clear this alarm, as long as all other alarm conditions are cleared, set the alarm action to
either no action or to the DAC clear code. Applying either alarm action sets the VOUT voltage within the
expected ADC thresholds and clears the alarm after the next ADC measurement of the SD4 (VOUT) channel.
Give special consideration to the alarm logic during the transient events. When the new DAC_CODE goes
beyond the SD4 (VOUT) alarm thresholds with the ADC monitoring the SD4 (VOUT) input in auto mode, the
ADC conversion can occur while VOUT settles to a new value. This conversion can trigger a false alarm. There
are two ways to prevent this false alarm:
1. Use direct mode and allow VOUT to settle before triggering the next ADC conversion.
2. Set ADC_CFG.FLT_CNT > 0. With this configuration, a single error in SD4 or any other measurement does
not cause an alarm condition to be asserted.
7.3.3.3 Temperature Sensor Alarm Function
The AFEx8101 continuously monitor the internal die temperature. In addition to the ADC measurement, the
temperature sensor triggers a comparator to show a thermal warning and a thermal error. A thermal warning
alarm is set when the temperature exceeds 85°C. Additionally, a thermal error alarm is set when the die
temperature exceeds 130°C.
The thermal warning and thermal error alarms can be configured to set the ALARM pin and are indicated in the
ALARM_STATUS register. These alarms can be masked with the ALARM_MASK register and also be
configured to control the DAC output with the ALARM_ACT register.
7.3.3.4 Internal Reference Alarm Function
The devices provide out-of-range detection for the reference voltage. When the reference voltage exceeds ±5%
of the nominal value, the reference alarm flag (VREF_FLT bit) is set. Make sure that a reference alarm condition
has not been issued by the device before powering up the DAC output.
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7.3.3.5 ADC Alarm Function
The AFEx8101 provide independent out-of-range detection for each of the ADC inputs. 图 7-13 shows the out-
of-range detection block. When the measurement is out of range, the corresponding alarm bit is set to flag the
out-of-range condition.
AIN0_THRESHOLD [15:8]
AIN1_THRESHOLD [15:8]
TEMP_THRESHOLD [15:8]
Register 12h, 13h, 14h
Upper threshold
–
+
ALARM_STATUS
ADC_AIN0_FLT,
ADC conversion value
ADC_AIN1_FLT,
ADC_TMP_FLT
Register 20h [3],[4],[2]
–
+
AIN0_THRESHOLD [7:0]
AIN1_THRESHOLD [7:0]
TEMP_THRESHOLD [7:0]
Register 12h, 13h, 14h
Lower threshold
图7-13. ADC Out-of-Range Alarm
An alarm event is only registered when the monitored signal is out of range for N number of consecutive
conversions, where N is configured in the ADC_CFG.FLT_CNT false alarm register settings. If the monitored
signal returns to the normal range before N consecutive conversions, an alarm event is not issued.
If an ADC input signal is out of range and the alarm is enabled, then the corresponding alarm bit is set to 1.
However, the alarm condition is cleared only when the conversion result returns to a value less than the high-
limit register setting and greater than the low-limit register setting by the number of codes specified by the
hysteresis setting (see 图 7-14). The hysteresis is a programmable value between 0 LSB to 127 LSB in the
ADC_CFG.HYST register.
High Threshold
Hysteresis
Hysteresis
Low Threshold
Over High Alarm
Below Low Alarm
图7-14. ADC Alarm Hysteresis
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7.3.3.6 Fault Detection
There are two fields within the ADC_CFG register: FLT_CNT and HYST. These fields are applied to the
assertion and deassertion of alarm conditions for all the ADC channels.
ADC_CFG.FLT_CNT determines the number of consecutive failures needed to trip an alarm condition. For
example, if ADC_CFG.FLT_CNT is set for three counts, then three consecutive conversions must be outside of
the thresholds. Each failure counts towards the FLT_CNT limit even if the failures alternate between high
threshold and low threshold.
ADC_CFG.HYST sets the hysteresis used by the alarm-detection circuit. After an alarm is triggered, the
hysteresis is applied before the alarm condition is released. In the case of the high threshold, the hysteresis is
subtracted from the threshold value. In the case of the low threshold limit, the hysteresis is added to the
threshold value.
Channels AIN0, AIN1, and TEMP have high and low thresholds associated with them. If a conversion value falls
outside of these limits (that is, if TEMP < low threshold or TEMP > high threshold), an alarm condition for that
channel is set. The alarms are disabled by setting 0x000 for the low threshold and 0xFFF for the high threshold,
respectively. These alarms are disabled by default. Because the configuration fields for the thresholds are only
eight bits wide, the four LSBs are hardcoded for each threshold. The high thresholds four LSBs are hardcoded to
0xF, and the low thresholds four LSBs are hardcoded to 0x0.
All the self diagnostic (SD) channels have fixed thresholds, except SD4, which measures the VOUT of the main
DAC. The threshold for SD4 tracks the VOUT with respect to the DAC code. 表 7-7 shows the calculations used
to determine the high and low ADC thresholds for each SD channel. The limits in the two right-most columns are
determined by the threshold columns to the left and given some margin. The four LSBs are assigned as
described previously.
表7-7. Self Diagnostic (SD) Alarm ADC Thresholds
ADC
INPUT
ACCEPTED LOW
VALUE
ACCEPTED HIGH
VALUE
LOW
HIGH
SD
ADC LOW (HEX) ADC HIGH (HEX)
THRESHOLD THRESHOLD
SD0 VREF/2
VREF/2 + 9% + 25 mV
0.54375 V
0.70625 V
0x6D0
0x92F
VREF/2 –9% –25
mV
SD1 PVDD/6
6/6 + 25 mV
2/2 + 25 mV
0.25 V
0.775 V
0.521 V
1.025 V
1.025 V
0x310
0x9C0
0x690
0xD3F
0xD3F
1.65/6 –25 mV
1.6/2 –25 mV
SD2
SD3
VDD/2
0.6 V
0.6 V + 9% + 25 mV
VOUT/2 + 6 mV
0.679 V
0x8CF
0.6 V –9% –25 mV
VOUT/2 –6 mV
SD4 VOUT/2
VOUT + 12 mV
Expected + 0x040
VOUT –12
Expected –
mV
0x040
The alarm threshold for the SD4 input depends on the expected ADC measurement based on the DAC code.
The threshold is different for each DAC range and is adjusted accordingly. 方程式 9 shows the expected ADC
code for RANGE = 0, and 方程式10 shows the expected ADC code for RANGE = 1.
DAC_CODE MSB:MSB – 11 × 113 ÷ 128 + 492
ADC Expected Code: RANGE 0 =
ADC Expected Code: RANGE 1 =
(9)
2
DAC_CODE MSB:MSB – 11 × 82 ÷ 128 + 655
2
(10)
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7.3.4 IRQ
The devices include an interrupt request (IRQ) to communicate the occurrence of a variety of events to the host
controller. The IRQ block initiates interrupts that are reported internally in a status register, externally on the IRQ
pin if the function is enabled, or on the ALARM pin if the condition is from the ALARM_STATUS register. 图 7-15
shows the IRQ block diagram.
CONFIG.IRQ_POL
Register 02h
CONFIG.IRQ_LVL
Register 02h
Interrupt
Generation
Maskable
Status Bits
1
0
XOR
IRQ
ALARM_STATUS
Register 20h
ALARM_STATUS_MASK
Register 1Dh
D
Q
D
Q
GEN_STATUS
Register 21h
GEN_STATUS_MASK
Register 1Eh
CLK
CLK
IRQ Pulse
Generation
(813-ns Wide)
Internal Oscillator
图7-15. IRQ Block Diagram
There are two registers that can generate interrupts: GEN_STATUS and ALARM_STATUS. Each of these
registers has a corresponding STATUS_MASK register. The mask register controls which of the events trigger
an interrupt. Writing a 1 in the mask register masks, or disables, the event from triggering an interrupt. Writing a
0 in the mask register allows the event to trigger an IRQ. All bits are masked by default. Some status bits are
sticky. Reading the corresponding register clears a sticky bit, unless the condition still exists.
The IRQ is configured through CONFIG.IRQ_LVL to be edge- or level-sensitive. Set this bit to logic 1 to enable
level-sensitive functionality (default). In edge-sensitive mode, the IRQ signal is a synchronous pulse, one internal
clock period wide (813 ns). In level-sensitive mode, the IRQ is set and remains set as long as the condition
exists. After the IRQ condition is removed, the condition is cleared by reading the corresponding status register.
Trying to clear the bit while the condition still exists does not allow the bit to be cleared if the bit is sticky.
CONFIG.IRQ_POL determines the active level of the IRQ. A logic 1 configures IRQ to be active high.
When using edge-sensitive IRQ signals, there is a clock cycle delay for synchronization and edge detection.
With a 307.2-kHz clock, this delay is up to 3.26 μs. For level-sensitive mode, the delay is approximately 10 ns to
20 ns.
Most status bits have two versions within the design. The first version is an edge event that is created when the
status is asserted. This signal is used to generate edge-sensitive IRQs. This edge detection prevents multiple
status events from blocking one another. The second version is the sticky version of the status bit. This signal is
set upon assertion of the status bit and cleared when the corresponding status register is read, as long as the
status condition does not still persist. Signals GEN_IRQ and ALARM_IRQ are driven by the logical OR of the of
the status bits within the corresponding register.
If a status bit is unmasked and the sticky version of that bit has been asserted, and the IRQ is level-sensitive,
then an interrupt is triggered as soon as the bit is unmasked. If the IRQ is edge-sensitive then a status event
must occur after the bit has been unmasked to assert an interrupt.
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7.3.5 Internal Reference
The AFEx8101 family of devices includes a 1.25-V precision band-gap reference. The internal reference is
externally available at the VREFIO pin and sources up to 2.5 mA. For noise filtering, use a 100-nF capacitor
between the reference output and GND.
The internal reference circuit is enabled or disabled by using the REF_EN pin. A logic high on this pin enables
the internal reference, and the VREFIO pin outputs 1.25 V. A logic low on this pin disables the internal reference,
and the device expects to have 1.25 V from external VREF at the VREFIO pin.
An invalid reference voltage asserts an alarm condition. The DAC response depends on the VREF_FLT setting
in the ALARM_ACT register (10h).
7.3.6 Integrated Precision Oscillator
The internal time base of the device is provided by an internal oscillator that is trimmed to less than 0.5%
tolerance at room temperature. The precision oscillator is the timing source for ADC conversions. At power up,
the internal oscillator and ADC take roughly 300 µs to reach < 1% error stability. After the clock stabilizes, the
ADC data output is accurate to the electrical specifications provided in 节6.
7.3.7 One-Time Programmable (OTP) Memory
One-time programmable (OTP) memory in the device is used to store the device trim settings and is not
accessible to users. The OTP memory data are loaded to the memory at power up. The OTP memory CRC is
performed to verify the correct data are loaded. The TRIGGER.SHADOWLOAD bit is available to initiate a
reload of the OTP memory data if a CRC error is detected. The SPECIAL_CFG.OTP_LOAD_SW_RST bit
controls whether the OTP memory data are reloaded with a software reset.
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7.4 Device Functional Modes
7.4.1 DAC Power-Down Mode
Power-down mode facilitates rapid turn-off of the voltage at the DAC output. The DAC can be set to enter and
exit power-down mode through hardware, software, or automatically in response to an alarm event. The DAC
output is specified for glitch-free performance when going into and out of power-down mode.
Power-down mode is also be enabled by setting DAC_CFG.PD to 1. In power-down mode, the DAC output
amplifier powers down and the DAC output pin is put into the Hi-Z configuration. The DAC output remains in
power-down mode until the DAC output is re-enabled.
Alarm control of the power-down mode is enabled by setting the alarm events as DAC power-down sources. The
alarm events that trigger the DAC output power-down state must be specified in the ALARM_ACT register. After
the alarm bit is cleared, the DAC returns to normal operation, as long as no other power-down controlling alarm
event has been triggered.
The DAC register does not change when the DAC enters power-down mode, which enables the device to return
to the original operating point after return from the power-down mode. Additionally, the DAC register can be
updated while the DAC is in power-down mode, thus allowing the DAC to output a new value upon return to
normal operation.
7.4.2 Reset
There are three reset mechanisms in the device: a power-on reset (POR), a RESET pin, and the SW_RST
command that can be sent through the either the SPI or by UBM.
When power is first applied to the device, a POR circuit holds the device in reset until all supplies reach the
specified operating voltages. The power-on reset returns the device to a known operating state in case a
brownout event occurs (when the supplies have dipped below the minimum operating voltages). The POR starts
all digital circuits in reset as the supply settles, and releases them to make sure that the device starts in the
default condition and loads the OTP memory. After the OTP memory has been loaded, the ALARM pin is
released. At this time, communication with the device is safe. This tPOR time is less than 100 µs.
The devices also have a RESET pin that is used as a hardware reset to the device. Send the RESET pin low for
a minimum of 100 ns (tRESET) to reset the device. A delay time of 10 μs (tRESETWAIT) is required before sending
the first serial interface command as the device latches and releases the reset. The release of the internal reset
state is synchronized to the internal clock. The RESET pin resets the SPI and the UART interfaces, the
watchdog timer, the internal oscillator, and the device registers. RESET does not reload the OTP memory.
The command to RESET.SW_RST = 0xAD resets the device as a software reset. The command is decoded at
the rising edge of CS with an SPI command or during the stop bit of the last character of a UBM frame. Set
UBM.REG_MODE again to put the device back into UBM when resetting the device in UBM. After sending the
RESET command, no delay time is required before sending the first serial interface command as the device
latches and releases the reset. The reset is synchronized to the falling edge of the internal clock and is released
well before the next rising edge. The ALARM pin pulses low for the width of the internal reset. This pulse
duration is less than 20 ns. This command resets the SPI and the UART interface, and the watchdog timer, but
does not reset the internal oscillator. The software reset also reloads internal factory trim registers if properly
configured in the SPECIAL_CFG register. The SPECIAL_CFG register is only reset with a POR.
The POR and hardware reset place the internal oscillator into a reset condition, which holds the clock low. When
these two signals are released, there is a delay of a few microseconds before the first rising edge of the clock.
The hardware reset, RESET, pulse width must be at least 100 ns to allow the oscillator to properly reset. The
SW_RST command is a short pulse. This pulse is not long enough to adequately reset the oscillator. The
SW_RST is asserted with a falling edge of the clock. As a result of the long oscillator period, the design
architecture provides that all devices are out of reset by the next rising edge.
图7-16 shows the reset tree.
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Device Resets
Device Module
Register Reset
Reset
Power-On Reset
Reset Command
Factory
Trim
Software Reset
ALARM_STATUS
ALARM_STATUS Read
SPI
GEN_STATUS
Other Registers
SPECIAL_CFG
Communication
GEN_STATUS Read
CS
Watchdog
Timer
WDT.WDT_EN
Power-On Reset
Reset Command
Pin Reset
Reset
UART
Communication
Power-On Reset
CONFIG.UART_DIS
Hardware Reset
Power-On Reset
Pin Reset
Oscillator
图7-16. Reset Conditions
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7.5 Programming
The AFEx8101 communicate with the system controller through a serial interface that supports either a UART-
compatible two-wire bus or an SPI-compatible bus. Based on the hardware configuration, either interface can be
enabled. 图 7-17 and 图 7-18 show the configurations to enable SPI mode and UART break mode (UBM),
respectively. The SPI supports an 8-bit frame-by-frame CRC that is enabled by default, but can be disabled by
the user. UBM does not support CRC, but does support the UART protocol parity bit.
7.5.1 Communication Setup
After any reset or power up, the AFEx8101 wake up able to use the SPI or UART break mode (UBM). The
devices include a robust mechanism that configures the interface between either an SPI-compatible or UART-
compatible protocol based system, thus preventing protocol change during normal operation. The selection is
based on initial conditions from the respective hardware configurations (see 图 7-17 and 图 7-18) and any
subsequent user configuration.
7.5.1.1 SPI Mode
By default, the AFEx8101 can be fully accessed with the SPI (except UBM.REG_MODE). To set up the device in
SPI mode:
1. Set CONFIG.UART_DIS = 1 (disables the UART communication).
2. Optionally, set CONFIG.DSDO, CONFIG.FSDO, CONFIG.CLR_PIN_EN, and CONFIG.IRQ_PIN_EN. For
details, see 表7-14.
System
System
AFE
AFE
Controller
Controller
UARTOUT
UARTIN
IOVDD
Interrupt
UARTOUT
UARTIN
IOVDD
UART
(UBM)
UART
(UBM)
CLK_OUT
CLK_OUT
Monitor
Chip Select
Data Out
Data In
Chip Select
Data Out
Data In
CS
SDI
SDO
SCLK
GND
CS
SDI
SDO
SCLK
Clock
Clock
SCLR
RESET
IOVDD
Clear
Reset
SCLR
RESET
Control Logic
Control Logic
Minimum
Functionality
Maximum
Functionality
图7-17. SPI Mode Connections
图 7-17 shows the SPI mode logical connections (through the isolation barrier, if used) for both minimum
functionality (all optional pins disconnected) and maximum functionality (all pins connected). If
CONFIG.IRQ_PIN_EN = 1 is set, then the UARTOUT pin functions as the IRQ output. In SPI mode, set
CONFIG.SDO_DSDO = 0 to enable the readback function. This function is disabled by default to save power. If
the readback function not enabled, SDO remains in Hi-Z mode even during the subsequent frame after a read
request.
7.5.1.2 UART Mode
At power up, the UART interface is set to 9600 baud with UBM enabled. Any reset clears the UBM register, and
the register must be set again to use UBM. To set up the device in UBM:
1. Using UBM, set UBM.REG_MODE = 1 at 9600 baud. This setting blocks the SPI from accessing the device
and enables the UART interface access to the entire register map.
2. Optionally, set CONFIG.CLR_PIN_EN and CONFIG.IRQ_PIN_EN (See 表7-14 for details).
图 7-18 shows the UBM logical connections (through the isolation barrier, if used) for both minimum functionality
(all optional pins disconnected) and maximum functionality (all pins connected). If CONFIG.IRQ_PIN_EN = 1 is
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set, then the SDO pin functions as the IRQ output. If CONFIG.CLR_PIN_EN = 1 is set, then the SDI pin controls
the clear pin function.
System
System
AFE
AFE
Controller
Controller
Rx
Tx
UARTOUT
UARTIN
Rx
Tx
UARTOUT
UARTIN
UART
(UBM)
UART
(UBM)
CLK_OUT
CLK_OUT
Monitor
IOVDD
CS
IOVDD
CS
SDI
Clear
SDI
SDO
Interrupt
SDO
SCLK
GND
SCLR
RESET
IOVDD
SCLK
GND
SCLR
RESET
Control Logic
Control Logic
Reset
Minimum
Functionality
Maximum
Functionality
图7-18. UBM (UART Interface) Connections
7.5.2 Serial Peripheral Interface (SPI)
The AFEx8101 are controlled over a versatile four-wire serial interface (SDIN, SDO, SCLK, and CS). The
interface operates at clock rates of up to 12.5 MHz and is compatible with SPI, QSPI, Microwire, and digital
signal processing (DSP) standards. The SPI communication command consists of a read or write address, a
data word, and an optional CRC byte.
The SPI can access all register addresses except for the UBM register. Read-only and read-write capability is
defined by register (see 表 7-10). The SPI supports both SPI Mode 1 (CPOL = 0, CPHA = 1) and SPI Mode 2
(CPOL = 1, CPHA = 0). The default SCLK value is low for SPI Mode 1 and high for SPI Mode 2. See 节 6.7 for
timing diagrams in each mode. The serial clock, SCLK, can be continuous or gated.
7.5.2.1 SPI Frame Definition
Subject to the timing requirements listed in the Timing Requirements, the first SCLK falling edge immediately
following the falling edge of CS captures the first frame bit. Subject to the same requirements, the last SCLK
falling edge before the rising edge of CS captures the last bit of the frame. 图 7-19 shows that the SPI shift
register frame is 32-bits wide, and consists of an R/W bit, followed by a 7-bit address, and a 16-bit data word.
The 8-bit CRC is optional (enabled by default) and is disabled by setting CONFIG.CRC_EN = 0 (see also 节
7.5.2.3). 图7-20 shows that when the CRC is disabled, the frame is 24-bits wide.
Don’t Care
Hi-Z
Valid Data
SCLK
CS
31
30~24
23~8
7~0
SDI
R/W (1b) Address (7b) Data Word (16b) CRC (8b)
Input Frame (n)
Next Frame (n+1), Command or NOP
Output Frame (n)
Output Frame (n-1)
R/W (1b)
Status (7b)
Data Word (16b) CRC (8b)
SDO
Status
Details
CRC_ERR
1'b0
1'b0
RESET
1'b0
GEN_IRQ
ALARM_IRQ
图7-19. SPI Frame Details (Default, CRC Enabled)
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Don’t Care
Hi-Z
Valid Data
SCLK
CS
23
22~16
15~0
SDI
R/W (1b) Address (7b) Data Word (16b)
Input Frame (n)
Next Frame (n+1), Command or NOP
Output Frame (n)
Output Frame (n-1)
R/W (1b)
Status (7b)
Data Word (16b)
SDO
图7-20. SPI Frame Details (CRC Disabled)
For a valid frame, a full frame length of data (24 bits if CRC is disabled or 32 bits if CRC is enabled) must be
transmitted before CS is brought high. If CS is brought high before the last falling SCLK edge of a full frame,
then the data word is not transferred into the internal registers. If more than a full frame length of falling SCLK
edges are applied before CS is brought high, then the last full frame length number of bits are used. In other
words, if the number of falling SCLK edges while CS = 0 is 34, then the last 32 SCLK cycles (or 24 if CRC is
disabled) are treated as the valid frame. The device internal registers are updated from the SPI shift register on
the rising edge of CS. To start another serial transfer, bring CS low again. When CS is high, the SCLK and SDI
signals are blocked and the SDO pin is high impedance.
7.5.2.2 SPI Read and Write
The SDI input bit is latched on the SCLK falling edge. The SDI pin receives right-justified data. At the rising edge
of CS, the right-most (last) bits are evaluated as a frame. Extra clock cycles (exceeding frame length) during the
frame begin to output on SDO the SDI data delayed by one frame length.
A read operation is started when R/W bit is 1. The data word input for SDI is ignored in the read command
frame. Send the subsequent read or write command frame into SDI to clock out the data of the addressed
register on SDO. If no other read or write commands are needed, then issue a NOP command to retrieve the
requested data. The read register value is output most significant bit first on SDO on successive edges (rising or
falling based on CONFIG.FSDO setting) of SCLK.
A write operation starts when R/W bit is 0. The SDO output to a write command, delivered in the next frame,
contains status bits, data described in 表7-8, and if the CRC is enabled, an 8-bit CRC for the output frame.
表7-8. Command Functions
COMMAND BIT
Write (R/W = 0)
Read (R/W = 1)
SDI INPUT DATA WORD
Data to be written (16b)
Ignored(2)
SDO RESPONSE DATA WORD(1)
0x0000
Register output data (16b)
(1) Response data portion in next frame output.
(2) The input bits are included in the calculation for CRC, if enabled (see 节7.5.2.3).
Valid SDO output is driven only when CS = 0 and CONFIG.DSDO = 0; otherwise, the SDO pin remains Hi-Z to
save power. The SDO data bits are left-justified within the frame, meaning the most significant bit is produced on
the line (subject to timing details) when CS is asserted low (bit is driven by falling edge of CS). The subsequent
bits in the frame are driven by the rising SCLK edge when CONFIG.FSDO = 0 (default). To drive the SDO data
on the falling edge of SCLK, set CONFIG.FSDO = 1. This setting effectively gives the SDO data an additional ½
clock period for setup time, but at the expense of hold time.
The frame output on SDO contains the command bit of the input that generated the frame (previous input frame),
followed by seven status bits (see 图 7-19). When an input frame CRC error is detected, the status bit
CRC_ERR = 1. If there is no input frame CRC error, then CRC_ERR = 0. See 表7-9 for details.
7.5.2.3 Frame Error Checking
If the AFEx8101 are used in a noisy environment, use the CRC to check the integrity of the SPI data
communication between the device and the system controller. This feature is enabled by default and is
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controlled by the CONFIG.CRC_EN bit. If the CRC is not required in the system, disable frame error checking
through the CRC_EN bit, and switch from the default 32-bit frame to the 24-bit frame.
Frame error checking is based on the CRC-8-ATM (HEC) polynomial: x8 + x2 + x + 1 (9'b100000111).
For the output register readback, the AFEx8101 supply the calculated 8-bit CRC for the 24 bits of data provided,
as part of the 32-bit frame.
The AFEx8101 decodes 24-bits of the input frame data and the 8-bit CRC to compute the CRC remainder. If no
error exists in the frame, the CRC remainder is zero. When the remainder is nonzero (that is, the input frame has
single-bit or multiple-bit errors) the ALARM_STATUS.CRC_ERR_CNT bits are incremented. A bad CRC value
prevents execution of commands to the device.
When the CRC error counter reaches the limit programmed in CONFIG.CRC_ERR_CNT, the CRC_FLT status
bit is set in the ALARM_STATUS register. The fault is reported (as long as the corresponding mask is not set) as
an ALARM_IRQ on SDO during the next frame. The ALARM pin asserts low if enabled by the alarm action
configuration (see 节7.3.3.1).
The CRC_ERR status bit (see 图 7-19) in the SDO frame is not sticky and is only reported for the previous
frame. The ALARM_STATUS.CRC_FLT bit is sticky and is only cleared after a successful read of the
ALARM_STATUS register. Read the GEN_STATUS or ALARM_STATUS registers to clear any sticky bits that are
set.
The sticky status bits are cleared at the start of the readback frame and are latched again at the end of the
readback frame. Therefore, if the fault condition previously reported in the status register is no longer present at
the end of the readback frame, and the data are received by the microcontroller with the CRC error, the fault
information is lost. If a robust monitoring of the status bits is required in a noisy environment, use the IRQ pin in
combination with the status mask bits to find out the status of each fault before clearing the status bits. Set the
CONFIG.IRQ_LVL bit to monitor the signal level on the IRQ pin, and unmask each status bit one at a time to
retrieve the information from the status registers.
7.5.2.4 Synchronization
The AFEx8101 register map runs on the internal clock domain. Both the SPI and UBM packets are synchronized
to this domain. This synchronization adds a latency of 0.4 µs to 1.22 µs (1.5 internal clocks), with respect to the
rising edge of CS or the STOP bit of the last byte of the UBM packet.
The effect of clock synchronization on UBM communication is not evident because of the lower speed and
asynchronous nature of UBM communication.
In SPI mode, if changing register bits CONFIG.DSDO, CONFIG.FSDO, or CONFIG.CRC_EN, keep CS high for
at least two clock cycles before issuing the next frame. Frame data corruption can occur if the two extra cycles
are not used. The following are examples of frame corruption:
• Setting CONFIG.DSDO = 0: SDO begins to drive in the middle of the next frame.
• Changing CONFIG.FSDO: The launching edge of SDO changes in the middle of the next frame.
• Setting CONFIG.CRC_EN = 1: The next frame has a CRC error because the CRC is enabled in the middle of
the frame.
Send a NOP command (SDI = 0x00_0000) after setting the DSDO, FSDO, and CRC_EN bits to prevent the
corrupted frames from impacting communication. Sending a NOP after CONFIG.CRC_EN is set still generates a
CRC error, and is reported in the STATUS portion of SDO. To avoid false errors, wait approximately 2 µs after
setting CONFIG.CRC_EN before sending the next frame.
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7.5.3 UART
In UART mode, the device expects 1 start bit, 8 data bits, 1 odd parity bit, and 1 stop bit, or an 8O1 UART
character format.
7.5.3.1 UART Break Mode (UBM)
In UART break mode (UBM), the microcontroller issues a UART break to start communication. The device
interprets the UART break as the start to receive commands from the UART. A communication UART character
consists of one start bit, eight data bits, one odd parity bit, and at least one stop bit. A UART break character is
all 11 bits (including start, data, parity and stop bit) held low by the microcontroller on the UARTIN pin and by the
AFEx8101 on the UARTOUT pin. When a valid break character is detected on UARTIN by the AFEx8101, no
parity (even though parity is odd) or stop bit errors are flagged for this character. The parity and stop bit
differences between valid UBM break and communication characters must be managed by the system
microcontroller when receiving these characters from the UARTOUT pin of the AFEx8101. See 图 6-2 for UBM
break character, communication timing details, and bit order.
AFEx8101 UART break mode communication is supported at 9600 baud.
Set UBM.REG_MODE = 1 to enable register map access through the UART. By default, this bit is set to 0. The
entire register map can only be accessed with SPI, except for the UBM register. The UBM register can only be
accessed with UBM. After UBM.REG_MODE is set to 1, the SPI does not have access to the register map, and
the full register map is accessible by UBM.
A UBM data output packet is initiated by AFEx8101 on UARTOUT in two cases. See 图7-23 for packet structure
details. If the R/IRQn status bit is 0 an IRQ event initiated the break command. If the R/IRQn status bit is 1, the
break command is a response to the prior read request.
To enable IRQ events, set CONFIG.UBM_IRQ_EN = 1. When IRQ is enabled, the AFEx8101 triggers a break
command followed by data on UARTOUT (see 图7-23).
The contents of the data are listed in order of priority below.
1. If ALARM_IRQ bit is set, then the contents of the ALARM_STATUS register are output.
2. If GEN_IRQ is set, then the contents of the GEN_STATUS register are output.
3. If none of the previous bits are set, then an IRQ is not generated.
A break byte is followed by three bytes. These three bytes have information identical to the SPI frame without
the CRC (see 图 7-20). The CRC cannot be enabled for UBM. All communication characters on the UART bus
are transmitted least significant data bit (D0) first.
图 7-21 shows the data structure of the UBM write command, and 图 7-22 shows the data structure of the UBM
read command.
UART Break
UART Break Write
UART Write Data MSB
UART Write Data LSB
Par
Par
Par
UARTIN
S
Address
[0:6]
1'b0 P S
(Write)
Data
[8:15]
P S
Data
[0:7]
P
S = Start bit, Par = Parity bit, P = Stop bit
图7-21. UARTIN Break Write Data Format
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UART Read
Command
UART Break
Par
UARTIN
S
Address
[0:6]
1'b1
(Read)
P
S = Start bit, Par = Parity bit, P = Stop bit
图7-22. UARTIN Break Read Data Format
图 7-23 shows the UARTOUT data frame with details of the status bits produced by the AFEx8101. See 表 7-9
for details.
1 = Read req.
0 = IRQ event
ALARM_IRQ
GEN_IRQ
1'b0
RESET
1'b0
1'b0
1'b0
R/IRQn
Continued from UART Break Read...
UARTOUT
Status Byte
UART Read Data
UART Read Data
Par
Par
Par
S
Status
[0:7]
P S
Data
[8:15]
P S
Data
[0:7]
P
UART Break
S = Start bit, Par = Parity bit, P = Stop bit
图7-23. UARTOUT Break Data Format
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7.5.4 Status Bits
Every response, in SPI mode and UBM, from the AFEx8101 includes a set of status bits. For SPI mode bit order,
see 节7.5.2.1, and for UBM bit order, 节7.5.3.1.
表7-9. Status Bits
STATUS BIT
ALARM_IRQ
DESCRIPTION
NOTES / REFERENCE
From the GEN_STATUS(1) register (表7-33).
Also see 节7.3.4.
1h = ALARM_IRQ asserted
0h = Normal operation
CRC_ERR
1h = CRC error detect in input frame
0h = No CRC error detected
Generated by the SPI on a frame by frame basis.
(CRC enabled SPI only)
See 节7.5.2.3.
From the ALARM_STATUS(1) register (表7-32).
Also see 节7.3.4.
GEN_IRQ
1h = GEN_IRQ asserted
0h = Normal Operation
R/IRQn
1h = Read request
0h = IRQ event
Generated by the UART interface on a frame by frame basis.
(UBM only)
See 节7.5.3.1 for details.
RESET
1h = First readback after RESET
0h = All other readbacks
From the GEN_STATUS register (表7-33).
Also see 节7.4.2.
(1) ALARM_STATUS, and GEN_STATUS registers contain cross-readable IRQ flags for the other register. The ALARM_STATUS register
has the GEN_IRQ bit. GEN_STATUS has the ALARM_IRQ bit. This functionality enables the system microcontroller to always get full
status information by reading only one register, and thus save power.
7.5.5 Watchdog Timer
The AFEx8101 include a watchdog timer (WDT) that is used to make sure that communication between the
system controller and the device is not lost. The WDT checks that the device received a communication from the
system controller within a programmable period of time. To enable this feature, set WDT.WDT_EN to 1. The
WDT monitors both SPI and UBM communications.
The WDT has two limit fields: WDT.WDT_UP and WDT.WDT_LO. The WDT_UP field sets the upper time limit
for the WDT. The WDT_LO field sets the lower time limit. If the WDT_LO is set to a value other than 2’b00,
then the WDT acts as a window comparator. If the write occurs too quickly (less than the WDT_LO time), or too
slowly (greater than the WDT_UP time), then a WDT error is asserted. When acting as a window comparator, in
the event of a WDT error, the WDT resets only when a write to the WDT register occurs. If the WDT_LO is set to
2'b00, then a write to any register resets the WDT time counter. In this mode, the WDT error is asserted when
the timer expires.
If enabled, the chip must have any SPI or UBM write to the device within the programmed timeout window.
Otherwise, the ALARM pin asserts low, and the ALARM_STATUS.WD_FLT bit is set to 1. The WD_FLT bit is
sticky. After a WD_FLT has been asserted, WDT.WDT_EN must be set to 0 to clear the WDT condition. Then the
WDT can be re-enabled. The WDT condition is also cleared by issuing a software or hardware reset. After the
WDT condition is clear, WD_FLT is cleared by reading the ALARM_STATUS register.
The watchdog timeout period is based on a 1200-Hz clock (1.2288 MHz / 1024).
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7.6 Register Maps
表 7-10 lists the memory-mapped registers for the AFEx8101 registers. Consider all register offset addresses not listed in 表 7-10 as reserved locations;
do not modify these register contents.
表7-10. Register Map
BIT DESCRIPTION
ADDR
REGISTER
(HEX)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
00h
01h
NOP
NOP [15:0]
DATA [15:0]
DAC_DATA
UBM_
IRQ_EN
IRQ_
PIN_EN
CLR_
PIN_EN
02h
03h
CONFIG
RESERVED
CRC_ERR_CNT [1:0]
RESERVED
CLKO_DIV
PD
CLKO_EN RESERVED
SR_CLK [2:0]
UART_DIS RESERVED
SR_EN
CRC_EN
IRQ_POL
IRQ_LVL
CLR
DSDO
FSDO
CLR_
RANGE
DAC_CFG
SR_STEP [2:0]
SR_MODE RESERVED
RANGE
04h
05h
DAC_GAIN
GAIN [15:0]
DAC_OFFSET
OFFSET [15:0]
CODE [15:0]
DAC_CLR_
CODE
06h
07h
08h
RESET
RESERVED
HYST [6:0]
SW_RST [7:0]
AIN_
RANGE
EOC_
PER_CH
DIRECT_
MODE
ADC_CFG
BUF_PD
FLT_CNT [2:0]
STOP [3:0]
CONV_RATE [1:0]
START [3:0]
ADC_INDEX_
CFG
09h
0Ah
RESERVED
SHADOW
LOAD
TRIGGER
RESERVED
ADC
OTP_
LOAD_
SW_RST
SPECIAL_
CFG (1)
ALMV_
POL
0Bh
RESERVED
AIN1_ENB
10h
11h
ALARM_ACT
WDT
SD_FLT [1:0]
TEMP_FLT [1:0]
AIN1_FLT [1:0]
RESERVED
AIN0_FLT [1:0]
CRC_WDT_FLT [1:0]
VREF_FLT [1:0]
WDT_UP [2:0]
THERM_ERR_FLT [1:0]
THERM_WARN_FLT [1:0]
WDT_LO [1:0]
WDT_EN
AIN0_
THRESHOLD
12h
13h
14h
16h
Hi [7:0]
Hi [7:0]
Hi [7:0]
Lo [7:0]
AIN1_
THRESHOLD
Lo [7:0]
Lo [7:0]
TEMP_
THRESHOLD
REG_
MODE
UBM (2)
RESERVED
ADC_
TEMP_
FLT
THERM_
WARN_
FLT
ALARM_
STATUS_MASK
OTP_
CRC_ERR
ADC_
AIN1_FLT
ADC_
AIN0_FLT
THERM_
ERR_FLT
1Dh
1Eh
20h
RESERVED
SD_FLT
SD_FLT
OSC_FAIL
RESERVED
CRC_FLT
WD_FLT
VREF_FLT
VREF_FLT
BREAK_
FRAME_
ERR
BREAK_
PARITY_
ERR
UART_
FRAME_
ERR
UART_
PARITY_
ERR
GEN_
STATUS_MASK
SR_
BUSYn
ADC_
EOC
RESERVED
RESERVED
ADC_
TEMP_
FLT
THERM_
WARN_
FLT
ALARM_
STATUS
GEN_
IRQ
OTP_
LOADEDn
OTP_
CRC_ERR
ADC_
AIN1_FLT
ADC_
AIN0_FLT
THERM_
ERR_FLT
RESERVED
OSC_FAIL
CRC_CNT [1:0]
CRC_FLT
WD_FLT
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表7-10. Register Map (continued)
BIT DESCRIPTION
ADDR
(HEX)
REGISTER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BREAK_
FRAME_
ERR
BREAK_
PARITY_
ERR
UART
_FRAME
_ERR
UART_
PARITY_
ERR
GEN_
STATUS
ALARM_
IRQ
OTP_
BUSY
SR_
BUSYn
ADC_
EOC
ADC_
BUSY
21h
23h
RESERVED
RESERVED
RESET
PVDD_HI
TEMP_
FAIL
AIN1_
FAIL
AIN0_
FAIL
ADC_FLAGS
RESERVED
SD4_FAIL
SD3_FAIL
SD2_FAIL
SD1_FAIL
SD0_FAIL
RESERVED
24h
25h
26h
27h
28h
2Ch
2Dh
ADC_AIN0
ADC_AIN1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
DATA [11:0]
DATA [11:0]
DATA [11:0]
DATA [11:0]
DATA [11:0]
ADC_TEMP
ADC_SD_MUX
ADC_OFFSET
DAC_OUT
DATA [15:0]
ADC_OUT
RESERVED
DATA [11:0]
DATA [11:0]
DATA_
BYP_EN
OFST_
BYP_EN
DIS_GND_
SAMP
2Eh
2Fh
ADC_BYP
RESERVED
THERM_
WARN_
FLT
THERM_
ERR_FLT
SD4_HI_
FLT
SD4_LO_
FLT
SD3_HI_
FLT
SD3_LO_
FLT
SD2_HI_
FLT
SD2_LO_
FLT
SD1_HI_
FLT
SD1_LO_
FLT
SD0_HI_
FLT
SD0_LO_
FLT
FORCE_FAIL
CRC_FLT
VREF_FLT
RESERVED
(1) The SPECIAL_CFG register can only be reset with POR, and does not respond to the RESET pin or SW_RST command.
(2) The UBM register can only be accessed with a UBM command.
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7.6.1 AFEx8101 Registers
Complex bit access types are encoded to fit into small table cells. 表 7-11 shows the codes that are used for
access types in this section.
表7-11. AFEx8101 Access-Type Codes
Access Type
Code
Description
Read Type
R
R
Read
Write Type
W
W
W
W
Write
WO
WSC
Write only
Write self clear
Reset or Default Value
-n
Value after reset or the default value
Register Array Variables
i,j,k,l,m,n
When used in a register name, an offset, or an address, these variables refer to the value of a register array
where the register is part of a group of repeating registers. The register groups form a hierarchical structure
and the array is represented with a formula.
y
When used in a register name, an offset, or an address, this variable refers to the value of a register array.
7.6.1.1 NOP Register (Offset = 0h) [Reset = 0000h]
Return to the Register Map.
表7-12. NOP Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
NOP
WO
0h
No operation. Data written to this field have no effect. Always reads
zeros.
7.6.1.2 DAC_DATA Register (Offset = 1h) [Reset = 0000h]
Return to the Register Map.
DAC code for VOUT.
表7-13. DAC_DATA Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
DATA
R/W
0h
Data.
DAC code for VOUT.
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7.6.1.3 CONFIG Register (Offset = 2h) [Reset = 0036h]
Return to the Register Map.
表7-14. CONFIG Register Field Descriptions
Bit
15
Field
Type
Reset
Description
RESERVED
CRC_ERR_CNT
R
0h
14-13
R/W
0h
CRC Errors Count Limit
Sets the numbers of consecutive SPI CRC frames that must have
errors before the status bits is set.
0h = 1 (default); 1h = 2; 2h = 4; 3h = 8
12
11
CLKO_DIV
CLKO_EN
R/W
R/W
0h
0h
CLKO Divider
Divide the clock by 128 to output to CLKO.
0h = Divider disabled, output 1.2288 MHz (default)
1h = Divider enabled, output 9600 Hz
CLKO Enable
Enable the internal oscillator to be driven on CLKO pin.
0h = Disabled (default); 1h = Enabled
10
9
RESERVED
R
0h
0h
UBM_IRQ_EN
R/W
UBM IRQ Enable
Enable IRQ to be sent on UARTOUT through UBM.
0h = Disabled (default); 1h = Enabled
8
7
IRQ_PIN_EN
CLR_PIN_EN
R/W
R/W
0h
0h
IRQ Pin Enable
Enable IRQ pin functionality.
0h = Disabled (default); 1h = Enabled
Clear Input Pin Enable
Enable pin-based transition to the CLEAR state in UBM and SPI.
0h = Disabled (default); 1h = SCLR pin enabled in SPI mode or SDI
pin configured as clear input pin in UBM
6
UART_DIS
R/W
0h
UART Disable
Disable UART functionality.
0h = Disabled (default); 1h = Enabled
5
4
RESERVED
CRC_EN
R
1h
1h
Reserved. Always set this bit to 1h for proper functionality.
R/W
CRC Enable
Enable CRC for SPI.
0h = Disabled; 1h = Enabled (default)
3
2
IRQ_POL
IRQ_LVL
R/W
R/W
0h
1h
IRQ Polarity
0h = Active low (default); 1h = Active high
IRQ Level
0h = Edge sensitive
1h = Level sensitive (default)
1
0
DSDO
FSDO
R/W
R/W
1h
0h
SDO Hi-Z
0h = Drive SDO during CS = 0
1h = SDO always Hi-Z (default)
Fast SDO
SDO is driven on negative edge of SCLK.
0h = drive SDO on rising edge of SCLK (launching edge) (default)
1h = drive SDO on falling edge of SCLK (capture edge 1/2 clock
early)
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7.6.1.4 DAC_CFG Register (Offset = 3h) [Reset = 0B00h]
Return to the Register Map.
表7-15. DAC_CFG Register Field Descriptions
Bit
15-13
12
Field
Type
R/W
R/W
Reset
Description
RESERVED
PD
0h
0h
DAC Output Buffer Power-down
DAC output set to Hi-Z in power-down.
0h = DAC output buffer enabled (default)
1h = DAC output buffer disabled
11-9
SR_CLK
R/W
5h
Slew Clock Rate
0h = 307.2 kHz
1h = 153.6 kHz
2h = 76.8 kHz
3h = 38.4 kHz
4h = 19.2 kHz
5h = 9600 Hz (default)
6h = 4800 Hz
7h = 2400 Hz
8-6
SR_STEP
R/W
4h
Slew Step Size
0h = 1 code
1h = 2 codes
2h = 4 codes
3h = 8 codes
4h = 16 codes (default)
5h = 32 codes
6h = 64 codes
7h = 128 codes
5
4
SR_EN
R/W
R/W
0h
0h
Slew Enable
Enables slew on the output voltage.
0h = Disabled (default)
1h = Enabled
SR_MODE
Slew Mode
Output slew rate mode select.
0h = Linear Slew (default)
1h = Sinusoidal Slew
3
2
RESERVED
CLR
R
0h
0h
R/W
CLEAR State
0h = Normal operation (default)
1h = Force the DAC to the CLEAR state
1
0
CLR_RANGE
RANGE
R/W
R/W
0h
0h
Clear Range
Sets DAC CLEAR state output range.
0h = 0.15 V to 1.25 V (default)
1h = 0.2 V to 1.0 V
Range
Sets DAC output range during normal operation.
0h = 0.15 V to 1.25 V (default)
1h = 0.2 V to 1.0 V
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7.6.1.5 DAC_GAIN Register (Offset = 4h) [Reset = 8000h]
Return to the Register Map.
表7-16. DAC_GAIN Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
GAIN
R/W
8000h
Gain
Set the gain of the DAC output from 0.5 –1.499985.
For example:
0000h = 0.5
8000h = 1.0 (default)
FFFFh = 1.499985
7.6.1.6 DAC_OFFSET Register (Offset = 5h) [Reset = 0000h]
Return to the Register Map.
表7-17. DAC_OFFSET Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
OFFSET
R/W
0h
Offset
Adjust the offset of the DAC output, 2's complement number.
For example:
0000h = 0 (default)
FFFFh = –1
7.6.1.7 DAC_CLR_CODE Register (Offset = 6h) [Reset = 0000h]
Return to the Register Map.
表7-18. DAC_CLR_CODE Register Field Descriptions
Bit
Field
Type
Reset
Description
CLEAR State DAC Code
DAC code applied in the CLEAR state. See 节7.3.1.6.
15-0
CODE
R/W
0h
7.6.1.8 RESET Register (Offset = 7h) [Reset = 0000h]
Return to the Register Map.
表7-19. RESET Register Field Descriptions
Bit
15-8
7-0
Field
Type
Reset
Description
RESERVED
SW_RST
R
0h
WSC
0h
Software Reset
Write ADh to initiate software reset.
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7.6.1.9 ADC_CFG Register (Offset = 8h) [Reset = 8810h]
Return to the Register Map.
表7-20. ADC_CFG Register Field Descriptions
Bit
Field
Type
Reset Description
15
BUF_PD
R/W
1h
8h
ADC Buffer Power-down
0h = ADC buffer enabled; 1h = ADC buffer powered down (default)
14-8 HYST
R/W
R/W
R/W
Hysteresis
The number of codes of hysteresis used when a threshold is exceeded for an ADC
measurement of AIN0/AIN1/TEMP.
7-5
4
FLT_CNT
0h
1h
Fault Count
Number of successive faults to trip an alarm.
Number of successive faults is programmed value + 1 (1-8 faults).
AIN_RANGE
ADC Analog Input Range
Can only be set if PVDD ≥2.7 V to use 2.5-V range for AIN0 and AIN1 inputs.
0h = 2 × VREF; 1h = 1 × VREF (default)
3
EOC_PER_CH
CONV_RATE
R/W
R/W
0h
0h
ADC End-of-Conversion for Every Channel
Sends an EOC pulse at the end of each channel instead of at the end of all the channels.
0h = EOC after last channel (default); 1h = EOC for every channel
2-1
ADC Conversion Rate
This setting only affects the conversion rate for channels AIN0 and AIN1. Rates are based
on a 76.8-kHz ADC clock. All other channels use 2560 Hz.
0h = 3840 Hz (default)
1h = 2560 Hz
2h = 1280 Hz
3h = 640 Hz
0
DIRECT_MODE R/W
0h
Direct Mode Enable
0h = Auto mode (default); 1h = Direct mode
7.6.1.10 ADC_INDEX_CFG Register (Offset = 9h) [Reset = 0080h]
The ADC custom channel sequencing configuration is shown in 表7-21.
Return to the Register Map.
表7-21. ADC_INDEX_CFG Register Field Descriptions
Bit
Field
Type
R
Reset Description
15-8 RESERVED
0h
7-4
STOP
R/W
8h
Custom Channel Sequencer Stop Index
CCS index to stop ADC sequence. Must be ≥START. If not, STOP is forced to = START.
0h = OFFSET
1h = AIN0
2h = AIN1
3h = TEMP
4h = SD0 (VREF)
5h = SD1 (PVDD)
6h = SD2 (VDD)
7h = SD3 (ZTAT)
8h = SD4 (VOUT) (default)
9h through Fh = GND
3-0
START
R/W
0h
Custom Channel Sequencer Start Index
CCS index to start ADC sequence.
0h through Fh = Same as STOP field (0h is default)
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7.6.1.11 TRIGGER Register (Offset = Ah) [Reset = 0000h]
Return to the Register Map.
表7-22. TRIGGER Register Field Descriptions
Bit
15-2
1
Field
Type
Reset
Description
RESERVED
SHADOWLOAD
R
0h
WSC
0h
Shadowload Trigger
This trigger initiates the loading of the OTP array into the parallel
latches. If an OTP CRC error is detected, assert this trigger to try
and reload the OTP into the memory locations.
0
ADC
WSC
0h
ADC Trigger
In auto mode, this bit enables or disables the conversions. Manually
set 1 (enable) and 0 (disable). In direct mode, setting this bit starts a
conversion sequence. The bit is cleared at the end of the sequence.
To stop a sequence prematurely, manually clear this bit.
7.6.1.12 SPECIAL_CFG Register (Offset = Bh) [Reset = 0000h]
Return to the Register Map.
表7-23. SPECIAL_CFG Register Field Descriptions
Bit
15-3
2
Field
Type
Reset
Description
RESERVED
OTP_LOAD_SW_RST
R
0h
R/W
0h
0h
OTP (One Time Programmable Factory Trimmed Registers) LOAD
with SW RESET
OTP reloads with the assertion of a software reset (SW_RST).
0h = No reload with SW_RST
1h = Reload with SW_RST
1
ALMV_POL
R/W
Alarm Voltage Polarity
This register bit is ORed with the POL_SEL/AIN1 pin (if AIN1_ENB
bit is low) to control the VOUT during a hardware reset condition or if
alarm is active and alarm action is set appropriately. The following
Boolean function is implemented for the internal signal
ALMV_POL_o that sets the VOUT voltage:
ALMV_POL_o = ALMV_POL OR (POL_SEL/AIN1 AND NOT
AIN1_ENB)
0h = Low (0 V)
1h = High (2.5 V)
0
AIN1_ENB
R/W
0h
AIN1 Pin Enable
This bit determines whether the POL_SEL/AIN1 pin acts as alarm
voltage polarity control bit or an input channel to the ADC.
0h = AIN1 pin acts as alarm voltage polarity bit and ADC converts
GND
1h = AIN1 pin is an active channel to the ADC
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7.6.1.13 ALARM_ACT Register (Offset = 10h) [Reset = 8020h]
Return to the Register Map.
表7-24. ALARM_ACT Register Field Descriptions
Bit
Field
Type
Reset Description
15-14 SD_FLT
R/W
2h
Self-Diagnostic Fault Action
These bits set the device action after a self-diagnostic fault.
0h = No Action
1h = Set DAC to CLEAR state
2h = Switch to alarm voltage determined by ALMV_POL (default)
3h = Place DAC into Hi-Z (power-down)
13-12 TEMP_FLT
11-10 AIN1_FLT
R/W
R/W
R/W
0h
0h
0h
TEMP Fault Action
These bits set the device action if the ADC temperature is outside the
TEMP_THRESHOLD Hi or Lo thresholds.
0h through 3h = Same as SD_FLT field (default 0h)
AIN1 Fault Action
These bits set the device action if the ADC AIN1 channel is outside the
AIN1_THRESHOLD Hi or Lo thresholds.
0h through 3h = Same as SD_FLT field (default 0h)
9-8
AIN0_FLT
AIN0 Fault Action
These bits set the device action if the ADC AIN0 channel is outside the
AIN0_THRESHOLD Hi or Lo thresholds.
0h through 3h = Same as SD_FLT field (default 0h)
7-6
5-4
3-2
1-0
CRC_WDT_FLT
VREF_FLT
R/W
R/W
R/W
0h
2h
0h
0h
CRC and WDT Fault Action
These bits set the device action when a SPI CRC or SPI Watchdog Timeout error occurs.
0h through 3h = Same as SD_FLT field (default 0h)
VREF Fault Action
These bits set the device action when a fault is detected on VREF.
0h through 3h = Same as SD_FLT field a
THERM_ERR_FLT
Thermal Error Fault Action
These bits set the device action when a high temperature error occurs (> 130°C).
0h through 3h = Same as SD_FLT field (default 0h)
THERM_WARN_FLT R/W
Thermal Warning Fault Action
These bits set the device action when a high temperature warning occurs (> 85°C).
0h through 3h = Same as SD_FLT field (default 0h)
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7.6.1.14 WDT Register (Offset = 11h) [Reset = 0018h]
Return to the Register Map.
表7-25. WDT Register Field Descriptions
Bit
15-6
5-3
Field
Type
Reset
Description
RESERVED
WDT_UP
R
0h
R/W
3h
Watchdog Timer (WDT) Upper Limit
If the WDT is enabled and the timer exceeds the programmed value,
a WDT error is asserted. All times are based on 1200-Hz clock
(1.2288 MHz / 1024).
0h = 53 ms (64 clocks)
1h = 106 ms (128 clocks)
2h = 427 ms (512 clocks)
3h = 853 ms (1024 clocks, default)
4h = 1.7 s (2048 clocks)
5h = 2.56 s (3072 clocks)
6h = 3.41 s (4096 clocks)
7h = 5.12 s (6144 clocks)
2-1
WDT_LO
R/W
0h
WDT Lower Limit
If the WDT is enabled and the WDT Lower Limit is enabled, then
only a write to this register resets the WDT timer. If the write occurs
before the WDT Lower Limit time, or after the WDT Upper Limit time,
then a WDT error is asserted. If WDT Lower Limit is disabled, then a
write to any register resets the timer. This is true for both SPI and
UART Break modes. All times are based on 1200-Hz clock
(1.2288 MHz / 1024).
0h = Disabled (default)
1h = 53 ms (64 clocks)
2h = 106 ms (128 clocks)
3h = 427 ms (512 clocks)
0
WDT_EN
R/W
0h
WDT Enable
0h = Disabled (default); 1h = Enabled
7.6.1.15 AIN0_THRESHOLD Register (Offset = 12h) [Reset = FF00h]
Return to the Register Map.
表7-26. AIN0_THRESHOLD Register Field Descriptions
Bit
Field
Type
Reset
Description
15-8
Hi
R/W
FFh
High Threshold for Channel AIN0 {[11:4],4b1111}
This value is compared (>) against AIN0 data bits[11:0].
7-0
Lo
R/W
0h
Low Threshold for Channel AIN0 {[11:4],4b0000}
This value is compared (<) against AIN0 data bits[11:0].
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7.6.1.16 AIN1_THRESHOLD Register (Offset = 13h) [Reset = FF00h]
Return to the Register Map.
表7-27. AIN1_THRESHOLD Register Field Descriptions
Bit
Field
Type
Reset
Description
15-8
Hi
R/W
FFh
High Threshold for Channel AIN1 {[11:4],4b1111}
This value is compared (>) against AIN1 data bits[11:0].
7-0
Lo
R/W
0h
Low Threshold for Channel AIN1 {[11:4],4b0000}
This value is compared (<) against AIN1 data bits[11:0].
7.6.1.17 TEMP_THRESHOLD Register (Offset = 14h) [Reset = FF00h]
Return to the Register Map.
表7-28. TEMP_THRESHOLD Register Field Descriptions
Bit
Field
Type
Reset
Description
15-8
Hi
R/W
FFh
High Threshold for Channel TEMP {[11:4],4b1111}
This value is compared (>) against TEMP data bits[11:0].
7-0
Lo
R/W
0h
Low Threshold for Channel TEMP {[11:4],4b0000}
This value is compared (<) against TEMP data bits[11:0].
7.6.1.18 UBM Register (Offset = 16h) [Reset = 0000h]
Return to the Register Map.
表7-29. UBM Register Field Descriptions
Bit
15-1
0
Field
Type
Reset
Description
RESERVED
REG_MODE
R
0h
R/W
0h
Register Mode
Configure the rest of the Register Map to be accessed by UART
break mode (UBM) or SPI. This register can only be written by the
UART Break communication.
0h = SPI Mode (default)
1h = UART Break Mode
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7.6.1.19 ALARM_STATUS_MASK Register (Offset = 1Dh) [Reset = EFDFh]
Return to the Register Map.
表7-30. ALARM_STATUS_MASK Register Field Descriptions
Bit
15-14
13
Field
Type
Reset
Description
RESERVED
SD_FLT
R
3h
R/W
1h
SD Fault Mask
0h = Fault asserts IRQ
1h = The mask prevents IRQ or Alarm being triggered (default).
The status is always set if the condition exists.
12
OSC_FAIL
R/W
0h
OSC_FAIL Fault Mask
Same as SD Fault Mask (default 0h).
11-9
8
RESERVED
R
7h
1h
OTP_CRC_ERR
R/W
OTP CRC Error Mask
Same as SD Fault Mask (default 1h).
7
6
5
4
3
2
1
0
CRC_FLT
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1h
1h
0h
1h
1h
1h
1h
1h
SPI CRC Fault Mask
Same as SD Fault Mask (default 1h).
WD_FLT
Watchdog Fault Mask
Same as SD Fault Mask (default 1h).
VREF_FLT
VREF Fault Mask
Same as SD Fault Mask (default 0h).
ADC_AIN1_FLT
ADC_AIN0_FLT
ADC_TEMP_FLT
THERM_ERR_FLT
THERM_WARN_FLT
ADC AIN1 Fault Mask
Same as SD Fault Mask (default 1h).
ADC AIN0 Fault Mask
Same as SD Fault Mask (default 1h).
ADC TEMP Fault Mask
Same as SD Fault Mask (default 1h).
Temperature > 130°C Error Mask
Same as SD Fault Mask (default 1h).
Temperature > 85°C Warning Mask
Same as SD Fault Mask (default 1h).
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7.6.1.20 GEN_STATUS_MASK Register (Offset = 1Eh) [Reset = FFFFh]
Return to the Register Map.
表7-31. GEN_STATUS_MASK Register Field Descriptions
Bit
15-8
7
Field
Type
Reset
FFh
1h
Description
RESERVED
SR_BUSYn
R
R/W
Slew Rate Not Busy Mask
0h = Fault asserts IRQ
1h = The mask prevents IRQ or Alarm being triggered (default).
The status is always set if the condition exists.
6
ADC_EOC
R/W
1h
ADC End Of Conversion Mask
Same as Slew Rate Not Busy Mask (default 1h).
5-4
3
RESERVED
R
3h
1h
BREAK_FRAME_ERR
R/W
Break Frame Error Fault Mask
Same as Slew Rate Not Busy Mask (default 1h).
2
1
0
BREAK_PARITY_ERR
UART_FRAME_ERR
UART_PARITY_ERR
R/W
R/W
R/W
1h
1h
1h
Break Parity Error Fault Mask
Same as Slew Rate Not Busy Mask (default 1h).
UART Frame Error Fault Mask
Same as Slew Rate Not Busy Mask (default 1h).
UART Parity Error Fault Mask
Same as Slew Rate Not Busy Mask (default 1h).
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7.6.1.21 ALARM_STATUS Register (Offset = 20h) [Reset = 0200h]
Return to the Register Map.
表7-32. ALARM_STATUS Register Field Descriptions
Bit
Field
Type
Reset Description
15
GEN_IRQ
R
0h
General IRQ OR of all the unmasked bits in the GEN_STATUS register.
0h = All of the unmasked bits of the GEN_STATUS register are low
1h = At least one of the unmasked bits in the GEN_STATUS register is high
14
13
RESERVED
SD_FLT
R
R
0h
0h
Self Diagnostic (SD) Fault
0h = All self diagnostic channels are within threshold limits
1h = At least one of the self diagnostic channels has failed
12
OSC_FAIL
R
0h
Oscillator Fault Oscillator failed to start. This bit holds ALARM low and does not feed
IRQ.
0h = Oscillator started; 1h = Oscillator has failed to start
11-10 CRC_CNT
R
R
0h
1h
CRC Fault Counter
If counter limit ≤4 then bits[1:0] of the counter are shown here.
If the counter limit = 8 then bits[2:1] of the counter are shown.
9
8
7
6
5
4
OTP_LOADEDn
OTP NOT Loaded Clears when OTP has loaded at least once.
Keeps ALARM asserted until OTP finishes loading. Does not feed IRQ.
0h = OTP has loaded at least once; 1h = OTP has not finished loading
OTP_CRC_ERR
CRC_FLT
R
R
R
R
R
0h
0h
0h
0h
0h
OTP CRC Error Maskable fault. An error occurred with the OTP CRC calculation.
Sticky, cleared by reading register, unless condition still persist.
0h = No OTP CRC fault; 1h = OTP CRC fault
CRC Fault Maskable fault. Invalid CRC value transmitted during SPI frame.
Sticky, cleared by reading register, unless condition still persist.
0h = No CRC fault; 1h = CRC fault
WD_FLT
Watchdog Timer Fault
Maskable fault. Sticky, cleared by reading register, unless condition still persist.
0h = No watchdog fault; 1h = Watchdog fault
VREF_FLT
Invalid Reference Voltage Maskable fault. OR with FORCE_FAIL.VREF_FLT bit.
Active signal, set as long as condition is true. Direct input from analog circuit.
0h = Valid VREF voltage; 1h = Invalid VREF voltage
ADC_AIN1_FLT
ADC AIN1 Fault. Maskable fault.
0h = AIN1 ADC measurement within threshold limits
1h = AIN1 ADC measurement outside threshold limits
3
2
1
ADC_AIN0_FLT
ADC_TEMP_FLT
THERM_ERR_FLT
R
R
R
0h
0h
0h
ADC AIN0 Fault. Maskable fault.
0h = AIN0 ADC measurement within threshold limits
1h = AIN0 ADC measurement outside threshold limits
ADC Temp Fault. Maskable fault.
0h = TEMP ADC measurement within threshold limits
1h = TEMP ADC measurement outside threshold limits
Temperature > 130°C error. Maskable fault.
OR with FORCE_FAIL.THERM_ERR_FLT bit.
Active signal, set as long as condition is true. Direct input from analog circuit.
0h = Temperature ≤130°C; 1h = Temperature > 130°C
0
THERM_WARN_FLT R
0h
Temperature > 85°C warning. Maskable fault.
OR with FORCE_FAIL.THERM_WARN_FLT bit.
Active signal, set as long as condition is true. Direct input from analog circuit.
0h = Temperature ≤85°C; 1h = Temperature > 85°C
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7.6.1.22 GEN_STATUS Register (Offset = 21h) [Reset = 1180h]
Return to the Register Map.
表7-33. GEN_STATUS Register Field Descriptions
Bit
Field
Type
Reset Description
15
ALARM_IRQ
R
0h
Alarm IRQ OR of all the unmasked bits in the ALARM_STATUS register.
0h = All of the unmasked bits of the ALARM_STATUS register are low
1h = At least one of the unmasked bits in the ALARM_STATUS register is high
14-13
12
R
R
0h
1h
RESERVED
OTP_BUSY
OTP Busy Status = 1h at power up while the OTP is being loaded into the trim latches.
0h = OTP has completed loading into the device
1h = OTP is being loaded into the device
11
RESERVED
R
R
R
0h
0h
1h
11-9 RESERVED
8
RESET
Device Reset Occurred. Status only. Does not feed IRQ.
Sticky, cleared by reading register, unless condition still persist.
0h = Device has not reset since last read of register
1h = Device has reset since last read of register
7
SR_BUSYn
R
1h
Slew Rate Not Busy. Maskable fault.
0h = DAC is slewing to the target code
1h = DAC_OUT has reached the DAC_DATA.
If slew rate is disabled, then this signal produces a rising edge within 3 internal clock
cycles. If slew rate is enabled, this signal creates an IRQ event when the DAC_OUT has
reached the DAC_DATA. At this time, slew rate can be safely disabled. If slew rate is
disabled prior to DAC_OUT = DAC_DATA then a jump of DAC_OUT occurs. This can
cause an unwanted fast transition on VOUT.
6
ADC_EOC
R
0h
ADC End of Conversion (EOC). Maskable fault.
Sticky, cleared by reading register, unless condition still persist.
0h = No EOC since last read of register; 1h = ADC end of conversion
5
4
3
ADC_BUSY
PVDD_HI
R
R
R
0h
0h
0h
ADC Busy. Status only. Does not feed IRQ. Active signal, set as long as condition is true.
0h = No ADC activity; 1h = ADC is actively converting
PVDD High. Status only. Does not feed IRQ. Set as long as condition is true.
0h = PVDD < 2.7 V; 1h = PVDD ≥2.7V
BREAK_
FRAME_ERR
Incorrect Stop Bit During Break Character. Maskable fault. Applies to UARTIN.
Sticky, cleared by reading register, unless condition still persist.
0h = No break frame error; 1h = Break frame error
2
1
0
BREAK_
PARITY_ERR
R
R
R
0h
0h
0h
Incorrect parity (ODD) bit during break character. Maskable fault. Applies to UARTIN.
Sticky, cleared by reading register, unless condition still persist.
0h = No break parity error; 1h = Break parity error
UART_
FRAME_ERR
Incorrect stop bit during UART character. Maskable fault. Applies to UARTIN.
Sticky, cleared by reading register, unless condition still persist.
0h = No UART frame error; 1h = UART frame error
UART_
PARITY_ERR
Incorrect parity (ODD) bit during UART character. Maskable fault. Applies to UARTIN.
Sticky, cleared by reading register, unless condition still persist.
0h = No UART parity error; 1h = UART parity error
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7.6.1.23 ADC_FLAGS Register (Offset = 23h) [Reset = 0000h]
Return to the Register Map.
The limits for Self Diagnostic (SD) Alarm ADC Thresholds are shown in 表7-7.
表7-34. ADC_FLAGS Register Field Descriptions
Bit
15-9
8
Field
Type
Reset
Description
RESERVED
SD4_FAIL
SD3_FAIL
SD2_FAIL
SD1_FAIL
SD0_FAIL
TEMP_FAIL
AIN1_FAIL
AIN0_FAIL
RESERVED
R
0h
R
0h
SD4 (VOUT) Limit Fail
SD3 (ZTAT) Limit Fail
SD2 (VDD) Limit Fail
SD1 (PVDD) Limit Fail
SD0 (VREF) Limit Fail
TEMP Limit Fail
7
R
0h
6
R
0h
5
R
0h
4
R
0h
3
R
0h
2
R
0h
AIN1 Limit Fail
1
R
0h
AIN0 Limit Fail
0
R
0h
7.6.1.24 ADC_AIN0 Register (Offset = 24h) [Reset = 0000h]
Return to the Register Map.
表7-35. ADC_AIN0 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
11-0
RESERVED
DATA
R
0h
R
0h
Converted Value of Voltage on Pin AIN0
7.6.1.25 ADC_AIN1 Register (Offset = 25h) [Reset = 0000h]
Return to the Register Map.
表7-36. ADC_AIN1 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
11-0
RESERVED
DATA
R
0h
R
0h
Converted Value of Voltage on Pin AIN1
7.6.1.26 ADC_TEMP Register (Offset = 26h) [Reset = 0000h]
Return to the Register Map.
表7-37. ADC_TEMP Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
11-0
RESERVED
DATA
R
0h
R
0h
Converted Value of Temperature
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7.6.1.27 ADC_SD_MUX Register (Offset = 27h) [Reset = 0000h]
Return to the Register Map.
表7-38. ADC_SD_MUX Register Field Descriptions
Bit
Field
Type
Reset
0h
0h
Description
15-12
11-0
RESERVED
DATA
R
R
Converted Value of Voltage on Self-Diagnostic (SD) MUX Input
7.6.1.28 ADC_OFFSET Register (Offset = 28h) [Reset = 0000h]
Return to the Register Map.
表7-39. ADC_OFFSET Register Field Descriptions
Bit
Field
Type
Reset
0h
0h
Description
15-12
11-0
RESERVED
DATA
R
R
ADC Comparator Offset
This value reports the offset measured in the device, and can be
used to adjust each conversion value. If ADC_BYP.OFST_BYP_EN
is set, then the value in ADC_BYP.DATA is used as the offset. This
value is not affected by ADC_BYP.
7.6.1.29 DAC_OUT Register (Offset = 2Ch) [Reset = 0000h]
Return to the Register Map.
表7-40. DAC_OUT Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
DATA
R
0h
DAC Code Applied to the Analog Circuit
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7.6.1.30 ADC_OUT Register (Offset = 2Dh) [Reset = 0000h]
Return to the Register Map.
表7-41. ADC_OUT Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
11-0
RESERVED
DATA
R
0h
R
0h
ADC Data for Each Conversion
Does not include ADC_OFFSET.DATA adjustment. Is not affected by
ADC_BYP.DATA.
7.6.1.31 ADC_BYP Register (Offset = 2Eh) [Reset = 0000h]
ADC_BYP is shown in ADC_BYP Register Field Descriptions.
Return to the Register Map.
表7-42. ADC_BYP Register Field Descriptions
Bit
Field
Type
Reset
Description
15
DATA_BYP_EN
R/W
0h
Data Bypass Enable
Applies ADC_BYP.DATA to the ADC channel being converted.
ADC_OFFSET is ignored. Do not set OFST_BYP_EN and
DATA_BYP_EN at the same time. If OFST_BYP_EN is also set,
OFST_BYP_EN takes priority over DATA_BYP_EN. In this case,
ADC_BYP.DATA is used for the ADC_OFFSET register, and
DATA_BYP_EN is forced to 0. After a channel is converted, the
ADC_BYP.DATA value appears in the readback register and is used
to calculate faults.
0h = Data bypass disabled (default)
1h = Data bypass enabled
14
13
OFST_BYP_EN
DIS_GND_SAMP
R/W
R/W
0h
0h
Offset Bypass Enable
Overrides the offset register with the ADC_BYP.DATA value. When
using this bit, the ADC_BYP.DATA field is processed as 2's
complement. Do not set OFST_BYP_EN and DATA_BYP_EN at the
same time.
0h = Offset bypass disabled (default)
1h = Offset bypass enabled
Disable GND Sampling
This bit disables the sampling of GND during SAR activity. The
sampling of GND is used to fully discharge the sampling CAP to
reduce channel crosstalk.
0h = GND sampling enabled (default)
1h = GND sampling disabled
12
RESERVED
DATA
R
0h
0h
11-0
R/W
Bypass Data
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7.6.1.32 FORCE_FAIL Register (Offset = 2Fh) [Reset = 0000h]
Return to the Register Map.
Force failures for fault detection.
表7-43. FORCE_FAIL Register Field Descriptions
Bit
Field
Type
Reset
Description
15
CRC_FLT
R/W
0h
Force CRC Failure on SDO by Inverting the CRC Byte
0h = No force failure of CRC (default)
1h = Force failure of CRC
14
13
12
VREF_FLT
R/W
R/W
R/W
0h
0h
0h
Force Reference Voltage Failure. Analog signal.
0h = No force failure of VREF (default)
1h = Force failure of VREF
THERM_ERR_FLT
THERM_WARN_FLT
Force Temperature > 130°C Thermal Error. Analog signal.
0h = No force temperature > 130°C error (default)
1h = Force temperature > 130°C error
Force Temperature > 85°C thermal Warning. Analog signal.
0h = No force temperature > 85°C warning (default)
1h = Force temperature > 85°C warning
11-10
9
RESERVED
SD4_HI_FLT
R/W
R/W
0h
0h
SD4 (VOUT) High Limit Failure. ADC measurement.
0h = No force failure of SD4 (VOUT) (default)
1h = Force failure of SD4 (VOUT)
8
7
6
5
4
3
2
1
0
SD4_LO_FLT
SD3_HI_FLT
SD3_LO_FLT
SD2_HI_FLT
SD2_LO_FLT
SD1_HI_FLT
SD1_LO_FLT
SD0_HI_FLT
SD0_LO_FLT
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
0h
0h
SD4 (VOUT) Low limit failure. ADC measurement.
0h = No force failure of SD4 (VOUT) (default)
1h = Force failure of SD4 (VOUT)
SD3 (ZTAT) High Limit Failure. ADC measurement.
0h = No force failure of SD3 (ZTAT) (default)
1h = Force failure of SD3 (ZTAT)
SD3 (ZTAT) Low Limit Failure. ADC measurement.
0h = No force failure of SD3 (ZTAT) (default)
1h = Force failure of SD3 (ZTAT)
SD2 (VDD) High Limit Failure. ADC measurement.
0h = No force failure of SD2 (VDD) (default)
1h = Force failure of SD2 (VDD)
SD2 (VDD) Low Limit Failure. ADC measurement.
0h = No force failure of SD2 (VDD) (default)
1h = Force failure of SD2 (VDD)
SD1 (PVDD) High Limit Failure. ADC measurement.
0h = No force failure of SD1 (PVDD) (default)
1h = Force failure of SD1 (PVDD)
SD1 (PVDD) Low Limit Failure. ADC measurement.
0h = No force failure of SD1 (PVDD) (default)
1h = Force failure of SD1 (PVDD)
SD0 (VREF) High Limit Failure. ADC measurement.
0h = No force failure of SD0 (VREF) (default)
1h = Force failure of SD0 (VREF)
SD0 (VREF) Low Limit Failure. ADC measurement.
0h = No force failure of SD0 (VREF) (default)
1h = Force failure of SD0 (VREF)
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The AFEx8101 are extremely low-power 16-bit and 14-bit voltage output DACs. The DACs support a low output
range of 0.15 V to 1.25 V or a high output range of 0.3 V to 2.5 V. These devices have an onboard oscillator and
an optional precision internal reference. Use these output values with a voltage-to-current (V-to-I) converter
stage for 4-mA to 20-mA, loop-powered applications. These devices also feature a SAR ADC that is used to
measure internal and external nodes for making diagnostic measurements with fault detection and alarm actions.
Use these diagnostic measurements together with the CRC and watchdog timer monitoring for device and
system monitoring for functional safety.
The AFEx8101 can operate using extremely low power with 1.8-V supplies. For low-voltage operation, use
PVDD with a 1.8-V nominal supply and an operating range of 1.71 V to 1.89 V. Run the digital interface supply,
IOVDD, from 1.71 V to 5.5 V. During low-voltage operation, the VDD LDO is automatically disabled and VDD is
tied to PVDD. Low-voltage operation allows for both lower power for field transmitter applications and better
voltage compliance when there are high resistances in the loop.
With higher-supply operation, the PVDD has an operating range of 2.7 V to 5.5 V. With this range of operation,
the VDD is powered from an onboard LDO.
8.1.1 Multichannel Configuration
Because CS low is required for communication and SDO can be set to a tri-state condition, only individual CS
signals are required from the microcontroller for all the AFEx8101 devices in the system. The SDI, SDO, and
SCLK signals can be combined. All the individual ALARM pins can be wired-OR together. This minimizes the
number of microcontroller GPIO signals required for communication, as well as the number of isolation channels
for isolated systems. The multichannel configuration block diagram is shown in 图8-1.
Microcontroller
AFE #1
SCLK
SDI
SCLK
DOUT
DIN
SDO
ALARM
CS
ALARM
GPIO1
GPIO2
GPIO3
AFE #2
SCLK
SDI
SDO
ALARM
CS
AFE #3
SCLK
SDI
SDO
ALARM
CS
图8-1. Multichannel Configuration
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8.2 Typical Application
This design example shows a loop-powered, 4-mA to 20-mA field transmitter featuring the AFE88101. The
AFE78101 can also be used in this design for lower-resolution applications.
This design example combines several circuit elements to create a subsystem that can support most field
sensors in two-wire, current-loop applications. The design accepts bus voltages from 12 V to 36 V, while
regulating the loop-current representation of a sensor to a post-calibration accuracy of less than 0.1% full-scale
range (FSR) of total error at room temperature. The high integration in the system allows for a compact circuit,
making this device an excellent choice for field transmitters where space is a concern. In field-transmitter
applications, the current-loop transmitter, microcontroller, sensors, and analog front end are all required to
consume less than the minimum bus current of 3 mA. Use an integrated DC/DC converter in the system to
extend the current budget and allow more current for sensors and the AFE.
图8-2 shows the schematic diagram for the loop-powered, 4-mA to 20-mA field transmitter.
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8.2.1 4-mA to 20-mA Current Transmitter
PWR ISO
22 μF
1 μF
1 k
LOOP+
510
3V ISO
TPS7A0230P
4.7 μF
OUT
IN
4
3
249 k
1 k
Q1
8.2
1
TPS60402
10
EN
2
5
GND
PZT2907A
Q2
6.8 μF
3.6-V Zener
3V3
5
CFLY+ CFLY-
3
Q3
1 μF
4.7 μF
Thermal Pad
1
OUT
IN
2
560 pF
1 μF
GND
4
3V3
4.7 μF
10 μF
10 μF
499 k
499 k
GND
ISO GND ISO GND
ISO GND
4.7 μF
330 k
200 k
GND
GND
GND
ISO GND
10 μF
GND
GND
GND
3V3
GND
GND
ISOLATION
100 nF 100 nF
GND
GND
AFE88101
3V ISO
3V3
ISO7021
100 nF
100 nF
1
2
3
4
8
7
6
5
12 IOVDD
17 PVDD
21
22
GND
GND
GND
GND
ISO GND
ALARM
RESET
ISO GND
VCC1
OUTA
INB
VCC2
INA
FB1
3V3
15.8
5
REF_EN
AIN0
GND
GND
OUTB
GND2
100 k
680 pF
GND
13 VDD
AIN0 15
GND1
2.2 μF
0
POL_SEL/AIN1 16
300 pF
300 pF
3V ISO
3V3
ISO7041
24 ALARM
100 nF
100 nF
1
2
3
4
5
6
7
8
16
6
RESET
ISO GND
ISO GND
GND
GND
VCC1
GND1
VCC2
100 nF
GND2 15
VREFIO 19
GND
GND
CD-MBL206SL
3V3
100 nF
SCLK
14
13
12
7
SCLK
INA
INB
OUTA
OUTB
OUTC
CS
SDI
10 CS
FB2
OPA333
8
9
SDI
NC 23
+
INC
Q4
1 k
100 k
–
SDO
OUTD
IND 11
SDO
VOUT 18
10
9
EN1
EN2
GND
GND
GND
2
1
UARTOUT
UARTIN
ISO GND
ISO GND
GND
GND
GND
11
GND1
GND2
CLK_OUT
40.2
40.2 k
40 M
3V ISO
3V3
ISO7021
100 nF
100 nF
LOOP-
3
4
NC
GND
14
1
2
3
4
8
7
6
5
VCC1
OUTA
INB
VCC2
INA
UARTOUT
UARTIN
REF_GND 10
SCLR
OUTB
GND2
40.2 k
GND
GND
ISO GND
GND1
3V3
100 nF
GND
40.2 k
+
–
AIN0
OPA333
GND
GND
图8-2. AFEx8101 in a 4-mA to 20-mA Current Transmitter
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8.2.1.1 Design Requirements
The design requirements are:
• Transmitter with a current output range of 4 mA to 20 mA for a process variable signal
• Out-of-range current output capability from 3 mA to 25 mA for error or fault signal levels
• Operation with standard industrial automation supply voltages from 12 V to 30 V
• Current and voltage outputs with TUE less than 0.5% at 25°C
• Total on-board current must be less than or equal to 3 mA
8.2.1.2 Detailed Design Procedure
图8-3 shows a block diagram of a loop-powered, 4-mA to 20-mA current transmitter.
Power
and
Start-Up and
V-to-I
Loop
Protection
LDO
Boost
LDO
+VTERMINAL
Digital
Isolation
Converter
4-mA to
20-mA
Loop
Sensor
and
AFE
MCU
MSP430FR5969
AFE88101
Terminals
–VTERMINAL
Constructed Section of the Circuit
图8-3. Block Diagram of a Loop-Powered, 4-mA to 20-mA Current Transmitter
The terminals connected to the loop are shown on the right side of the block diagram. This connection to the
loop powers the entire transmitter. A bridge rectifier at the input protects against reverse connection to the loop.
The rectified loop voltage powers a start-up circuit that provides power to an LDO, that in turn powers the
AFE88101. The LDO powers a flyback converter acting as a boost and supplies power across an isolation
barrier. On the other side of the isolation barrier, another LDO powers the MCU and any sensor connected to the
transmitter. The LDOs also power the digital signal isolation on each side of the barrier.
The AFE88101 controls the loop current through the voltage-to-current (V-to-I) converter block. The DAC voltage
sets the output from 0.3 V to 2.5 V. The output is sent through a V-to-I converter block using an OPA333 and an
NPN bipolar junction transistor (BJT).
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8.2.1.2.1 Start-Up Circuit
When the loop is applied to the terminals, the loop power starts up the board. Transistor Q4 from 图 8-2 pulls
current from the start-up and current-shunt regulator sections of the transmitter. The start-up circuit is shown in
图8-4.
LOOP+
8.2
510
249 k 1 k
3.6-V Zener
Q1
Q2
Q3
3V3
330 k
10 μF
200 k
Current
sourced to
loop control
图8-4. Start-Up Circuit
In the start-up circuit, the 3.6-V Zener diode sets the voltage at the base of Q1. If the TLVH431B shunt regulator
has not started, apply voltage to LOOP+ and LOOP– to turn on Q1 and source current to the shunt regulator.
As the shunt regulator turns on and approaches the set voltage of 3.3 V, the base-emitter voltage (VBE) of Q1
becomes smaller. The collector current of Q2 drives the current of the shunt regulator to set the LOOP current
going through the 40.2-Ωresistor in the current loop control circuit shown in the following section. After the start-
up circuit has started, Q1 stops supplying current because the VBE is restricted. Q1 shuts off, leaving several
microamps of current flowing through the 3.6-V Zener diode.
Take care when selecting the Zener diode. The voltage across the Zener diode varies with the loop voltage and
the temperature of the circuit. This variance can change the VBE across Q1 and change the total current going
through the start-up circuit. If the voltage is too high, the Zener diode sets Q1 to continue to source current after
the circuit starts up. If the voltage is too low, the Zener diode prevents the TLVH431B from turning on. Verify
proper start up by checking that the 3.3-V supply starts up, and that Q1 turns off when in operation.
When the circuit starts up and the 3V3 line comes up to the desired 3.3-V supply level, the current through the
TLVH431B is primarily sourced through Q2. The Q2 transistor must be able to dissipate enough power to handle
the high current (> 20 mA) and the high voltage (> 30 V) in the loop. Because the biased transistor, Q2, is
responsible for sourcing most of the output current, choose the components in the path of this current flow with
appropriate power ratings. In this case, the 8.2-Ωresistor is rated to 0.25 W.
The current mirror is set up so that the current gain from Q3 to Q2 is approximately a factor of 60 ×. The exact
current gain is not important as long as the current through Q3 is low.
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8.2.1.2.2 Current Loop Control
The AFE88101 sets an output voltage from 0.3 V to 2.5 V if configured in Range 0 with PVDD > 2.7 V. 图 8-5
shows the feedback circuit that sets the loop current from the DAC output voltage.
LOOP+
8.2
510
Q2
Q3
3V3
330 k
200 k
10 μF
3V3
3V3
100 nF
100 k
0.3 V to 2.5 V
from
AFE88101
OPA333
Q4
1 k
+
–
VOUT
40.2 k
20 M
40.2
LOOP–
ILOOP
图8-5. Current Loop Control for the AFE88101 Transmitter
In this circuit, the VOUT voltage is set across the 100-kΩ resistor by the AFE88101. The opposite end of the
100-kΩ resistor is set to ground by the feedback of the OPA333. The current across the 100-kΩ resistor is
VOUT divided by 100 kΩ. This current continues through the 40.2-kΩ resistor so that the voltage at LOOP– is
less than ground. 方程式11 calculates the voltage at LOOP–.
V
= – VOUT / 100 kΩ × 40.2 kΩ = – VOUT × 0.402
(11)
LOOP–
When the DAC output voltage is set to 0.3 V, the voltage at LOOP– is 0.1206 V less than ground. When the
DAC output voltage is set to 2.5 V, the voltage at LOOP– is 1.005 V less than ground. The LOOP– voltage
sets the loop current that flows from ground to LOOP–through the 40.2-Ωresistor. This current is sourced from
ground but controlled by the current sunk from Q4 coming from the start-up circuit. 方程式 12 calculates the loop
current.
I
= – V
/ 40.2 kΩ
LOOP
(12)
LOOP
Substituting 方程式12 into 方程式11, 方程式13 is obtained.
I
= VOUT × 0.402 / 40.2 Ω = VOUT / 100 Ω
(13)
LOOP
When the DAC output voltage is set to 0.3 V, the loop current is 3 mA. When the DAC output voltage is set to
2.5 V, the loop current is 25 mA. The OPA333 drives the base of transistor Q4 to pull the correct amount of
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current to set the feedback loop. The current pulled from LOOP+ powers the board. Excess current greater than
what is required to power the board is shunted through the TLVH431B regulator.
The AFE88101 sets the DAC output voltage through an output code. This conversion to output voltage is set
through 方程式1; VMIN = 0.3 V and FSR = 2.2 V, resulting in 方程式14.
DAC_CODE
VOUT =
× 2.2 V + 0.3 V
(14)
16
2
In 4-mA to 20-mA systems, the nominal output operates from 4 mA as the low output and 20 mA as the high
output. However, systems sometimes use current outputs that are outside this range to indicate different error
conditions. Loop currents of 3.375 mA and 21.75 mA can be used to indicate different loop errors. 表 8-1 shows
different loop output currents, along with the DAC code and voltages used.
表8-1. DAC Voltage Output and Loop Current Based on DAC Output Codes
OUTPUT CONDITION
DAC minimum
Error low
DAC CODE
DAC OUTPUT (V)
LOOP CURRENT (mA)
0x0000
0.3
0.3375
0.4
3
3.375
4
0x045D
0x0BA2
0x68BA
0xC5D1
0xDA2E
0xFFFF
In-range minimum
In-range midscale
In-range maximum
Error high
1.2
12
2.0
20
2.175
2.5
21.75
25
DAC maximum
Among the passive devices included in the design, choose gain setting resistors that exhibit tight tolerances to
achieve high accuracy. These resistors are primarily responsible for setting the gain of the current loop, along
with primary path of the output current flow.
8.2.1.2.3 Input Protection and Rectification
图 8-6 shows the simple protection scheme implemented in the design to mitigate issues that arise from voltage
and current transients on the bus. These transients have two main components: high-frequency and high-
energy. These two components can be leveraged with a strategy of attenuation and diversion by the protection
circuitry to deliver robust immunity.
Ferrite
Bead
LOOP+
+VTERMINAL
36-V
LOOP-
Bidirectional
TVS Diode
-VTERMINAL
图8-6. Loop Input Protection
Attenuation uses passive components, primarily resistors and capacitors, to attenuate high-frequency transients
and to limit series current. Use ferrite beads to maintain dc accuracy while still delivering the ability to limit
current from high-frequency transients. This circuit uses a capacitor placed across the input terminals, as well as
ferrite beads in series with the terminals.
Diversion capitalizes on the high-voltage properties of the transient signals by using a diode to clamp the
transient within supply voltages, or to divert the energy away from the system. Transient voltage suppressor
(TVS) diodes help protect against transients because TVS diodes break down very quickly and often feature
high power ratings that are critical to survive multiple transient strikes.
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A rectifier is also implemented for reverse polarity protection so that the design can be connected to the bus
regardless of the pin orientation or polarity without damage to the design.
8.2.1.2.4 System Current Budget
Power consumption is an important consideration when designing two-wire transmitters. Power supplied from
the loop must power all the circuitry related to the transmitter and sensor. The minimum loop current in two-wire
applications is typically 4 mA. However, for error indications, this current is as low as 3.375 mA. Therefore, the
power budget of all transducer circuitry must be less than the maximum allowable system power budget of 3 mA.
表 8-2 lists the specified maximum quiescent current of all included active components (provided from the
respective data sheets).
表8-2. Typical Component Currents
DEVICE
TPS7A0230
DESCRIPTION
TYPICAL CURRENT (µA)
LDO
0.025
AFE88101
16-bit DAC
170
OPA333 (2)
Operational amplifier
Shunt regulator
Microcontroller
Digital isolation
17
60
TLVH431B
MSP430
Dependent on firmware
Dependent on communications
ISO7021D (2), ISO7041F
8.2.1.3 Application Curves
图8-7. Circuit Start-Up
8.3 Initialization Set Up
This section describes several recommendations to set up the AFEx8101.
The AFEx8101 power up with the CRC enabled. If the device is intended to be run without the CRC, the CRC
must be disabled by setting the CRC_EN bit to 0h in the CONFIG register. Be aware that the command to write
to this register is first done with the CRC enabled. The CRC byte must be appended to the command for the
device to interpret the command correctly. To disable the CRC after start up, write 0x02 0x00 0x26 0x24 to the
device. The first three bytes write the command, while the last byte is the CRC byte. For more information on the
CRC, see the communication description in 节7.5.2.3.
The AFEx8101 also power up with the SDO pin disabled. The SDO is required for reading from any of the device
registers, as well as reading any data from the ADC in SPI mode. The SDO is enabled by writing 0h into the
DSDO bit in the CONFIG register. See also 节7.5.2.1 and 节7.5.2.2.
To enable the ADC, first enable the ADC buffer by writing 0h into the BUF_PD bit in the ADC_CFG register.
Information about using the ADC in different modes of operation is in 节7.3.2.
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8.4 Power Supply Recommendations
The AFEx8101 can operate within a single-supply range of 2.7 V to 5.5 V applied to the PVDD pin. When 2.7 V
to 5.5 V is provided to PVDD, an internal LDO is enabled that drives VDD internally. VDD pin must have 1 μF to
10 μF of capacitance for operation.
The AFEx8101 can also be operated with a lower supply voltage of 1.71 V to 1.89 V applied to the PVDD pin.
When the voltage is within this lower range, the internal LDO is not operational, and the lower external supply on
the PVDD pin must be tied to the VDD pin.
The digital interface supply, IOVDD, can operate with a supply range of 1.71 V to 5.5 V.
Switching power supplies and DC/DC converters often have high-frequency glitches or spikes riding on the
output voltage. In addition, digital components can create similar high-frequency spikes. This noise can easily
couple into the DAC output voltage or current through various paths between the power connections and analog
output. To further reduce noise, include bulk and local decoupling capacitors. The current consumption on the
PVDD and IOVDD pins, the short-circuit current limit for the voltage output, and the current ranges for the
current output are listed in the Electrical Characteristics. The power supply must meet the requirements listed in
the Recommended Operating Conditions.
8.5 Layout
8.5.1 Layout Guidelines
To maximize the performance of the AFEx8101 in any application, follow good layout practices and proper circuit
design. The following recommendations are specific to the device:
• For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal
traces on this layer. However, depending on restrictions imposed by specific end equipment, a dedicated
ground plane is not always practical. If ground-plane separation is necessary, make a direct connection of the
planes at the DAC. Do not connect individual ground planes at multiple locations because this configuration
creates ground loops.
• IOVDD and PVDD must have 100-nF decoupling capacitors local to the respective pins. VDD must have at
least a 1-μF decoupling capacitor used for the internal LDO, or for an external 1.8-V supply. Use a high-
quality ceramic-type NP0 or X7R capacitor for best performance across temperature and a very low
dissipation factor.
• Place a 100-nF reference capacitor close to the VREFIO pin.
• Avoid routing switching signals near the reference input.
• Maintain proper placement for the digital and analog sections with respect to the digital and analog
components. Separate the analog and digital circuitry for less coupling into neighboring blocks and to
minimize the interaction between analog and digital return currents.
• For designs that include protection circuits:
– Place diversion elements, such as TVS diodes or capacitors, close to off-board connectors to make sure
that return current from high-energy transients does not cause damage to sensitive devices
– Use large, wide traces to provide a low-impedance path to divert high-energy transients away from the I/O
pins.
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8.5.2 Layout Example
IOVDD
ALARM
Pull-Up
Resistor
VREFIO
Bypass
Capacitor
PVDD
Bypass
PVDD
24 23 22 21 20 19
Capacitor
UART_IN
1
2
3
4
5
6
18 VOUT
UART_OUT
NC
17 PVDD
16 POL_SEL/AIN1
15 AIN0
Digital
Signals
AFE88101
SCLR
REF_EN
RESET
14 GND
VDD
13
7
8
9
10 11
12
VDD
Bypass
Capacitor
IOVDD
Bypass
Capacitor
IOVDD
图8-8. Layout Example
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9 Device and Documentation Support
9.1 Documentation Support
9.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, AFE881H1 Evaluation Module User's Guide
• Texas Instruments, REF35 Ultra Low-Power, High-Precision Voltage Reference data sheet
• Texas Instruments, OPA391 Precision, Ultra-Low IQ, Low Offset Voltage, e-trim™ Op Amp data sheet
• Texas Instruments, ADS1220 4-Channel, 2-kSPS, Low-Power, 24-Bit ADC with Integrated PGA and
Reference data sheet
• Texas Instruments, TPS7A16 60-V, 5-µA IQ, 100-mA, Low-Dropout Voltage Regulator With Enable and
Power-Good data sheet
• Texas Instruments, TPS7A02 Nanopower IQ, 25-nA, 200-mA, Low-Dropout Voltage Regulator With Fast
Transient Response data sheet
• Texas Instruments, ISO7021 Ultra-Low Power Two-Channel Digital Isolator data sheet
• Texas Instruments, Isolated, Ultra-Low Power Design for 4- to 20-mA Loop Powered Transmitters design
guide
• Texas Instruments, Isolated Loop Powered Thermocouple Transmitter design guide
• Texas Instruments, Small Form Factor, 2-Wire, 4- to 20-mA Current-Loop, RTD Temperature Transmitter
design guide
• Texas Instruments, Isolated Power and Data Interface for Low-power Applications reference design
• Texas Instruments, Uniquely Efficient Isolated DC/DC Converter for Ultra-Low Power and Low-Power
Applications design guide
9.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
82
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Product Folder Links: AFE78101 AFE88101
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AFE88101RRUR
ACTIVE
UQFN
RRU
24
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
AFE
88101
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
RRU0024A
UQFN - 0.7 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
A
B
PIN 1 INDEX AREA
4.1
3.9
0.05 C
0.01 C
C
0.7
0.6
SEATING PLANE
0.08 C
0.01
0.00
2X 2.5
SYMM
(0.2) TYP
(0.1) TYP
7
12
6
13
24X (0.18)
SYMM
2X 2.5
7X (45 X 0.087)
20X 0.5
1
18
0.3
0.2
24
19
24X
(0.25)
0.6
0.4
0.1
C A B
C
(0.663)
24X
0.05
PIN 1 ID
4225850/A 04/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RRU0024A
UQFN - 0.7 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
SEE SOLDER MASK
19
24
DETAIL
24X (0.7)
18
1
24X (0.25)
20X (0.5)
SYMM
(3.7)
(R0.05) TYP
6
13
7
12
(3.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225850/A 04/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RRU0024A
UQFN - 0.7 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
19
24
24X (0.7)
18
24X (0.25)
20X (0.5)
1
SYMM
(3.7)
(R0.05) TYP
13
6
7
12
SYMM
(3.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
4225850/A 04/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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