ALM2403-Q1 [TI]
适用于旋转变压器应用且具有低失真的汽车类双通道高电压功率运算放大器;
| 型号： | ALM2403-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于旋转变压器应用且具有低失真的汽车类双通道高电压功率运算放大器 变压器 放大器 运算放大器 |
| 文件： | 总30页 (文件大小：2151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ALM2403-Q1
ZHCSMT3A –NOVEMBER 2020 –REVISED MARCH 2023
ALM2403-Q1 适用于旋转变压器驱动且具有集成保护功能的
汽车类低失真双通道运算放大器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准：
– 温度等级1：–40°C 至+125°C，TA
• 提供功能安全
ALM2403-Q1 是一款双电源运算放大器，其特性和性
能使该器件更适合基于旋转变压器的应用。该器件具有
高增益带宽和压摆率以及连续高输出电流驱动功能，非
常适合为激励旋转变压器初级线圈提供所需的低失真和
差分高振幅激励。尤其在易受故障影响的电线上驱动模
拟信号时，电流限制和过热检测功能可增强整体系统稳
健性。
– 可帮助进行功能安全系统设计的文档
• 高输出电流驱动：500 mA 峰值电流（每通道）
– 取代分立式运算放大器和晶体管
• 两个电源的宽电源电压范围（最高24 V）
• 过热关断
具有散热焊盘和低 RθJA 的小型 HTSSOP 封装能够向
负载提供高电流，同时更大程度地减小布板空间。
ALM2403-Q1 具有更高增益带宽，该器件可配置为滤
波器级，同时仍提供高输出驱动，从而显著减小旋转变
压器驱动信号链的总解决方案尺寸。这种缩小的解决方
案尺寸是 ALM2403-Q1 在汽车和工业应用中的一项关
键优势。
• 电流限制
• 实现低IQ 应用的关断引脚
• 21MHz 增益带宽，具有50V/µs 的压摆率
• 封装：14 引脚HTSSOP (PWP)
2 应用
• 基于旋转变压器的汽车和工业应用
• 逆变器和电机控制
• 制动系统
• 电动助力转向(EPS)
• 后视镜模块
• 汽车电子视镜
封装信息
封装(1)
封装尺寸（标称值）
器件型号
ALM2403-Q1
HTSSOP (14)
5.00mm × 4.40mm
(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。
• 伺服驱动器功率级模块
• 飞行控制系统
35
VS = 24 V
VS = 15 V
VS = 5 V
30
25
+
Sin
Þ
ALM2403-Q1
20
15
10
5
Cos
+
Þ
Resolver
GND
简化版原理图
0
1
10
100
1k
10k
100k
1M
10M 100M
Frequency (Hz)
输出电压与频率间的关系
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOSA37
ALM2403-Q1
ZHCSMT3A –NOVEMBER 2020 –REVISED MARCH 2023
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................14
8 Application and Implementation..................................15
8.1 Application Information............................................. 15
8.2 Typical Application.................................................... 15
8.3 Power Supply Recommendations.............................19
8.4 Layout....................................................................... 19
9 Device and Documentation Support............................22
9.1 Documentation Support............................................ 22
9.2 接收文档更新通知..................................................... 22
9.3 支持资源....................................................................22
9.4 Trademarks...............................................................22
9.5 静电放电警告............................................................ 22
9.6 术语表....................................................................... 22
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................7
7 Detailed Description......................................................12
7.1 Overview...................................................................12
7.2 Functional Block Diagram.........................................12
7.3 Feature Description...................................................13
Information.................................................................... 22
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (November 2020) to Revision A (May 2022)
Page
• 将特性 中的输出电流从 650mA 更改为 500mA..................................................................................................1
• 更改了首页图中的标题和 Y 轴单位.....................................................................................................................1
• Changed pin names to synchronize pin naming throughout document..............................................................3
• Changed thermal pad description text for clarity................................................................................................ 3
• Changed voltage range for VOTF/SH_DN in the Absolute Maximum Ratings ....................................................... 4
• Changed all VS voltages to single-supply nomenclature in the Electrical Characteristics and Typical
Chacteristics ...................................................................................................................................................... 5
• Deleted test conditions from enable high and low input voltages in the Electrical Characteristics ....................5
• Moved shutdown current parameter to Power Supply section in the Electrical Characteristics ........................ 5
• Changed Figures 6-12 through 6-16 to correct axis units and values................................................................ 7
• Changed functional block diagram to correct inaccuracies.............................................................................. 12
• Changed EMC capacitance from 50 nF to 10 nF in Table 8-1, Design Parameters ........................................16
• Added test condition to first bullet of Detailed Design Procedure ....................................................................17
• Changed R3 to R2 in 2nd paragraph of Filter Design section.......................................................................... 17
• Changed terms in Equation 4 to Equation 6 for clarity..................................................................................... 18
• Changed Figure 8-4, 2nd-Order MFB LP Filter AC Output Characteristics .....................................................19
• Changed values in Table 8-2, Signal Attenuation vs Frequency ..................................................................... 19
• Changed Figure 8-6, ALM2403-Q1 Layout Example, to match EVM layout.................................................... 20
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SBOSA37
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5 Pin Configuration and Functions
IN1–
IN1+
1
2
3
4
5
6
7
14
13
12
11
10
9
V–
OUT1
V+
OTF/SH_DN
IN2+
Thermal Pad
V+
IN2–
V+
V–
OUT2
NC
NC
8
Not to scale
图5-1. PWP Package, 14-Pin HTSSOP (Top View)
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
IN1–
IN1+
1
Input
Input
Inverting op amp input for channel 1
2
Noninverting op amp input for channel 1
Overtemperature flag and shutdown (see 表7-1, Shutdown Truth Table)
Noninverting op amp input for channel 2
Inverting op amp input for channel 2
3
OTF/SH_DN Input/Output
4
IN2+
IN2–
V–
Input
Input
5
6, 14
Negative supply pin (both negative supply pins must be used and connected together)
No internal connection (do not connect)
Op amp output for channel 2
—
7, 8
NC
—
9
OUT2
V+
Output
10, 11, 12
13
Positive supply pin
—
OUT1
Output
Op amp output for channel 1
Connect the exposed thermal pad to the most negative supply on the device, V–, for best
thermal performance. The thermal pad can also be left floating electrically; the heat spread
of the pad can be thermally maximized and conducted into the PCB.
Thermal Pad
Thermal Pad
—
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English Data Sheet: SBOSA37
ALM2403-Q1
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
26
±13
Single-supply, VS = (V+) –GND
VS
Supply voltage
V
Dual-supply, VS = (V+) –(V–)
Common-mode
(V+) + 0.7
(V–) –0.7
(V–) –0.2
Signal input voltage
V
(V+) –(V–) +
Differential
0.2
VOTF/SH_DN OTF/SH_DN pin voltage
Signal input current
V
(V–) + 5.7
±10
mA
Output short circuit(2)
Continuous
Continuous
150
TA
Operating temperature
Junction temperature
Storage temperature
°C
°C
°C
–55
TJ
150
Tstg
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD classification level 2
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC Q100-011
CDM ESD classification level C5
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
5
NOM
MAX
24
UNIT
V
Single-supply, VS = (V+) –GND
Dual-supply, VS = (V+) –(V–)
VS
TA
Supply voltage
±2.5
–40
±12
125
Operating temperature
°C
6.4 Thermal Information
ALM2403-Q1
THERMAL METRIC(1)
PWP (HTSSOP)
UNIT
14 PINS
46.9
42.1
22.6
1.2
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJT
22.5
5.9
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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English Data Sheet: SBOSA37
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6.5 Electrical Characteristics
at TA = 25°C, VS = V+ = 24 V, V–= GND, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
±6
±15
±10
±25
±50
±47
±50
mV
dVOS/dT
Input offset voltage drift
TA = –40°C to +125°C
μV/°C
VS = 5 V to 24 V
Power-supply rejection
ratio
PSRR
μV/V
VS = 5 V to 24 V, TA = –40°C to +125°C
Channel separation
f = 10 kHz
120
10
dB
INPUT BIAS CURRENT
±100
±100
±200
±100
pA
nA
pA
nA
IB
Input bias current
TA = –40°C to +125°C
TA = –40°C to +125°C
10
IOS
Input offset current
NOISE
Input voltage noise
f = 0.1 Hz to 10 Hz
f = 1 kHz
8
150
22
µVRMS
nV/√Hz
fA/√Hz
Input voltage noise
density
eN
iN
f = 100 kHz
f = 1 kHz
Input current noise
48
INPUT VOLTAGE
VCM
Common-mode voltage
(V+) + 0.2
V
(V–) –0.2
49
72
94
59
(V–) –0.5 V < VCM < (V+) + 0.5 V, 10 V ≤VS < 24 V
(V–) –0.2 V < VCM < (V+) + 0.2 V,
TA = –40°C to +125°C, 10 V < VS < 24 V
52
80
Common-mode rejection
ratio
(V–) + 2.5 V < VCM < (V+) –2.5 V,
10 V < VS < 24 V
CMRR
dB
(V–) + 2.5 V < VCM < (V+) –2.5 V,
TA = –40°C to +125°C, 10 V < VS < 24 V
75
44
(V–) –0.5 V < VCM < (V+) + 0.5 V, 5 V < VS < 24 V
INPUT CAPACITANCE
ZID
Differential
1 || 2
1 || 2
GΩ|| pF
ZICM
Common-mode
OPEN-LOOP GAIN
103
96
111
104
(V–) + 0.5 V < VO < (V+) –0.5 V,
VS = 24 V
TA = –40°C to +125°C
AOL
Open-loop voltage gain
dB
96
(V–) + 1.5 V < VO < (V+) –1.5 V,
RL = 225 Ω, VS = 24 V
94
TA = –40°C to +125°C
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product VS = 24 V
21
50
MHz
Slew rate
10-V step, gain = +1
V/μs
To 0.1%, 10-V step , gain = +1, CL = 10 pF
To 0.1%, 10-V step , gain = –1, CL = 10 pF
VIN × gain > VS
0.31
0.40
0.28
tS
Settling time
μs
Overload recovery time
μs
Total harmonic distortion VS = 15 V, VO = 10 Vpp, gain = –1,
+ noise
THD+N
74
dB
f = 10 kHz, RL = 100 Ω
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6.5 Electrical Characteristics (continued)
at TA = 25°C, VS = V+ = 24 V, V–= GND, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
Voltage output swing
from rail
IOUT = ±5 mA
35
60
mV
mA
Sinking
400
500
ISC
Short-circuit current
Sourcing
ENABLE
VIH_OTF
VIL_OTF
Enable high input voltage
Enable low input voltage
Enable hysteresis
1.2
V
V
0.5
220
5
mV
μs
tOTF/SH_DN Enable start-up time
POWER SUPPLY
IO = 0 A
3.6
5.5
6
IQ
Total quiescent current
mA
IO = 0 A, TA = –40°C to +125°C
ISD
Shutdown current
VOTF/SH_DN = 0 V
260
μA
TEMPERATURE
Thermal shutdown
172
150
°C
°C
Thermal shutdown
recovery
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6.6 Typical Characteristics
at TA= 25°C, VS = 24 V, VCM = VS/2, and RL = 10 kΩ(unless otherwise noted)
30
25
20
15
10
5
40
30
20
10
0
0
-25 -20 -15 -10
-5
0
5
10
15
20
25
-50 -40 -30 -20 -10
0
10
20
30
40
50
D000
D001
Offset Voltage (mV)
Offset Voltage Drift (mV/èC)
235 channels
235 channels
图6-1. Offset Voltage Production Distribution
图6-2. Offset Voltage Drift Production Distribution
25
25
20
15
10
5
20
15
10
5
0
0
-5
-5
-10
-15
-20
-25
-10
-15
-20
-25
-75
-50
-25
0
25
50
75
100 125 150
2
3
4
5
6
Supply Voltage (V)
7
8
9
10
11
12
Temperature (èC)
D016
D018
5 typical units
5 typical units
图6-3. Offset voltage vs Temperature
图6-4. Offset Voltage vs Power Supply
25
20
15
10
5
120
100
80
60
40
20
0
210
180
150
120
90
Gain
Phase
0
-5
-10
-15
-20
-25
60
30
-20
100m
0
10k 100k 1M 10M 100M
-12.5 -10 -7.5 -5 -2.5
0
Input Common-mode Voltage (V)
2.5
5
7.5 10 12.5
1
10
100
1k
Frequency (Hz)
D017
D002
5 typical units
图6-5. Offset Voltage vs Input Common-Mode Voltage
图6-6. Open-Loop Gain and Phase vs Frequency
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6.6 Typical Characteristics (continued)
at TA= 25°C, VS = 24 V, VCM = VS/2, and RL = 10 kΩ(unless otherwise noted)
50
40
30
20
10
0
120
100
80
60
40
20
0
G = +1
PSRR+
PSRR-
G = -1
G = +10
G = +100
-10
-20
100
1k
10k
100k
Frequency (Hz)
1M
10M
100M
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M 100M
D004
D005
CLOAD = 200 nF, RL = 50 Ω
图6-7. Closed-Loop Gain vs Frequency
图6-8. PSRR vs Frequency
0.1
-60
100
90
80
70
60
50
40
30
20
10
0
RLOAD = 100 W
RLOAD = 600 W
RLOAD = 2 kW
RLOAD = 10 kW
CMRR
0.05
0.03
0.02
0.01
-80
0.005
0.003
0.002
0.001
-100
0.0005
0.0003
0.0002
0.0001
-120
20k
20
200
2k
Frequency (Hz)
D008
100m
1
10
100
1k
Frequency (Hz)
10k 100k 1M 10M 100M
VO = 10 VPP, gain = 1 V/V,
D006
measurement bandwidth = 80 kHz
图6-10. THD+N Ratio vs Frequency
图6-9. CMRR vs Frequency
0.1
0.01
-60
35
G+1, RLOAD = 100 W
G+1, RLOAD = 10 kW
G-1, RLOAD = 100 W
G-1, RLOAD = 10 kW
VS = 24 V
VS = 15 V
VS = 5 V
30
25
20
15
10
5
-80
0.001
-100
0.0001
-120
10
10m
100m 1
Output Amplitude (VRMS
)
D011
0
Input signal frequency = 1 kHz,
1
10
100
1k
10k
100k
1M
10M 100M
measurement bandwidth = 80 kHz
Frequency (Hz)
图6-12. Output Voltage vs Frequency
图6-11. THD+N vs Output Amplitude
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6.6 Typical Characteristics (continued)
at TA= 25°C, VS = 24 V, VCM = VS/2, and RL = 10 kΩ(unless otherwise noted)
12
11
10
9
6
5
4
3
2
1
0
−40C
25C
85C
125C
8
−40C
25C
85C
125C
7
6
0
0.1
0.2
0.3
0.4
0.5
0.6
0
-0.1
-0.2
-0.3
-0.4
-0.5
Output Current (A)
Output Current (A)
VS = 12 V
VS = 12 V
图6-13. Output Voltage Swing vs Output Source Current
图6-14. Output Voltage Swing vs Output Sink Current
24
12
−40C
25C
22
10
8
85C
125C
20
18
16
14
12
6
4
−40ꢀC
25ꢀC
85ꢀC
125ꢀC
2
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
0.1
0.2
0.3
0.4
0.5
0.6 0.65
Output Current (A)
Output Current (A)
VS = 24 V
VS = 24 V
图6-15. Output Voltage Swing vs Output Source Current
图6-16. Output Voltage Swing vs Output Sink Current
10000
8
6
1000
100
10
VS = ê2.5 V
4
2
0
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
D007
0
2
4
6
8
Supply Voltage (V)
10
12
14
D027
5 typical units
图6-17. Input Voltage Spectral Noise Density vs Frequency
图6-18. Quiescent Current vs Power Supply
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6.6 Typical Characteristics (continued)
at TA= 25°C, VS = 24 V, VCM = VS/2, and RL = 10 kΩ(unless otherwise noted)
6.5
6
100000
10000
1000
100
5.5
5
4.5
4
3.5
3
10
-75
-50
-25
0
25
50
75
100 125 150
100m
1
10
100
1k
Frequency (Hz)
10k 100k 1M 10M 100M
Temperature (èC)
D029
D012
5 typical units
图6-19. Quiescent Current vs Temperature
图6-20. Open-Loop Output Impedance vs Frequency
40
95
RISO = 0 W
RISO = 25 W
RISO = 50 W
RISO = 0 W
RISO = 25 W
RISO = 50 W
90
85
80
75
70
65
60
55
50
45
40
35
30
25
35
30
25
20
15
10
5
0
10
100
Capactiance (pF)
1000
0
100 200 300 400 500 600 700 800 900 1000
Capacitance (pF)
D032
D033
10-mV output step, gain = 1 V/V
10-mV output step, gain = –1 V/V
图6-22. Small-Signal Overshoot vs Capacitive Load
图6-21. Small-Signal Overshoot vs Capacitive Load
VIN (V)
VOUT (V)
VIN (V)
VOUT (V)
Time (100 ms/div)
Time (200 ns/div)
D034
D038
Gain = –1 V/V
图6-23. No Phase Reversal
图6-24. Large-Signal Step Response
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6.6 Typical Characteristics (continued)
at TA= 25°C, VS = 24 V, VCM = VS/2, and RL = 10 kΩ(unless otherwise noted)
G = 1 V/V, VIN = 10 VPP
G = –1 V/V, VIN = 10 VPP
图6-26. Settling Time
图6-25. Settling Time
700
600
500
400
300
200
120
100
80
60
40
Sourcing
Sinking
20
10M
100M
Frequency (Hz)
1G
10G
-50
-25
0
25
50
75
100
125
Temperature (èC)
D015
D041
PRF_PEAK = –10 dBm
图6-27. Short-Circuit Current vs Temperature
图6-28. EMIRR vs Frequency
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7 Detailed Description
7.1 Overview
The ALM2403-Q1 is a dual-power op amp qualified for use in automotive applications. Key features for this
device are low offset voltage, high output current drive capability, and high FPBW capability. The device also
offers protection features such as thermal shutdown and current limit. The 14-pin HTSSOP package minimizes
board space and power dissipation.
7.2 Functional Block Diagram
V+
12
13
PMOS Current Limiting and
Biasing
IN1+
IN1–
2
1
+
EMI
OUT1
OTA
Rejection
–
NMOS Current Limiting and
Biasing
5 V
V
14
EN
OTF/SH_DN
3
V+
Thermal Detection
V+
V+
11
10
PMOS Current Limiting and
Biasing
IN2+
4
+
–
EMI
OTA
9
OUT2
Rejection
IN2–
V
NMOS Current Limiting and
Biasing
5
6
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7.3 Feature Description
7.3.1 Overtemperature and Shutdown Pin (OTF/SH_DN)
The overtemperature and shutdown pin, OTF/SH_DN, is bidirectional and allows both op amps to be put into a
low IQ state (approximately 200 µA per amplifier) when forced low or to less than VIL_OTF. As a result of being
bidirectional, and the respective enable and disable functionality, this pin must be pulled high or greater than
VIH_OTF through a pullup resistor. The use of a 10-kΩ pullup resistor leads to a drive current of approximately
210 µA when used with a pullup voltage of 3.3 V.
When the junction temperature of the ALM2403-Q1 exceeds the specified limits, OTF/SH_DN goes low to alert
the application that both the outputs have turned off because of an overtemperature event.
When OTF/SH_DN is pulled low and the op amps are shut down, the op amps are in an open loop, even when
there is negative feedback applied. This occurrence is due to the loss of the open-loop gain in the op amps when
the biasing is disabled.
7.3.2 Thermal Shutdown
If the die temperature exceeds safe limits, all outputs are disabled, and the OTF/SH_DN pin is driven low. After
the die temperature has fallen to a safe level, operation automatically resumes. The OTF/SH_DN pin is released
after operation has resumed.
When operating the die at a high temperature, the op amp toggles on and off between the thermal shutdown
hysteresis. In this event, the safe limits for the die temperature must be taken in to account. Do not continuously
operate the device in thermal hysteresis for long periods of time.
7.3.3 Current-Limit and Short-Circuit Protection
Each op amp in the ALM2403-Q1 has separate internal current limiting for the PMOS (high-side) and NMOS
(low-side) output transistors. If the output is shorted to ground, then the PMOS (high-side) current limit is
activated, and limits the current to 500 mA nominally. If the output is shorted to supply, then the NMOS (low-side)
current limit is activated and limits the current to 400 mA nominally at 25°C. The current limit value is inversely
proportional to temperature; therefore, the current limit value increases at low temperatures.
When current is limited, the safe limits for the die temperature must be taken in to account. With too much power
dissipation, the die temperature can surpass thermal shutdown limits; the op amp shuts down and reactivates
after the die has fallen below thermal limits.
CAUTION
Do not continuously operate the device in thermal hysteresis for long periods of time because this
action may cause irreversible damage to the device.
7.3.4 Input Common-Mode Range
The input common-mode range of the ALM2403-Q1 is between (V–) – 0.2 V and (V+) + 0.2 V. Staying within
this range allows the op amps to perform and operate within specification. Operating beyond these limits can
cause distortion and nonlinearities.
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7.3.5 Reverse Body Diodes in Output-Stage Transistors
Designed as a high-voltage, high current operational amplifier, the ALM2403-Q1 delivers robust output drive
capability. A class AB output stage with common-source transistors is used to achieve full rail-to-rail output swing
capability. Different load conditions change the ability of the amplifier to swing close to the rails.
Each output transistor has internal reverse diodes between drain and source that conduct if the output is forced
to greater than the supply or less than ground (reverse current flow). These diodes can be used as flyback
protection in inductive-load-driving applications. Limit the use of these diodes to pulsed operation in order to
minimize junction temperature overheating due to (VF × IF). Internal current-limiting circuitry does not operate
when current is flown in the reverse direction and the reverse diodes are active. A method to protect these
reverse body diodes is shown in 节8.2.2.1.2.
7.3.6 EMI Filtering
Op amps vary with regard to the susceptibility of the device to electromagnetic interference (EMI). If conducted
EMI enters the op amp, the dc offset observed at the amplifier output may shift from the nominal value while EMI
is present. This shift is a result of signal rectification associated with the internal semiconductor junctions. While
all op-amp pin functions can be affected by EMI, the signal input pins are likely to be the most susceptible. The
ALM2403-Q1 incorporates an internal input low-pass filter that reduces the amplifiers response to EMI. Both
common-mode and differential mode filtering are provided by this filter.
Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational
amplifier over a broad frequency spectrum extending from 10 MHz to 990 MHz. The EMI rejection ratio (EMIRR)
metric allows op amps to be directly compared by the EMI immunity. Detailed information can also be found in
the EMI Rejection Ratio of Operational Amplifiers application report, available for download from www.ti.com.
7.4 Device Functional Modes
7.4.1 Open-Loop and Closed-Loop Operation
As a result of the very-high, open-loop dc gain of the ALM2403-Q1, the device functions as a comparator in
open loop for most applications. A majority of electrical characteristics are verified in negative feedback, closed-
loop configurations. Certain dc electrical characteristics, like offset, may have a higher drift across temperature
and lifetime when continuously operated in open loop over the lifetime of the device.
7.4.2 Shutdown
When the OTF/SH_DN pin is left floating or is grounded, the op amp shuts down to a low IQ state and does not
operate; the op amp outputs go to a high-impedance state.
表7-1. Shutdown Truth Table
PIN NAME
LOGIC STATE
High ( > VIH_OTF )
Low ( < VIL_OTF )
OP AMP STATE
Operating
OTF/SH_DN
Shutdown (low IQ state)
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The ALM2403-Q1 is a dual-power op amp with performance and protection features that are optimal for many
applications. For op amps, there are many general design consideration that must be taken into account. The
following subsections describe what to consider for most closed-loop applications. 节 8.2 gives a specific
example of the ALM2403-Q1 being used in a resolver application.
8.1.1 Capacitive Load and Stability
The ALM2403-Q1 is designed for applications where driving a capacitive load is required. As with all op amps,
specific instances can occur where the ALM2403-Q1 device can become unstable. The particular op-amp circuit
configuration, layout, gain, and output loading are some of the factors to consider when establishing whether or
not an amplifier is stable in operation. An op amp in a unity-gain (1-V/V) buffer configuration that drives a
capacitive load exhibits a greater tendency to become unstable compared to an amplifier operated at a higher-
noise gain. The capacitive load, in conjunction with the op-amp output resistance, creates a pole within the
feedback loop that degrades the phase margin. The degradation of the phase margin increases as the
capacitive loading increases. When operating in a unity-gain configuration, the ALM2403-Q1 remains stable with
a pure capacitive load up to approximately 30 pF. Increasing the amplifier closed-loop gain allows the amplifier to
drive increasingly larger capacitance. This increased capability is evident when observing the overshoot
response of the amplifier at higher voltage gains.
One technique for increasing the capacitive load drive capability of the amplifier operating in a unity-gain
configuration is to insert a small resistor (RS; typically, 100 mΩto 10 Ω) in series with the output, as shown in 图
8-1. This resistor significantly reduces the overshoot and ringing associated with large capacitive loads.
V+
RS
œ
VOUT
CL
+
RL
+
VIN
œ
图8-1. Capacitive Load Drive
8.2 Typical Application
High-power ac and brushless dc (BLDC) motor-drive applications need position feedback to efficiently and
accurately drive the motor. Position feedback can be achieved by using optical encoders, hall sensors, or
resolvers. Resolvers are the main choice when environmental or longevity requirements are challenging and
extensive.
A resolver acts as a transformer with one primary coil and two secondary coils. The primary coil, or excitation
coil, is located on the rotor of the resolver. As the rotor of the resolver spins, the excitation coil induces a current
into the sine and cosine sensing coils. These coils are oriented 90 degrees from one another, and the voltage
from the sine and cosine coils is translated into a vector position by the microcontroller or resolver-to-digital
converter chip.
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Resolver excitation coils can have a very low dc resistance (< 100 Ω), requiring a sink and a source of up to 200
mA from the excitation driver. The ALM2403-Q1 can source and sink this current while providing current-limiting
and thermal-shutdown protection. Incorporating these protections in a resolver design can increase the life of the
end product.
The input to the ALM2403-Q1 can be an analog sine wave generated by the resolver-to-digital converter chip or
a pulse-width modulation (PWM) signal generated from a microcontroller I/O pin. In the case of the latter, a filter
stage is needed to extract a lower bandwidth sine wave from the PWM signal. This sine wave would then be the
input signal to the ALM2403-Q1. As a result of high gain bandwidth, the ALM2403-Q1 can be configured as a
filter stage while providing the required output drive. This configuration significantly reduces the total solution
size and design complexity of the resolver-drive signal chain. The fundamental design steps to achieve this
functionality are shown in this application example, and can be applied to other inductive-load applications as
well.
R2
C3
R1
R3
VOUT1
C1
œ
C2
PWM input
+
VBIAS
ALM2403-Q1 channel 1
CEMC
Sin
C4
R5
CEMC
Cos
Resolver
VOUT1
R4
œ
+
VBIAS
ALM2403-Q1 channel 2
图8-2. Resolver-Based Application
8.2.1 Design Requirements
For this design example, use the parameters listed in 表8-1 as the input parameters.
表8-1. Design Parameters
DESIGN PARAMETER
Ambient temperature range
Available supply voltages
EMC capacitance (CL)
EXAMPLE VALUE
–40°C to +125°C
15 V
10 nF
Resolver excitation input voltage
Excitation frequency
7 VRMS
10 kHz
PWM signal frequency
320 kHz
3.3 V
PWM signal amplitude
Functional safety capable
Short-to-battery protection
Yes
Yes
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8.2.2 Detailed Design Procedure
When using the ALM2403-Q1 in a resolver application, determine:
• Resolver excitation input impedance or resistance and inductance: ZO = 100 + j188, R = 100 Ω, and
L = 3 mH at 10 kHz
• Resolver transformation ratio (VSINCOS / VEXC): 0.5 V/V at 10 kHz
• Package and RθJA: HTSSOP, 46.9°C/W
• Op amp maximum junction temperature: 150°C
• Op amp bandwidth: 21 MHz
• Op amp slew rate: 50 V/µS
8.2.2.1 Resolver Excitation Amplifier Combined With MFB 2nd-Order, Low-Pass Filter
R2
6 kΩ
C1
159 nF
C3 1 nF
R1
2 kΩ
R3
2 kΩ
œ
VOUT1
PWM input
C2
12 nF
VBIAS
+
ALM2403-Q1
SD1 1N5827
15 V
图8-3. Two-Pole MFB Filter
When designing a low-pass filter, the most important design criteria is to decide the corner frequency. In this
design example, the resolver excitation frequency is 10 kHz and PWM frequency is 320 kHz. Thus, we want to
make sure that the low-pass filter corner frequency is greater than 10 kHz, and there is maximum attenuation of
harmonic interference generated from the PWM signal. 图 8-3 shows a single channel of the ALM2403-Q1
configured as a 2-pole multiple feedback (MFB) filter with a –40 dB/decade rolloff. The MFB topology enables a
steep rolloff while reducing BOM count. The output from this circuit is a sine wave that can then be inverted
using the second channel of the ALM2403-Q1; see 图 8-2. Thus, both ALM2403-Q1 channels combined provide
the required resolver excitation signal.
8.2.2.1.1 Filter Design
The corner frequency of the 2nd-order MFB filter is set to approximately twenty times less than the PWM
frequency. The corner frequency defined at –3 dB is shown in 方程式1.
1
f
=
(1)
p
2 × π ×
R × C × R × C
3 3 2 2
The 2nd-order MFB active filter uses an inverted input topology and the op amp gain is determined by the ratios
of resistors R2 and R1:
R
2
Gain = −
(2)
R
1
The gain settings are based on the output drive requirements and PWM signal amplitude. With different gain
settings, the filter characteristics, such as rolloff, can change. The design must be fine-tuned to meet optimal
performance needs.
The quality (Q) factor of the low-pass filter is configured with Q = 1. The purpose of designing for this Q factor is
to minimize attenuation around the corner frequency of 10 kHz, thus extending the pass-band gain. The Q factor
of the 2nd-order MFB filter is given by 方程式3:
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C
/C
3
2
Q =
(3)
R
/R
+
R
/R
+
R × R /R
3 2 1
3
2
2
3
8.2.2.1.2 Short-to-Battery Protection
Resolver-based applications require the power op amp stage to provide the resolver excitation signal over long
cables. In many applications, such as automotive traction inverters, the cables are housed in a harness and a
short-circuit condition between different cables in the same harness can occur. In this situation, the output of the
ALM2403-Q1 can see a higher voltage than provided at the positive supply pin. This condition causes the body
diode in the output stage PMOS to become forward-biased and start conducting. As a precaution, use a blocking
diode in series with the positive power supply; see also 图8-3.
For related information, see the ALM2403-Q1 Overvoltage Protection of Resolver-Based Circuits application
note.
8.2.2.2 Power Dissipation and Thermal Reliability
Power dissipation is critical to many industrial and automotive applications. Resolvers are typically chosen over
other position feedback techniques because of reliability and accuracy in harsh conditions and high
temperatures.
The ALM2403-Q1 is capable of high output current with power-supply voltages up to 24 V. Internal power
dissipation increases when operating at high supply voltages. The power dissipated in the op amp (POPA) is
calculated using 方程式4:
V
OUT
P
=
V − V
× I
=
V − V ×
OUT
(4)
OPA
S
OUT
OUT
S
R
L
To calculate the worst-case power dissipation in the op amp, the ac and dc cases must be considered
separately.
In the case of constant output current (dc) to a resistive load, the maximum power dissipation in the op amp
occurs when the output voltage is half the positive supply voltage. This calculation assumes that the op amp is
sourcing current from the positive supply to a grounded load. If the op amp sinks current from a grounded load,
modify 方程式5 to include the negative supply voltage instead of the positive.
2
V
V
S
S
P
= P
=
(5)
OPA MAX⎽DC
OPA
2
4 × R
L
The ac maximum of average power dissipation in the op amp for a sinusoidal output current (ac) to a resistive
load occurs when the peak output voltage is 2/π times the supply voltage, given symmetrical supply voltages,
as shown in 方程式6:
2
2 × V
OPA
π
2 × V
S
S
P
= P
=
(6)
OPA PEAK⎽AC
2
π
× R
L
After the total power dissipation is determined, the junction temperature at the worst expected ambient
temperature case must be determined by using 方程式7:
T
= P
× R
+ T
A MAX
(7)
J MAX
OPA
θJA
8.2.2.2.1 Improving Package Thermal Performance
The value of RθJA depends on the printed circuit board (PCB) layout. An external heat sink, a cooling
mechanism such as a cold air fan, or both, can help reduce RθJA, and thus improve device thermal capabilities.
See TI’s design support web page at www.ti.com/thermal for general guidance on improving device thermal
performance.
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8.2.3 Application Curves
The roll of characteristics and output waveform for the designed MFB filter are shown in 图 8-4 and 图 8-5. The
attenuation is specified in 表8-2.
25
0
300
250
200
150
100
50
12
11
10
9
-25
8
7
-50
6
-75
5
4
-100
-125
-150
3
2
0
Gain
Phase
1
-50
0
1
10
100
1000 10000 100000
Frequency (Hz)
1M
10M
0
100
200
Time (ms)
300
400
500
D051
图8-4. 2nd-Order MFB LP Filter AC Output
图8-5. 2nd-Order MFB LP Filter DC Output
Characteristics
表8-2. Signal Attenuation vs Frequency
2ND-ORDER MFB LPF FREQUENCY
ATTENUATION
(dB)
(kHz)
DC
9.54
9.70
10.0
15.4
6.54
19
3.54
30
–4.38
–45.9
320
8.3 Power Supply Recommendations
The ALM2403-Q1 is recommended for continuous operation from 5 V to 24 V (±2.5 V to ±12 V) for VS, and many
specifications apply from –40°C to +125°C.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling from noisy or high-
impedance power supplies.
CAUTION
Supply voltages larger than 26 V can permanently damage the device (see 节6.1).
8.4 Layout
8.4.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
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• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, see
Circuit Board Layout Techniques.
• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces. If
keeping the traces separate is not possible, then cross the sensitive trace perpendicular, as opposed to in
parallel with the noisy trace.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
8.4.2 Layout Example
This layout does not verify optimum thermal impedance performance. See TI’s design support web page at
www.ti.com/thermal for general guidance on improving device thermal performance.
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To
For optimal thermal performance,
connect exposed pad to as much
top-layer copper as possible, as well
as vias to underlying ground layers.
Supply
Voltage
Connect a ceramic
bypass capacitor from
V+ at pin 12 to GND
through vias and metal
on an internal layer.
Input 1
V–
IN1–
IN1+
Output, Channel 1
OUT1
OTF/SH_DN
IN2+
V+
To
Supply
V+
Voltage
Input 2
V+
IN2–
OUT2
V–
Output, Channel 2
NC
NC
Connect a ceramic
bypass capacitor from
V+ at pin 10 to GND
through vias and metal
on an internal layer.
To
Supply
Voltage
图8-6. ALM2403-Q1 Layout Example
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9 Device and Documentation Support
9.1 Documentation Support
9.1.1 Related Documentation
For related documentation see the following: ALM2403-Q1 Evaluation Module user's guide.
9.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ALM2403QPWPRQ1
ACTIVE
HTSSOP
PWP
14
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
A2403Q
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Mar-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ALM2403QPWPRQ1
HTSSOP PWP
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Mar-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 14
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
ALM2403QPWPRQ1
2000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
PWP 14
4.4 x 5.0, 0.65 mm pitch
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224995/A
www.ti.com
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