AM2634COLFHAZCZR [TI]

具有实时控制和安全功能且频率高达 400MHz 的四核 Arm® Cortex®-R5F MCU | ZCZ | 324 | -40 to 105;


型号：	AM2634COLFHAZCZR
厂家：	TEXAS INSTRUMENTS
描述：	具有实时控制和安全功能且频率高达 400MHz 的四核 Arm® Cortex®-R5F MCU \| ZCZ \| 324 \| -40 to 105
文件：	总169页 (文件大小：3984K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM2634, AM2634-Q1, AM2632, AM2632-Q1, AM2631, AM2631-Q1

ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

AM263x Sitara™ 微控制器

传感和驱动：

1 特性

• 实时控制子系统(CONTROLSS)

• 灵活的输入/输出交叉开关(XBAR)

• 5 个12 位模数转换器(ADC)

处理器内核：

• 单核、双核和四核Arm^®Cortex^®-R5F MCU，每个

内核运行频率高达400 MHz

– 6 输入SAR ADC，高达4MSPS

– 16KB 指令缓存，每个CPU 内核具有64 位

• 6 个单端通道或

• 3 个差分通道

– 高度可配置的ADC 数字逻辑

ECC

– 16KB 数据缓存，每个CPU 内核具有32 位

ECC

– 64KB 紧耦合存储器(TCM)，每个CPU 内核具

有32 位ECC

– 支持锁步或双核模式的集群

• XBAR 转换启动(SOC) 触发

• 用户定义的采样保持(S+H)

• 灵活的后处理块(PPB)

• 带A 类可编程DAC 基准的10 个模拟比较器

(CMPSSA)

存储器子系统：

• 带B 类可编程DAC 基准的10 个模拟比较器

(CMPSSB)

• 1 个12 位数模转换器(DAC)

• 32 个脉宽调制(EPWM) 模块

• 2MB 片上RAM (OCSRAM)

– 4 组x 512KB

– ECC 错误保护

– 内部DMA 引擎支持

– 单或双PWM 通道

– 高级PWM 配置

片上系统(SoC) 服务和架构：

– 扩展的HRPWM 时间分辨率

• 10 个增强型捕获(ECAP) 模块

• 3 个增强型正交编码器脉冲(EQEP) 模块

• 2 个4 通道Σ-Δ滤波器模块(SDFM)

• 额外的信号多路复用交叉开关(XBAR)

• 1 个EDMA，支持数据移动功能

• 支持从以下接口启动器件：

– UART（主/备）

– QSPI NOR 闪存(4S/1S)（主）

• 处理器间通信模块

工业连接：

– 用于同步多核上运行的进程的自旋锁模块

– 通过CTRLMMR 寄存器实现的MAILBOX 功能

• 通过时间同步和比较事件中断路由器支持中央平台

时间同步(CPTS)

• 可编程实时单元(PRU-SS) 和

PRU 工业通信子系统(PRU-ICSS)

– 双核可编程实时单元子系统(PRU0/PRU1)

媒体和数据存储：

• 确定性硬件

• 动态固件

– 每个PRU 具有20 通道增强型输入(eGPI)

– 每个PRU 具有20 通道增强型输出(eGPO)

– 嵌入式外设和存储器

• 1 个4 位多媒体卡/安全数字(MMC/SD) 接口

• 通用存储器控制器(GPMC)

– 16 位并行数据总线和22 位地址总线

– 高达4MB 可寻址存储器空间

– 支持错误检查的集成错误定位模块(ELM)

• 1 个UART、1 个ECAP

• 1 个MDIO、1 个IEP

通用连接：

• 1 个32KB 共享通用RAM

• 2 个8KB 共享数据RAM

• 每个PRU 1 个12KB IRAM

• 暂存器(SPAD)、MAC/CRC

– 数字编码器和Σ-Δ控制环路

– PRU-ICSS 支持高级工业协议，包括：

• EtherCAT^®、Ethernet/IP^™、

• PROFINET^®、IO-Link^®，可供订购

– 专用中断控制器(INTC)

• 6 个通用异步接收器/发送器(UART)

• 5 个串行外设接口(SPI) 控制器

• 5 个本地互联网络(LIN) 端口

• 4 个内部集成电路(I2C) 端口

• 4 个支持CAN-FD 的模块化控制器局域网(MCAN)

模块

• 1 个四线串行外设接口(QSPI)

• 4 个快速串行接口发送器(FSITX)

• 4 个快速串行接口接收器(FSIRX)

• 多达140 个通用I/O (GPIO) 引脚

– 动态CONTROLSS XBAR 集成

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SPRSP74

AM2634, AM2634-Q1, AM2632, AM2632-Q1, AM2631, AM2631-Q1

ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

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高速接口：

功能安全：

• 支持设计具有功能安全要求的系统

• 支持两个外部端口的集成以太网交换机

– RMII (10/100) 或RGMII (10/100/1000)

– IEEE 1588（2008 附件D、E 和F）及

802.1AS PTP

– 具有指定SAFETY_ERRORn 引脚的错误信令模

块(ESM)

– 计算临界存储器具有ECC 或奇偶校验

– CPU 和片上RAM 的内置自检(BIST) 和故障注

入

– 运行时内部诊断模块，包括电压、温度和时钟监

控，窗口式看门狗计时器，用于存储器完整性检

查的CRC 引擎

– 第45 条MDIO PHY 管理规范

– 512 个基于ALE 引擎的数据包分类器

– 基于优先级的流量控制，数据包大小高达2KB

– 四个CPU 硬件中断节奏

– 硬件中的IP/UDP/TCP 校验和卸载

• 以符合功能安全标准为目标[工业]

安全性：

– 专为功能安全应用开发

– 可提供用于IEC 61508 功能安全系统设计的文

档

• 支持Auto SHE 1.1/EVITA 的硬件安全模块(HSM)

• 安全启动支持

– 器件接管保护

– 硬件强制可信根

– 经认证的引导

– 软件防回滚保护

– 以系统能力达到SIL-3 级为目标

– 以硬件完整性达到SIL-3 级为目标

– 安全相关认证

• 计划通过IEC 61508 认证

• 以符合功能安全标准为目标[汽车]

• 调试安全

– 仅在通过正确的身份验证后才能安全调试器件

– 能够禁用器件调试功能

• 器件ID 和密钥管理

– 专为功能安全应用开发

– 可提供用于ISO 26262 功能安全系统设计的文

档

– 以系统功能达到ASIL-D 级为目标

– 以硬件完整性达到ASIL-D 级为目标

– 安全相关认证

– 支持OTP 存储器(FUSEROM)

• 存储根密钥和其他安全字段

– 独立的EFUSE 控制器和FUSE ROM

– 公共设备唯一标识符(UID)

• 计划通过ISO 26262 认证

• 存储器保护单元(MPU)

技术/封装：

– 每个Cortex®-R5F 内核具有专用的Arm® MPU

– 系统MPU - 出现在SoC 中的各种接口上（MPU

或防火墙）

• 符合面向汽车应用的AEC-Q100 标准

• 45nm 技术

– 8-16 个可编程区域

• ZCZ 封装

• 启用/特权ID

• 起始/结束地址

• 读取/写入/可缓存

– 324 引脚NFBGA

– 15.0mm x 15.0mm

– 0.8 mm 间距

• 安全/非安全

• 加解密加速

2 应用

– 支持DMA 的加解密内核

– AES - 128/192/256 位密钥大小

– SHA2 - 256/384/512 位支持

– 带有伪真随机数生成器的DRBG

– 可在RSA/ECC 处理中提供帮助的PKA（公钥

加速器）

• 单轴及多轴伺服驱动器

• 交流逆变器和变频驱动器

• 太阳能

• 电动汽车充电

• 可再生能源存储

• 牵引逆变器

• 车载充电器

• 直流/直流转换器

• 电池管理系统

• 整体式架构

• IO 聚合器

• 域控制器

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ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

3 说明

AM263x Sitara^™Arm® 微控制器旨在满足下一代工业和汽车嵌入式产品复杂的实时处理需求。AM263x MCU 系

列包含多个具有多达四个400MHz Arm® Cortex®-R5F 内核的引脚对引脚兼容器件。可选择将 Arm® R5F 子系统

编程为在锁步或双核模式下运行，从而实现多种功能安全配置。工业通信子系统 (PRU-ICSS) 支持集成工业以太

网通信协议（例如 PROFINET®、TSN、Ethernet/IP®、EtherCAT® 以及多个其他协议）、标准以太网连接和自

定义I/O 接口。该系列面向使用高级模拟感应和数字驱动模块的未来电机控制和数字电源应用而设计。

多个 R5F 内核排列成具有 256KB 共享紧耦合存储器 (TCM) 和 2MB 共享 SRAM 的集群子系统，显著降低了对外

部存储器的需求。片上存储器、外设和互联中包含广泛的ECC，增强了可靠性。由硬件安全管理器(HSM) 管理的

粒度防火墙支持开发人员满足严格的安全敏感型系统设计要求。AM263x 器件还提供加解密加速和安全启动功

能。

TI 为AM263x 系列微控制器提供了一整套微控制器软件和开发工具。

封装信息

器件型号^{(1) (2)}

封装

封装尺寸

AM2634...ZCZ

15.0mm × 15.0mm

nFBGA [SiP]（324 引脚）

AM2632...ZCZ

AM2631...ZCZ

AM2634...ZCZQ1

AM2632...ZCZQ1

AM2631...ZCZQ1

(1) 如需更多信息，请参阅节11 机械、封装和可订购信息。

(2) 所有器件均采用托盘或卷带包装。

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ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

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3.1 功能方框图

图3-1 展示了器件的功能方框图。

AM263Ǩ

Realtime Cores

Industrial Connectivity

ICSS

Industrial Ethernet/Motor Control

Arm^®

Cortex^®-R5F

Sensing and Actuation

20x

Comparators

(CMPSS)

with DAC Ref

5x 6-ch ADC

3x eQEP

10x eCAP

128-KB TCM

12-bit DAC

32x eHRPWM

2x 4-ch SDFM

Arm^®

Connectivity

Cortex^®-R5F

MMC/SD

5x LIN

GPIO

5x SPI

4x CAN-FD

QSPI

128-KB TCM

Gb Ethernet

Switch w/ 1588

6x UART

4x I2C

Memory Subsystem

Security

Debug

AES

SHA

MD5

PKA

RNG

HSM

(Secure Boot)

2 MB SRAM with ECC

3DES

System Services

DMA

Firewall

DCC

ESM

ECC

Timers

Power

Manager

System

Monitor

Secure

Boot

Debug

IPC

图3-1. 功能方框图

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ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

Table of Contents

7.8 Electrical Characteristics...........................................68

7.9 VPP Specifications for One-Time Programmable

1 特性................................................................................... 1

2 应用................................................................................... 2

3 说明................................................................................... 3

3.1 功能方框图..................................................................4

4 Revision History.............................................................. 5

5 Device Comparison.........................................................7

5.1 Related Products........................................................ 8

6 Terminal Configuration and Functions..........................9

6.1 Pin Diagram................................................................ 9

6.2 Pin Attributes.............................................................10

6.3 Signal Descriptions................................................... 36

6.4 Pin Connectivity Requirements.................................63

7 Specifications................................................................ 64

7.1 Absolute Maximum Ratings...................................... 64

7.2 Electrostatic Discharge (ESD) Extended

(OTP) eFuses..............................................................74

7.10 Thermal Resistance Characteristics....................... 75

7.11 Timing and Switching Characteristics..................... 76

7.12 Decoupling Capacitor Requirements.................... 148

8 Detailed Description....................................................149

8.1 Overview.................................................................149

8.2 Processor Subsystems........................................... 150

9 Applications, Implementation, and Layout............... 151

9.1 Device Connection and Layout Fundamentals....... 151

10 Device and Documentation Support........................152

10.1 Device Nomenclature............................................152

10.2 Tools and Software............................................... 156

10.3 Documentation Support........................................ 156

10.4 支持资源................................................................156

10.5 Trademarks...........................................................156

10.6 Electrostatic Discharge Caution............................157

10.7 术语表................................................................... 157

11 Mechanical, Packaging, and Orderable

Automotive Ratings..................................................... 64

7.3 Electrostatic Discharge (ESD) Industrial Ratings......65

7.4 Power-On Hours (POH) Summary............................66

7.5 Recommended Operating Conditions.......................66

7.6 Operating Performance Points..................................66

7.7 Power Consumption Summary................................. 67

Information.................................................................. 158

4 Revision History

Changes from October 18, 2022 to November 18, 2022 (from Revision B (October 2022) to

Revision C (November 2022))

Page

• 通篇：将文档产品状态从“预告信息”更改为“量产数据”.............................................................................. 1

• 通篇：添加了以下新GPN：AM2632、AM2632-Q1、AM2631 和AM2631-Q1.................................................1

•

（封装信息）：添加了AM2631...ZCZQ1 行......................................................................................................3

• (Device Comparison): Updated/Changed the Arm Cortex-R5F row...................................................................7

• (Device Comparison): Added table note to clarify JTAG Device ID features......................................................7

• (Device Comparison): Updated Arm^®Cortex-R5 reference name to R5FSS.....................................................7

• (Device Comparison): Updated Hardware Security Module reference name to HSM........................................7

• (Pin Attributes): Updated/Changed all applicable Ball State After Reset values from "Off / Off / Off" to "Off /

On / Down"........................................................................................................................................................13

• (Pin Attributes): Updated/Changed QSPI0_CLKLB Ball State After Reset value from "Off / Off / Off" to "On /

On / Down"........................................................................................................................................................13

• (Operating Performance Points): Removed M grade row.................................................................................64

• (Power Consumption Summary): Renamed Power Consumption Summary to Power Consumption -

Maximum......................................................................................................................................................... 67

• (Power Consumption Summary): Added Power Consumption - Typical and Power Consumption -

Traction Inverter sections............................................................................................................................... 67

• (Analog-to-Digital Converter (ADC)): Updated Input Conversion MAX Range from "33/18 x V_REFFHIV" to

"32/18 x V_REFHIV" ............................................................................................................................................68

• (Analog-to-Digital Converter (ADC)): Updated TYP V_REFHIinput current from "300 µA" to "400 µA"...............68

• (Analog-to-Digital Converter (ADC)): Added TYP Input Leakage value........................................................... 68

• (Analog-to-Digital Converter (ADC)): Updated Power Consumption (VDDA18) TYP value from "500 µA" to

"700 µA"............................................................................................................................................................68

• (Comparator Subsystem A (CMPSSA)): Removed first option for Comparator input range MAX parameter.. 68

• (Comparator Subsystem A (CMPSSA)): Updated DAC static offset error MIN value from "–20 mV" to "–45

mV" and MAX value from "70 mV" to "45 mV"..................................................................................................68

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• (Comparator Subsystem A (CMPSSA)): Updated DAC_VREF loading TYP value from "6 kΩ" to "37 kΩ"..... 68

• (Comparator Subsystem A (CMPSSA)): Updated Input Leakage TYP value "1 μA" to "0.1 μA" and added

MAX value "5 μA"............................................................................................................................................68

• (Comparator Subsystem B (CMPSSB)): Updated Comparator input range MIN value from "0 V" to "0.1 V" and

MAX value from "1.8 x DAC_VREF" to "VDDA33 - 50mV"...............................................................................68

• (Comparator Subsystem B (CMPSSB)): Updated DAC output range MIN value from "0 V" to "0.1 V" and MAX

value from "DAC_VREF" to "Minimum of 33/18 x DAC_VREF or VDDA33 - 50mV"....................................... 68

• (Comparator Subsystem B (CMPSSB)): Updated DAC static offset error MIN value from "–20 mV" to "–45

mV" and max value from "70 mV" to "45 mV"...................................................................................................68

• (Comparator Subsystem B (CMPSSB)): Updated DAC MAX settling time from "2 μs" to "1 μs".................. 68

• (Comparator Subsystem B (CMPSSB)): Updated DAC_VREF loading TYP value from "6 kΩ" to "37 kΩ"..... 68

• (Comparator Subsystem B (CMPSSB)): Updated Input Leakage TYP value "1 μA" to "0.1 μA" and added

MAX value "5 μA"............................................................................................................................................68

• (Digital-to-Analog Converter (DAC)): Updated Power-up time MAX value from "10 µs" to "1 µs" ...................68

• (Hardware Design Guide): Added new section...............................................................................................151

• (Device Naming Convention): Changed "Device Speed and Memory Grades" to "Device Operating

Performance Points".......................................................................................................................................154

• (Device Naming Convention): Removed M OPP speed grade row................................................................154

• (Documentation Support): Added AM263x TRM Register Addendum Link....................................................156

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5 Device Comparison

表5-1 shows a comparison between devices, highlighting the differences.

表5-1. Device Comparison

REFERENCE

NAME

FEATURES

AM2634

AM2632

AM2631

JTAG DEVICE ID COMPARISON (FEATURES)

JTAG Device ID⁽¹⁾

Industrial:

M: 0x4111BBE6

M: 0x4109BBE6

L: 0x41119BE6

K: 0x41117BE6

E: 0x4110BBE6

D: 0x41109BE6

L: 0x41099BE6

K: 0x41097BE6

E: 0x4108BBA6

D: 0x41089BA6

E: 0x4104B3A6

D: 0x410493A6

Extended

K: 0x41117BFE

K: 0x41097BFE

Automotive:

D: 0x41109BFE (Grade O)

D: 0x41109C3E (Grade P)

D: 0x41089BFE (Grade O)

D: 0x41089C3E (Grade P)

D: 0x410493BE

PROCESSORS AND ACCELERATORS

Speed Grade

See 节7.6, Operating Performance Points

Arm^®Cortex-R5F

R5FSS

HSM

Yes

Hardware Security Module

Crypto Accelerators

Security

Yes

PROGRAM AND DATA STORAGE

On-Chip Shared Memory (RAM)

R5F Tightly Coupled Memory (TCM)

General-Purpose Memory Controller

PERIPHERALS

OCSRAM

TCM

See 节7.6, Operating Performance Points

256KB

4MB

GPMC

Modular Controller Area Network Interface

Full CAN-FD Support

MCAN

GPIO

General-Purpose I/O

Up to 140

Serial Peripheral Interface

SPI

Universal Asynchronous Receiver and Transmitter

Local Interconnect Network

UART

LIN

Inter-Integrated Circuit Interface

Analog-to-Digital Converter

I2C

3⁽³⁾or 5⁽⁴⁾

12⁽³⁾or 20⁽⁴⁾

ADC

3⁽³⁾or 5⁽⁴⁾

Comparator Modules

CMPSS

DAC

12⁽³⁾or 20⁽⁴⁾

Digital-to-Analog Converter

Programmable Real-Time Unit Subsystem⁽⁵⁾

Industrial Communication Subsystem Support⁽⁶⁾

Gigabit Ethernet Interface

PRU-ICSS

CPSW3G

MMCSD

EHRPWM

ECAP

EQEP

SDFM

FSI

0 or 1

Optional

Yes (2-port)

Multi-Media Card/Secure Digital Interface

Enhanced High-Resolution Pulse-Width Modulator Module

Enhanced Capture Module

16⁽²⁾or 32⁽⁴⁾

5⁽³⁾or 10⁽⁴⁾

2⁽³⁾or 3⁽⁴⁾

1⁽³⁾or 2⁽⁴⁾

16⁽³⁾or 32⁽⁴⁾

5⁽³⁾or 10⁽⁴⁾

2⁽³⁾or 3⁽⁴⁾

1⁽³⁾or 2⁽⁴⁾

4x FSI_RX + 4x FSI_TX

Enhanced Quadrature Encoder Pulse Module

Sigma Delta Filter Module

Fast Serial Interface

Quad SPI Flash Interface

QSPI

Miscellaneous

Junction Temperature

Industrial: –40°C to 105°C

Extended Automotive: –40°C to 150°C

AEC-Q100⁽⁷⁾Option

Automotive Qualification

(1) "X:" letter refers to feature parameter and (Grade "X") refers to Grade in the 节7.6, Operating Performance Points table.

(2) For more details about the CTRLMMR_WKUP_JTAG_DEVICE_ID register and DEVICE_ID bit field, see the device TRM.

(3) Standard Analog configuration contains 3x ADC, 16x EHRPWM, 5x eCAP, 2x EQEP, 1x SDFM, 12x CMPSS

(4) Enhanced Analog configuration contains 5x ADC, 32x EHRPWM, 10x eCAP, 3x EQEP, 2x SDFM, 20x CMPSS

(5) Programmable Real-Time Unit Subsystem is available when selecting an orderable part number that includes a feature code of D, E, F,

K, L, or M. Refer to the Nomenclature Description table for definition of feature codes.

(6) Industrial Communication Subsystem Support is available when selecting an orderable part number that includes a feature code of D,

E, F, K, L, or M. Refer to the Nomenclature Description table for definition of feature codes.

(7) AEC-Q100 qualification is applicable to select part number variants as indicated by the Automotive Designator (Q1) identifier in the

Nomenclature Description table.

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5.1 Related Products

Sitara™ Microcontrollers Family of Arm® Cortex®-R based high performance microcontrollers with advanced

networking, real-time control, and signal processing accelerators to meet emerging MCU requirements for

industrial and automotive applications.

Sitara™ Processors Family of broad, scalable processors based on Arm® Cortex®-A cores with flexible

accelerators, peripherals, connectivity and unified software support –an excellent choice for sensors to servers.

Sitara™ processors have the features and reliability necessary for the latest industrial and automotive

application-level requirements.

Sitara™ Microcontrollers - Evaluation Modules TI provides device-specific Evaluation Module (EVM) designs

to help kick-start product development. See the AM263x ControlCard and AM263x LaunchPad for more

information.

Products to complete your design The following list of products are frequently purchased or used in

conjunction with the AM263x device to meet your system design requirements.

• TPS653851A-Q1 - Functional safety-compliant multi-rail power supply for safety MCUs for Q100 grade-0

applications.

• TPS3704-Q1 - Automotive multichannel window supervisor with very-high accuracy and compact form factor.

• DP83TG720S-Q1 - 1000BASE-T1 automotive Ethernet PHY with RGMII.

• DP83826E - Low latency 10/100-Mbps Ethernet PHY with MII interface and enhanced mode.

• TCAN1042H-Q1 - Automotive 70-V bus-fault-protected CAN transceiver with flexible data-rate.

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6 Terminal Configuration and Functions

6.1 Pin Diagram

备注

The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt

is made to use "ball" only when referring to the physical package.

The diagrams in this section are used in conjunction with the other Terminal Configuration and Functions tables

to locate signal names and ball grid numbers.

6.1.1 ZCZ Pin Diagram

PR0_PRU1

_GPIO11

PR0_PRU1

_GPIO9

PR0_PRU1

_GPIO8

PR0_PRU1

_GPIO3

PR0_PRU1

_GPIO0

PR0_PRU0

_GPIO10

PR0_PRU0

_GPIO16

PR0_PRU0

_GPIO2

PR0_PRU0

_GPIO1

PR0_MDIO0

_MDC

RGMII1_TX

_CTL

RGMII1

_TXC

RGMII1

_TD2

RGMII1_RX

_CTL

RGMII1

_RD3

RGMII1

_RD2

VSS

PR0_PRU1

_GPIO15

PR0_PRU1

_GPIO12

PR0_PRU1

_GPIO14

PR0_PRU1

_GPIO10

PR0_PRU1

_GPIO2

PR0_PRU0

_GPIO9

PR0_PRU0

_GPIO5

PR0_PRU0

_GPIO13

PR0_PRU0

_GPIO3

PR0_PRU0

_GPIO0

PR0_MDIO0

_MDIO

RGMII1

_TD3

RGMII1

_TD1

RGMII1

_RXC

RGMII1

_RD1

RGMII1

_RD0

MDIO0_MDC

EPWM14_A

VSSA

SDFM0

_CLK1

SDFM0

_CLK0

PR0_PRU1

_GPIO16

PR0_PRU1

_GPIO13

PR0_PRU1

_GPIO6

PR0_PRU1

_GPIO4

PR0_PRU1

_GPIO1

PR0_PRU0

_GPIO14

PR0_PRU0

_GPIO4

PR0_PRU0

_GPIO15

PR0_PRU0

_GPIO11

MDIO0

_MDIO

RGMII1

_TD0

RSVD_J16

VDDAR1

VSS

EPWM15_B

VDDS33

EPWM14_B

ADC_CAL1

ADC0_AIN2

ADC_CAL0

ADC0_AIN1

ADC0_AIN3

SDFM0

_CLK3

SDFM0

_CLK2

PR0_PRU1

_GPIO18

PR0_PRU1

_GPIO19

PR0_PRU1

_GPIO5

PR0_PRU0

_GPIO8

PR0_PRU0

_GPIO6

PR0_PRU0

_GPIO12

VDDS18

VSS

VDDS33

VSS

VDDS33

VSS

VDDS18

VDD

EPWM15_A

ADC0_AIN0

ADC

_VREFHI

_G0

EQEP0_B

I2C0_SCL

MCAN2_RX

SPI0_CLK

SPI1_CLK

LIN1_RXD

LIN2_TXD

UART0_RXD

EQEP0_A

I2C0_SDA

MCAN2_TX

SPI0_D1

SDFM0_D3

SDFM0_D2

EQEP0_S

SPI0_CS0

SPI0_D0

SDFM0_D0

SDFM0_D1

VDDS33

EQEP0_I

VDDAR2

SPI1_D1

VDDS33

I2C1_SCL

VDDS18

TMS

VSS

VDD

VSS

ADC0_AIN5

VSSA

ADC

_VREFLO

_G0

VSS

VDD

VSS

DAC_VREF0 ADC0_AIN4

VSS

VSSA

ADC1_AIN5

VDDA18

ADC1_AIN2

ADC1_AIN0

ADC2_AIN1

ADC2_AIN3

ADC2_AIN5

ADC3_AIN2

ADC1_AIN4

ADC1_AIN1

ADC2_AIN2

ADC3_AIN5

ADC3_AIN1

ADC3_AIN0

ADC1_AIN3

ADC

_VREFLO

_G1

VDD

VSS

VDDA33

VSSA

ADC

_VREFHI

_G1

SPI1_D0

VSS

ADC2_AIN0

LIN1_TXD

LIN2_RXD

SPI1_CS0

I2C1_SDA

VDD

VSS

VDDA33

VSSA

VDD

ADC2_AIN4

ADC3_AIN4

VSS

VDDA18

ADC

_VREFLO

_G2

UART0

_CTSn

UART0

_RTSn

VSS

VDDA33

VSSA

ADC3_AIN3

ADC

_VREFHI

_G2

VDDA18

_LDO

UART0_TXD MMC0_CLK

MMC0_WP

VSS

VDD

VSS

VDD

VSS

VDD

DAC_VREF1 ADC4_AIN0

MMC0_CD

MMC0_CMD

MMC0_D2

MMC0_D3

VSS

MMC0_D0

MMC0_D1

TCK

TDI

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VSSA

DAC_OUT

RSVD_T4

ADC4_AIN3

ADC4_AIN5

RSVD_U3

ADC4_AIN1

ADC4_AIN2

ADC4_AIN4

RSVD_V2

SAFETY

_ERRORn

VDDA18

_OSC_PLL

TDO

EPWM4_B

EPWM3_B

EPWM3_A

EPWM6_A

EPWM7_A

EPWM6_B

EPWM5_A

EPWM7_B

EPWM10_A

EPWM8_A

EPWM5_B

EPWM9_A

VDDS33

VDDAR3

EPWM8_B

EPWM11_A

EPWM12_B

EPWM10_B

EPWM9_B

EPWM11_B

EPWM13_A

VDDS18

QSPI0_D2

QSPI0_D1

VDDS33

QSPI0_D3

QSPI0

_CSn1

VDDS18

_LDO

WARMRSTn

EPWM2_A

EPWM2_B

EPWM1_A

EPWM1_B

EPWM4_A

EPWM13_B UART1_RXD UART1_TXD

VPP

EXT

_REFCLK0

EPWM0_A

EPWM0_B

EPWM12_A

MCAN1_TX

MCAN1_RX

MCAN0_TX

CLKOUT0

QSPI0_CLK

QSPI0_D0

PORz

VSS

VSYS_MON

RSVD_U1

QSPI0

_CSn0

MCAN0_RX

XTAL_XO

XTAL_XI

VSSA

Not to scale

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6.2 Pin Attributes

The following list describes the contents of each column in the Pin Attributes table:

1. Ball Number: Ball numbers assigned to each terminal of the Ball Grid Array package.

2. Ball Name: Ball name assigned to each terminal of the Ball Grid Array package (this name is typically taken

from the primary MUXMODE 0 signal function).

3. Signal Name: Signal name of all dedicated and pin multiplexed signal functions associated with a ball.

备注

The Pin Attributes table, defines the SoC pin multiplexed signal function implemented at the pin

and does not define secondary multiplexing of signal functions implemented in device

subsystems. Secondary multiplexing of signal functions are not described in this table. For more

information on secondary multiplexed signal functions, see the respective peripheral chapter of

the device TRM.

4. Mux Mode: The MUXMODE value associated with each pin multiplexed signal function:

• MUXMODE 0 is the primary pin multiplexed signal function. However, the primary pin multiplexed signal

function is not necessarily the default pin multiplexed signal function.

• MUXMODE values 1 through 15 are possible for pin multiplexed signal functions. However, not all

MUXMODE values have been implemented. The only valid MUXMODE values are those defined as pin

multiplexed signal functions within the Pin Attributes table. Only defined valid values of MUXMODE can

be used.

• Bootstrap defines SOC configuration pins, where the logic state applied to each pin is latched on the

rising edge of PORz. These input signal functions are fixed to their respective pins and are not

programmable via MUXMODE.

• An empty box or "-" means Not Applicable.

备注

• The value found in the MUX MODE AFTER RESET column defines the default pin multiplexed

signal function selected when PORz is deasserted.

• Configuring two pins to the same pin multiplexed signal function can yield unexpected results

and is not supported. This can be prevented with proper software configuration.

• Configuring a pad to an undefined multiplexing mode results in undefined behavior and must

be avoided.

5. Type: Signal type and direction:

• I = Input

• O = Output

• ID = Input, with open-drain output function

• OD = Output, with open-drain output function

• IO = Input, Output, or simultaneously Input and Output

• IOD = Input, Output, or simultaneously Input and Output, with open-drain output function

• IOZ = Input, Output, or simultaneously Input and Output, with three-state output function

• OZ = Output with three-state output function

• A = Analog

• CAP = LDO capacitor

• PWR = Power

• GND = Ground

6. DSIS: The deselected input state (DSIS) indicates the state driven to the subsystem input (logic "0", logic

"1", or "pad" level) when the pin multiplexed signal function is not selected by MUXMODE.

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• 0: Logic 0 driven to the subsystem input.

• 1: Logic 1 driven to the subsystem input.

• pad: Logic state of the pad is driven to the subsystem input.

• An empty box, NA, or "-" means Not Applicable.

7. Ball State During Reset (RX/TX/PULL): State of the terminal while PORz is asserted, where RX defines

the state of the input buffer, TX defines the state of the output buffer, and PULL defines the state of internal

pull resistors:

• RX (Input buffer)

– Off: The input buffer is disabled.

– On: The input buffer is enabled.

• TX (Output buffer)

– Off: The output buffer is disabled.

– Low: The output buffer is enabled and drives V_OL

• PULL (Internal pull resistors)

– Off: Internal pull resistors are turned off.

– Up: Internal pull-up resistor is turned on.

– Down: Internal pull-down resistor is turned on.

– NA: No internal pull resistor.

• An empty box, or "-" means Not Applicable.

8. Ball State After Reset (RX/TX/PULL): State of the terminal after PORz is deasserted, where RX defines the

state of the input buffer, TX defines the state of the output buffer, and PULL defines the state of internal pull

resistors:

• RX (Input buffer)

– Off: The input buffer is disabled.

– On: The input buffer is enabled.

• TX (Output buffer)

– Off: The output buffer is disabled.

– SS: The subsystem selected with MUXMODE determines the output buffer state.

• PULL (Internal pull resistors)

– Off: Internal pull resistors are turned off.

– Up: Internal pull-up resistor is turned on.

– Down: Internal pull-down resistor is turned on.

– NA: No internal pull resistor.

• An empty box, NA, or "-" means Not Applicable.

9. Mux Mode After Reset: The value found in this column defines the default pin multiplexed signal function

after PORz is deasserted.

• An empty box, NA, or "-" means Not Applicable.

10. I/O Voltage: This column describes I/O operating voltage options of the respective power supply, when

applicable.

• An empty box, NA, or "-" means Not Applicable.

For more information, see valid operating voltage range defined for each power supply in Recommended

Operating Conditions.

11. Power: The power supply of the associated I/O, when applicable.

• An empty box, NA, or "-" means Not Applicable.

12. Hys: Indicates if the input buffer associated with this I/O has hysteresis:

• Yes: Hysteresis Support

• No: No Hysteresis Support

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• An empty box, NA, or "-" means Not Applicable.

For more information, see the hysteresis values in Electrical Characteristics.

13. Pull Type: Indicates the presence of an internal pull-up or pull-down resistor. Internal resistors can be

enabled or disabled via software.

• PU: Internal pull-up Only

• PD: Internal pull-down Only

• PU/PD: Internal pull-up and pull-down

• An empty box, NA, or "-" means No internal pull.

备注

Configuring two pins to the same pin multiplexed signal function is not supported as this yields

unexpected results. Issues can be easily prevented with the proper software configuration.

When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s

behavior is undefined. This must be avoided.

14. Buffer Type: This column defines the buffer type associated with a terminal. This information can be used to

determine the applicable Electrical Characteristics table.

• An empty box, NA, or "-" means Not Applicable.

For electrical characteristics, refer to the appropriate buffer type table in Electrical Characteristics.

15. Pad Configuration Register Name: This is the name of the device pad/pin configuration register.

16. Pad Configuration Register Address: This is the memory address of the device pad/pin configuration

17. Pad Configuration Register Default Value: This is the default value of the register device pad/pin

configuration register after PORz is deasserted.

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表6-1. Pin Attributes (ZCZ Package)

BALL NAME [2]/

IOMUX

ADDRESS [16]/

DEFAULT VALUE [17]

BALL

MUX

MODE

AFTER

BALL

NUMBER

[1]

STATE

DURING

RESET

STATE

AFTER

RESET

VOLTAGE

[10]

PULL

TYPE

[13]

MUX

MODE [4]

HYS

[12] TYPE [14]

BUFFER

SIGNAL NAME [3]

TYPE [5]

POWER [11]

RESET [9]

RX/TX/PULL [7]

RX/TX/PULL [8]

V15

U15

T14

U14

U13

R14

T11

U11

T12

V12

U12

R12

R10

T10

U10

ADC0_AIN0

ADC0_AIN1

ADC0_AIN0

ADC0_AIN1

ADC0_AIN2

ADC0_AIN3

ADC0_AIN4

ADC0_AIN5

ADC1_AIN0

ADC1_AIN1

ADC1_AIN2

ADC1_AIN3

ADC1_AIN4

ADC1_AIN5

ADC2_AIN0

ADC2_AIN1

ADC2_AIN2

ADC2_AIN3

ADC2_AIN4

ADC2_AIN5

ADC3_AIN0

ADC3_AIN1

ADC3_AIN2

ADC3_AIN3

ADC3_AIN4

ADC3_AIN5

ADC4_AIN0

ADC4_AIN1

ADC4_AIN2

ADC4_AIN3

ADC4_AIN4

ADC4_AIN5

ADC_CAL0

ADC_CAL1

3.3 V

1.8 V

VDDA_CIO

AnalogCIO

ADC0_AIN2

ADC0_AIN3

ADC0_AIN4

ADC0_AIN5

ADC1_AIN0

ADC1_AIN1

ADC1_AIN2

ADC1_AIN3

ADC1_AIN4

ADC1_AIN5

ADC2_AIN0

ADC2_AIN1

ADC2_AIN2

ADC2_AIN3

ADC2_AIN4

ADC2_AIN5

ADC3_AIN0

ADC3_AIN1

ADC3_AIN2

ADC3_AIN3

ADC3_AIN4

ADC3_AIN5

ADC4_AIN0

ADC4_AIN1

ADC4_AIN2

ADC4_AIN3

ADC4_AIN4

ADC4_AIN5

ADC_CAL0

U16

T15

V14

V10

ADC_CAL1

ADC_VREFHI_G0

ADC_VREFHI_G1

ADC_VREFHI_G2

ADC_VREFLO_G0

ADC_VREFHI_G0

ADC_VREFHI_G1

ADC_VREFHI_G2

ADC_VREFLO_G0

V13

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表6-1. Pin Attributes (ZCZ Package) (continued)

BALL NAME [2]/

IOMUX

ADDRESS [16]/

DEFAULT VALUE [17]

BALL

MUX

MODE

AFTER

BALL

NUMBER

[1]

STATE

DURING

RESET

STATE

AFTER

RESET

VOLTAGE

[10]

PULL

TYPE

[13]

MUX

MODE [4]

HYS

[12] TYPE [14]

BUFFER

SIGNAL NAME [3]

TYPE [5]

POWER [11]

RESET [9]

RX/TX/PULL [7]

RX/TX/PULL [8]

V11

ADC_VREFLO_G1

1.8 V

3.3 V

VDDA_CIO

VDDSHV0

AnalogCIO

ADC_VREFLO_G2

CLKOUT0

ADC_VREFLO_G2

CLKOUT0

Off / Off / Off

Off / SS / Off

Yes

LVCMOS

PU/PD

CLKOUT0_CFG_REG

0x5310 0228

GPIO138

0x0000 0570

T13

DAC_OUT

DAC_VREF0

DAC_VREF1

EPWM0_A

GPIO43

3.3 V

VDDA_CIO

VDDSHV0

AnalogCIO

LVCMOS

DAC_VREF0

DAC_VREF1

EPWM0_A

Off / Off / Off

Off / On / Down

Yes

PU/PD

EPWM0_A_CFG_REG

0x5310 00AC

0x0000 05F7

EPWM0_B

GPIO44

3.3 V

VDDSHV0

LVCMOS

EPWM0_B_CFG_REG

0x5310 00B0

0x0000 05F7

EPWM1_A

GPIO45

EPWM1_A_CFG_REG

0x5310 00B4

0x0000 05F7

EPWM1_B

GPIO46

EPWM1_B_CFG_REG

0x5310 00B8

0x0000 05F7

EPWM2_A

GPIO47

EPWM2_A_CFG_REG

0x5310 00BC

0x0000 05F7

EPWM2_B

GPIO48

EPWM2_B_CFG_REG

0x5310 00C0

0x0000 05F7

EPWM3_A

GPIO49

EPWM3_A_CFG_REG

0x5310 00C4

0x0000 05F7

EPWM3_B

GPIO50

EPWM3_B_CFG_REG

0x5310 00C8

0x0000 05F7

EPWM4_A

GPIO51

EPWM4_A_CFG_REG

0x5310 00CC

0x0000 05F7

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表6-1. Pin Attributes (ZCZ Package) (continued)

BALL NAME [2]/

IOMUX

ADDRESS [16]/

DEFAULT VALUE [17]

BALL

MUX

MODE

AFTER

BALL

NUMBER

[1]

STATE

DURING

RESET

STATE

AFTER

RESET

VOLTAGE

[10]

PULL

TYPE

[13]

MUX

MODE [4]

HYS

[12] TYPE [14]

BUFFER

SIGNAL NAME [3]

TYPE [5]

POWER [11]

RESET [9]

RX/TX/PULL [7]

RX/TX/PULL [8]

EPWM4_B

EPWM4_B_CFG_REG

0x5310 00D0

0x0000 05F7

EPWM4_B

FSITX1_CLK

GPIO52

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

EPWM5_A

VDDSHV0

EPWM5_A_CFG_REG

0x5310 00D4

0x0000 05F7

FSITX1_DATA0

GPIO53

EPWM5_B

FSITX1_DATA1

GPIO54

EPWM5_B_CFG_REG

0x5310 00D8

0x0000 05F7

EPWM6_A

FSIRX1_CLK

GPIO55

EPWM6_A_CFG_REG

0x5310 00DC

0x0000 05F7

EPWM6_B

FSIRX1_DATA0

GPIO56

EPWM6_B_CFG_REG

0x5310 00E0

0x0000 05F7

EPWM7_A

FSIRX1_DATA1

GPIO57

EPWM7_A_CFG_REG

0x5310 00E4

0x0000 05F7

EPWM7_B

GPIO58

EPWM7_B_CFG_REG

0x5310 00E8

0x0000 05F7

EPWM8_A

UART4_TXD

I2C3_SDA

FSITX2_CLK

GPIO59

EPWM8_A_CFG_REG

0x5310 00EC

0x0000 05F7

IOD

EPWM8_B

UART4_RXD

I2C3_SCL

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

EPWM8_B_CFG_REG

0x5310 00F0

0x0000 05F7

IOD

FSITX2_DATA0

GPIO60

EPWM9_A

FSITX2_DATA1

GPIO61

Off / Off / Off

Off / On / Down

3.3 V

EPWM9_A_CFG_REG

0x5310 00F4

0x0000 05F7

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表6-1. Pin Attributes (ZCZ Package) (continued)

BALL NAME [2]/

IOMUX

ADDRESS [16]/

DEFAULT VALUE [17]

BALL

MUX

MODE

AFTER

BALL

NUMBER

[1]

STATE

DURING

RESET

STATE

AFTER

RESET

VOLTAGE

[10]

PULL

TYPE

[13]

MUX

MODE [4]

HYS

[12] TYPE [14]

BUFFER

SIGNAL NAME [3]

TYPE [5]

POWER [11]

RESET [9]

RX/TX/PULL [7]

RX/TX/PULL [8]

EPWM9_B

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

EPWM9_B_CFG_REG

0x5310 00F8

0x0000 05F7

UART1_RTSn

FSIRX2_CLK

GPIO62

EPWM10_A

UART1_CTSn

VDDSHV0

EPWM10_A_CFG_REG

0x5310 00FC

0x0000 05F7

FSIRX2_DATA0

GPIO63

EPWM10_B

UART2_RTSn

FSIRX2_DATA1

GPIO64

EPWM10_B_CFG_REG

0x5310 0100

0x0000 05F7

EPWM11_A

UART2_CTSn

GPMC0_CLKLB

GPIO65

EPWM11_A_CFG_REG

0x5310 0104

0x0000 05F7

EPWM11_B

UART3_RTSn

GPMC0_OEn_REn

GPIO66

EPWM11_B_CFG_REG

0x5310 0108

0x0000 05F7

EPWM12_A

UART3_CTSn

SPI4_CS1

EPWM12_A_CFG_REG

0x5310 010C

0x0000 05F7

GPMC0_WEn

GPIO67

EPWM12_B

UART1_DCDn

GPMC0_CSn0

GPIO68

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

EPWM12_B_CFG_REG

0x5310 0110

0x0000 05F7

EPWM13_A

UART1_RIn

GPMC0_AD0

GPIO69

EPWM13_A_CFG_REG

0x5310 0114

0x0000 05F7

EPWM13_B

UART1_DTRn

GPMC0_AD1

GPIO70

EPWM13_B_CFG_REG

0x5310 0118

0x0000 05F7

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ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

表6-1. Pin Attributes (ZCZ Package) (continued)

BALL NAME [2]/

IOMUX

ADDRESS [16]/

DEFAULT VALUE [17]

BALL

MUX

MODE

AFTER

BALL

NUMBER

[1]

STATE

DURING

RESET

STATE

AFTER

RESET

VOLTAGE

[10]

PULL

TYPE

[13]

MUX

MODE [4]

HYS

[12] TYPE [14]

BUFFER

SIGNAL NAME [3]

TYPE [5]

POWER [11]

RESET [9]

RX/TX/PULL [7]

RX/TX/PULL [8]

V17

T16

P15

EPWM14_A

EPWM14_A_CFG_REG

0x5310 011C

0x0000 05F7

EPWM14_A

UART1_DSRn

GPMC0_AD2

GPIO71

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

EPWM14_B

MII1_RX_ER

GPMC0_AD3

GPIO72

VDDSHV0

EPWM14_B_CFG_REG

0x5310 0120

0x0000 05F7

EPWM15_A

UART5_TXD

MII1_COL

EPWM15_A_CFG_REG

0x5310 0124

0x0000 05F7

GPMC0_AD4

GPIO73

R16

B14

A14

D11

EPWM15_B

UART5_RXD

MII1_CRS

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

EPWM15_B_CFG_REG

0x5310 0128

0x0000 05F7

GPMC0_AD5

GPIO74

EQEP0_A

UART4_RTSn

SPI4_CLK

GPIO130

EQEP0_A_CFG_REG

0x5310 0208

0x0000 05F7

EQEP0_A

SDFM1_CLK0

UART4_CTSn

SPI4_CS0

GPIO131

EQEP0_B

EQEP0_B_CFG_REG

0x5310 020C

0x0000 05F7

EQEP0_B

SDFM1_D0

UART4_RXD

LIN4_RXD

SPI4_D1

EQEP0_I

EQEP0_I_CFG_REG

0x5310 0214

0x0000 05F7

GPIO133

EQEP0_I

SDFM1_D1

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ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

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表6-1. Pin Attributes (ZCZ Package) (continued)

BALL NAME [2]/

IOMUX

ADDRESS [16]/

DEFAULT VALUE [17]

BALL

MUX

MODE

AFTER

BALL

NUMBER

[1]

STATE

DURING

RESET

STATE

AFTER

RESET

VOLTAGE

[10]

PULL

TYPE

[13]

MUX

MODE [4]

HYS

[12] TYPE [14]

BUFFER

SIGNAL NAME [3]

TYPE [5]

POWER [11]

RESET [9]

RX/TX/PULL [7]

RX/TX/PULL [8]

C12

EQEP0_S

UART4_TXD

LIN4_TXD

SPI4_D0

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

EQEP0_S_CFG_REG

0x5310 0210

0x0000 05F7

GPIO132

EQEP0_S

SDFM1_CLK1

EXT_REFCLK0

XBAROUT15

GPIO121

A13

B13

EXT_REFCLK0

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

I2C OD

PU/PD

EXT_REFCLK0_CFG_REG

0x5310 01E4

0x0000 05F7

IOD

EQEP1_I

I2C0_SCL

GPIO135

I2C0_SCL_CFG_REG

0x5310 021C

0x0000 05F7

EQEP2_B

SDFM1_CLK3

I2C0_SDA

GPIO134

I2C0_SDA

I2C OD

I2C0_SDA_CFG_REG

0x5310 0218

0x0000 05F7

EQEP2_A

SDFM1_CLK2

I2C1_SCL

SPI3_CS0

XBAROUT7

GPIO23

I2C1_SCL

LVCMOS

PU/PD

I2C1_SCL_CFG_REG

0x5310 005C

0x0000 05F7

IOD

I2C1_SDA

SPI3_CLK

XBAROUT8

GPIO24

I2C1_SDA_CFG_REG

0x5310 0060

0x0000 05F7

LIN1_RXD

UART1_RXD

SPI2_CS0

XBAROUT5

GPIO19

LIN1_RXD_CFG_REG

0x5310 004C

0x0000 05F7

LIN1_TXD

UART1_TXD

SPI2_CLK

XBAROUT6

GPIO20

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

LIN1_TXD_CFG_REG

0x5310 0050

0x0000 05F7

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ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

表6-1. Pin Attributes (ZCZ Package) (continued)

BALL NAME [2]/

IOMUX

ADDRESS [16]/

DEFAULT VALUE [17]

BALL

MUX

MODE

AFTER

BALL

NUMBER

[1]

STATE

DURING

RESET

STATE

AFTER

RESET

VOLTAGE

[10]

PULL

TYPE

[13]

MUX

MODE [4]

HYS

[12] TYPE [14]

BUFFER

SIGNAL NAME [3]

TYPE [5]

POWER [11]

RESET [9]

RX/TX/PULL [7]

RX/TX/PULL [8]

LIN2_RXD

LIN2_RXD_CFG_REG

0x5310 0054

0x0000 05F7

LIN2_RXD

UART2_RXD

SPI2_D0

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

GPIO21

LIN2_TXD

UART2_TXD

SPI2_D1

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

PU/PD

LIN2_TXD_CFG_REG

0x5310 0058

0x0000 05F7

GPIO22

MCAN0_RX

SPI4_CS0

GPIO7

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

MCAN0_RX_CFG_REG

0x5310 001C

0x0000 05F7

MCAN0_TX

SPI4_CLK

GPIO8

MCAN0_TX_CFG_REG

0x5310 0020

0x0000 05F7

MCAN1_RX

SPI4_D0

GPIO9

MCAN1_RX_CFG_REG

0x5310 0024

0x0000 05F7

MCAN1_TX

SPI4_D1

GPIO10

MCAN1_TX_CFG_REG

0x5310 0028

0x0000 05F7

A12

MCAN2_RX

UART2_RTSn

GPIO137

MCAN2_RX_CFG_REG

0x5310 0224

0x0000 05F7

EQEP2_I

SDFM1_D3

MCAN2_TX

UART1_RTSn

GPIO136

B12

MCAN2_TX

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

MCAN2_TX_CFG_REG

0x5310 0220

0x0000 05F7

EQEP2_S

SDFM1_D2

MDIO0_MDC

GPIO42

M17

N16

MDIO0_MDC

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

MDIO0_MDC_CFG_REG

0x5310 00A8

0x0000 05F7

MDIO0_MDIO

GPIO41

MDIO0_MDIO_CFG_REG

0x5310 00A4

0x0000 05F7

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ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

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表6-1. Pin Attributes (ZCZ Package) (continued)

BALL NAME [2]/

IOMUX

ADDRESS [16]/

DEFAULT VALUE [17]

BALL

MUX

MODE

AFTER

BALL

NUMBER

[1]

STATE

DURING

RESET

STATE

AFTER

RESET

VOLTAGE

[10]

PULL

TYPE

[13]

MUX

MODE [4]

HYS

[12] TYPE [14]

BUFFER

SIGNAL NAME [3]

TYPE [5]

POWER [11]

RESET [9]

RX/TX/PULL [7]

RX/TX/PULL [8]

MMC0_CD

UART0_CTSn

I2C2_SDA

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

MMC0_CD_CFG_REG

0x5310 0150

0x0000 05F7

IOD

EPWM20_B

GPMC0_AD15

GPIO84

SDFM1_D3

MMC0_CLK

UART0_RXD

LIN0_RXD

MMC0_CLK

VDDSHV0

MMC0_CLK_CFG_REG

0x5310 0134

0x0000 05F7

EPWM17_A

GPMC0_AD8

GPIO77

SDFM1_CLK0

MMC0_CMD

UART0_TXD

LIN0_TXD

MMC0_CMD

MMC0_CMD_CFG_REG

0x5310 0138

0x0000 05F7

EPWM17_B

GPMC0_AD9

GPIO78

SDFM1_D0

MMC0_WP

UART0_RTSn

I2C2_SCL

MMC0_WP

MMC0_WP_CFG_REG

0x5310 014C

0x0000 05F7

IOD

EPWM20_A

GPMC0_AD14

GPIO83

SDFM1_CLK3

MMC0_D0

MMC0_D0_CFG_REG

0x5310 013C

0x0000 05F7

UART2_RXD

I2C1_SCL

IOD

EPWM18_A

GPMC0_AD10

GPIO79

SDFM1_CLK1

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ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

表6-1. Pin Attributes (ZCZ Package) (continued)

BALL NAME [2]/

IOMUX

ADDRESS [16]/

DEFAULT VALUE [17]

BALL

MUX

MODE

AFTER

BALL

NUMBER

[1]

STATE

DURING

RESET

STATE

AFTER

RESET

VOLTAGE

[10]

PULL

TYPE

[13]

MUX

MODE [4]

HYS

[12] TYPE [14]

BUFFER

SIGNAL NAME [3]

TYPE [5]

POWER [11]

RESET [9]

RX/TX/PULL [7]

RX/TX/PULL [8]

MMC0_D1

MMC0_D1_CFG_REG

0x5310 0140

0x0000 05F7

MMC0_D1

EPWM18_B

GPMC0_AD11

GPIO80

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

SDFM1_D1

MMC0_D2

UART2_TXD

I2C1_SDA

EPWM19_A

GPMC0_AD12

GPIO81

MMC0_D2

IOD

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

LVCMOS

PU/PD

MMC0_D2_CFG_REG

0x5310 0144

0x0000 05F7

SDFM1_CLK2

MMC0_D3

UART3_RTSn

EPWM19_B

GPMC0_AD13

GPIO82

MMC0_D3

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

MMC0_D3_CFG_REG

0x5310 0148

0x0000 05F7

SDFM1_D2

PORz

3.3 V

VDDSHV0

Yes

RESET

L18

PR0_MDIO0_MDC

EPWM21_B

GPMC0_CSn3

GPIO86

Off / Off / Off

Off / On / Down

LVCMOS

PU/PD

PR0_MDIO0_MDC_CFG_REG

0x5310 0158

0x0000 05F7

L17

K17

PR0_MDIO0_MDIO

EPWM21_A

GPMC0_CSn2

GPIO85

3.3 V

VDDSHV0

Yes

LVCMOS

PR0_MDIO0_MDIO_CFG_REG

0x5310 0154

0x0000 05F7

PR0_PRU0_GPIO0

RMII2_RXD0

RGMII2_RD0

MII2_RXD0

PR0_PRU0_GPIO0_CFG_REG

0x5310 0174

0x0000 05F7

EPWM25_A

GPMC0_A1

GPIO93

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ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

www.ti.com.cn

表6-1. Pin Attributes (ZCZ Package) (continued)

BALL NAME [2]/

IOMUX

ADDRESS [16]/

DEFAULT VALUE [17]

BALL

MUX

MODE

AFTER

BALL

NUMBER

[1]

STATE

DURING

RESET

STATE

AFTER

RESET

VOLTAGE

[10]

PULL

TYPE

[13]

MUX

MODE [4]

HYS

[12] TYPE [14]

BUFFER

SIGNAL NAME [3]

TYPE [5]

POWER [11]

RESET [9]

RX/TX/PULL [7]

RX/TX/PULL [8]

K18

PR0_PRU0_GPIO1

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

PR0_PRU0_GPIO1_CFG_REG

0x5310 0178

0x0000 05F7

RMII2_RXD1

RGMII2_RD1

MII2_RXD1

EPWM25_B

GPMC0_A2

GPIO94

J18

J17

K16

G17

PR0_PRU0_GPIO2

RGMII2_RD2

MII2_RXD2

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

PR0_PRU0_GPIO2_CFG_REG

0x5310 017C

0x0000 05F7

EPWM26_A

GPMC0_A3

GPIO95

PR0_PRU0_GPIO3

RGMII2_RD3

MII2_RXD3

PR0_PRU0_GPIO3_CFG_REG

0x5310 0180

0x0000 05F7

EPWM26_B

GPMC0_A4

GPIO96

PR0_PRU0_GPIO4

RGMII2_RX_CTL

MII2_RXDV

EPWM24_B

GPMC0_A0

GPIO92

PR0_PRU0_GPIO4_CFG_REG

0x5310 0170

0x0000 05F7

PR0_PRU0_GPIO5

RMII2_RX_ER

MII2_RX_ER

EPWM22_A

GPMC0_DIR

GPIO87

PR0_PRU0_GPIO5_CFG_REG

0x5310 015C

0x0000 05F7

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ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

表6-1. Pin Attributes (ZCZ Package) (continued)

BALL NAME [2]/

IOMUX

ADDRESS [16]/

DEFAULT VALUE [17]

BALL

MUX

MODE

AFTER

BALL

NUMBER

[1]

STATE

DURING

RESET

STATE

AFTER

RESET

VOLTAGE

[10]

PULL

TYPE

[13]

MUX

MODE [4]

HYS

[12] TYPE [14]

BUFFER

SIGNAL NAME [3]

TYPE [5]

POWER [11]

RESET [9]

RX/TX/PULL [7]

RX/TX/PULL [8]

K15

PR0_PRU0_GPIO6

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

PR0_PRU0_GPIO6_CFG_REG

0x5310 016C

0x0000 05F7

RMII2_REF_CLK

RGMII2_RXC

MII2_RXCLK

EPWM24_A

GPMC0_CSn1

GPIO91

G15

F17

PR0_PRU0_GPIO8

EPWM23_B

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

PR0_PRU0_GPIO8_CFG_REG

0x5310 0168

0x0000 05F7

GPMC0_WPn

GPIO90

PR0_PRU0_GPIO9

PR0_UART0_CTSn

MII2_COL

PR0_PRU0_GPIO9_CFG_REG

0x5310 0160

0x0000 05F7

EPWM22_B

GPMC0_CLK

GPIO88

G18

PR0_PRU0_GPIO10

RMII2_CRS_DV

PR0_UART0_RTSn

MII2_CRS

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

PR0_PRU0_GPIO10_CFG_REG

0x5310 0164

0x0000 05F7

EPWM23_A

GPMC0_WAIT0

GPIO89

M16

PR0_PRU0_GPIO11

RMII2_TXD0

RGMII2_TD0

MII2_TXD0

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

PR0_PRU0_GPIO11_CFG_REG

0x5310 018C

0x0000 05F7

EPWM28_A

GPMC0_A7

GPIO99

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ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

www.ti.com.cn

表6-1. Pin Attributes (ZCZ Package) (continued)

BALL NAME [2]/

IOMUX

ADDRESS [16]/

DEFAULT VALUE [17]

BALL

MUX

MODE

AFTER

BALL

NUMBER

[1]

STATE

DURING

RESET

STATE

AFTER

RESET

VOLTAGE

[10]

PULL

TYPE

[13]

MUX

MODE [4]

HYS

[12] TYPE [14]

BUFFER

SIGNAL NAME [3]

TYPE [5]

POWER [11]

RESET [9]

RX/TX/PULL [7]

RX/TX/PULL [8]

M15

PR0_PRU0_GPIO12

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

PR0_PRU0_GPIO12_CFG_REG

0x5310 0190

0x0000 05F7

RMII2_TXD1

RGMII2_TD1

MII2_TXD1

EPWM28_B

GPMC0_A8

GPIO100

H17

H16

L16

PR0_PRU0_GPIO13

RGMII2_TD2

MII2_TXD2

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

PR0_PRU0_GPIO13_CFG_REG

0x5310 0194

0x0000 05F7

EPWM29_A

GPMC0_A9

GPIO101

PR0_PRU0_GPIO14

RGMII2_TD3

MII2_TXD3

PR0_PRU0_GPIO14_CFG_REG

0x5310 0198

0x0000 05F7

EPWM29_B

GPMC0_A10

GPIO102

PR0_PRU0_GPIO15

RMII2_TX_EN

RGMII2_TX_CTL

MII2_TX_EN

EPWM27_B

GPMC0_A6

PR0_PRU0_GPIO15_CFG_REG

0x5310 0188

0x0000 05F7

GPIO98

H18

PR0_PRU0_GPIO16

RGMII2_TXC

MII2_TXCLK

EPWM27_A

GPMC0_A5

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

PR0_PRU0_GPIO16_CFG_REG

0x5310 0184

0x0000 05F7

GPIO97

F18

PR0_PRU1_GPIO0

FSITX2_DATA1

TRC_DATA6

GPMC0_A13

GPIO109

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

PR0_PRU1_GPIO0_CFG_REG

0x5310 01B4

0x0000 05F7

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www.ti.com.cn

ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

表6-1. Pin Attributes (ZCZ Package) (continued)

BALL NAME [2]/

IOMUX

ADDRESS [16]/

DEFAULT VALUE [17]

BALL

MUX

MODE

AFTER

BALL

NUMBER

[1]

STATE

DURING

RESET

STATE

AFTER

RESET

VOLTAGE

[10]

PULL

TYPE

[13]

MUX

MODE [4]

HYS

[12] TYPE [14]

BUFFER

SIGNAL NAME [3]

TYPE [5]

POWER [11]

RESET [9]

RX/TX/PULL [7]

RX/TX/PULL [8]

G16

E17

E18

F16

F15

E16

D18

PR0_PRU1_GPIO1

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

PR0_PRU1_GPIO1_CFG_REG

0x5310 01B8

0x0000 05F7

FSIRX2_CLK

TRC_DATA7

GPMC0_A14

GPIO110

PR0_PRU1_GPIO2

FSIRX2_DATA0

TRC_DATA8

GPMC0_A15

GPIO111

VDDSHV0

PR0_PRU1_GPIO2_CFG_REG

0x5310 01BC

0x0000 05F7

PR0_PRU1_GPIO3

FSIRX2_DATA1

TRC_DATA9

GPMC0_A16

GPIO112

PR0_PRU1_GPIO3_CFG_REG

0x5310 01C0

0x0000 05F7

PR0_PRU1_GPIO4

FSITX2_DATA0

TRC_DATA5

GPMC0_A12

GPIO108

PR0_PRU1_GPIO4_CFG_REG

0x5310 01B0

0x0000 05F7

PR0_PRU1_GPIO5

TRC_DATA0

EPWM30_A

PR0_PRU1_GPIO5_CFG_REG

0x5310 019C

0x0000 05F7

GPMC0_OEn_REn

GPIO103

PR0_PRU1_GPIO6

FSITX2_CLK

TRC_DATA4

GPMC0_A11

GPIO107

PR0_PRU1_GPIO6_CFG_REG

0x5310 01AC

0x0000 05F7

PR0_PRU1_GPIO8

TRC_DATA3

EPWM31_B

PR0_PRU1_GPIO8_CFG_REG

0x5310 01A8

0x0000 05F7

GPMC0_WEn

GPIO106

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ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

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表6-1. Pin Attributes (ZCZ Package) (continued)

BALL NAME [2]/

IOMUX

ADDRESS [16]/

DEFAULT VALUE [17]

BALL

MUX

MODE

AFTER

BALL

NUMBER

[1]

STATE

DURING

RESET

STATE

AFTER

RESET

VOLTAGE

[10]

PULL

TYPE

[13]

MUX

MODE [4]

HYS

[12] TYPE [14]

BUFFER

SIGNAL NAME [3]

TYPE [5]

POWER [11]

RESET [9]

RX/TX/PULL [7]

RX/TX/PULL [8]

C18

PR0_PRU1_GPIO9

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

PR0_PRU1_GPIO9_CFG_REG

0x5310 01A0

0x0000 05F7

PR0_UART0_RXD

TRC_DATA1

EPWM30_B

GPMC0_BE0n_CLE

GPIO104

D17

PR0_PRU1_GPIO10

PR0_UART0_TXD

TRC_DATA2

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

PR0_PRU1_GPIO10_CFG_REG

0x5310 01A4

0x0000 05F7

EPWM31_A

GPMC0_BE1n

GPIO105

B18

B17

D16

PR0_PRU1_GPIO11

FSITX3_DATA1

TRC_DATA12

GPMC0_A19

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

PR0_PRU1_GPIO11_CFG_REG

0x5310 01CC

0x0000 05F7

GPIO115

PR0_PRU1_GPIO12

FSIRX3_CLK

TRC_DATA13

GPMC0_A20

PR0_PRU1_GPIO12_CFG_REG

0x5310 01D0

0x0000 05F7

GPIO116

PR0_PRU1_GPIO13

FSIRX3_DATA0

TRC_DATA14

XBAROUT11

PR0_PRU1_GPIO13_CFG_REG

0x5310 01D4

0x0000 05F7

GPMC0_A21

GPIO117

C17

PR0_PRU1_GPIO14

FSIRX3_DATA1

TRC_DATA15

XBAROUT12

GPMC0_CSn0

GPIO118

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

PR0_PRU1_GPIO14_CFG_REG

0x5310 01D8

0x0000 05F7

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ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

表6-1. Pin Attributes (ZCZ Package) (continued)

BALL NAME [2]/

IOMUX

ADDRESS [16]/

DEFAULT VALUE [17]

BALL

MUX

MODE

AFTER

BALL

NUMBER

[1]

STATE

DURING

RESET

STATE

AFTER

RESET

VOLTAGE

[10]

PULL

TYPE

[13]

MUX

MODE [4]

HYS

[12] TYPE [14]

BUFFER

SIGNAL NAME [3]

TYPE [5]

POWER [11]

RESET [9]

RX/TX/PULL [7]

RX/TX/PULL [8]

A17

C16

C15

PR0_PRU1_GPIO15

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

PR0_PRU1_GPIO15_CFG_REG

0x5310 01C8

0x0000 05F7

FSITX3_DATA0

TRC_DATA11

GPMC0_A18

GPIO114

PR0_PRU1_GPIO16

FSITX3_CLK

VDDSHV0

PR0_PRU1_GPIO16_CFG_REG

0x5310 01C4

0x0000 05F7

TRC_DATA10

GPMC0_A17

GPIO113

PR0_PRU1_GPIO18

UART3_TXD

PR0_PRU1_GPIO18_CFG_REG

0x5310 01E0

0x0000 05F7

PR0_IEP0_EDIO_DATA_IN_OUT31

TRC_CTL

XBAROUT14

GPMC0_WAIT1

GPIO120

EQEP1_B

D15

PR0_PRU1_GPIO19

UART3_RXD

PR0_IEP0_EDC_SYNC_OUT0

TRC_CLK

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

PR0_PRU1_GPIO19_CFG_REG

0x5310 01DC

0x0000 05F7

XBAROUT13

GPIO119

EQEP1_A

QSPI0_CLK

Off / Off / Off

Off / On / Down

On / On / Down

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

QSPI0_CLK_CFG_REG

0x5310 0008

0x0000 05F7

GPIO2

QSPI0_CLKLB

QSPI0_CLKLB_CFG_REG

0x5310 0244

0x5F0

QSPI0_CSn0

GPIO0

QSPI0_CSn0_CFG_REG

0x5310 0000

0x0000 05F7

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ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

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表6-1. Pin Attributes (ZCZ Package) (continued)

BALL NAME [2]/

IOMUX

ADDRESS [16]/

DEFAULT VALUE [17]

BALL

MUX

MODE

AFTER

BALL

NUMBER

[1]

STATE

DURING

RESET

STATE

AFTER

RESET

VOLTAGE

[10]

PULL

TYPE

[13]

MUX

MODE [4]

HYS

[12] TYPE [14]

BUFFER

SIGNAL NAME [3]

TYPE [5]

POWER [11]

RESET [9]

RX/TX/PULL [7]

RX/TX/PULL [8]

QSPI0_CSn1

XBAROUT0

GPIO1

Off / Off / Off

On / Off / Off

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

QSPI0_CSn1_CFG_REG

0x5310 0004

0x0000 05F7

QSPI0_D0

GPIO3

On / Off / Off

VDDSHV0

QSPI0_D0_CFG_REG

0x5310 000C

0x0000 05D7

SOP0

Bootstrap

QSPI0_D1

GPIO4

On / Off / Off

QSPI0_D1_CFG_REG

0x5310 0010

0x0000 05D7

SOP1

Bootstrap

QSPI0_D2

GPIO5

Off / On / Down

QSPI0_D2_CFG_REG

0x5310 0014

0x0000 05F7

QSPI0_D3

GPIO6

QSPI0_D3_CFG_REG

0x5310 0018

0x0000 05F7

R17

RGMII1_RXC

RGMII1_RXC_CFG_REG

0x5310 0074

0x0000 05F7

RMII1_REF_CLK

MII1_RXCLK

FSITX0_CLK

GPIO29

EQEP2_A

R18

RGMII1_RX_CTL

RMII1_RX_ER

MII1_RXDV

FSITX0_DATA0

GPIO30

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

RGMII1_RX_CTL_CFG_REG

0x5310 0078

0x0000 05F7

EQEP2_B

N18

RGMII1_TXC

MII1_TXCLK

FSITX1_CLK

GPIO35

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

RGMII1_TXC_CFG_REG

0x5310 008C

0x0000 05F7

EQEP0_I

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ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

表6-1. Pin Attributes (ZCZ Package) (continued)

BALL NAME [2]/

IOMUX

ADDRESS [16]/

DEFAULT VALUE [17]

BALL

MUX

MODE

AFTER

BALL

NUMBER

[1]

STATE

DURING

RESET

STATE

AFTER

RESET

VOLTAGE

[10]

PULL

TYPE

[13]

MUX

MODE [4]

HYS

[12] TYPE [14]

BUFFER

SIGNAL NAME [3]

TYPE [5]

POWER [11]

RESET [9]

RX/TX/PULL [7]

RX/TX/PULL [8]

M18

U17

T17

RGMII1_TX_CTL

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

RGMII1_TX_CTL_CFG_REG

0x5310 0090

0x0000 05F7

RMII1_TX_EN

MII1_TX_EN

FSITX1_DATA0

GPIO36

EQEP0_S

RGMII1_RD0

RMII1_RXD0

MII1_RXD0

FSITX0_DATA1

GPIO31

VDDSHV0

RGMII1_RD0_CFG_REG

0x5310 007C

0x0000 05F7

EQEP2_S

RGMII1_RD1

RMII1_RXD1

MII1_RXD1

FSIRX0_CLK

GPIO32

VDDSHV0

RGMII1_RD1_CFG_REG

0x5310 0080

0x0000 05F7

EQEP2_I

U18

T18

P16

RGMII1_RD2

MII1_RXD2

FSIRX0_DATA0

GPIO33

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

RGMII1_RD2_CFG_REG

0x5310 0084

0x0000 05F7

EQEP0_A

RGMII1_RD3

MII1_RXD3

FSIRX0_DATA1

GPIO34

RGMII1_RD3_CFG_REG

0x5310 0088

0x0000 05F7

EQEP0_B

RGMII1_TD0

RMII1_TXD0

MII1_TXD0

FSITX1_DATA1

GPIO37

RGMII1_TD0_CFG_REG

0x5310 0094

0x0000 05F7

EQEP1_A

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ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

www.ti.com.cn

表6-1. Pin Attributes (ZCZ Package) (continued)

BALL NAME [2]/

IOMUX

ADDRESS [16]/

DEFAULT VALUE [17]

BALL

MUX

MODE

AFTER

BALL

NUMBER

[1]

STATE

DURING

RESET

STATE

AFTER

RESET

VOLTAGE

[10]

PULL

TYPE

[13]

MUX

MODE [4]

HYS

[12] TYPE [14]

BUFFER

SIGNAL NAME [3]

TYPE [5]

POWER [11]

RESET [9]

RX/TX/PULL [7]

RX/TX/PULL [8]

P17

P18

N17

RGMII1_TD1

RMII1_TXD1

MII1_TXD1

FSIRX1_CLK

GPIO38

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

RGMII1_TD1_CFG_REG

0x5310 0098

0x0000 05F7

EQEP1_B

RGMII1_TD2

VDDSHV0

RGMII1_TD2_CFG_REG

0x5310 009C

0x0000 05F7

RMII1_CRS_DV

MII1_TXD2

FSIRX1_DATA0

GPIO39

EQEP1_S

RGMII1_TD3

MII1_TXD3

FSIRX1_DATA1

GPIO40

VDDSHV0

RGMII1_TD3_CFG_REG

0x5310 00A0

0x0000 05F7

EQEP1_I

J16

RSVD_J16

RSVD_T4

RSVD_J16

RSVD_T4

RSVD

Reserved

VDDSHV0

Reserved

LVCMOS

RSVD_U1

RSVD_U3

RSVD_V2

SAFETY_ERRORn

On / Off / Down

Off / Off / Off

On / NA / Down

Off / On / Down

3.3 V

Yes

PU/PD

SAFETY_ERRORn_CFG_REG

0x5310 0230

0x410

B16

A16

SDFM0_CLK0

CLKOUT1

VDDSHV0

LVCMOS

SDFM0_CLK0_CFG_REG

0x5310 01E8

0x0000 05F7

GPIO122

SDFM0_CLK0

EQEP1_S

SDFM0_CLK1

PR0_PRU1_GPIO7

CPTS0_TS_SYNC

UART5_RTSn

PR0_IEP0_EDC_SYNC_OUT1

I2C3_SDA

Off / Off / Off

Off / On / Down

3.3 V

Yes

PU/PD

SDFM0_CLK1_CFG_REG

0x5310 01F0

0x0000 05F7

IOD

GPIO124

SDFM0_CLK1

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ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

表6-1. Pin Attributes (ZCZ Package) (continued)

BALL NAME [2]/

IOMUX

ADDRESS [16]/

DEFAULT VALUE [17]

BALL

MUX

MODE

AFTER

BALL

NUMBER

[1]

STATE

DURING

RESET

STATE

AFTER

RESET

VOLTAGE

[10]

PULL

TYPE

[13]

MUX

MODE [4]

HYS

[12] TYPE [14]

BUFFER

SIGNAL NAME [3]

TYPE [5]

POWER [11]

RESET [9]

RX/TX/PULL [7]

RX/TX/PULL [8]

B15

SDFM0_CLK2

UART5_TXD

I2C3_SCL

IOD

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

SDFM0_CLK2_CFG_REG

0x5310 01F8

0x0000 05F7

GPMC0_ADVn_ALE

GPIO126

SDFM0_CLK2

MCAN3_TX

A15

SDFM0_CLK3

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

LVCMOS

PU/PD

SDFM0_CLK3_CFG_REG

0x5310 0200

0x0000 05F7

UART5_RXD

GPIO128

SDFM0_CLK3

PR0_ECAP0_APWM_OUT

GPIO123

D14

D13

SDFM0_D0

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

SDFM0_D0_CFG_REG

0x5310 01EC

0x0000 05F7

SDFM0_D0

SDFM0_D1

PR0_PRU1_GPIO17

UART5_CTSn

SDFM0_D1_CFG_REG

0x5310 01F4

0x0000 05F7

PR0_IEP0_EDIO_DATA_IN_OUT30

GPIO125

SDFM0_D1

C13

C14

A11

SDFM0_D2

UART5_RXD

Off / Off / Off

On / Off / Off

Off / On / Down

On / Off / Off

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

SDFM0_D2_CFG_REG

0x5310 01FC

0x0000 05F7

GPIO127

SDFM0_D2

SDFM0_D3

MCAN3_RX

GPIO129

SDFM0_D3_CFG_REG

0x5310 0204

0x0000 05F7

SDFM0_D3

SPI0_CLK

UART3_TXD

LIN3_TXD

FSITX0_CLK

GPIO12

SPI0_CLK_CFG_REG

0x5310 0030

0x0000 05D7

SOP2

Bootstrap

A10

SPI1_CLK

UART4_RXD

LIN4_RXD

XBAROUT2

FSIRX0_CLK

GPIO16

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

SPI1_CLK_CFG_REG

0x5310 0040

0x0000 05F7

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ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

www.ti.com.cn

表6-1. Pin Attributes (ZCZ Package) (continued)

BALL NAME [2]/

IOMUX

ADDRESS [16]/

DEFAULT VALUE [17]

BALL

MUX

MODE

AFTER

BALL

NUMBER

[1]

STATE

DURING

RESET

STATE

AFTER

RESET

VOLTAGE

[10]

PULL

TYPE

[13]

MUX

MODE [4]

HYS

[12] TYPE [14]

BUFFER

SIGNAL NAME [3]

TYPE [5]

POWER [11]

RESET [9]

RX/TX/PULL [7]

RX/TX/PULL [8]

C11

SPI0_CS0

UART3_RXD

LIN3_RXD

GPIO11

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

SPI0_CS0_CFG_REG

0x5310 002C

0x0000 05F7

C10

SPI0_D0

On / Off / Off

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

SPI0_D0_CFG_REG

0x5310 0034

0x0000 05D7

FSITX0_DATA0

GPIO13

SOP3

Bootstrap

B11

SPI0_D1

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

SPI0_D1_CFG_REG

0x5310 0038

0x0000 05F7

FSITX0_DATA1

GPIO14

SPI1_CS0

UART4_TXD

LIN4_TXD

XBAROUT1

GPIO15

SPI1_CS0_CFG_REG

0x5310 003C

0x0000 05F7

B10

SPI1_D0

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

SPI1_D0_CFG_REG

0x5310 0044

0x0000 05F7

UART5_TXD

XBAROUT3

FSIRX0_DATA0

GPIO17

SPI1_D1

Off / Off / Off

Off / On / Down

3.3 V

SPI1_D1_CFG_REG

0x5310 0048

0x0000 05F7

UART5_RXD

XBAROUT4

FSIRX0_DATA1

GPIO18

TCK

On / NA / Up

On / Off / Up

Off / Off / Up

On / NA / Up

On / Off / Up

Off / NA / Up

3.3 V

VDDSHV0

Yes

HIGH

HYST

TCK_CFG_REG

0x5310 0240

0x210

TDI

LVCMOS

PU/PD

TDI_CFG_REG

0x5310 0234

0x6D0

TDO

TDO_CFG_REG

0x5310 0238

0x630

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ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

表6-1. Pin Attributes (ZCZ Package) (continued)

BALL NAME [2]/

IOMUX

ADDRESS [16]/

DEFAULT VALUE [17]

BALL

MUX

MODE

AFTER

BALL

NUMBER

[1]

STATE

DURING

RESET

STATE

AFTER

RESET

VOLTAGE

[10]

PULL

TYPE

[13]

MUX

MODE [4]

HYS

[12] TYPE [14]

BUFFER

SIGNAL NAME [3]

TYPE [5]

POWER [11]

RESET [9]

RX/TX/PULL [7]

RX/TX/PULL [8]

TMS

On / Off / Up

On / NA / Up

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

TMS_CFG_REG

0x5310 023C

0x610

UART0_CTSn

I2C2_SDA

SPI3_D1

IOD

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

PU/PD

UART0_CTSn_CFG_REG

0x5310 0068

0x0000 05F7

MCAN3_RX

SPI0_CS1

XBAROUT10

GPIO26

UART0_RTSn

I2C2_SCL

SPI3_D0

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

UART0_RTSn_CFG_REG

0x5310 0064

0x0000 05F7

IOD

MCAN3_TX

XBAROUT9

GPIO25

UART0_RXD

LIN0_RXD

GPIO27

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

UART0_RXD_CFG_REG

0x5310 006C

0x0000 05F7

UART0_TXD

LIN0_TXD

GPIO28

UART0_TXD_CFG_REG

0x5310 0070

0x0000 05F7

UART1_RXD

LIN1_RXD

EPWM16_A

GPMC0_AD6

GPIO75

UART1_RXD_CFG_REG

0x5310 012C

0x0000 05F7

UART1_TXD

LIN1_TXD

Off / Off / Off

Off / On / Down

3.3 V

VDDSHV0

Yes

LVCMOS

PU/PD

UART1_TXD_CFG_REG

0x5310 0130

0x0000 05F7

EPWM16_B

GPMC0_AD7

GPIO76

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AM2634, AM2634-Q1, AM2632, AM2632-Q1, AM2631, AM2631-Q1

ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

www.ti.com.cn

表6-1. Pin Attributes (ZCZ Package) (continued)

BALL NAME [2]/

IOMUX

ADDRESS [16]/

DEFAULT VALUE [17]

BALL

MUX

MODE

AFTER

BALL

NUMBER

[1]

STATE

DURING

RESET

STATE

AFTER

RESET

VOLTAGE

[10]

PULL

TYPE

[13]

MUX

MODE [4]

HYS

[12] TYPE [14]

BUFFER

SIGNAL NAME [3]

TYPE [5]

POWER [11]

RESET [9]

RX/TX/PULL [7]

RX/TX/PULL [8]

E11, E9, VDD

F11, F9,

VDD

PWR

1.2V

G13, G14,

G5, G6,

K13, K14,

K5, K6,

N13, N14,

N5, N6,

R11, R8 VDDA18

VDDA18

PWR

1.8V

3.3V

VDDA18_LDO

VDDA18_OSC_PLL

VDDA18_LDO

VDDA18_OSC_PLL

VDDA33

P11, P7, VDDA33

J15

D10

VDDAR1

VDDAR2

VDDAR3

VDDAR1

VDDAR2

VDDAR3

VDDS18

PWR

1.2V

1.8V

D6, E15, VDDS18

L4, N15

VDDS18_LDO

VDDS33

PWR

1.8V

3.3V

D12, D8, VDDS33

H15, H4,

L15, P4,

R15

VPP

PWR

VPP

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表6-1. Pin Attributes (ZCZ Package) (continued)

BALL NAME [2]/

IOMUX

ADDRESS [16]/

DEFAULT VALUE [17]

BALL

MUX

MODE

AFTER

BALL

NUMBER

[1]

STATE

DURING

RESET

STATE

AFTER

RESET

VOLTAGE

[10]

PULL

TYPE

[13]

MUX

MODE [4]

HYS

[12] TYPE [14]

BUFFER

SIGNAL NAME [3]

TYPE [5]

POWER [11]

RESET [9]

RX/TX/PULL [7]

RX/TX/PULL [8]

A1, A18, VSS

E10, E12,

E13, E14,

E5, E6,

VSS

GND

VSS

E7, E8,

F10, F12,

F13, F14,

F5, F6, F7,

F8, G10,

G11, G12,

G7, G8,

G9, H10,

H11, H12,

H13, H14,

H5, H6,

H7, H8,

H9, J10,

J11, J12,

J13, J14,

J5, J6, J7,

J8, J9,

K10, K11,

K12, K7,

K8, K9,

L10, L11,

L12, L13,

L14, L5,

L6, L7, L8,

L9, M10,

M11, M12,

M13, M14,

M5, M6,

M7, M8,

M9, N10,

N11, N12,

N7, N8,

N9, P13,

P14, P5,

T2, V18

P10, P12, VSSA

P6, P8,

VSSA

AGND

VSSA

R13, R5,

V1, V16

VSYS_MON

WARMRSTn

VSYS_MON

WARMRSTn

PWR

0.9 V

3.3 V

VDDA_CIO

VDDSHV0

AnalogCIO

FS OD

On / Off / Off

On / NA / Off

WARMRSTn_CFG_REG

0x5310 022C

0x510

XTAL_XI

1.8 V

VDDS_OSC

Yes

HFOSC

XTAL_XO

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6.3 Signal Descriptions

Many signals are available on multiple pins, according to the software configuration of the pin multiplexing

options.

The following list describes the column headers:

1. SIGNAL NAME: The name of the signal passing through the pin.

备注

Signal names and descriptions provided in each Signal Descriptions table, represent the pin

multiplexed signal function which is implemented at the pin and selected via IOMUX pad

configuration registers. Some device subsystems provide secondary multiplexing of signal

functions, which are not described in these tables. For more information on secondary multiplexed

signal functions, see the respective peripheral chapter of the device TRM.

2. PIN TYPE: Signal direction and type:

• I = Input

• O = Output

• IO = Input, Output, or simultaneously Input and Output

• ID = Input with open-drain output function

• OD = Output, with open-drain output function

• IOD = Input, Output, or simultaneously Input and Output, with open-drain output function

• IOZ = Input, Output, or simultaneously Input and Output, with three-state output function

• OZ = Output with three-state output function

• A = Analog

• CAP = LDO capacitor

• PWR = Power

• GND = Ground

3. DESCRIPTION: Description of the signal

4. BALL: Associated ball number

For more information on the I/O cell configurations, see the Pad Configuration Registers section within the

Device Configuration chapter of the device TRM.

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6.3.1 ADC

表6-2. ADC0 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

ADC Analog Input 0 (+IN0)

CMPSSA0: inH (+IN)

ADC0_AIN0

ADC0_AIN1

ADC0_AIN2

ADC0_AIN3

ADC0_AIN4

ADC0_AIN5

V15

ADC Analog Input 1 (-IN0)

CMPSSA0: inL (-IN)

U15

T14

U14

U13

R14

ADC Analog Input 2 (+IN1)

CMPSSA1: inH (+IN)

ADC Analog Input 3 (-IN1)

CMPSSA1: inL (-IN)

ADC Analog Input 4 (+IN2)

CMPSSB0: inH/inL (+IN/-IN)

ADC Analog Input 5 (-IN2)

CMPSSB1: inH/inL (+IN/-IN)

表6-3. ADC1 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

ADC Analog Input 0 (+IN0)

CMPSSA2: inH (+IN)

ADC1_AIN0

ADC1_AIN1

ADC1_AIN2

ADC1_AIN3

ADC1_AIN4

ADC1_AIN5

T11

ADC Analog Input 1 (-IN0)

CMPSSA2: inL (-IN)

U11

T12

V12

U12

R12

ADC Analog Input 2 (+IN1)

CMPSSA3: inH (+IN)

ADC Analog Input 3 (-IN1)

CMPSSA3: inL (-IN)

ADC Analog Input 4 (+IN2)

CMPSSB2: inH/inL (+IN/-IN)

ADC Analog Input 5 (-IN2)

CMPSSB3: inH/inL (+IN/-IN)

表6-4. ADC2 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

ADC Analog Input 0 (+IN0)

CMPSSA4: inH (+IN)

ADC2_AIN0

ADC2_AIN1

ADC2_AIN2

ADC2_AIN3

ADC2_AIN4

ADC2_AIN5

R10

ADC Analog Input 1 (-IN0)

CMPSSA4: inL (-IN)

T10

U10

ADC Analog Input 2 (+IN1)

CMPSSA5: inH (+IN)

ADC Analog Input 3 (-IN1)

CMPSSA5: inL (-IN)

ADC Analog Input 4 (+IN2)

CMPSSB4: inH/inL (+IN/-IN)

ADC Analog Input 5 (-IN2)

CMPSSB5: inH/inL (+IN/-IN)

表6-5. ADC3 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

ADC Analog Input 0 (+IN0)

CMPSSA6: inH (+IN)

ADC3_AIN0

ADC3_AIN1

ADC Analog Input 1 (-IN0)

CMPSSA6: inL (-IN)

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表6-5. ADC3 Signal Descriptions (continued)

SIGNAL NAME [1]

ADC3_AIN2

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

ADC Analog Input 2 (+IN1)

CMPSSA7: inH (+IN)

ADC Analog Input 3 (-IN1)

CMPSSA7: inL (-IN)

ADC3_AIN3

ADC3_AIN4

ADC3_AIN5

ADC Analog Input 4 (+IN2)

CMPSSB6: inH/inL (+IN/-IN)

ADC Analog Input 5 (-IN2)

CMPSSB7: inH/inL (+IN/-IN)

表6-6. ADC4 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

ADC Analog Input 0 (+IN0)

CMPSSA8: inH (+IN)

ADC4_AIN0

ADC4_AIN1

ADC4_AIN2

ADC4_AIN3

ADC4_AIN4

ADC4_AIN5

ADC Analog Input 1 (-IN0)

CMPSSA8: inL (-IN)

ADC Analog Input 2 (+IN1)

CMPSSA9: inH (+IN)

ADC Analog Input 3 (-IN1)

CMPSSA9: inL (-IN)

ADC Analog Input 4 (+IN2)

CMPSSB8: inH/inL (+IN/-IN)

ADC Analog Input 5 (-IN2)

CMPSSB9: inH/inL (+IN/-IN)

6.3.1.1 ADC-CMPSS Signal Connections

This table describes the connectivity between the ADC input signals and the associated CMPSS signals.

Signal/Pin Name

ADC Input

CMPSS Input

ADC0 Channels

ADC0_AIN0

ADC0_AIN1

ADC0_AIN2

ADC0_AIN3

ADC0_AIN4

ADC0_AIN5

ADC_CAL1

ADC_CAL0

ADC0:inp0 (+IN0)

ADC0:inm0 (-IN0)

ADC0:inp1 (+IN1)

ADC0:inm1 (-IN1)

ADC0:inp2 (+IN2)

ADC0:inm2 (-IN2)

ADC0:inm3 (-IN3)

ADC0:inp3 (+IN3)

CMPSSA0:inH (+IN)

CMPSSA0:inL (-IN)

CMPSSA1:inH (+IN)

CMPSSA1:inL (-IN)

CMPSSB0:inH/inL (+IN/-IN)

CMPSSB1:inH/inL (+IN/-IN)

ADC1 Channels

ADC1_AIN0

ADC1_AIN1

ADC1_AIN2

ADC1_AIN3

ADC1_AIN4

ADC1_AIN5

ADC_CAL1

ADC_CAL0

ADC1:inp0 (+IN0)

ADC1:inm0 (-IN0)

ADC1:inp1 (+IN1)

ADC1:inm1 (-IN1)

ADC1:inp2 (+IN2)

ADC1:inm2 (-IN2)

ADC1:inm3 (-IN3)

ADC1:inp3 (+IN3)

CMPSSA2:inH (+IN)

CMPSSA2:inL (-IN)

CMPSSA3:inH (+IN)

CMPSSA3:inL (-IN)

CMPSSB2:inH/inL (+IN/-IN)

CMPSSB3:inH/inL (+IN/-IN)

ADC2 Channels

ADC2_AIN0

ADC2_AIN1

ADC2_AIN2

ADC2:inp0 (+IN0)

ADC2:inm0 (-IN0)

ADC2:inp1 (+IN1)

CMPSSA4:inH (+IN)

CMPSSA4:inL (-IN)

CMPSSA5:inH (+IN)

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This table describes the connectivity between the ADC input signals and the associated CMPSS signals.

Signal/Pin Name

ADC2_AIN3

ADC2_AIN4

ADC2_AIN5

ADC_CAL1

ADC Input

CMPSS Input

ADC2:inm1 (-IN1)

ADC2:inp2 (+IN2)

ADC2:inm2 (-IN2)

ADC2:inm3 (-IN3)

ADC2:inp3 (+IN3)

CMPSSA5:inL (-IN)

CMPSSB4:inH/inL (+IN/-IN)

CMPSSB5:inH/inL (+IN/-IN)

ADC_CAL0

ADC3 Channels

ADC3_AIN0

ADC3_AIN1

ADC3_AIN2

ADC3_AIN3

ADC3_AIN4

ADC3_AIN5

ADC_CAL1

ADC_CAL0

ADC3:inp0 (+IN0)

ADC3:inm0 (-IN0)

ADC3:inp1 (+IN1)

ADC3:inm1 (-IN1)

ADC3:inp2 (+IN2)

ADC3:inm2 (-IN2)

ADC3:inm3 (-IN3)

ADC3:inp3 (+IN3)

CMPSSA6:inH (+IN)

CMPSSA6:inL (-IN)

CMPSSA7:inH (+IN)

CMPSSA7:inL (-IN)

CMPSSB6:inH/inL (+IN/-IN)

CMPSSB7:inH/inL (+IN/-IN)

ADC4 Channels

ADC4_AIN0

ADC4_AIN1

ADC4_AIN2

ADC4_AIN3

ADC4_AIN4

ADC4_AIN5

ADC_CAL0

ADC_CAL1

ADC4:inp0 (+IN0)

ADC4:inm0 (-IN0)

ADC4:inp1 (+IN1)

ADC4:inm1 (-IN1)

ADC4:inp2 (+IN2)

ADC4:inm2 (-IN2)

ADC4:inp3 (+IN3)

ADC4:inm3 (-IN3)

CMPSSA8:inH (+IN)

CMPSSA8:inL (-IN)

CMPSSA9:inH (+IN)

CMPSSA9:inL (-IN)

CMPSSB8:inH/inL (+IN/-IN)

CMPSSB9:inH/inL (+IN/-IN)

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6.3.2 ADC_CAL

表6-7. ADC_CAL Signal Descriptions

SIGNAL NAME [1]

ADC_CAL0 ⁽¹⁾

ADC_CAL1 ⁽¹⁾

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

U16

ADC Calibration Pin 0

ADC Calibration Pin 1

T15

(1) This pin is shared between ADC[0:4].

6.3.3 ADC VREF

表6-8. ADC_VREF Signal Descriptions

SIGNAL NAME [1] (⁽⁵⁾

)

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

V14

ADC_VREFHI_G0

ADC Reference (Positive)

ADC_VREFHI_G1 ⁽²⁾

ADC_VREFHI_G2

ADC Reference (Positive)

ADC Reference (Negative)

V10

ADC_VREFLO_G0 ⁽¹⁾

ADC_VREFLO_G1 ⁽³⁾

ADC_VREFLO_G2 ⁽⁴⁾

V13

V11

(1) This pin should be connected (shorted) to analog ground (VSSA).

(2) This pin can be connected (shorted) to ADC_VREFHI_G0.

(3) This pin can be connected (shorted) to ADC_VREFLO_G0.

(4) This pin can be connected (shorted) to analog ground (VSSA).

(5) See the Layout Guidelines section and Hardware Design Guideline for additional details on connecting these pins.

6.3.4 CPSW

表6-9. CPSW3G0 RGMII1 Signal Descriptions

SIGNAL NAME [1]

RGMII1_RXC

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

R17

RGMII Receive Clock

RGMII1_RX_CTL

RGMII1_TXC

RGMII1_TX_CTL

RGMII1_RD0

RGMII1_RD1

RGMII1_RD2

RGMII1_RD3

RGMII1_TD0

RGMII1_TD1

RGMII1_TD2

RGMII1_TD3

RGMII Receive Control

RGMII Transmit Clock

RGMII Transmit Control

RGMII Receive Data 0

RGMII Receive Data 1

RGMII Receive Data 2

RGMII Receive Data 3

RGMII Transmit Data 0

RGMII Transmit Data 1

RGMII Transmit Data 2

RGMII Transmit Data 3

R18

N18

M18

U17

T17

U18

T18

P16

P17

P18

N17

表6-10. CPSW3G0 RGMII2 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

K15

RGMII2_RXC

RGMII2_RX_CTL

RGMII2_TXC

RGMII2_TX_CTL

RGMII2_RD0

RGMII2_RD1

RGMII2_RD2

RGMII2_RD3

RGMII Receive Clock

RGMII Receive Control

RGMII Transmit Clock

RGMII Transmit Control

RGMII Receive Data 0

RGMII Receive Data 1

RGMII Receive Data 2

RGMII Receive Data 3

K16

H18

L16

K17

K18

J18

J17

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表6-10. CPSW3G0 RGMII2 Signal Descriptions (continued)

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

M16

RGMII2_TD0

RGMII2_TD1

RGMII2_TD2

RGMII2_TD3

RGMII Transmit Data 0

RGMII Transmit Data 1

RGMII Transmit Data 2

RGMII Transmit Data 3

M15

H17

H16

表6-11. CPSW3G0 RMII1 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

P18

RMII1_CRS_DV

RMII1_REF_CLK

RMII1_RX_ER

RMII1_TX_EN

RMII1_RXD0

RMII1_RXD1

RMII1_TXD0

RMII Carrier Sense / Data Valid

RMII Reference Clock

RMII Receive Data Error

RMII Transmit Enable

RMII Receive Data 0

RMII Receive Data 1

RMII Transmit Data 0

RMII Transmit Data 1

R17

R18

M18

U17

T17

P16

RMII1_TXD1

P17

表6-12. CPSW3G0 RMII2 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

G18

RMII2_CRS_DV

RMII2_REF_CLK

RMII2_RX_ER

RMII2_TX_EN

RMII2_RXD0

RMII2_RXD1

RMII2_TXD0

RMII Carrier Sense / Data Valid

RMII Reference Clock

RMII Receive Data Error

RMII Transmit Enable

RMII Receive Data 0

RMII Receive Data 1

RMII Transmit Data 0

RMII Transmit Data 1

K15

G17

L16

K17

K18

M16

RMII2_TXD1

M15

表6-13. CPSW3G0 MII1 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

P15

MII1_COL

MII Collision Detected

MII Carrier Sense

MII Receive Clock

MII1_CRS

R16

MII1_RXCLK

MII1_RXDV

MII1_RX_ER

MII1_TXCLK

MII1_TX_EN

MII1_RXD0

MII1_RXD1

MII1_RXD2

MII1_RXD3

MII1_TXD0

MII1_TXD1

MII1_TXD2

MII1_TXD3

R17

MII Receive Data Valid

MII Receive Data Error

MII Transmit Clock

MII Transmit Enable

MII Receive Data 0

MII Receive Data 1

MII Receive Data 2

MII Receive Data 3

MII Transmit Data 0

MII Transmit Data 1

MII Transmit Data 2

MII Transmit Data 3

R18

T16

N18

M18

U17

T17

U18

T18

P16

P17

P18

N17

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表6-14. CPSW3G0 MII2 Signal Descriptions

SIGNAL NAME [1]

MII2_COL

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

F17

MII Collision Detected

MII Carrier Sense

MII Receive Clock

MII2_CRS

G18

K15

MII2_RXCLK

MII2_RXDV

MII2_RX_ER

MII2_TXCLK

MII2_TX_EN

MII2_RXD0

MII2_RXD1

MII2_RXD2

MII2_RXD3

MII2_TXD0

MII2_TXD1

MII2_TXD2

MII2_TXD3

MII Receive Data Valid

MII Receive Error

K16

G17

H18

MII Transmit Clock

MII Transmit Enable

MII Receive Data 0

MII Receive Data 1

MII Receive Data 2

MII Receive Data 3

MII Transmit Data 0

MII Transmit Data 1

MII Transmit Data 2

MII Transmit Data 3

L16

K17

K18

J18

J17

M16

M15

H17

H16

表6-15. MDIO0 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

M17

MDIO0_MDC

MDIO0_MDIO

MDIO Clock

MDIO Data

N16

6.3.5 CPTS

表6-16. CPTS0 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

CPTS0_TS_SYNC

CPTS Time Stamp Counter Bit Output

A16

6.3.6 DAC

表6-17. DAC Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

DAC_OUT

DAC Output

T13

DAC_VREF0 ^{(1) (2)}

DAC_VREF1 ^{(1) (2)}

DAC Voltage Reference 0

DAC Voltage Reference 1

(1) See the Layout Guidelines sections for details on connecting these pins.

(2) This pin can be connected (shorted) to VDDA18_LDO.

6.3.7 Emulation and Debug

表6-18. Trace Signal Descriptions

SIGNAL NAME [1]

TRC_CLK

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

D15

Trace Clock

Trace Control

Trace Data 0

Trace Data 1

Trace Data 2

Trace Data 3

Trace Data 4

TRC_CTL

C15

TRC_DATA0

TRC_DATA1

TRC_DATA2

TRC_DATA3

TRC_DATA4

F15

C18

D17

D18

E16

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表6-18. Trace Signal Descriptions (continued)

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

F16

TRC_DATA5

TRC_DATA6

TRC_DATA7

TRC_DATA8

TRC_DATA9

TRC_DATA10

TRC_DATA11

TRC_DATA12

TRC_DATA13

TRC_DATA14

TRC_DATA15

Trace Data 5

Trace Data 6

Trace Data 7

Trace Data 8

Trace Data 9

Trace Data 10

Trace Data 11

Trace Data 12

Trace Data 13

Trace Data 14

Trace Data 15

F18

G16

E17

E18

C16

A17

B18

B17

D16

C17

表6-19. JTAG Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

TCK

TDI

JTAG Test Clock Input

JTAG Test Data Input

TDO

TMS

JTAG Test Data Output

JTAG Test Mode Select Input

6.3.8 EPWM

表6-20. EPWM0 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

EPWM0_A

EPWM0_B

EPWM Output A

EPWM Output B

表6-21. EPWM1 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

EPWM1_A

EPWM1_B

EPWM Output A

EPWM Output B

表6-22. EPWM2 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

EPWM2_A

EPWM2_B

EPWM Output A

EPWM Output B

表6-23. EPWM3 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

EPWM3_A

EPWM3_B

EPWM Output A

EPWM Output B

表6-24. EPWM4 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

EPWM4_A

EPWM4_B

EPWM Output A

EPWM Output B

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表6-25. EPWM5 Signal Descriptions

SIGNAL NAME [1]

EPWM5_A

EPWM5_B

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

EPWM Output A

EPWM Output B

表6-26. EPWM6 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

EPWM6_A

EPWM6_B

EPWM Output A

EPWM Output B

表6-27. EPWM7 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

EPWM7_A

EPWM7_B

EPWM Output A

EPWM Output B

表6-28. EPWM8 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

EPWM8_A

EPWM8_B

EPWM Output A

EPWM Output B

表6-29. EPWM9 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

EPWM9_A

EPWM9_B

EPWM Output A

EPWM Output B

表6-30. EPWM10 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

EPWM10_A

EPWM10_B

EPWM Output A

EPWM Output B

表6-31. EPWM11 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

EPWM11_A

EPWM11_B

EPWM Output A

EPWM Output B

表6-32. EPWM12 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

EPWM12_A

EPWM12_B

EPWM Output A

EPWM Output B

表6-33. EPWM13 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

EPWM13_A

EPWM13_B

EPWM Output A

EPWM Output B

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表6-34. EPWM14 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

V17

EPWM14_A

EPWM14_B

EPWM Output A

EPWM Output B

T16

表6-35. EPWM15 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

P15

EPWM15_A

EPWM15_B

EPWM Output A

EPWM Output B

R16

表6-36. EPWM16 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

EPWM16_A

EPWM16_B

EPWM Output A

EPWM Output B

表6-37. EPWM17 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

EPWM17_A

EPWM17_B

EPWM Output A

EPWM Output B

表6-38. EPWM18 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

EPWM18_A

EPWM18_B

EPWM Output A

EPWM Output B

表6-39. EPWM19 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

EPWM19_A

EPWM19_B

EPWM Output A

EPWM Output B

表6-40. EPWM20 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

EPWM20_A

EPWM20_B

EPWM Output A

EPWM Output B

表6-41. EPWM21 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

L17

EPWM21_A

EPWM21_B

EPWM Output A

EPWM Output B

L18

表6-42. EPWM22 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

G17

EPWM22_A

EPWM22_B

EPWM Output A

EPWM Output B

F17

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表6-43. EPWM23 Signal Descriptions

SIGNAL NAME [1]

EPWM23_A

EPWM23_B

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

G18

EPWM Output A

EPWM Output B

G15

表6-44. EPWM24 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

K15

EPWM24_A

EPWM24_B

EPWM Output A

EPWM Output B

K16

表6-45. EPWM25 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

K17

EPWM25_A

EPWM25_B

EPWM Output A

EPWM Output B

K18

表6-46. EPWM26 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

J18

EPWM26_A

EPWM26_B

EPWM Output A

EPWM Output B

J17

表6-47. EPWM27 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

H18

EPWM27_A

EPWM27_B

EPWM Output A

EPWM Output B

L16

表6-48. EPWM28 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

M16

EPWM28_A

EPWM28_B

EPWM Output A

EPWM Output B

M15

表6-49. EPWM29 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

H17

EPWM29_A

EPWM29_B

EPWM Output A

EPWM Output B

H16

表6-50. EPWM30 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

F15

EPWM30_A

EPWM30_B

EPWM Output A

EPWM Output B

C18

表6-51. EPWM31 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

D17

EPWM31_A

EPWM31_B

EPWM Output A

EPWM Output B

D18

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6.3.9 EQEP

表6-52. EQEP0 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

B14, U18

A14, T18

D11, N18

C12, M18

EQEP0_A

EQEP0_B

EQEP0_I

EQEP0_S

EQEP Quadrature Input A

EQEP Quadrature Input B

EQEP Index

EQEP Strobe

表6-53. EQEP1 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

D15, P16

C15, P17

N17, P2

EQEP1_A

EQEP1_B

EQEP1_I

EQEP1_S

EQEP Quadrature Input A

EQEP Quadrature Input B

EQEP Index

EQEP Strobe

B16, P18

表6-54. EQEP2 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

B13, R17

A13, R18

A12, T17

B12, U17

EQEP2_A ⁽¹⁾

EQEP2_B ⁽²⁾

EQEP2_I

EQEP Quadrature Input A

EQEP Quadrature Input B

EQEP Index

EQEP2_S

EQEP Strobe

(1) EQEP2_A is implemented with the I2C OD FS (Open Drain Fail Safe) voltage buffer.

(2) EQEP2_B is implemented with the I2C OD FS (Open Drain Fail Safe) voltage buffer.

6.3.10 FSI

表6-55. FSIRX0 Signal Descriptions

SIGNAL NAME [1]

FSIRX0_CLK

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

A10, T17

B10, U18

D9, T18

FSI Clock

FSI Data 0

FSI Data 1

FSIRX0_DATA0

FSIRX0_DATA1

表6-56. FSIRX1 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

E1, P17

FSIRX1_CLK

FSI Clock

FSI Data 0

FSI Data 1

FSIRX1_DATA0

FSIRX1_DATA1

F3, P18

F4, N17

表6-57. FSIRX2 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

G16, J2

FSIRX2_CLK

FSI Clock

FSI Data 0

FSI Data 1

FSIRX2_DATA0

FSIRX2_DATA1

E17, G4

E18, J3

表6-58. FSIRX3 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

B17

FSIRX3_CLK

FSI Clock

FSIRX3_DATA0

FSI Data 0

D16

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表6-58. FSIRX3 Signal Descriptions (continued)

SIGNAL NAME [1]

FSIRX3_DATA1

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

FSI Data 1

C17

表6-59. FSITX0 Signal Descriptions

SIGNAL NAME [1]

FSITX0_CLK

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

A11, R17

C10, R18

B11, U17

FSI Clock

FSI Data 0

FSI Data 1

FSITX0_DATA0

FSITX0_DATA1

表6-60. FSITX1 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

E4, N18

FSITX1_CLK

FSI Clock

FSI Data 0

FSI Data 1

FSITX1_DATA0

FSITX1_DATA1

F2, M18

G2, P16

表6-61. FSITX2 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

E16, G3

FSITX2_CLK

FSI Clock

FSI Data 0

FSI Data 1

FSITX2_DATA0

FSITX2_DATA1

F16, H2

F18, G1

表6-62. FSITX3 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

C16

FSITX3_CLK

FSI Clock

FSI Data 0

FSI Data 1

FSITX3_DATA0

FSITX3_DATA1

A17

B18

6.3.11 GPIO

表6-63. GPIO Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

General Purpose Input/Output

C11

A11

C10

B11

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表6-63. GPIO Signal Descriptions (continued)

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

A10

B10

GPIO16

General Purpose Input/Output

GPIO17

General Purpose Input/Output

GPIO18

GPIO19

GPIO100

GPIO101

GPIO102

GPIO103

GPIO104

GPIO105

GPIO106

GPIO107

GPIO108

GPIO109

GPIO110

GPIO111

GPIO112

GPIO113

GPIO114

GPIO115

GPIO116

GPIO117

GPIO118

GPIO119

GPIO120

GPIO121

GPIO122

GPIO123

GPIO124

GPIO125

GPIO126

GPIO127

GPIO128

GPIO129

GPIO130

GPIO131

GPIO132

GPIO133

GPIO134 ⁽¹⁾

GPIO135 ⁽²⁾

GPIO136

GPIO137

GPIO138

GPIO20

M15

H17

H16

F15

C18

D17

D18

E16

F16

F18

G16

E17

E18

C16

A17

B18

B17

D16

C17

D15

C15

B16

D14

A16

D13

B15

C13

A15

C14

B14

A14

C12

D11

B13

A13

B12

A12

IOD

GPIO21

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表6-63. GPIO Signal Descriptions (continued)

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

GPIO22

GPIO23

GPIO24

GPIO25

GPIO26

GPIO27

GPIO28

GPIO29

GPIO30

GPIO31

GPIO32

GPIO33

GPIO34

GPIO35

GPIO36

GPIO37

GPIO38

GPIO39

GPIO40

GPIO41

GPIO42

GPIO43

GPIO44

GPIO45

GPIO46

GPIO47

GPIO48

GPIO49

GPIO50

GPIO51

GPIO52

GPIO53

GPIO54

GPIO55

GPIO56

GPIO57

GPIO58

GPIO59

GPIO60

GPIO61

GPIO62

GPIO63

GPIO64

GPIO65

GPIO66

General Purpose Input/Output

R17

R18

U17

T17

U18

T18

N18

M18

P16

P17

P18

N17

N16

M17

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表6-63. GPIO Signal Descriptions (continued)

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

GPIO67

GPIO68

GPIO69

GPIO70

GPIO71

GPIO72

GPIO73

GPIO74

GPIO75

GPIO76

GPIO77

GPIO78

GPIO79

GPIO80

GPIO81

GPIO82

GPIO83

GPIO84

GPIO85

GPIO86

GPIO87

GPIO88

GPIO89

GPIO90

GPIO91

GPIO92

GPIO93

GPIO94

GPIO95

GPIO96

GPIO97

GPIO98

GPIO99

General Purpose Input/Output

V17

T16

P15

R16

L17

L18

G17

F17

G18

G15

K15

K16

K17

K18

J18

J17

H18

L16

M16

(1) GPIO134 is implemented with the I2C OD FS (Open Drain Fail Safe) voltage buffer.

(2) GPIO135 is implemented with the I2C OD FS (Open Drain Fail Safe) voltage buffer.

6.3.12 GPMC

表6-64. GPMC0 Signal Descriptions

SIGNAL NAME [1]

GPMC0_ADVn_ALE

PIN TYPE [2]

DESCRIPTION [3]

GPMC Address Valid (active low) or Address Latch Enable

GPMC Clock

ZCZ PIN [4]

B15

GPMC0_CLK ⁽²⁾

GPMC0_CLKLB ⁽¹⁾

GPMC0_DIR

F17

GPMC Clock Loopback

GPMC Data Bus Signal Direction Control

G17

GPMC Output Enable (active low) or Read Enable (active

low)

GPMC0_OEn_REn

GPMC0_WEn

F15, J1

D18, K2

GPMC Write Enable (active low)

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表6-64. GPMC0 Signal Descriptions (continued)

SIGNAL NAME [1]

GPMC0_WPn

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

GPMC Flash Write Protect (active low)

G15

GPMC Address 0 Output. Only used to effectively address 8-

bit data non-multiplexed memories

GPMC0_A0

GPMC0_A1

GPMC0_A2

GPMC0_A3

GPMC0_A4

GPMC0_A5

GPMC0_A6

GPMC0_A7

GPMC0_A8

GPMC0_A9

GPMC0_A10

GPMC0_A11

GPMC0_A12

GPMC0_A13

GPMC0_A14

GPMC0_A15

GPMC0_A16

GPMC0_A17

GPMC0_A18

GPMC0_A19

GPMC0_A20

GPMC0_A21

GPMC0_AD0

GPMC0_AD1

GPMC0_AD2

GPMC0_AD3

K16

K17

K18

J18

J17

H18

L16

M16

M15

H17

H16

E16

F16

F18

G16

E17

E18

C16

A17

B18

B17

D16

GPMC Address 1 Output in A/D non-multiplexed mode and

Address 17 in A/D multiplexed mode

GPMC Address 2 Output in A/D non-multiplexed mode and

Address 18 in A/D multiplexed mode

GPMC Address 3 Output in A/D non-multiplexed mode and

Address 19 in A/D multiplexed mode

GPMC Address 4 Output in A/D non-multiplexed mode and

Address 20 in A/D multiplexed mode

GPMC Address 5 Output in A/D non-multiplexed mode and

Address 21 in A/D multiplexed mode

GPMC Address 6 Output in A/D non-multiplexed mode and

Address 22 in A/D multiplexed mode

GPMC Address 7 Output in A/D non-multiplexed mode and

Address 23 in A/D multiplexed mode

GPMC Address 8 Output in A/D non-multiplexed mode and

Address 24 in A/D multiplexed mode

GPMC Address 9 Output in A/D non-multiplexed mode and

Address 25 in A/D multiplexed mode

GPMC Address 10 Output in A/D non-multiplexed mode and

Address 26 in A/D multiplexed mode

GPMC Address 11 Output in A/D non-multiplexed mode and

unused in A/D multiplexed mode

GPMC Address 12 Output in A/D non-multiplexed mode and

unused in A/D multiplexed mode

GPMC Address 13 Output in A/D non-multiplexed mode and

unused in A/D multiplexed mode

GPMC Address 14 Output in A/D non-multiplexed mode and

unused in A/D multiplexed mode

GPMC Address 15 Output in A/D non-multiplexed mode and

unused in A/D multiplexed mode

GPMC Address 16 Output in A/D non-multiplexed mode and

unused in A/D multiplexed mode

GPMC Address 17 Output in A/D non-multiplexed mode and

unused in A/D multiplexed mode

GPMC Address 18 Output in A/D non-multiplexed mode and

unused in A/D multiplexed mode

GPMC Address 19 Output in A/D non-multiplexed mode and

unused in A/D multiplexed mode

GPMC Address 20 Output in A/D non-multiplexed mode and

unused in A/D multiplexed mode

GPMC Address 21 Output in A/D non-multiplexed mode and

unused in A/D multiplexed mode

GPMC Data 0 Input/Output in A/D non-multiplexed mode and

additionally Address 1 Output in A/D multiplexed mode

GPMC Data 1 Input/Output in A/D non-multiplexed mode and

additionally Address 2 Output in A/D multiplexed mode

GPMC Data 2 Input/Output in A/D non-multiplexed mode and

additionally Address 3 Output in A/D multiplexed mode

V17

T16

GPMC Data 3 Input/Output in A/D non-multiplexed mode and

additionally Address 4 Output in A/D multiplexed mode

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表6-64. GPMC0 Signal Descriptions (continued)

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

GPMC Data 4 Input/Output in A/D non-multiplexed mode and

additionally Address 5 Output in A/D multiplexed mode

GPMC0_AD4

GPMC0_AD5

GPMC0_AD6

GPMC0_AD7

GPMC0_AD8

GPMC0_AD9

GPMC0_AD10

GPMC0_AD11

GPMC0_AD12

GPMC0_AD13

GPMC0_AD14

GPMC0_AD15

GPMC0_BE0n_CLE

P15

GPMC Data 5 Input/Output in A/D non-multiplexed mode and

additionally Address 6 Output in A/D multiplexed mode

R16

GPMC Data 6 Input/Output in A/D non-multiplexed mode and

additionally Address 7 Output in A/D multiplexed mode

GPMC Data 7 Input/Output in A/D non-multiplexed mode and

additionally Address 8 Output in A/D multiplexed mode

C18

GPMC Data 8 Input/Output in A/D non-multiplexed mode and

additionally Address 9 Output in A/D multiplexed mode

GPMC Data 9 Input/Output in A/D non-multiplexed mode and

additionally Address 10 Output in A/D multiplexed mode

GPMC Data 10 Input/Output in A/D non-multiplexed mode

and additionally Address 11 Output in A/D multiplexed mode

GPMC Data 11 Input/Output in A/D non-multiplexed mode

and additionally Address 12 Output in A/D multiplexed mode

GPMC Data 12 Input/Output in A/D non-multiplexed mode

and additionally Address 13 Output in A/D multiplexed mode

GPMC Data 13 Input/Output in A/D non-multiplexed mode

and additionally Address 14 Output in A/D multiplexed mode

GPMC Data 14 Input/Output in A/D non-multiplexed mode

and additionally Address 15 Output in A/D multiplexed mode

GPMC Data 15 Input/Output in A/D non-multiplexed mode

and additionally Address 16 Output in A/D multiplexed mode

GPMC Lower-Byte Enable (active low) or Command Latch

Enable

GPMC0_BE1n

GPMC0_CSn0

GPMC0_CSn1

GPMC0_CSn2

GPMC0_CSn3

GPMC0_WAIT0

GPMC0_WAIT1

GPMC Upper-Byte Enable (active low)

GPMC Chip Select 0 (active low)

GPMC Chip Select 1 (active low)

GPMC Chip Select 2 (active low)

GPMC Chip Select 3 (active low)

GPMC External Indication of Wait

D17

C17, J4

K15

L17

L18

G18

C15

(1) GPMC0_CLKLB is a clock loopback signal used internally for retiming purposes.

(2) The RXACTIVE bit of the MSS_IOMUX:PR0_PRU0_GPO9_CFG_REG register must be set to 0x1 and the TX_DIS bit of the

MSS_IOMUX:PR0_PRU0_GPO9_CFG_REG register must be reset to 0x0 when GPMC0 is operating in synchronous mode.

6.3.13 I2C

表6-65. I2C0 Signal Descriptions

SIGNAL NAME [1]

I2C0_SCL ⁽²⁾

I2C0_SDA ⁽¹⁾

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

A13

IOD

I2C Clock

I2C Data

IOD

B13

(1) I2C0_SDA is implemented with the I2C OD FS (Open Drain Fail Safe) voltage buffer.

(2) I2C0_SCL is implemented with the I2C OD FS (Open Drain Fail Safe) voltage buffer.

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备注

I2C signals that are implemented on an LVCMOS voltage buffer pin can be configured to operate as

open-drain outputs by configuring the I2C module to source a constant low output and toggle the

output enable. The output buffer drives low when enabled and is high impedance when disabled.

The (I2C OD FS) are the only IO voltage buffers which are fail-safe. These are implemented for I2C0

pins only. Other IOs do not allow any potential greater than (VDD + 0.3V) to be applied. This means

you can not source any potential to these pins when power is off. All attached devices that can source

a potential to these IOs must be powered from the same power supply that is sourcing the respective

IO power rail.

表6-66. I2C1 Signal Descriptions

SIGNAL NAME [1]

I2C1_SCL ⁽¹⁾

I2C1_SDA ⁽²⁾

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

B5, D7

IOD

I2C Clock

I2C Data

IOD

A3, C8

(1) I2C1_SCL is implemented with the typical LVCMOS voltage buffer and should be properly configured to operate as an Input/Output

Open Drain signal type.

(2) I2C1_SDA is implemented with the typical LVCMOS voltage buffer and should be properly configured to operate as an Input/Output

Open Drain signal type.

表6-67. I2C2 Signal Descriptions

SIGNAL NAME [1]

I2C2_SCL ⁽¹⁾

I2C2_SDA ⁽²⁾

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

C6, C7

IOD

I2C Clock

I2C Data

IOD

A5, B7

(1) I2C2_SCL is implemented with the typical LVCMOS voltage buffer and should be properly configured to operate as an Input/Output

Open Drain signal type.

(2) I2C2_SDA is implemented with the typical LVCMOS voltage buffer and should be properly configured to operate as an Input/Output

Open Drain signal type.

表6-68. I2C3 Signal Descriptions

SIGNAL NAME [1]

I2C3_SCL ⁽²⁾

I2C3_SDA ⁽¹⁾

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

B15, H2

IOD

I2C Clock

I2C Data

IOD

A16, G3

(1) I2C3_SDA is implemented with the typical LVCMOS voltage buffer and should be properly configured to operate as an Input/Output

Open Drain signal type.

(2) I2C3_SCL is implemented with the typical LVCMOS voltage buffer and should be properly configured to operate as an Input/Output

Open Drain signal type.

6.3.14 LIN

表6-69. LIN0 Signal Descriptions

SIGNAL NAME [1]

LIN0_RXD

LIN0_TXD

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

A7, B6

LIN Receive Data

LIN Transmit Data

A4, A6

表6-70. LIN1 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

A9, L3

LIN1_RXD

LIN1_TXD

LIN Receive Data

LIN Transmit Data

B9, M3

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表6-71. LIN2 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

LIN2_RXD

LIN2_TXD

LIN Receive Data

LIN Transmit Data

表6-72. LIN3 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

C11

LIN3_RXD

LIN3_TXD

LIN Receive Data

LIN Transmit Data

A11

表6-73. LIN4 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

A10, D11

C12, C9

LIN4_RXD

LIN4_TXD

LIN Receive Data

LIN Transmit Data

6.3.15 MCAN

表6-74. MCAN0 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

MCAN0_RX

MCAN0_TX

MCAN Receive Data

MCAN Transmit Data

表6-75. MCAN1 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

MCAN1_RX

MCAN1_TX

MCAN Receive Data

MCAN Transmit Data

表6-76. MCAN2 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

A12

MCAN2_RX

MCAN2_TX

MCAN Receive Data

MCAN Transmit Data

B12

表6-77. MCAN3 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

B7, C14

MCAN3_RX

MCAN3_TX

MCAN Receive Data

MCAN Transmit Data

A15, C7

6.3.16 SPI (MCSPI)

表6-78. SPI0 Signal Descriptions

SIGNAL NAME [1]

SPI0_CLK ⁽¹⁾

SPI0_CS0

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

A11

SPI Clock (SOP2)

SPI Chip Select 0

SPI Chip Select 1

SPI Data 0 (SOP3)

SPI Data 1

C11

SPI0_CS1

SPI0_D0 ⁽²⁾

C10

SPI0_D1

B11

(1) The SPI0_CLK pin is also used as SOP2 bootmode configuration pin.

(2) The SPI0_D0 pin is also used as SOP3 bootmode configuration pin.

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表6-79. SPI1 Signal Descriptions

SIGNAL NAME [1]

SPI1_CLK

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

SPI Clock

A10

SPI1_CS0

SPI1_D0

SPI1_D1

SPI Chip Select 0

SPI Data 0

B10

SPI Data 1

表6-80. SPI2 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

SPI2_CLK

SPI2_CS0

SPI2_D0

SPI2_D1

SPI Clock

SPI Chip Select 0

SPI Data 0

SPI Data 1

表6-81. SPI3 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

SPI3_CLK

SPI3_CS0

SPI3_D0

SPI3_D1

SPI Clock

SPI Chip Select 0

SPI Data 0

SPI Data 1

表6-82. SPI4 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

B14, L1

A14, M1

SPI4_CLK

SPI4_CS0

SPI4_CS1

SPI4_D0

SPI4_D1

SPI Clock

SPI Chip Select 0

SPI Chip Select 1

SPI Data 0

C12, L2

D11, K1

SPI Data 1

6.3.17 MMC

表6-83. MMC0 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

MMC0_CD

MMC0_CLK

MMC0_CMD

MMC0_WP

MMC0_D0

MMC0_D1

MMC0_D2

MMC0_D3

MMC/SD Card Detect

MMC/SD Clock

MMC/SD Command

MMC/SD Write Protect

MMC/SD Data

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6.3.18 Power Supply

表6-84. Power Supply Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

E11, E9, F11, F9,

G13, G14, G5, G6,

K13, K14, K5, K6,

N13, N14, N5, N6,

VDD

PWR

1.2V Core supply

VDDA18

PWR

1.8V Analog supply

R11, R8

VDDA18_LDO ^{(1) (2)}

VDDA18_OSC_PLL

VDDA33

1.8V Analog LDO Output

1.8V OSC PLL supply

3.3V Analog supply

P11, P7, P9

VDDAR1

1.2V SRAM Array supply

1.8V IO supply

J15

VDDAR2

D10

VDDAR3

D6, E15, L4, N15

VDDS18

VDDS18_LDO ^{(1) (3)}

1.8V Digital LDO Output

D12, D8, H15, H4,

L15, P4, R15

VDDS33

VPP

PWR

3.3V IO supply

eFuse ROM programming supply

A1, A18, E10,

E12, E13, E14,

E5, E6, E7, E8,

F10, F12, F13,

F14, F5, F6, F7,

F8, G10, G11,

G12, G7, G8, G9,

H10, H11, H12,

H13, H14, H5, H6,

H7, H8, H9, J10,

J11, J12, J13, J14,

J5, J6, J7, J8, J9,

K10, K11, K12, K7,

K8, K9, L10, L11,

L12, L13, L14, L5,

L6, L7, L8, L9,

VSS

GND

Ground

M10, M11, M12,

M13, M14, M5,

M6, M7, M8, M9,

N10, N11, N12,

N7, N8, N9, P13,

P14, P5, T2, V18

P10, P12, P6, P8,

R13, R5, V1, V16

VSSA

AGND

Analog Ground

(1) See the Layout Guidelines sections for details on connecting this pin.

(2) PCB should directly route VDDA18_LDO to all of the VDDA18 pins and the VDDA_OSC_PLL pin.

(3) PCB should directly route VDDS18_LDO to all of the VDDS18 pins.

6.3.19 PRU-ICSS

表6-85. PRU-ICSS ECAP Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

PRU-ICSS Enhanced Capture (ECAP) Input or ECAP

Auxiliary PWM (APWM) Output

PR0_ECAP0_APWM_OUT

D14

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表6-86. PRU-ICSS GPIO Signal Descriptions

PIN TYPE [2]

SIGNAL NAME [1] (⁽¹⁾

PR0_PRU0_GPIO0

)

DESCRIPTION [3]

PRU0 General Purpose Input/Output

PRU1 General Purpose Input/Output

ZCZ PIN [4]

K17

K18

J18

PR0_PRU0_GPIO1

PR0_PRU0_GPIO2

PR0_PRU0_GPIO3

PR0_PRU0_GPIO4

PR0_PRU0_GPIO5

PR0_PRU0_GPIO6

PR0_PRU0_GPIO8

PR0_PRU0_GPIO9

PR0_PRU0_GPIO10

PR0_PRU0_GPIO11

PR0_PRU0_GPIO12

PR0_PRU0_GPIO13

PR0_PRU0_GPIO14

PR0_PRU0_GPIO15

PR0_PRU0_GPIO16

PR0_PRU1_GPIO0

PR0_PRU1_GPIO1

PR0_PRU1_GPIO2

PR0_PRU1_GPIO3

PR0_PRU1_GPIO4

PR0_PRU1_GPIO5

PR0_PRU1_GPIO6

PR0_PRU1_GPIO7

PR0_PRU1_GPIO8

PR0_PRU1_GPIO9

PR0_PRU1_GPIO10

PR0_PRU1_GPIO11

PR0_PRU1_GPIO12

PR0_PRU1_GPIO13

PR0_PRU1_GPIO14

PR0_PRU1_GPIO15

PR0_PRU1_GPIO16

PR0_PRU1_GPIO17

PR0_PRU1_GPIO18

PR0_PRU1_GPIO19

J17

K16

G17

K15

G15

F17

G18

M16

M15

H17

H16

L16

H18

F18

G16

E17

E18

F16

F15

E16

A16

D18

C18

D17

B18

B17

D16

C17

A17

C16

D13

C15

D15

(1) PR0_PRU0_GPIO7, PR0_PRU0_GPIO17, PR0_PRU0_GPIO18, and PR0_PRU0_GPIO19, signals are not pinned out. The equivalent

PR0_PRU1_GPIO signals are pinned out and available.

表6-87. PRU-ICSS IEP Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

D15

PR0_IEP0_EDC_SYNC_OUT0

PR0_IEP0_EDC_SYNC_OUT1

PR0_IEP0_EDIO_DATA_IN_OUT30

PR0_IEP0_EDIO_DATA_IN_OUT31

PRU-ICSS Industrial Ethernet Distributed Clock Sync Output

PRU-ICSS Industrial Ethernet Digital I/O Data Input/Output

A16

D13

C15

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表6-88. PRU-ICSS MDIO Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

PRU-ICSS MDIO Clock

PRU-ICSS MDIO Data

ZCZ PIN [4]

L18

PR0_MDIO0_MDC

PR0_MDIO0_MDIO

L17

表6-89. PRU-ICSS UART Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

PRU-ICSS UART Clear to Send (Active Low)

PRU-ICSS UART Request to Send (Active Low)

PRU-ICSS UART Receive Data

ZCZ PIN [4]

F17

PR0_UART0_CTSn

PR0_UART0_RTSn

PR0_UART0_RXD

PR0_UART0_TXD

G18

C18

PRU-ICSS UART Transmit Data

D17

6.3.20 QSPI

表6-90. QSPI0 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

QSPI0_CLK

QSPI0_CLKLB ⁽³⁾

QSPI0_CSn0

QSPI0_CSn1

QSPI0_D0 ⁽¹⁾

QSPI0_D1 ⁽²⁾

QSPI0_D2

QSPI Clock

QSPI Clock Loopback

QSPI Chip Select 0

QSPI Chip Select 1

QSPI Data bit 0 (SOP0)

QSPI Data bit 1 (SOP1)

QSPI Data bit 2

QSPI0_D3

QSPI Data bit 3

(1) The QSPI0_D0 pin is also used as SOP0 boot mode configuration pin.

(2) The QSPI0_D1 pin is also used as SOP1 boot mode configuration pin.

(3) QSPI0_CLKLB is a clock loopback signal used internally for retiming purposes.

6.3.21 Reserved

表6-91. Reserved Signal Descriptions

SIGNAL NAME [1]

RSVD_J16

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

Reserved (RSVD_J16). This pin must be connected to 1.2 V

supply (VDD).

RSVD

J16

Reserved (RSVD_T4). This pin must be connected to ground

(VSS).

RSVD_T4

RSVD_U1

RSVD

Reserved (RSVD_U1). This pin must be connected to ground

(VSS).

RSVD_U3

RSVD_V2

RSVD

Reserved (RSVD_U3). This pin must be left unconnected.

Reserved (RSVD_V2). This pin must be left unconnected.

6.3.22 SDFM

表6-92. SDFM0 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

B16

SDFM0_CLK0

SDFM0_CLK1

SDFM0_CLK2

SDFM0_CLK3

SDFM0_D0

SDFM Clock 0 Input

SDFM Clock 1 Input

SDFM Clock 2 Input

SDFM Clock 3 Input

SDFM Data 0 Input

SDFM Data 1 Input

SDFM Data 2 Input

A16

B15

A15

D14

SDFM0_D1

D13

SDFM0_D2

C13

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表6-92. SDFM0 Signal Descriptions (continued)

SIGNAL NAME [1]

SDFM0_D3

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

SDFM Data 3 Input

C14

表6-93. SDFM1 Signal Descriptions

SIGNAL NAME [1]

SDFM1_CLK0

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

B14, B6

B5, C12

A3, B13

A13, C6

A14, A4

B4, D11

A2, B12

A12, A5

SDFM Clock 0 Input

SDFM Clock 1 Input

SDFM Clock 2 Input

SDFM Clock 3 Input

SDFM Data 0 Input

SDFM Data 1 Input

SDFM Data 2 Input

SDFM Data 3 Input

SDFM1_CLK1

SDFM1_CLK2 ⁽¹⁾

SDFM1_CLK3 ⁽²⁾

SDFM1_D0

SDFM1_D1

SDFM1_D2

SDFM1_D3

(1) SDFM1_CLK2 is implemented with the I2C OD FS (Open Drain Fail Safe) voltage buffer.

(2) SDFM1_CLK3 is implemented with the I2C OD FS (Open Drain Fail Safe) voltage buffer.

6.3.23 System and Miscellaneous

6.3.23.1 Boot Mode Configuration

表6-94. Boot Mode Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

Boot Mode configuration bit 0 (QSPI0_D0)

Boot Mode configuration bit 1 (QSPI0_D1)

Boot Mode configuration bit 2 (SPI0_CLK)

Boot Mode configuration bit 3 (SPI0_D0)

ZCZ PIN [4]

SOP0

SOP1

SOP2

SOP3

A11

C10

6.3.23.2 Clocking

表6-95. XTAL Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

XTAL_XI ⁽¹⁾

XTAL_XO ⁽¹⁾

External Crystal (XTAL) Input

External Crystal (XTAL) Output

(1) The XTAL interface requires a 25 MHz clock source.

表6-96. Output Clock Signal Descriptions

SIGNAL NAME [1]

CLKOUT0

CLKOUT1

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

Output Clock 0

Output Clock 1

B16

表6-97. External Reference Clock Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

EXT_REFCLK0

External Reference Clock Input

6.3.23.3 SYSTEM

表6-98. System Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

Device Power-On (PORz) cold reset

ESM Safety Error Signal

ZCZ PIN [4]

PORz

SAFETY_ERRORn

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表6-98. System Signal Descriptions (continued)

SIGNAL NAME [1]

WARMRSTn

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

Warm Reset Request (Input) / Warm Reset Status (Output)

备注

The SAFETY_ERRORn signal is implemented on an LVCMOS voltage buffer pin can be configured to

operate as open-drain outputs by configuring the ESM module to source a constant low output and

toggle the output enable. The output buffer drives low when enabled and is high impedance when

disabled.

The (I2C OD FS) are the only IO voltage buffers which are fail-safe. These are implemented for I2C0

pins only. Other IOs do not allow any potential greater than (VDD + 0.3V) to be applied. This means

you cannot source any potential to these pins when power is off. All attached devices that can source

a potential to these IOs must be powered from the same power supply that is sourcing the respective

IO power rail.

6.3.23.4 VMON

表6-99. VMON Signal Descriptions

SIGNAL NAME [1]

VSYS_MON ⁽¹⁾

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

PWR

External Voltage Monitor with 0.9 V (+/-3%) setpoint.

(1) See the Electrical Specifications - Safety Comparators section for additional details on this pin.

6.3.24 UART

表6-100. UART0 Signal Descriptions

SIGNAL NAME [1]

UART0_CTSn

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

A5, B7

UART Clear to Send (active low)

UART0_RTSn

UART0_RXD

UART0_TXD

UART Request to Send (active low)

UART Receive Data

C6, C7

A7, B6

UART Transmit Data

A4, A6

表6-101. UART1 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

UART1_CTSn

UART1_DCDn

UART1_DSRn

UART1_DTRn

UART1_RIn

UART Clear to Send (active low)

UART Data Carrier Detect (Active Low)

UART Data Set Ready (Active Low)

UART Data Terminal Ready (Active Low)

UART Ring Indicator

V17

UART1_RTSn

UART1_RXD

UART1_TXD

UART Request to Send (active low)

UART Receive Data

B12, J2

A9, L3

B9, M3

UART Transmit Data

表6-102. UART2 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

UART2_CTSn

UART2_RTSn

UART2_RXD

UART2_TXD

UART Clear to Send (active low)

UART Request to Send (active low)

UART Receive Data

A12, J3

B5, B8

A3, A8

UART Transmit Data

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表6-103. UART3 Signal Descriptions

SIGNAL NAME [1]

UART3_CTSn

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

UART Clear to Send (active low)

UART3_RTSn

UART3_RXD

UART3_TXD

UART Request to Send (active low)

UART Receive Data

A2, J1

C11, D15

A11, C15

UART Transmit Data

表6-104. UART4 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

A14

UART4_CTSn

UART4_RTSn

UART4_RXD

UART4_TXD

UART Clear to Send (active low)

UART Request to Send (active low)

UART Receive Data

B14

A10, D11, H2

C12, C9, G3

UART Transmit Data

表6-105. UART5 Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

D13

UART5_CTSn

UART5_RTSn

UART5_RXD

UART5_TXD

UART Clear to Send (active low)

UART Request to Send (active low)

UART Receive Data

A16

A15, C13, D9, R16

B10, B15, P15

UART Transmit Data

6.3.25 XBAR

表6-106. Output XBAR Signal Descriptions

SIGNAL NAME [1]

PIN TYPE [2]

DESCRIPTION [3]

ZCZ PIN [4]

XBAROUT0

XBAROUT1

XBAROUT2

XBAROUT3

XBAROUT4

XBAROUT5

XBAROUT6

XBAROUT7

XBAROUT8

XBAROUT9

XBAROUT10

XBAROUT11

XBAROUT12

XBAROUT13

XBAROUT14

XBAROUT15

OUTPUTXBAR Signal 0

OUTPUTXBAR Signal 1

OUTPUTXBAR Signal 2

OUTPUTXBAR Signal 3

OUTPUTXBAR Signal 4

OUTPUTXBAR Signal 5

OUTPUTXBAR Signal 6

OUTPUTXBAR Signal 7

OUTPUTXBAR Signal 8

OUTPUTXBAR Signal 9

OUTPUTXBAR Signal 10

OUTPUTXBAR Signal 11

OUTPUTXBAR Signal 12

OUTPUTXBAR Signal 13

OUTPUTXBAR Signal 14

OUTPUTXBAR Signal 15

A10

B10

D16

C17

D15

C15

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6.4 Pin Connectivity Requirements

This section describes connectivity requirements for package balls that have specific connectivity requirements

and package balls that may be unused.

备注

All power balls must be supplied with the voltages specified in the Recommended Operating

Conditions section, unless otherwise specified in Signal Descriptions.

For additional clarification, "leave unconnected" or "no connect" (NC) mean no signal traces should be

connected to these device ball numbers.

表6-107. Pin Connectivity Requirements

BALL NUMBER

BALL NAME

PIN CONNECTIVITY REQUIREMENTS

Each of these balls must be connected to ground (VSS) through separate

external pull resistors to ensure they are held to a valid logic low level if a

PCB signal trace is connected and not actively driven by an attached device.

The internal pull-down may be used to hold a valid logic low level if no PCB

signal trace is connected to the ball.

SAFETY_ERRORn

Each of these balls must be connected to the corresponding power supply⁽¹⁾

through separate external pull resistors to ensure these balls are held to a

valid logic high level if a PCB signal trace is connected and not actively

driven by an attached device. The internal pull-up may be used to hold a

valid logic high level if no PCB signal trace is connected to the ball.

TCK

TDI

TMS

Each of these balls must be connected to the corresponding power supply⁽¹⁾

through separate external pull resistors to ensure these balls are held to a

valid logic high level.

A13

B13

I2C0_SCL

I2C0_SDA

A11

C10

QSPI0_D0 (SOP0)

QSPI0_D1

SPI0_CLK (SOP2)

SPI0_D0 (SOP3)

Each of these balls must be connected to the corresponding power supply⁽¹⁾

or ground (VSS) through separate external pull resistors to ensure these

balls are held to a valid logic high or low level as appropriate to select the

desired device boot mode.

Any unused ADCx_AINy input ball for any ADC instance (ADC[0:4]_AIN[0:5])

must be connected (shorted) directly to ground (VSS).

ADC ZCZ PIN

ADC[0:4]_AIN[0:5]

If all ADCx_AINy inputs for all ADC instances (ADC[0:4]_AIN[0:5]) are not

used, the ADC_CAL[0:1] analog ball must be connected (shorted) directly to

ground (VSS).

U16

T15

ADC_CAL0

ADC_CAL1

If VSYS_MON is not used, this ball may be connected (shorted) directly to

ground (VSS).

VSYS_MON

If a pin has an associated IOMUX Pad Configuration Registration then the

ball may remain unconnected. After PORz, the LVCMOS voltage buffer is

configured to a default state compatible with an unconnected ball.

Any LVCMOS Voltage Buffer

LVCMOS ZCZ PIN

(1) To determine which power supply is associated with any IO, see POWER column of the Pin Attributes table.

备注

Internal pull resistors are weak and may not source enough current to maintain a valid logic level for

some operating conditions. This may be the case when connected to components with leakage to the

opposite logic level, or when external noise sources couple to signal traces attached to balls which are

only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors may be

required to hold a valid logic level on balls with external connections.

If balls are allowed to float between valid logic levels, the input buffer may enter a high-current state

which could damage the IO cell.

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7 Specifications

7.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted)^{(1) (2)}

PARAMETER

MIN

–0.5

MAX

UNIT

VDD

1.2V SOC core supply

1.5

VDDAR1

VDDAR2

VDDAR3

1.2V SRAM Array Supply 1

1.2V SRAM Array Supply 2

1.2V SRAM Array Supply 3

1.8V IO Bias Supply from Bias LDO routed

through Board

VDDS18

2.1

4.0

2.1

4.0

2.1

–0.5

VDDS33

3.3V IO Supply

1.8V Analog Supply for PLL. Routed from

the 1.8V Analog LDO out through Board

VDDA18_OSC_PLL

VDDA33

Analog 3.3V Supply

1.8V Analog Supply. Routed from the 1.8V

Analog LDO out through Board

VDDA18

3.3V LVCMOS IO Buffer

3.3V I2C Open-Drain IO Buffers

XTAL Pad

VDDS33⁽³⁾+ 0.3

2.1

–0.3

–0.5

IO Pin Steady State Voltage

VDDS33⁽³⁾+ 0.2 × VDDS33⁽³⁾for up

to 20% of signal period

All Other IO Terminals

–0.3

Transient

Overshoot and

Undershoot

XTAL Pad

20% of VDDA18_OSC_PLL for up to 20%

of signal period

0.2 × VDDA18_OSC_PLL

Latch-up I-test Performance (Current-Pulse

Injection on each IO pin)

±100

Latch Up Performance

Class II (150°C)

Latch-up Overvoltage Performance (Voltage

Injection on each IO pin)

Output current

Digital output (per pin), I_OUT

T_stg

°C

–20

–55

Storage temperature⁽⁴⁾

155

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltage values are with respect to VSS, unless otherwise noted.

(3) VDDS33 is the voltage on the corresponding power-supply pin(s) for the IC.

(4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device

life. For additional information, see the Semiconductor and IC Package Thermal Metrics Application Report.

7.2 Electrostatic Discharge (ESD) Extended Automotive Ratings

over recommended operating conditions (unless otherwise noted)

VALUE

±2000

±500

UNIT

Human body model (HBM), per AEC-Q100-002⁽¹⁾

Electrostatic

Discharge

(ESD)

All pins

V_(ESD)

Charged device model (CDM), per AEC-

Q100-011

Corner balls

±750

(A1, A18, V1, V18)

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification

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7.3 Electrostatic Discharge (ESD) Industrial Ratings

over recommended operating conditions (unless otherwise noted)

VALUE

UNIT

Electrostatic

Discharge

(ESD)

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002⁽²⁾

±2000

V_(ESD)

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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7.4 Power-On Hours (POH) Summary

over recommended operating conditions (unless otherwise noted)

PARAMETER

INDUSTRIAL

EXTENDED AUTOMOTIVE

–40℃to 150℃

20K @ Automotive Temp Profile⁽¹⁾

Operating Junction Temperature (Tj)

–40℃to 105℃

100K @ 97℃(100% @ 97℃)

70K @ 105℃(100% @ 105℃)

POH @ Temp Profile

(1) See Automotive Temperature Profile section

7.4.1 Automotive Temperature Profile

HOURS

DAYS

YEARS

PERCENT OF TIME

T_J(℃)

1200

4000

13000

1600

200

~50

~0.14

~0.46

~1.48

~0.18

~0.023

~2.28

–40

~167

~541

~67

20%

65%

130

150

Total

~8.5

~833

20000

100%

7.5 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)

PARAMETER

DESCRIPTION

MIN

NOM

1.200

MAX

UNIT

VDD

1.2V SOC Core Supply

1.140

1.260

VDDAR1, VDDAR2,

VDDAR3

SRAM Array Supplies

1.140

1.200

1.260

VDDS18

VDDS33

1.8V IO Bias Supply from Bias LDO routed through board

3.3V IO Supply

1.710

3.135

1.800

3.300

1.890

3.465

1.8V Analog supply for PLL. Routed from the Analog LDO

out through board

VDDA18_OSC_PLL

VDDA33

1.710

3.135

1.710

1.800

3.300

1.800

1.890

3.465

1.890

Analog 3.3V Supply

1.8V Analog supply. Routed from 1.8V Analog LDO out

through Board

VDDA18

Extended

Free-air temperature

T_A

T_J

125

105

150

°C

–40

Automotive

Industrial

Operating junction temperature range

Extended

Automotive

7.6 Operating Performance Points

This section describes the operating conditions of the device. This section also contains the description of each Operating

Performance Point (OPP) for processor clocks, device core clocks, and available memory.

RAM

(MB)

R5FSS

(MHz)

HSM

(MHz)

ICSS

(MHz)

INFRA⁽¹⁾

(MHz)

DEVICE

AM263x

GRADE

400

200

AM263x

(1) Infrastructure includes all other modules and IP integrated in the device (such as CBASS/Interconnect and other SoC level peripherals)

unless otherwise noted in the table.

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7.7 Power Consumption Summary

节 7.7.1, Power Consumption - Maximum shows the maximum current consumed by each rail and should be

used for power supply selection. 节7.7.2, Power Consumption - Typical shows the typical power consumption by

Module. 节 7.7.3, Power Consumption - Traction Inverter shows the nominal power consumption of the SoC at

different Junction Temperatures for a Traction Inverter application.

For application specific power usage estimates, reference the AM263x Power Estimation Tool Application

Note.

7.7.1 Power Consumption - Maximum

over recommended operating conditions (unless otherwise noted)

SUPPLY NAME

VDD + VDDARn

VDDS33

PARAMETER

Maximum Current Rating for Core Domain

Maximum Current Rating for IO supply

MIN

MAX⁽¹⁾UNIT

2.5

200

100

VDDA33

Maximum Current Rating for 3.3-V Analog supply

(1) The maximum values show the maximum possible current needed for each power rail, and are only intended for power supply

selection. For power consumption in typical applications, see Power Consumption - Typical.

7.7.2 Power Consumption - Typical

Typical usecase power consumption summary, T_J= 85℃

PARAMETER

MIN

TYP

360

MAX

UNIT

Cores and Memory

Infrastructure

Peripherals

Total

424

Power Consumption

258

1042

7.7.3 Power Consumption - Traction Inverter

Traction Inverter Application Power Consumption Across Temperature

PARAMETER

MIN

TYP

MAX

UNIT

1042

1120

1232

1460

T_J= 85℃

T_J= 105℃

T_J= 125℃

T_J= 150℃

Power Consumption

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7.8 Electrical Characteristics

备注

The interfaces or signals described in 节 7.8.1 Digital and Analog IO Electrical Characteristics through

节 7.8.6 Power Management Unit (PMU) correspond to the interfaces or signals available in

multiplexing mode 0 (Primary Function).

All interfaces or signals multiplexed on the balls described in these tables have the same DC electrical

characteristics, unless multiplexing involves a PHY and GPIO combination, in which case different DC

electrical characteristics are specified for the different multiplexing modes (Functions).

7.8.1 Digital and Analog IO Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

PORz IO

V_IH

High-Level Input Voltage

1.35

V_IL

Low-Level Input Voltage

Hysteresis Voltage at an Input

Input Leakage Current

0.5

V_HYS

I_L

Warm Reset IO

0.070

–2

μA

V_IH

High-Level Input Voltage

V_IL

Low-Level Input Voltage

0.8

0.1

V_HYS

V_OL

Hysteresis Voltage at an Input

0.347

Low Level Output Voltage, Driver Enabled : I_OL= 6 mA

× VDDS33⁽¹⁾

I_L

Input Leakage Current, Receiver Disabled, Pull Disabled

–57

μA

TCK IO

V_IH

High-Level Input Voltage

2.15

V_IL

Low-Level Input Voltage

0.55

V_HYS

Hysteresis Voltage at an Input

0.4

Input Leakage Current, Receiver Disabled, Pull Disabled

Input Leakage Current, Receiver Disabled, Pullup Enabled

Input Leakage Current, Receiver Disabled, Pulldown Enabled

8.9

17.2

128.2

130.3

–3.9

μA

106.9

100.3

I_L

I2C OD IOs

V_IH

V_IL

High-Level Input Voltage

Low-Level Input Voltage

0.8

V_HYS

I_L

Hysteresis Voltage at an Input

0.165

Input Leakage Current, Receiver Disabled, Pull Disabled

Low Level Output Voltage, Driver Enabled : I_OL= 3 mA

–18

μA

V_OL

0.1

× VDDS33⁽¹⁾

All Other LVCMOS

V_IH

High- Level Input Voltage

V_IL

Low-Level Input Voltage

0.8

V_HYS

V_OL

Hysteresis Voltage at an Input

0.265

Low Level Output Voltage, Driver Enabled : I_OL= 6 mA

0.1

× VDDS33⁽¹⁾

V_OH

High Level Output Voltage, Driver Enabled : I_OH= 6 mA

0.9

× VDDS33⁽¹⁾

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over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

μA

I_L

Input Leakage Current, Receiver Disabled, Pull Disabled

Input Leakage Current, Receiver Disabled, Pullup Enabled

Input Leakage Current, Receiver Disabled, Pulldown Enabled

-19

–18

-100

100

–243

210

(1) VDDS33 is the voltage on the corresponding power-supply pin on the IC.

7.8.2 Analog-to-Digital Converter (ADC)

over operating junction temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_REFHI

1.71

1.8

1.89

Input Conversion Range (Vin+,

Vin-)

Must be < VDDA33

32/18 × V_REFHI

Power-up time

500

µs

Gain error

±3

±2

LSBs

–5

–4

Offset error

Channel-to-channel gain error

Channel-to-channel offset error

ADC-to-ADC gain error

ADC-to-ADC offset error

DNL

±4

±2

Same reference group

±4

Same reference group

±2

Controlled environment to minimize input noise

±0.5

±1.0

–1

–2

INL

SNR

ENOB (Synchronous Operation)

ENOB (Asynchronous Operation)

ADC-to-ADC isolation

V_REFHIinput current

Conversion time

bits

9.7

bits

Synchronous operation

10 LSBs

µA

–10

400

250

µA

Input Leakage

0.1

3.3

3.46

1.89

Power supply (VDDA33)

Power supply (VDDA18)

Power Consumption (VDDA33)

Power Consumption (VDDA18)

3.13

1.71

1.8

200

700

µA

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7.8.3 Comparator Subsystem A (CMPSSA)

SUBGROUP

PARAMETER

MIN

TYP

MAX

UNIT

µs

Power-up time

VDDA33⁽¹⁾–50mV

Comparator input range

Input referred offset error

Hysteresis (H1)

0.1

LSB

–20

1.8

Comparator

Hysteresis (H2)

Hysteresis (H3)

Hysteresis (H4)

Propagation delay

DAC_VREF reference voltage

1.71

0.1

1.89

Minimum of 33/18 ×

DAC_VREF or

DAC output range

VDDA33⁽¹⁾- 50mV

Static offset error

Static gain error

Static DNL

-45

–2

% of FSR

LSB

>–1

–16

DAC

Static INL

LSB

Settling time

Resolution

µs

bits

DAC output disturbance (comparator trip

kickback)

100

LSB

–100

DAC output disturbance (comparator trip

kickback)

200

DAC_VREF loading

0.1

3.3

1.8

900

120

kΩ

µA

Input Leakage

3.46

1.89

Power supply (VDDA33)

Power supply (VDDA18)

Power Consumption (VDDA33)

Power Consumption (VDDA18)

Failsafe Input current injection

3.13

1.71

Common

µA

(1) VDDA33 is the voltage on the corresponding power-supply pin(s) on the IC.

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7.8.4 Comparator Subsystem B (CMPSSB)

SUBGROUP

PARAMETER

MIN

TYP

MAX

UNIT

µs

Power-up time

VDDA33⁽¹⁾–50mV

Comparator input range

Input referred offset error

Hysteresis (H1)

0.1

LSB

–20

1.8

Comparator

Hysteresis (H2)

Hysteresis (H3)

Hysteresis (H4)

Step response time

DAC_VREF reference voltage

1.71

0.1

1.89

Minimum of 33/18 ×

DAC_VREF or

DAC output range

VDDA33⁽¹⁾- 50mV

Static offset error

Static gain error

Static DNL

% of FSR

LSB

–45

–2

>–1

–16

DAC

Static INL

LSB

Settling time

Resolution

µs

bits

DAC output disturbance (comparator trip

kickback)

100

LSB

–100

DAC output disturbance (comparator trip

kickback)

200

DAC_VREF loading

0.1

3.3

1.8

900

120

kΩ

µA

Input Leakage

3.46

1.89

Power supply (VDDA33)

Power supply (VDDA18)

Power consumption (VDDA33)

Power consumption (VDDA18)

Failsafe input current injection

3.13

1.71

Common

µA

(1) VDDA33 is the voltage on the corresponding power-supply pin(s) on the IC.

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7.8.5 Digital-to-Analog Converter (DAC)

over operating junction temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

µs

Power-up time

DAC_VREF

Voltage output range

Trimmed offset error

Gain error

1.71

0.3

1.8

1.89

VDDA33⁽¹⁾–0.3

Offset is checked at Midpoint (code 2048)

DAC_VREF = 1.8V

–10

–2.5

–1

2.5 % of FSR

DNL

Endpoint corrected

LSB

INL

Endpoint corrected

–20

Settling to 2 LSBs (~1.6mV) after 0.3V-to-3V

transition

Settling time

µs

Resolution

bits

Capacitive load

Resistive load

DAC_VREF loading

Output drive capability

DAC_VREF

100

kΩ

Output noise (100 Hz- 100 KHz) Integrated noise from 100 Hz to 100 kHz

mVrms

2MHz DACVALA update rate, 200kHz output

SNR @ 1KHz

filter

Power supply (VDDA33)

3.13

1.71

3.3

1.8

850

3.46

1.89

Power supply (VDDA18)

Power Consumption (VDDA33)

Power Consumption (VDDA18)

µA

(1) VDDA33 is the voltage on the corresponding power-supply pin(s) on the IC.

7.8.6 Power Management Unit (PMU)

over operating junction temperature range (unless otherwise noted)

GROUP

PARAMETER

MIN

3.1

TYP

MAX

UNIT

PMU

Power supply (VDDA33)

3.3

0.9

1.8

3.46

0.914

1.836

1.89

Bandgap

V_REFtrimmed

0.886

1.764

1.71

DC accuracy

Transient load regulation

DC Load regulation

Load current

1.8V LDO

Power up time

Inrush current

800

150

20%

External decap

Load Regulation

DC accuracy

4.7

+/-1

1.8

–20%

ADC Reference

1.764

1.836

800

Power up time

Inrush current

External decap

4.7

20%

–20%

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7.8.7 Safety Comparators

PARAMETER

MIN

1.40

0.75

0.935

1.47

2.13

0.98

1.407

1.56

2.09

1.47

2.13

1.56

2.09

0.873

2.59

1.56

2.09

TYP

1.5

MAX

1.6

UNIT

C0 C0: 1.8-V Monitor Threshold

Lower Threshold

Upper Threshold

Lower Threshold

Upper Threshold

Lower Threshold

Upper Threshold

Lower Threshold

Upper Threshold

Lower Threshold

Upper Threshold

Lower Threshold

Upper Threshold

Lower Threshold

0.8

0.85

1.065

1.57

2.26

1.041

1.494

1.66

2.22

1.57

2.26

1.66

2.22

0.927

2.95

1.66

2.22

C1 BGAP Monitor

1.52

2.195

1.011

1.451

1.61

2.16

1.52

2.195

1.61

2.16

0.9

C2 Monitors 1.8-V Supply vs BGAP

C3 Monitors 1.2-V vs BGAP

C4 Vref Monitor (ROK0)

C5 Monitors IO Bias Supply vs BGAP

C6 Vref Monitor (ROK0B)

C7 System Supply Monitor (VSYS_MON)

C8 UnderVoltage Threshold

2.77

1.61

2.16

Lower Threshold

Upper Threshold

C9 Vref Monitor (ROK1)

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7.9 VPP Specifications for One-Time Programmable (OTP) eFuses

This section specifies the operating conditions required for programming the OTP eFuses.

7.9.1 VPP Specifications

over recommended operating conditions (unless otherwise noted)

PARAMETER

DESCRIPTION

TEST CONDITIONS

MIN

NOM

MAX UNIT

Supply voltage range for the core

domain during OTP operation

VDD

Normal Operation (OPP100)

1.140

1.200

1.260

Supply voltage range for the eFuse

ROM domain

Normal Operation (OPP100)

OTP Programming

No Connection

1.7

Supply voltage range for the eFuse

ROM domain during OTP

programming

VPP

1.65

1.75

I_(VPP)

T_A

VPP Current

I_(VPP)

100 mA

Ambient Temperature

℃

7.9.2 Hardware Requirements

The following hardware requirements must be met when programming keys in the OTP eFuses:

• The VPP power supply must be disabled when not programming OTP registers.

• The VPP power supply must be ramped up after the proper device power-on sequence (for more details, see

节7.11.2.1, Power-On and Reset Sequencing).

7.9.3 Programming Sequence

Programming sequence for OTP eFuses:

• Power on the board per the power-on sequencing. No voltage should be applied on the VPP terminal during

power up and normal operation.

• Load the OTP write software required to program the eFuse (contact your local TI representative for the OTP

software package).

• Apply the voltage on the VPP terminal according to the specification in 节7.9.1, VPP Specifications.

• Run the software that programs the OTP registers.

• After validating the content of the OTP registers, remove the voltage from the VPP terminal.

7.9.4 Impact to Your Hardware Warranty

You accept that e-Fusing the TI Devices with security keys permanently alters them. You acknowledge that the

e-Fuse can fail, for example, due to incorrect or aborted program sequence or if you omit a sequence step.

Further the TI Device may fail to secure boot if the error code correction check fails for the Production Keys or if

the image is not signed and optionally encrypted with the current active Production Keys. These types of

situations will render the TI Device inoperable and TI will be unable to confirm whether the TI Devices conformed

to their specifications prior to the attempted e-Fuse.

CONSEQUENTLY, TI WILL HAVE NO LIABILITY (WARRANTY OR OTHERWISE) FOR ANY TI DEVICES THAT

HAVE BEEN e-FUSED WITH SECURITY KEYS.

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7.10 Thermal Resistance Characteristics

This section provides the thermal resistance characteristics used on this device.

For reliability and operability concerns, the maximum junction temperature of the device has to be at or below

the T_Jvalue identified in 节7.5, Recommended Operating Conditions.

7.10.1 Package Thermal Characteristics

It is recommended to perform thermal simulations at the system level with the worst case device power consumption.

AIR FLOW (m/s)

℃/W^{(1) (2)}

PARAMETER

DESCRIPTION

(3)

Junction-to-case

Junction-to-board

Junction-to-free air

5.6

N/A

RΘ_JC

RΘ_JB

RΘ_JA

5.7

18.6

12.9

11.8

11.1

0.1

Junction-to-moving air

RΘ_JA

0.4

Junction-to-package top

Junction-to-board

Ψ_JT

0.5

0.6

5.6

5.7

Ψ_JB

5.7

5.6

(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘ_JC] value, which is based on a

JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/

JEDEC standards:

•JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)

•JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

•JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)

•JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

•JESD51-9, Test Boards for Area Array Surface Mount Packages

(2) ℃/W = degrees Celsius per watt

(3) m/s = meters per second

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7.11 Timing and Switching Characteristics

备注

The default SLEWRATE settings in each pad configuration register must be used to ensure timings,

unless specific instructions are given otherwise.

7.11.1 Timing Parameters and Information

The timing parameter symbols used in Timing and Switching Characteristics sections are created in accordance

with JEDEC Standard 100. To shorten the symbols, some pin names and other related terminologies have been

abbreviated in 表7-1:

表7-1. Timing Parameters Subscripts

SYMBOL

PARAMETER

Cycle time (period)

Delay time

dis

Disable time

Enable time

Hold time

START

Setup time

Start bit

Transition time

Valid time

Pulse duration (width)

Unknown, changing, or don't care level

Fall time

High

Low

Rise time

Valid

Invalid

Active Edge

First Edge

Last Edge

High impedance

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7.11.2 Power Supply Sequencing

This section describes power supply sequencing required to ensure proper device operation.

7.11.2.1 Power-On and Reset Sequencing

AM263x attempts to simplify the power reset requirements from previous Sitara MCU devices. There is no

sequencing requirement with respect to the primary core digital VDD 1.2-V and I/O power 3.3-V rails. A pair of

on-die LDO are supplied through the VDDS33 power net. These on-die LDO generate the required VDDS1V8

and VDDA1V8 1.8-V digital and analog power. The AM263x does require the minimum ramp time be respected

for 3.3-V power-on. Additional PORz and SOP boot mode latch timing must be respected by the EVM design as

well. 图7-1 describes the device power-on sequencing.

表7-2. AM263x Power-On Sequencing

PARAMETER

MIN

MAX

UNIT

Time for 1.2-V and 3.3-V DC-DC converters to startup after being enabled. This is an

arbitrary amount of time - no constraint imposed by the device.

t_Startup

–

Time for Power Good signals to be generated from DC-DC converters after rails are

stable. This is an arbitrary amount of time - no constraint imposed by the device.

t_PGood

Ramp time of the VDDS3V3 and VDDA3V3 supplies. This is a requirement imposed by

the device.

t_{Ramp_3V3}

0.1

Time from PORz de-assertion until the SOP[3:0] pins are sampled. This is a device

internal pentameter. Sampling happens when the internally generated supplies are

stable. For information only. Refer to TSU_SOP and TH_SOP parameters for application

usage.

t_{SOP_Sampled}

–

Setup time for SOP relative to PORz assertion.

t_{SU_SOP}

t_{H_SOP}

μs

–

Hold time for SOP relative to WARMRSTn deassertion.

t_WARMRSTn

Time from PORz de-assertion until the device de-asserts the WARMRESETn signal.

2.0

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tStartup

tPGood

VDD, VDDARn (1.2 V)

1.2V Power Good

Output (PG_1V2)

tPORz

VDDS33, VDDA33 (3.3 V)

3.3V Power Good

tRamp_3V3

Output (PG_3V3)

PG_1V2 AND PG_3V3

PORz

tWARMRSTn

Pin is Tristate.

Signal Level determined by external pull or driver.

WARMRSTn

tSOP_Sampled

SOP[3:0]

tSU_SOP

tH_SOP

图7-1. Power-On Sequencing

7.11.2.1.1 Power Reset Sequence Description

The following set of steps shall occur on the EVM and AM263x to boot the device from power-on reset.

1. PORz is held low by the external power supply monitor

2. VDD core digital 1.2V and VDDS3V3/VDDA3V3 3.3V supplies ramp to their nominal voltages

a. This requires a logical AND be applied to the power good signal generated from each supply

3. SOP[3:0] pins held in their boot latch state

4. After PCB supplied power nets are stable, the external supply monitor will de-assert PORz

5. Device will startup 1.8V on-die LDO

6. After internal supply monitors show externally and internally generated supplies are stable, the SOP[3:0] pin

states are latched

7. R5F cores are unhalted and SOP selected boot ROM execution begins

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7.11.2.2 Power-Down Sequencing

图7-2 describes the device power-down sequencing. The order of AM263x 1.2V and 3.3V does not matter.

VDD, VDDARn (1.2 V)

1.2V Power Good

Output (PG_1V2)

VDDS33, VDDA33 (3.3 V)

3.3V Power Good

Output (PG_3V3)

AM263x PORz

图7-2. Power-Down Sequencing

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7.11.3 System Timing

For more details about features and additional description information on the subsystem multiplexing signals,

see the corresponding subsections within Signal Descriptions and Detailed Description sections.

System Timing Conditions

PARAMETER

MIN

0.5

MAX

UNIT

V/ns

INPUT CONDITIONS

SR_I

Input Slew Rate

OUTPUT CONDITIONS

C_L

Output Load Capacitance

7.11.3.1 Reset Timing

Tables and figures provided in this section define timing requirements and switching characteristics for reset

related signals.

PORz Timing Requirements

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

Hold time, PORz active (low) at

Power-up after supplies valid (using

external crystal)

t_{h(SUPPLIES_VALID-}

RST1

RST3

PORz)

Pulse Width minimum, PORz low after

Power-up (without removal of Power

or system reference clock

t_w(PORzL)

1000

XTAL_XI/XO)

RST1

RST3

PORz

ALL SUPPLIES

VALID

图7-3. PORz Timing Requirements

WARMRSTn Switching Characteristics

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

t_d(PORzL:-

Delay time, PORz active (low) to WARMRSTn

high impedance

RST4

WARMRSTnZ)

t_d(PORzH-

Delay time, PORz inactive (high) to

WARMRSTn active (low)

RST5

RST6

WARMRSTnL)

t_d(PORzH-

Delay time, PORz inactive (high) to

WARMRSTn inactive (high)

2000000

6000000

WARMRSTnH)

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RST4

RST5

PORz

RST6

WARMRSTn

图7-4. WARMRSTn Switching Characteristics

WARMRSTn Timing Requirements

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

Pulse Width minimum, WARMRSTn

active (low)

(1)

RST10

t_w(WARMRSTnL)

500

16384000

(1) This timing parameter is controlled by the TOP_RCM.WARM_RSTTIME1/2/3 registers. See the Reset section of the Technical

Reference Manual for more details.

RST10

WARMRSTn

图7-5. WARMRSTn Timing Requirements and Switching Characteristics

7.11.3.2 Safety Signal Timing

Tables and figures provided in this section define switching characteristics for SAFETY_ERRORn.

SAFETY_ERRORn Switching Characteristics

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

Cycle time minimum, SAFETY_ERRORn

(PWM mode enabled)

(P⁽¹⁾× H⁽³⁾) + (P⁽¹⁾

SFTY1

t_{c(SAFETY_ERRORn)}

L)⁽⁴⁾

Pulse width minimum, SAFETY_ERRORn

active (PWM mode disabled)⁽⁵⁾

SFTY2

SFTY3

t_{w(SAFETY_ERRORn)}

P⁽¹⁾× R⁽²⁾

50 × P⁽¹⁾

t_{d(ERROR_CONDITIO}Delay time, ERROR_CONDITION to

SAFETY_ERRORn active⁽⁵⁾

N-SAFETY_ERRORnL)

(1) P = ESM functional clock

(2) R = Error Pin Counter Pre-Load Register count value

(3) H = Error Pin PWM High Pre-Load Register count value

(4) L = Error Pin PWM Low Pre-Load Register count value

(5) When PWM mode is enabled, SAFETY_ERRORn stops toggling after RST22 and will maintain its value (either high or low) until the

error is cleared. When PWM mode is disabled, SAFETY_ERRORn is active low

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Internal Error Condition

(Active High)

SFTY1

SAFETY_ERRORn

(PWM Mode Enabled)

SFTY2

SFTY3

SAFETY_ERRORn

(PWM Mode Disabled)

图7-6. MCU_SAFETY_ERRORn Timing Requirements and Switching Characteristics

7.11.4 Clock Specifications

7.11.4.1 Input Clocks / Oscillators

7.11.4.1.1 Crystal Oscillator (XTAL) Parameters

PARAMETER

MIN

TYP

MAX

UNIT

Crystal Parallel Resonance Frequency

(Fundamental mode oscillation only)

F_xtal

50ppm

MHz

–50ppm

CC1

Capacitance of C_L1+ C_PCBXI

Ω

CC2

Capacitance of C_L2+ C_PCBXO

Crystal Circuit Shunt Capacitance

Crystal Effective Series Resistance

C_shunt

ESR_xtal

7.11.4.1.2 External Clock Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

C_Pkg

P_xtal

t_s

Shunt Capacitance of pkg

Power dissipation

Start up time

0.01

0.5 × ESR × (2 × π× F_xtal× C_L× 1.8)²

1.5

7.11.4.2 Clock Timing

Tables and figures provided in this section define timing requirements and switching characteristics for clock

signals.

Clock Timing Requirements

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

CLK1

CLK2

tc(EXT_REFCLK) Cycle time minimum, EXT_REFCLK

tw(EXT_REFCLK Pulse Duration minimum,

E⁽¹⁾× 0.45

E⁽¹⁾× 0.55

tw(EXT_REFCLKL Pulse Duration minimum,

EXT_REFCLK low

EXT_REFCLK high

CLK3

)

(1) E = EXT_REFCLK cycle time

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CLK1

CLK3

CLK2

EXT_REFCLK

图7-7. Clock Timing Requirements

Clock Switching Characteristics

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

CLK4

t_c(CLKOUT0)

Cycle time minimum, CLKOUT0

CLK5

CLK6

CLK7

CLK8

CLK9

t_w(CLKOUT0H)

t_w(CLKOUT0L)

t_c(CLKOUT1)

Pulse Duration minimum, CLKOUT0 high

Pulse Duration minimum, CLKOUT0 low

Cycle time minimum, CLKOUT1

A⁽¹⁾× 0.4

A⁽¹⁾× 0.6

t_w(CLKOUT1H)

t_w(CLKOUT1L)

Pulse Duration minimum, CLKOUT1 high

Pulse Duration minimum, CLKOUT1 low

B⁽²⁾× 0.4

B⁽²⁾× 0.6

(1) A = CLKOUT0 cycle time

(2) B = CLKOUT1 cycle time

CLK4

CLK5

CLK6

CLKOUT0

CLKOUT1

CLK7

CLK8

CLK9

图7-8. Clock Switching Characteristics

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7.11.5 Peripherals

7.11.5.1 2-port Gigabit Ethernet MAC (CPSW3G)

备注

The CPSW3G supports two external Ethernet ports and one internal port.

For more details about features and additional description information on the device CPSW3G (2-port Gigabit

Ethernet MAC), see the corresponding subsections within Signal Descriptions and Detailed Description sections.

7.11.5.1.1 CPSW3G MDIO Timing

CPSW3G MDIO Timing Conditions

PARAMETER

MIN

0.9

MAX

3.6

UNIT

V/ns

INPUT CONDITIONS

SR_I

Input Slew Rate

OUTPUT CONDITIONS

C_L

Output Load Capacitance

470

CPSW3G MDIO Timing Requirements

NO.

MDIO1

MDIO2

PARAMETER

t_sw(MDIO-MDC)

t_h(MDC-MDIO)

DESCRIPTION

MIN

MAX

UNIT

Setup time, MDIO_DATA valid before

MDIO_CLK high

Hold time, MDIO_DATA valid after MDIO_CLK

high

CPSW3G MDIO Switching Characteristics

NO.

PARAMETER

t_c(MDC)

t_w(MDCH)

t_w(MDCL)

DESCRIPTION

MIN

400

160

MAX

UNIT

MDIO3

Cycle time, MDIO_CLK

MDIO4

MDIO5

Pulse duration, MDIO_CLK high

Pulse duration, MDIO_CLK low

Delay time, MDIO_CLK low to MDIO_DATA

valid

MDIO7

t_{d(MDC_MDIO)}

150

–150

MDIO3

MDIO4

MDIO5

MDIO[x]_MDC

MDIO1

MDIO2

MDIO[x]_MDIO

(input)

MDIO7

MDIO[x]_MDIO

(output)

CPSW2G_MDIO_TIMING_01

图7-9. CPSW3G MDIO Timing Requirements and Switching Characteristics

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7.11.5.1.2 CPSW3G RMII Timing

CPSW3G RMII Timing Conditions

PARAMETER

MIN

0.4

MAX

1.2

UNIT

V/ns

INPUT CONDITIONS

SR_I

Input Slew Rate

VDD = 3.3V

OUTPUT CONDITIONS

C_LOutput Load Capacitance

CPSW3G RMII[x]_REFCLK Timing Requirements - RMII Mode

NO.

PARAMETER

t_{c(REF_CLK)}

t_{w(REF_CLKH)}

t_{w(REF_CLKL)}

DESCRIPTION

MIN

MAX

UNIT

RMII1

Cycle time, REF_CLK

19.999

RMII2

RMII3

Pulse duration, REF_CLK High

Pulse duration, REF_CLK Low

RMII1

RMII2

RMII[x]_REF_CLK

RMII3

图7-10. CPSW3G RMII[x]_REF_CLK Timing Requirements –RMII Mode

CPSW3G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER Timing Requirements - RMII Mode

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

t_{su(RXD-REF_CLK)}

Setup time, RXD[1:0] valid before REF_CLK

Setup time, CRS_DV valid before REF_CLK

Setup time, RX_ER valid before REF_CLK

Hold time, RXD[1:0] valid after REF_CLK

Hold time, CRS_DV valid after REF_CLK

Hold time, RX_ER valid after REF_CLK

RMII4

t_{su(CRS_DV-REF_CLK)}

t_{su(RX_ER-REF_CLK)}

t_{h(REF_CLK-RXD)}

RMII5

t_{h(REF_CLK-CRS_DV)}

t_{h(REF_CLK-RX_ER)}

RMII4

RMII5

RMII[x]_REF_CLK

RMII[x]_RXD[1:0], RMII[x]_CRS_DV,

RMII[x]_RX_ER

图7-11. CPSW3G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RX_ER Timing Requirements –RMII Mode

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CPSW3G RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics - RMII Mode

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

Delay time, REF_CLK High to TXD[1:0]

valid

t_{d(REF_CLK-TXD)}

RMII6

t_{d(REF_CLK-TXEN)}

Delay time, REF_CLK to TXEN valid

RMII6

RMII[x]_REF_CLK

RMII[x]_TXD[1:0], RMII[x]_TX_EN

图7-12. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics –RMII Mode

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7.11.5.1.3 CPSW3G RGMII Timing

CPSW3G RGMII Timing Conditions

PARAMETER

MIN

2.64

MAX

UNIT

V/ns

INPUT CONDITIONS

SR_I

Input Slew Rate

OUTPUT CONDITIONS

C_L

Output Load Capacitance

PCB Connectivity Requirements

RGMII[x]_RXC

RGMII[x]_RD[3:0]

RGMII[x]_RX_CTL

t_d(Trace Mismatch Propogation Delay mismatch across all

Delay)

traces

RGMII[x]_TXC

RGMII[x]_TD[3:0]

RGMII[x]_TX_CTL

CPSW3G RGMII[x]_RCLK Timing Requirements - RGMII Mode

NO.

PARAMETER

DESCRIPTION

MODE

10Mbps

MIN

MAX

UNIT

360

440

RGMII1

t_c(RXC)

Cycle time, RXC

100Mbps

1000Mbps

10Mbps

7.2

160

8.8

240

RGMII2

RGMII3

tw(RXCH)

tw(RXCL)

Pulse duration, RXC high

Pulse duration, RXC low

100Mbps

1000Mbps

10Mbps

3.6

160

4.4

240

100Mbps

1000Mbps

3.6

4.4

CPSW3G RGMII[x]_RD[3:0], and RGMII[x]_RCTL Timing Requirements

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

10Mbps

Setup time, RD[3:0] valid before RXC

high/low

t_su(RD-RXC)

100Mbps

1000Mbps

10Mbps

RGMII4

Setup time, RX_CTL valid before RXC

high/low

t_{su(RX_CTL-RXC)}

100Mbps

1000Mbps

10Mbps

t_h(RXC-RD)

Hold time, RD[3:0] valid after RXC high/low 100Mbps

1000Mbps

10Mbps

RGMII5

Hold time, RX_CTL valid after RXC

t_{h(RXC-RX_CTL)}

100Mbps

high/low

1000Mbps

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RGMII1

RGMII2

RGMII3

RGMII[x]_RXC^(A)

RGMII4

RGMII5

RGMII[x]_RD[3:0]^(B)

RGMII[x]_RX_CTL^(B)

1st Half-byte

RXDV

2nd Half-byte

RXERR

A. RGMII[x]_RXC must be externally delayed relative to the data and control pins.

B. Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the rising edge of

RGMII[x]_RXC and data bits 7-4 on the falling edge of RGMII[x]_RXC. Similarly, RGMII[x]_RX_CTL carries RXDV on rising edge of

RGMII[x]_RXC and RXERR on falling edge of RGMII[x]_RXC.

图7-13. CPSW3G RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL Timing Requirements - RGMII

Mode

CPSW3G RGMII[x]_TCLK Switching Characteristics - RGMII Mode

NO.

PARAMETER

DESCRIPTION

MODE

10Mbps

MIN

360

MAX

440

UNIT

RGMII6

t_c(TXC)

Cycle time, TXC

100Mbps

1000Mbps

10Mbps

7.2

160

8.8

240

RGMII7

RGMII8

t_w(TXCH)

Pulse duration, TXC high

Pulse duration, TXC low

100Mbps

1000Mbps

10Mbps

3.6

160

4.4

240

t_w(TXCL)

100Mbps

1000Mbps

3.6

4.4

CPSW3G RGMII[x]_TD[3:0], and RGMII[x]_TCTL Switching Characteristics - RGMII Mode

NO.

PARAMETER

DESCRIPTION

MODE

MIN

1.2

MAX

UNIT

10Mbps

Output setup time, RGMII[x]_TD[3:0] valid

to RGMII[x]_TXC high/low

t_osu(TD-TXC)

100Mbps

1000Mbps

10Mbps

RGMII9

Output setup time, RGMII[x]_TX_CTL valid

to RGMII[x]_TXC high/low

t_{osu(TX_CTL-TXC)}

100Mbps

1000Mbps

10Mbps

Output hold time, RGMII[x]_TD[3:0] valid

after RGMII[x]_TXC high/low

t_oh(TXC-TD)

100Mbps

1000Mbps

10Mbps

RGMII10

Output hold time, RGMII[x]_TX_CTL valid

after RGMII[x]_TXC high/low

t_{oh(TXC-TX_CTL)}

100Mbps

1000Mbps

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RGMII6

RGMII7

RGMII8

RGMII[x]_TXC^(A)

RGMII9

RGMII[x]_TD[3:0]^(B)

RGMII[x]_TX_CTL^(B)

1st Half-byte

TXEN

2nd Half-byte

RGMII10

TXERR

A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.

B. Data and control information is received using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on the rising edge of

RGMII[x]_TXC and data bits 7-4 on the falling edge of RGMII[x]_TXC. Similarly, RGMII[x]_TX_CTL carries TXEN on rising edge of

RGMII[x]_TXC and TXERR on falling edge of RGMII[x]_TXC.

图7-14. CPSW3G RGMII[x]_TXC, RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics -

RGMII Mode

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7.11.5.2 Enhanced Capture (eCAP)

备注

The device has multiple eCAP modules. The generic CAP_ prefix is used to represent the signal

names for all eCAP instances.

For more information, see Enhanced Capture (eCAP) Module section in the device TRM.

eCAP Timing Conditions

PARAMETER

MIN

MAX

UNIT

V/ns

INPUT CONDITIONS

SR_I

Input Slew Rate

OUTPUT CONDITIONS

C_L

Output Load Capacitance

eCAP Timing Requirements

NO.

PARAMETER

DESCRIPTION

Asynchronous

MIN MAX

UNIT

(2 + X⁽²⁾) × P⁽¹⁾

(3 + X⁽²⁾) × P⁽¹⁾

(2 + X⁽²⁾) × P⁽¹⁾+ U⁽³⁾

CAP1

t_w(CAP)

Capture input pulse width

Synchronous

With input qualifier

(1) P = sysclk period in ns.

(2) X = value of ECCTL0_TYPE3[QUALPRD] setting.

(3) U = the input qualifier sampling window. See GPIO Electrical Data and Timing section for details on Input Qualifier Mode

CAP1

CAP

EPERIPHERALS_TIMNG_01

图7-15. ECAP Timings Requirements

eCAP Switching Charcteristics

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

CAP2

t_w(APWM)

Pulse duration, APWMx output high/low

CAP2

APWM

EPERIPHERALS_TIMNG_02

图7-16. ECAP Switching Characteristics

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7.11.5.3 Enhanced Pulse Width Modulation (ePWM)

备注

The device has multiple ePWM modules. The generic EHRPWM_ prefix is used to represent the

signal names for all ePWM instances.

For more information, see Enhanced Pulse Width Modulation (ePWM) Module section in the device TRM.

ePWM Timing Conditions

PARAMETER

MIN

MAX

UNIT

V/ns

INPUT CONDITIONS

SR_I

Input Slew Rate

OUTPUT CONDITIONS

C_L

Output Load Capacitance

ePWM Timing Requirements

NO.

PWM6

PWM7

PARAMETER

t_w(SYNCIN)

t_w(TZ)

DESCRIPTION

Pulse duration, EHRPWM_SYNCI

Pulse duration, EHRPWM_TZn_IN low

MIN

2P⁽¹⁾

1P⁽¹⁾

MAX

UNIT

(1) P = sysclk period in ns.

PWM6

EHRPWM_SYNCI

PWM7

EHRPWM_TZn_IN

EPERIPHERALS_TIMNG_07

图7-17. EPWM Timing Requirements

ePWM Switching Characteristics

NO.

PARAMETER

t_w(PWM)

t_w(SYNCOUT)

DESCRIPTION

MIN

MAX

UNIT

PWM1

Pulse duration, EHRPWM_A/B high/low

Pulse duration, EHRPWM_SYNCO

PWM2

PWM3

8P⁽¹⁾

Delay time, EHRPWM_TZn_IN active to

EHRPWM_A/B forced high/low

t_d(TZ-PWM)

t_d(TZ-PWMZ)

t_w(SOC)

Delay time, EHRPWM_TZn_IN active to

EHRPWM_A/B Hi-Z

PWM4

PWM5

Pulse duration, EHRPWM_SOCA/B output

32P⁽¹⁾

(1) P = sysclk period in ns.

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PWM1

EHRPWM_A/B

PWM1

PWM2

EHRPWM_SYNCO

PWM5

EHRPWM_SOCA/B

EPERIPHERALS_TIMNG_04

图7-18. EHRPWM Switching Characteristics

PWM3

EHRPWM_A/B

EHRPWM_TZn_IN

EPERIPHERALS_TIMING_05

图7-19. EHRPWM_TZn_IN to EHRPWM_A/B Forced Switching Characteristics

PWM4

EHRPWM_A/B

EHRPWM_TZn_IN

图7-20. EHRPWM_TZn_IN to EHRPWM_A/B Hi-Z Switching Characteristics

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7.11.5.4 Enhanced Quadrature Encoder Pulse (eQEP)

备注

The device has multiple eQEP modules. The generic QEP_ prefix is used to represent the signal

names for all eQEP instances.

For more information, see Enhanced Quadrature Encoder Pulse (eQEP) Module section in the device TRM.

eQEP Timing Conditions

PARAMETER

MIN

MAX

UNIT

V/ns

INPUT CONDITIONS

SR_I

Input Slew Rate

OUTPUT CONDITIONS

C_L

Output Load Capacitance

eQEP Timing Requirements

NO.

PARAMETER

DESCRIPTION

Synchronous⁽³⁾

MIN

MAX

UNIT

3P⁽¹⁾

QEP1

t_w(QEPP)

QEP input period

With input qualifier

Synchronous⁽³⁾

2 × (P⁽¹⁾+ U⁽²⁾

)

2 + 3P⁽¹⁾

2P⁽¹⁾+ U⁽²⁾

3P⁽¹⁾

QEP2

QEP3

QEP4

QEP5

t_w(INDEXH)

t_w(INDEXL)

t_w(STROBH)

t_w(STROBL)

QEP Index Input High time

QEP Index Input Low time

QEP Strobe High time

QEP Strobe Input Low time

With input qualifier

Synchronous⁽³⁾

With input qualifier

Synchronous⁽³⁾

2P⁽¹⁾+ U⁽²⁾

3P⁽¹⁾

With input qualifier

Synchronous⁽³⁾

2P⁽¹⁾+ U⁽²⁾

3P⁽¹⁾

With input qualifier

2P⁽¹⁾+ U⁽²⁾

(1) P = sysclk period in ns.

(2) U = the input qualifier sampling window. See GPIO Electrical Data and Timing section for details on Input Qualifier Mode.

(3) The GPIO GPxQSELn Asynchronous mode should not be used for eQEP module input pins.

QEP1

QEP_A/B

QEP2

QEP_I

QEP3

QEP4

QEP_S

QEP5

EPERIPHERALS_TIMNG_03

图7-21. EQEP Timing Requirements

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eQEP Switching Characteristics

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

QEP6

t_d(CNTR)xin

Delay time, external clock to counter increment

4 + U⁽²⁾+ 6P⁽¹⁾

Delay time, QEP input edge to position compare

sync output

QEP7

t_{d(PCS-OUT)QEP}

4 + U⁽²⁾+ 7P⁽¹⁾+ 4

(1) P = sysclk period in ns.

(2) U = the input qualifier sampling window. See GPIO Electrical Data and Timing section for details on Input Qualifier Mode.

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7.11.5.5 Fast Serial Interface (FSI)

备注

The device has multiple FSI modules. FSIn is a generic prefix applied to FSI signal names, where n

represents the specific FSI module.

For more information, see Fast Serial Interface section in the device TRM.

FSI Timing Conditions

PARAMETER

MIN

0.8

MAX

UNIT

V/ns

INPUT CONDITIONS

SR_I

Input Slew Rate

OUTPUT CONDITIONS

C_L

Output Load Capacitance

FSIRX Timing Requirements

NO.

PARAMETER

DESCRIPTION

Cycle time, FSIRXn_CLK

MIN

MAX

UNIT

FSIR1

t_{c(RX_CLK)}

16.67

Pulse width, FSIRXn_CLK low or

FSIRXn_CLK high

FSIR2

FSIR3

FSIR4

t_{w(RX_CLK)}

0.65P⁽¹⁾+ 1

0.35P⁽¹⁾–1

Delay time, FSIRXn_D[0:1] valid before

FSIRXn_CLK

td_{(RX_D–RX_CLK)}

t_{h(RX_CLK–RX_D)}

1.7

Hold time with respect to both edges of

FSIRXn_CLK

(1) P = Tc(RXCLK) = RX Interface clock period in ns.

FSIR1

FSIR2

FSI_RXn_CLK

FSI_RXn_D0

FSI_RXn_D1

FSIR3

FSIR4

图7-22. FSI Timing Requirements

FSIRX Switching Characteristics

NO.

PARAMETER

t_{d(RX_CLK)}

t_{d(RX_D0)}

t_{d(RX_D1)}

DESCRIPTION

MIN

MAX

UNIT

FSIRXn_CLK delay compensation at

RX_DLYLINE_CTRL[RXCLK_DLY]=31

FSIR5

FSIRXn_D0 delay compensation at

RX_DLYLINE_CTRL[RXCLK_DLY]=31

FSIR6

FSIR7

FSIRXn_D1 delay compensation at

RX_DLYLINE_CTRL[RXCLK_DLY]=31

Incremental delay of each delay line element

for FSIRXn_CLK, FSIRXn_D0, and

FSIRXn_D1

FSIR8

t_{d(DELAY_ELEMENT)}

0.3

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NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

FSIR_TD

Delay skew between FSIRXn_TDM_CLK

delay and FSIRXn_TDM_D[0:1]

t_{skew(RX_CLK-TX_TDM_D)}

–3

FSIR_TD t_{skew(RX_CLK-}

Delay time, FSIRXn_CLK input to

FSITXn_TDM_CLK output

TX_TDM_CLK)

FSIR_TD

Delay time, FSIRXn_D0 input to

FSITXn_TDM_D0 output

t_{skew(RX_D0-TX_TDM_D0)}

FSIR_TD

Delay time, FSIRXn_D1 input to

FSITXn_TDM_D1 output

t_{skew(RX_D1-TX_TDM_D1)}

FSITX Switching Characteristics

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

FSIT1

t_{c(TX_CLK)}

Cycle time, FSITXn_CLK

16.67

Pulse width, FSITXn_CLK low or

FSITXn_CLK high

FSIT2

FSIT3

FSIT4

FSIT5

FSIT6

t_{w(TX_CLK)}

td_{(TX_CLK-TX_D)}

t_d(TXCLKL)

t_{d(TX_D0)}

0.5P⁽¹⁾+ 1

0.5P⁽¹⁾–1

0.25P⁽¹⁾–2

9.95

Delay time, FSITXn_Dx valid after

FSITXn_CLK high or FSITXn_CLK low

0.25P⁽¹⁾+ 2

FSITXn_CLK delay compensation at

TX_DLYLINE_CTRL[TXCLK_DLY]=31

FSITXn_D0 delay compensation at

TX_DLYLINE_CTRL[TXCLK_DLY]=31

9.95

FSITXn_D1 delay compensation at

TX_DLYLINE_CTRL[TXCLK_DLY]=31

t_{d(TX_D1)}

9.95

Incremental delay of each delay line element

FSIT7

t_{d(TX_DELAY_ELEMENT)}for FSITXn_CLK, FSITXn_D0, and

FSITXn_D1

0.3

Delay skew introduced between

FSIT_TD t_{skew(TX_TDM_CLK-}

FSITXn_TDM_CLK delay and

FSITXn_TDM_D[0:1] delays

2.5

–2.5

TX_TDM_D)

FSIT_TD t_{skew(TX_TDM_CLK-}

Delay time, FSITXn_TDM_CLK input to

FSITXn_CLK output

TX_CLK)

FSIT_TD

Delay time, FSITXn_TDM_D0 input to

FSITXn_D0 output

t_{skew(TX_TDM_D0-TX_D0)}

FSIT_TD

Delay time, FSITXn_TDM_D1 input to

FSITXn_D1 output

t_{skew(TX_TDM_D1-TX_D1)}

(1) P = t_{c(TX_CLK)}= FSITX Interface clock period in ns.

FSIT1

FSIT2

FSI_TXn_CLK

FSI_TXn_D0

FSI_TXn_D1

FSIT3

图7-23. FSI Switching Characteristics - FSI Mode

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FSITX SPI Signaling Mode Switching Characteristics

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

FSIT4

t_{c(TX_CLK)}

Cycle time, FSITXn_CLK

16.67

Pulse width, FSITXn_CLK low or

FSITXn_CLK high

FSIT5

FSIT6

FSIT7

FSIT8

t_{w(TX_CLK)}

0.5P⁽¹⁾+ 1

0.5P⁽¹⁾–1

Delay time, FSITXn_CLK high to FSITXn_D0

valid

t_{d(TX_CLKH–TX_D0)}

t_{d(TX_D1-TX_CLK)}

t_{d(TX_CLK-TX_D1)}

Delay time, FSITXn_D1 low to FSITXn_CLK

high

P⁽¹⁾–3

Delay time, FSITXn_CLK low to FSITXn_D1

high

P⁽¹⁾

(1) P = t_{c(TX_CLK)}= FSITX Interface clock period in ns.

FSIT4

FSIT5

FSI_TXn_CLK

FSI_TXn_D0

FSI_TXn_D1

FSIT6

FSIT8

FSIT7

图7-24. FSI Switching Characteristics - SPI Mode

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7.11.5.6 General Purpose Input/Output (GPIO)

For more details about features and additional description information on the device GPIO, see the

corresponding subsections within Signal Descriptions and Detailed Description sections.

For more information, see General-Purpose Interface (GPIO) section in the device TRM.

GPIO Timing Conditions

PARAMETER

BUFFER TYPE

MIN

MAX

UNIT

INPUT CONDITIONS

SR_I

Input Slew Rate

0.75

6.6

V/ns

OUTPUT CONDITIONS

LVCMOS

I2C OD FS⁽¹⁾

C_L

Output Load Capacitance

(1) A pull-up resistor is required for buffer type I2C OD FS.

GPIO Timing Requirements

NO.

PARAMETER

DESCRIPTION

BUFFER TYPE

MIN

MAX

UNIT

LVCMOS

2P⁽¹⁾+ 2

t_{w(GPIO_IN)}

Minimum Input Pulse Width

I2C OD FS⁽²⁾

(1) P = functional clock period in ns.

(2) A pull-up resistor is required for buffer type I2C OD FS.

GPIO Switching Characteristics

NO.

PARAMETER

t_{w(GPIO_OUT)}

DESCRIPTION

BUFFER TYPE

MIN

MAX UNIT

0.975P⁽¹⁾–2

2P⁽¹⁾+ 160

Minimum Output Pulse Width

Minimum Output Pulse Width Low

Minimum Output Pulse Width High

LVCMOS

I2C OD FS⁽²⁾

(1) P = functional clock period in ns.

(2) A pull-up resistor is required for buffer type I2C OD FS.

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7.11.5.7 General Purpose Memory Controller (GPMC)

For more details about features and additional description information on the device General-Purpose Memory

Controller, see the corresponding subsections within Signal Descriptions and Detailed Description sections.

For more information, see the General-Purpose Memory Controller (GPMC) section in the device TRM.

GPMC Timing Conditions

PARAMETER

MIN

1.65

MAX

UNIT

V/ns

INPUT CONDITIONS

SR_I

Input Slew Rate

OUTPUT CONDITIONS

C_LOutput Load Capacitance

PCB CONNECTIVITY REQUIREMENTS

t_{d(Trace Delay)}Propagation delay of each trace

100MHz

140

720

200

t_{d(Trace Mismatch Delay)}Propagation delay mismatch across all traces

GPMC/NOR Flash Timing Requirements - Synchronous Mode 100MHz

(1) (2)

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

div_by_1_mode

1.81

(4)

Setup time, GPMC0_AD[31:0]

valid before GPMC0_CLK high

F12

F13

F21

F22

t_su(dV-clkH)

not_div_by_1_m

ode⁽⁵⁾

1.06

2.29

1.81

1.06

2.29

div_by_1_mode

(4)

Hold time, GPMC0_AD[31:0] valid

after GPMC0_CLK high

t_h(clkH-dV)

not_div_by_1_m

ode⁽⁵⁾

div_by_1_mode

(4)

Setup time, GPMC0_WAIT[x]⁽³⁾

valid before GPMC0_CLK high

t_{su(waitV-clkH)}

not_div_by_1_m

ode⁽⁵⁾

div_by_1_mode

(4)

Hold time, GPMC0_WAIT[x]⁽³⁾

valid after GPMC0_CLK high

t_{h(clkH-waitV)}

not_div_by_1_m

ode⁽⁵⁾

(1) 100MHz GPMC_FCLK selected - CTRLMMR_GPMC_CLKSEL[0] CLK_SEL = 1 = MAIN_PLL2_HSDIV7_CLKOUT (100/60 MHz).

(2) Trace length from GPMC pins to device assumed to be less than 4" and length matched to within 200ps for 100MHz Synchronous

Mode.

(3) In GPMC_WAIT[x], x is equal to 0 or 1.

(4) In div_by_1_mode, GPMC0_CLK refers to either GPMC0_CLKOUT or GPMC0_FCLK_MUX (free-running). Both signals are pin-

muxed to the same pin.

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:

–GPMC0_CLK frequency = GPMC_FCLK frequency

(5) In not_div_by_1_mode, GPMC_CLK only refers to GPMC0_CLKOUT. GPMC0_FCLK_MUX cannot be clock divided to match the

GPMC0_CLKOUT frequency if GPMCFCLKDIVIDER > 0.

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:

–GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4)

GPMC/NOR Flash Switching Charcteristics - Synchronous Mode 100MHz

(18) (19)

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

Clock period, GPMC0_CLK,

GPMC0_FCLK_MUX

t_c(clk)

10⁽²⁰⁾

0.475P⁽¹⁶⁾

–

Typical pulse duration, GPMC0_CLK high or

low

t_w(clk)

0.3⁽²⁰⁾

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(18) (19)

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

Delay time, GPMC0_CLK rising edge to

GPMC0_CSn[x]⁽¹⁵⁾transition

t_d(clkH-csnV)

F⁽⁶⁾+3.75

F⁽⁶⁾–2.2⁽²⁰⁾

Delay time, GPMC0_CLK rising edge to

GPMC0_CSn[x]⁽¹⁵⁾invalid

t_{d(clkH-csnIV)}

t_d(aV-clk)

E⁽⁵⁾+3.18

B⁽²⁾+ 4.5

4.5

E⁽⁵⁾–2.2

B⁽²⁾–2.3⁽²⁰⁾

–2.3⁽²⁰⁾

Delay time, GPMC0_A[27:1] valid to

GPMC0_CLK first edge

Delay time, GPMC0_CLK rising edge to

GPMC0_A[27:1] invalid

t_d(clkH-aIV)

Delay time, GPMC0_BE0n_CLE,

GPMC0_BE1n valid to GPMC0_CLK first

edge

B⁽²⁾–2.3⁽²⁰⁾

D⁽⁴⁾–2.3⁽²⁰⁾

t_{d(be[x]nV-clk)}

B⁽²⁾+ 1.9

D⁽⁴⁾+ 1.9

Delay time, GPMC0_CLK rising edge to

t_{d(clkH-be[x]nIV)}GPMC0_BE0n_CLE, GPMC0_BE1n

invalid⁽¹²⁾

Delay time, GPMC0_CLK falling edge to

t_{d(clkL-be[x]nIV)}GPMC0_BE0n_CLE, GPMC0_BE1n

invalid⁽¹³⁾

Delay time, GPMC0_CLK falling edge to

t_{d(clkL-be[x]nIV)}GPMC0_BE0n_CLE, GPMC0_BE1n

invalid⁽¹⁴⁾

G^{(7) (8)}

–

2.3⁽²⁰⁾

Delay time, GPMC0_CLK rising edge to

t_d(clkH-advn)

G^{(7) (8)}+ 4.5

D⁽⁴⁾+ 4.5

H⁽⁹⁾+ 3.5

I⁽¹⁰⁾+ 4.5

J⁽¹¹⁾+ 2.7

J⁽¹¹⁾+ 1.9

GPMC0_ADVn_ALE transition

Delay time, GPMC0_CLK rising edge to

t_{d(clkH-advnIV)}

D⁽⁴⁾–2.3⁽²⁰⁾

GPMC0_ADVn_ALE invalid

Delay time, GPMC0_CLK rising edge to

t_d(clkH-oen)

H⁽⁹⁾–2.3⁽²⁰⁾

I⁽¹⁰⁾–2.3⁽²⁰⁾

J⁽¹¹⁾–2.3⁽²⁰⁾

F10

F11

F14

F15

F17

GPMC0_OEn_REn transition

Delay time, GPMC0_CLK rising edge to

t_{d(clkH-oenIV)}

GPMC0_OEn_REn invalid

Delay time, GPMC0_CLK rising edge to

t_d(clkH-wen)

GPMC0_WEn transition

Delay time, GPMC0_CLK rising edge to

t_d(clkH-do)

GPMC0_AD[31:0] transition⁽¹²⁾

Delay time, GPMC0_CLK falling edge to

t_d(clkL-do)

GPMC0_AD[31:0] data bus transition⁽¹³⁾

Delay time, GPMC0_CLK falling edge to

t_d(clkL-do)

GPMC0_AD[31:0] data bus transition⁽¹⁴⁾

Delay time, GPMC0_CLK rising edge to

t_{d(clkH-be[x]n)}

GPMC0_BE0n_CLE transition⁽¹²⁾

Delay time, GPMC0_CLK falling edge to

F17

t_{d(clkL-be[x]n)}

GPMC0_BE0n_CLE, GPMC0_BE1n

J⁽¹¹⁾+ 1.9

J⁽¹¹⁾–2.3⁽²⁰⁾

transition⁽¹³⁾

Delay time, GPMC0_CLK falling edge to

GPMC0_BE0n_CLE, GPMC0_BE1n

transition⁽¹⁴⁾

J⁽¹¹⁾–2.3⁽²⁰⁾

t_{d(clkL-be[x]n)}

Read

A⁽¹⁾

F18

F19

t_w(csnV)

Pulse duration, GPMC0_CSn[x]⁽¹⁵⁾low

Write

Read

Write

Read

Write

C⁽³⁾

Pulse duration, GPMC0_BE0n_CLE,

GPMC0_BE1n low

t_w(be[x]nV)

C⁽³⁾

K⁽¹⁷⁾

F20

(1)

t_w(advnV)

Pulse duration, GPMC0_ADVn_ALE low

For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)

For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)

For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)

With n being the page burst access number.

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(2) B = ClkActivationTime × GPMC_FCLK(17)

(3) For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(17)

For burst read: C = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)

For burst write: C = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)

With n being the page burst access number.

(4) For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)

For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)

For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)

(5) For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)

For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)

For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)

(6) For csn falling edge (CS activated):

–Case GpmcFCLKDivider = 0:

–F = 0.5 × CSExtraDelay × GPMC_FCLK(17)

–Case GpmcFCLKDivider = 1:

–F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime

are even)

–F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) otherwise

–Case GpmcFCLKDivider = 2:

–F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime) is a multiple of 3)

–F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)

–F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)

(7) For ADV falling edge (ADV activated):

–Case GpmcFCLKDivider = 0:

–G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)

–Case GpmcFCLKDivider = 1:

–G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and

ADVOnTime are even)

–G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise

–Case GpmcFCLKDivider = 2:

–G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime) is a multiple of 3)

–G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)

–G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Reading mode:

–Case GpmcFCLKDivider = 0:

–G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)

–Case GpmcFCLKDivider = 1:

–G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and

ADVRdOffTime are even)

–G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise

–Case GpmcFCLKDivider = 2:

–G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)

–G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)

–G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)

(8) For ADV rising edge (ADV deactivated) in Writing mode:

–Case GpmcFCLKDivider = 0:

–G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)

–Case GpmcFCLKDivider = 1:

–G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and

ADVWrOffTime are even)

–G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise

–Case GpmcFCLKDivider = 2:

–G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)

–G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)

–G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)

(9) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):

–Case GpmcFCLKDivider = 0:

–H = 0.5 × OEExtraDelay × GPMC_FCLK(17)

–Case GpmcFCLKDivider = 1:

–H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime

are even)

–H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise

–Case GpmcFCLKDivider = 2:

–H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime) is a multiple of 3)

–H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)

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–H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)

For OE rising edge (OE deactivated):

–Case GpmcFCLKDivider = 0:

–H = 0.5 × OEExtraDelay × GPMC_FCLK(17)

–Case GpmcFCLKDivider = 1:

–H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime

are even)

–H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise

–Case GpmcFCLKDivider = 2:

–H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime) is a multiple of 3)

–H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)

–H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)

(10) For WE falling edge (WE activated):

–Case GpmcFCLKDivider = 0:

–I = 0.5 × WEExtraDelay × GPMC_FCLK(17)

–Case GpmcFCLKDivider = 1:

–I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime

are even)

–I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise

–Case GpmcFCLKDivider = 2:

–I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime) is a multiple of 3)

–I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)

–I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)

For WE rising edge (WE deactivated):

–Case GpmcFCLKDivider = 0:

–I = 0.5 × WEExtraDelay × GPMC_FCLK (17)

–Case GpmcFCLKDivider = 1:

–I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime

are even)

–I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise

–Case GpmcFCLKDivider = 2:

–I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime) is a multiple of 3)

–I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)

–I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)

(11) J = GPMC_FCLK(17)

(12) First transfer only for CLK DIV 1 mode.

(13) Half cycle; for all data after initial transfer for CLK DIV 1 mode.

(14) Half cycle of GPMC_CLK_OUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLK_OUT divide down from GPMC_FCLK.

(15) In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.

(16) P = GPMC_CLK period in ns

(17) For read: K = (ADVRdOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)

For write: K = (ADVWrOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)

(18) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

(19) 100MHz GPMC_FCLK selected - CTRLMMR_GPMC_CLKSEL[0] CLK_SEL = 1 = MAIN_PLL2_HSDIV7_CLKOUT (100/60 MHz)

(20) In div_by_1_mode, GPMC0_CLK refers to either GPMC0_CLKOUT or GPMC0_FCLK_MUX (free-running). Both signals are pin-

muxed to the same pin

–GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:

–GPMC0_CLK frequency = GPMC_FCLK frequency

In not_div_by_1_mode, GPMC0_CLK only refers to GPMC0_CLKOUT. GPMC0_FCLK_MUX cannot be clock divided to match the

GPMC0_CLKOUT frequency if GPMCFCLKDIVIDER > 0

–GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:

–GPMC0_CLK frequency = GPMC_FCLK frequency / (2 to 4)

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GPMC_CLK

F18

GPMC_CSn[i]

GPMC_A[MSB:1]

Valid Address

F19

GPMC_BE0n_CLE

GPMC_BE1n

F19

F20

GPMC_ADVn_ALE

GPMC_OEn_REn

F10

F11

F13

F12

D 0

GPMC_AD[15:0]

GPMC_WAIT[j]

GPMC_01

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

B. In GPMC_WAIT[j], j is equal to 0 or 1.

图7-25. GPMC and NOR Flash —Synchronous Single Read (GPMCFCLKDIVIDER = 0)

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GPMC_CLK

GPMC_CSn[i]

GPMCA[MSB:1]

Valid Address

GPMC_BE0n_CLE

GPMC_BE1n

GPMC_ADVn_ALE

GPMC_OEn_REn

F10

F11

F13

F12

D 0

F22

GPMC_AD[15:0]

GPMC_WAIT[j]

D 1

D 2

D 3

F21

GPMC_02

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

B. In GPMC_WAIT[j], j is equal to 0 or 1.

图7-26. GPMC and NOR Flash —Synchronous Burst Read —4x16–bit (GPMCFCLKDIVIDER = 0)

GPMC_CLK

GPMC_CSn[i]

Valid Address

GPMC_A[MSB:1]

F17

GPMC_BE0n_CLE

GPMC_BE1n

GPMC_ADVn_ALE

GPMC_WEn

F14

F15

D 1

F15

D 2

F15

GPMC_AD[15:0]

GPMC_WAIT[j]

D 0

D 3

GPMC_03

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

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B. In GPMC_WAIT[j], j is equal to 0 or 1.

图7-27. GPMC and NOR Flash—Synchronous Burst Write (GPMCFCLKDIVIDER = 0)

GPMC_CLK

GPMC_CSn[i]

GMPC_BE0n_CLE

Valid

GPMC_BE1n

GPMC_A[27:17]

Address (MSB)

F12

F13

F12

GPMC_AD[15:0]

Address (LSB)

GPMC_ADVn_ALE

F10

F11

GPMC_OEn_REn

GPMC_WAIT[j]

GPMC_04

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

B. In GPMC_WAIT[j], j is equal to 0 or 1.

图7-28. GPMC and Multiplexed NOR Flash —Synchronous Burst Read

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GPMC_CLK

F18

GPMC_CSn[i]

GPMC_A[27:17]

Address (MSB)

F17

GPMC_BE1n

BPMC_BE0n_CLE

F20

GPMC_ADVn_ALE

F14

GPMC_WEn

F15

D 1

F15

D 2

F15

GPMC_AD[15:0]

Address (LSB)

D 0

D 3

F22

F21

GPMC_WAIT[j]

GPMC_05

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

B. In GPMC_WAIT[j], j is equal to 0 or 1.

图7-29. GPMC and Multiplexed NOR Flash —Synchronous Burst Write

GPMC/NOR Flash Timing Requirements - Asynchronous Mode 100MHz

(6)

NO.

PARAMETER

t_acc(d)

DESCRIPTION

Data access time

MIN

MAX

UNIT

FA5⁽¹⁾

H⁽⁵⁾

Page mode successive data access

time

FA20⁽²⁾

FA21⁽³⁾

t_{acc1-pgmode(d)}

t_{acc2-pgmode(d)}

P⁽⁴⁾

H⁽⁵⁾

Page mode first data access time

(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active

functional clock edge. FA5 value must be stored inside the AccessTime register bit field.

(2) The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of

GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional

clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.

(3) The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by

active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.

(4) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6)

(5) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6)

(6) 133MHz GPMC_FCLK selected - CTRLMMR_GPMC_CLKSEL[0] CLK_SEL = 0 = MAIN_PLL0_HSDIV3_CLKOUT (133/100/80 MHz)

GPMC/NOR Flash Switching Charcteristics - Asynchronous Mode 100MHz

(14)

NO.

PARAMETER

DESCRIPTION

MODE

Read

Write

MIN

MAX

N⁽¹²⁾

UNIT

Pulse duration, GPMC0_BE0n_CLE,

GPMC0_BE1n valid time

FA0

t_w(be[x]nV)

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(14)

NO.

PARAMETER

DESCRIPTION

MODE

Read

MIN

MAX

A⁽¹⁾

UNIT

FA1

FA3

t_w(csnV)

Pulse duration, GPMC0_CSn[x]⁽¹³⁾low

Write

Read

Write

A⁽¹⁾

B⁽²⁾+ 2

B⁽²⁾–2

Delay time, GPMC0_CSn[x]⁽¹³⁾valid to

GPMC0_ADVn_ALE invalid

t_{d(csnV-advnIV)}

Delay time, GPMC0_CSn[x]⁽¹³⁾valid to

GPMC0_OEn_REn invalid (Single read)

C⁽³⁾–2

J⁽⁹⁾–2

FA4

FA9

t_{d(csnV-oenIV)}

t_d(aV-csnV)

C⁽³⁾+ 2

J⁽⁹⁾+ 2

Delay time, GPMC0_A[27:1] valid to

GPMC0_CSn[x]⁽¹³⁾valid

Delay time, GPMC0_BE0n_CLE,

FA10

t_{d(be[x]nV-csnV)}GPMC0_BE1n valid to GPMC0_CSn[x]⁽¹³⁾

valid

J⁽⁹⁾+ 2

J⁽⁹⁾–2

Delay time, GPMC0_CSn[x]⁽¹³⁾valid to

t_{d(csnV-advnV)}

K⁽¹⁰⁾–2

L⁽¹¹⁾–2

FA12

FA13

K⁽¹⁰⁾+ 2

L⁽¹¹⁾+ 2

GPMC0_ADVn_ALE valid

Delay time, GPMC0_CSn[x]⁽¹³⁾valid to

t_d(csnV-oenV)

GPMC0_OEn_REn valid

Pulse durationm GPMC0_A[26:1] invalid

between two successive read and write

accesses

FA16

t_w(alV)

G⁽⁷⁾

Delay time, GPMC0_CSn[x]⁽¹³⁾valid to

GPMC0_OEn_REn invalid (Burst read)

FA18

FA20

FA25

FA27

FA28

FA29

FA37

t_{d(csnV-oenIV)}

t_w(av)

I⁽⁸⁾+ 2

I⁽⁸⁾–2

D⁽⁴⁾

Pulse duration, GPMC0_A[27:1] valid - 2nd,

3rd, and 4th accesses

Delay time, GPMC0_CSn[x]⁽¹³⁾valid to

GPMC0_WEn valid

t_{d(csnV-wenIV)}

t_d(wenV-dV)

t_d(dV-csnV)

t_d(oenV-aIV)

E⁽⁵⁾+ 2

F⁽⁶⁾+ 2

E⁽⁵⁾–2

F⁽⁶⁾–2

Delay time, GPMC0_CSn[x]⁽¹³⁾valid to

GPMC0_WEn invalid

Delay time, GPMC0_WEn valid to

GPMC0_AD[31:0] valid

Delay time, GPMC0_AD[31:0] valid to

GPMC0_CSn[x]⁽¹³⁾valid

J⁽¹⁰⁾+ 2

J⁽⁹⁾–2

Delay time, GPMC0_OEn_REn valid to

GPMC0_AD[31:0] phase end

(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

with n being the page burst access number

(2) For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×

GPMC_FCLK(14)

For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×

GPMC_FCLK(14)

(3) C = \((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay\)) × GPMC_FCLK(14)

(4) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)

(5) E = \((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay\)) × GPMC_FCLK(14)

(6) F = \((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay\)) × GPMC_FCLK(14)

(7) G = Cycle2CycleDelay × GPMC_FCLK(14)

(8) I = \((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay\))

× GPMC_FCLK(14)

(9) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK(14)

(10) K = \((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay\)) × GPMC_FCLK(14)

(11) L = \((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay\)) × GPMC_FCLK(14)

(12) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)

For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)

For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

(13) In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.

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(14) 133MHz GPMC_FCLK selected - CTRLMMR_GPMC_CLKSEL[0] CLK_SEL = 0 = MAIN_PLL0_HSDIV3_CLKOUT (133/100/80 MHz)

GPMC_FCLK

GPMC_CLK

FA5

FA1

GPMC_CSn[i]

FA9

GPMC_A[MSB:1]

Valid Address

FA0

FA10

Valid

FA0

GPMC_BE0n_CLE

GPMC_BE1n

Valid

FA3

FA12

GPMC_ADVn_ALE

FA4

FA13

GPMC_OEn_REn

GPMC_AD[15:0]

Data IN 0

GPMC_WAIT[j]

GPMC_06

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock

cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock

edge. FA5 value must be stored inside AccessTime register bits field.

C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

图7-30. GPMC and NOR Flash —Asynchronous Read —Single Word

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GPMC_FCLK

GPMC_CLK

GPMC_CSn[i]

FA5

FA1

FA16

FA9

Address 0

FA0

Address 1

FA0

GPMC_A[MSB:1]

FA10

Valid

FA0

Valid

FA0

GPMC_BE0n_CLE

GPMC_BE1n

Valid

FA10

FA3

FA12

GPMC_ADCn_ALE

FA4

FA13

GPMC_OEn_REn

GPMC_AD[15:0]

Data Upper

GPMC_WAIT[j]

GPMC_07

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock

cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock

edge. FA5 value must be stored inside AccessTime register bits field.

C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

图7-31. GPMC and NOR Flash —Asynchronous Read —32–Bit

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GPMC_FCLK

GPMC_CLK

FA20

Add3

FA20

Add1

FA21

FA20

Add2

FA1

GPMC_CSn[i]

FA9

Add0

Add4

GPMC_A[MSB:1]

GPMC_BE0n_CLE

FA0

FA10

FA0

GPMC_BE1n

FA12

GPMC_ADVn_ALE

FA18

FA13

GPMC_OEn_REn

GPMC_AD[15:0]

GPMC_WAIT[j]

GPMC_08

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

B. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data will be internally sampled by

active functional clock edge. FA21 calculation must be stored inside AccessTime register bits field.

C. FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC

functional clock cycles. After each access to input page data, next input page data will be internally sampled by active functional clock

edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first

input page data). FA20 value must be stored in PageBurstAccessTime register bits field.

D. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

图7-32. GPMC and NOR Flash —Asynchronous Read —Page Mode 4x16–Bit

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GPMC_FCLK

GPMC_CLK

FA1

GPMC_CSn[i]

FA9

GPMC_A[MSB:1]

GPMC_BE0n_CLE

GPMC_BE1n

Valid Address

FA0

FA10

FA0

FA3

FA12

GPMC_ADVn_ALE

FA27

FA25

GPMC_WEn

GPMC_AD[15:0]

GPMC_WAIT[j]

FA29

Data OUT

GPMC_09

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

图7-33. GPMC and NOR Flash —Asynchronous Write —Single Word

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GPMC_FCLK

GPMC_CLK

FA1

FA5

GPMC_CSn[i]

FA9

Address (MSB)

FA0

GPMC_A[27:17]

GPMC_BE0n_CLE

GPMC_BE1n

FA10

Valid

FA0

Valid

FA3

FA12

GPMC_ADVn_ALE

GPMC_OEn_REn

FA4

FA13

FA29

FA37

Data IN

Address (LSB)

GPMC_AD[15:0]

GPMC_WAIT[j]

GPMC_10

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock

cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock

edge. FA5 value must be stored inside AccessTime register bits field.

C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

图7-34. GPMC and Multiplexed NOR Flash —Asynchronous Read —Single Word

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GPMC_FCLK

GPMC_CLK

GPMC_CSn[i]

FA1

FA9

GPMC_A[27:17]

Address (MSB)

FA0

FA10

GPMC_BE0n_CLE

GPMC_BE1n

FA0

FA3

FA12

GPMC_ADVn_ALE

FA27

FA25

GPMC_WEn

FA29

FA28

GPMC_AD[15:0]

Valid Address (LSB)

Data OUT

GPMC_WAIT[j]

GPMC_11

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

图7-35. GPMC and Multiplexed NOR Flash —Asynchronous Write —Single Word

GPMC/NAND Flash Timing Requirements - Asynchronous Mode 100MHz

(4)

NO.

GNF12⁽¹⁾

PARAMETER

t_acc(d)

DESCRIPTION

MIN

MAX

UNIT

Access time, GPMC0_AD[31:0]⁽³⁾

J⁽²⁾

(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC

functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the

active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.

(2) J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3)

(3) GPMC_FCLK is general-purpose memory controller internal functional clock.

(4) 133MHz GPMC_FCLK selected - CTRLMMR_GPMC_CLKSEL[0] CLK_SEL = 0 = MAIN_PLL0_HSDIV3_CLKOUT (133/100/80 MHz)

GPMC/NAND Flash Switching Charcteristics - Asynchronous Mode 100MHz

(14)

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

GNF0

GNF1

t_w(wenV)

Pulse duration, GPMC0_WEn valid

A⁽¹⁾

Delay time, GPMC0_CSn[x]⁽¹³⁾valid to

GPMC0_WEn valid

t_d(csnV-wenV)

t_w(cleH-wenV)

t_w(wenV-dV)

B⁽²⁾+ 2

C⁽³⁾+ 2

D⁽⁴⁾+ 2

E⁽⁵⁾+ 2

F⁽⁶⁾+ 2

B⁽²⁾–2

C⁽³⁾–2

D⁽⁴⁾–2

E⁽⁵⁾–2

F⁽⁶⁾–2

Delay time, GPMC0_BE0n_CLE high to

GPMC0_WEn valid

GNF2

GNF3

GNF4

GNF5

Delay time, GPMC0_AD[31:0] valid to

GPMC0_WEn valid

Delay time, GPMC0_WEn invalid to

GPMC0_AD[31:0] invalid

t_w(wenIV-dIV)

t_{w(wenIV-cleIV)}

Delay time, GPMC0_WEn invalid to

GPMC0_BE0n_CLE invalid

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(14)

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

Delay time, GPMC0_WEn invalid to

GPMC0_CSn[x]⁽¹³⁾invalid

GNF6

GNF7

t_{w(wenIV-csnIV)}

G⁽⁷⁾+ 2

G⁽⁷⁾–2

Delay time, GPMC0_ADVn_ALE high to

GPMC0_WEn valid

t_w(aleH-wenV)

C⁽³⁾+ 2

C⁽³⁾–2

F⁽⁶⁾–2

Delay time, GPMC0_WEn invalid to

GPMC0_ADVn_ALE invalid

GNF8

GNF9

t_{w(wenIV-aleIV)}

t_c(wen)

F⁽⁶⁾+ 2

H⁽⁸⁾

Cycle time, write

Delay time, GPMC0_CSn[x]⁽¹³⁾valid to

GPMC0_OEn_REn valid

GNF10

t_d(csnV-oenV)

I⁽⁹⁾+ 2

K⁽¹⁰⁾

I⁽⁹⁾–2

GNF13

GNF14

t_w(oenV)

t_c(oen)

Pulse duration, GPMC0_OEn_REn valid

Cycle time, read

L⁽¹¹⁾

Delay time, GPMC0_OEn_REn invalid to

GPMC0_CSn[x]⁽¹³⁾invalid

M⁽¹²⁾–2

GNF15

t_{w(oenIV-csnIV)}

M⁽¹²⁾+ 2

(1) A = (WEOffTime - WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

(2) B = \((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay\)) × GPMC_FCLK(14)

(3) C = \((WEOnTime - ADVOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - ADVExtraDelay\)) × GPMC_FCLK(14)

(4) D = (WEOnTime × (TimeParaGranularity + 1) + 0.5 × WEExtraDelay) × GPMC_FCLK(14)

(5) E = \((WrCycleTime - WEOffTime) × (TimeParaGranularity + 1) - 0.5 × WEExtraDelay) × GPMC_FCLK(14)

(6) F = \((ADVWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - WEExtraDelay\)) × GPMC_FCLK(14)

(7) G = \((CSWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - WEExtraDelay\)) × GPMC_FCLK(14)

(8) H = WrCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14)

(9) I = \((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay\)) × GPMC_FCLK(14)

(10) K = (OEOffTime - OEOnTime) × (1 + TimeParaGranularity) × GPMC_FCLK(14)

(11) L = RdCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14)

(12) M = \((CSRdOffTime - OEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - OEExtraDelay\)) × GPMC_FCLK(14)

(13) In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.

(14) 133MHz GPMC_FCLK selected - CTRLMMR_GPMC_CLKSEL[0] CLK_SEL = 0 = MAIN_PLL0_HSDIV3_CLKOUT (133/100/80 MHz)

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GPMC_FCLK

GNF1

GNF6

GNF5

GPMC_CSn[i]

GNF2

GPMC_BE0n_CLE

GPMC_ADCn_ALE

GPMC_OEn_REn

GPMC_WEn

GNF0

GNF3

GNF4

GPMC_AD[15:0]

Command

GPMC_12

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

图7-36. GPMC and NAND Flash —Command Latch Cycle

GPMC_FCLK

GPMC_CSn[i]

GNF1

GNF6

GPMC_BE0n_CLE

GPMC_ADVn_ALE

GNF7

GNF8

GPMC_OEn_REn

GPMC_WEn

GNF9

GNF0

GNF3

GNF4

Address

GPMC_AD[15:0]

GPMC_13

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

图7-37. GPMC and NAND Flash —Address Latch Cycle

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GPMC_FCLK

GNF12

GNF10

GNF15

GPMC_CSn[i]

GPMC_BE0n_CLE

GPMC_ADVn_ALE

GNF14

GNF13

GPMC_OEn_REn

GPMC_AD[15:0]

GPMC_WAIT[j]

DATA

GPMC_14

A. GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional

clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional

clock edge. GNF12 value must be stored inside AccessTime register bits field.

B. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

C. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

图7-38. GPMC and NAND Flash —Data Read Cycle

GPMC_FCLK

GNF1

GNF6

GPMC_CSn[i]

GPMC_BE0n_CLE

GPMC_ADVn_ALE

GPMC_OEn_REn

GNF9

GNF0

GPMC_WEn

GNF3

GNF4

GPMC_AD[15:0]

DATA

GPMC_15

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

图7-39. GPMC and NAND Flash —Data Write Cycle

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7.11.5.8 Inter-Integrated Circuit (I²C)

For more details about features and additional description information on the device Inter-Integrated Circuit, see

the corresponding subsections within Signal Descriptions and Detailed Description sections.

For more information, see the Inter-Integrated Circuit (I2C) section in the device TRM.

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7.11.5.8.1 I2C

The device contains four multicontroller Inter-Integrated Circuit (I2C) controllers. Each I2C controller was

designed to be compliant to the Philips I²C-bus™ specification version 2.1. However, the device IOs are not fully

compliant to the I2C electrical specification. The speeds supported and exceptions are described per port below:

• I2C1, I2C2, and I2C3

– Speeds:

• Standard-mode (up to 100 Kbits/s)

– 3.3 V

• Fast-mode (up to 400 Kbits/s)

– 3.3 V

– Exceptions:

• The IOs associated with these ports are not compliant to the fall time requirements defined in the I2C

specification because they are implemented with higher performance LVCMOS push-pull IOs that were

designed to support other signal functions that could not be implemented with I2C compatible IOs. The

LVCMOS IOs being used on these ports are connected such they emulate open-drain outputs. This

emulation is achieved by forcing a constant low output and disabling the output buffer to enter the Hi-Z

state.

• The I2C specification defines a maximum input voltage V_IHof (V_DD+ 0.5 V), which exceeds the

absolute maximum ratings for the device IOs. The system must be^md^ae^xsigned to ensure the I2C signals

never exceed the limits defined in the Absolute Maximum Ratings section of this datasheet.

• I2C0

– Speeds:

• Standard-mode (up to 100 Kbits/s)

– 3.3 V

• Fast-mode (up to 400 Kbits/s)

– 3.3 V

– Exceptions:

• The IOs associated with this port were not design to support Hs-mode.

• The rise and fall times of the I2C signals connected to these ports must not exceed a slew rate of 0.8

V/ns (or 8E+7 V/s). This limit is more restrictive than the minimum fall time limits defined in the I2C

specification. Therefore, it may be necessary to add additional capacitance to the I2C signals to slow

the rise and fall times such that they do not exceed a slew rate of 0.8 V/ns.

• The I2C specification defines a maximum input voltage V_IHof (V_DD+ 0.5 V), which exceeds the

absolute maximum ratings for the device IOs. The system must be^md^ae^xsigned to ensure the I2C signals

never exceed the limits defined in the Absolute Maximum Ratings section of this datasheet.

Refer to the Philips I2C-bus specification version 2.1 for timing details.

For more details about features and additional description information on the device Inter-Integrated Circuit, see

the corresponding subsections within Signal Descriptions and Detailed Description sections.

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7.11.5.9 Local Interconnect Network (LIN)

备注

The device has multiple LIN modules. LINn is a generic prefix applied to LIN signal names, where n

represents the specific LIN module.

For more information, see the Local Interconnect Network (LIN) Module section in the device TRM.

LIN Timing Conditions

PARAMETER

MIN

MAX

UNIT

V/ns

INPUT CONDITIONS

SR_I

Input Slew Rate

OUTPUT CONDITIONS

C_L

Output Load Capacitance

LIN Timing Requirements

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

Delay time, LINn_RX shift register to

LINn_RX pin

LIN2

t_{d(LINn_RX)}

LIN Switching Charcteristics

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

LIN4

t_{d(LINn_TX)}

Delay time, LINn_TX shift register to LINn_TX pin

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7.11.5.10 Modular Controller Area Network (MCAN)

For more details about features and additional description information on the device Controller Area Network

Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.

备注

The device has multiple MCAN modules. MCANn is a generic prefix applied to MCAN signal names,

where n represents the specific MCAN module.

For more information, see Controller Area Network (MCAN) section in the device TRM.

MCAN Timing Conditions

PARAMETER

MIN

MAX

UNIT

V/ns

INPUT CONDITIONS

SR_I

Input Slew Rate

OUTPUT CONDITIONS

C_L

Output Load Capacitance

MCAN Switching Characteristics

NO.

PARAMETER

t_{d(MCAN_TX)}

t_{d(MCAN_RX)}

DESCRIPTION

MIN

MAX

UNIT

Delay time, transmit shift register to MCANn_TX

Delay time, MCANn_RX pin to receive shift

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7.11.5.11 Serial Peripheral Interface (SPI)

For more details about features and additional description information on the device Serial Port Interface, see

the corresponding subsections within Signal Descriptions and Detailed Description sections.

备注

The device has multiple SPI modules. The generic SPI_ prefix is used to represent the signal names

for all SPI instances.

For more information, see the Serial Peripheral Interface (SPI) section in the device TRM.

SPI Timing Conditions

PARAMETER

MIN

MAX

8.5

UNIT

V/ns

INPUT CONDITIONS

SR_I

Input Slew Rate

OUTPUT CONDITIONS

C_L

Output Load Capacitance

SPI Controller Mode Timing Requirements

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

Normal Mode

Setup time, spi_d[x] valid before spi_sclk active

edge

SM4

SM5

t_{su(MISO-SPICLK)}

t_{h(SPICLK-MISO)}

Hold time, spi_d[x] valid after spi_sclk active

edge

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PHA=0

EPOL=1

SPI_CS[i] (OUT)

SM1

SM3

SM8

SM2

SM9

POL=0

POL=1

SPI_SCLK (OUT)

SM1

SM3

SM2

SPI_SCLK (OUT)

SM5

SM4

Bit n-1

Bit n-2

Bit n-3

Bit n-4

Bit 0

SPI_D[x] (IN)

PHA=1

EPOL=1

SPI_CS[i] (OUT)

SPI_SCLK (OUT)

SM2

SM1

SM8

SM3

SM2

SM9

POL=0

POL=1

SM1

SM3

SPI_SCLK (OUT)

SM5

SM4

SM5

Bit n-2

SM4

Bit n-1

Bit n-3

Bit 1

Bit 0

SPI_D[x] (IN)

SPRSP08_TIMING_McSPI_02

图7-40. SPI Controller Mode Receive Timing

SPI Controller Mode Switching Characteristics (Clock Phase = 0)

NO.

Normal Mode

SM1

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

t_c(SPICLK)

Cycle time, spi_sclk

Typical Pulse duration, spi_sclk

low

–1 + 0.5P⁽¹⁾

SM2

SM3

SM6

SM7

t_w(SPICLKL)

Typical Pulse duration, spi_sclk

high

–1 + 0.5P⁽¹⁾

t_w(SPICLKH)

t_{d(SPICLK-SIMO)}

t_sk(CS-SIMO)

Delay time, spi_sclk active

edge to spi_d[x] transition

–3

Delay time, spi_cs[x] active to

spi_d[x] transition

–4 + B⁽³⁾

–4 + A⁽²⁾

PHA = 0

PHA = 1

Delay time, spi_cs[x] active to

spi_sclk first edge

SM8

t_d(SPICLK-CS)

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NO.

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PARAMETER

t_d(SPICLK-CS)

DESCRIPTION

MIN

–4 + A⁽²⁾

–4 + B⁽³⁾

MAX

UNIT

PHA = 0

PHA = 1

Delay time, spi_sclk last edge

to spi_cs[x] inactive

SM9

(1) P = SPICLK period in ns.

(2) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A =

(TCS + 0.5) * Fratio * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.

(3) B = (TCS + .5) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even >= 2.

PHA=0

EPOL=1

SPI_CS[i] (OUT)

SM1

SM3

SM8

SM2

SM9

POL=0

POL=1

SPI_SCLK (OUT)

SM1

SM3

SM2

SPI_SCLK (OUT)

SPI_D[x] (OUT)

SM7

Bit n-1

SM6

Bit n-2

SM6

Bit n-3

Bit n-4

Bit 0

PHA=1

EPOL=1

SPI_CS[i] (OUT)

SPI_SCLK (OUT)

SM1

SM2

SM8

SM3

SM2

SM9

POL=0

POL=1

SM1

SM3

SPI_SCLK (OUT)

SPI_D[x] (OUT)

SM6

Bit n-1

SM6

Bit n-2

SM6

Bit n-3

SM6

Bit 1

Bit0

SPRSP08_TIMING_McSPI_01

图7-41. SPI Controller Mode Transmit Timing

SPI Peripheral Mode Timing Requirements

NO.

PARAMETER

t_c(SPICLK)

t_w(SPICLKL)

t_w(SPICLKH)

DESCRIPTION

MIN

MAX

UNIT

SS1

SS2

SS3

Cycle time, spi_sclk

Typical Pulse duration, spi_sclk low

Typical Pulse duration, spi_sclk high

18.45 × P⁽¹⁾

Setup time, spi_d[x] valid before spi_sclk active

edge

SS4

SS5

t_{su(SIMO-SPICLK)}

Hold time, spi_d[x] valid after spi_sclk active

edge

th(SPICLK-SIMO)

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NO.

PARAMETER

t_{su(CS-SPICLK)}

t_h(SPICLK-CS)

DESCRIPTION

MIN

MAX

UNIT

Setup time, spi_cs[x] valid before spi_sclk first

edge

SS8

SS9

Hold time, spi_cs[x] valid after spi_sclk last edge

(1) P = SPICLK period.

PHA=0

EPOL=1

SPI_CS[i] (IN)

SS1

SS2

SS8

SS3

SS9

POL=0

SPI_SCLK (IN)

SS1

SS2

POL=1

SPI_SCLK (IN)

SS5

SS4

SS5

Bit n-2

SS4

Bit n-1

Bit n-3

Bit n-4

Bit 0

SPI_D[x] (IN)

PHA=1

EPOL=1

SPI_CS[i] (IN)

SS1

SS2

SS8

SS3

SS2

SS9

POL=0

SPI_SCLK (IN)

SS1

SS3

POL=1

SPI_SCLK (IN)

SS4

SS5

SS4

SS5

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit 0

SPI_D[x] (IN)

SPRSP08_TIMING_McSPI_04

图7-42. SPI Peripheral Mode Receive Timing

SPI Peripheral Mode Switching Characteristics

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

Normal Mode

Delay time, spi_sclk active edge to

mcspi_somi transition

SS6

SS7

t_{d(SPICLK-SOMI)}

t_sk(CS-SOMI)

17.12

Delay time, spi_cs[x] active edge to

mcspi_somi transition

20.95

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PHA=0

EPOL=1

SPI_CS[i] (IN)

SPI_SCLK (IN)

SS1

SS2

SS8

SS3

SS9

POL=0

POL=1

SS1

SS2

SPI_SCLK (IN)

SPI_D[x] (OUT)

SS7

Bit n-1

SS6

Bit n-2

SS6

Bit n-3

Bit n-4

Bit 0

PHA=1

EPOL=1

SPI_CS[i] (IN)

SPI_SCLK (IN)

SS1

SS2

SS8

SS3

SS2

SS9

POL=0

POL=1

SS1

SS3

SPI_SCLK (IN)

SPI_D[x] (OUT)

SS6

Bit n-1

SS6

Bit n-2

SS6

Bit n-3

SS6

Bit 1

Bit 0

SPRSP08_TIMING_McSPI_03

图7-43. SPI Peripheral Mode Transmit Timing

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7.11.5.12 Multi-Media Card/Secure Digital (MMCSD)

The MMCSD Host Controller provides an interface to embedded Multi-Media Card (MMC) and Secure Digital

(SD)devices. The MMCSD Host Controller deals with MMC/SD protocol at transmission level, data packing,

adding cyclic redundancy checks (CRCs), start/end bit insertion, and checking for syntactical correctness.

For more details about MMCSD interfaces, see the corresponding MMC subsection within Signal Descriptions

and Detailed Description sections.

For more information, see Multi-Media Card/Secure Digital (MMCSD) Interface section in Peripherals chapter in

the device TRM.

MMC Timing Conditions

PARAMETER

MODE

MIN

MAX

UNIT

INPUT CONDITIONS

Default Speed

High Speed

0.69

2.06

V/ns

SR_I

Input Slew Rate

OUTPUT CONDITIONS

C_LOutput Load Capacitance

Default Speed

High Speed

MMC Timing Requirements - SD Card Default Speed Mode

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

Setup time, MMC_CMD valid before MMC_CLK

rising edge

DS1

DS2

DS3

DS4

t_{su(cmdV-clkH)}

2.15

Hold time, MMC_CMD valid after MMC_CLK

rising edge

t_h(clkH-cmdV)

t_su(dV-clkH)

t_h(clkH-dV)

19.67

2.15

Setup time, MMC_DAT[3:0] valid before

MMC_CLK rising edge

Hold time, MMC_DAT[3:0] valid after MMC_CLK

rising edge

19.67

MMC[x]_CLK

DS2

DS1

DS3

MMC[x]_CMD

DS4

MMC[x]_DAT[3:0]

图7-44. MMC –Default Speed –Receive Mode

MMC Switching Characteristics - SD Card Default Speed Mode

NO.

PARAMETER

DESCRIPTION

Operating frequency, MMC_CLK

Operating period, MMC_CLK

Pulse duration, MMC_CLK high

Pulse duration, MMC_CLK low

MIN

MAX

UNIT

MHz

f_op(clk)

DS5

DS6

DS7

t_c(clk)

t_w(clkH)

t_w(clkL)

18.7

Delay time, MMC_CLK falling edge to

MMC_CMD transition

DS8

DS9

t_d(clkL-cmdV)

t_d(clkL-dV)

14.1

–14.1

Delay time, MMC_CLK falling edge to

MMC_DAT[3:0] transition

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DS5

DS6

DS7

MMC[x]_CLK

MMC[x]_CMD

DS8

DS9

MMC[x]_DAT[3:0]

图7-45. MMC –Default Speed –Transmit Mode

MMC Timing Requirements - SD Card High Speed Mode

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

Setup time, MMC_CMD valid before MMC_CLK

rising edge

HS1

HS2

HS3

HS4

t_{su(cmdV-clkH)}

2.15

Hold time, MMC_CMD valid after MMC_CLK

rising edge

t_h(clkH-cmdV)

t_su(dV-clkH)

t_h(clkH-dV)

2.67

2.15

2.67

Setup time, MMC_DAT[3:0] valid before

MMC_CLK rising edge

Hold time, MMC_DAT[3:0] valid after MMC_CLK

rising edge

MMC[x]_CLK

HS1

HS3

HS2

MMC[x]_CMD

HS4

MMC[x]_DAT[3:0]

图7-46. MMC –High Speed –Receive Mode

MMC Switching Characteristics - SD Card High Speed Mode

NO.

PARAMETER

DESCRIPTION

Operating frequency, MMC_CLK

Operating period, MMC_CLK

Pulse duration, MMC_CLK high

Pulse duration, MMC_CLK low

MIN

MAX

UNIT

MHz

f_op(clk)

HS5

HS6

HS7

t_c(clk)

t_w(clkH)

t_w(clkL)

9.2

Delay time, MMC_CLK falling edge to

MMC_CMD transition

HS8

HS9

t_d(clkL-cmdV)

t_d(clkL-dV)

3.35

–7.35

Delay time, MMC_CLK falling edge to

MMC_DAT[3:0] transition

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HS5

HS6

HS7

MMC[x]_CLK

HS8

MMC[x]_CMD

HS9

MMC[x]_DAT[3:0]

图7-47. MMC –High Speed –Transmit Mode

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7.11.5.13 Quad Serial Peripheral Interface (QSPI)

For more details about features and additional description information on the device Quad Serial Peripheral

Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.

For more information, see Quad Serial Peripheral Interface (QSPI) section in the device TRM.

QSPI Timing Conditions

PARAMETER

MIN

MAX

UNIT

V/ns

INPUT CONDITIONS

SR_I

Input Slew Rate

OUTPUT CONDITIONS

C_L

Output Load Capacitance

QSPI Timing Requirements

(1) (2)

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

Manual IO

Timing Modes,

Clock Mode 0

Setup time, d[3:0] valid before

falling rtclk edge

t_su(D-RTCLK)

2.69

5.7

Q12

Q13

Manual IO

Timing Modes,

Clock Mode 3

Setup time, d[3:0] valid before

falling sclk edge

t_su(D-SCLK)

t_h(RTCLK-D)

t_h(SCLK-D)

Manual IO

Timing Modes,

Clock Mode 0

Hold time, d[3:0] valid after falling

rtclk edge

–0.1

0.1

Manual IO

Timing Modes,

Clock Mode 3

Hold time, d[3:0] valid after falling

sclk edge

(1) Clock Modes 1 and 2 are not supported.

(2) The device captures data on the falling clock edge in Clock Mode 0 and 3, as opposed to the traditional rising clock edge. Although

non-standard, the falling-edge-based setup and hold timings have been designed to be compatible with standard SPI devices that

launch data on the falling edge in Clock Modes 0 and 3.

图7-48. QSPI Timing Requirements

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QSPI Switching Characteristics

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

Manual IO

Timing Modes,

Clock Mode 0

10.41

t_c(SCLK)

Cycle time, sclk

Manual IO

Timing Modes,

Clock Mode 3

13.02

Y⁽⁴⁾× P⁽¹⁾–1

t_w(SCLKL)

t_w(SCLKH)

Pulse duration, sclk low

Pulse duration, sclk high

All

Delay time, sclk falling edge to cs active Manual IO

–M⁽²⁾× P⁽¹⁾–2

N⁽³⁾× P⁽¹⁾–2

–1

–M⁽²⁾× P⁽¹⁾+ 2

N⁽³⁾× P⁽¹⁾+ 2

t_d(CS-SCLK)

t_d(SCLK-CS)

t_d(SCLK-D0)

t_ena(CS-D0LZ)

t_dis(CS-D0Z)

edge, CS1:0

Timing Modes

Delay time, sclk falling edge to cs

inactive edge, CS1:0

Manual IO

Timing Modes

Delay time, sclk falling edge to d[0]

transition

Manual IO

Timing Modes

Enable time, cs active edge to d[0] drive

(lo-z)

–P⁽¹⁾–2

–P⁽¹⁾+ 2

All

Disable time, cs active edge to d[0] tri-

stated (hi-z)

Manual IO

Timing Modes,

PHA=0 Only

Delay time, sclk first falling edge to first

d[0] transition

–P⁽¹⁾–1

–P⁽¹⁾+ 2

t_d(SCLK-D0)

(1) P = SCLK period

(2) M=QSPI_SPI_DC_REG.DDx + 1 when Clock Mode 0. M=QSPI_SPI_DC_REG.DDx when Clock Mode 3.

(3) N = 2 when Clock Mode 0. N = 3 when Clock Mode 3.

(4) Y = 0.5 when DCLK_DIV is 0 or ODD

Y = (DCLK_DIV/2)/(DCLK_DIV+1) when DCLK_DIV is EVEN

图7-49. QSPI Switching Characteristics

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7.11.5.14 Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS)

The device has integrated a single Programmable Real-Time Unit and Industrial Communication Subsystem

(PRU-ICSS0). The programmable nature of the PRU cores, along with their access to pins, events and all device

resources, provides flexibility in implementing fast real-time responses, specialized data handling operations,

custom peripheral interfaces, and in offloading tasks from the other processor cores in the device.

For more details about features and additional description information on the device PRU-ICSS, see the

corresponding subsections within Signal Descriptions and Detailed Description sections.

备注

The PRU-ICSS0 supports an internal wrapper multiplexing that expands the device top-level

multiplexing.

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7.11.5.14.1 PRU-ICSS Programmable Real-Time Unit (PRU)

备注

The PRU-ICSS PRU signals have different functionality depending on the mode of operation. The

signal naming in this section matches the naming used in the PRU Module Interface section in the

device TRM.

PRU-ICSS PRU Timing Conditions

PARAMETER

MIN

MAX

UNIT

V/ns

INPUT CONDITIONS

SR_I

Input Slew Rate

OUTPUT CONDITIONS

C_L

Output Load Capacitance

PRU-ICSS PRU Switching Characteristics - Direct Output Mode

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

PRDO1

t_{sk(PRU_GPO)}

PRU_GPO (data out) skew

GPO[n:0]

PRDO1

PRU_TIMING_02

A. n in GPO[n:0] = 19.

图7-50. PRU-ICSS PRU Direct Output Timing

PRU-ICSS PRU Timing Requirements - Parallel Capture Mode

NO.

PARAMETER

t_{c(PRU_CLOCK)}

t_{w(PRU_CLOCKL}

t_{w(PRU_CLOCKH)}

DESCRIPTION

MIN

MAX

UNIT

PRPC1

Cycle time, PRU_CLOCK

PRPC2

PRPC3

Pulse duration, PRU_CLOCK Low

Pulse duration, PRU_CLOCK High

Setup time, PRU_DATAIN valid before

PRU_CLOCK active edge

PRPC4

PRPC5

t_{su(PRU_DATAIN-PRU_CLK)}

t_{th(PRU_CLOCK-}

Hold time, PRU_DATAIN valid after

PRU_CLOCK active edge

PRU_DATAIN)

PRPC1

PRPC3

PRPC2

CLOCKIN

DATAIN

PRPC5

PRPC4

PRU_TIMING_03

图7-51. PRU-ICSS PRU Parallel Capture Timing Requirements –Rising Edge Mode

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PRPC1

PRPC3

PRPC2

CLOCKIN

DATAIN

PRPC5

PRPC4

PRU_TIMING_04

图7-52. PRU-ICSS PRU Parallel Capture Timing Requirements –Falling Edge Mode

PRU-ICSS PRU Timing Requirements - Shift In Mode

NO.

PRSI1

PRSI2

PARAMETER

t_{w(PRU_DATAINH)}

t_{w(PRU_DATAINL)}

DESCRIPTION

Pulse duration, PRU_DATAIN High

Pulse duration, PRU_DATAIN Low

MIN

2 + 2P⁽¹⁾

2+ 2P⁽¹⁾

MAX

UNIT

(1) P = Internal shift in clock period, defined by PRU_GPI_DIV0 and PRU0_GPI_DIV1 bit fields in the GPCFGn register.

PRSI1

PRSI2

DATAIN

PRU_TIMING_05

图7-53. PRU-ICSS PRU Shift In Timing

PRU-ICSS PRU Switching Characteristics - Shift Out Mode

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

PRSO1

t_{c(PRU_CLOCKOUT)}

Cycle time, PRU_CLOCKOUT

–0.3 + 0.475 × P⁽¹⁾× Z⁽²⁾

–0.3 + 0.475 × P⁽¹⁾× Y⁽³⁾

PRSO2L t_{w(PRU_CLOCKOUTL)}

PRSO2H t_{w(PRU_CLOCKOUTH)}

Pulse duration, PRU_CLOCKOUT Low

Pulse duration, PRU_CLOCKOUT High

t_{d(PRU_CLOCKOUT-}

Delay time, PRU_CLOCKOUT to

PRU_DATAOUT Valid

PRSO3

PRU_DATAOUT)

(1) P = Software programmable shift out clock period, defined by PRU0_GP0_Div0 and PRU0_GPO_DIV1 bit fields in the GPCFGn

(2) The Z parameter is defined as follows:

If PRU0_GPI_DIV0 and PRU0_GPI_DIV1 are INTEGERS -or- if PRU0_GPI_DIV0 is a NON-INTEGER and PRU0_GPI_DIV1 is an

EVEN INTEGER then,

Z equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1).

If PRU0_GPI_DIV0 is a NON-INTEGER and PRU0_GPI_DIV1 is an ODD INTEGER then,

Z equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1 + 0.5).

If PRU0_GPI_DIV0 is an INTEGER and PRU0_GPI_DIV1 is a NON-INTEGER then,

Z equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1 + 0.5 * PRU0_GPI_DIV0).

If PRU0_GPI_DIV0 and PRU0_GPI_DIV1 are NON-INTEGERS then,

Z equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1 + 0.25 * PRU0_GPI_DIV0).

The Y parameter is defined as follows:

(3)

If PRU0_GPI_DIV0 and PRU0_GPI_DIV1 are INTEGERS -or- if PRU0_GPI_DIV0 is a NON-INTEGER and PRU0_GPI_DIV1 is an

EVEN INTEGER then,

Y equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1).

If PRU0_GPI_DIV0 is a NON-INTEGER and PRU0_GPI_DIV1 is an ODD INTEGER then,

Y equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1 - 0.5).

If PRU0_GPI_DIV0 is an INTEGER and PRU0_GPI_DIV1 is a NON-INTEGER then,

Y equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1 - 0.5 * PRU0_GPI_DIV0).

If PRU0_GPI_DIV0 and PRU0_GPI_DIV1 are NON-INTEGERS then,

Y1 equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1 - 0.25 * PRU0_GPI_DIV0) and

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Y2 equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1 + 0.25 * PRU0_GPI_DIV0), where Y1 is the first high pulse and Y2 is the second high

pulse.

PRSO1

PRSO2H

PRSO2L

CLOCKOUT

DATAOUT

PRSO3

PRU_TIMING_06

图7-54. PRU-ICSS PRU Shift Out Timing

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7.11.5.14.2 PRU-ICSS PRU Sigma Delta and Peripheral Interface

PRU-ICSS PRU Sigma Delta and Peripheral Interface Timing Conditions

PARAMETER

MIN

MAX

UNIT

V/ns

INPUT CONDITIONS

SR_I

Input Slew Rate

OUTPUT CONDITIONS

C_L

Output Load Capacitance

PRU-ICSS PRU Timing Requirements - Sigma Delta Mode

NO.

PARAMETER

t_{c(SD_CLK)}

t_{w(SD_CLKL)}

t_{w(SD_CLKH)}

DESCRIPTION

MIN

MAX

UNIT

PRSD1

Cycle time, SD_CLK

PRSD2L

PRSD2H

Pulse duration, SD_CLK Low

Pulse duration, SD_CLK High

Setup time, SD_D valid before SD_CLK active

edge

PRSD3

PRSD4

t_{su(SD_D-SDCLK)}

t_{su(SDCLK-SD_D)}

Hold time, SD_D valid after SD_CLK active

edge

PRSD1

PRSD2H

SDx_CLK

SDx_D

PRSD2L

PRSD4

PRSD3

PRU_TIMING_07

图7-55. PRU-ICSS PRU SD_CLK Falling Active Edge

PRSD2L

SDx_CLK

SDx_D

PRSD4

PRSD3

PRU_TIMING_08

图7-56. PRU-ICSS PRU SD_CLK Rising Active Edge

PRU-ICSS PRU Timing Requirements - Peripheral Interface Mode

NO.

PRPIF1

PRPIF2

PARAMETER

t_{w(PIF_DATA_INH)}

t_{w(PIF_DATA_INL)}

DESCRIPTION

Pulse duration, PIF_DATA_IN High

Pulse duration, PIF_DATA_IN Low

MIN

MAX

UNIT

2 + 0.475 × (4 × P⁽¹⁾

)

(1) P = 1x (or TX) clock period, defined by TX_DIV_FACTOR and TX_DIV_FACTOR_FRAC in the CFG_ED_P<n>_TXCFG register.

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PRPIF1

PRPIF2

PIF_DATA_IN

PRUPIF_TIMING_01

图7-57. PRU-ICSS PRU Peripheral Interface Timing Requirements

PRU-ICSS PRU Switching Characteristics - Peripheral Interface Mode

NO.

PARAMETER

t_{c(PIF_CLK)}

t_{w(PIF_CLKH)}

t_{w(PIF_CLKL)}

DESCRIPTION

MIN

MAX

UNIT

PRPIF3

Cycle time, PIF_CLK

PRPIF4

PRPIF5

PRPIF6

PRPIF7

Pulse duration, PIF_CLK High

Pulse duration, PIF_CLK Low

0.475P⁽¹⁾

–5

t_{d(PIF_CLK-PIF_DATA_OUT)}Delay time, PIF_CLK fall to PIF_DATA_OUT

t_{d(PIF_CLK-PIF_DATA_EN)}Delay time, PIF_CLK fall to PIF_DATA_EN

–5

(1) P = 1x (or TX) clock period, defined by TX_DIV_FACTOR and TX_DIV_FACTOR_FRAC in the CFG_ED_P<n>_TXCFG register.

PRPIF3

PRPIF4

PRPIF5

PIF_CLK

PRPIF6

PIF_DATA_OUT

PRPIF7

PIF_DATA_EN

图7-58. PRU-ICSS PRU Peripheral Interface Switching Characteristics

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7.11.5.14.3 PRU-ICSS Pulse Width Modulation (PWM)

PRU-ICSS PWM Timing Conditions

PARAMETER

MIN

MAX

UNIT

V/ns

INPUT CONDITIONS

SR_I

Input Slew Rate

OUTPUT CONDITIONS

C_L

Output Load Capacitance

PRU-ICSS PWM Switching Characteristics

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

PRPWM1

t_{sk(PWM_A/B)}

PWM_A/B skew

PWM_A/B

PRPWM1

PRU_PWM_TIMING_01

图7-59. PRU-ICSS PWM Timing

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7.11.5.14.4 PRU-ICSS Industrial Ethernet Peripheral (IEP)

PRU-ICSS IEP Timing Conditions

PARAMETER

MIN

MAX

UNIT

V/ns

INPUT CONDITIONS

SR_I

Input Slew Rate

OUTPUT CONDITIONS

C_L

Output Load Capacitance

PRU-ICSS IEP Timing Requirements - Input Validated with SYNCx

NO.

PARAMETER

t_{w(EDC_SYNCx_OUTL)}

t_{w(EDC_SYNCx_OUTH)}

DESCRIPTION

MIN

MAX

UNIT

–2 + 20P⁽¹⁾

PRIEP1

Pulse duration, EDC_SYNCx_OUT Low

Pulse duration, EDC_SYNCx_OUT High

PRIEP2

PRIEP3

t_{su(EDIO_DATA_IN-}

Setup time, EDIO_DATA_IN valid before

EDC_SYNCx_OUT active edge

EDC_SYNCx_OUT

t_{h(EDC_SYNCx_OUT-}

Hold time, EDIO_DATA_IN valid after

EDC_SYNCx_OUT active edge

PRIEP4

EDIO_DATA_IN)

(1) P = PRU-ICSS IEP clock source period.

EDC_SYNC_OUTx

PRIEP2

PRIEP1

PRIEP3

PRIEP4

EDIO_DATA_IN[7:0]

PRU_IEP_TIMING_01

图7-60. PRU-ICSS IEP SYNC Timing Requirements

PRU-ICSS IEP Timing Requirements - Digital IOs

NO.

PARAMETER

t_{w(EDIO_OUTVALIDL)}

t_{w(EDIO_OUTVALIDH)}

DESCRIPTION

MIN

–2 + 14P⁽¹⁾

–2 + 32P⁽¹⁾

MAX

UNIT

IEPIO1

Pulse duration, EDIO_OUTVALID Low

Pulse duration, EDIO_OUTVALID High

IEPIO2

IEPIO3

IEPIO4

t_{d(EDIO_OUTVALID-}

Delay time, EDIO_OUTVALID to EDIO_DATA

OUT

18P⁽¹⁾

EDIO_DATA_OUT)

t_{sk(EDIO_DATA_OUT)}

EDIO_DATA_OUT skew

(1) P = PRU-ICSS IEP clock source period.

EDIO_DATA_OUT

IEPIO4

PRU_EDIO_DATA_OUT_TIMING_00

图7-61. PRU-ICSS IEP Digital IOs Timing Requirements

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PRU-ICSS IEP Timing Requirements - LATCHx_IN

NO.

PRLA1

PRLA2

PARAMETER

t_{w(EDC_LATCHx_INL)}

t_{w(EDC_LATCHx_INH)}

DESCRIPTION

MIN

2 + 3P⁽¹⁾

MAX

UNIT

Pulse duration, EDC_LATCHx_IN Low

Pulse duration, EDC_LATCHx_IN High

(1) P = PRU-ICSS IEP clock source period.

PRLA1

EDC_LATCH_INx

PRLA2

PRU_IEP_TIMING_02

图7-62. PRU-ICSS IEP LATCH_INx Timing Requirements

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7.11.5.14.5 PRU-ICSS Universal Asynchronous Receiver Transmitter (UART)

PRU-ICSS UART Timing Conditions

PARAMETER

MIN

0.01

MAX

UNIT

V/ns

INPUT CONDITIONS

SR_I

Input Slew Rate

0.33

OUTPUT CONDITIONS

C_L

Output Load Capacitance

PRU-ICSS UART Timing Requirements

NO.

PRUR1H

PRUR1L

PARAMETER

t_w(RXH)

t_w(RXL)

DESCRIPTION

MIN

MAX

UNIT

Pulse duration, Receive start, stop, data bit High

Pulse duration, Receive start, stop, data bit Low

U⁽¹⁾

–2 + U⁽¹⁾

(1) U = UART baud time = 1/programmed baud rate.

PRU-ICSS UART Switching Characteristics

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

PRUR2

f_(baud)

Maximum programmable baud rate

U⁽¹⁾

Pulse duration, Transmit start, stop, data bit

High

–2 + U⁽¹⁾

PRUR3H

t_w(TXH)

(1) U = UART baud time = 1/programmed baud rate.

PRUR1L

PRUR1H

Start

Bit

PRGi_UART0_RXD⁽¹⁾

Data Bits

PRUR3L

PRUR3H

Start

Bit

PRGi_UART0_TXD⁽¹⁾

Data Bits

PRU_UART_TIMING_01

(1) i in PRGi_UART0_RXD and PRGi_UART0_TXD = 0, 1 or 2

图7-63. PRU-ICSS UART Timing Requirements and Switching Characteristics

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ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

7.11.5.14.6 PRU-ICSS Enhanced Capture Peripheral (ECAP)

PRU-ICSS ECAP Timing Conditions

PARAMETER

MIN

MAX

UNIT

V/ns

INPUT CONDITIONS

SR_I

Input Slew Rate

OUTPUT CONDITIONS

C_L

Output Load Capacitance

PRU-ICSS ECAP Timing Requirements

NO.

PREP1

PREP2

PARAMETER

t_w(CAP)

t_w(SYNCI)

DESCRIPTION

MIN

MAX

UNIT

Pulse duration, Capture input (asynchronous)

Pulse duration, Sync input (asynchronous)

2 + 2P⁽¹⁾

(1) P = core_clk period

PREP1

PREP2

CAP

SYNCI

PRU_ECAP_TIMING_01

图7-64. PRU-ICSS ECAP Timing

PRU-ICSS ECAP Switching Characteristics

NO.

PREP3

PREP4

(1) P = core_clk period

PARAMETER

t_w(APWM)

t_w(SYNCO)

DESCRIPTION

MIN

2P⁽¹⁾

P⁽¹⁾

MAX

UNIT

Pulse duration, Auxillary PWM (APWM) output

high/low

Pulse duration, Sync output (asynchronous

PREP3

APWM_OUT

SYNC_OUT

PRI_ECAP_TIMING_02

图7-65. PRU-ICSS ECAP Switching Characteristics

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7.11.5.14.7 PRU-ICSS MDIO and MII

7.11.5.14.7.1 PRU-ICSS MDIO Timing

PRU-ICSS MDIO Timing Conditions

PARAMETER

MIN

0.9

MAX

UNIT

V/ns

INPUT CONDITIONS

SR_I

Input Slew Rate

3.6

OUTPUT CONDITIONS

C_L

Output Load Capacitance

470

PRU-ICSS MDIO Timing Requirements

NO.

MDIO1

MDIO2

PARAMETER

t_su(MDIO-MDC)

t_h(MDC-MDIO)

DESCRIPTION

MIN

MAX

UNIT

Setup time, MDIO[x]_MDIO valid before

MDIO[x]_MDC high

Hold time, MDIO[x]_MDIO valid from

MDIO[x]_MDC high

PRU-ICSS MDIO Switching Characteristics

NO.

PARAMETER

t_c(MDC)

t_w(MDCH)

t_w(MDCL)

DESCRIPTION

MIN

400

160

MAX

UNIT

MDIO3

Cycle time, MDIO[x]_MDC

MDIO4

MDIO5

Pulse duration, MDIO[x]_MDC high

Pulse duration, MDIO[x]_MDC low

Delay time, MDIO[x]_MDC low to

MDIO[x]_MDIO valid

MDIO7

t_d(MDC-MDIO)

150

–150

MDIO3

MDIO4

MDIO5

MDIO[x]_MDC

MDIO1

MDIO2

MDIO[x]_MDIO

(input)

MDIO7

MDIO[x]_MDIO

(output)

CPSW2G_MDIO_TIMING_01

图7-66. PRU-ICSS MDIO Timing Requirements and Switching Characteristics

7.11.5.14.7.2 PRU-ICSS MII Timing

PRU-ICSS MII Timing Conditions

PARAMETER

MIN

0.9

MAX

3.6

UNIT

V/ns

INPUT CONDITIONS

SR_I

Input Slew Rate

OUTPUT CONDITIONS

C_L

Output Load Capacitance

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PRU-ICSS MII Timing Requirements - MII[x]_RX_CLK

NO.

PARAMETER

DESCRIPTION

MODE

10 Mbps

MIN

399.96

39.996

140

MAX

400.04

40.004

260

UNIT

PMIR1

t_{c(RX_CLK)}

Cycle time, MII[x]_RX_CLK

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

PMIR2

PMIR3

t_{w(RX_CLKH)}

Pulse duration, MII[x]_RX_CLK high

Pulse duration, MII[x]_RX_CLK low

140

260

t_{w(RX_CLKL)}

PMIR1

PMIR2

PMIR3

MII_RX_CLK

PRU_MII_RT_TIMING_04

图7-67. PRU-ICSS MII[x]_RX_CLK Timing

PRU-ICSS MII Timing Requirements - MII[x]_RXD[3:0], MII[x]_RX_DV, and MII[x]_RX_ER

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

Setup time, MII[x]_RXD[3:0] valid before

MII[x]_RX_CLK

t_{su(RXD-RX_CLK)}

Setup time, MII[x]_RX_DV valid before

MII[x]_RX_CLK

t_{su(RX_DV-RX_CLK)}

t_{su(RX_ER-RX_CLK)}

t_{su(RXD-RX_CLK)}

t_{su(RX_DV-RX_CLK)}

t_{su(RX_ER-RX_CLK)}

t_{h(RX_CLK-RXD)}

10 Mbps

Setup time, MII[x]_RX_ER valid before

MII[x]_RX_CLK

PMIR4

Setup time, MII[x]_RXD[3:0] valid before

MII[x]_RX_CLK

Setup time, MII[x]_RX_DV valid before

MII[x]_RX_CLK

100 Mbps

10 Mbps

100 Mbps

Setup time, MII[x]_RX_ER valid before

MII[x]_RX_CLK

Hold time, MII[x]_RXD[3:0] valid after

MII[x]_RX_CLK

Hold time, MII[x]_RX_DV valid after

MII[x]_RX_CLK

t_{h(RX_CLK-RX_DV)}

t_{h(RX_CLK-RX_ER)}

t_{h(RX_CLK-RXD)}

Hold time, MII[x]_RX_ER valid after

MII[x]_RX_CLK

PMIR5

Hold time, MII[x]_RXD[3:0] valid after

MII[x]_RX_CLK

Hold time, MII[x]_RX_DV valid after

MII[x]_RX_CLK

t_{h(RX_CLK-RX_DV)}

t_{h(RX_CLK-RX_ER)}

Hold time, MII[x]_RX_ER valid after

MII[x]_RX_CLK

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PMIR4

PMIR5

MII_RX_CLK

MII_RXD[3:0],

MII_RX_DV, MII_RX_ER

图7-68. PRU-ICSS MII[x]_RXD[3:0], MII[x]_RX_DV, and MII[x]_RX_ER Timing

PRU-ICSS MII Switching Characteristics - MII[x]_TX_CLK

NO.

PARAMETER

DESCRIPTION

MODE

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

MIN

399.96

39.996

140

MAX

400.04

40.004

260

UNIT

PMIT1

t_{c(TX_CLK)}

Cycle time, MII[x]_TX_CLK

PMIT2

PMIT3

t_{w(TX_CLKH)}

Pulse duration, MII[x]_TX_CLK high

Pulse duration, MII[x]_TX_CLK low

140

260

t_{w(TX_CLKL)}

PMIT1

PMIT2

PMIT3

MII_TX_CLK

图7-69. PRU-ICSS MII[x]_TX_CLK Timing

PRU-ICSS MII Switching Characteristics - MII[x]_TXD[3:0] and MII[x]_TXEN

NO.

PARAMETER

t_{d(TX_CLK-TXD)}

t_{d(TX_CLK-TX_EN)}

t_{d(TX_CLK-TXD)}

DESCRIPTION

MODE

MIN

MAX

UNIT

Delay time, MII[x]_TX_CLK high to

MII[x]_TXD[3:0] valid

10 Mbps

Delay time, MII[x]_TX_CLK high to

MII[x]_TX_EN valid

PMIT4

Delay time, MII[x]_TX_CLK high to

MII[x]_TXD[3:0] valid

100 Mbps

Delay time, MII[x]_TX_CLK high to

MII[x]_TX_EN valid

t_{d(TX_CLK-TX_EN)}

PMIT4

MII_TX_CLK

MII_TXD[3:0], MII_TX_EN

图7-70. PRU-ICSS MII[x]_TXD[3:0], MII[x]_TX_EN Timing

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ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

7.11.5.15 Sigma Delta Filter Module (SDFM)

For more information, see Sigma Delta Filter Module section in the device TRM.

SDFM Timing Conditions

PARAMETER

MODE

MIN

MAX

UNIT

INPUT CONDITIONS

SR_I

Input Slew Rate

Mode 0

0.5

V/ns

SDFM Switching Characteristics

(2)

NO.

PARAMETER

t_c(SDC)

DESCRIPTION

Cycle time, SDx_Cy

MODE

Mode 0

MIN

MAX

UNIT

M0-1

M0-2

5P⁽¹⁾

2P⁽¹⁾

256P⁽¹⁾

t_w(SDCHL)

Pulse duration, SDx_Cy (high/low)

Mode 0

Setup time, SDx_dy valid before

SDx_Cy high

M0-3

M0-4

t_{sh(SDDV-SDCH)}

2P⁽¹⁾

Hold time, SDx_Dy wait after SDx_Cy

high

t_h(SDCH-SDD)

Mode 0

(1) P = SYSCLK period in ns.

(2) Some SDFM signals are pinmuxed with I2C0 SDA and SCL pins. These pins use an alternate open drain voltage buffer and may not

meet the specified parameters. Values are pending additional post-silicon validation.

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7.11.5.16 Universal Asynchronous Receiver/Transmitter (UART)

For more details about features and additional description information on the device Universal Asynchronous

Receiver Transmitter, see the corresponding subsections within Signal Descriptions and Detailed Description

sections.

For more information, see Universal Asynchronous Receiver/Transmitter (UART) section in the device TRM.

UART Timing Conditions

PARAMETER

MIN

0.5

MAX

UNIT

V/ns

INPUT CONDITIONS

SR_I

Input Slew Rate

OUTPUT CONDITIONS

C_L

Output Load Capacitance

UART Timing Requirements

NO.

PARAMETER

t_w(RX)

t_w(CTS)

DESCRIPTION

MIN

MAX

1.05U⁽¹⁾

UNIT

Pulse width, receive data bit, high or low

Pulse width, receive start bit, high or low

0.95U⁽¹⁾

(1) U = UART baud time = 1 / Programmed baud rate.

UART Switching Characteristics

NO.

PARAMETER

DESCRIPTION

MODE

15 pF

30 pF

MIN

MAX

UNIT

0.115

f_(baud)

Programmable baud rate

MHz

t_w(TX)

Pulse width, transmit data bit, high or low

Pulse width, transmit start bit, high or low

Delay time, receive CTS bit to trasmit data

U⁽¹⁾- 2.2

U⁽¹⁾+ 2.2

t_w(RTS)

t_d(CTS-TX)

(1) U = UART baud time = 1 / Programmed baud rate.

图7-71. UART Timing Requirements and Switching Characteristics

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ZHCSQ84C –OCTOBER 2022 –REVISED NOVEMBER 2022

7.11.6 Emulation and Debug

For more details about features and additional description information on the device Trace and JTAG interfaces,

see the corresponding subsections within Signal Descriptions and Detailed Description sections. For more

information, see the On-Chip Debug section in the device TRM.

7.11.6.1 JTAG

The acronym stands for the Joint Test Action Group, the committee of engineers who defined the boundary-

scan standard (IEEE std 1149.1). For more details about features and additional description information on the

device JTAG interface, see the corresponding subsections within Signal Descriptions and Detailed Description

sections.

JTAG Timing Conditions

PARAMETER

MIN

0.5

MAX

2.00

UNIT

V/ns

INPUT CONDITIONS

SR_I

Input Slew Rate

OUTPUT CONDITIONS

C_L

Output Load Capacitance

JTAG Timing Requirements

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

t_c(TCK)

Cycle time, TCK

t_w(TCKH)

Pulse width, TCK high

t_w(TCKL)

Pulse width, TCK low

t_su(TDI-TCKH)

t_su(TMS-TCKH)

t_h(TCK-TDI)

t_h(TCK-TMS)

Input setup time, TDI valid to TCK high

Input setup time, TMS valid to TCK high

Input hold time, TDI valid from TCK high

Input hold time, TMS valid from TCK high

15.9

JTAG Switching Characteristics

NO.

PARAMETER

DESCRIPTION

Delay time, TCK low to TDO invalid

Delay time, TCK low to TDO valid

MIN

MAX

UNIT

t_d(TCKL-TDOI)

–0.067005

t_d(TCKL-TDOV)

11.89594

TCK

TDI / TMS

TDO

图7-72. JTAG Timing Requirements and Switching Characteristics

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7.11.6.2 Trace

Debug Trace Timing Conditions

PARAMETER

MIN

MAX

UNIT

OUTPUT CONDITIONS

C_L

Output Load Capacitance

OUTPUT CONDITIONS

t_{d(Trace Mismatch)}

Propagation delay mismatch across all traces.

200

Debug Trace Switching Characteristics

NO.

PARAMETER

tc_{(TRC_CLK)}

t_{w(TRC_CLKH)}

t_{w(TRC_CLKL)}

DESCRIPTION

MIN

9.75

4.13

MAX

UNIT

DBTR1

Cycle time, TRC_CLK

DBTR2

DBTR3

Pulse width, TRC_CLK high

Pulse width, TRC_CLK low

Output setup time, TRC_DATA valid to

TRC_CLK edge

DBTR4

DBTR5

DBTR6

DBTR7

t_{osu(TRC_DATAV-TRC_CLK)}

t_{oh(TRC_CLK-TRC-DATAI)}

t_{osu(TRC_CTLV-TRC_CLK)}

t_{oh(TRC_CLK-TRC_CTLI)}

1.22

Output hold time, TRC_CLK edge to

TRC_DATA invalid

Output setup time, TRC_CTL valid to TRC_CLK

edge

Output hold time, TRC_CLK edge to TRC_CTL

invalid

DBTR1

DBTR2

DBTR3

TRC_CLK

(Worst Case 1)

(Ideal)

(Worst Case 2)

DBTR4

DBTR6

DBTR5

DBTR7

DBTR4

DBTR6

DBTR5

DBTR7

TRC_DATA

TRC_CTL

SPRSP08_Debug_01

图7-73. Trace Switching Characteristics

7.12 Decoupling Capacitor Requirements

7.12.1 Decoupling Capacitor Requirements

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

µF

C_VDD

Ground (Cap)

C_VDDS33

C_VDDA33

C_VDDS18

C_VDDA18

3.3V VDDS (Cap)

3.3V VDDA (Cap)

1.8V VDDS (Cap)

1.8V VDDA (Cap)

1.8V LDO VDDS (Cap)

1.8V LDO VDDA (Cap)

µF

0.1

3.3

µF

C_{VDDS18_LDO}

C_{VDDA18_LDO}

µF

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8 Detailed Description

8.1 Overview

The AM263x Sitara Arm Microcontrollers are built to meet the complex real-time processing and control needs of

next generation industrial and automotive embedded projects. AM263x uniquely combines advanced compute

with industry leading real-time control to meet the growing performance needs of applications such as HEV/EV

(traction inverters, Onboard Chargers, and DC-DC Converters), motor drives, solar energy, and energy storage.

AM263x combines up to four Cortex-R5F MCUs, a real-time control subsystem, a Hardware Security Module

(HSM), and one instance of Sitara’s TSN-enabled PRU-ICSS, making AM263x designed for advanced motor

control and digital power control applications.

The multiple R5F cores are arranged in cluster with 256KB of shared tightly coupled memory (TCM) along with

2MB of shared SRAM. The multiple Arm® cores can be optionally programmed to run in lock-step option for

different functional safety configurations. Extensive ECC is included on on-chip memory, peripherals, and

interconnect for enhanced reliability. Cryptographic acceleration and secure boot are also available on AM263x

devices in addition to granular firewalls managed by the HSM for developers to design the most secure systems.

The Real-Time Control Subsystem (CONTROLSS) is a revolutionary subsystem integrated into the device.

CONTROLSS contains multiple digital and analog control peripherals including: ADC, CMPSS, EPWM, ECAP,

and EQEP, among others to enable efficient execution of critical sense/process/actuate real-time signal chain

control loops. The integrated crossbar (XBAR) infrastructure enables flexible configuration and routing of

external signals to internal ports and internal signals to external pins.

The PRU-ICSS in AM263x provides the flexible industrial communications capability necessary to run TSN,

EtherCAT, PROFINET, Ethernet/IP, or for standard Ethernet connectivity or custom I/O interfacing. The PRU also

enables additional interfaces in the SoC including sigma delta decimation filters and absolute encoder interfaces.

Additional standard Ethernet ports are also provided with the CPSW interface.

TI provides a complete set of microcontroller software and development tools for the AM263x family of

microcontrollers in addition to multiple pin-to-pin compatible devices for scalability and ease of use.

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8.2 Processor Subsystems

8.2.1 Arm Cortex-R5F Subsystem

The R5FSS is a dual-core implementation of the Arm^®Cortex^®-R5F processor configured for dual-core (split) or

lockstep modes of operation. It also includes accompanying memories (L1 caches and tightly-coupled

memories), standard Arm^®CoreSight^™debug and trace architecture, integrated Vectored Interrupt Manager

(VIM), ECC Aggregators, and various wrappers for protocol conversion and address translation for easy

integration into the SoC. The device supports up to two R5FSS modules for a total possible 4x functional cores

(dual-core mode) or 2x functional cores (lockstep mode).

备注

The Arm^®Cortex^®-R5F processor is a Cortex-R5 processor that includes the optional Floating-point

Unit (FPU) extension.

For more information, see R5FSS section in Processors and Accelerators chapter in the device TRM.

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9 Applications, Implementation, and Layout

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Device Connection and Layout Fundamentals

9.1.1 External Oscillator

For more information about External Oscillators, see the Clock Specifications section.

9.1.2 JTAG, EMU, and TRACE

Texas Instruments supports a variety of eXtended Development System (XDS) JTAG controllers with various

debug capabilities beyond only JTAG support. A summary of this information is available in the XDS Target

Connection Guide.

For recommendations on JTAG, EMU, and TRACE routing, see the Emulation and Trace Headers Technical

Reference Manual

9.1.3 Hardware Design Guide

For details regarding creating PCB systems based on the AM263x family of MCU devices, please see the

AM263x Hardware Design Guide.

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10 Device and Documentation Support

10.1 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

microcontrollers (MCUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for

example, XAM2634AOLFGMZCZQ). Texas Instruments recommends two of three possible prefix designators for

its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from

engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).

Device development evolutionary flow:

Experimental device that is not necessarily representative of the final device's electrical specifications and

may not use production assembly flow.

Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical

specifications.

null Production version of the silicon die that is fully qualified.

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.

TMDS Fully-qualified development-support product.

X and P devices and TMDX development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

Production devices and TMDS development-support tools have been characterized fully, and the quality and

reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (X or P) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system because their

expected end-use failure rate still is undefined. Only qualified production devices are to be used.

For orderable part numbers of AM263x devices in the ZCZ package type, see the Package Option Addendum of

this document, the TI website (ti.com), or contact your TI sales representative.

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10.1.1 Standard Package Symbolization

备注

Some devices may have a cosmetic circular marking visible on the top of the device package which

results from the production test process. In addition, some devices may also show a color variation in

the package substrate which results from the substrate manufacturer. These differences are cosmetic

only with no reliability impact.

aBBBBBBr

ZfYytPPPQ1

A1 (PIN ONE INDICATOR)

XXXXXXX

ZZZ

YYY

图10-1. Printed Device Reference

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10.1.2 Device Naming Convention

表10-1. Nomenclature Description

FIELD PARAMETER

FIELD DESCRIPTION

VALUE

DESCRIPTION

Prototype

a⁽¹⁾

Device evolution stage

Preproduction (production test flow, no reliability data)

Production

BLANK

AM2634

BBBBBB

Base production part number

Device revision

AM2632

See Device Comparison.

AM2631

SR 1.0

SR 1.0A

SR 1.1

Device Operating

Performance Points

See Operating Performance Points.

PRU Only

+ CAN-FD Supported

+ Standard Analog

PRU-ICSS

+ CAN-FD Supported

+ Standard Analog

PRU-ICSS

+ EtherCAT HW Accelerator

+ CAN-FD Supported

+ Standard Analog

PRU-ICSS

+ EtherCAT HW Accelerator

+ CAN-FD Supported

+ Pre-integrated Stacks Enabled

+ Standard Analog

Features

(see 表5-1, Device

Comparison)

PRU Only

+ CAN-FD Supported

+ Enhanced Analog

PRU-ICSS

+ CAN-FD Supported

+ Enhanced Analog

PRU-ICSS

+ EtherCAT HW Accelerator

+ CAN-FD Supported

+ Enhanced Analog

PRU-ICSS

+ EtherCAT HW Accelerator

+ CAN-FD Supported

+ Pre-integrated Stacks

+ Enhanced Analog

Non-Functional Safety (AM2631 only)

Functional Safety

Security

Secure

–40°C to 105°C - Industrial

–40°C to 150°C - Extended Automotive

ZCZ NFBGA-N324 (15 mm × 15 mm) Package

Auto Qualified (AEC-Q100)

Standard

Junction Temperature

(see 节7.5, ROC)

t⁽²⁾

PPP

Package Designator

ZCZ

BLANK

Automotive Designator

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表10-1. Nomenclature Description (continued)

FIELD PARAMETER

FIELD DESCRIPTION

VALUE

DESCRIPTION

XXXXXXX

YYY

ZZZ

Lot Trace Code (LTC)

Production Code; For TI use only

Pin one designator

ECAT - Green package designator

(1) To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. These prefixes represent

evolutionary stages of product development from engineering prototypes through fully qualified production devices.

Prototype devices are shipped against the following disclaimer:

“This product is still in development and is intended for internal evaluation purposes.”

Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of

merchantability of fitness for a specific purpose, of this device.

(2) Applies to device max junction temperature.

备注

BLANK in the symbol or part number is collapsed so there are no gaps between characters.

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10.2 Tools and Software

The following products support development for AM263x platforms:

Development Tools

Code Composer Studio^™Integrated Development Environment Code Composer Studio (CCS) Integrated

Development Environment (IDE) is a development environment that supports TI's Microcontroller and Embedded

Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded

applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger,

profiler, and many other features. The intuitive IDE provides a single user interface taking you through each step

of the application development flow. Familiar tools and interfaces allow users to get started faster than ever

before. Code Composer Studio combines the advantages of the Eclipse software framework with advanced

embedded debug capabilities from TI resulting in a compelling feature-rich development environment for

embedded developers.

SysConfig-PinMux Tool The SysConfig-PinMux Utility is a software tool which provides a Graphical User

Interface for configuring pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI

Embedded Processor devices. The tool can be used to automatically calculate the optimal pinmux configuration

to satisfy entered system requirements. The tool will generate output C header/code files that can be imported

into software development kits (SDKs) and used to configure customer's software to meet custom hardware

requirements.

For a complete listing of development-support tools for the processor platform, visit the Texas Instruments

website at ti.com. For information on pricing and availability, contact the nearest TI field sales office or authorized

distributor.

10.3 Documentation Support

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

The following documents are provided to describe the AM263x device.

AM263x Silicon Errata Describes the known exceptions to the functional specifications for the device.

AM263x Technical Reference Manual Details the integration, the environment, the functional description, and

the programming models for each peripheral and subsystem in the AM263x family of devices.

AM263x TRM Register Addendum Details the memory mapped register information for each peripheral and

subsystem in the AM263x family of devices.

10.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

10.5 Trademarks

Ethernet/IP^™is a trademark of ODVA, INC..

Sitara^™, Code Composer Studio^™, and TI E2E^™are trademarks of Texas Instruments.

CoreSight^™is a trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Arm^®and Cortex^®are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

EtherCAT^®is a registered trademark of Beckhoff Automation GmbH.

PROFINET^®is a registered trademark of PROFINET International.

IO-Link^®is a registered trademark of PROFIBUS Nutzerorganisation e.V. eingetragener verein (e.v.) FED REP

GERMANY.

所有商标均为其各自所有者的财产。

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10.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

10.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

To learn more about TI packaging, visit the Packaging information website.

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PACKAGE OPTION ADDENDUM

www.ti.com

20-Jun-2023

PACKAGING INFORMATION

Orderable Device

AM2631CNDGHAZCZR

AM2631CNDGHMZCZRQ1

AM2631CODGHMZCZRQ1

AM2632CNDFHAZCZR

AM2632CNEFHAZCZR

AM2632CODFHMZCZRQ1

AM2632COKFHAZCZR

AM2632COKFHMZCZRQ1

AM2632COLFHAZCZR

AM2632COMFHAZCZR

AM2632CPDFHMZCZRQ1

AM2634CODFHAZCZR

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

-40 to 105

-40 to 150

-40 to 105

-40 to 150

-40 to 105

-40 to 150

-40 to 105

-40 to 150

-40 to 105

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

ACTIVE

NFBGA

ZCZ

324

1000 RoHS & Green

Call TI

Level-3-260C-168 HR

AM2631C

NDGHAZCZ

548

Samples

ACTIVE

ZCZ

Call TI

AM2631C

NDGHMZCZQ1

548

AM2631C

ODGHMZCZQ1

548

AM2632C

NDFHAZCZ

548

AM2632C

NEFHAZCZ

548

AM2632C

ODFHMZCZQ1

548

AM2632C

OKFHAZCZ

548

AM2632C

OKFHMZCZQ1

548

AM2632C

OLFHAZCZ

548

AM2632C

OMFHAZCZ

548

AM2632C

PDFHMZCZQ1

548

AM2634C

ODFHAZCZ

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

20-Jun-2023

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

548

AM2634CODFHMZCZRQ1

AM2634COEFHAZCZR

AM2634COKFHAZCZR

AM2634COKFHMZCZRQ1

AM2634COLFHAZCZR

AM2634COMFHAZCZR

AM2634CPDFHMZCZRQ1

ACTIVE

NFBGA

ZCZ

324

1000 RoHS & Green

Call TI

Level-3-260C-168 HR

-40 to 150

-40 to 105

-40 to 150

-40 to 105

-40 to 150

AM2634C

ODFHMZCZQ1

548

Samples

ZCZ

Call TI

AM2634C

OEFHAZCZ

548

ZCZ

AM2634C

OKFHAZCZ

548

ZCZ

AM2634C

OKFHMZCZQ1

548

ZCZ

AM2634C

OLFHAZCZ

548

ZCZ

AM2634C

OMFHAZCZ

548

ZCZ

AM2634C

PDFHMZCZQ1

548

XAM2634BOLFHMZCZQ

XAM2634BOMFHAZCZ

ACTIVE

NFBGA

ZCZ

324

TBD

Call TI

-40 to 150

-40 to 105

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

20-Jun-2023

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF AM2631, AM2631-Q1, AM2632, AM2632-Q1, AM2634, AM2634-Q1 :

Catalog : AM2631, AM2632, AM2634

•

Automotive : AM2631-Q1, AM2632-Q1, AM2634-Q1

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

AM2631CNDGHAZCZR NFBGA

AM2631CNDGHMZCZRQ1 NFBGA

AM2631CODGHMZCZRQ1 NFBGA

AM2632CNDFHAZCZR NFBGA

AM2632CNEFHAZCZR NFBGA

AM2632CODFHMZCZRQ1 NFBGA

AM2632COKFHAZCZR NFBGA

AM2632COKFHMZCZRQ1 NFBGA

AM2632COLFHAZCZR NFBGA

AM2632COMFHAZCZR NFBGA

AM2632CPDFHMZCZRQ1 NFBGA

AM2634CODFHAZCZR NFBGA

AM2634CODFHMZCZRQ1 NFBGA

AM2634COEFHAZCZR NFBGA

AM2634COKFHAZCZR NFBGA

AM2634COKFHMZCZRQ1 NFBGA

ZCZ

324

1000

330.0

24.4

15.3

2.35

20.0

24.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2023

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

AM2634COLFHAZCZR NFBGA

AM2634COMFHAZCZR NFBGA

AM2634CPDFHMZCZRQ1 NFBGA

ZCZ

324

1000

330.0

24.4

15.3

2.35

20.0

24.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

AM2631CNDGHAZCZR

AM2631CNDGHMZCZRQ1

AM2631CODGHMZCZRQ1

AM2632CNDFHAZCZR

AM2632CNEFHAZCZR

AM2632CODFHMZCZRQ1

AM2632COKFHAZCZR

AM2632COKFHMZCZRQ1

AM2632COLFHAZCZR

AM2632COMFHAZCZR

AM2632CPDFHMZCZRQ1

AM2634CODFHAZCZR

AM2634CODFHMZCZRQ1

AM2634COEFHAZCZR

AM2634COKFHAZCZR

AM2634COKFHMZCZRQ1

AM2634COLFHAZCZR

AM2634COMFHAZCZR

NFBGA

ZCZ

324

1000

336.6

41.3

Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2023

Device

AM2634CPDFHMZCZRQ1

Package Type Package Drawing Pins

NFBGA ZCZ 324

SPQ

Length (mm) Width (mm) Height (mm)

336.6 336.6 41.3

1000

Pack Materials-Page 4

PACKAGE OUTLINE

NFBGA - 1.4 mm max height

ZCZ0324A

PLASTIC BALL GRID ARRAY

15.1

14.9

BALL A1 CORNER

15.1

14.9

1.4 MAX

SEATING PLANE

BALL TYP

0.45

0.35

0.12 C

13.6 TYP

SYMM

13.6

TYP

0.55

0.45

324X Ø

0.15

0.05

A B

(0.7) TYP

0.8 TYP

10 11 12 13

14 15 16 17

(0.7) TYP

SYMM

0.8 TYP

4226659/A 03/2021

NOTES:

NanoFree is a trademark of Texas Instruments.

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

NFBGA - 1.4 mm max height

PLASTIC BALL GRID ARRAY

ZCZ0324A

SYMM

(0.8) TYP

324X (Ø 0.4)

(0.8) TYP

SYMM

10 11 12 13 14 15 16 17

LAND PATTERN EXAMPLE

SCALE: 8X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

EXPOSED

METAL UNDER

SOLDER MASK

METAL

(Ø 0.40)

SOLDER MASK

OPENING

(Ø 0.40)

METAL

SOLDER MASK

OPENING

EXPOSED

METAL

NON- SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4226659/A 03/2021

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments

Literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com

EXAMPLE STENCIL DESIGN

NFBGA - 1.4 mm max height

PLASTIC BALL GRID ARRAY

ZCZ0324A

SYMM

(0.8) TYP

324X (Ø 0.4)

(0.8) TYP

SYMM

10 11 12 13 14 15 16 17 18

SOLDER PASTE EXAMPLE

BASED ON 0.150 mm THICK STENCIL

SCALE: 8X

4226659/A 03/2021

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

AM2634COLFHAZCZR [TI]

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