AM3517_16_技术文档

AM3517/05 ARM Microprocessor

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SPRS550–OCTOBER 2009

1 AM3517/05 ARM Microprocessor

1.1 Features

•

HDQ/1-Wire Interface

•

AM3517/05 ARM Microprocessor:

–

Software Compatible with OMAP^TM

Processors**

3

4 UARTs (One with Infrared Data

Association [IrDA] and Consumer

Infrared [CIR] Modes)

3 Master/Slave High-Speed

Inter-Integrated Circuit (I2C) Controllers

12 32-bit General Purpose Timers

1 32-bit Watchdog Timer

1 32-bit 32-kHz Sync Timer

Up to 186 General-Purpose I/O (GPIO)

Pins

–

MPU Subsystem

•

500-MHz ARM Cortex-A8 Core

NEON SIMD Coprocessor and Vector

floating point (FP) co-processor

•

–

Memory Interfaces:

•

16/32- bit DDR2 Interface with 1 GByte

total addressable space

•

General Purpose Memory Interface

supporting 16-bit Wide Multiplexed

Address/Data bus

•

Display subsystem

–

Parallel Digital Output

Up to 24-Bit RGB

Supports Up to 2 LCD Panels

Support for Remote Frame Buffer Interface

(RFBI) LCD Panels

Two 10-bit Digital-to-Analog Converters

(DACs) Supporting

Composite NTSC/PAL Video

Luma/Chroma Separate Video (S-Video)

Serial Digital Output

Rotation 90-, 180-, and 270-degrees

Resize Images From 1/4x to 8x

Color Space Converter

•

64 K-Byte shared SRAM

3 Removable Removable Media

Interfaces [MMC/SD/SDIO]

–

IO Voltage: DDR2 IOs: 1.8V; Other IOs: 1.8V

and 3.3V,1.2V Core Voltage

Commerial and Industrial temperature

grade*

16-bit Video Input Port capable of capturing

HD video

491-pin sBGA package (17x17, .65 mm

pitch)

–

HD resolution Display Subsystem

Serial Communication

8-bit Alpha Blending

•

High-End CAN Controller

10/100 Mbit Ethernet MAC

USB OTG subsystem with standard

DP/DM interface[HS/FS/LS]

•

Video Processing Front End (VPFE) 16-bit

Video Input Port

–

RAW Data Interface

75-MHz Maximum Pixel Clock

Supports REC656/CCIR656 Standard

Supports YCbCr422 Format (8-bit or 16-bit

With Discrete Horizontal and Vertical Sync

Signals)

Generates Optical Black Clamping Signals

Built-in Digital Clamping and Black Level

Compensation

10-bit to 8-bit A-law Compression Hardware

Supports up to 16K Pixels (Image Size) in

Horizontal and Vertical Directions

•

Multiport USB Host Subsystem

[HS/FS/LS]

–

12-/8-Pin ULPI Interface or 6-/4-/3-Pin

•

Four Master/Slave Multichannel Serial

Port Interface (McSPI) Ports

Five Multichannel Buffered Serial Ports

–

512-Byte Transmit/Receive Buffer

(McBSP1/3/4/5)

5K-Byte Transmit/Receive Buffer

(McBSP2)

SIDETONE Core Support (McBSP2

and 3 Only) For Filter, Gain, and Mix

Operations

–

•

System Direct Memory Access (sDMA)

Controller (32 Logical Channels With

Configurable Priority)

–

128-Channel Transmit/Receive Mode

Direct Interface to I2S and PCM

Device and TDM Buses

Comprehensive Power, Reset and Clock

Management

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this document.

POWERVR SGX is a trademark of Imagination Technologies Ltd.

All other trademarks are the property of their respective owners.

PRODUCT PREVIEW information concerns products in the

formative or design phase of development. Characteristic data and

other specifications are design goals. Texas Instruments reserves

the right to change or discontinue these products without notice.

AM3517/05 ARM Microprocessor

SPRS550–OCTOBER 2009

www.ti.com

ARM Cortex^TM-A8 Memory Architecture

–

Interfaces to Double Data Rate (DDR2)

SRAM

SDRAM Memory Scheduler (SMS) and

Rotation Engine

•

–

ARMv7 Architecture

•

Trust Zone

Thumb-2

MMU Enhancements

•

General Purpose Memory Controller (GPMC)

–

16-bit Wide Multiplexed Address/Data Bus

Up to 8 Chip Select Pins With 128M-Byte

Address Space per Chip Select Pin

Glueless Interface to NOR Flash, NAND

Flash (With ECC Hamming Code

Calculation), SRAM and Pseudo-SRAM

Flexible Asynchronous Protocol Control for

Interface to Custom Logic (FPGA, CPLD,

ASICs, etc.)

Nonmultiplexed Address/Data Mode

(Limited 2K-Byte Address Space)

–

In-Order, Dual-Issue, Superscalar

Microprocessor Core

–

NEON Multimedia Architecture

Over 2x Performance of ARMv6 SIMD

Supports Both Integer and Floating Point

SIMD

–

JAZELLE RCT Execution Environment

Architecture

Dynamic Branch Prediction with Branch

Target Address Cache, Global history

buffer and 8 entry return stack

•

Test Interfaces

–

Embedded Trace Macrocell [ETM] support

for Non_invasive Debug

16K-Byte instruction Cache (4-Way set-

associative)

16K-Byte Data Cache (4-Way

Set-Associative)

256K-Byte L2 Cache

IEEE-1149.1 (JTAG) Boundary-Scan

Compatible

Embedded Trace Macro Interface (ETM)

Serial Data Transport Interface (SDTI)

–

•

65-nm CMOS technology

Applications:

•

POWERVR SGX™ Graphics Accelerator

–

Single Board Computers

Industrial and Home Automation

Digital Signage

Point-of-Sale Devices

Portable Media Player

Portable Industrial

Transportation

Navigation

Smart White Goods

Digital TV

Digital Video Camera

Gaming

Notes:

*Operating condition restrictions apply.

**Different memory controller to support

DDR2. New IP support for VPFE, EMAC,

and HECC.

–

Tile Based Architecture Delivering up to 10

MPoly/sec

–

Universal Scalable Shader Engine:

Multi-threaded Engine Incorporating Pixel

and Vertex Shader Functionality

–

Industry Standard API Support: OpenGLES

1.1 and 2.0, OpenVG1.0

Fine Grained Task Switching, Load

Balancing, and Power Management

Programmable, High-Quality Image

Anti-Aliasing

•

Endianess

–

ARM Instructions - Little Endian

ARM Data – Configurable

SDRC Memory Controller

–

16, 32-bit Memory Controller With 1G-Byte

Total Address Space

2

AM3517/05 ARM Microprocessor

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AM3517/05 ARM Microprocessor

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1.2 Description

AM3517/05 high-performance, industrial applications processors with video, image, and graphics

processing sufficient to support the following:

•

Single Board Computers

Home and Industrial automation

Digital Signage

The device supports high-level operating systems (OSs), such as:

•

Linux

Windows CE

The following subsystems are part of the device:

•

Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor

POWERVR SGX™ Graphics Accelerator (AM3517 Device only) Subsystem for 3D graphics

acceleration to support display and gaming effects (3517 only)

•

Display subsystem with several features for multiple concurrent image manipulation, and a

programmable interface supporting a wide variety of displays. The display subsystem also supports

NTSC/PAL video out.

High performance interconnects provide high-bandwidth data transfers for multiple initiators to the

internal and external memory controllers and to on-chip peripherals. The device also offers a

comprehensive clock-management scheme.

AM3517/05 devices are available in a 491-pin sBGA package.

This AM3517/05 data manual presents the electrical and mechanical specifications for the AM3517/05

ARM Microprocessor.

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AM3517/05 ARM Microprocessor

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AM3517/05 ARM Microprocessor

SPRS550–OCTOBER 2009

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1.3 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the AM3517/05 ARM Microprocessor.

CVBS

or

S-Video

LCD Panel

Parallel

USB transceivers /

device ports [3]

MPU

Subsystem

Analog

DAC

ARM Cortex-

A8^TMCore

16K/16K L1$

HS/FS/

LS

USB

Host

Dual Output 3-Layer

Display Processor

(1xGraphics, 2xVideo)

Temporal Dithering

SDTV → QCIF Support

POWERVR

SGX^TM

Graphics

Accelerator

(AM3517 only)

32

USB PHY

USB OTG

Controller

Channel

System

DMA

L2$

256K

64

32

32 32

32

Async

VPFE

HECC

EMAC

64

L3 Interconnect Network-Hierarchial, Performance, and Power Driven

64 32 32

SMS:

32

L4 Interconnect

SDRAM

Memory

Scheduler/

Rotation

132K

On-Chip

BOOT

ROM

64K

On-Chip

RAM

GPMC:

Peripherals:

4xUART, 3xHigh-Speed I2C,

5xMcBSP

(2x with Sidetone/Audio Buffer)

4xMcSPI, 186xGPIO,

3xHigh-Speed MMC/SDIO,

HDQ/1 Wire,

General

Purpose

Memory

Controller

System

Controls

PRCM

SDRC

Controller

DDR PHY

12xGPTimers, 1xWDT,

32K Sync Timer

External

Peripherals

Interfaces

Emulation

Debug: SDTI, ETM, JTAG,

External

DDR2

NAND/NOR/

FLASH,

SRAM

Coresight^TMDAP

SPRS550-006

Figure 1-1. AM3517/05 Functional Block Diagram

4

AM3517/05 ARM Microprocessor

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Contents

1

2

AM3517/05 ARM Microprocessor..................... 1

1.1 Features .............................................. 1

5

VIDEO DAC SPECIFICATIONS....................... 78

5.1 Interface Description ................................ 79

5.2

Electrical Specifications Over Recommended

1.2 Description............................................ 3

1.3 Functional Block Diagram ............................ 4

TERMINAL DESCRIPTION.............................. 6

2.1 Pin Assignments...................................... 6

2.2 Ball Characteristics.................................. 11

2.3 Multiplexing Characteristics ......................... 31

2.4 Signal Description ................................... 38

ELECTRICAL CHARACTERISTICS.................. 59

3.1 Absolute Maximum Ratings ......................... 59

3.2 Recommended Operating Conditions............... 61

3.3 DC Electrical Characteristics........................ 63

3.4 Core Voltage Decoupling............................ 65

3.5 Power-up and Power-down ......................... 67

CLOCK SPECIFICATIONS ............................ 70

4.1 Oscillator ............................................ 72

4.2 Input Clock Specifications........................... 72

4.3 Output Clock Specifications ......................... 73

4.4 DPLL Specifications................................. 75

Operating Conditions................................ 80

5.3

Analog Supply (vdda_dac) Noise Requirements.... 82

5.4 External Component Value Choice ................. 83

TIMING REQUIREMENTS AND SWITCHING

6

CHARACTERISTICS ................................... 84

6.1 Timing Test Conditions.............................. 84

6.2 Interface Clock Specifications....................... 84

6.3 Timing Parameters .................................. 85

6.4 External Memory Interfaces ......................... 86

6.5 Video Interfaces.................................... 119

6.6 Serial Communications Interfaces ................. 124

6.7 Removable Media Interfaces ...................... 160

6.8 Test Interfaces ..................................... 174

PACKAGE CHARACTERISTICS.................... 180

7.1 Package Thermal Resistance...................... 180

7.2 Device Support..................................... 180

3

4

7

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Contents

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AM3517/05 ARM Microprocessor

SPRS550–OCTOBER 2009

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2 TERMINAL DESCRIPTION

2.1 Pin Assignments

2.1.1 Pin Map (Top View)

Figure 2-1 through Figure 2-4 show the top view of the 491-pin sPBGA package [ZCN] package pin

assignments in four quadrants (A, B, C, and D).

Note: A pin with an "NC" designator indicates No Connection. For proper device operation, these pins

must be left unconnected.

6

TERMINAL DESCRIPTION

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25

24

23

22

21

20

19

18

17

16

15

14

dss_acbias

dss_pclk

etk_d15

etk_d12

etk_d8

etk_d5

etk_ctl

mcspi2_cs1

mcspi1_cs3

mcspi1_cs2

mcspi1_clk

AE

VSS

AE

AD

dss_data1

dss_data4

dss_data0

dss_data3

dss_vsync

dss_data2

dss_hsync

etk_d13

etk_d14

etk_d9

etk_d10

etk_d11

etk_d6

etk_d0

etk_d1

etk_clk

mcspi2_clk

mcspi1_simo

mcspi1_cs1

AD

AC

mcspi2_simo mcspi1_somi

dss_data6

dss_data9

dss_data5

dss_data8

etk_d7

etk_d2

etk_d3

mcspi2_somi

mcspi2_cs0

mcspi1_cs0

AB

AA

AB

AA

VDDS_

DPLL_MPU

_USBHOST

dss_data7

uart1_tx

dss_data11

dss_data16

dss_data13

dss_data18

dss_data12

dss_data17

dss_data10

dss_data15

uart1_cts

uart1_rx

uart1_rts

etk_d4

VDDS

Y

VDDSHV

Y

W

dss_data14

W

dss_data20

dss_data19

jtag_ntrst

jtag_tdo

VDD_CORE VDD_CORE

V

U

T

VSS

V

U

T

dss_data21

jtag_rtck

jtag_tck

dss_data23

dss_data22

VDD_CORE

VDDS

VDDSHV

VSS

jtag_emu0

jtag_tdi

VDD_CORE

VDDSHV

jtag_tms_tmsc

jtag_emu1

mcbsp1_clkr

mcbsp_clks

VDD_CORE VDD_CORE

R

P

VSS

R

P

mcbsp1_fsx

mcbsp1_dr

mcbsp1_dx

mcbsp1_fsr

Reserved

VDDSHV

VSS

VDDS_DPLL_

PER_CORE

sys_clkout1 mcbsp1_clkx

N

VSS

VDDS

VSS

N

sys_clkout2

sys_clkreq

M

VDD_CORE

VSS

17

VSS

14

M

VSS

16

VSS

15

25

24

23

22

21

20

19

18

Figure 2-1. ZCN Pin Map [Quadrant A]

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AM3517/05 ARM Microprocessor

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13

12

11

10

9

8

7

6

5

4

3

2

1

rmii_50mhz

_clk

rmii_mdio

_data

mmc2_dat7 mmc2_dat3 mmc2_cmd mmc1_dat7 mmc1_dat2

rmii_txd1

ccdc_data4 ccdc_data1

ccdc_data3 ccdc_data0

ccdc_wen

ccdc_hs

AE

VSS

AE

rmii_mdio

_clk

mmc2_dat6 mmc2_dat2

mmc2_dat5 mmc2_dat1

mmc2_clk

mmc1_dat6 mmc1_dat1

mmc1_dat5 mmc1_dat0

rmii_txen

rmii_txd0

rmii_rxer

ccdc_vd

ccdc_pclk

sys_boot7

ccdc_field

sys_boot6

AD

AC

AD

AC

ccdc_data7 ccdc_data2

sys_boot8

mmc2_dat4 mmc2_dat0

VDDS_SRAM CAP_VDD_

mmc1_dat4 mmc1_cmd

mmc1_dat3 mmc1_clk

rmii_crs_dv

rmii_rxd1

rmii_rxd0

ccdc_data6

sys_boot5

sys_boot2

sys_boot4

sys_boot1

sys_nirq

AB

AA

Y

sys_boot3

AA

_MPU

SRAM_MPU

sys

_nreswarm

sys

_nrespwron

ccdc_data5

sys_boot0

i2c3_scl

i2c1_scl

Y

VDDSHV

VDDS

i2c3_sda

VDDSHV

i2c2_sda

VDDSHV

i2c2_scl

W

V

VDDSHV

W

V

VDDSHV

VDD_CORE VDD_CORE

i2c1_sda

hecc1_rxd

hecc1_txd

Reserved

gpmc_nwp

gpmc_noe

VSS

VDDSHV

Reserved

gpmc_wait3

gpmc_nbe1

U

T

VSS

U

VDD_CORE VDD_CORE

gpmc_wait2 gpmc_wait1 gpmc_wait0

VSS

VDDSHV

T

gpmc_nbe0

_cle

gpmc_nadv

_ale

gpmc_nwe

VDDS

R

P

VSS

R

uart3_tx

_irtx

uart3_rx

_irrx

VSS

P

uart3_cts

gpmc_ncs6 gpmc_ncs7

_sd

uart3_cts

_rctx

gpmc_clk

N

M

VSS

VDDSHV

N

gpmc_ncs2 gpmc_ncs3

gpmc_ncs4 gpmc_ncs5

VSS

10

VSS

9

VSS

8

VDDSHV

M

13

12

11

7

6

5

4

3

2

1

Figure 2-2. ZCN Pin Map [Quadrant B]

8

TERMINAL DESCRIPTION

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25

24

23

22

21

20

19

18

17

15

14

16

hdq_sio

VDD_CORE

L

K

J

NC

VDDSHV

VSS

L

NC

VDDSOSC

VSS

sys_xtalin

sys_32k

NC

VDD_CORE VDD_CORE

VDDSHV

VSS

K

tv_out1

tv_vfb1

VDD_CORE

VSSOSC

sys_xtalout

usb0_id

VSS

VDDSHV

VDDS

VSS

J

VDD_CORE

VDDSHV

VDD_CORE

tv_out2

usb0_vbus

usb0_dm

H

G

F

tv_vfb2

VSS

H

G

F

E

D

C

B

A

NC

tv_vref

VSSA_DAC

VDDA_DAC

VDDS

VDDA1P8V

_USBPHY

VDDS

Reserved

VDDS

CAP_

VDDA3P3V

_USBPHY

usb0_dp

VDDA1P2LDO

_USBPHY

uart2_cts

uart2_rts

VREFSSTL

sdrc_ncas

sdrc_cke0

sdrc_nras

sdrc_nwe

VDDS

Reserved

VDDS_SRAM

_CORE_BG

CAP_VDD_

usb0_drvvbus

mcbsp2_fsx

mcbsp2_clkx

mcbsp2_dr

uart2_tx

uart2_rx

E

D

C

B

A

sdrc_d4

sdrc_d5

sdrc_d6

sdrc_d7

SRAM_CORE

mcbsp2_dx

mcbsp3_dr

mcbsp3_dx

sdrc_d2

sdrc_d9

sdrc_d11

sdrc_d12

sdrc_d13

mcbsp3_fsx

sdrc_dm0

sdrc_d3

sdrc_d10

mcbsp4_clkx mcbsp4_dx

sdrc_d0

sdrc_dqs0p

sdrc_d8

sdrc_dqs1p

sdrc_dm1

sdrc_strben

_dly0

mcbsp3_clkx

mcbsp4_dr

mcbsp4_fsx

sdrc_d1

sdrc_dqs0n

sdrc_strben0

sdrc_dqs1n

sdrc_d15

sdrc_ncs1

VSS

sdrc_d14

25

24

23

22

21

20

19

18

17

15

14

16

Figure 2-3. ZCN Pin Map [Quadrant C]

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AM3517/05 ARM Microprocessor

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13

12

11

10

9

8

7

6

5

4

3

2

1

VDD_CORE VDD_CORE

gpmc_ncs0 gpmc_ncs1

L

VSS

L

VSS

gpmc_d12

gpmc_d8

gpmc_d13

gpmc_d9

gpmc_d14

gpmc_d10

gpmc_d5

gpmc_d3

gpmc_a8

gpmc_a2

scrc_d29

sdrc_d28

gpmc_d15

gpmc_d11

gpmc_d6

gpmc_d4

gpmc_a9

gpmc_a3

sdrc_dm3

sdrc_d31

K

VSS

VDDSHV

gpmc_d7

K

J

VDD_CORE VDD_CORE

J

H

G

F

VSS

VDDS

VSS

H

G

F

E

D

C

B

A

gpmc_a10

gpmc_a5

gpmc_d0

gpmc_d1

gpmc_a6

gpmc_d2

gpmc_a7

gpmc_a1

VDDS

gpmc_a4

sdrc_d19

sdrc_d18

VDDS

sdrc_ncs0

sdrc_ba2

sdrc_ba1

sdrc_nclk

sdrc_a4

sdrc_a3

sdrc_a2

sdrc_a1

sdrc_a9

sdrc_a8

sdrc_a7

sdrc_a6

sdrc_dm2

sdrc_a14

sdrc_odt0

sdrc_a13

E

D

C

B

A

sdrc_d21

sdrc_d20

sdrc_d23

sdrc_d27

sdrc_d26

ddr_padref

sdrc_a11

sdrc_d17

sdrc_dqs2n sdrc_d22

sdrc_24

sdrc_dqs3n sdrc_d30

sdrc_strben

_dly1

sdrc_clk

13

sdrc_ba0

sdrc_a0

11

sdrc_a5

10

sdrc_a10

sdrc_a12

sdrc_d16

sdrc_dqs2p sdrc_strben1

sdrc_d25

sdrc_dqs3p

VSS

1

12

9

8

7

6

5

4

3

2

Figure 2-4. ZCN Pin Map [Quadrant D]

10

TERMINAL DESCRIPTION

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2.2 Ball Characteristics

Table 2-1 describes the terminal characteristics and the signals multiplexed on each pin for the ZCN

package. The following list describes the table column headers.

1. BALL LOCATION: Ball number(s) on the bottom side associated with each signal(s) on the bottom.

2. PIN NAME: Names of signals multiplexed on each ball (also notice that the name of the pin is the

signal name in mode 0).

Note: Table 2-1 does not take into account subsystem pin multiplexing options. Subsystem pin

multiplexing options are described in Section 2.4, Signal Descriptions.

3. MODE: Multiplexing mode number.

a. Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the pin

corresponds to the name of the pin. There is always a function mapped on the primary mode.

Notice that primary mode is not necessarily the default mode.

Note: The default mode is the mode which is automatically configured on release of the internal

GLOBAL_PWRON reset; also see the RESET REL. MODE column.

b. Modes 1 to 7 are possible modes for alternate functions. On each pin, some modes are effectively

used for alternate functions, while some modes are not used and do not correspond to a functional

configuration.

4. TYPE: Signal direction

–

I = Input

O = Output

I/O = Input/Output

D = Open drain

DS = Differential

A = Analog

Note: In the safe_mode, the buffer is configured in high-impedance.

5. BALL RESET STATE: The state of the terminal at reset (power up).

–

0: The buffer drives V_OL(pulldown/pullup resistor not activated)

0(PD): The buffer drives V_OLwith an active pulldown resistor.

1: The buffer drives V_OH(pulldown/pullup resistor not activated)

1(PU): The buffer drives V_OHwith an active pullup resistor.

Z: High-impedance

–

L: High-impedance with an active pulldown resistor

H : High-impedance with an active pullup resistor

6. BALL RESET REL. STATE: The state of the terminal at reset release.

–

0: The buffer drives V_OL(pulldown/pullup resistor not activated)

0(PD): The buffer drives V_OLwith an active pulldown resistor.

1: The buffer drives V_OH(pulldown/pullup resistor not activated)

1(PU): The buffer drives V_OHwith an active pullup resistor.

Z: High-impedance

–

L: High-impedance with an active pulldown resistor

H : High-impedance with an active pullup resistor

7. RESET REL. MODE: This mode is automatically configured on release of the internal

GLOBAL_PWRON reset.

8. POWER: The voltage supply that powers the terminal’s I/O buffers.

9. VOLTAGE: Supply voltage for associated pin.

10. HYS: Indicates if the input buffer is with hysteresis.

11. LOAD: Load capacitance of the associated output buffer.

12. PULL U/D - TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and

pulldown resistors can be enabled or disabled via software.

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13. IO CELL: IO cell information.

Note: Configuring two pins to the same input signal is not supported as it can yield unexpected results.

This can be easily prevented with the proper software configuration.

Table 2-1. Ball Characteristics (ZCN Pkg.)

BALL

PIN NAME

MODE [3]

TYPE [4]

BALL

RESET REL. POWER [8] VOLTAGE

HYS [10]

LOAD (pF) PULL U/D

IO CELL [13]

LOCATION [2]

[1]

RESET

STATE [5]

RESET REL. MODE [7]

STATE [6]

[9]

[11]

TYPE [12]

B21

A21

D20

C20

E19

D19

C19

B19

B18

D17

C17

D16

C16

B16

A16

A15

A7

sdrc_d0

0

IO

O

L

Z

0

VDDS

1.8V

Yes

No

4

8

PU/ PD

LVCMOS

sdrc_d1

sdrc_d2

sdrc_d3

sdrc_d4

sdrc_d5

sdrc_d6

sdrc_d7

sdrc_d8

sdrc_d9

sdrc_d10

sdrc_d11

sdrc_d12

sdrc_d13

sdrc_d14

sdrc_d15

sdrc_d16

sdrc_d17

sdrc_d18

sdrc_d19

sdrc_d20

sdrc_d21

sdrc_d22

sdrc_d23

sdrc_d24

sdrc_d25

sdrc_d26

sdrc_d27

sdrc_d28

sdrc_d29

sdrc_d30

sdrc_d31

sdrc_ba0

sdrc_ba1

sdrc_ba2

sdrc_a0

sdrc_a1

sdrc_a2

sdrc_a3

sdrc_a4

sdrc_a5

sdrc_a6

sdrc_a7

sdrc_a8

sdrc_a9

sdrc_a10

sdrc_a11

sdrc_a12

sdrc_a13

B7

D7

E7

C6

D6

B5

C5

B4

A3

B3

C3

C2

D2

B1

C1

A12

C13

D13

A11

B11

C11

D11

E11

A10

B10

C10

D10

E10

A9

O

No

O

No

O

No

O

No

O

No

O

No

O

No

O

No

O

No

O

No

O

No

O

No

O

No

B9

O

No

A8

O

No

B8

O

No

12

TERMINAL DESCRIPTION

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SPRS550–OCTOBER 2009

Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL

PIN NAME

MODE [3]

TYPE [4]

BALL

RESET REL. POWER [8] VOLTAGE

HYS [10]

LOAD (pF) PULL U/D

IO CELL [13]

LOCATION [2]

[1]

RESET

STATE [5]

RESET REL. MODE [7]

STATE [6]

[9]

[11]

TYPE [12]

D8

sdrc_a14

0

7

O

IO

O

L

Z

0

7

VDDS

1.8V

No

8

PU/ PD

LVCMOS

E13

A14

A13

B13

D14

sdrc_ncs0

sdrc_ncs1

sdrc_clk

Z

No

Z

No

Z

Yes

No

sdrc_nclk

sdrc_cke0

Z

PD

Yes

sdrc_cke0_s

afe

C14

E14

B14

C21

B15

E8

sdrc_nras

0

O

L

Z

0

VDDS

1.8V

No

8

PU/ PD

LVCMOS

sdrc_ncas

sdrc_nwe

O

No

O

No

sdrc_dm0

O

No

sdrc_dm1

O

No

sdrc_dm2

O

No

D1

sdrc_dm3

O

No

B20

B17

A6

sdrc_dqs0p

sdrc_dqs1p

sdrc_dqs2p

sdrc_dqs3p

sdrc_dqs0n

sdrc_dqs1n

sdrc_dqs2n

sdrc_dqs3n

sdrc_odt0

IO

Yes

A2

A20

A17

B6

B2

C8

A19

A18

sdrc_strben0

sdrc_strben_

dly0

A5

A4

sdrc_strben1

0

L

Z

0

VDDS

1.8V

8

PU/ PD

LVCMOS

sdrc_strben_

dly1

B12

E3

ddr_padref

gpmc_a1

gpio_34

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

PWR

O

VDDS

1.8V

L

PD

PU

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

IO

safe_mode

gpmc_a2

gpio_35

E2

E1

F7

F6

F4

F3

F2

O

L

VDDSHV

1.8V/3.3V

IO

safe_mode

gpmc_a3

gpio_36

O

L

IO

safe_mode

gpmc_a4

gpio_37

O

L

IO

safe_mode

gpmc_a5

gpio_38

O

L

IO

safe_mode

gpmc_a6

gpio_39

O

H

IO

safe_mode

gpmc_a7

gpio_40

O

IO

safe_mode

gpmc_a8

gpio_41

O

IO

safe_mode

Submit Documentation Feedback

TERMINAL DESCRIPTION

13

AM3517/05 ARM Microprocessor

SPRS550–OCTOBER 2009

www.ti.com

Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL

PIN NAME

MODE [3]

TYPE [4]

BALL

RESET REL. POWER [8] VOLTAGE

HYS [10]

LOAD (pF) PULL U/D

IO CELL [13]

LOCATION [2]

[1]

RESET

STATE [5]

RESET REL. MODE [7]

STATE [6]

[9]

[11]

TYPE [12]

F1

gpmc_a9

0

1

O

I

H

PU

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

sys_

ndmareq2

gpio_42

4

7

0

1

IO

safe_mode

gpmc_a10

G6

O

I

H

PU

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

sys_

ndmareq3

gpio_43

4

7

0

4

0

4

0

4

0

4

0

4

0

4

0

4

0

4

0

4

0

2

IO

safe_mode

gpmc_d0

gpmc_d1

gpmc_d2

gpmc_d3

gpmc_d4

gpmc_d5

gpmc_d6

gpmc_d7

gpmc_d8

gpio_44

G5

G4

G3

G2

G1

H2

H1

J5

IO

O

H

PU

0

VDDSHV

1.8V/3.3V

30

PU/ PD

LVCMOS

Yes

J4

J3

J2

J1

K4

K3

K2

K1

gpmc_d9

gpio_45

H

PU

0

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

gpmc_d10

gpio_46

gpmc_d11

gpio_47

gpmc_d12

gpio_48

gpmc_d13

gpio_49

gpmc_d14

gpio_50

gpmc_d15

gpio_51

L2

L1

gpmc_ncs0

gpmc_ncs1

gpio_52

H

Z

0

VDDSHV

1.8V/3.3V

No

30

NA

LVCMOS

O

Yes

PU/ PD

IO

O

M4

gpmc_ncs2

H

PU

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

gpt9_pwm_e

vt

IO

gpio_53

4

7

0

1

IO

safe_mode

gpmc_ncs3

M3

O

I

H

PU

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

sys_

ndmareq0

gpt10_pwm_

evt

2

IO

gpio_54

4

7

0

1

safe_mode

gpmc_ncs4

M2

O

I

H

PU

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

sys_

ndmareq1

gpt9_pwm_e

vt

3

IO

gpio_55

4

7

0

safe_mode

gpmc_ncs5

M1

O

H

PU

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

14

TERMINAL DESCRIPTION

Submit Documentation Feedback

AM3517/05 ARM Microprocessor

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SPRS550–OCTOBER 2009

Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL

PIN NAME

MODE [3]

TYPE [4]

BALL

RESET REL. POWER [8] VOLTAGE

HYS [10]

LOAD (pF) PULL U/D

IO CELL [13]

LOCATION [2]

[1]

RESET

STATE [5]

RESET REL. MODE [7]

STATE [6]

[9]

[11]

TYPE [12]

sys_

ndmareq2

1

3

I

gpt10_pwm_

evt

IO

gpio_56

4

7

0

1

safe_mode

gpmc_ncs6

N5

O

I

H

PU

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

sys_

ndmareq3

gpt11_pwm_

evt

3

IO

gpio_57

4

7

0

1

3

safe_mode

gpmc_ncs7

gpmc_io_dir

N4

O

H

PU

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

O

gpt8_pwm_e

vt

IO

gpio_58

4

7

0

4

0

IO

safe_mode

gpmc_clk

gpio_59

N1

R1

O

L

Z

0

VDDSHV

1.8V/3.3V

Yes

No

30

PU/ PD

LVCMOS

IO

O

gpmc_nadv_

ale

R2

R3

R4

gpmc_noe

gpmc_nwe

0

O

H

L

Z

0

VDDSHV

1.8V/3.3V

No

30

PU/ PD

LVCMOS

No

gpmc_nbe0_

cle

Yes

gpio_60

4

0

4

7

0

4

0

1

4

7

0

1

4

7

0

1

IO

O

T1

T2

gpmc_nbe1

gpio_61

L

PD

Z

7

0

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

IO

safe_mode

gpmc_nwp

gpio_62

O

IO

I

T3

T4

gpmc_wait0

gpmc_wait1

uart4_tx

H

PU

0

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

I

O

IO

gpio_63

safe_mode

gpmc_wait2

uart4_rx

T5

U1

I

H

PU

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

I

gpio_64

IO

safe_mode

gpmc_wait3

I

sys_

ndmareq1

uart3_cts_rct

x

2

I

gpio_65

4

7

0

4

7

0

4

7

0

4

7

IO

safe_mode

dss_pclk

AE23

AD22

AD23

O

H

PU

7

VDDSHV

1.8V/3.3V

Yes

20

PU/ PD

LVCMOS

gpio_66

IO

safe_mode

dss_hsync

gpio_67

O

IO

safe_mode

dss_vsync

gpio_68

O

IO

safe_mode

Submit Documentation Feedback

TERMINAL DESCRIPTION

15

AM3517/05 ARM Microprocessor

SPRS550–OCTOBER 2009

www.ti.com

Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL

PIN NAME

MODE [3]

TYPE [4]

BALL

RESET REL. POWER [8] VOLTAGE

HYS [10]

LOAD (pF) PULL U/D

IO CELL [13]

LOCATION [2]

[1]

RESET

STATE [5]

RESET REL. MODE [7]

STATE [6]

[9]

[11]

TYPE [12]

AE24

dss_acbias

0

4

7

0

2

3

O

L

PD

7

VDDSHV

1.8V/3.3V

Yes

20

PU/ PD

LVCMOS

gpio_69

IO

safe_mode

dss_data0

uart1_cts

AD24

O

I

1.8V/3.3V

Yes

20

PU/ PD

LVCMOS

dssvenc656_

data0

I

gpio_70

4

7

0

2

3

IO

safe_mode

dss_data1

uart1_rts

AD25

O

I

L

PD

7

VDDSHV

1.8V/3.3V

Yes

20

PU/ PD

LVCMOS

dssvenc656_

data1

gpio_71

4

7

0

3

IO

safe_mode

dss_data2

AC23

AC24

AC25

O

I

L

PD

7

VDDSHV

1.8V/3.3V

Yes

20

PU/ PD

LVCMOS

dssvenc656_

data2

gpio_72

4

7

0

3

IO

safe_mode

dss_data3

O

I

dssvenc656_

data3

gpio_73

4

7

0

2

3

IO

safe_mode

dss_data4

uart3_rx_ irrx

O

I

dssvenc656_

data4

I

gpio_74

4

7

0

2

3

IO

safe_mode

dss_data5

uart3_tx_ irtx

AB24

AB25

AA23

O

I

L

PD

7

VDDSHV

1.8V/3.3V

Yes

20

PU/ PD

LVCMOS

dssvenc656_

data5

gpio_75

4

7

0

2

3

IO

safe_mode

dss_data6

uart1_tx

O

I

dssvenc656_

data6

gpio_76

4

7

0

2

3

IO

safe_mode

dss_data7

uart1_rx

O

I

dssvenc656_

data7

I

gpio_77

4

7

0

4

7

0

4

7

0

4

IO

safe_mode

dss_data8

gpio_78

AA24

AA25

Y22

O

L

PD

7

VDDSHV

1.8V/3.3V

Yes

20

PU/ PD

LVCMOS

IO

safe_mode

dss_data9

gpio_79

O

IO

safe_mode

dss_data10

gpio_80

O

IO

16

TERMINAL DESCRIPTION

Submit Documentation Feedback

AM3517/05 ARM Microprocessor

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SPRS550–OCTOBER 2009

Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL

PIN NAME

MODE [3]

TYPE [4]

BALL

RESET REL. POWER [8] VOLTAGE

HYS [10]

LOAD (pF) PULL U/D

IO CELL [13]

LOCATION [2]

[1]

RESET

STATE [5]

RESET REL. MODE [7]

STATE [6]

[9]

[11]

TYPE [12]

safe_mode

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

2

3

4

7

0

2

Y23

Y24

Y25

W21

W22

W23

W24

W25

dss_data11

gpio_81

O

L

PD

7

VDDSHV

1.8V/3.3V

Yes

20

PU/ PD

LVCMOS

IO

safe_mode

dss_data12

gpio_82

O

1.8V/3.3V

20

PU/ PD

IO

safe_mode

dss_data13

gpio_83

O

IO

safe_mode

dss_data14

gpio_84

O

IO

safe_mode

dss_data15

gpio_85

O

IO

safe_mode

dss_data16

gpio_86

O

IO

safe_mode

dss_data17

gpio_87

O

IO

safe_mode

dss_data18

mcspi3_clk

dss_data4

gpio_88

O

IO

O

IO

safe_mode

dss_data19

V24

O

L

PD

7

VDDSHV

1.8V/3.3V

Yes

20

PU/ PD

LVCMOS

mcspi3_

simo

IO

dss_data3

gpio_89

3

4

7

0

2

O

IO

safe_mode

dss_data20

V25

O

L

PD

7

VDDSHV

1.8V/3.3V

Yes

20

PU/ PD

LVCMOS

mcspi3_

somi

IO

dss_data2

gpio_90

3

4

7

0

2

3

4

7

0

2

3

4

7

0

3

4

7

0

O

IO

safe_mode

dss_data21

mcspi3_cs0

dss_data1

gpio_91

U21

U22

U23

O

L

PD

7

VDDSHV

1.8V/3.3V

Yes

20

PU/ PD

LVCMOS

IO

O

IO

safe_mode

dss_data22

mcspi3_cs1

dss_data0

gpio_92

O

IO

safe_mode

dss_data23

dss_data5

gpio_93

O

IO

safe_mode

tv_out2

H24

K21

O

0

VDDA_DAC 1.8V

NA

10-bit DAC

tv_out1

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TERMINAL DESCRIPTION

17

AM3517/05 ARM Microprocessor

SPRS550–OCTOBER 2009

www.ti.com

Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL

PIN NAME

MODE [3]

TYPE [4]

BALL

RESET REL. POWER [8] VOLTAGE

HYS [10]

LOAD (pF) PULL U/D

IO CELL [13]

LOCATION [2]

[1]

RESET

STATE [5]

RESET REL. MODE [7]

STATE [6]

[9]

[11]

TYPE [12]

K20

H23

H20

AD2

tv_vfb1

0

4

7

0

1

2

3

4

7

0

2

4

7

0

2

4

7

0

1

2

4

7

0

3

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

O

I

Z

L

NA

PD

0

7

VDDA_DAC 1.8V

NA

10-bit DAC

LVCMOS

tv_vfb2

NA

tv_vref

NA

ccdc_pclk

gpio_94

IO

VDDSHV

1.8V/3.3V

Yes

15

PU/ PD

safe_mode

ccdc_field

ccdc_data8

uart4_tx

AD1

IO

I

L

PD

7

VDDSHV

1.8V/3.3V

PU/ PD

LVCMOS

O

i2c3_scl

OD

IO

gpio_95

safe_mode

ccdc_ hd

uart4_rts

AE2

AD3

AE3

IO

O

L

PD

7

VDDSHV

1.8V/3.3V

Yes

15

PU/ PD

PU/PD

LVCMOS

gpio_96

IO

safe_mode

ccdc_vd

IO

I

uart4_cts

gpio_97

IO

safe_mode

ccdc_wen

ccdc_data9

uart4_rx

IO

I

gpio_98

IO

safe_mode

ccdc_data0

i2c3_sda

AD4

I

L

PD

7

VDDSHV

1.8V/3.3V

Yes

15

PU/PD

LVCMOS

IOD

I

gpio_99

safe_mode

ccdc_data1

gpio_100

safe_mode

ccdc_data2

gpio_101

safe_mode

ccdc_data3

gpio_102

safe_mode

ccdc_data4

gpio_103

safe_mode

ccdc_data5

gpio_104

safe_mode

ccdc_data6

gpio_105

safe_mode

ccdc_data7

gpio_106

safe_mode

AE4

AC5

AD5

AE5

Y6

I

L

H

PD

PU

7

VDDSHV

1.8V/3.3V

Yes

15

25

PU/PD

PU/ PD

PU/PD

LVCMOS

I

IO

I

IO

I

IO

I

IO

AB6

AC6

AE6

I

IO

I

IO

rmii_mdio_da 0

ta

O

Yes

8

ccdc_data8

gpio_107

1

4

7

I

IO

safe_mode

18

TERMINAL DESCRIPTION

Submit Documentation Feedback

AM3517/05 ARM Microprocessor

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SPRS550–OCTOBER 2009

Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL

PIN NAME

MODE [3]

TYPE [4]

BALL

RESET REL. POWER [8] VOLTAGE

HYS [10]

LOAD (pF) PULL U/D

IO CELL [13]

LOCATION [2]

[1]

RESET

STATE [5]

RESET REL. MODE [7]

STATE [6]

[9]

[11]

TYPE [12]

AD6

rmii_mdio_cl

k

0

I

H

PU

7

VDDSHV

1.8V/3.3V

Yes

8

25

PU/PD

LVCMOS

ccdc_data9

gpio_108

safe_mode

rmii_rxd0

ccdc_data10

gpio_109

safe_mode

rmii_rxd1

ccdc_data11

gpio_110

safe_mode

rmii_crs_dv

ccdc_data12

gpio_111

safe_mode

rmii_rxer

1

4

7

0

1

4

7

0

1

4

7

0

1

4

7

0

1

4

7

0

I

IO

Y7

I

H

PU

7

VDDSHV

1.8V/3.3V

Yes

25

PU/ PD

PU/PD

LVCMOS

I

IO

AA7

AB7

AC7

AD7

AE7

I

IO

I

IO

O

I

ccdc_data13

gpio_167

safe_mode

rmii_txd0

IO

O

I

ccdc_ data14 1

gpio_126

4

7

0

1

4

7

0

4

7

0

IO

safe_mode

rmii_txd1

O

I

ccdc_data15

gpio_112

I

safe_mode

rmii_txen

AD8

AE8

O

I

H

PU

7

VDDSHV

1.8V/3.3V

25

PU/PD

PU/ PD

LVCMOS

gpio_113

NA

safe_mode

rmii_50mhz_

clk

I

gpio_114

4

7

0

4

7

0

NA

safe_mode

mcbsp2_fsx

gpio_116

D25

C25

IO

L

PD

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

safe_mode

mcbsp2_

clkx

IO

Yes

gpio_117

4

7

0

4

7

0

4

7

0

4

7

0

4

7

safe_mode

mcbsp2_dr

gpio_118

B25

D24

AA9

AB9

I

L

PD

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

IO

safe_mode

mcbsp2_dx

gpio_119

IO

safe_mode

mmc1_clk

gpio_120

O

IO

safe_mode

mmc1_cmd

gpio_121

IO

safe_mode

Submit Documentation Feedback

TERMINAL DESCRIPTION

19

AM3517/05 ARM Microprocessor

SPRS550–OCTOBER 2009

www.ti.com

Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL

PIN NAME

MODE [3]

TYPE [4]

BALL

RESET REL. POWER [8] VOLTAGE

HYS [10]

LOAD (pF) PULL U/D

IO CELL [13]

LOCATION [2]

[1]

RESET

STATE [5]

RESET REL. MODE [7]

STATE [6]

[9]

[11]

TYPE [12]

AC9

AD9

AE9

AA10

mmc1_dat0

0

1

4

7

0

1

4

7

0

1

4

7

0

1

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

1

2

4

7

0

1

IO

L

PD

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

mcspi2_clk

gpio_122

safe_mode

mmc1_dat1

mcspi2_simo

gpio_123

IO

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

safe_mode

mmc1_dat2

mcspi2_somi

gpio_124

IO

safe_mode

mmc1_dat3

mcspi2_cs0

gpio_125

IO

O

IO

safe_mode

mmc1_dat4

gpio_126

AB10

AC10

AD10

AE10

AD11

IO

L

PD

7

VDDSHV

1.8V/3.3V

No

Yes

30

PU/ PD

LVCMOS

safe_mode

mmc1_dat5

gpio_127

IO

safe_mode

mmc1_dat6

gpio_128

IO

safe_mode

mmc1_dat7

gpio_129

IO

safe_mode

mmc2_clk

mcspi3_clk

uart4_cts

O

IO

I

gpio_130

IO

safe_mode

mmc2_ cmd

AE11

IO

H

PU

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

mcspi3_

simo

uart4_rts

2

4

7

0

1

O

gpio_131

IO

safe_mode

mmc2_ dat0

AB12

IO

H

PU

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

mcspi3_

somi

uart4_tx

2

4

7

0

2

4

7

0

1

4

7

0

1

O

gpio_132

IO

safe_mode

mmc2_ dat1

uart4_rx

AC12

AD12

IO

I

H

PU

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

gpio_133

IO

safe_mode

mmc2_ dat2

mcspi3_cs1

gpio_134

IO

O

IO

safe_mode

mmc2_ dat3

mcspi3_cs0

AE12

IO

20

TERMINAL DESCRIPTION

Submit Documentation Feedback

AM3517/05 ARM Microprocessor

www.ti.com

SPRS550–OCTOBER 2009

Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL

PIN NAME

MODE [3]

TYPE [4]

BALL

RESET REL. POWER [8] VOLTAGE

HYS [10]

LOAD (pF) PULL U/D

IO CELL [13]

LOCATION [2]

[1]

RESET

STATE [5]

RESET REL. MODE [7]

STATE [6]

[9]

[11]

TYPE [12]

gpio_135

4

7

0

IO

safe_mode

AB13

mmc2_ dat4

IO

O

L

PD

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

mmc2_dir_da 1

t0

mmc3_dat0

gpio_136

3

4

7

0

IO

safe_mode

mmc2_ dat5

AC13

IO

O

L

PD

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

mmc2_dir_da 1

t1

mmc3_dat1

gpio_137

3

4

IO

mm_fsusb3_r 6

xdp

safe_mode

7

0

1

AD13

mmc2_ dat6

IO

O

L

PD

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

mmc2_dir_

cmd

mmc3_dat2

gpio_138

3

4

7

0

1

3

4

IO

safe_mode

mmc2_ dat7

mmc2_ clkin

mmc3_dat3

gpio_139

AE13

IO

I

L

PD

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

IO

mm_fsusb3_r 6

xdm

safe_mode

mcbsp3_dx

uart2_cts

7

0

1

4

7

0

1

4

7

0

B24

C24

A24

IO

I

L

PD

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

gpio_140

IO

safe_mode

mcbsp3_dr

uart2_rts

I

O

IO

gpio_141

safe_mode

mcbsp3_

clkx

IO

uart2_tx

1

4

7

0

1

4

7

0

1

2

O

gpio_142

safe_mode

mcbsp3_fsx

uart2_rx

IO

C23

F20

IO

I

L

PD

PU

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

gpio_143

safe_mode

uart2_cts

mcbsp3_dx

IO

I

H

IO

gpt9_pwm_e

vt

gpio_144

safe_mode

uart2_rts

4

7

0

1

2

IO

F19

O

I

H

PU

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

mcbsp3_dr

gpt10_pwm_

evt

IO

gpio_145

4

IO

Submit Documentation Feedback

TERMINAL DESCRIPTION

21

AM3517/05 ARM Microprocessor

SPRS550–OCTOBER 2009

www.ti.com

Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL

PIN NAME

MODE [3]

TYPE [4]

BALL

RESET REL. POWER [8] VOLTAGE

HYS [10]

LOAD (pF) PULL U/D

IO CELL [13]

LOCATION [2]

[1]

RESET

STATE [5]

RESET REL. MODE [7]

STATE [6]

[9]

[11]

TYPE [12]

safe_mode

7

0

1

E24

uart2_tx

O

H

PU

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

mcbsp3_

clkx

IO

gpt11_pwm

_evt

2

IO

gpio_146

safe_mode

uart2_rx

4

7

0

1

2

E23

I

H

PU

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

mcbsp3_fsx

IO

gpt8_pwm_e

vt

gpio_147

safe_mode

uart1_tx

4

7

0

4

7

0

4

7

0

4

7

0

2

3

4

7

0

IO

AA19

Y19

O

L

PD

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

gpio_148

safe_mode

uart1_rts

IO

O

gpio_149

safe_mode

uart1_cts

gpio_150

safe_mode

uart1_rx

IO

Y20

I

IO

W20

I

mcbsp1_ clkr

mcspi4_clk

gpio_151

safe_mode

I

IO

B23

mcbsp4_

clkx

IO

L

PD

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

gpio_152

4

IO

mm_fsusb3_t 6

xse0

safe_mode

mcbsp4_dr

gpio_153

7

0

4

A23

B22

A22

I

L

PD

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

IO

mm_fsusb3_r 6

xrcv

safe_mode

mcbsp4_dx

gpio_154

7

0

4

IO

mm_fsusb3_t 6

xdat

safe_mode

mcbsp4_fsx

gpio_155

7

0

4

IO

mm_fsusb3_t 6

xen_ n

safe_mode

mcbsp1_ clkr

mcspi4_clk

gpio_156

7

0

1

4

7

0

4

7

0

R25

P21

IO

safe_mode

mcbsp1_fsr

gpio_157

IO

L

PD

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

safe_mode

mcbsp1_dx

P22

IO

22

TERMINAL DESCRIPTION

Submit Documentation Feedback

AM3517/05 ARM Microprocessor

www.ti.com

SPRS550–OCTOBER 2009

Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL

PIN NAME

MODE [3]

TYPE [4]

BALL

RESET REL. POWER [8] VOLTAGE

HYS [10]

LOAD (pF) PULL U/D

IO CELL [13]

LOCATION [2]

[1]

RESET

STATE [5]

RESET REL. MODE [7]

STATE [6]

[9]

[11]

TYPE [12]

mcspi4_

1

IO

simo

mcbsp3_dx

gpio_158

safe_mode

mcbsp1_dr

2

4

7

0

1

IO

P23

I

L

PD

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

mcspi4_

somi

IO

mcbsp3_dr

gpio_159

2

4

7

0

4

5

7

0

1

2

4

7

0

I

IO

safe_mode

mcbsp_clks

gpio_160

P25

P24

I

L

PD

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

IO

I

uart1_cts

safe_mode

mcbsp1_fsx

mcspi4_cs0

mcbsp3_fsx

gpio_161

IO

safe_mode

N24

mcbsp1_

clkx

IO

L

PD

PU

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

mcbsp3_

clkx

2

gpio_162

4

7

0

safe_mode

N2

uart3_cts_

rctx

IO

H

PU/ PD

gpio_163

4

7

0

4

7

0

4

7

0

4

7

0

1

0

1

0

safe_mode

uart3_rts_ sd

gpio_164

N3

P1

P2

O

H

PU

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

IO

safe_mode

uart3_rx_ irrx

gpio_165

I

IO

safe_mode

uart3_tx_ irtx

gpio_166

O

IO

safe_mode

usb0_dp

F25

F24

IO

O

IO

I

5.0V

Yes

PU/ PD

LVCMOS

uart3_tx_ irtx

usb0_dm

uart3_rx_ irrx

usb0_vbus

G24

G25

E25

IO

VDDA3P3V_ 5.0V

USBPHY

Yes

PU/ PD

LVCMOS

usb0_id

0

IO

O

VDDA3P3V_ 3.3V

USBPHY

usb0_drvvbu

s

L

PD

7

VDDSHV

1.8V/3.3V

30

uart3_tx_ irtx

gpio_125

2

4

7

0

2

4

7

0

O

IO

safe_mode

hecc1_ txd

uart3_rx_ irrx

gpio_130

V2

V3

IO

I

H

PU

7

VDDSHV

1.8V/3.3V

Yes

24

PU/ PD

LVCMOS

IO

safe_mode

hecc1_ rxd

IO

Submit Documentation Feedback

TERMINAL DESCRIPTION

23

AM3517/05 ARM Microprocessor

SPRS550–OCTOBER 2009

www.ti.com

Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL

PIN NAME

MODE [3]

TYPE [4]

BALL

RESET REL. POWER [8] VOLTAGE

HYS [10]

LOAD (pF) PULL U/D

IO CELL [13]

LOCATION [2]

[1]

RESET

STATE [5]

RESET REL. MODE [7]

STATE [6]

[9]

[11]

TYPE [12]

uart3_rts_ sd

2

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

1

2

3

4

7

0

1

4

7

0

O

gpio_131

safe_mode

i2c1_scl

IO

V4

V5

W1

OD

IOD

OD

IO

H

PU

0

7

VDDSHV

1.8V/3.3V

Yes

40

PU/ PD

Open Drain

i2c1_ sda

i2c2_scl

gpio_168

safe_mode

i2c2_sda

W2

W4

W5

L25

IOD

IO

H

PU

7

VDDSHV

1.8V/3.3V

Yes

40

PU/ PD

Open Drain

LVCMOS

gpio_183

safe_mode

i2c3_scl

OD

IO

gpio_184

safe_mode

i2c3_sda

IOD

IO

gpio_185

safe_mode

hdq_sio

IO

I

sys_altclk

i2c2_sccbe

i2c3_sccbe

gpio_170

safe_mode

mcspi1_clk

mmc2_dat4

gpio_171

safe_mode

O

IO

AE14

AD15

IO

L

PD

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

mcspi1_

simo

IO

mmc2_dat5

gpio_172

1

4

7

0

IO

safe_mode

AC15

mcspi1_

somi

IO

L

PD

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

mmc2_dat6

gpio_173

1

4

7

0

1

4

7

0

3

4

7

0

3

4

7

0

2

IO

safe_mode

mcspi1_cs0

mmc2_dat7

gpio_174

AB15

AD14

AE15

AE16

IO

H

PU

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

safe_mode

mcspi1_cs1

mmc3_cmd

gpio_175

O

IO

safe_mode

mcspi1_cs2

mmc3_clk

gpio_176

O

IO

safe_mode

mcspi1_cs3

O

hsusb2_tll_

data2

IO

hsusb2_

data2

3

4

IO

gpio_177

24

TERMINAL DESCRIPTION

Submit Documentation Feedback

AM3517/05 ARM Microprocessor

www.ti.com

SPRS550–OCTOBER 2009

Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL

PIN NAME

MODE [3]

TYPE [4]

BALL

RESET REL. POWER [8] VOLTAGE

HYS [10]

LOAD (pF) PULL U/D

IO CELL [13]

LOCATION [2]

[1]

RESET

STATE [5]

RESET REL. MODE [7]

STATE [6]

[9]

[11]

TYPE [12]

mm_fsusb2_t 5

IO

xdat

safe_mode

mcspi2_clk

7

0

2

AD16

IO

L

PD

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

hsusb2_tll_

data7

hsusb2_

data7

3

IO

gpio_178

4

7

0

safe_mode

AC16

mcspi2_

simo

IO

L

PD

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

gpt9_pwm_e

vt

1

2

3

hsusb2_tll_

data4

hsusb2_

data4

gpio_179

4

7

0

safe_mode

AB16

mcspi2_

somi

IO

L

PD

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

gpt10_pwm_

evt

1

2

3

hsusb2_tll_

data5

hsusb2_

data5

gpio_180

4

7

0

1

safe_mode

mcspi2_cs0

AA16

IO

H

PU

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

gpt11_pwm_

evt

hsusb2_tll_

data6

2

3

IO

hsusb2_

data6

gpio_181

4

7

0

1

safe_mode

mcspi2_cs1

AE17

O

L

PD

7

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

gpt8_pwm_e

vt

IO

hsusb2_tll_

data3

2

3

4

IO

hsusb2_

data3

gpio_182

IO

mm_fsusb2_t 5

xen_ n

safe_mode

sys_32k

7

0

4

0

4

7

0

K24

K25

H25

M24

I

Z

L

Z

0

VDDSHV

VDDSOSC

VDDSHV

1.8V/3.3V

1.8V

Yes

NA

30

PU/ PD

LVCMOS

sys_xtalin

sys_xtalout

sys_clkreq

gpio_1

I

O

IO

I

1.8V

NA

1.8V/3.3V

Yes

30

Y1

sys_nirq

H

PU

7

VDDSHV

1.8V/3.3V

Yes

PU/ PD

LVCMOS

gpio_0

IO

safe_mode

Y2

Y3

sys_

nrespwron

I

Z

L

Z

0

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

sys_

0

IO

PD

nreswarm

Submit Documentation Feedback

TERMINAL DESCRIPTION

25

AM3517/05 ARM Microprocessor

SPRS550–OCTOBER 2009

www.ti.com

Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL

PIN NAME

MODE [3]

TYPE [4]

BALL

RESET REL. POWER [8] VOLTAGE

HYS [10]

LOAD (pF) PULL U/D

IO CELL [13]

LOCATION [2]

[1]

RESET

STATE [5]

RESET REL. MODE [7]

STATE [6]

[9]

[11]

TYPE [12]

gpio_30

4

0

4

0

4

0

4

0

4

0

IO

I

Open Drain

LVCMOS

Y4

sys_boot0

gpio_2

Z

0

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

IO

I

AA1

AA2

AA3

AB1

sys_boot1

gpio_3

LVCMOS

IO

I

sys_boot2

gpio_4

IO

I

sys_boot3

gpio_5

IO

I

sys_boot4

mmc2_dir_da 1

t2

O

gpio_6

4

0

IO

I

AB2

sys_boot5

Z

0

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

mmc2_dir_da 1

t3

O

gpio_7

4

0

4

0

4

7

0

4

7

0

IO

I

AC1

sys_boot6

gpio_8

Z

VDDSHV

1.8V/3.3V

Yes

30

PU/ PD

LVCMOS

IO

I

AC2

AC3

N25

sys_boot7

sys_boot8

sys_clkout1

gpio_10

Z

H

Z

0

VDDSHV

1.8V/3.3V

Yes

30

PU/PD

PU/ PD

LVCMOS

I

Z

0

O

IO

PD

0/7

safe_mode

sys_clkout2

gpio_186

safe_mode

jtag_ntrst

jtag_tck

M25

O

L

PD

7

VDDSHV

1.8V/3.3V

Yes

10

PU/ PD

LVCMOS

IO

U24

U25

T21

T22

I

L

H

PD

Z

0

VDDSHV

1.8V/3.3V

Yes

20

PU/ PD

LVCMOS

I

jtag_rtck

O

IO

jtag_tms_tms 0

c

PU

T23

T24

T25

jtag_tdi

0

4

0

4

0

1

I

H

L

PU

Z

0

VDDSHV

1.8V/3.3V

Yes

20

PU/ PD

LVCMOS

jtag_tdo

jtag_emu0

gpio_11

jtag_emu1

gpio_31

etk_clk

O

IO

O

H

PU

R24

H

PU

0

4

VDDSHV

1.8V/3.3V

Yes

20

PU/ PD

LVCMOS

AD17

9, 25

mcbsp5_

clkx

IO

mmc3_clk

hsusb1_stp

gpio_12

2

3

4

6

O

IO

I

hsusb1_tll_st

p

AE18

etk_ctl

0

2

3

4

O

H

PU

4

VDDSHV

1.8V/3.3V

Yes

9, 25

PU/ PD

LVCMOS

mmc3_cmd

hsusb1_clk

gpio_13

IO

O

IO

mm_fsusb1_r 5

xdp

hsusb1_tll_cl

k

6

O

AD18

etk_d0

0

1

O

H

PU

4

VDDSHV

1.8V/3.3V

Yes

9, 25

PU/ PD

LVCMOS

mcspi3_

simo

IO

26

TERMINAL DESCRIPTION

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Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL

PIN NAME

MODE [3]

TYPE [4]

BALL

RESET REL. POWER [8] VOLTAGE

HYS [10]

LOAD (pF) PULL U/D

IO CELL [13]

LOCATION [2]

[1]

RESET

STATE [5]

RESET REL. MODE [7]

STATE [6]

[9]

[11]

TYPE [12]

mmc3_dat4

2

3

IO

hsusb1_

data0

gpio_14

4

IO

mm_fsusb1_r 5

xrcv

hsusb1_tll_

data0

6

IO

AC18

etk_d1

0

1

O

H

PU

4

VDDSHV

1.8V/3.3V

Yes

9, 25

PU/ PD

LVCMOS

mcspi3_

somi

IO

hsusb1_

data1

3

IO

gpio_15

4

IO

mm_fsusb1_t 5

xse0

hsusb1_tll_

data1

6

IO

AB18

etk_d2

0

1

3

O

H

PU

4

VDDSHV

1.8V/3.3V

Yes

9, 25

PU/ PD

LVCMOS

mcspi3_cs0

IO

hsusb1_

data2

gpio_16

4

IO

mm_fsusb1_t 5

xdat

hsusb1_tll_d

ata2

6

IO

AA18

etk_d3

0

1

2

3

O

L

PU

PD

4

VDDSHV

1.8V/3.3V

Yes

9, 25

PU/ PD

LVCMOS

mcspi3_clk

mmc3_dat3

IO

hsusb1_

data7

gpio_17

4

6

IO

hsusb1_tll_

data7

Y18

etk_d4

0

1

2

3

O

I

mcbsp5_dr

mmc3_dat0

IO

hsusb1_

data4

gpio_18

4

6

IO

hsusb1_tll_

data4

AE19

AD19

AB19

etk_d5

0

1

2

3

O

mcbsp5_fsx

mmc3_dat1

IO

hsusb1_

data5

gpio_19

4

6

IO

hsusb1_tll_

data5

etk_d6

0

1

2

3

O

mcbsp5_dx

mmc3_dat2

IO

hsusb1_

data6

gpio_20

4

6

IO

hsusb1_tll_

data6

etk_d7

0

1

O

mcspi3_cs1

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27

AM3517/05 ARM Microprocessor

SPRS550–OCTOBER 2009

www.ti.com

Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL

PIN NAME

MODE [3]

TYPE [4]

BALL

RESET REL. POWER [8] VOLTAGE

HYS [10]

LOAD (pF) PULL U/D

IO CELL [13]

LOCATION [2]

[1]

RESET

STATE [5]

RESET REL. MODE [7]

STATE [6]

[9]

[11]

TYPE [12]

mmc3_dat7

2

3

IO

hsusb1_

data3

gpio_21

4

IO

mm_fsusb1_t 5

xen_n

hsusb1_tll_

data3

6

IO

AE20

etk_d8

0

1

O

I

L

PD

4

VDDSHV

1.8V/3.3V

Yes

9, 25

PU/ PD

LVCMOS

sys_drm_

msecure

mmc3_dat6

hsusb1_dir

gpio_22

2

3

4

6

IO

I

IO

O

hsusb1_tll_di

r

AD20

etk_d9

0

1

O

L

PD

4

VDDSHV

1.8V/3.3V

Yes

9, 25

PU/ PD

LVCMOS

sys_secure_i

ndic ator

mmc3_dat5

hsusb1_nxt

gpio_23

2

3

4

IO

I

IO

mm_fsusb1_r 5

xdm

hsusb1_tll_n

xt

6

O

AC20

etk_d10

0

2

3

4

6

O

I

L

PD

4

VDDSHV

1.8V/3.3V

Yes

9, 25

PU/ PD

LVCMOS

uart1_rx

hsusb2_clk

gpio_24

O

IO

O

hsusb2_tll_cl

k

AB20

etk_d11

0

1

3

4

O

L

PD

4

VDDSHV

1.8V/3.3V

Yes

9, 25

PU/ PD

LVCMOS

mcspi3_clk

hsusb2_stp

gpio_25

IO

O

IO

mm_fsusb2_r 5

xdp

hsusb2_tll_st

p

6

I

AE21

AD21

etk_d12

0

3

4

6

O

I

L

PD

4

VDDSHV

1.8V/3.3V

Yes

9, 25

PU/ PD

LVCMOS

hsusb2_dir

gpio_26

IO

O

hsusb2_tll_di

r

etk_d13

0

3

4

O

I

9, 25

hsusb2_nxt

gpio_27

IO

mm_fsusb2_r 5

xdm

hsusb2_tll_n

xt

6

O

AC21

etk_d14

0

3

O

L

PD

4

VDDSHV

1.8V/3.3V

Yes

9, 25

PU/ PD

LVCMOS

hsusb2_

data0

IO

gpio_28

4

IO

mm_fsusb2_r 5

xrcv

hsusb2_tll_

data0

6

IO

O

AE22

etk_d15

0

L

PD

4

VDDSHV

1.8V/3.3V

Yes

9, 25

PU/ PD

LVCMOS

28

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Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL

LOCATION [2]

[1]

PIN NAME

MODE [3]

TYPE [4]

BALL

RESET

STATE [5]

BALL

RESET REL. POWER [8] VOLTAGE

HYS [10]

LOAD (pF) PULL U/D

[11] TYPE [12]

IO CELL [13]

RESET REL. MODE [7]

STATE [6]

[9]

hsusb2_

data1

3

4

IO

gpio_29

IO

mm_fsusb2_t 5

xse0

hsusb2_tll_

data1

6

IO

V16, V15,

V11, V10,

U16, U15,

U11, U10,

T18, T17, T9,

T8, R18,

VDD_CORE

0

PWR

1.2V

R17, R9, R8,

M18, L18,

L9, L8, K18,

K17, K9, K8,

J16, J15,

J11, J10,

H15, H11,

H10

AA13

VDDS_SRA

M_MPU

0

PWR

1.8V

E17

VDDS_SRA

M_CORE_B

G0

AA12

E16

CAP_VDD_S 0

RAM_MPU

PWR

1.8V

1.2V

1.8V

CAP_VDD_S 0

RAM_CORE

AA15

VDDS_DPLL

_MPU_USB

HOST

0

N20

VDDS_DPLL

_PER_CORE

0

PWR

1.8V

H21

F23

VDDA_DAC

0

PWR

1.8V

3.3V

VDDA3P3V_

USBPHY

G22

F22

VDDA1P8V_

USBPHY

0

PWR

1.8V

1.2V

CAP_VDDA1 0

P2LDO_USB

PHY

Y16, Y15,

VDDSHV

0

PWR

1.8V/3.3V

Y13, Y12,

Y10, W16,

W15, W13,

W12,W10,

W9, W6, V7,

V6, U19,

T20, T19, T7,

T6, R7, R6,

P20, P19,

N19, N7, N6,

M7, M6, M5,

L19, K19,

K7, K6, K5,

J7, H18, H17

Y9, W18,

U20, R5,

VDDS

0

PWR

1.8V

H16, H8,

G17, G16,

G14, G13,

G11, G10,

G8, F16,

F13, F11,

F10, F8, N22

F14

L20

VREFSSTL

VDDSOSC

0

PWR

1.8V

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AM3517/05 ARM Microprocessor

SPRS550–OCTOBER 2009

www.ti.com

Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL

LOCATION [2]

[1]

PIN NAME

MODE [3]

TYPE [4]

BALL

RESET

STATE [5]

BALL

RESET REL. POWER [8] VOLTAGE

HYS [10]

LOAD (pF) PULL U/D

[11] TYPE [12]

IO CELL [13]

RESET REL. MODE [7]

STATE [6]

[9]

AE25, AE1, VSS

V18, V17,

V14, V13,

V12, V9, V8,

U18, U17,

U14, U13,

U12, U9, U8,

T14, T13,

0

GND

T12, R16,

R15, R14,

R13, R12,

R11, R10,

P18, P17,

P16, P15,

P14, P13,

P12, P11,

P10, P9, P8,

N18, N17,

N14, N13,

N12, N9, N8,

M17, M16,

M15, M14,

M13,M12,

M11, M10,

M9, M8, L17,

L16, L15,

L14, L13,

L12, L11,

L10, K14,

K13, K12,

J18, J17,

J14, J13,

J12, J9, J8,

H14, H13,

H12, H9,

A25, A1, N23

H22

VSSA_DAC

0

GND

L24, L23,

L22, L21,

L20, K23,

K22, H19

NC⁽¹⁾

F17⁽²⁾

U2⁽³⁾

Reserved

V1⁽³⁾

N21⁽⁴⁾

G20⁽⁵⁾

G21⁽⁵⁾

(1) "NC" indicates "No Connect". For proper device operation, these pins must be left unconnected.

(2) For proper device operation, this pin should be left unconnected.

(3) For proper device operation, this pin must be pulled up via a 10k-Ω resistor.

(4) For proper device operation, this pin must be connected to ground via a 1µF capacitor.

(5) For proper device operation, this pin must be tied to VSS.

30

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2.3 Multiplexing Characteristics

Table Table 2-2 provides descriptions of the AM3517/05 pin multiplexing on the ZCN package.

Table 2-2. Multiplexing Characteristics (ZCN Pkg.)

PIN MULTIPLEXING CONFIGURATIONS

Ball No.

B21

A21

D20

C20

E19

D19

C19

B19

B18

D17

C17

D16

C16

B16

A16

A15

A7

Option 0

sdrc_d0

sdrc_d1

sdrc_d2

sdrc_d3

sdrc_d4

sdrc_d5

sdrc_d6

sdrc_d7

sdrc_d8

sdrc_d9

sdrc_d10

sdrc_d11

sdrc_d12

sdrc_d13

sdrc_d14

sdrc_d15

sdrc_d16

sdrc_d17

sdrc_d18

sdrc_d19

sdrc_d20

sdrc_d21

sdrc_d22

sdrc_d23

sdrc_d24

sdrc_d25

sdrc_d26

sdrc_d27

sdrc_d28

sdrc_d29

sdrc_d30

sdrc_d31

sdrc_ba0

sdrc_ba1

sdrc_ba2

sdrc_a0

sdrc_a1

sdrc_a2

sdrc_a3

sdrc_a4

sdrc_a5

sdrc_a6

sdrc_a7

sdrc_a8

sdrc_a9

sdrc_a10

Option 1

Option 2

Option 3

Option 4

Option 5

Option 6

Option 7

B7

D7

E7

C6

D6

B5

C5

B4

A3

B3

C3

C2

D2

B1

C1

A12

C13

D13

A11

B11

C11

D11

E11

A10

B10

C10

D10

E10

A9

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SPRS550–OCTOBER 2009

www.ti.com

Table 2-2. Multiplexing Characteristics (ZCN Pkg.) (continued)

PIN MULTIPLEXING CONFIGURATIONS

Option 2 Option 3 Option 4

Ball No.

B9

Option 0

sdrc_a11

Option 1

Option 5

Option 6

Option 7

A8

sdrc_a12

B8

sdrc_a13

D8

sdrc_a14

E13

A14

A13

B13

D14

C14

E14

B14

C21

B15

E8

sdrc_ncs0

sdrc_ncs1

sdrc_clk

sdrc_nclk

sdrc_cke0

sdrc_nras

sdrc_ncas

sdrc_nwe

sdrc_dm0

sdrc_dm1

sdrc_dm2

sdrc_dm3

sdrc_dqs0p

sdrc_dqs1p

sdrc_dqs2p

sdrc_dqs3p

sdrc_dqs0n

sdrc_dqs1n

sdrc_dqs2n

sdrc_dqs3n

sdrc_odt0

sdrc_strben0

ddr_cke0_safe

D1

B20

B17

A6

A2

A20

A17

B6

B2

C8

A19

A18

sdrc_strben_dly

0

A5

A4

sdrc_strben1

sdrc_strben_dly

1

E3

E2

E1

F7

F6

F4

F3

F2

F1

G6

G5

G4

G3

G2

G1

H2

H1

J5

gpmc_a1

gpmc_a2

gpmc_a3

gpmc_a4

gpmc_a5

gpmc_a6

gpmc_a7

gpmc_a8

gpmc_a9

gpmc_a10

gpmc_d0

gpmc_d1

gpmc_d2

gpmc_d3

gpmc_d4

gpmc_d5

gpmc_d6

gpmc_d7

gpmc_d8

gpmc_d9

gpio_34

safe_mode

gpio_35

gpio_36

gpio_37

gpio_38

gpio_39

gpio_40

gpio_41

gpio_42

gpio_43

sys_ndmareq2

sys_ndmareq3

J4

gpio_44

gpio_45

J3

32

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Table 2-2. Multiplexing Characteristics (ZCN Pkg.) (continued)

PIN MULTIPLEXING CONFIGURATIONS

Ball No.

J2

Option 0

gpmc_d10

gpmc_d11

gpmc_d12

gpmc_d13

gpmc_d14

gpmc_d15

gpmc_ncs0

gpmc_ncs1

gpmc_ncs2

gpmc_ncs3

gpmc_ncs4

gpmc_ncs5

gpmc_ncs6

gpmc_ncs7

gpmc_clk

Option 1

Option 2

Option 3

Option 4

gpio_46

Option 5

Option 6

Option 7

J1

gpio_47

gpio_48

gpio_49

gpio_50

gpio_51

K4

K3

K2

K1

L2

L1

gpio_52

gpio_53

gpio_54

gpio_55

M4

gpt9_pwm_evt

gpt10_pwm_evt

safe_mode

M3

sys_ndmareq0

sys_ndmareq1

sys_ndmareq2

sys_ndmareq3

gpmc_io_dir

M2

gpt9_pwm_evt

M1

gpt10_pwm_evt gpio_56

gpt11_pwm_evt gpio_57

N5

N4

gpt8_pwm_evt

gpio_58

gpio_59

N1

R1

gpmc_nadv_ale

gpmc_noe

gpmc_nwe

gpmc_nbe0_cle

gpmc_nbe1

gpmc_nwp

gpmc_wait0

gpmc_wait1

gpmc_wait2

gpmc_wait3

dss_pclk

R2

R3

R4

gpio_60

gpio_61

gpio_62

T1

safe_mode

T2

T3

T4

uart4_tx

gpio_63

gpio_64

gpio_65

gpio_66

gpio_67

gpio_68

gpio_69

gpio_70

gpio_71

gpio_72

gpio_73

gpio_74

gpio_75

gpio_76

gpio_77

gpio_78

gpio_79

gpio_80

gpio_81

gpio_82

gpio_83

gpio_84

gpio_85

gpio_86

gpio_87

gpio_88

gpio_89

gpio_90

safe_mode

T5

uart4_rx

U1

sys_ndmareq1

uart3_cts_rctx

AE23

AD22

AD23

AE24

AD24

AD25

AC23

AC24

AC25

AB24

AB25

AA23

AA24

AA25

Y22

Y23

Y24

Y25

W21

W22

W23

W24

W25

V24

V25

hw_dbg12

dss_hsync

dss_vsync

dss_acbias

dss_data0

dss_data1

dss_data2

dss_data3

dss_data4

dss_data5

dss_data6

dss_data7

dss_data8

dss_data9

dss_data10

dss_data11

dss_data12

dss_data13

dss_data14

dss_data15

dss_data16

dss_data17

dss_data18

dss_data19

dss_data20

hw_dbg13

uart1_cts

uart1_rts

uart3_rx_irrx

uart3_tx_irtx

uart1_tx

hw_dbg14

hw_dbg15

hw_dbg16

hw_dbg17

uart1_rx

mcspi3_clk

dss_data4

dss_data3

dss_data2

mcspi3_simo

mcspi3_somi

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33

AM3517/05 ARM Microprocessor

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Table 2-2. Multiplexing Characteristics (ZCN Pkg.) (continued)

PIN MULTIPLEXING CONFIGURATIONS

Ball No.

U21

U22

U23

K20

Option 0

dss_data21

dss_data22

dss_data23

tv_vfb1

Option 1

Option 2

mcspi3_cs0

mcspi3_cs1

Option 3

dss_data1

Option 4

gpio_91

Option 5

Option 6

Option 7

safe_mode

dss_data0

dss_data5

gpio_92

gpio_93

safe_mode

K21

tv_out1

H23

H24

H20

AD2

AD1

AE2

AD3

AE3

AD4

AE4

AC5

AD5

AE5

Y6

tv_vfb2

tv_out2

tv_vref

ccdc_pclk

ccdc_field

ccdc_hd

gpio_94

hw_dbg0

safe_mode

ccdc_data8

ccdc_data9

uart4_tx

uart4_rts

uart4_cts

uart4_rx

i2c3_scl

gpio_95

hw_dbg1

gpio_96

ccdc_vd

gpio_97

hw_dbg2

hw_dbg3

ccdc_wen

ccdc_data0

ccdc_data1

ccdc_data2

ccdc_data3

ccdc_data4

ccdc_data5

ccdc_data6

ccdc_data7

gpio_98

i2c3_sda

gpio_99

gpio_100

gpio_101

gpio_102

gpio_103

gpio_104

gpio_105

gpio_106

gpio_107

gpio_108

gpio_109

gpio_110

gpio_111

gpio_167

gpio_126

gpio_112

gpio_113

gpio_114

gpio_116

gpio_117

gpio_118

gpio_119

gpio_120

gpio_121

gpio_122

gpio_123

gpio_124

gpio_125

gpio_126

gpio_127

gpio_128

gpio_129

gpio_130

gpio_131

gpio_132

gpio_133

gpio_134

hw_dbg4

hw_dbg5

hw_dbg6

hw_dbg7

AB6

AC6

AE6

AD6

Y7

rmii_mdio_data ccdc_data8

rmii_mdio_clk ccdc_data9

rmii_rxd0

rmii_rxd1

ccdc_data10

ccdc_data11

ccdc_data12

ccdc_data13

ccdc_data14

ccdc_data15

hw_dbg8

hw_dbg9

AA7

AB7

AC7

AD7

AE7

AD8

AE8

D25

C25

B25

rmii_crs_dv

rmii_rxer

hw_dbg10

hw_dbg11

rmii_txd0

rmii_txd1

rmii_txen

rmii_50mhz_clk

mcbsp2_fsx

mcbsp2_clkx

mcbsp2_dr

mcbsp2_dx

mmc1_clk

D24

AA9

AB9

AC9

AD9

AE9

AA10

AB10

AC10

AD10

AE10

AD11

AE11

AB12

AC12

AD12

mmc1_cmd

mmc1_dat0

mmc1_dat1

mmc1_dat2

mmc1_dat3

mmc1_dat4

mmc1_dat5

mmc1_dat6

mmc1_dat7

mmc2_clk

mcspi2_clk

mcspi2_simo

mcspi2_somi

mcspi2_cs0

mcspi3_clk

uart4_cts

uart4_rts

uart4_tx

uart4_rx

mmc2_cmd

mmc2_dat0

mmc2_dat1

mmc2_dat2

mcspi3_simo

mcspi3_somi

mcspi3_cs1

34

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Table 2-2. Multiplexing Characteristics (ZCN Pkg.) (continued)

PIN MULTIPLEXING CONFIGURATIONS

Ball No.

AE12

Option 0

mmc2_dat3

mmc2_dat4

mmc2_dat5

Option 1

mcspi3_cs0

Option 2

Option 3

Option 4

gpio_135

Option 5

Option 6

Option 7

safe_mode

AB13

mmc2_dir_dat0

mmc2_dir_dat1

mmc3_dat0

mmc3_dat1

gpio_136

gpio_137

AC13

mm_fsusb3_rxd safe_mode

p

AD13

AE13

mmc2_dat6

mmc2_dat7

mmc2_dir_cmd

mmc2_clkin

mmc3_dat2

mmc3_dat3

gpio_138

gpio_139

safe_mode

mm_fsusb3_rxd safe_mode

m

B24

C24

A24

C23

F20

F19

E24

E23

AA19

Y19

Y20

W20

B23

mcbsp3_dx

mcbsp3_dr

mcbsp3_clkx

mcbsp3_fsx

uart2_cts

uart2_rts

uart2_cts

gpio_140

gpio_141

gpio_142

gpio_143

gpio_144

gpio_145

gpio_146

gpio_147

gpio_148

gpio_149

gpio_150

gpio_151

gpio_152

safe_mode

uart2_rts

uart2_tx

uart2_rx

mcbsp3_dx

mcbsp3_dr

mcbsp3_clkx

mcbsp3_fsx

gpt9_pwm_evt

gpt10_pwm_evt

gpt11_pwm_evt

gpt8_pwm_evt

uart2_tx

uart2_rx

uart1_tx

uart1_rts

uart1_cts

uart1_rx

mcbsp1_clkr

mcspi4_clk

mcbsp4_clkx

mm_fsusb3_txs safe_mode

e0

A23

B22

A22

mcbsp4_dr

mcbsp4_dx

mcbsp4_fsx

gpio_153

gpio_154

gpio_155

mm_fsusb3_rxr safe_mode

cv

mm_fsusb3_txd safe_mode

at

mm_fsusb3_txe safe_mode

n_n

R25

P21

P22

P23

P25

P24

N24

N2

mcbsp1_clkr

mcbsp1_fsr

mcbsp1_dx

mcbsp1_dr

mcbsp_clks

mcbsp1_fsx

mcbsp1_clkx

uart3_cts_rctx

uart3_rts_sd

uart3_rx_irrx

uart3_tx_irtx

usb0_dp

mcspi4_clk

gpio_156

gpio_157

gpio_158

gpio_159

gpio_160

gpio_161

gpio_162

gpio_163

gpio_164

gpio_165

gpio_166

safe_mode

mcspi4_simo

mcspi4_somi

mcbsp3_dx

mcbsp3_dr

uart1_cts

mcspi4_cs0

mcbsp3_fsx

mcbsp3_clkx

N3

P1

P2

F25

F24

G24

G25

E25

V2

uart3_rx_irrx

uart3_tx_irtx

usb0_dm

usb0_vbus

usb0_id

usb0_drvvbus

hecc1_txd

hecc1_rxd

i2c1_scl

uart3_tx_irtx

uart3_rx_irrx

uart3_rts_sd

safe_mode

gpio_130

gpio_131

V3

V4

V5

i2c1_sda

W1

W2

W4

W5

L25

i2c2_scl

gpio_168

gpio_183

gpio_184

gpio_185

gpio_170

safe_mode

i2c2_sda

i2c3_scl

i2c3_sda

hdq_sio

sys_altclk

i2c2_sccbe

i2c3_sccbe

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AM3517/05 ARM Microprocessor

SPRS550–OCTOBER 2009

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Table 2-2. Multiplexing Characteristics (ZCN Pkg.) (continued)

PIN MULTIPLEXING CONFIGURATIONS

Ball No.

AE14

AD15

AC15

AB15

AD14

AE15

AE16

Option 0

mcspi1_clk

mcspi1_simo

mcspi1_somi

mcspi1_cs0

mcspi1_cs1

mcspi1_cs2

mcspi1_cs3

Option 1

mmc2_dat4

mmc2_dat5

mmc2_dat6

mmc2_dat7

Option 2

Option 3

Option 4

gpio_171

Option 5

Option 6

Option 7

safe_mode

gpio_172

gpio_173

gpio_174

gpio_175

gpio_176

gpio_177

safe_mode

mmc3_cmd

mmc3_clk

hsusb2_tll_data hsusb2_data2

2

mm_fsusb2_txd

at

AD16

AC16

AB16

AA16

AE17

mcspi2_clk

mcspi2_simo

mcspi2_somi

mcspi2_cs0

mcspi2_cs1

hsusb2_tll_data hsusb2_data7

7

gpio_178

gpio_179

gpio_180

gpio_181

gpio_182

safe_mode

gpt9_pwm_evt

hsusb2_tll_data hsusb2_data4

4

gpt10_pwm_evt hsusb2_tll_data hsusb2_data5

5

gpt11_pwm_evt hsusb2_tll_data hsusb2_data6

6

gpt8_pwm_evt

hsusb2_tll_data hsusb2_data3

3

mm_fsusb2_txe

n_n

Y1

sys_nirq

sys_clkout2

etk_clk

gpio_0

safe_mode

hw_dbg0

M25

gpio_186

gpio_12

gpio_13

AD17

AE18

mcbsp5_clkx

mmc3_clk

hsusb1_stp

hsusb1_clk

hsusb1_tll_stp

etk_ctl

mmc3_cmd

mm_fsusb1_rxd hsusb1_tll_clk

p

hw_dbg1

AD18

AC18

AB18

AA18

Y18

etk_d0

etk_d1

etk_d2

etk_d3

etk_d4

etk_d5

etk_d6

etk_d7

etk_d8

etk_d9

mcspi3_simo

mcspi3_somi

mcspi3_cs0

mcspi3_clk

mcbsp5_dr

mcbsp5_fsx

mcbsp5_dx

mcspi3_cs1

mmc3_dat4

hsusb1_data0

hsusb1_data1

hsusb1_data2

hsusb1_data7

hsusb1_data4

hsusb1_data5

hsusb1_data6

hsusb1_data3

hsusb1_dir

gpio_14

gpio_15

gpio_16

gpio_17

gpio_18

gpio_19

gpio_20

gpio_21

gpio_22

gpio_23

mm_fsusb1_rxr hsusb1_tll_data hw_dbg2

cv

0

mm_fsusb1_txs hsusb1_tll_data hw_dbg3

e0

1

mm_fsusb1_txd hsusb1_tll_data hw_dbg4

at

2

mmc3_dat3

mmc3_dat0

mmc3_dat1

mmc3_dat2

mmc3_dat7

hsusb1_tll_data hw_dbg5

7

hsusb1_tll_data hw_dbg6

4

AE19

AD19

AB19

AE20

AD20

hsusb1_tll_data hw_dbg7

5

hsusb1_tll_data hw_dbg8

6

mm_fsusb1_txe hsusb1_tll_data hw_dbg9

n_n

3

sys_drm_msec mmc3_dat6

ure

hsusb1_tll_dir

hw_dbg10

hw_dbg11

sys_secure_indi mmc3_dat5

cator

hsusb1_nxt

mm_fsusb1_rxd hsusb1_tll_nxt

m

AC20

AB20

etk_d10

etk_d11

uart1_rx

hsusb2_clk

hsusb2_stp

gpio_24

gpio_25

hsusb2_tll_clk

hw_dbg12

hw_dbg13

mcspi3_clk

mm_fsusb2_rxd hsusb2_tll_stp

p

AE21

AD21

etk_d12

etk_d13

hsusb2_dir

hsusb2_nxt

gpio_26

gpio_27

hsusb2_tll_dir

hw_dbg14

hw_dbg15

mm_fsusb2_rxd hsusb2_tll_nxt

m

AC21

AE22

etk_d14

etk_d15

hsusb2_data0

hsusb2_data1

gpio_28

gpio_29

mm_fsusb2_rxr hsusb2_tll_data hw_dbg16

cv

0

mm_fsusb2_txs hsusb2_tll_data hw_dbg17

e0

1

K24

K25

H25

M24

sys_32k

sys_xtalin

sys_xtalout

sys_clkreq

gpio_1

36

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Table 2-2. Multiplexing Characteristics (ZCN Pkg.) (continued)

PIN MULTIPLEXING CONFIGURATIONS

Option 2 Option 3 Option 4

Ball No.

Y2

Option 0

sys_nrespwron

sys_nreswarm

sys_boot0

sys_boot1

sys_boot2

sys_boot3

sys_boot4

sys_boot5

sys_boot6

sys_boot7

sys_boot8

sys_clkout1

jtag_ntrst

Option 1

Option 5

Option 6

Option 7

Y3

gpio_30

Y4

gpio_2

gpio_3

gpio_4

gpio_5

gpio_6

gpio_7

gpio_8

AA1

AA2

AA3

AB1

AB2

AC1

AC2

AC3

N25

U24

U25

T21

T22

T23

T24

T25

R24

B12

mmc2_dir_dat2

mmc2_dir_dat3

gpio_10

safe_mode

jtag_tck

jtag_rtck

jtag_tms_tmsc

jtag_tdi

jtag_tdo

jtag_emu0

jtag_emu1

ddr_padref

gpio_11

gpio_31

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AM3517/05 ARM Microprocessor

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2.4 Signal Description

Many signals are available on multiple pins according to the software configuration of the pin multiplexing

options.

1. SIGNAL NAME: The signal name

2. DESCRIPTION: Description of the signal

3. TYPE: Type = Ball type for this specific function:

–

I = Input

O = Output

Z = High-impedance

D = Open Drain

DS = Differential

A = Analog

4. BALL: Associated ball location

5. SUBSYSTEM PIN MULTIPLEXING: Contains a list of the pin multiplexing options at the

module/subsystem level. The pin function is selected at the module/system level.

Note: The Subsystem Multiplexing Signals are not described in Table 2-1 through .

2.4.1 External Memory Interfaces

Table 2-3. External Memory Interfaces – GPMC Signals Description (ZCN Pkg.)

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

BALL

(ZCN Pkg.) [4]

SUBSYSTEM PIN

MULTIPLEXING

[5]

gpmc_a1

gpmc_a2

gpmc_a3

gpmc_a4

gpmc_a5

gpmc_a6

gpmc_a7

gpmc_a8

gpmc_a9

gpmc_a10

gpmc_a11

gpmc_a12

gpmc_a13

gpmc_a14

gpmc_a15

gpmc_a16

gpmc_a17

gpmc_a18

gpmc_a19

gpmc_a20

gpmc_a21

gpmc_a22

gpmc_a23

gpmc_a24

gpmc_a25

gpmc_a26

General-purpose memory address bit 1

General-purpose memory address bit 2

General-purpose memory address bit 3

General-purpose memory address bit 4

General-purpose memory address bit 5

General-purpose memory address bit 6

General-purpose memory address bit 7

General-purpose memory address bit 8

General-purpose memory address bit 9

General-purpose memory address bit 10

General-purpose memory address bit 11

General-purpose memory address bit 12

General-purpose memory address bit 13

General-purpose memory address bit 14

General-purpose memory address bit 15

General-purpose memory address bit 16

General-purpose memory address bit 17

General-purpose memory address bit 18

General-purpose memory address bit 19

General-purpose memory address bit 20

General-purpose memory address bit 21

General-purpose memory address bit 22

General-purpose memory address bit 23

General-purpose memory address bit 24

General-purpose memory address bit 25

General-purpose memory address bit 26

O

E3/ G5

E2/ G4

E1/ G3

F7/ G2

F6/ G1

F4/ H2

F3/ H1

F2/ J5

F1/ J4

G6/ J3

J2

gpmc_a17/ gpmc_d0

gpmc_a18/ gpmc_d1

gpmc_a19/ gpmc_d2

gpmc_a20/ gpmc_d3

gpmc_a21/ gpmc_d4

gpmc_a22/ gpmc_d5

gpmc_a23/ gpmc_d6

gpmc_a24/ gpmc_d7

gpmc_a25/ gpmc_d8

gpmc_a26/ gpmc_d9

/ gpmc_d10

J1

/ gpmc_d11

K4

/ gpmc_d12

K3

/ gpmc_d13

K2

/ gpmc_d14

K1

/ gpmc_d15

E3

/ gpmc_d16

E2

/ gpmc_a1

E1

/ gpmc_a2

F7

/ gpmc_a3

F6

/ gpmc_a4

F4

/ gpmc_a5

F3

/ gpmc_a6

F2

/ gpmc_a7

F1

/ gpmc_a8

G6

/ gpmc_a9

38

TERMINAL DESCRIPTION

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Table 2-3. External Memory Interfaces – GPMC Signals Description (ZCN Pkg.) (continued)

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

BALL

(ZCN Pkg.) [4]

SUBSYSTEM PIN

MULTIPLEXING

[5]

gpmc_d0

GPMC Data bit 0

IO

O

G5

G4

G3

G2

G1

H2

H1

J5

gpmc_a1/ gpmc_d0

gpmc_d1

GPMC Data bit 1

gpmc_a2/ gpmc_d1

gpmc_d2

GPMC Data bit 2

gpmc_a3/ gpmc_d2

gpmc_d3

GPMC Data bit 3

gpmc_a4/ gpmc_d3

gpmc_d4

GPMC Data bit 4

gpmc_a5/ gpmc_d4

gpmc_d5

GPMC Data bit 5

gpmc_a6/ gpmc_d5

gpmc_d6

GPMC Data bit 6

gpmc_a7 /gpmc_d6

gpmc_d7

GPMC Data bit 7

gpmc_a8/ gpmc_d7

gpmc_d8

GPMC Data bit 8

J4

gpmc_a9/ gpmc_d8

gpmc_d9

GPMC Data bit 9

J3

gpmc_a10/ gpmc_d9

gpmc_d10

gpmc_d11

gpmc_d12

gpmc_d13

gpmc_d14

gpmc_d15

gpmc_ncs0

gpmc_ncs1

gpmc_ncs2

gpmc_ncs3

gpmc_ncs4

gpmc_ncs5

gpmc_ncs6

gpmc_ncs7

gpmc_clk

GPMC Data bit 10

GPMC Data bit 11

GPMC Data bit 12

GPMC Data bit 13

GPMC Data bit 14

GPMC Data bit 15

GPMC Chip Select 0

GPMC Chip Select 1

GPMC Chip Select 2

GPMC Chip Select 3

GPMC Chip Select 4

GPMC Chip Select 5

GPMC Chip Select 6

GPMC Chip Select 7

GPMC clock

J2

gpmc_a11/ gpmc_d10

J1

gpmc_a12/ gpmc_d11

K4

K3

K2

K1

L2

gpmc_a13/ gpmc_d12

gpmc_a14/ gpmc_d13

gpmc_a15/ gpmc_d14

gpmc_a16/ gpmc_d15

NA

O

L1

O

M4

M3

M2

M1

N5

N4

N1

R1

R2

R3

R4

O

gpmc_nadv_ale

gpmc_noe

gpmc_nwe

gpmc_nbe0_cle

Address Valid or Address Latch Enable

Output Enable

O

Write Enable

O

Lower Byte Enable. Also used for Command

Latch Enable

O

gpmc_nbe1

gpmc_nwp

gpmc_wait0

gpmc_wait1

gpmc_wait2

gpmc_wait3

Upper Byte Enable

O

I

T1

T2

T3

T4

T5

U1

NA

Flash Write Protect

External indication of wait

I

Table 2-4. External Memory Interfaces – SDRC Signals Description (ZCN Pkg.)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

sdrc_d0

SDRAM data bit 0

IO

B21

A21

D20

C20

E19

D19

sdrc_d1

sdrc_d2

sdrc_d3

sdrc_d4

sdrc_d5

SDRAM data bit 1

SDRAM data bit 2

SDRAM data bit 3

SDRAM data bit 4

SDRAM data bit 5

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Table 2-4. External Memory Interfaces – SDRC Signals Description (ZCN Pkg.) (continued)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

sdrc_d6

SDRAM data bit 6

IO

O

C19

B19

B18

D17

C17

D16

C16

B16

A16

A15

A7

sdrc_d7

SDRAM data bit 7

sdrc_d8

SDRAM data bit 8

sdrc_d9

SDRAM data bit 9

sdrc_d10

sdrc_d11

sdrc_d12

sdrc_d13

sdrc_d14

sdrc_d15

sdrc_d16

sdrc_d17

sdrc_d18

sdrc_d19

sdrc_d20

sdrc_d21

sdrc_d22

sdrc_d23

sdrc_d24

sdrc_d25

sdrc_d26

sdrc_d27

sdrc_d28

sdrc_d29

sdrc_d30

sdrc_d31

sdrc_ba0

sdrc_ba1

sdrc_ba2

sdrc_a0

SDRAM data bit 10

SDRAM data bit 11

SDRAM data bit 12

SDRAM data bit 13

SDRAM data bit 14

SDRAM data bit 15

SDRAM data bit 16

SDRAM data bit 17

SDRAM data bit 18

SDRAM data bit 19

SDRAM data bit 20

SDRAM data bit 21

SDRAM data bit 22

SDRAM data bit 23

SDRAM data bit 24

SDRAM data bit 25

SDRAM data bit 26

SDRAM data bit 27

SDRAM data bit 28

SDRAM data bit 29

SDRAM data bit 30

SDRAM data bit 31

SDRAM bank select 0

SDRAM bank select 1

SDRAM address bit 0

SDRAM address bit 1

SDRAM address bit 2

SDRAM address bit 3

SDRAM address bit 4

SDRAM address bit 5

SDRAM address bit 6

SDRAM address bit 7

SDRAM address bit 8

SDRAM address bit 9

SDRAM address bit 10

SDRAM address bit 11

SDRAM address bit 12

SDRAM address bit 13

SDRAM address bit 14

Chip select 0

B7

D7

E7

C6

D6

B5

C5

B4

A3

B3

C3

C2

D2

B1

C1

A12

C13

D13

A11

B11

C11

D11

E11

A10

B10

C10

D10

E10

A9

O

sdrc_a1

O

sdrc_a2

O

sdrc_a3

O

sdrc_a4

O

sdrc_a5

O

sdrc_a6

O

sdrc_a7

O

sdrc_a8

O

sdrc_a9

O

sdrc_a10

sdrc_a11

sdrc_a12

sdrc_a13

sdrc_a14

sdrc_ncs0

sdrc_ncs1

O

B9

O

A8

O

B8

O

D8

O

E13

A14

Chip select 1

O

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Table 2-4. External Memory Interfaces – SDRC Signals Description (ZCN Pkg.) (continued)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

sdrc_clk

Clock

IO

O

A13

B13

D14

C14

E14

B14

C21

B15

E8

sdrc_nclk

Clock Invert

sdrc_cke0

Clock Enable 0

O

sdrc_nras

SDRAM Row Access

SDRAM column address strobe

SDRAM write enable

Data Mask 0

O

sdrc_ncas

O

sdrc_nwe

O

sdrc_dm0

O

sdrc_dm1

Data Mask 1

O

sdrc_dm2

Data Mask 2

O

sdrc_dm3

Data Mask 3

O

D1

sdrc_strben0

sdrc_strben_dly0

sdrc_strben1

sdrc_strben_dly1

sdrc_odt0

PCB layout trace loop 0 pin 0

PCB layout trace loop 0 pin 1

PCB layout trace loop 1 pin 0

PCB layout trace loop 1 pin 1

On-die termination output

Data Strobe 0

A

A19

A18

A5

A

A4

O

C8

sdrc_dqs0p

sdrc_dqs0n

sdrc_dqs1p

sdrc_dqs1n

sdrc_dqs2p

sdrc_dqs2n

sdrc_dqs3p

sdrc_dqs3n

ddr_padref

IO

B20

A20

B17

A17

A6

Data Strobe 0

Data Strobe 1

Data Strobe 2

B6

Data Strobe 3

A2

Data Strobe 3

B2

Impedance control for DDR2 output.

This pin must be connected to ground via a

50-ohm (± 1%) resistor.

B12

2.4.2 Video Interfaces

Table 2-5. Video Interfaces – CCDC Signals Description (ZCN Pkg.)

SIGNAL NAME[1]

ccdc_pclk

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

CCDC pixel clock

IO

AD2

AD1

AE2

AD3

AE3

AD4

AE4

AC5

AD5

AE5

Y6

ccdc_field

ccdc_hd

CCDC field ID signal

CCDC horizontal sync

CCDC vertical sync

CCDC write enable

CCDC data bit 0

CCDC data bit 1

CCDC data bit 2

CCDC data bit 3

CCDC data bit 4

CCDC data bit 5

CCDC data bit 6

CCDC data bit 7

IO

ccdc_vd

IO

ccdc_wen

ccdc_data0

ccdc_data1

ccdc_data2

ccdc_data3

ccdc_data4

ccdc_data5

ccdc_data6

ccdc_data7

I

AB6

AC6

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Table 2-6. Video Interfaces – DSS Signals Description (ZCN Pkg.)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

AE23

AD22

AD23

AE24

AD24

AD25

AC23

AC24

AC25

AB24

AB25

AA23

AA24

AA25

Y22

dss_pclk

LCD Pixel Clock

O

dss_hsync

dss_vsync

dss_acbias

dss_data0

dss_data1

dss_data2

dss_data3

dss_data4

dss_data5

dss_data6

dss_data7

dss_data8

dss_data9

dss_data10

dss_data11

dss_data12

dss_data13

dss_data14

dss_data15

dss_data16

dss_data17

dss_data18

dss_data19

dss_data20

dss_data21

dss_data22

dss_data23

LCD Horizontal Synchronization

LCD Vertical Synchronization

AC bias control (STN) or pixel data enable (TFT) output

LCD Pixel Data bit 0

O

IO

O

LCD Pixel Data bit 1

LCD Pixel Data bit 2

LCD Pixel Data bit 3

LCD Pixel Data bit 4

LCD Pixel Data bit 5

LCD Pixel Data bit 6

LCD Pixel Data bit 7

LCD Pixel Data bit 8

LCD Pixel Data bit 9

LCD Pixel Data bit 10

LCD Pixel Data bit 11

LCD Pixel Data bit 12

LCD Pixel Data bit 13

LCD Pixel Data bit 14

LCD Pixel Data bit 15

LCD Pixel Data bit 16

LCD Pixel Data bit 17

LCD Pixel Data bit 18

LCD Pixel Data bit 19

LCD Pixel Data bit 20

LCD Pixel Data bit 21

LCD Pixel Data bit 22

LCD Pixel Data bit 23

Y23

Y24

Y25

W21

W22

W23

W24

W25

V24

V25

O

U21

O

U22

O

U23

Table 2-7. Video Interfaces – RFBI Signals Description

SIGNAL

NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL BOTTOM

(ZCN Pkg.) [4]

SUBSYSTEM PIN

MULTIPLEXING

[5]

rfbi_a0

RFBI command/data control

O

AE24

AD22

AD24

AD25

AC23

AC24

AC25

AB24

AB25

AA23

AA24

AA25

Y22

dss_acbias

dss_hsync

dss_data0

dss_data1

dss_data2

dss_data3

dss_data4

dss_data5

dss_data6

dss_data7

dss_data8

dss_data9

dss_data10

rfbi_cs0

rfbi_da0

rfbi_da1

rfbi_da2

rfbi_da3

rfbi_da4

rfbi_da5

rfbi_da6

rfbi_da7

rfbi_da8

rfbi_da9

rfbi_da10

1st LCD chip select

RFBI data bus 0

RFBI data bus 1

RFBI data bus 2

RFBI data bus 3

RFBI data bus 4

RFBI data bus 5

RFBI data bus 6

RFBI data bus 7

RFBI data bus 8

RFBI data bus 9

RFBI data bus 10

O

IO

42

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Table 2-7. Video Interfaces – RFBI Signals Description (continued)

SIGNAL

NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL BOTTOM

(ZCN Pkg.) [4]

SUBSYSTEM PIN

MULTIPLEXING

[5]

rfbi_da11

RFBI data bus 11

IO

O

Y23

Y24

dss_data11

dss_data12

dss_data13

dss_data14

dss_data15

dss_pclk

rfbi_da12

rfbi_da13

rfbi_da14

rfbi_da15

rfbi_rd

RFBI data bus 12

RFBI data bus 13

RFBI data bus 14

RFBI data bus 15

Read enable for RFBI

Write Enable for RFBI

Y25

W21

W22

AE23

AD23

W23

rfbi_wr

O

dss_vsync

dss_data16

rfbi_te_vsync0

tearing effect removal and Vsync input from 1st

LCD

I

rfbi_hsync0

Hsync for 1st LCD

I

W24

W25

dss_data17

dss_data18

rfbi_te_vsync1

tearing effect removal and Vsync input from 2nd

LCD

rfbi_hsync1

rfbi_cs1

Hsync for 2nd LCD

2nd LCD chip select

I

V24

V25

dss_data19

dss_data20

O

Table 2-8. Video Interfaces – TV Signals Description (ZCN Pkg.)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

tv_out1

tv_out2

tv_vfb1

tv_vfb2

tv_vref

TV analog output Composite: tv_out1

TV analog output S-VIDEO: tv_out2

O

I

K21

H24

K20

H23

H20

tv_vfb1: Feedback through external resistorto composite

tv_vfb2: Feedback through external resistorto S-VIDEO

External capacitor

2.4.3 Serial Communication Interfaces

Table 2-9. Serial Communication Interfaces – HDQ/1-Wire Signals Description (ZCN Pkg.)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

hdq_sio

Bidirectional HDQ 1-Wire control and data Interface. Output is

open drain.

IOD

L25

Table 2-10. Serial Communication Interfaces – I²C Signals Description (ZCN Pkg.)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

INTER-INTEGRATED CIRCUIT INTERFACE (I2C1)

i2c1_scl

I²C Master Serial clock. Output is open drain.

I²C Serial Bidirectional Data. Output is open drain.

IOD

V4

V5

i2c1_sda

INTER-INTEGRATED CIRCUIT INTERFACE (I2C2)

i2c2_scl

I²C Master Serial clock. Output is open drain.

I²C Serial Bidirectional Data. Output is open drain.

IOD

W1

W2

i2c2_sda

INTER-INTEGRATED CIRCUIT INTERFACE (I2C3)

i2c3_scl

I²C Master Serial clock. Output is open drain.

I²C Serial Bidirectional Data. Output is open drain.

IOD

W4

W5

i2c3_sda

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Table 2-11. Serial Communication Interfaces – McBSP LP Signals Description (ZCN Pkg.)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 1)

mcbsp1_dr

mcbsp1_clkr

mcbsp1_fsr

mcbsp1_dx

mcbsp1_clkx

mcbsp1_fsx

mcbsp_clks

Received serial data

I

P23

R25

P21

P22

N24

P24

P25

Receive Clock

IO

I

Receive frame synchronization

Transmitted serial data

Transmit clock

Transmit frame synchronization

External clock input (shared by McBSP1, 2, 3, 4, and 5)

MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 2)

mcbsp2_dr

mcbsp2_dx

mcbsp2_clkx

mcbsp2_fsx

Received serial data

I

B25

D24

C25

D25

Transmitted serial data

Combined serial clock

IO

Combined frame synchronization

MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 3)

mcbsp3_dr

mcbsp3_dx

mcbsp3_clkx

mcbsp3_fsx

Received serial data

I

C24

B24

A24

C23

Transmitted serial data

Combined serial clock

IO

Combined frame synchronization

MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 4)

mcbsp4_dr

mcbsp4_dx

mcbsp4_clkx

mcbsp4_fsx

Received serial data

I

A23

B22

B23

A22

Transmitted serial data

Combined serial clock

IO

Combined frame synchronization

MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 5)

mcbsp5_dr

mcbsp5_dx

mcbsp5_clkx

mcbsp5_fsx

Received serial data

I

Y18

Transmitted serial data

Combined serial clock

IO

AD19

AD17

AE19

Combined frame synchronization

Table 2-12. Serial Communication Interfaces – McSPI Signals Description (ZCN Pkg.)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

MULTICHANNEL SERIAL PORT INTERFACE (McSPI1)

mcspi1_clk

mcspi1_simo

mcspi1_somi

mcspi1_cs0

mcspi1_cs1

mcspi1_cs2

mcspi1_cs3

SPI Clock

IO

O

AE14

AD15

AC15

AB15

AD14

AE15

AE16

Slave data in, master data out

Slave data out, master data in

SPI Enable 0, polarity configured by software

SPI Enable 1, polarity configured by software

SPI Enable 2, polarity configured by software

SPI Enable 3, polarity configured by software

O

MULTICHANNEL SERIAL PORT INTERFACE (McSPI2)

mcspi2_clk

SPI Clock

IO

AD16,AC9

AC16,AD9

AB16,AE9

AA16,AA10

mcspi2_simo

mcspi2_somi

mcspi2_cs0

Slave data in, master data out

Slave data out, master data in

SPI Enable 0, polarity configured by software

44

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Table 2-12. Serial Communication Interfaces – McSPI Signals Description (ZCN Pkg.) (continued)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

mcspi2_cs1

SPI Enable 1, polarity configured by software

O

AE17

MULTICHANNEL SERIAL PORT INTERFACE (McSPI3)

mcspi3_clk

mcspi3_simo

mcspi3_somi

mcspi3_cs0

mcspi3_cs1

SPI Clock

IO

O

W25,AD11,AA18

V24,AE11,AD18

V25, AB12, AC18

U21,AE12,AB18

U22, AD12, AB19

Slave data in, master data out

Slave data out, master data in

SPI Enable 0, polarity configured by software

SPI Enable 1, polarity configured by software

MULTICHANNEL SERIAL PORT INTERFACE (McSPI4)

mcspi4_clk

SPI Clock

IO

W20, R25

P22

mcspi4_simo

mcspi4_somi

mcspi4_cs0

Slave data in, master data out

Slave data out, master data in

SPI Enable 0, polarity configured by software

P23

P24

Table 2-13. Serial Communication Interfaces – HECC Signals Description (ZCN Pkg.)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

HIGH-END CONTROLLER AREA NETWORK CONTROLLER (HECC)

hecc1_txd

hecc1_rxd

Transmit serial data pin

Receive serial data pin

IO

V2

V3

Table 2-14. Serial Communication Interfaces – EMAC (RMII) Signals Description (ZCN Pkg.)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

EMAC (RMII)

rmii_mdio_data

rmii_mdio_clk

rmii_rxd0

Management data I/O

IO

I

AE6

AD6

Y7

Management data clock

EMAC receive data pin 0

EMAC receive data pin 1

EMAC carrier sense/receive data valid

EMAC receive error

rmii_rxd1

I

AA7

AB7

AC7

AD7

AE7

AD8

AE8

rmii_crs_dv

rmii_rxer

I

rmii_txd0

EMAC transmit data pin 0

EMAC transmit data pin 1

EMAC transmit enable

O

I

rmii_txd1

rmii_txen

rmii_50mhz_clk

EMAC RMII 50 MHz clock

Table 2-15. Serial Communication Interfaces – UARTs Signals Description (ZCN Pkg.)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART1)

uart1_cts

uart1_rts

uart1_rx

uart1_tx

UART1 Clear To Send

UART1 Request To Send

UART1 Receive data

UART1 Transmit data

I

AD24,Y20,P25

AD25,Y19

O

I

AA23,W20,AC20

AB25,AA19

O

UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART2)

uart2_cts

uart2_rts

UART2 Clear To Send

I

B24,F20

C24,F19

UART2 Request To Send

O

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Table 2-15. Serial Communication Interfaces – UARTs Signals Description (ZCN Pkg.) (continued)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

uart2_rx

uart2_tx

UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART3) / IrDA

UART2 Receive data

I

C23,E23

A24,E24

UART2 Transmit data

O

uart3_cts_rctx

UART3 Clear To Send (input), Remote TX

(output)

IO

U1,N2

uart3_rts_sd

uart3_rx_irrx

uart3_tx_irtx

UART3 Request To Send, IR enable

UART3 Receive data, IR and Remote RX

UART3 Transmit data, IR TX

O

I

N3,V3

AC25,P1,F25,V2

AB24,P2,F24,E25

O

UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART2)

uart4_cts

uart4_rts

uart4_rx

uart4_tx

UART4 Clear To Send

UART4 Request To Send

UART4 Receive data

UART4 Transmit data

I

AD3,AD11

AE2,AE11

O

I

T5,AE3,AC12

T4,AD1,AB12

O

Table 2-16. Serial Communication Interfaces – USB Signals Description (ZCN Pkg.)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

UNIVERSAL SERIAL BUS INTERFACE (USB0)

usb0_dp

USB D+ (differential signal pair)

USB D- (differential signal pair)

A I/O/Z

O/Z

F25

F24

E25

G25

G24

usb0_dm

usb0_drvvbus

usb0_id

Digital output to control external supply

USB operating mode identification pin

A I/O/Z

usb0_vbus

For host or device mode operation, tie the VBUS/USB power signal to the

USB connector.

When used in OTG mode operation, tie VBUS to the external charge

pump and to the VBUS signal on the USB connector.

MM_FSUSB3

mm_fsusb3_rxdm

mm_fsusb3_rxdp

mm_fsusb3_rxrcv

mm_fsusb3_txse0

mm_fsusb3_txdat

mm_fsusb3_txen_n

MM_FSUSB2

Vminus receive data (not used in 3- or 4-pin configurations)

Vplus receive data (not used in 3- or 4-pin configurations)

Differential receiver signal input (not used in 3-pin mode)

Single-ended zero. Used as VM in 4-pin VP_VM mode.

USB data. Used as VP in 4-pin VP_VM mode.

Transmit enable

IO

AE13

AC13

A23

B23

B22

A22

mm_fsusb2_rxdm

mm_fsusb2_rxdp

mm_fsusb2_rxrcv

mm_fsusb2_txse0

mm_fsusb2_txdat

mm_fsusb2_txen_n

MM_FSUSB1

Vminus receive data (not used in 3- or 4-pin configurations)

Vplus receive data (not used in 3- or 4-pin configurations)

Differential receiver signal input (not used in 3-pin mode)

Single-ended zero. Used as VM in 4-pin VP_VM mode.

USB data. Used as VP in 4-pin VP_VM mode.

Transmit enable

IO

AD21

AB20

AC21

AE22

AE16

AE17

mm_fsusb1_rxdm

mm_fsusb1_rxdp

mm_fsusb1_rxrcv

mm_fsusb1_txse0

mm_fsusb1_txdat

mm_fsusb1_txen_n

HSUSB2

Vminus receive data (not used in 3- or 4-pin configurations)

Vplus receive data (not used in 3- or 4-pin configurations)

Differential receiver signal input (not used in 3-pin mode)

Single-ended zero. Used as VM in 4-pin VP_VM mode.

USB data. Used as VP in 4-pin VP_VM mode.

Transmit enable

IO

AD20

AE18

AD18

AC18

AB18

AB19

46

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Table 2-16. Serial Communication Interfaces – USB Signals Description (ZCN Pkg.) (continued)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

hsusb2_clk

Dedicated for external transceiver 60-MHz clock input from PHY

Dedicated for external transceiver Stop signal

O

I

AC20

AB20

AE21

AD21

AC21

AE22

AE16

AE17

AC16

hsusb2_stp

hsusb2_dir

Dedicated for external transceiver Data direction control from PHY

Dedicated for external transceiver Next signal from PHY

Dedicated for external transceiver Bidirectional data bus

hsusb2_nxt

I

hsusb2_data0

hsusb2_data1

hsusb2_data2

hsusb2_data3

hsusb2_data4

IO

Dedicated for external transceiver Bidirectional data bus additional signals

for 12-pin ULPI operation

hsusb2_data5

hsusb2_data6

hsusb2_data7

Dedicated for external transceiver Bidirectional data bus additional signals

for 12-pin ULPI operation

IO

AB16

AA16

AD16

Dedicated for external transceiver Bidirectional data bus additional signals

for 12-pin ULPI operation

Dedicated for external transceiver Bidirectional data bus additional signals

for 12-pin ULPI operation

HSUSB2_TLL

hsusb2_tll_clk

Dedicated for external transceiver 60-MHz clock input from PHY

Dedicated for external transceiver Stop signal

O

I

AC20

AB20

AE21

AD21

AC21

AE22

AE16

AE17

AC16

hsusb2_tll_stp

hsusb2_tll_dir

Dedicated for external transceiver data direction control from PHY

Dedicated for external transceiver Next signal from PHY

Dedicated for external transceiver Bidirectional data bus

O

hsusb2_tll_nxt

hsusb2_tll_data0

hsusb2_tll_data1

hsusb2_tll_data2

hsusb2_tll_data3

hsusb2_tll_data4

O

IO

Dedicated for external transceiver Bidirectional data bus additional signals

for 12-pin ULPI operation

hsusb2_tll_data5

hsusb2_tll_data6

hsusb2_tll_data7

Dedicated for external transceiver Bidirectional data bus additional signals

for 12-pin ULPI operation

IO

AB16

AA16

AD16

Dedicated for external transceiver Bidirectional data bus additional signals

for 12-pin ULPI operation

Dedicated for external transceiver Bidirectional data bus additional signals

for 12-pin ULPI operation

HSUSB1

hsusb1_clk

Dedicated for external transceiver 60-MHz clock input from PHY

Dedicated for external transceiver Stop signal

O

I

AE18

AD17

AE20

AD20

AD18

AC18

AB18

AB19

Y18

hsusb1_stp

hsusb1_dir

Dedicated for external transceiver data direction control from PHY

Dedicated for external transceiver Next signal from PHY

Dedicated for external transceiver Bidirectional data bus

hsusb1_nxt

hsusb1_data0

hsusb1_data1

hsusb1_data2

hsusb1_data3

hsusb1_data4

I

IO

Dedicated for external transceiver Bidirectional data bus additional signals

for 12-pin ULPI operation

hsusb1_data5

hsusb1_data6

hsusb1_data7

Dedicated for external transceiver Bidirectional data bus additional signals

for 12-pin ULPI operation

IO

AE19

AD19

AA18

Dedicated for external transceiver Bidirectional data bus additional signals

for 12-pin ULPI operation

Dedicated for external transceiver Bidirectional data bus additional signals

for 12-pin ULPI operation

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Table 2-16. Serial Communication Interfaces – USB Signals Description (ZCN Pkg.) (continued)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

HSUSB1_TLL

hsusb1_tll_clk

Dedicated for external transceiver 60-MHz clock input from PHY

Dedicated for external transceiver Stop signal

O

I

AE18

AD17

AE20

AD20

AD18

AC18

AB18

AB19

Y18

hsusb1_tll_stp

hsusb1_tll_dir

Dedicated for external transceiver data direction control from PHY

Dedicated for external transceiver Next signal from PHY

Dedicated for external transceiver Bidirectional data bus

O

hsusb1_tll_nxt

hsusb1_tll_data0

hsusb1_tll_data1

hsusb1_tll_data2

hsusb1_tll_data3

hsusb1_tll_data4

O

IO

Dedicated for external transceiver Bidirectional data bus additional signals

for 12-pin ULPI operation

hsusb1_tll_data5

hsusb1_tll_data6

hsusb1_tll_data7

Dedicated for external transceiver Bidirectional data bus additional signals

for 12-pin ULPI operation

IO

AE19

AD19

AA18

Dedicated for external transceiver Bidirectional data bus additional signals

for 12-pin ULPI operation

Dedicated for external transceiver Bidirectional data bus additional signals

for 12-pin ULPI operation

2.4.4 Removable Media Interfaces

Table 2-17. Removable Media Interfaces – MMC/SDIO Signals Description (ZCN Pkg.)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

MULTIMEDIA MEMORY CARD (MMC1) / SECURE DIGITAL IO (SDIO1)

mmc1_clk

MMC/SD Output Clock

O

AA9

AB9

mmc1_cmd

mmc1_dat0

mmc1_dat1

mmc1_dat2

mmc1_dat3

mmc1_dat4

mmc1_dat5

mmc1_dat6

mmc1_dat7

MMC/SD command signal

MMC/SD Card Data bit 0 / SPI Serial Input

MMC/SD Card Data bit 1

MMC/SD Card Data bit 2

MMC/SD Card Data bit 3

MMC/SD Card Data bit 4

MMC/SD Card Data bit 5

MMC/SD Card Data bit 6

MMC/SD Card Data bit 7

IO

AC9

AD9

AE9

AA10

AB10

AC10

AD10

AE10

MULTIMEDIA MEMORY CARD (MMC2) / SECURE DIGITAL IO (SDIO2)

mmc2_clk

MMC/SD Output Clock

O

AD11

AB13

AC13

mmc2_dir_dat0

mmc2_dir_dat1

Direction control for DAT0 signal case an external transceiver used

Direction control for DAT1 and DAT3 signals case an external

transceiver used

mmc2_dir_dat2

mmc2_dir_dat3

Direction control for DAT2 signal case an external transceiver used

O

AB1

AB2

Direction control for DAT4, DAT5, DAT6, and DAT7 signals case an

external transceiver used

mmc2_clkin

mmc2_dat0

mmc2_dat1

mmc2_dat2

mmc2_dat3

mmc2_dat4

MMC/SD input Clock

I

AE13

AB12

AC12

AD12

AE12

AB13

MMC/SD Card Data bit 0

MMC/SD Card Data bit 1

MMC/SD Card Data bit 2

MMC/SD Card Data bit 3

MMC/SD Card Data bit 4

IO

48

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Table 2-17. Removable Media Interfaces – MMC/SDIO Signals Description (ZCN Pkg.) (continued)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

mmc2_dat5

mmc2_dat6

mmc2_dat7

mmc2_dir_cmd

mmc2_cmd

MMC/SD Card Data bit 5

MMC/SD Card Data bit 6

MMC/SD Card Data bit 7

IO

O

AC13

AD13

AE13

AD13

AE11

Direction control for CMD signal case an external transceiver is used

MMC/SD command signal

IO

MULTIMEDIA MEMORY CARD (MMC3) / SECURE DIGITAL IO (SDIO3)

mmc3_clk

MMC/SD Output Clock

O

AD15,AE17

AD14,AE18

AB13,Y18

AC13,AE19

AD13,AD19

AE13,AA18

AD18

mmc3_cmd

mmc3_dat0

mmc3_dat1

mmc3_dat2

mmc3_dat3

mmc3_dat4

mmc3_dat5

mmc3_dat6

mmc3_dat7

MMC/SD command signal

MMC/SD Card Data bit 0 / SPI Serial Input

MMC/SD Card Data bit 1

MMC/SD Card Data bit 2

MMC/SD Card Data bit 3

MMC/SD Card Data bit 4

MMC/SD Card Data bit 5

MMC/SD Card Data bit 6

MMC/SD Card Data bit 7

IO

AD20

AE20

AB19

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2.4.5 Test Interfaces

Table 2-18. Test Interfaces – ETK Signals Description (ZCN Pkg.)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

etk_ctl

etk_clk

etk_d0

etk_d1

etk_d2

etk_d3

etk_d4

etk_d5

etk_d6

etk_d7

etk_d8

etk_d9

ETK trace ctl

O

AE18

AD17

AD18

AC18

AB18

AA18

Y18

ETK trace clock

ETK data 0

ETK data 1

ETK data 2

ETK data 3

ETK data 4

ETK data 5

ETK data 6

ETK data 7

ETK data 8

ETK data 9

ETK data 10

ETK data 11

ETK data 12

ETK data 13

ETK data 14

ETK data 15

AE19

AD19

AB19

AE20

AD20

AC20

AB20

AE21

AD21

AC21

AE22

etk_d10

etk_d11

etk_d12

etk_d13

etk_d14

etk_d15

Table 2-19. Test Interfaces – JTAG Signals Description (ZCN Pkg.)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

jtag_ntrst

jtag_tck

Test Reset

I

U24

U25

T21

T22

T23

T24

T25

R24

Test Clock

I

jtag_rtck

ARM Clock Emulation

Test Mode Select

Test Data Input

Test Data Output

Test emulation 0

Test emulation 1

O

IO

I

jtag_tms_tmsc

jtag_tdi

jtag_tdo

O

IO

jtag_emu0

jtag_emu1

Table 2-20. Test Interfaces – HWDBG Signals Description (ZCN Pkg.)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

AD2,AD17

AD1,AE18

AD3,AD18

AE3,AC18

AC5,AC18

AD5,AA18

Y18,AE5

hw_dbg0

hw_dbg1

hw_dbg2

hw_dbg3

hw_dbg4

hw_dbg5

hw_dbg6

hw_dbg7

hw_dbg8

hw_dbg9

Debug signal 0

O

Debug signal 1

Debug signal 2

Debug signal 3

Debug signal 4

Debug signal 5

Debug signal 6

Debug signal 7

Debug signal 8

Debug signal 9

Y6,AE19

Y7,AD19

AA7,AB19

50

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Table 2-20. Test Interfaces – HWDBG Signals Description (ZCN Pkg.) (continued)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

hw_dbg10

hw_dbg11

hw_dbg12

hw_dbg13

hw_dbg14

hw_dbg15

hw_dbg16

hw_dbg17

Debug signal 10

O

AC7,AE20

AD7,AD20

AE23,AC20

AD22,AB20

AB25,AE21

AA23,AD21

AA24,AC21

AA25,AE22

Debug signal 11

Debug signal 12

Debug signal 13

Debug signal 14

Debug signal 15

Debug signal 16

Debug signal 17

2.4.6 Miscellaneous

Table 2-21. Miscellaneous – GP Timer Signals Description (ZCN Pkg.)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

gpt8_pwm_evt

PWM or event for GP timer 8

PWM or event for GP timer 9

PWM or event for GP timer 10

PWM or event for GP timer 11

IO

N4,E23,AE17

M4,M2,F20,AC16

M3,M1,F19,AB16

N5,E24,AA16,AA12

gpt9_pwm_evt

gpt10_pwm_evt

gpt11_pwm_evt

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2.4.7 General-Purpose IOs

Table 2-22. General-Purpose IOs Signals Description (ZCN Pkg.)

SIGNAL NAME[1]

gpio_0

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

General-purpose IO 0

IO

Y1

M24

Y4

gpio_1

General-purpose IO 1

General-purpose IO 2

General-purpose IO 3

General-purpose IO 4

General-purpose IO 5

General-purpose IO 6

General-purpose IO 7

General-purpose IO 8

General-purpose IO 10

General-purpose IO 11

General-purpose IO 12

General-purpose IO 13

General-purpose IO 14

General-purpose IO 15

General-purpose IO 16

General-purpose IO 17

General-purpose IO 18

General-purpose IO 19

General-purpose IO 20

General-purpose IO 21

General-purpose IO 22

General-purpose IO 23

General-purpose IO 24

General-purpose IO 25

General-purpose IO 26

General-purpose IO 27

General-purpose IO 28

General-purpose IO 29

General-purpose IO 30

General-purpose IO 31

General-purpose IO 34

General-purpose IO 35

General-purpose IO 36

General-purpose IO 37

General-purpose IO 38

General-purpose IO 39

General-purpose IO 40

General-purpose IO 41

General-purpose IO 42

General-purpose IO 43

General-purpose IO 44

General-purpose IO 45

General-purpose IO 46

gpio_2

gpio_3

AA1

AA2

AA3

AB1

AB2

AC1

N25

T25

AD17

AE18

AD18

AC18

AB18

AA18

Y18

AE19

AD19

AB19

AE20

AD20

AC20

AB20

AE21

AD21

AC21

AE22

Y3

gpio_4

gpio_5

gpio_6

gpio_7

gpio_8

gpio_10

gpio_11

gpio_12

gpio_13

gpio_14

gpio_15

gpio_16

gpio_17

gpio_18

gpio_19

gpio_20

gpio_21

gpio_22

gpio_23

gpio_24

gpio_25

gpio_26

gpio_27

gpio_28

gpio_29

gpio_30

gpio_31

gpio_34

gpio_35

gpio_36

gpio_37

gpio_38

gpio_39

gpio_40

gpio_41

gpio_42

gpio_43

gpio_44

gpio_45

gpio_46

R24

E3

E2

E1

F7

F6

F4

F3

F2

F1

G6

J4

J3

J2

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Table 2-22. General-Purpose IOs Signals Description (ZCN Pkg.) (continued)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

gpio_47

gpio_48

gpio_49

gpio_50

gpio_51

gpio_52

gpio_53

gpio_54

gpio_55

gpio_56

gpio_57

gpio_58

gpio_59

gpio_60

gpio_61

gpio_62

gpio_63

gpio_64

gpio_65

gpio_66

gpio_67

gpio_68

gpio_69

gpio_70

gpio_71

gpio_72

gpio_73

gpio_74

gpio_75

gpio_76

gpio_77

gpio_78

gpio_79

gpio_80

gpio_81

gpio_82

gpio_83

gpio_84

gpio_85

gpio_86

gpio_87

gpio_88

gpio_89

gpio_90

gpio_91

gpio_92

General-purpose IO 47

IO

J1

K4

General-purpose IO 48

General-purpose IO 49

General-purpose IO 50

General-purpose IO 51

General-purpose IO 52

General-purpose IO 53

General-purpose IO 54

General-purpose IO 55

General-purpose IO 56

General-purpose IO 57

General-purpose IO 58

General-purpose IO 59

General-purpose IO 60

General-purpose IO 61

General-purpose IO 62

General-purpose IO 63

General-purpose IO 64

General-purpose IO 65

General-purpose IO 66

General-purpose IO 67

General-purpose IO 68

General-purpose IO 69

General-purpose IO 70

General-purpose IO 71

General-purpose IO 72

General-purpose IO 73

General-purpose IO 74

General-purpose IO 75

General-purpose IO 76

General-purpose IO 77

General-purpose IO 78

General-purpose IO 79

General-purpose IO 80

General-purpose IO 81

General-purpose IO 82

General-purpose IO 83

General-purpose IO 84

General-purpose IO 85

General-purpose IO 86

General-purpose IO 87

General-purpose IO 88

General-purpose IO 89

General-purpose IO 90

General-purpose IO 91

General-purpose IO 92

K3

K2

K1

L1

M4

M3

M2

M1

N5

N4

N1

R4

T1

T2

T4

T5

U1

AE23

AD22

AD23

AE24

AD24

AD25

AC23

AC24

AC25

AB24

AB25

AA23

AA24

AA25

Y22

Y23

Y24

Y25

W21

W22

W23

W24

W25

V24

V25

U21

U22

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Table 2-22. General-Purpose IOs Signals Description (ZCN Pkg.) (continued)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

gpio_93

General-purpose IO 93

IO

I

U23

AD2

AD1

AE2

AD3

AE3

AD4

AE4

AC5

AD5

AE5

Y6

gpio_94

General-purpose IO 94

General-purpose IO 95

General-purpose IO 96

General-purpose IO 97

General-purpose IO 98

General-purpose IO 99

General-purpose IO 100

General-purpose IO 101

General-purpose IO 102

General-purpose IO 103

General-purpose IO 104

General-purpose IO 105

General-purpose IO 106

General-purpose IO 107

General-purpose IO 108

General-purpose IO 109

General-purpose IO 110

General-purpose IO 111

General-purpose IO 112

General-purpose IO 113

General-purpose IO 114

General-purpose IO 116

General-purpose IO 117

General-purpose IO 118

General-purpose IO 119

General-purpose IO 120

General-purpose IO 121

General-purpose IO 122

General-purpose IO 123

General-purpose IO 124

General-purpose IO 125

General-purpose IO 126

General-purpose IO 127

General-purpose IO 128

General-purpose IO 129

General-purpose IO 130

General-purpose IO 131

General-purpose IO 132

General-purpose IO 133

General-purpose IO 134

General-purpose IO 135

General-purpose IO 136

General-purpose IO 137

General-purpose IO 138

General-purpose IO 139

gpio_95

gpio_96

gpio_97

gpio_98

gpio_99

gpio_100

gpio_101

gpio_102

gpio_103

gpio_104

gpio_105

gpio_106

gpio_107

gpio_108

gpio_109

gpio_110

gpio_111

gpio_112

gpio_113

gpio_114

gpio_116

gpio_117

gpio_118

gpio_119

gpio_120

gpio_121

gpio_122

gpio_123

gpio_124

gpio_125

gpio_126

gpio_127

gpio_128

gpio_129

gpio_130

gpio_131

gpio_132

gpio_133

gpio_134

gpio_135

gpio_136

gpio_137

gpio_138

gpio_139

I

IO

I

AB6

AC6

AE6

AD6

Y7

AA7

AB7

AE7

AD8

AE8

D25

I

IO

C25

B25

D24

AA9

AB9

AC9

AD9

AE9

AA10

AB10

AC10

AD10

AE10

AD11

AE11

AB12

AC12

AD12

AE12

AB13

AC13

AD13

AE13

54

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Table 2-22. General-Purpose IOs Signals Description (ZCN Pkg.) (continued)

SIGNAL NAME[1]

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

gpio_140

gpio_141

gpio_142

gpio_143

gpio_144

gpio_145

gpio_146

gpio_147

gpio_148

gpio_149

gpio_150

gpio_151

gpio_152

gpio_153

gpio_154

gpio_155

gpio_156

gpio_157

gpio_158

gpio_159

gpio_160

gpio_161

gpio_162

gpio_163

gpio_164

gpio_165

gpio_166

gpio_167

gpio_168

gpio_170

gpio_171

gpio_172

gpio_173

gpio_174

gpio_175

gpio_176

gpio_177

gpio_178

gpio_179

gpio_180

gpio_181

gpio_182

gpio_183

gpio_184

gpio_185

gpio_186

General-purpose IO 140

IO

B24

C24

A24

C23

F20

General-purpose IO 141

General-purpose IO 142

General-purpose IO 143

General-purpose IO 144

General-purpose IO 145

General-purpose IO 146

General-purpose IO 147

General-purpose IO 148

General-purpose IO 149

General-purpose IO 150

General-purpose IO 151

General-purpose IO 152

General-purpose IO 153

General-purpose IO 154

General-purpose IO 155

General-purpose IO 156

General-purpose IO 157

General-purpose IO 158

General-purpose IO 159

General-purpose IO 160

General-purpose IO 161

General-purpose IO 162

General-purpose IO 163

General-purpose IO 164

General-purpose IO 165

General-purpose IO 166

General-purpose IO 167

General-purpose IO 168

General-purpose IO 170

General-purpose IO 171

General-purpose IO 172

General-purpose IO 173

General-purpose IO 174

General-purpose IO 175

General-purpose IO 176

General-purpose IO 177

General-purpose IO 178

General-purpose IO 179

General-purpose IO 180

General-purpose IO 181

General-purpose IO 182

General-purpose IO 183

General-purpose IO 184

General-purpose IO 185

General-purpose IO 186

F19

E24

E23

AA19

Y19

Y20

W20

B23

A23

B22

A22

R25

P21

P22

P23

P25

P24

N24

N2

N3

P1

P2

AC7

W1

L25

AE14

AD15

AC15

AB15

AD14

AE15

AE16

AD16

AC16

AB16

AA16

AE17

W2

W4

W5

M25

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2.4.8 System and Miscellaneous Terminals

Table 2-23. System and Miscellaneous Signals Description (ZCN Pkg.)

SIGNAL NAME[1]

sys_32k

DESCRIPTION[2]

TYPE[3]

BALL

(ZCN Pkg.) [4]

32-kHz clock input

I

K24

K25

H25

L25

sys_xtalin

sys_xtalout

sys_altclk

Main input clock. Oscillator input or LVCMOS at 19.2, 13, or 12 MHz.

Output of oscillator

O

I

Alternate clock source selectable for GPTIMERs (maximum 54 MHz),

USB (48 MHz), or NTSC/PAL (54 MHz)

sys_clkreq

sys_clkout1

sys_clkout2

sys_boot0

sys_boot1

sys_boot2

sys_boot3

sys_boot4

sys_boot5

sys_boot6

sys_boot7

sys_boot8

sys_nrespwron

sys_nreswarm

sys_nirq

Request from device for system clock (open source type)

Configurable output clock1

IO

M24

N25

M25

Y4

O

Configurable output clock2

O

Boot configuration mode bit 0

Boot configuration mode bit 1

Boot configuration mode bit 2

Boot configuration mode bit 3

Boot configuration mode bit 4

Boot configuration mode bit 5

Boot configuration mode bit 6

Boot configuration mode bit 7

Boot configuration mode bit 8

Power On Reset

I

AA1

AA2

AA3

AB1

AB2

AC1

AC2

AC3

Y2

I

Warm Boot Reset (open drain output)

External FIQ input

IOD

Y3

I

Y1

sys_ndmareq0

External DMA request 0 (system expansion). Level (active low) or edge

(falling) selectable.

M3

sys_ndmareq1

sys_ndmareq2

sys_ndmareq3

External DMA request 1 (system expansion). Level (active low) or edge

(falling) selectable.

I

M2,U1

F1,M1

G6,N5

External DMA request 2 (system expansion). Level (active low) or edge

(falling) selectable.

External DMA request 3 (system expansion). Level (active low) or edge

(falling) selectable.

56

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2.4.9 Power Supplies

Table 2-24. Power Supplies Description

BALL

(ZCN Pkg.) [4]

SIGNAL NAME[1]

DESCRIPTION[2]

V16, V15, V11, V10,

U16, U15, U11, U10,

T18, T17, T9, T8,

R18, R17, R9, R8,

M18, L18, L9, L8,

K18, K17, K9, K8,

J16, J15, J11, J10,

H15, H11, H10

VDD_CORE

1.2-V core and oscillator macros power supply.

AE25, AE1, V18, V17,

V14, V13, V12, V9,

V8, U18, U17, U14,

U13, U12, U9, U8,

T14, T13, T12, R16,

R15, R14, R13, R12,

R11, R10, P18, P17,

P16, P15, P14, P13,

P12, P11, P10, P9,

P8, N18, N17, N14,

N13, N12, N9, N8,

M17, M16, M15, M14,

M13,M12, M11, M10,

M9, M8, L17, L16,

L15, L14, L13, L12,

L11, L10, K14, K13,

K12, J18, J17, J14,

J13, J12, J9, J8, H14,

H13, H12, H9, A25,

A1, N23, G20, G21

VSS

Core and I/O common ground.

VDDS_SRAM_MPU

1.8-V MPU SLDO analog power supply.

AA13

VDDS_SRAM_CORE_BG

1.8-V Core SLDO and VDDA of BandGap analog power supply.

E17

1.2-V SRAMOUT for MPU SLDO.

For proper device operation, connect to a 1µF decoupling capacitor.

CAP_VDD_SRAM_MPU

AA12

1.2-V SRAMOUT for Core SLDO.

For proper device operation, connect to a 1µF decoupling capacitor.

CAP_VDD_SRAM_CORE

VDDS_DPLL_MPU_USBHOST

VDDS_DPLL_PER_CORE

E16

1.8-V MPUSS DPLL and USBHOST DPLL analog power supply.

AA15

N20

1.8-V DPLL and HSDIVIDER/ CORE and HSDIVIDER analog power

supply.

VDDA_DAC

1.8-V DAC analog power supply.

DAC analog ground.

H21

H22

F23

G22

VSSA_DAC

VDDA3P3V_USBPHY

VDDA1P8V_USBPHY

3.3-V USB transceiver analog power supply.

1.8-V USB transceiver power supply.

Output of the 1.2-V internal LDO.

CAP_VDDA1P2LDO_USBPHY

For proper device operation, connect a 0.22uF capacitor between this pin F22

and VSSA.

Y16, Y15, Y13, Y12,

Y10, W16, W15, W13,

W12,W10, W9, W6,

V7, V6, U19, T20,

T19, T7, T6, R7, R6,

P20, P19, N19, N7,

N6, M7, M6, M5, L19,

K19, K7, K6, K5, J7,

H18, H17

VDDSHV

1.8/3.3-V power supply.

1.8-V power supply.

Y9, W18, U20, R5,

H16, H8, G17, G16,

G14, G13, G11, G10,

G8, F16, F13, F11,

F10, F8, N22

VDDS

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Table 2-24. Power Supplies Description (continued)

BALL

(ZCN Pkg.) [4]

SIGNAL NAME[1]

DESCRIPTION[2]

VREFSSTL

VDDSOSC

0.9-V DDR data PHY0 reference voltage input.

1.8-V oscillator power supply.

F14

L20

58

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3 ELECTRICAL CHARACTERISTICS

3.1 Absolute Maximum Ratings

The following table specifies the absolute maximum ratings over the operating junction temperature range

of commercial and extended temperature devices. Stresses beyond those listed under absolute maximum

ratings may cause permanent damage to the device. These are stress ratings only and functional

operation of the device at these or any other conditions beyond those indicated under recommended

operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods

may affect device reliability.

Notes:

•

Logic functions and parameter values are not assured out of the range specified in the recommended

operating conditions.

•

The AM3517/05 device adheres to EIA/JESD22–A114, Electrostatic Discharge (ESD) Sensitivity

Testing Human Body Model (HBM). Minimum pass level for HBM is 2 kV.

Table 3-1. Absolute Maximum Ratings Over Operating Junction Temperature Range

PARAMETER

MIN

0.5

MAX

1.6

UNIT

VDD_CORE

VDDS

Supply voltage range for core macros

Second supply voltage range for 1.8-V I/O macros

Supply voltage range for 1.8/3.3V I/O macros

V

0.5

2.25

TBD

VDDSHV

TBD

VDDS_SRAM_MP Analog Supply voltage range for 1.8-V MPU SLDO

U

VDDS_SRAM_CO Analog Supply voltage range for 1.8-V Core SLDO and VDDA

TBD

V

RE_BG

VDDS_DPLL_MPU Analog power supply for 1.8-V MPUSS DPLL and USBHOST

_USBHOST DPLL

VDDS_DPLL_PER Analog power supply for 1.8-V DPLL and HSDIVIDER/ CORE

of BandGap

_CORE

and HSDIVIDER

VDDA_DAC

Analog Power Supply for 1.8-V DAC

TBD

V

VDDA3P3V_USBP Analog power supply for 3.3-V USB transceiver

HY

VDDA1P8V_USBP Power Supply for 1.8-V USB transceiver

HY

TBD

V

VDDSOSC

V_PAD

Power Supply for 1.8-V oscillator

Voltage range at PAD

TBD

0.5

TBD

Vdds + 0.5

2.43

V

vdda

Supply voltage range for analog macros

0.5

V_ESD

ESD stress voltage⁽¹⁾

HBM (human body model)⁽²⁾

CDM (charged device model)⁽³⁾

TBD

I_IOI

Current-pulse injection on each I/O pin⁽⁴⁾

Clamp current for an input or output

Storage temperature range⁽⁵⁾

200

mA

C

I_clamp

T_stg

20

65

20

150

(1) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.

(2) JEDEC JESD22–A114 D with the following exception-no connect pins are not stressed. 2000V Human Body Model (HBM)

(3) JEDEC JESD22–C101C with the following exception-split out pin groupings to eliminate cumulative stress effect

(4) Each device is tested with I/O pin injection of 200 mA with a stress voltage of 1.5 times maximum vdd at room temperature.

(5) These temperatures extreme do not simulate actual operating conditions but exaggerate any faults that might exist.

The supply voltages and power consumption estimates are detailed in Table 3-2.

Table 3-2. Estimated Power Consumption at Ball Level

MAX CURRENT

SIGNAL NAME

VDD_CORE

DESCRIPTION

(mA)

1.2-V core and oscillator macros power supply

1500 mA

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Table 3-2. Estimated Power Consumption at Ball Level (continued)

VDDS_SRAM_MPU

VDDS_SRAM_CORE_BG

VDDS_DPLL_MPU_USBHOST

VDDS_DPLL_PER_CORE

VDDA_DAC

1.8-V MPU SLDO analog power supply

1.8-V Core SLDO and VDDA of BandGap analog power supply

1.8-V MPUSS DPLL and USBHOST DPLL analog power supply

1.8-V DPLL and HSDIVIDER/ CORE and HSDIVIDER analog power supply

1.8-V DAC analog power supply

40 mA

25 mA

65 mA

10 mA

50 mA

300 mA

200 mA

20 mA

VDDA3P3V_USBPHY

VDDA1P8V_USBPHY

VDDSHV

3.3-V USB transceiver analog power supply

1.8-V USB transceiver power supply

3.3-/1.8-V power supply

VDDS

1.8-V power supply

VDDSOSC

1.8-V oscillator power supply

60

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3.2 Recommended Operating Conditions

All AM3517/05 modules are used under the operating conditions contained in Table 3-3.

Note: Logic functions and parameter values are not assured if the device is operated out of the range

specified in the recommended operating conditions.

Table 3-3. Recommended Operating Conditions

PARAMETER

VDD_CORE

DESCRIPTION

Core and oscillator macros power supply.

Core and I/O common ground.

NOM

1.2

UNIT

V

VSS

0

V

VDDS_SRAM_MPU

VDDS_SRAM_CORE_BG

VDDS_DPLL_MPU_USBHOST

VDDS_DPLL_PER_CORE

VDDA_DAC

MPU SLDO analog power supply.

1.8

V

Core SLDO and VDDA of BandGap analog power supply.

MPUSS DPLL and USBHOST DPLL analog power supply.

DPLL and HSDIVIDER/ CORE and HSDIVIDER analog power supply

DAC analog power supply.

1.8

V

1.8

V

1.8

V

1.8

V

VSSA_DAC

DAC analog ground.

0

V

VDDA3P3V_USBPHY

VDDSHV

USB transceiver analog power supply.

3.3-/1.8-V power supply.

3.3

V

3.3/1.8

1.8

V

VDDS

1.8-V power supply.

V

T_J

Operating junction

temperature range

Commercial Temperature

Extended Temperature

Commercial Temperature

Extended Temperature

TBD

°C

T_J

Operating junction

temperature range

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Figure 3-1 illustrates the power domains:

vdds_dpll_mpu_usbhost

DLL/DCDL

BandGap

LDO3

1.0 V/1.2 V

BCK

MEM

vddshv

LDO

MPU

in 1.8 V

out 1.2 V

DPLL_MPU

vdds

LDO

in 1.8 V

out 1.2 V

vdd_core

Core

SRAM 1 LDO

SRAM1

ARRAY

0 V/1.0 V/1.2 V

DPLL_CORE

LDO

tv_ref

(for capacitor)

HSDIVIDER

vdds_dpll_per_core

vdda_dac

SRAM2

ARRAY

SRAM 2 LDO

0 V/1.0 V/1.2 V

Dual Video DAC

cap_vdd_sram_core

LDO

in 1.8 V

out 1.2 V

Periph1

DPLL4

LDO

vss

HSDIVIDER

vssa_dac

LDO

in 1.8 V

out 1.2 V

Periph2

DPLL5

vdd_core domain

Device

030-003

Figure 3-1. AM3517/05 Voltage Domains

62

ELECTRICAL CHARACTERISTICS

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3.3 DC Electrical Characteristics

Table 3-4 summarizes the dc electrical characteristics.

Table 3-4. DC Electrical Characteristics⁽¹⁾

PARAMETER

MIN

NOM

MAX

UNIT

LVCMOS Pin Buffers

vddshv = 1.8 V

vddshv = 3.3 V

vddshv = 1.8 V

vddshv = 3.3 V

vddshv = 1.8 V

vddshv = 3.3 V

vddshv = 1.8 V

vddshv = 3.3 V

V_IH

V_IL

High-level input voltage

0.6 x vddshv

TBD

vddshv + 0.3

0.3 x vddshv

0.6

V

Low-level input voltage

TBD

V_OH

High-level output voltage⁽²⁾

Low-level output voltage⁽²⁾

vddshv x 0.2

0.75 x vddshv

V_OL

0.2

0.125 x

vddshv

t_T

Input transition time (rise time, t_Ror fall time, t_Fevaluated

between 10% and 90% at PAD)

10

ns

I_I

Input current with V_I= V_Imax

TBD

A

I_OZ

Off-state output current for output in high impedance with driver

only, driver disabled

Off-state output current for output in high impedance with

driver/receiver/pullup only, driver disabled, pullup not inhibited

TBD

Off-state output current for output in high impedance with

driver/receiver/pulldown only, driver disabled, pulldown not

inhibited

I_Z

Total leakage current through the PAD connection of a

driver/receiver combination that may include a pullup or pulldown.

The driver output is disabled and the pullup or pulldown is

inhibited.

TBD

A

LVCMOS Open-Drain Pin Buffers Dedicated to I2C IOs

V_IH

V_IL

V_OL

I_I

High level input voltage

Low level input voltage

TBD

0.6

V

A

Low-level output voltage open-drain at 3-mA sink current

TBD

Input current at each I/O pin with an input voltage between 0.1 x

vddshv to 0.9 x vddshv

C_I

Capacitance for each I/O pin

TBD

pF

ns

T_OF

Output fall time from V_IHminto V_ILmaxwith a

bus capacitance C_Bfrom 10 pF to 400 pF

Fast mode

TBD

Standard mode

Output fall time with a capacitive load from 10 High-speed mode

pF to 100 pF at 3-mA sink current

TBD

Output fall time with a capacitive load of 400

pF at 3-mA sink current

TBD

Output fall time with a capacitive load of 40

pF (for CBUS compatibility)

Complex IO Dedicated to USB

TBD

V_IH

V_IL

V_OH

V_OL

I_I

High-level input voltage

TBD

0.6

V

A

Low-level input voltage

TBD

High-level output voltage at 4-mA sink current

Low-level output voltage at 4-mA sink current

TBD

Input current at each I/O pin with an input voltage between 0.1 x

vddshv to 0.9 x vddshv

TBD

C_I

Capacitance for each I/O pin

TBD

pF

(1) Values are subject to change after characterization.

(2) With 100 A sink / source current at vddsxmin.

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Table 3-4. DC Electrical Characteristics (continued)

PARAMETER

MIN

NOM

MAX

TBD

UNIT

T_OF

Output fall time from V_IHminto V_ILmaxwith a

bus capacitance C_Bfrom 10 pF to 400 pF

Fast mode

TBD

ns

Standard mode

Output fall time with a capacitive load from 10 High-speed mode

pF to 100 pF at 3-mA sink current

TBD

Output fall time with a capacitive load of 400

pF at 3-mA sink current

TBD

Output fall time with a capacitive load of 40

pF (for CBUS compatibility)

64

ELECTRICAL CHARACTERISTICS

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3.4 Core Voltage Decoupling

For module performance, decoupling capacitors are required to suppress the switching noise generated

by high frequency and to stabilize the supply voltage. A decoupling capacitor is most effective when it is

close to the device because this minimizes the inductance of the circuit board wiring and interconnects.

Table 3-5 summarizes the power supplies decoupling characteristics.

Table 3-5. Core Voltage Decoupling Characteristics

PARAMETER

MIN

TYP

100

MAX

UNIT

nF

Cvdd_core⁽¹⁾

50

120

Ccap_vdd_sram_core

Cvdds_dpll_mpu_usbhost

Cvdds_dpll_per_core

Cvdda_dac

Cvdd_sram_core

Cvdd_sram_core_bg

Cvdds_mmc1

Cvdds_sram_mpu

(1) 1 capacitor per 2 to 4 balls

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Figure 3-2 illustrates an example of power supply decoupling.

Device

vdds_sram_mpu

Cvdds_sram_mpu

vdda_dac

vdds_sram_mpu

Cvdda_dac

Video DAC

vssa_dac

cap_vdd_sram_mpu

SRAM_LDO1

Ccap_vdd_sram_mpu

vdds_sram_core_bg

Cvdds_sram_core_bg

vdds_sram_core_bg

vdd_sram_core

SRAM_LDO2

Cvdd_sram_core

WKUP_LDO

BG

cap_vdd_sram

_core

Ccap_vdd_sram_core

DPLL_MPU

vdds_dpll_mpu

_usbhost

vdds_dpll_mpu_usbhost

Cvdds_dpll_mpu_usbhost

DPLL_CORE

vdds_dpll_per_core

Cvdds_dpll_per_core

vdds_dpll_per_core

DPLL5

DPLL4

Vdd_core

vdd_core

VSS

Core

MPU

Cvdd_core

030-004

(1) Decoupling capacitors must be placed as closed as possible to the power ball. Choose the ground located closest to the power pin

for each decoupling capacitor. Place the decoupling capacitor Ci in a group of 1, 2, or 3 balls; the total must be equal to the

decoupling requirement. In case you interconnect powers, first insert the decoupling capacitor and then interconnect the powers.

(2) The decoupling capacitor value depends on the board characteristics.

Figure 3-2. Power Supply Decoupling

66

ELECTRICAL CHARACTERISTICS

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3.5 Power-up and Power-down

This section provides the timing requirements for the AM3517/05 hardware signals.

3.5.1 Power-up Sequence

The following steps give an example of power-up sequence supported by the AM3517/05.

3.3-V Operation Sequence:

1. IO 1.8V (VDDS) supply should come up first. This is required to bias the circuitry for the 3.3V IO’s.

2. IO 3.3V (VDDSHV) supply should be ramped up next.

3. Band-gap, LDO supplies (VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU) should be ramped up next.

4. Core supply follows next.

5. All the PLL supplies (VDDS_DPLL_PER_CORE, VDDS_DPLL_MPU_USBHOST) should be ramped

up next. Ensure PLL is powered-up in OFFMODE=1 to control any transients.

6. All the other complex IO power supplies should be ramped up next (DAC, USB).

7. sys_nrespwron must be held low at the time the power supplies are ramped up till the time the

sys_32k and sys_xtalin clocks are stable.

1.8-V Operation Sequence:

1. IO 1.8V (VDDS and VDDSHV) supply should come up first. This is required to bias the circuitry for the

3.3V IO’s.

2. Band-gap, LDO supplies (VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU) should be ramped up next.

3. Core supply follows next.

4. All the PLL supplies (VDDS_DPLL_PER_CORE, VDDS_DPLL_MPU_USBHOST) should be ramped

up next. Ensure PLL is powered-up in OFFMODE=1 to control any transients.

5. All the other complex IO power supplies should be ramped up next (DAC, USB).

6. sys_nrespwron must be held low at the time the power supplies are ramped up till the time the

sys_32k and sys_xtalin clocks are stable.

7. The other power supplies can then be turned on upon software request.

Notes: Depending on the target Power IC

•

VDDS, VDDSHV (1.8-V operation only), VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU, and

VDDSOSC can be grouped and powered up together.

•

VDDS_DPLL_PER_CORE, VDDS_DPLL_MPU_HOST and all the other complex IO power supplies

can be grouped together.

Figure 3-3 shows the power-up sequence.

Note: If an external square clock is provided, it could be started after sys_nrespwron release provided it is

clean: no glitch, stable frequency, and duty cycle.

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1.8V

VDDS

VDDSHV

3.3V

VDDS_SRAM_CORE_BG,

VDDS_SRAM_MPU,

VDDSOSC

1.8V

1.2V

VDD_CORE

sys_nrespwron

sys_32k

sys_xtalin

VDDS_DPLL_PER_CORE,

VDDS_DPLL_MPU_USBHOST

1.8V

VDDA_DAC,

VDDA1P8V_USBPHY

3.3V

VDDA3P3V_USBPHY

Figure 3-3. Power-up Sequence

68

ELECTRICAL CHARACTERISTICS

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3.5.2 Power-down Sequence

The AM3517/05 device proceeds with the power-down sequence shown below.

The following steps give an example of the power-down sequence supported by the AM3517/05

device.

1. Reset AM3517/05 device.

2. Stop all signals driven to AM3517/05.

3. Option 1: Power down all domains simutaneously.

4. Option 2: If all domains cannot be powered down simultaneously, follow the below sequence:

a. Power off all complex I/O domains

b. Power off core domain (VDD_CORE)

c. Power off all PLL domains (VDDS_DPLL_MPU_USBHOST and VDDS_DPLL_PER_CORE)

d. Power off all SRAM LDOs

e. Power off all standard I/O domains (VDDS and VDDSHV)

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4 CLOCK SPECIFICATIONS

The AM3517/05 device has three external input clocks, a low frequency (sys_32k), a high frequency

(sys_xtalin), and an optional (sys_altclk). The AM3517/05 device has two configurable output clocks,

sys_clkout1 and sys_clkout2.

Figure 4-1 shows the interface to the external clock sources and clock outputs.

AM35x

sys_32k

Power IC

Alternate Clock Source Selectable (54, 48 MHz or other [up

to 59 MHz])

sys_altclk

rmii_50mhz_clk

sys_clkout1

Ethernet input 50-MHz clock

To Peripherals (From OSC_CLK: 12, 13,16.8, 19.2, 26, or

38.4 MHz)

To Peripherals (From OSC_CLK: 12,13, 16.8, 19.2, 26, or

38.4 MHz, core_clk [DPLL, up to 166 MHz], DPLL-96 MHz

or DPLL-54 MHz outputs with a divider of 1, 2, 4, 8, or 16)

sys_clkout2

sys_xtalout

To Quartz (Oscillator output) or Unconnected

sys_xtalin

sys_clkreq

sys_xtalout

sys_xtalin

From Quartz (Oscillator input), Square Clock, or Crystal

Clock Request. To Square Clock Source or from Peripherals

sys_xtalout

Unconnected

Oscillator

is Bypassed

Oscillator

is Used

sys_xtalin

Square

Clock

Source

sys_clkreq

GPin

030-007

Figure 4-1. Clock Interface

The AM3517/05 device operation requires the following three input clocks:

•

The 32-kHz clock can be generated using one of the following options and can be selected via the

sys_boot7 pin. See Figure 4-2.

–

External: Supplied by an oscillator on the sys_32k pin.

Internal: 32-kHz clock generation using a fixed divider on the HS system clock (26MHz).

•

The system alternative clock can be used (through the sys_altclk pin) to provide alternative 48 or 54

MHz or other clock source (up to 54 MHz).

The system clock input (26 MHz) is used to generate the main source clock of the AM3517/05 device.

It supplies the DPLLs as well as several AM3517/05 modules. The system clock input can be

connected to either:

–

A crystal oscillator clock managed by sys_xtalin and sys_xtalout. In this case, the sys_clkreq is

used as an input (GPIN).

–

A CMOS digital clock through the sys_xtalin pin. In this case, the sys_clkreq is used as an output to

request the external system clock.

70

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0

Sys_32k

Sys_32k_in

(to wkup_pd)

Fixed

Divider

/800

32.5 kHz

1

Sys_clk=

26 MHz

Sys_xtalin

Gz Coming From WKUP_PD

Pwrdn Coming From WKUP_PD

Sys_xtalout

Latch

0

Sys_boot7

1

JTAG Overrides

for DFT

1

Sys_clk

PowerOn Reset

Figure 4-2. 32-kHz Clock Generation

The AM3517/05 outputs externally two clocks:

•

sys_clkout1 can output the oscillator clock (26 MHz) at any time.

sys_clkout2 can output the oscillator clock, core_clk, 96 MHz or 54 MHz. It can be divided by 2, 4, 8,

or 16 and its off state polarity is programmable.

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4.1 Oscillator

On AM3517/05, VSSOSC has a dedicated ground (sys_xtalgnd) that is used to help reduce jitter. The load

capacitors for sys_xtalin and sys_xtalout should be connected between the corresponding xtal pin to

sys_xtalgnd as shown in Figure 4-3.

OSC BUFFER

IOSC/OOSC

S

Y

S

_

S

Y

S

Y

S

_

X

T

A

L

I

XT

A

L

O

U

T

XT

AL

G

N

D

N

Figure 4-3. AM3517/05 Oscillator Connections

4.2 Input Clock Specifications

The clock system accepts three input clock sources:

•

32-kHz digital CMOS clock

Crystal oscillator clock or CMOS digital clock (26 MHz)

Alternate clock (48 or 54 MHz, or other up to 54 MHz)

72

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4.3 Output Clock Specifications

Two output clocks (pin sys_clkout1 and pin sys_clkout2) are available:

•

sys_clkout1 can output the oscillator clock (26 MHz) at any time. It can be controlled by software or

externally using sys_clkreq control. When the device is in the off state, the sys_clkreq can be asserted

to enable the oscillator and activate the sys_clkout1 without waking up the device. The off state polarity

of sys_clkout1 is programmable.

•

sys_clkout2 can output sys_clk (26 MHz), core_clk (core DPLL output), APLL-96 MHz, or APLL-54

MHz. It can be divided by 2, 4, 8, or 16 and its off state polarity is programmable. This output is active

only when the core domain is active.

Table 4-1 summarizes the sys_clkout1 output clock electrical characteristics.

Table 4-1. sys_clkout1 Output Clock Electrical Characteristics

NAME

DESCRIPTION

MIN

TYP

26

MAX

UNIT

MHz

pF

f

Frequency

Load capacitance⁽¹⁾

C_I

f(max) = 38.4 MHz

f(max) = 26 MHz

70

125

(1) The load capacitance is adapted to a frequency.

Table 4-2 details the sys_clkout1 output clock timing characteristics.

Table 4-2. sys_clkout1 Output Clock Switching Characteristics

NAME

DESCRIPTION

Frequency

MIN

TYP

MAX

UNIT

MHz

ns

f

1 / CO0

26

CO1

t_w(CLKOUT1)

Pulse duration, sys_clkout1 low or high

0.40 *

0.60 *

t_c(CLKOUT1)

CO2

CO3

t_R(CLKOUT1)

t_F(CLKOUT1)

Rise time, sys_clkout1⁽¹⁾

Fall time, sys_clkout1⁽¹⁾

3.31

ns

3.31

(1) With a load capacitance of 25 pF.

CO0

CO1

sys_clkout

030-014

Figure 4-4. sys_clkout1 System Output Clock

Table 4-3 summarizes the sys_clkout2 output clock electrical characteristics.

Table 4-3. sys_clkout2 Output Clock Electrical Characteristics

NAME

DESCRIPTION

Frequency, sys_clkout2⁽¹⁾

Load capacitance⁽²⁾

MIN

TYP

MAX

166

12

UNIT

MHz

pF

f

C_L

f(max) = 166 MHz

2

8

(1) The maximum frequency supported is core_clk/2 MHz.

(2) The load capacitance is adapted to a frequency.

Table 4-4 details the sys_clkout2 output clock timing characteristics.

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Table 4-4. sys_clkout2 Output Clock Switching Characteristics

NAME

DESCRIPTION

Frequency

MIN

TYP

MAX

UNIT

MHz

ns

f

1 / CO0

322

CO1

CO2

CO3

t_w(CLKOUT2)

t_R(CLKOUT2)

t_F(CLKOUT2)

Pulse duration, sys_clkout2 low or high

Rise time, sys_clkout2⁽¹⁾

Fall time, sys_clkout2⁽¹⁾

0.40 * tc(CLKOUT2)

0.60 * tc(CLKOUT2)

3.7

4.3

ns

(1) With a load capacitance of 25 pF.

CO0

CO1

sys_clkout

030-015

Figure 4-5. sys_clkout2 System Output Clock

74

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4.4 DPLL Specifications

The AM3517/05 integrates four DPLLs. The PRM and CM drive them.

The four main DPLLs are:

•

DPLL1 (MPU)

DPLL3 (Core)

DPLL4 (Peripherals)

DPLL5 (Second Peripherals DPLL)

Figure 4-6 illustrates the DPLL implementation.

Device

VDDS_DPLL_MPU_USBHOST Power Rail

DPLL1

DPLL3

DPLL4

DPLL5

VDDS_DPLL_PER_CORE

030-016

Figure 4-6. DPLL Implementation

4.4.1 Digital Phase-Locked Loop (DPLL)

The DPLL provides all interface clocks and some functional clocks (such as the processor clocks) of the

AM3517/05 device.

DPLL1 gets an always-on clock used to produce the synthesized clock. They get a high-speed bypass

clock used to switch the DPLL output clock on this high-speed clock during bypass mode.

The high-speed bypass clock is an L3 divided clock (programmable by 1 or 2) that saves DPLL processor

power consumption when the processor does not need to run faster than the L3 clock speed, or optimizes

performance during frequency scaling.

Each DPLL synthesized frequency is set by programming M (multiplier) and N (divider) factors. In addition,

all DPLL outputs can be controlled by an independent divider (M2 to M6).

The clock generating DPLLs of the AM3517/05 device have following features:

•

Independent power domain per DPLL

Controlled by clock-manager (CM)

Fed with always-on system clock with independent gating control per DPLL

Analog part supplied through dedicated power supply (1.8 V) and an embedded LDO to get rid of

1-MHz noise

•

Up to four independent output dividers for simultaneous generation of multiple clock frequencies

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4.4.1.1 DPLL1 (MPU)

DPLL1 is located in the MPU subsystem and supplies all clocks of the subsystem. All MPU subsystem

clocks are internally generated in the subsystem. When the core domain is on, it can use the DPLL3

(CORE DPLL) output as a high-frequency bypass input clock.

4.4.1.2 DPLL3 (CORE)

DPLL3 supplies all interface clocks and also a few module functional clocks. It can be also source of the

emulation trace clock. It is located in the core domain area. All interface clocks and a few module

functional clocks are generated in the CM. When the core domain is on, it can be used as a bypass input

to DPLL1.

4.4.1.3 DPLL4 (Peripherals)

DPLL4 generates clocks for the peripherals. It supplies five clock sources: 96-MHz functional clocks to

subsystems and peripherals, 54 MHz to TV DAC, display functional clock, camera sensor clock, and

emulation trace clock. It is located in the core domain area. All interface clocks and few module functional

clocks are generated in the CM. Its outputs to the DSS, PER, and EMU domains are propagated with

always-on clock trees.

4.4.1.4 DPLL5 (Second peripherals DPLL)

DPLL5 supplies the 120-MHz functional clock to the CM.

76

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4.4.2 DPLL Noise Isolation

The DPLL requires dedicated power supply pins to isolate the core analog circuit from the switching noise

generated by the core logic that can cause jitter on the clock output signal. Guard rings are added to the

cell to isolate it from substrate noise injection.

The vdd supplies are the most sensitive to noise; decoupling capacitance is recommended below the

supply rails. The maximum input noise level allowed is 30 mV_PPfor frequencies below 1 MHz.

illustrates an example of a noise filter.

Noise Filter

VDDS_DPLL_MPU_USBHOST

C

DPLL_MPU

DLL

DPLL_CORE

Noise Filter

VDDS_DPLL_PER_CORE

C

DPLL5

DPLL4

030-017

Figure 4-7. DPLL Noise Filter

Table 4-5 specifies the noise filter requirements.

Table 4-5. DPLL Noise Filter Requirements

NAME

MIN

TYP

MAX

UNIT

Filtering capacitor

100

nF

(1) The capacitors must be inserted between power and ground as close as possible.

(2) This circuit is provided only as an example.

(3) The filter must be located as close as possible to the device.

(4) No filtering required if noise is below 10 mV_PP

.

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5 VIDEO DAC SPECIFICATIONS

A dual-display interface equips the AM3517/05 processor. This display subsystem provides the necessary

control signals to interface the memory frame buffer directly to the external displays (TV-set). Two (one

per channel) 10-bit current steering DACs are inserted between the DSS and the TV set to generate the

video analog signal. One of the video DACs also includes TV detection and power-down mode. Figure 5-1

illustrates the AM3517/05 DAC architecture.

Device

TV DCT

tv_vfb1

DIN1[9:0]

TVOUT

BUFFER

Video DAC 1

tv_out1

DSS

tv_vfb2

DIN2[9:0]

TVOUT

Video DAC 2

BUFFER

tv_out2

V_ref

vdda_dac

vssa_dac

tv_vref

CBG

030-018

Figure 5-1. Video DAC Architecture

The following paragraphs detail the 10-bit DAC interface pinout, static and dynamic specifications, and

noise requirements. The operating conditions and absolute maximum ratings are detailed in Table 5-2 and

Table 5-4.

78

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5.1 Interface Description

Table 5-1 summarizes the external pins of the video DAC.

Table 5-1. External Pins of 10-bit Video DAC

PIN NAME

I/O

DESCRIPTION

tv_out1

O

TV analog output composite

DAC1 video output. An external resistor is connected between this

node and tv_vfb1. The nominal value of ROUT1 is 1650 . Finally, note

that this is the output node that drives the load (75 ).

tv_out2

O

TV analog output S-VIDEO

DAC2 video output. An external resistor is connected between this

node and tv_vfb2. The nominal value of ROUT2 is 1650 . Finally, note

that this is the output node that drives the load (75 ).

tv_vref

tv_vfb1

tv_vfb2

I

Reference output voltage from internal

bandgap

A decoupling capacitor (CBG) needs to be connected for optimum

performance.

O

Amplifier feedback node

Amplifier feedback node. An external resistor is connected between

this node and tv_out1. The nominal value of ROUT1 is 1650 (1%).

Amplifier feedback node

Amplifier feedback node. An external resistor is connected between

this node and tv_out2. The nominal value of ROUT2 is 1650 (1%).

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5.2 Electrical Specifications Over Recommended Operating Conditions

(T_MINto T_MAX, vdda_dac = 1.8 V, R_OUT1/2= 1650 , R_LOAD= 75 , unless otherwise noted)

Table 5-2. DAC Static Electrical Specification

PARAMETER

Resolution

DC ACCURACY

CONDITIONS/ASSUMPTIONS

MIN

TYP

MAX

UNIT

R

10

Bits

INL⁽¹⁾

DNL⁽²⁾

Integral nonlinearity

1

LSB

Differential nonlinearity

ANALOG OUTPUT

-

Full-scale output voltage

R_LOAD= 75

0,7

0.88

50

1

V

-

Output offset voltage

Output offset voltage drift

Gain error

mV

-

20

mV/C

% FS

-

17

19

R_VOUT

Output impedance

67.5

75

82.5

REFERENCE

V_REF

-

Reference voltage range

Reference noise density

0.525

3700

0.55

129

0.575

4200

V

100-kHz reference noise

bandwidth

R_SET

P_SRR

Full-scale current adjust resistor

Reference PSRR⁽³⁾(Up to 6 MHz)

4000

40

dB

POWER CONSUMPTION

I_vdda-up

Analog Supply Current⁽⁴⁾

-

2 channels, no load

2 channels

8

mA

Analog supply driving a 75- load

(RMS)

50

I_vdda-up(peak) Peak analog supply current:

Lasts less than 1 ns

60

2

mA

I_vdd-up

Digital supply current⁽⁵⁾

Measured at f_CLK= 54 MHz, f_OUT

= 2 MHz sine wave, vdd = 1.3 V

I_{vdd-up (peak)}

I_vdda-down

I_vdd-down

Peak digital supply current⁽⁶⁾

Analog power at power-down

Digital power at power-down

Lasts less than 1 ns

T = 30C, vdda = 1.8 V

T = 30C, vdd = 1.3 V

2.5

1.5

1

mA

(1) The INL is measured at the output of the DAC (accessible at an external pin during bypass mode).

(2) The DNL is measured at the output of the DAC (accessible at an external pin during bypass mode).

(3) Assuming a capacitor of 0.1 F at the tv_ref node.

(4) The analog supply current I_vddais directly proportional to the full-scale output current IFS and is insensitive to f_CLK

(5) The digital supply current I_VDDis dependent on the digital input waveform, the DAC update rate f_CLK, and the digital supply VDD.

(6) The peak digital supply current occurs at full-scale transition for duration less than 1 ns.

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(T_MINto T_MAX, vdda_dac = 1.8 V, R_OUT1/2= 1650 , R_LOAD= 75 , unless otherwise noted)

Table 5-3. Video DAC Dynamic Electrical Specification

PARAMETER

Output update rate

Clock jitter

CONDITIONS/ASSUMPTIONS

MIN

TYP

MAX

UNIT

MHz

ps

(1)

f_CLK

Equal to input clock frequency

54

rms clock jitter required in order to assure

10-bit accuracy

40

Attenuation at 5.1 MHz

Attenuation at 54 MHz⁽¹⁾

Output settling time

Corner frequency for signal

Image frequency

0.1

25

0.5

30

85

1.5

33

dB

ns

t_ST

Time from the start of the output transition to

output within 1 LSB of final value.

t_Rout

t_Fout

BW

Output rise time

Output fall time

Measured from 10% to 90% of full-scale

transition

25

ns

Measured from 10% to 90% of full-scale

transition

Signal bandwidth

Differential gain⁽²⁾

Differential phase⁽²⁾

Within bandwidth

6

1.5%

1

MHz

deg.

dB

SFDR

SNR

f_CLK= 54 MHz, f_OUT= 1 MHz

45

55⁽³⁾

Signal-to-noise ratio

dB

1 kHz to 6 MHz bandwidth

PSRR

Power supply rejection ratio Up to 6 MHz

20⁽⁴⁾

50

dB

Crosstalk Between the two video

channels

40

(1) For internal input clock information, For more information, see the Device Display Interface Subsystem Reference Guide [literature

number SPRUFV2].

(2) The differential gain and phase value is for dc coupling. Note that there is degradation for the ac coupling.

(3) The SNR value is for dc coupling. Note that there is a 6-dB degradation for ac coupling.

(4) The PSSR value is for dc coupling. Note that there is a 10-dB degradation for ac coupling.

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5.3 Analog Supply (vdda_dac) Noise Requirements

In order to assure 10-bit accuracy of the DAC analog output, the analog supply vdda_dac has to meet the

noise requirements stated in this section.

The DAC Power Supply Rejection Ratio is defined as the relative variation of the full-scale output current

divided by the supply variation. Thus, it is expressed in percentage of Full-Scale Range (FSR) per volt of

DI_OUT

100×

I_OUTFS

% FSR

PSRR_DAC

=

V

V_AC

supply variation as shown in the following equation:

Depending on frequency, the PSRR is defined in Table 5-4.

Table 5-4. Video DAC Power Supply Rejection Ratio

Supply Noise Frequency

PSRR % FSR/V

0 to 100 kHz

> 100 kHz

1

The rejection decreases 20 dB/dec.

Example: at 1 MHz the PSRR is 10% of FSR/V

A graphic representation is shown in Figure 5-2.

PSRR (% FSR/V)

First pole of

DAC output load

10

1

f

1 MHz

100 kHz

030-019

Figure 5-2. Video DAC Power Supply Rejection Ratio

To ensure that the DAC SFDR specification is met, the PSRR values and the clock jitter requirements

translate to the following limits on vdda_dac (for the Video DAC).

The maximum peak-to-peak noise on vdda (ripple) is defined in Table 5-5:

Table 5-5. Video DAC Maximum Peak-to-Peak Noise on vdda_dac

Tone Frequency

0 to 100 kHz

> 100 kHz

Maximum Peak-to-Peak Noise on vdda_dac

< 30 mVpp

Decreases 20 dB/dec.

Example: at 1 MHz the maximum is 3 mVpp

The maximum noise spectral density (white noise) is defined in Table 5-6:

Table 5-6. Video DAC Maximum Noise Spectral Density

Supply Noise Bandwidth

0 to 100 kHz

Maximum Supply Noise Density

< 20 V / Hz

> 100 kHz

Decreases 20 dB/dec.

Example: at 1 MHz the maximum noise density is 2 / Hz

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Because the DAC PSRR deteriorates at a rate of 20 dB/dec after 100 kHz, it is highly recommended to

have vdda_dac low pass filtered (proper decoupling) (see the illustrated application: Section 5.4, External

Component Value Choice).

5.4 External Component Value Choice

The full-scale output voltage V_OUTMAXis regulated by the reference amplifier, and is set by an internal

resistor R_SET. I_OUTMAXcan be expressed as:

I_OUTMAX= I_REF/8 * (63 + 15/16)

Where:

V_REF= 0.5V

I_REF= V_REF/R_SET

The output current I_OUTappearing at DAC output is a function of both the input code and I_OUTMAXand can

be expressed as:

I_OUT= (DAC_CODE/1023) * I_OUTMAX

Where:

DAC_CODE = 0 to 1023 is the DAC input code in decimal.

The output voltage is:

V_OUT= I_OUT*N* R_CABLE

Where:

(N = amplifier gain = 21)

R_CABLE= 75 (cable typical impedance)

The TV-out buffer requires a per channel external resistors: R_OUT1/2. The equation below can be used to

select different resistor values (if necessary):

R_OUT= (N+1) R_CABLE= 1650

Recommended parameter values are:

Table 5-7. Video DAC Recommended External Components Values

Recommended Value

UNIT

C_BG

100

nF

R_OUT1/2

1650

In order to limit the reference noise bandwidth and to suppress transients on V_REF, it is necessary to

connect a large decoupling capacitor _BG) between the tv_vref and vssa_dac pins.

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6 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

Note: The timing data shown is preliminary data and is subject to change in future revisions.

6.1 Timing Test Conditions

All timing requirements and switching characteristics are valid over the recommended operating conditions

of Table 3-3, unless otherwise specified.

6.2 Interface Clock Specifications

6.2.1 Interface Clock Terminology

The Interface clock is used at the system level to sequence the data and/or control transfers accordingly

with the interface protocol.

6.2.2 Interface Clock Frequency

The two interface clock characteristics are:

•

The maximum clock frequency

The maximum operating frequency

The interface clock frequency documented in this document is the maximum clock frequency, which

corresponds to the maximum frequency programmable on this output clock. This frequency defines the

maximum limit supported by the AM3517/05 IC and doesn't take into account any system consideration

(PCB, peripherals).

The system designer will have to consider these system considerations and AM3517/05 IC timings

characteristics as well, to define properly the maximum operating frequency, which corresponds to the

maximum frequency supported to transfer the data on this interface.

6.2.3 Clock Jitter Specifications

Jitter is a phase noise, which may alter different characteristics of a clock signal. The jitter specified in this

document is the time difference between the typical cycle period and the actual cycle period affected by

noise sources on the clock. The cycle (or period) jitter terminology identifies this type of jitter.

Cycle (or Period) Jitter

T_n-1

T_n

T_n+1

Max. Cycle Jitter = Max (T_i)

Min. Cycle Jitter = Min (T_i)

Jitter Standard Deviation (or rms Jitter) = Standard Deviation (T_i)

030-020

Figure 6-1. Cycle (or Period) Jitter

6.2.4 Clock Duty Cycle Error

The duty cycle error is the ratio between either the high-level pulse duration or the low-level pulse duration

and the cycle time of a clock signal.

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6.3 Timing Parameters

The timing parameter symbols used in the timing requirement and switching characteristic tables are

created in accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other

related terminologies have been abbreviated as follows:

Table 6-1. Timing Parameters

LOWERCASE SUBSCRIPTS

Symbols

Parameter

Cycle time (period)

Delay time

c

d

dis

en

h

Disable time

Enable time

Hold time

su

START

t

Setup time

Start bit

Transition time

Valid time

v

w

Pulse duration (width)

Unknown, changing, or dont care level

High

X

H

L

Low

V

Valid

IV

AE

FE

LE

Z

Invalid

Active Edge

First Edge

Last Edge

High impedance

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6.4 External Memory Interfaces

The AM3517/05 processor includes the following external memory interfaces:

•

General-purpose memory controller (GPMC)

SDRAM controller (SDRC)

6.4.1 General-Purpose Memory Controller (GPMC)

The GPMC is the AM3517/05 unified memory controller used to interface external memory devices such

as:

•

Asynchronous SRAM-like memories and ASIC devices

Asynchronous page mode and synchronous burst NOR flash

NAND flash

6.4.1.1 GPMC/NOR Flash Interface Synchronous Timing

Table 6-3 and Table 6-4 assume testing over the recommended operating conditions (see Figure 6-2

through Figure 6-5) and electrical characteristic conditions.

Table 6-2. GPMC/NOR Flash Synchronous Mode Timing Conditions

TIMING CONDITION PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

Input Conditions

t_R

Input signal rise time

Input signal fall time

TBD

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

TBD

pF

Table 6-3. GPMC/NOR Flash Interface Timing Requirements Synchronous Mode

NO.

PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

F12

t_su(DV-CLKH)

Setup time, read gpmc_d[15:0] valid before

gpmc_clk high

TBD

ns

F13

F21

t_h(CLKH-DV)

Hold time, gpmc_d[15:0] valid after gpmc_clk high

Setup time, gpmc_waitx⁽¹⁾valid before gpmc_clk

high

TBD

ns

t_{su(WAITV-CLKH)}

F22

t_{h(CLKH-WAITV)}

Hold Time, gpmc_waitx⁽¹⁾valid after gpmc_clk

high

TBD

ns

(1) Wait monitoring support is limited to a WaitMonitoringTime value > 0.

Table 6-4. GPMC/NOR Flash Interface Switching Characteristics Synchronous Mode

NO.

PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

F0

F1

t_c(CLK)

Cycle time⁽¹⁾, output clock gpmc_clk

period

TBD

ns

t_w(CLKH)

t_w(CLKL)

Typical pulse duration, output clock

gpmc_clk high

TBD

Typical pulse duration, output clock

gpmc_clk low

t_dc(CLK)

t_j(CLK)

Duty cycle error, output clk gpmc_clk

Jitter standard deviation⁽²⁾, output clock

gpmc_clk

TBD

ps

(1) Related to the gpmc_clk output clock maximum and minimum frequencies programmable in the I/F module by setting the

GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider.

(2) The jitter probability density can be approximated by a Gaussian function.

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Table 6-4. GPMC/NOR Flash Interface Switching Characteristics Synchronous Mode (continued)

NO.

PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

TBD

t_R(CLK)

Rise time, output clock gpmc_clk

Fall time, output clock gpmc_clk

Rise time, output data

ns

t_F(CLK)

t_R(DO)

t_F(DO)

Fall time, output data

F2

t_d(CLKH-nCSV)

Delay time, gpmc_clk rising edge to

gpmc_ncsx⁽³⁾transition

TBD

F3

t_{d(CLKH-nCSIV)}

t_d(ADDV-CLK)

t_{d(CLKH-ADDIV)}

t_d(nBEV-CLK)

t_{d(CLKH-nBEIV)}

t_d(CLKH-nADV)

t_{d(CLKH-nADVIV)}

t_d(CLKH-nOE)

t_{d(CLKH-nOEIV)}

t_d(CLKH-nWE)

t_d(CLKH-Data)

t_d(CLKH-nBE)

t_W(nCSV)

Delay time, gpmc_clk rising edge to

gpmc_ncsx⁽³⁾invalid

TBD

ns

F4

Delay time, address bus valid to

gpmc_clk first edge

F5

Delay time, gpmc_clk rising edge to

gpmc_a[16:1] invalid

F6

Delay time, gpmc_nbe0_cle, gpmc_nbe1

valid to gpmc_clk first edge

TBD

F7

Delay time, gpmc_clk rising edge to

gpmc_nbe0_cle, gpmc_nbe1 invalid

F8

Delay time, gpmc_clk rising edge to

gpmc_nadv_ale transition

F9

Delay time, gpmc_clk rising edge to

gpmc_nadv_ale invalid

F10

F11

F14

F15

F17

F18

Delay time, gpmc_clk rising edge to

gpmc_noe transition

Delay time, gpcm rising edge to

gpmc_noe invalid

Delay time, gpmc_clk rising edge to

gpmc_nwe transition

Delay time, gpmc_clk rising edge to data

bus transition

Delay time, gpmc_clk rising edge to

gpmc_nbex_cle transition

Pulse duration,

Read

Write

Read

Write

TBD

ns

gpmc_ncsx⁽³⁾low

F19

F20

t_W(nBEV)

Pulse duration,

gpmc_nbe0_cle,

gpmc_nbe1 low

t_W(nADVV)

Pulse duration,

gpmc_nadv_ale low

Read

Write

TBD

ns

F23

F24

t_{d(CLKH-IODIR)}

Delay time, gpmc_clk rising edge to

gpmc_io_dir high (IN direction)

TBD

t_{d(CLKH-IODIRIV)}

Delay time, gpmc_clk rising edge to

gpmc_io_dir low (OUT direction)

TBD

ns

(3) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

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F1

F0

F1

gpmc_clk

F2

F3

F7

F18

gpmc_ncsx

F4

gpmc_a[10:1]

Valid Address

F19

F6

gpmc_nbe0_cle

gpmc_nbe1

F19

F6

F8

F20

F9

gpmc_nadv_ale

gpmc_noe

F10

F11

F13

F12

D 0

gpmc_d[15:0]

gpmc_waitx

gpmc_io_dir

F23

F24

OUT

IN

OUT

030-021

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-2. GPMC/NOR Flash Synchronous Single Read (GpmcFCLKDivider = 0)

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F1

F0

F1

gpmc_clk

F2

F3

gpmc_ncsx

F4

F6

gpmc_a[10:1]

gpmc_nbe0_cle

gpmc_nbe1

Valid Address

F7

F9

F6

F8

gpmc_nadv_ale

gpmc_noe

F10

F11

F13

F12

D 0

F22

F12

D 3

gpmc_d[15:0]

gpmc_waitx

gpmc_io_dir

D 1

D 2

F21

F23

F24

OUT

IN

OUT

030-022

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-3. GPMC/NOR Flash Synchronous Burst Read 4x16-bit (GpmcFCLKDivider = 0)

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F1

F0

gpmc_clk

F2

F3

gpmc_ncsx

F4

gpmc_a[10:1]

Valid Address

F17

F6

F17

gpmc_nbe0_cle

gpmc_nbe1

gpmc_nadv_ale

gpmc_nwe

F8

F9

F14

F15

D 1

F15

D 2

F15

gpmc_d[15:0]

gpmc_waitx

D 0

D 3

gpmc_io_dir

OUT

030-023

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-4. GPMC/NOR Flash Synchronous Burst Write (GpmcFCLKDivider = 0)

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F1

F0

F1

gpmc_clk

gpmc_ncsx

F2

F3

F6

F4

F7

gpmc_nbe0_cle

gpmc_nbe1

Valid

F7

Valid

gpmc_a[26:17]

Address (MSB)

F5

F12

F13

D1 D2

F4

F12

gpmc_a[16:1]_d[15:0]

gpmc_nadv_ale

gpmc_noe

Address (LSB)

F8

D0

D3

F8

F9

F10

F11

gpmc_waitx

F24

F23

gpmc_io_dir

OUT

IN

OUT

030-024

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-5. GPMC/Multiplexed NOR Flash Synchronous Burst Read

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F1

F0

gpmc_clk

F2

F3

gpmc_ncsx

F4

gpmc_a[26:17]

Address (MSB)

F17

F6

F17

gpmc_nbe0_cle

gpmc_nbe1

F6

F8

F9

gpmc_nadv_ale

F14

gpmc_nwe

F15

D 1

F15

D 2

F15

gpmc_d[15:0]

gpmc_waitx

Address (LSB)

D 0

D 3

gpmc_io_dir

OUT

030-025

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-6. GPMC/Multiplexed NOR Flash Synchronous Burst Write

6.4.1.2 GPMC/NOR Flash Interface Asynchronous Timing

Table 6-7 and Table 6-8 assume testing over the recommended operating conditions (see Figure 6-7

through Figure 6-12) and electrical characteristic conditions.

Table 6-5. GPMC/NOR Flash Asynchronous Mode Timing Conditions

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

1.8

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

15.94

pF

Table 6-6. GPMC/NOR Flash Interface Asynchronous Timing – Internal Parameters⁽¹⁾⁽²⁾

NO.

PARAMETER

1.8V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

FI1

FI2

FI3

Maximum output data generation delay from internal

functional clock

6.5

9.1

13.7

ns

Maximum input data capture delay by internal

functional clock

4

5.6

9.1

8.1

Maximum device select generation delay from internal

functional clock

6.5

13.7

(1) The internal parameters table must be used to calculate Data Access Time stored in the corresponding CS register bit field.

(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.

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Table 6-6. GPMC/NOR Flash Interface Asynchronous Timing – Internal Parameters (continued)

NO.

PARAMETER

1.8V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

FI4

FI5

FI6

FI7

FI8

FI9

Maximum address generation delay from internal

functional clock

6.5

9.1

13.7

ns

ps

Maximum address valid generation delay from internal

functional clock

6.5

100

9.1

170

13.7

200

Maximum byte enable generation delay from internal

functional clock

Maximum output enable generation delay from internal

functional clock

Maximum write enable generation delay from internal

functional clock

Maximum functional clock skew

Table 6-7. GPMC/NOR Flash Interface Timing Requirements – Asynchronous Mode

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN MAX

MIN

MAX

MIN

MAX

FA5⁽¹⁾

t_acc(DAT)

Data maximum access

time

H⁽²⁾

P⁽⁴⁾

H⁽²⁾

GPMC_FCLK cycles

FA20⁽³⁾t_{acc1-pgmode(DAT)}Page mode successive

P⁽⁴⁾

data maximum access

time

FA21⁽⁵⁾t_{acc2-pgmode(DAT)}Page mode first data

maximum access time

H⁽²⁾

GPMC_FCLK cycles

(1) The FA5 parameter illustrates the amount of time required to internally sample input Data. It is expressed in number of GPMC functional

clock cycles. From start of read cycle and after FA5 functional clock cycles, input Data is internally sampled by active functional clock

edge. FA5 value must be stored inside the AccessTime register bit field.

(2) H = AccessTime * (TimeParaGranularity + 1)

(3) The FA20 parameter illustrates amount of time required to internally sample successive input Page Data. It is expressed in number of

GPMC functional clock cycles. After each access to input Page Data, next input Page Data is internally sampled by active functional

clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.

(4) P = PageBurstAccessTime * (TimeParaGranularity + 1)

(5) The FA21 parameter illustrates amount of time required to internally sample first input Page Data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA21 functional clock cycles, First input Page Data is internally sampled by

active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.

Table 6-8. GPMC/NOR Flash Interface Switching Characteristics – Asynchronous Mode

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

2.0

MIN

MAX

2.0

MIN

MAX

2.0

t_R(DO)

Rise time, output data

ns

t_F(DO)

Fall time, output data

Pulse duration, Read

2.0

FA0

t_W(nBEV)

N⁽¹²⁾

gpmc_nbe0_cl

e, gpmc_nbe1

Write

valid time

FA1

FA3

t_W(nCSV)

Pulse duration, Read

A⁽¹⁾

ns

gpmc_ncsx⁽¹³⁾

Write

v low

t_{d(nCSV-nADVIV)}

Delay time,

gpmc_ncsx⁽¹³⁾

valid to

Read

Write

B⁽²⁾– 0.2

B⁽²⁾+ 2.0

B⁽²⁾– 0.2

B⁽²⁾+ 2.6

B⁽²⁾– 0.2

B⁽²⁾+ 3.7

ns

gpmc_nadv_al

e invalid

FA4

t_{d(nCSV-nOEIV)}

Delay time,

C⁽³⁾– 0.2

C⁽³⁾+ 2.0

C⁽³⁾– 0.2

C⁽³⁾+ 2.6

C⁽³⁾– 0.2

C⁽³⁾+ 3.7

ns

gpmc_ncsx⁽¹³⁾valid to

gpmc_noe invalid

(Single read)

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Table 6-8. GPMC/NOR Flash Interface Switching Characteristics – Asynchronous Mode (continued)

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

FA9

t_d(AV-nCSV)

Delay time, address

J⁽⁹⁾– 0.2

J⁽⁹⁾+ 2.0

J⁽⁹⁾– 0.2

J⁽⁹⁾+ 2.6

J⁽⁹⁾– 0.2

J⁽⁹⁾+ 3.7

ns

bus valid to

gpmc_ncsx⁽¹³⁾valid

FA10 t_d(nBEV-nCSV)

Delay time,

J⁽⁹⁾– 0.2

J⁽⁹⁾+ 2.0

J⁽⁹⁾– 0.2

J⁽⁹⁾+ 2.6

J⁽⁹⁾– 0.2

J⁽⁹⁾+ 3.7

ns

gpmc_nbe0_cle,

gpmc_nbe1 valid to

gpmc_ncsx⁽¹³⁾valid

FA12 t_{d(nCSV-nADVV)}

FA13 t_d(nCSV-nOEV)

FA14 t_{d(nCSV-IODIR)}

FA15 t_{d(nCSV-IODIR)}

FA16 t_w(AIV)

Delay time,

K⁽¹⁰⁾– 0.2 K⁽¹⁰⁾+ 2.0 K⁽¹⁰⁾– 0.2 K⁽¹⁰⁾+ 2.6 K⁽¹⁰⁾– 0.2 K⁽¹⁰⁾+ 3.7

L⁽¹¹⁾– 0.2 L⁽¹¹⁾+ 2.0 L⁽¹¹⁾– 0.2 L⁽¹¹⁾+ 2.6 L⁽¹¹⁾– 0.2 L⁽¹¹⁾+ 3.7

M⁽¹⁴⁾– 0.2 M⁽¹⁴⁾+ 2.0 M⁽¹⁴⁾– 0.2 M⁽¹⁴⁾+ 2.6 M⁽¹⁴⁾– 0.2 M⁽¹⁴⁾+ 3.7

ns

gpmc_ncsx⁽¹³⁾valid to

gpmc_nadv_ale valid

Delay time,

gpmc_ncsx⁽¹³⁾valid to

gpmc_noe valid

Delay time,

gpmc_ncsx⁽¹³⁾valid to

gpmc_io_dir high

Delay time,

gpmc_ncsx⁽¹³⁾valid to

gpmc_io_dir low

Address invalid

duration between 2

successive R/W

accesses

G⁽⁷⁾

FA18 t_{d(nCSV-nOEIV)}

Delay time,

I⁽⁸⁾– 0.2

I⁽⁸⁾+ 2.0

I⁽⁸⁾– 0.2

I⁽⁸⁾+ 2.6

I⁽⁸⁾– 0.2

I⁽⁸⁾+ 3.7

ns

gpmc_ncsx⁽¹³⁾valid to

gpmc_noe invalid

(Burst read)

FA20 t_w(AV)

Pulse duration, address

valid – 2nd, 3rd, and

4th accesses

D⁽⁴⁾

ns

FA25 t_d(nCSV-nWEV)

Delay time,

E⁽⁵⁾– 0.2

F⁽⁶⁾– 0.2

E⁽⁵⁾+ 2.0

F⁽⁶⁾+ 2.0

E⁽⁵⁾– 0.2

F⁽⁶⁾– 0.2

E⁽⁵⁾+ 2.6

F⁽⁶⁾+ 2.6

E⁽⁵⁾– 0.2

F⁽⁶⁾– 0.2

E⁽⁵⁾+ 3.7

F⁽⁶⁾+ 3.7

gpmc_ncsx⁽¹³⁾valid to

gpmc_nwe valid

FA27 t_{d(nCSV-nWEIV)}

Delay time,

gpmc_ncsx⁽¹³⁾valid to

gpmc_nwe invalid

FA28 t_d(nWEV-DV)

FA29 t_d(DV-nCSV)

Delay time, gpmc_ new

valid to data bus valid

2.0

2.6

3.7

ns

Delay time, data bus

valid to gpmc_ncsx⁽¹³⁾

valid

J⁽⁹⁾– 0.2

J⁽⁹⁾+ 2.0

J⁽⁹⁾– 0.2

J⁽⁹⁾+ 2.6

J⁽⁹⁾– 0.2

J⁽⁹⁾+ 3.7

FA37 t_d(nOEV-AIV)

Delay time, gpmc_noe

valid to

2.0

2.6

3.7

ns

gpmc_a[16:1]_d[15:0]

address phase end

(1) For single read: A = (CSRdOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For single write: A = (CSWrOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK with n

being the page burst access number

(2) For reading: B = ((ADVRdOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK

For writing: B = ((ADVWrOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK

(3) C = ((OEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK

(4) D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK

(5) E = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK

(6) F = ((WEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK

(7) G = Cycle2CycleDelay * GPMC_FCLK

(8) I = ((OEOffTime + (n – 1) * PageBurstAccessTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) *

GPMC_FCLK

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(9) J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK

(10) K = ((ADVOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK

(11) L = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK

(12) For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK

For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: N = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst write: N = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

(13) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.

(14) M = ((RdCycleTime - CSOnTime) * (TimeParaGranularity + 1) - 0.5 * CSExtraDelay) * GPMC_FCLK

Above M parameter expression is given as one example of GPMC programming. IO DIR signal will go from IN to OUT after both

RdCycleTime and BusTurnAround completion. Behavior of IO direction signal does depend on kind of successive Read/Write accesses

performed to Memory and multiplexed or non-multiplexed memory addressing scheme, bus keeping feature enabled or not. IO DIR

behavior is automatically handled by GPMC controller.

GPMC_FCLK

gpmc_clk

FA5

FA1

gpmc_ncsx

FA9

gpmc_a[10:1]

Valid Address

FA0

FA10

gpmc_nbe0_cle

gpmc_nbe1

Valid

FA0

Valid

FA10

FA3

FA12

gpmc_nadv_ale

FA4

FA13

gpmc_noe

gpmc_d[15:0]

Data IN 0

gpmc_waitx

gpmc_io_dir

FA15

FA14

OUT

IN

OUT

030-026

Figure 6-7. GPMC/NOR Flash – Asynchronous Read – Single Word Timing^(1)(2)(3)

(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock

cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge.

FA5 value must be stored inside AccessTime register bit field.

(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

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GPMC_FCLK

gpmc_clk

FA5

FA1

gpmc_ncsx

FA16

FA9

gpmc_a[10:1]

Address 0

FA0

Address 1

FA0

FA10

gpmc_nbe0_cle

Valid

FA0

Valid

FA0

gpmc_nbe1

FA10

Valid

FA10

FA3

FA12

gpmc_nadv_ale

FA4

FA13

gpmc_noe

Data Upper

gpmc_d[15:0]

gpmc_waitx

FA15

FA14

OUT

FA14

OUT

gpmc_io_dir

IN

030-027

Figure 6-8. GPMC/NOR Flash – Asynchronous Read – 32-bit Timing^(1)(2)(3)

(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock

cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge.

FA5 value must be stored inside AccessTime register bit field.

(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

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GPMC_FCLK

gpmc_clk

FA21

FA20

Add1

FA20

Add3

FA20

FA1

gpmc_ncsx

FA9

gpmc_a[10:1]

Add0

Add2

Add4

FA0

FA10

gpmc_nbe0_cle

FA0

gpmc_nbe1

FA12

gpmc_nadv_ale

FA18

FA13

gpmc_noe

D3

gpmc_d[15:0]

D0

D1

D2

D3

gpmc_waitx

gpmc_io_dir

FA15

FA14

OUT

IN

030-028

Figure 6-9. GPMC/NOR Flash – Asynchronous Read – Page Mode 4x16-bit Timing^(1)(2)(3)(4)

(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

(2) FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by

active functional clock edge. FA21 value must be stored inside AccessTime register bit field.

(3) FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC

functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock edge

after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first input

page data). FA20 value must be stored in PageBurstAccessTime register bit field.

(4) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

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gpmc_fclk

gpmc_clk

FA1

gpmc_ncsx

FA9

gpmc_a[10:1]

Valid Address

FA0

FA10

gpmc_nbe0_cle

FA0

FA10

gpmc_nbe1

FA3

FA12

gpmc_nadv_ale

FA27

FA25

gpmc_nwe

gpmc_d[15:0]

gpmc_waitx

gpmc_io_dir

FA29

Data OUT

OUT

030-029

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-10. GPMC/NOR Flash – Asynchronous Write – Single Word Timing

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GPMC_FCLK

gpmc_clk

FA1

FA5

gpmc_ncsx

FA9

gpmc_a[26:17]

Address (MSB)

FA0

FA10

gpmc_nbe0_cle

gpmc_nbe1

Valid

FA0

Valid

FA3

FA12

gpmc_nadv_ale

gpmc_noe

FA4

FA13

FA29

FA37

Data IN

gpmc_a[16:1]_d[15:0]

gpmc_io_dir

Address (LSB)

FA15

FA14

OUT

IN

gpmc_waitx

030-030

Figure 6-11. GPMC/Multiplexed NOR Flash – Asynchronous Read – Single Word Timing^(1)(2)(3)

(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock

cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge.

FA5 value must be stored inside AccessTime register bit field.

(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

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gpmc_fclk

gpmc_clk

FA1

gpmc_ncsx

FA9

gpmc_a[26:17]

Address (MSB)

FA0

FA10

gpmc_nbe0_cle

FA0

FA10

gpmc_nbe1

FA3

FA12

gpmc_nadv_ale

FA27

FA25

gpmc_nwe

gpmc_a[16:1]_d[15:0]

gpmc_waitx

FA29

Valid Address (LSB)

FA28

Data OUT

gpmc_io_dir

OUT

030-031

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-12. GPMC/Multiplexed NOR Flash – Asynchronous Write – Single Word Timing

6.4.1.3 GPMC/NAND Flash Interface Timing

Table 6-10 through Table 6-12 assume testing over the recommended operating conditions (see

Figure 6-13 through Figure 6-16) and electrical characteristic conditions.

Table 6-9. GPMC/NAND Flash Asynchronous Mode Timing Conditions

TIMING CONDITION PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

Input Conditions

t_R

t_F

Input signal rise time

Input signal fall time

1.8

ns

C_LOAD

Output load capacitance

55

pF

Table 6-10. GPMC/NAND Flash Interface Asynchronous Timing Internal Parameters⁽¹⁾⁽²⁾

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

GNFI1

Maximum output data generation delay from

internal functional clock

6.5

9.1

13.7

ns

(1) Internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.

(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.

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Table 6-10. GPMC/NAND Flash Interface Asynchronous Timing Internal Parameters (continued)

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

GNFI2

GNFI3

GNFI4

GNFI5

GNFI6

GNFI7

GNFI8

Maximum input data capture delay by internal

functional clock

4

5.6

8.1

ns

ps

Maximum device select generation delay from

internal functional clock

6.5

100

9.1

170

13.7

200

Maximum address latch enable generation delay

from internal functional clock

Maximum command latch enable generation

delay from internal functional clock

Maximum output enable generation delay from

internal functional clock

Maximum write enable generation delay from

internal functional clock

Maximum functional clock skew

Table 6-11. GPMC/NAND Flash Interface Timing Requirements

NO.

PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

GNF12⁽¹⁾

t_acc(DAT)

Data maximum access time

J⁽²⁾

GPMC_FCLK cycles

(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC

functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the

active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.

(2) J = AccessTime * (TimeParaGranularity + 1)

Table 6-12. GPMC/NAND Flash Interface Switching Characteristics

NO.

PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

2.0

t_R(DO)

Rise time, output data

ns

t_F(DO)

Fall time, output data

2.0

GNF0

GNF1

GNF2

GNF3

GNF4

GNF5

GNF6

GNF7

GNF8

t_w(nWEV)

Pulse duration, gpmc_nwe

valid time

A⁽¹⁾

t_d(nCSV-nWEV)

t_w(CLEH-nWEV)

t_w(nWEV-DV)

Delay time, gpmc_ncsx⁽¹³⁾

valid to gpmc_nwe valid

B⁽²⁾- 0.2

C⁽³⁾- 0.2

D⁽⁴⁾- 0.2

E⁽⁵⁾- 0.2

F⁽⁶⁾- 0.2

G⁽⁷⁾- 0.2

C⁽³⁾- 0.2

F⁽⁶⁾- 0.2

B⁽²⁾+ 2.0

C⁽³⁾+ 2.0

D⁽⁴⁾+ 2.0

E⁽⁵⁾+ 2.0

F⁽⁶⁾+ 2.0

G⁽⁷⁾+ 2.0

C⁽³⁾+ 2.0

F⁽⁶⁾+ 2.0

ns

Delay time, gpmc_nbe0_cle

high to gpmc_nwe valid

Delay time, gpmc_d[15:0]

valid to gpmc_nwe valid

t_w(nWEIV-DIV)

t_{w(nWEIV-CLEIV)}

t_{w(nWEIV-nCSIV)}

t_w(ALEH-nWEV)

t_{w(nWEIV-ALEIV)}

Delay time, gpmc_nwe invalid

to gpmc_d[15:0] invalid

Delay time, gpmc_nwe invalid

to gpmc_nbe0_cle invalid

Delay time, gpmc_nwe invalid

to gpmc_ncsx⁽¹³⁾invalid

Delay time, gpmc_nadv_ale

High to gpmc_nwe valid

Delay time, gpmc_nwe invalid

to gpmc_nadv_ale invalid

GNF9

t_c(nWE)

Cycle time, Write cycle time

Delay time, gpmc_ncsx⁽¹³⁾

valid to gpmc_noe valid

H⁽⁸⁾

ns

GNF10

t_d(nCSV-nOEV)

I⁽⁹⁾- 0.2

I⁽⁹⁾+ 2.0

GNF13

GN F14

t_w(nOEV)

t_c(nOE)

Pulse duration, gpmc_noe

valid time

K⁽¹⁰⁾

L⁽¹¹⁾

ns

Cycle time, Read cycle time

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Table 6-12. GPMC/NAND Flash Interface Switching Characteristics (continued)

NO.

PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

GNF15

t_{w(nOEIV-nCSIV)}

Delay time, gpmc_noe invalid

to gpmc_ncsx⁽¹³⁾invalid

M⁽¹²⁾- 0.2

M⁽¹²⁾+ 2.0

ns

(1) A = (WEOffTime – WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

(2) B = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK

(3) C = ((WEOnTime – ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – ADVExtraDelay)) * GPMC_FCLK

(4) D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay ) * GPMC_FCLK

(5) E = (WrCycleTime – WEOffTime * (TimeParaGranularity + 1) – 0.5 * WEExtraDelay ) * GPMC_FCLK

(6) F = (ADVWrOffTime – WEOffTime * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – WEExtraDelay ) * GPMC_FCLK

(7) G = (CSWrOffTime – WEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – WEExtraDelay ) * GPMC_FCLK

(8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK

(9) I = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK

(10) K = (OEOffTime – OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK

(11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK

(12) M = (CSRdOffTime – OEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – OEExtraDelay ) * GPMC_FCLK

(13) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.

GPMC_FCLK

GNF1

GNF2

GNF6

GNF5

gpmc_ncsx

gpmc_nbe0_cle

gpmc_nadv_ale

gpmc_noe

GNF0

gpmc_nwe

GNF3

GNF4

gpmc_a[16:1]_d[15:0]

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.

Command

030-032

Figure 6-13. GPMC/NAND Flash – Command Latch Cycle Timing

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GPMC_FCLK

gpmc_ncsx

GNF1

GNF7

GNF6

gpmc_nbe0_cle

gpmc_nadv_ale

gpmc_noe

GNF8

GNF9

GNF0

gpmc_nwe

GNF3

GNF4

gpmc_a[16:1]_d[15:0]

Address

030-033

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.

Figure 6-14. GPMC/NAND Flash – Address Latch Cycle Timing

GPMC_FCLK

GNF12

GNF10

GNF15

gpmc_ncsx

gpmc_nbe0_cle

gpmc_nadv_ale

GNF14

GNF13

gpmc_noe

gpmc_a[16:1]_d[15:0]

DATA

gpmc_waitx

030-034

Figure 6-15. GPMC/NAND Flash – Data Read Cycle Timing^(1)(2)(3)

(1) The GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional

clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data is internally sampled by active functional clock

edge. The GNF12 value must be stored inside AccessTime register bit field.

(2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

(3) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0 ,1, 2, or 3.

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GPMC_FCLK

gpmc_ncsx

GNF1

GNF6

gpmc_nbe0_cle

gpmc_nadv_ale

gpmc_noe

GNF9

GNF0

gpmc_nwe

GNF3

GNF4

gpmc_a[16:1]_d[15:0]

DATA

030-035

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0 or 1.

Figure 6-16. GPMC/NAND Flash – Data Write Cycle Timing

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6.4.2 DDR2 Memory Controller

The DDR2 Memory Controller is a dedicated interface to DDR2 SDRAM. It supports JESD79D-2A

standard compliant DDR2 SDRAM devices and compliant Mobile DDR SDRAM devices. DDR2 SDRAM

plays a key role in an AM3517/05-based system. Such a system is expected to require a significant

amount of high-speed external memory for all of the following functions:

•

Buffering of input image data from sensors or video sources

Intermediate buffering for processing/resizing of image data in the VPFE

Numerous OSD display buffers

Intermediate buffering for large raw Bayer data image files while performing image processing

functions

•

Buffering for intermediate data while performing video encode and decode functions

Storage of executable code for the ARM

The DDR2 Memory Controller supports the following features:

•

JESD79D-2A standard compliant DDR2 SDRAM

Mobile DDR SDRAM

256 MByte memory space

Data bus width 16 bits

CAS latencies:

–

DDR2: 2, 3, 4, and 5

Internal banks:

DDR2: 1, 2, 4, and 8

•

–

•

Burst length: 8

Burst type: sequential

•

1 CS signal

Page sizes: 256, 512, 1024, and 2048

SDRAM autoinitialization

Self-refresh mode

Partial array self-refresh

Power down mode

Prioritized refresh

Programmable refresh rate and backlog counter

Programmable timing parameters

Little endian

6.4.3 DDR2 Memory Controller Electrical Data/Timing

Table 6-13. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory

Controller⁽¹⁾⁽²⁾(see )

NO

.

PARAMETER

MIN MAX UNIT

333-DDR2 (supported for 216-MHz device)

216-DDR2 (supported for 270-MHz device)

243-DDR2 (supported for 300-MHz device)

90 TBD

1

t_{c(sdrc_clk)}

Cycle time, sdrc_clk

90 216

MHz

90 243

(1) sdrc_clk cycle time = 2 x PLLC1.SYSCLK7 or 2 x PLLC2.SYSCLK3 cycle time.

(2) The PLL2 Controller must be programmed such that the resulting sdrc_nclk clock frequency is within the specified range.

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1

sdrc_clk

Figure 6-17. DDR2 Memory Controller Clock Timing

6.4.3.1 DDR2 Interface

This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing

specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,

and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need

for a complex timing closure process. For more information regarding guidelines for using this DDR2

specification, Understanding TI's PCB Routing Rule-Based DDR2 Timing Specification (SPRAAV0).

6.4.3.1.1 DDR2 Interface Schematic

Figure 6-18 shows the DDR2 interface schematic for a single-memory DDR2 system. The dual-memory

system shown in Figure 6-19. Pin numbers for the AM3517/05 can be obtained from the pin description

section.

6.4.3.1.2 Compatible JEDEC DDR2 Devices

Table 6-14 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface.

Generally, the DDR2 interface is compatible with x16 DDR2 speed grade DDR2 devices.

The AM3517/05 also supports JEDEC DDR2 x8 devices in the dual chip configuration. In this case, one

chip supplies the upper byte and the second chip supplies the lower byte. Addresses and most control

signals are shared just like regular dual chip memory configurations.

Table 6-14. Compatible JEDEC DDR2 Devices

No.

1

Parameter

Min

Max

Unit

Notes

(1)

(2)

JEDEC DDR2 Device Speed Grade

JEDEC DDR2 Device Bit Width

JEDEC DDR2 Device Count

JEDEC DDR2 Device Ball Count

DDR2-333 MHz

See Note

2

x16

1

x32

2

Bits

Devices

Balls

3

4

84

92

See Note

(1) Higher DDR2 speed grades are supported due to inherent JEDEC DDR2 backwards compatibility.

(2) 92 ball devices retained for legacy support. New designs will migrate to 84 ball DDR2 devices. Electrically, the 92 and 84 ball DDR2

devices are the same.

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6.4.3.1.3 PCB Stackup

The minimum stackup required for routing the AM3517/05 is a six layer stack as shown in Table 6-15.

Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size

of the PCB footprint.

Table 6-15. Minimum PCB Stack Up

Layer

Type

Signal

Plane

Signal

Plane

Signal

Description

Top Routing Mostly Horizontal

Ground

1

2

3

4

5

6

Power

Internal Routing

Ground

Bottom Routing Mostly Vertical

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Complete stack up specifications are provided in Table 6-16.

AM35x

SDRC_D0

T

DQ0

DQ7

T

SDRC_D7

T

LDM

LDQS

LDQS#

SDRC_DM0

SDRC_DQS0P

SDRC_DQS0N

SDRC_D8

LQ8

T

LQ15

SDRC_D15

T

SDRC_DM1

SDRC_DQS1P

UDM

UDQS

SDRC_DQS1N

UDQS#

T

SDRC_STRBEN0

SDRC_STRBEN_DLY0

Length = avg DQS0-1 length+CLK

x16 DDR2

SDRC_D16

T

DQ0

T

SDRC_D23

DQ7

LDM

SDRC_DM2

SDRC_DQS2P

SDRC_DQS2N

T

LDQS

LDQS#

SDRC_D24

T

DQ8

SDRC_D31

DQ15

T

UDM

SDRC_DM3

SDRC_DQS3P

SDRC_DQS3N

UDQS

UDQS#

T

SDRC_STRBEN1

SDRC_STRBEN_DLY1

Length = avg DQS2-3 length+CLK

T

BA0

BA1

BA2*

BA0

BA1

BA2*

SDRC_BA0

SDRC_BA1

SDRC_BA2

A0

T

SDRC_A0

A14*

SDRC_A14

T

CS1

CS2*

CAS#

CS1

CS2*

CAS#

SDRC_nCS0

SDRC_nCS1

SDRC_nCAS

SDRC_nRAS

SDRC_nWE

SDRC_nCKE0

SDRC_CLK

Vio1.8*

RAS#

WE#

RAS#

WE#

CLK

0.1

mF

SDRC_nCLK

CLK#

1K W

T

SDRC_ODT0

VREFSSTL

ODT*

VREF

ODT*

VREF

1%

0.1mF

0.1mF**

0.1

mF**

1K W

DDR_PADREF

1%

50 1%

SPRS550-008

Figure 6-18. DDR2 Single-Memory High Level Schematic

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DDR2

SDRC_D0

DQ0

T

SDRC_D7

DQ7

SDRC_DM0

SDRC_DQS0P

SDRC_DQS0N

DM0

DQS0

DQS0#

T

DQ8

SDRC_D8

T

SDRC_D15

T

DQ15

SDRC_DM1

SDRC_DQS1P

SDRC_DQS1N

DM1

DQS1

DQS1#

T

SDRC_STRBEN0

SDRC_STRBEN_DLY0

T

Length = avg D0-D15 length+CLK

T

SDRC_D16

SDRC_D23

DQ16

DQ23

T

SDRC_DM2

SDRC_DQS2P

SDRC_DQS2N

DM2

DQS2

DQS2#

SDRC_D24

DQ24

DQ31

T

SDRC_D31

T

SDRC_DM3

SDRC_DQS3P

SDRC_DQS3N

DM3

DQS3

DQS3#

SDRC_STRBEN1

T

Length = avg D16-D31 length+CLK

SDRC_STRBEN_DLY1

BA0

BA1

BA2*

T

SDRC_BA0

SDRC_BA1

SDRC_BA2

A0

T

SDRC_A0

A14*

SDRC_A14

SDRC_nCS0

SDRC_nCS1

SDRC_nCAS

SDRC_nRAS

SDRC_nWE

SDRC_nCKE0

CS1

T

CS2*

CAS#

RAS#

WE#

CKE

Vio1.8*

CLK

CLK#

SDRC_CLK

SDRC_nCLK

0.1mF

1K W 1%

SDRC_ODT0

ODT*

VREF

T

VREFSSTL

0.1mF**

1K W 1%

DDR_PADREF

50 1%

SPRS550-009

Figure 6-19. DDR2 Dual-Memory High Level Schematic

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Table 6-16. PCB Stack Up Specifications

No. Parameter

Min

6

Typ

Max Unit

Notes

1

2

PCB Routing/Plane Layers

Signal Routing Layers

3

Full ground layers under DDR2 routing Region

Number of ground plane cuts allowed within DDR routing region

Number of ground reference planes required for each DDR2 routing layer

Number of layers between DDR2 routing layer and ground plane

PCB Routing Feature Size

2

4

0

5

1

6

0

7

4

Mils

8

PCB Trace Width w

9

PCB BGA escape via pad size

20

10

12

10

11

12

13

14

PCB BGA escape via hole size

(1)

AM3517/05 BGA pad size

See Note

(2)

DDR2 Device BGA pad size

See Note

Single Ended Impedance, Zo

50

75

Ω

(3)

Impedance Control

Z-5

Z

Z+5

See Note

(1) The recommended pad size is 0.3 mm per IPC-7351 specification.

(2) Please refer to IPC standard IPC-7351 or manufacturer's recommendations for correct BGA pad size.

(3) Z is the nominal singled ended impedance selected for the PCB specified by item 12.

6.4.3.1.4 Placement

Figure 6-19 shows the required placement for the DDR2 devices. The dimensions for Figure 6-20 are

defined in Table 6-17. The placement does not restrict the side of the PCB that the devices are mounted

on. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper

routing space. For single-memory DDR2 systems, the second DDR2 device is omitted from the

placement.

X

A1

Y

OFFSET

DDR2

Device

Y

AM3517/05

OFFSET

A1

Recommended DDR2

Device Orientation

Figure 6-20. DDR2 Device Placement

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Table 6-17. Placement Specifications

No. Parameter

Min

Max

1750

1280

650

Unit

Mils

Notes

See Notes

(1) (2)

1

2

3

X

,

(1) (2)

Y

,

(1) (2)

Y Offset

See Notes

.

,

(3)

(4)

4

5

DDR2 Keepout Region

See Note

(5)

Clearance from non-DDR2 signal to DDR2 Keepout Region

4

w

(1) See Figure 6-18 for dimension definitions.

(2) Measurements from center of AM3517/05 device to center of DDR2 device.

(3) For single memory systems it is recommended that Y Offset be as small as possible.

(4) DDR2 Keepout region to encompass entire DDR2 routing area

(5) Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground plane.

6.4.3.1.5 DDR2 Keep Out Region

The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2 keep

out region is defined for this purpose and is shown in Figure 6-21. The size of this region varies with the

placement and DDR routing. Additional clearances required for the keep out region are shown in

Table 6-17.

A1

DDR2

Device

A1

Region should encompass all DDR2 circuitry and varies depending

on placement. Non-DDR2 signals should not be routed on the DDR

signal layers within the DDR2 keep out region. Non-DDR2 signals may

be routed in the region provided they are routed on layers separated

from DDR2 signal layers by a ground layer. No breaks should be

allowed in the reference ground layers in this region. In addition, the

1.8 V power plane should cover the entire keep out region.

Figure 6-21. DDR2 Keepout Region

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6.4.3.1.6 Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry.

Table 6-18 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note

that this table only covers the bypass needs of the AM3517/05 and DDR2 interfaces. Additional bulk

bypass capacitance may be needed for other circuitry.

Table 6-18. Bulk Bypass Capacitors

No. Parameter

Min

Max

Unit

Notes

1

V_{DD18_DDR}Bulk Bypass Capacitor Count

3

Devices See Note

(1)

2

3

V_{DD18_DDR}Bulk Bypass Total Capacitance

DDR#1 Bulk Bypass Capacitor Count

30

1

uF

Devices See Note

(1)

4

5

DDR#1 Bulk Bypass Total Capacitance

DDR#2 Bulk Bypass Capacitor Count

22

1

uF

Devices See Notes

(1) (2)

,

6

DDR#2 Bulk Bypass Total Capacitance

22

uF

See Note

(2)

(1) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed

(HS) bypass caps.

(2) Only used on dual-memory systems

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6.4.3.1.7 High-Speed Bypass Capacitors

High-speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly

important to minimize the parasitic series inductance of the HS bypass cap, AM3517/05/DDR2 power, and

AM3517/05/DDR2 ground connections. Table 6-19 contains the specification for the HS bypass capacitors

as well as for the power connections on the PCB.

6.4.3.1.8 Net Classes

Table 6-20 lists the clock net classes for the DDR2 interface. Table 6-21 lists the signal net classes, and

associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the

termination and routing rules that follow.

Table 6-19. High-Speed Bypass Capacitors

No. Parameter

Min

Max

0402

250

Unit

10 Mils

Mils

Notes

(1)

(2)

1

2

3

4

5

6

7

8

9

HS Bypass Capacitor Package Size

See Note

Distance from HS bypass capacitor to device being bypassed

Number of connection vias for each HS bypass capacitor

Trace length from bypass capacitor contact to connection via

Number of connection vias for each DDR2 device power or ground balls

Trace length from DDR2 device power ball to connection via

V_{DD18_DDR}HS Bypass Capacitor Count

2

1

Vias

See Note

30

35

Mils

Vias

Mils

(3)

20

1.2

8

Devices

µF

See Note

V_{DD18_DDR}HS Bypass Capacitor Total Capacitance

DDR#1 HS Bypass Capacitor Count

Devices

µF

10 DDR#1 HS Bypass Capacitor Total Capacitance

11 DDR#2 HS Bypass Capacitor Count

0.4

8

Devices

See Notes

(3) (4)

,

(4)

12 DDR#2 HS Bypass Capacitor Total Capacitance

0.4

µF

See Note

(1) LxW, 10 mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor

(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.

(3) These devices should be placed as close as possible to the device being bypassed.

(4) Only used on dual-memory systems

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Table 6-20. Clock Net Class Definitions

Clock Net Class

AM3517/05 Device Pin Names

sdrc_clk/sdrc_nclk

CK

DQS0

DQS1

sdrc_dqs0p /sdrc_dqs0n

sdrc_dqs1p /sdrc_dqs1n

Table 6-21. Signal Net Class Definitions

Associated Clock Net

Clock Net Class

Class

AM3517/05 Device Pin Names

ADDR_CTRL

CK

sdrc_ba[2:0], sdrc_a[13:0], sdrc_ncs0 , sdrc_ncas, sdrc_nras, sdrc_nwe,

sdrc_cke0

DQ0

DQ1

DQS0

sdrc_d[7:0], sdrc_dm0

DQS1

sdrc_d[15:8], sdrc_dm1

sdrc_strben0, sdrc_strben_dly0

SDRC_STRBENx

CK, DQS0, DQS1

6.4.3.1.9 DDR2 Signal Termination

No terminations of any kind are required in order to meet signal integrity and overshoot requirements.

Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only

type permitted. Table 6-22 shows the specifications for the series terminators.

Table 6-22. DDR2 Signal Terminations

No. Parameter

Min

0

Typ

Max

10

Unit

Ω

Notes

See Note

See Notes

(1)

1

2

CLK Net Class

ADDR_CTRL Net Class

0

22

10

Zo

Ω

,

(2) (3)

,

(1)

3

4

Data Byte Net Classes (DQS0-DQS1, D0-D31)

SDRC_STRBENx Net Class (SDRC_STRBENx)

0

Zo

Ω

See Notes

(2) (3) (4)

,

(1)

See Notes

(2) (3)

,

(1) Only series termination is permitted, parallel or SST specifically disallowed.

(2) Terminator values larger than typical only recommended to address EMI issues.

(3) Termination value should be uniform across net class.

(4) When no termination is used on data lines (0 Ωs), the DDR2 devices must be programmed to operate in 60% strength mode.

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6.4.3.1.10 VREF Routing

VREF is used as a reference by the input buffers of the DDR2 memories as well as the AM3517/05. VREF

is intended to be ＝ the DDR2 power supply voltage and should be created using a resistive divider as

shown in Figure 6-18. Other methods of creating VREF are not recommended. Figure 6-22 shows the

layout guidelines for VREF.

VREF Bypass Capacitor

DDR2 Device

A1

VREF Nominal Minimum

AM3517/05

Device

Trace Width is 20 Mils

A1

Neck down to minimum in BGA escape

regions is acceptable. Narrowing to

accomodate via congestion for short

distances is also acceptable. Best

performance is obtained if the width

of VREF is maximized.

Figure 6-22. VREF Routing and Topology

6.4.3.1.11 DDR2 CLK and ADDR_CTRL Routing

Figure 6-23 shows the topology of the routing for the CLK and ADDR_CTRL net classes. The route is a

balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A

should be maximized.

A1

T

A

AM3517/05

A1

Figure 6-23. CLKand ADDR_CTRL Routing and Topology

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(1)

Table 6-23. CLKand ADDR_CTRL Routing Specification

No

1

Parameter

Min

Typ

Max

2w

25

Unit

Notes

Center to center DQS-DQSN spacing

CLKA to B/A to C Skew Length Mismatch

CLKB to C Skew Length Mismatch

(1)

2

Mils

See Note

3

25

(2)

(3)

4

Center to center CLKto other DDR2 trace spacing

CK/ADDR_CTRL nominal trace length

ADDR_CTRL to CLKSkew Length Mismatch

ADDR_CTRL to ADDR_CTRL Skew Length Mismatch

4w

See Note

5

CACLM-50

CACLM

CACLM+50

100

Mils

6

7

100

(2)

(1)

8

Center to center ADDR_CTRL to other DDR2 trace

spacing

4w

3w

See Note

9

Center to center ADDR_CTRL to other ADDR_CTRL

trace spacing

10

11

ADDR_CTRL A to B/A to C Skew Length Mismatch

ADDR_CTRL B to C Skew Length Mismatch

100

Mils

(1) Series terminator, if used, should be located closest to AM3517/05.

(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing

congestion.

(3) CACLM is the longest Manhattan distance of the CLKand ADDR_CTRL net classes.

Figure 6-24 shows the topology and routing for the DQS and Dx net classes; the routes are point to point.

Skew matching across bytes is not needed nor recommended.

T

E0

A1

T

E1

AM3517/05

T

E2

A1

T

E3

Figure 6-24. DQS and Dx Routing and Topology

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Table 6-24. DQS and Dx Routing Specification^{(1) (2)}

No. Parameter

Min

Typ

Max

2w

Unit

Mils

Notes

1

2

3

4

Center to center DQS-DQSN spacing

DQS E Skew Length Mismatch

25

(3)

(2)

Center to center DQS to other DDR2 trace spacing

DQS/Dx nominal trace length

4w

See Note

DQLM-50 DQLM DQLM+

50

See Notes

,

(4)

(3)

5

6

7

Dx to DQS Skew Length Mismatch

100

Mils

See Note

Dx to Dx Skew Length Mismatch

100

Center to center Dx to other DDR2 trace spacing

4w

See Notes

,

(5)

(6)

(4)

8

Center to Center Dx to other Dx trace spacing

3w

See Notes

,

(3)

9

Dx/DQS E Skew Length Mismatch

100

Mils

See Note

(1) "Dx" indicates a data line.

(2) Series terminator, if used, should be located closest to DDR.

(3) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing

congestion.

(4) There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte

1.

(5) Dx's from other DQS domains are considered other DDR2 trace.

(6) DQLM is the longest Manhattan distance of each of the DQS and Dx net classes.

Figure 6-25 shows the routing for the SDRC_STRBENx net classes. Table 6-25 contains the routing

specification.

A1

T

AM3517/05

A1

Figure 6-25. SDRC_STRBENx Routing

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Table 6-25. SDRC_STRBENx Routing Specification

No. Parameter

Min

Typ

Max

Unit

Notes

(1)

1

SDRC_STRBEN0 Length F

CKB0B1

CKB0B2

See Note

(2)

SDRC_STRBEN1 Length F

See Note

3

4

5

Center to center SDRC_STRBENx to any other trace spacing

DQS/Dx nominal trace length

4w

DQLM-50

DQLM

DQLM+50

100

Mils

(3)

SDRC_STRBENx Skew

Mils See Note

(1) CKB0B1 is the sum of the length of the CLK net plus the average length of the DQS0 and DQS1 nets.

(2) CKB0B2 is the sum of the length of the CLK net plus the average length of the DQS2 and DQS3 nets.

(3) Skew from CKB0B1 or CKB0B2.

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6.5 Video Interfaces

6.5.1 Video Processing Subsystem (VPSS)

The Video Processing Sub-System (VPSS) provides a Video Processing Front End (VPFE) input interface

for external imaging peripherals (i.e., image sensors, video decoders, etc.).

6.5.1.1 Video Processing Front End (VPFE)

The Video Processing Front-End (VPFE) controller receives input video/image data from external capture

devices and stores it to external memory which is transferred into the external memory via a built in DMA

engine. An internal buffer block provides a high bandwidth path between the VPSS module and the

external memory. The Cortex-A8 will process the image data based on application requirements.

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6.5.1.1.1 Video Processing Front End (VPFE) Timing

Table 6-26, , and Table 6-27 assume testing over recommended operating conditions (see Figure 6-26

through Figure 6-28).

Table 6-26. VPFE Timing Requirements

1.8-V, 3.3-V

NO.

PARAMETER

MIN

13.33

MAX

100

UNIT

ns

VF1 t_{c(VDIN_CLK)}

Cycle time, pixel clock input, VDIN_CLK

VF2 t_{su(VDIN_D-VDIN_CLK)}

VF3 t_{su(VDIN_HD-VDIN_CLK)}

VF4 t_{su(VDIN_VD-VDIN_CLK)}

Setup time, VDIN_D to VDIN_CLK rising edge

Setup time, VDIN_HD to VDIN_CLK rising edge

Setup time, VDIN_VD to VDIN_CLK rising edge

TBD

ns

VF5 t_{su(VDIN_WEN-VDIN_CLK)}Setup time, VDIN_WEN to VDIN_CLK rising edge

ns

VF6 t_{su(C_FLD-VDIN_CLK)}

VF7 t_{h(VDIN_CLK-VDIN_D)}

VF8 t_{h(VDIN-HD-VDIN_CLK)}

VF9 t_{h(VDIN_VD-VDIN_CLK)}

VF10 t_{h(VDIN_WEN-VDIN_CLK)}

VF11 t_{h(C_FLD-VDIN_CLK)}

Setup time, VDIN_FIELD to VDIN_CLK rising edge

Hold time, VDIN_D valid after VDIN_CLK rising edge

Hold time, VDIN_HD to VDIN_CLK rising edge

Hold time, VDIN_VD to VDIN_CLK rising edge

Hold time, VDIN_WEN to VDIN_CLK rising edge

Hold time, VDIN_FIELD to VDIN_CLK rising edge

ns

Table 6-27. VPFE Output Switching Characteristics

1.8-V, 3.3-V

MIN MAX

NO.

PARAMETER

UNIT

ns

VF12 t_{d(VDIN_HD-VDIN_CLK)}

VF13 t_{d(VDIN_VD-VDIN_CLK)}

VF14 t_{d(VDIN_WEN-VDIN_CLK)}

VF15 t_{oh(VDIN_HD-VDIN_CLK)}

VF16 t_{oh(VDIN_VD-VDIN_CLK)}

VF17 t_{oh(C_FLD-VDIN_CLK)}

Output delay time, VDIN_HD to CLK rising edge

Output delay time, VDIN_VD to CLK rising edge

Output delay time, VDIN_WEN to CLK rising edge

Output hold time, VDIN_HD to CLK rising edge

Output hold time, VDIN_VD to CLK rising edge

Output hold time, VDIN_FLD to CLK rising edge

TBD

ns

TBD

ns

VF1

VDIN_CLK

(Falling Edge)

VDIN_CLK

(Rising Edge)

VF7

VF2

VF7

VDIN_D[xx]

VF8, VF9, VF11

VF3, VF4, VF6

VF5

VDIN_HD,

VDIN_VD,

VDIN_FIELD

VF10

VDIN_WEN

SPRS550-001

Figure 6-26. VPFE0 Input Timings

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VDIN_CLK

(Falling Edge)

VDIN_CLK

(Rising Edge)

VF15, VF16,

VF17

VF15, VF16,

VF17

VF12,

VF13, VF14

VF12, VF13, VF14

VDIN_HD,

VDIN_VD,

VDIN_FIELD

SPRS550-002

Figure 6-27. VPFE Output Timings

VF18

VDIN_HD

(Falling Edge)

VDIN_HD

(Rising Edge)

VF20

VF19

VDIN_D[xx]

SPRS550-003

Figure 6-28. VPFE Input Timings With VDIN0_HD as Pixel Clock

6.5.2 Display Subsystem (DSS)

The display subsystem (DSS) provides the logic to display the video frame from external (SDRAM) or

internal (SRAM) memory on an LCD panel or a TV set. The DSS integrates a display controller. It can be

used in two configurations:

•

LCD display support in:

–

Bypass mode (RFBI module bypassed)

RFBI mode (through RFBI module)

•

TV display support (not discussed in this document because of its analog IO signals)

The two display supports can be active at the same time.

6.5.2.1 LCD Display Support in Bypass Mode

Two types of LCD panel are supported:

•

Thin film transistor (TFT) or active matrix technology

Supertwisted nematic (STN) or passive matrix technology

Both configurations are discussed in the following paragraphs.

6.5.2.1.1 LCD Display in TFT Mode

Table 6-28 assumes testing over the recommended operating conditions (see Figure 6-29).

Table 6-28. LCD Display Interface Switching Characteristics in TFT Mode⁽¹⁾

NO.

PARAMETER

1.8V, 3.3V

MIN

UNIT

MAX

TBD

DL0

DL1

DL2

DL3

t_{d(PCLKA-HSYNCT)}

t_{d(PCLKA-VSYNCT)}

t_{d(PCLKA-ACBIASA)}

t_{d(PCLKA-DATAV)}

Delay time, dss_pclk active edge to dss_hsync transition

Delay time, dss_pclk active edge to dss_vsync transition

Delay time, dss_pclk active edge to dss_acbias active level

Delay time, dss_pclk active edge to dss_data bus valid

TBD

ns

(1) The capacitive load is equivalent to 25 pF.

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Table 6-28. LCD Display Interface Switching Characteristics in TFT Mode (continued)

NO.

PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

DL4

DL5

t_c(PCLK)

t_w(PCLK)

c_load

Cycle time⁽²⁾, dss_pclk

TBD

ns

pF

Pulse duration, dss_pclk low or high

Load capacitance

TBD

(2) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the

DISPC_DIVISOR register.

DL5

DL4

dss_pclk

DL1

dss_vsync

DL0

dss_hsync

DL2

dss_acbias

DL3

dss_data[23:0]

030-061

Figure 6-29. LCD Display in TFT ModeStep 1Step 2Step 3

(1) The pixel data bus depends on the use of 8-, 9-, 12-, 16-, 18-, or 24-bit per pixel data output pins.

(2) The pixel clock frequency is programmable.

(3) All timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk.

6.5.2.1.2 LCD Display in STN Mode

Table 6-29 assumes testing over the recommended operating conditions (see Figure 6-30).

Table 6-29. LCD Display Interface Switching Characteristics in STN Mode⁽¹⁾⁽²⁾

NO.

PARAMETER

1.8V, 3.3V

MAX

UNIT

MIN

TBD

DL3

DL4

DL5

t_{d(PCLKA-DATAV)}

t_c(PCLK)

Delay time, dss_pclk active edge to dss_data bus valid

Cycle time⁽³⁾, dss_pclk

TBD

ns

pF

t_w(PCLK)

Pulse duration, dss_pclk low or high

Load capacitance

TBD

c_load

(1) The DSS in STN mode is used with 4 or 8 pins only; unused pixel data bits always remain low.

(2) The capacitive load is equivalent to 40 pF.

(3) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the

DISPC_DIVISOR register.

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DL5

DL4

dss_pclk

dss_vsync

dss_hsync

dss_acbias

DL3

dss_data[23:0]

030-062

Figure 6-30. LCD Display in STN Mode^(1)(2)(3)(4)

(1) The pixel data bus depends on the use 4-, 8-, 12-, 16-, 18-, or 24-bit per pixel data output pins.

(2) All timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk.

(3) dss_vsync width must be programmed to be as small as possible.

(4) The pixel clock frequency is programmable.

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6.6 Serial Communications Interfaces

6.6.1 Multichannel Buffered Serial Port (McBSP) Timing

There are five McBSP modules called McBSP1 through McBSP5. McBSP provides a full-duplex, direct

serial interface between the AM3517/05 device and other devices in a system such as other application

devices or codecs. It can accommodate a wide range of peripherals and clocked frame-oriented protocols

(I2S, PCM, and TDM) due to its high level of versatility.

The McBSP1-5 modules may support two types of data transfer at the system level:

•

The full-cycle mode, for which one clock period is used to transfer the data, generated on one edge

and captured on the same edge (one clock period later).

•

The half-cycle mode, for which one half clock period is used to transfer the data, generated on one

edge and captured on the opposite edge (one half clock period later). Note that a new data is

generated only every clock period, which secures the required hold time.

The interface clock (CLKX/CLKR) activation edge (data/frame sync capture and generation) has to be

configured accordingly with the external peripheral (activation edge capability) and the type of data

transfer required at the system level.

The AM3517/05 McBSP1-5 timing characteristics are described for both rising and falling activation edges.

McBSP1 supports:

•

6-pin mode: dx and dr as data pins; clkx, clkr, fsx, and fsr as control pins.

4-pin mode: dx and dr as data pins; clkx and fsx pins as control pins. The clkx and fsx pins are

internally looped back via software configuration, respectively, to the clkr and fsr internal signals for

data receive.

McBSP2, 3, 4, and 5 support only the 4-pin mode.

The following sections describe the timing characteristics for applications in normal mode (that is,

AM3517/05 McBSPx connected to one peripheral) and TDM applications in multipoint mode.

6.6.1.1 McBSP in Normal Mode

Table 6-30. McBSP Timing Conditions (Normal Mode)

TIMING CONDITION PARAMETER

Input Conditions

1.8V, 3.3 V

UNIT

MIN

TBD

MAX

TBD

t_R

Input signal rise time

Input signal fall time

ns

t_F

Output Conditions

C_LOAD

Output load

capacitance

TBD

pF

Table 6-31. McBSP Output Clock Pulse Duration

NO.

PARAMETER

1.8 V

3.3 V

UNIT

MIN

MAX

MIN

MAX

t_W(CLKH)

t_W(CLKL)

t_dc(CLK)

Typical pulse duration, mcbsp1_clkr / mcbspx_clkx

high⁽¹⁾

TBD

ns

Typical pulse duration, mcbsp1_clkr / mcbspx_clkx

low⁽¹⁾

Duty cycle error, mcbsp1_clkr / mcbspx_clkx⁽¹⁾

TBD

(1) In mcbspx, x identifies the McBSP number: 1, 2, 3, 4, or 5.

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6.6.1.1.1 Receive Timing with Rising Edge as Activation Edge

Table 6-32 through Table 6-37 assume testing over the recommended operating conditions (see

Figure 6-31 through Figure 6-32).

Table 6-32. McBSP1, 2, and 3 (Sets #1 and #2) Timing Requirements Rising Edge and Receive Mode⁽¹⁾

NO.

PARAMETER

1.8V

MIN MAX

3.3V

MIN MAX

TBD

UNIT

B3

t_{su(DRV-CLKAE)}

Setup time, mcbspx_dr valid before mcbsp1_clkr /

mcbspx_clkx active edge

Master

Slave

TBD

ns

TBD

B4

t_h(CLKAE-DRV)

Hold time, mcbspx_dr valid after mcbsp1_clkr /

mcbspx_clkx active edge

Master

Slave

B5

B6

t_{su(FSV-CLKAE)}

t_h(CLKAE-FSV)

Setup time, mcbsp1_fsr / mcbspx_fsx valid before mcbsp1_clkr /

mcbspx_clkx active edge

Hold time, mcbsp1_fsr / mcbspx_fsx valid after mcbsp1_clkr /

mcbspx_clkx active edge

TBD

ns

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

Table 6-33. McBSP1, 2, and 3 (Sets #1 and #2) Switching Characteristics Rising Edge and Receive

Mode⁽¹⁾

NO.

PARAMETER

1.8V

3.3V

UNIT

MIN

TBD

MAX

MIN

TBD

MAX

B2

t_d(CLKAE-FSV)

Delay time, mcbsp1_clkr / mcbspx_clkx active edge to mcbsp1_fsr /

mcbspx_fsx valid

TBD

ns

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

Table 6-34. McBSP4 (Set #3) Timing Requirements Rising Edge and Receive Mode⁽¹⁾

NO.

B3

PARAMETER

1.8 V

MIN MAX

3.3 V

MIN MAX

UNIT

t_{su(DRV-CLKXAE)}

Setup time, mcbspx_dr valid before

mcbspx_clkx active edge

Master

Slave

TBD

ns

B4

t_{h(CLKXAE-DRV)}

Hold time, mcbspx_dr valid after mcbspx_clkx

active edge

Master

Slave

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time mcbspx_fsx valid before mcbspx_clkx active edge

Hold Time mcbspx_fsx valid after mcbspx_clkx active edge

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-36 and Table 6-37

Table 6-35. McBSP4 (Set #3) Switching Characteristics Rising Edge and Receive Mode⁽¹⁾

NO.

PARAMETER

1.8 V

MIN

TBD

3.3 V

UNIT

MAX

MIN MAX

TBD TBD

B2

t_{d(CLKXAE-FSXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx valid

TBD

ns

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-36 and Table 6-37

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Table 6-36. McBSP3 (Set #3), 4 (Set #1), and 5 Timing Requirements Rising Edge and Receive Mode⁽¹⁾

NO.

PARAMETER

1.8 V

3.3 V

MIN MAX

UNIT

MIN

TBD

MAX

B3

t_{su(DRV-CLKXAE)}

Setup time, mcbspx_dr valid before

mcbspx_clkx active edge

Master

Slave

TBD

ns

B4

t_{h(CLKXAE-DRV)}

Hold time, mcbspx_dr valid after mcbspx_clkx Master

active edge

Slave

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time, mcbspx_fsx valid before mcbspx_clkx active edge

Hold time, mcbspx_fsx valid after mcbspx_clkx active edge

(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode

by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are

specified in Table 6-34 and Table 6-35.

For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).

Table 6-37. McBSP3 (Set #3), 4 (Set #1), and 5 Switching Requirements Rising Edge and Receive Mode⁽¹⁾

NO.

PARAMETER

1.8 V

3.3 V

MAX

TBD

UNIT

MIN

MAX

MIN

B2

t_{d(CLKXAE-FSXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx valid

TBD

ns

mcbspx_clkr

B2

mcbspx_fsr

mcbspx_dr

B3

B4

D7

D6

D5

030-068

Figure 6-31. McBSP Rising Edge Receive Timing in Master Mode

mcbspx_clkr

mcbspx_fsr

mcbspx_dr

B5

B6

B3

B4

D7

D6

D5

030-069

Figure 6-32. McBSP Rising Edge Receive Timing in Slave Mode

(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode

by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are

specified in Table 6-34 and Table 6-35.

For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).

6.6.1.1.2 Transmit Timing with Rising Edge as Activation Edge

Table 6-38 through Table 6-43 assume testing over the recommended operating conditions (see

Figure 6-33 and Figure 6-34).

Table 6-38. McBSP1, 2, and 3 (Sets #1 and #2) Timing Requirements Rising Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.8V

3.3V

UNIT

MIN

MAX

MIN

MAX

B5

t_{su(FSXV-CLKXAE)}

Setup time, mcbspx_fsx valid before mcbspx_clkx active

edge

TBD

ns

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

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Table 6-38. McBSP1, 2, and 3 (Sets #1 and #2) Timing Requirements Rising Edge and Transmit Mode

(continued)

NO.

PARAMETER

1.8V

3.3V

UNIT

MIN

MAX

MIN

MAX

B6

t_{h(CLKXAE-FSXV)}

Hold time, mcbspx_fsx valid after mcbspx_clkx active

edge

TBD

ns

Table 6-39. McBSP1, 2, and 3 (Sets #1 and #2) Switching Characteristics Rising Edge and Transmit

Mode⁽¹⁾

NO.

PARAMETER

1.8V

MIN

3.3V

MIN

UNIT

MAX

TBD

MAX

TBD

B2

B8

t_{d(CLKXAE-FSXV)}

t_{d(CLKXAE-DXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx valid

TBD

ns

Delay time, mcbspx_clkx active edge to

mcbspx_dx valid

Master

Slave

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

Table 6-40. McBSP4 (Set #3) Timing Requirements Rising Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.8V

3.3V

UNIT

MIN

MAX

MIN

MAX

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time, mcbspx_fsx valid before mcbspx_clkx

active edge

TBD

ns

Hold time, mcbspx_fsx valid after mcbspx_clkx active

edge

TBD

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-42.

Table 6-41. McBSP4 (Set #3) Switching Characteristics Rising Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.8V

3.3V

UNIT

MIN

MAX

MIN

MAX

B2

B8

t_{d(CLKXAE-FSXV)}

t_{d(CLKXAE-DXV)}

Delay time, mcbspx_clkx active edge to

mcbspx_fsx valid

TBD

ns

Delay time, mcbspx_clkx active edge

to mcbspx_dx valid

Master

Slave

TBD

ns

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-42.

Table 6-42. McBSP3 (Set #3), 4 (Set #1), and 5 Timing Requirements Rising Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.8V

3.3V

UNIT

MIN

MAX

MIN

MAX

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time, mcbspx_fsx valid before mcbspx_clkx

active edge

TBD

ns

Hold time, mcbspx_fsx valid after mcbspx_clkx active

edge

TBD

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-42.

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Table 6-43. McBSP 3 (Set #3), 4 (Set #1), and 5 Switching Requirements Rising Edge and Transmit

Mode⁽¹⁾

NO.

PARAMETER

1.8V

3.3V

UNIT

MIN

MAX

MIN

MAX

B2

B8

t_{d(CLKXAE-FSXV)}

t_{d(CLKXAE-DXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx

valid

TBD

ns

Delay time, mcbspx_clkx active edge to Master

TBD

ns

mcbspx_dx valid

Slave

mcbspx_clkx

B2

B8

mcbspx_fsx

mcbspx_dx

D7

D6

D5

030-070

Figure 6-33. McBSP Rising Edge Transmit Timing in Master Mode

mcbspx_clkx

mcbspx_fsx

mcbspx_dx

B5

B6

B8

D7

D6

D5

030-071

Figure 6-34. McBSP Rising Edge Transmit Timing in Slave Mode

(1) In mcbspx, x identifies the McBSP number: 3, 4 or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode

by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are

specified in the table above. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).

6.6.1.1.3 Receive Timing with Falling Edge as Activation Edge

Table 6-44 through Table 6-49 assume testing over the recommended operating conditions (see

Figure 6-35 and Figure 6-36).

Table 6-44. McBSP1, 2, and 3 (Sets #1 and #2) Timing Requirements Falling Edge and Receive Mode⁽¹⁾

NO.

PARAMETER

1.8V

3.3V

UNIT

MIN

TBD

MAX

MIN

TBD

MAX

B3

t_{su(DRV-CLKAE)}

Setup time, mcbspx_dr valid before

mcbsp1_clkr / mcbspx_clkx active edge

Master

Slave

ns

B4

t_h(CLKAE-DRV)

Hold time, mcbspx_dr valid after

mcbsp1_clkr / mcbspx_clkx active edge

Master

Slave

B5

B6

t_{su(FSV-CLKAE)}

t_h(CLKAE-FSV)

Setup time, mcbsp1_fsr / mcbspx_fsx valid before

mcbsp1_clkr /mcbspx_clkx active edge

Hold time, mcbsp1_fsr / mcbspx_fsx valid after

mcbsp1_clkr /mcbspx_clkx active edge

TBD

ns

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

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Table 6-45. McBSP1, 2, and 3 (Sets #1 and #2) Switching Characteristics Falling Edge and Receive

Mode⁽¹⁾

NO.

PARAMETER

1.8 V

3.3 V

UNIT

MIN

MAX

MIN

MAX

B2

t_d(CLKAE-FSV)

Delay time, mcbsp1_clkr / mcbspx_clkx active edge to

mcbsp1_fsr / mcbspx_fsx valid

TBD

ns

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

Table 6-46. McBSP4 (Set #3) Timing Requirements Falling Edge and Receive Mode⁽¹⁾

NO.

B3

PARAMETER

1.8 V

3.3 V

UNIT

MIN

TBD

MAX

MIN

TBD

MAX

t_{su(DRV-CLKXAE)}

Setup time, mcbspx_dr valid before

mcbspx_clkx active edge

Master

Slave

ns

B4

t_{h(CLKXAE-DRV)}

Hold time, mcbspx_dr valid after

mcbspx_clkx active edge

Master

Slave

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time mcbspx_fsx valid before mcbspx_clkx active

edge

Hold time mcbspx_fsx valid after mcbspx_clkx active

edge

TBD

ns

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-48

Table 6-47. McBSP4 (Set #3) Switching Characteristics Falling Edge and Receive Mode⁽¹⁾

NO.

PARAMETER

1.8 V

3.3 V

UNIT

MIN

MAX

MIN

MAX

B2

t_{d(CLKXAE-FSXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx valid

TBD

ns

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-48

Table 6-48. McBSP3 (Set #3), 4 (Set #1), and 5 Timing Requirements Falling Edge and Receive Mode⁽¹⁾

NO.

PARAMETER

1.8 V

3.3 V

UNIT

MIN

TBD

MAX

MIN

TBD

MAX

B3

t_{su(DRV-CLKXAE)}

Setup time, mcbspx_dr valid before

mcbspx_clkx active edge

Master

Slave

ns

B4

t_{h(CLKXAE-DRV)}

Hold time, mcbspx_dr valid after mcbspx_clkx Master

active edge

Slave

B5

B6

t_{su(FSXV-CLKXAE)}Setup time, mcbspx_fsx valid before mcbspx_clkx active

edge

t_{h(CLKXAE-FSXV)}

Hold time, mcbspx_fsx valid after mcbspx_clkx active

edge

TBD

ns

(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode

by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are

specified in the table above. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).

Table 6-49. McBSP3 (Set #3), 4 (Set #1), and 5 Switching Requirements Falling Edge and Receive Mode⁽¹⁾

NO.

PARAMETER

1.8 V

3.3 V

UNIT

MIN

MAX

MIN

MAX

B2

t_{d(CLKXAE-FSXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx

valid

TBD

ns

(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode

by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are

specified in the table above. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).

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mcbspx_clkr

mcbspx_fsr

mcbspx_dr

B2

B3

B4

D7

D6

D5

030-072

Figure 6-35. McBSP Falling Edge Receive Timing in Master Mode

mcbspx_clkr

mcbspx_fsr

mcbspx_dr

B5

B6

B3

B4

D7

D6

D5

030-073

Figure 6-36. McBSP Falling Edge Receive Timing in Slave Mode

6.6.1.1.4 Transmit Timing with Falling Edge as Activation Edge

Table 6-50 through Table 6-55 assume testing over the recommended operating conditions (see

Figure 6-37 and Figure 6-38).

Table 6-50. McBSP1, 2, and 3 (Sets #1 and #2) Timing Requirements Falling Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.8 V

3.3 V

UNIT

MIN

MAX

MIN

MAX

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time, mcbspx_fsx valid before mcbspx_clkx

active edge

TBD

ns

Hold time, mcbspx_fsx valid after mcbspx_clkx

active edge

TBD

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

Table 6-51. McBSP1, 2, and 3 (Sets #1 and #2) Switching Characteristics Falling Edge and Transmit

Mode⁽¹⁾

NO.

PARAMETER

1.8 V

3.3 V

UNIT

MIN

MAX

MIN

MAX

B2

B8

t_{d(CLKXAE-FSXV)}

t_{d(CLKXAE-DXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx

valid

TBD

ns

Delay time, mcbspx_clkx active edge to Master

TBD

ns

mcbspx_dx valid

Slave

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

Table 6-52. McBSP4 (Set #3) Timing Requirements Falling Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.8 V

3.3 V

UNIT

MIN

MAX

MIN

MAX

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time, mcbspx_fsx valid before

mcbspx_clkx active edge

TBD

ns

Hold time, mcbspx_fsx valid after mcbspx_clkx

active edge

TBD

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-54.

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Table 6-53. McBSP4 (Set #3) Switching Characteristics Falling Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.8 V

3.3 V

UNIT

MIN

MAX

MIN

MAX

B2

B8

t_{d(CLKXAE-FSXV)}

t_{d(CLKXAE-DXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx

valid

TBD

ns

Delay time, mcbspx_clkx active edge to

mcbspx_dx valid

Master

Slave

TBD

0.6

TBD

17.3

TBD

0.6

TBD

33.1

ns

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-54.

Table 6-54. McBSP3 (Set #3), 4 (Set #1), and 5 Timing Requirements Falling Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.8 V

3.3 V

UNIT

MIN

MAX

MIN

MAX

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time, mcbspx_fsx valid before mcbspx_clkx

active edge

5.8

12.2

ns

Hold time, mcbspx_fsx valid after mcbspx_clkx

active edge

0.5

(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode

by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are

specified in Table 6-54. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).

Table 6-55. McBSP3 (Set #3), 4 (Set #1), and 5 Switching Requirements Falling Edge and Transmit

Mode⁽¹⁾

NO.

PARAMETER

1.8 V

MAX

3.3 V

MAX

UNIT

MIN

TBD

MIN

TBD

B2

B8

t_{d(CLKXAE-FSXV)}

t_{d(CLKXAE-DXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx valid

TBD

ns

Delay time, mcbspx_clkx active edge to

mcbspx_dx valid

Master

Slave

(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode

by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are

specified in Table 6-54. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).

mcbspx_clkx

B2

mcbspx_fsx

mcbspx_dx

B8

D7

D6

D5

030-074

Figure 6-37. McBSP Falling Edge Transmit Timing in Master Mode

mcbspx_clkx

mcbspx_fsx

mcbspx_dx

B5

B6

B8

D7

D6

D5

030-075

Figure 6-38. McBSP Falling Edge Transmit Timing in Slave Mode

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6.6.1.2 McBSP in TDMMultipoint Mode (McBSP3)

For TDM application in multipoint mode, AM3517/05 is considered as a slave. Table 6-57 and Table 6-58

assume testing over the operating conditions and electrical characteristic conditions described below.

Table 6-56. McBSP3 Timing ConditionsTDM in Multipoint Mode

TIMING CONDITION PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

Input Conditions

t_R

t_F

Input signal rising time

Input signal falling time

TBD

ns

Output Conditions

C_LOADOutput Load Capacitance

TBD

pF

Table 6-57. McBSP3 Timing RequirementsTDM in Multipoint Mode⁽¹⁾

NO.

PARAMETER

1.8 V

3.3 V

UNIT

MIN

MAX

MIN

MAX

t_W(CLKH)

Cycle Time, mcbsp3_clkx

TBD

ns

t_W(CLKH)

Typical Pulse duration, mcbsp3_clkx high

Typical Pulse duration, mcbsp3_clkx low

Duty cycle error, mcbsp3_clkx

TBD

t_W(CLKL)

t_dc(CLK)

TBD

B3⁽²⁾

B4⁽²⁾

B5⁽²⁾

B6⁽²⁾

t_{su(DRV-CLKAE)}

Setup time, mcbsp3_dr valid before

mcbsp3_clkx active edge

t_h(CLKAE-DRV)

t_{su(FSV-CLKAE)}

t_h(CLKAE-FSV)

Hold time, mcbsp3_dr valid after mcbsp3_clkx

active edge

TBD

ns

Setup time, mcbsp3_fsx valid before

mcbsp3_clkx active edge

Hold time, mcbsp3_fsx valid after

mcbsp3_clkx active edge

(1) For McBSP3, these timings concern only Set #3 (multiplexing mode in McBSP1 pins).

(2) See Section 6.6.1.1, McBSP in Normal Mode for corresponding figures.

Table 6-58. McBSP3 Switching CharacteristicsTDM in Multipoint Mode⁽¹⁾

NO.

B8⁽²⁾

PARAMETER

1.8 V

3.3 V

UNIT

MIN

MAX

MIN

MAX

t_{d(CLKXAE-DXV)}Delay time, mcbsp3_clkx active edge to

mcbsp3_dx valid

TBD

ns

(1) For McBSP3, these timings concern only Set #3 (multiplexing mode in McBSP1 pins).

(2) See Section 6.6.1.1, McBSP in Normal Mode for corresponding figures.

6.6.2 Multichannel Serial Port Interface (McSPI) Timing

The multichannel SPI is a master/slave synchronous serial bus. The McSPI1 module supports up to four

peripherals and the others (McSPI2, McSPI3, and McSPI4) support up to two peripherals. The following

timings are applicable to the different configurations of McSPI in master/slave mode for any McSPI and

any channel (n).

6.6.2.1 McSPI in Slave Mode

Table 6-59 and Table 6-60 assume testing over the recommended operating conditions (see Figure 6-39).

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Table 6-59. McSPI Interface Timing Requirements – Slave Mode⁽¹⁾⁽²⁾

NO.

PARAMETER

1.8 V

3.3 V

UNIT

MIN

TBD

MAX

MIN

TBD

MAX

SS0 t_c(CLK)

Cycle time, mcspix_clk

ns

SS1 t_w(CLK)

Pulse duration, mcspix_clk high or low

SS2 t_{su(SIMOV-CLKAE)}

Setup time, mcspix_simo valid before mcspix_clk

active edge

SS3 t_{h(SIMOV-CLKAE)}

SS4 t_{su(CS0V-CLKFE)}

SS5 t_{h(CS0I-CLKLE)}

Hold time, mcspix_simo valid after mcspix_clk active

edge

TBD

ns

Setup time, mcspix_cs0 valid before mcspix_clk first

edge

Hold time, mcspix_cs0 invalid after mcspix_clk last

edge

(1) The input timing requirements are given by considering a rise time and a fall time of 4 ns.

(2) In mcspix, x is equal to 1, 2, 3, or 4.

Table 6-60. McSPI Interface Switching Requirements^(1)(2)(3)(4)

NO.

PARAMETER

1.8 V

3.3 V

UNIT

MIN

MAX

MIN

MAX

SS6 t_{d(CLKAE-SOMIV)}

SS7 t_{d(CS0AE-SOMIV)}

Delay time, mcspix_clk active edge to mcspix_somi

shifted

TBD

ns

Delay time, mcspix_cs0 active edge to Modes 0 and 2

mcspix_somi shifted

TBD

(1) The capacitive load is equivalent to 20 pF.

(2) In mcspix, x is equal to 1, 2, 3, or 4.

(3) The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all

software configurable.

(4) This timing applies to all configurations regardless of mcspix_clk polarity and which clock edges are used to drive output data and

capture input data.

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Mode 0 & 2

mcspix_cs0(EPOL=1)

SS0

SS1

SS4

SS5

mcspix_clk(POL=0)

mcspix_clk(POL=1)

SS0

SS1

SS2

SS3

Bit n-1

SS7

Bit n-1

mcspix_simo

mcspix_somi

Bit n-2

SS6

Bit n-3

Bit n-4

Bit 0

Bit n-2

Bit n-3

Bit 0

Mode 1 & 3

mcspix_cs0(EPOL=1)

SS0

SS1

mcspix_clk(POL=0)

mcspix_clk(POL=1)

SS0

SS1

SS4

SS5

SS3

SS2

Bit n-1

SS6

Bit n-1

mcspix_simo

mcspix_somi

Bit n-2

Bit n-3

Bit 1

Bit 0

Bit n-3

Bit 1

030-076

Figure 6-39. McSPI Interface Transmit and Receive in Slave Mode⁽¹⁾⁽²⁾

(1) The active clock edge (rising or falling) on which mcspi_somi is driven and mcspi_simo data is latched is software configurable with the

bit MSPI_CHCONFx[0] = PHA and the bit MSPI_CHCONFx[1] = POL.

(2) The polarity of mcspix_csi is software configurable with the bit MSPI_CHCONFx[6] = EPOL In mcspix, x is equal to 1, 2, 3, or 4.

6.6.2.2 McSPI in Master Mode

Table 6-61 and Table 6-62 assume testing over the recommended operating conditions (see Figure 6-40).

Table 6-61. McSPI1, 2, and 4 Interface Timing Requirements – Master Mode⁽¹⁾⁽²⁾

NO.

PARAMETER

1.8 V

3.3 V

UNIT

MIN

MAX

MIN

MAX

SM2 t_{su(SOMIV-CLKAE)}

SM3 t_{h(SOMIV-CLKAE)}

Setup time, mcspix_somi valid before mcspix_clk

active edge

TBD

ns

Hold time, mcspix_somi valid after mcspix_clk active

edge

TBD

(1) The input timing requirements are given by considering a rise time and a fall time of 4 ns.

(2) In mcspix, x is equal to 1, 2, 3, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 3.

n is equal to 0 for x equal to 4.

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Table 6-62. McSPI1, 2, and 4 Interface Switching Characteristics – Master Mode^(1)(2)(3)

NO.

PARAMETER

1.8 V

3.3 V

UNIT

MIN

TBD

MAX

MIN

TBD

MAX

SM0

SM1

SM4

t_c(CLK)

Cycle time, mcspix_clk

ns

t_w(CLK)

Pulse duration, mcspix_clk high or low

TBD

t_{d(CLKAE-SIMOV)}

Delay time, mcspix_clk active edge to mcspix_simo

shifted

TBD

SM5

SM6

SM7

t_{d(CSnA-CLKFE)}

t_{d(CLKLE-CSnI)}

t_{d(CSnAE-SIMOV)}

Delay time, mcspix_csi active to

mcspix_clk first edge

Modes 1

and 3

TBD

ns

Modes 0

and 2

Delay time, mcspix_clk last edge to

mcspix_csi inactive

Modes 1

and 3

Modes 0

and 2

Delay time, mcspix_csi active edge to Modes 0

mcspix_simo shifted and 2

TBD

(1) Timings are given for a maximum load capacitance of 20 pF for spix_csn signals, 30 pF for spix_clk and spix_simo signals with x = 1 or

2, and 20 pF for spi4_clk and spi4_simo signals.

(2) In mcspix, x is equal to 1, 2, 3, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 3.

n is equal to 0 for x equal to 4.

(3) The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all

software configurable.

Table 6-63 and Table 6-64 assume testing over the recommended operating conditions (see Figure 6-40).

Table 6-63. McSPI 3 Interface Timing Requirements – Master Mode⁽¹⁾⁽²⁾

NO.

PARAMETER

1.8 V

3.3 V

UNIT

MIN

MAX

MIN

MAX

SM2 t_{su(SOMIV-CLKAE)}

SM3 t_{h(SOMIV-CLKAE)}

Setup time, mcspi3_somi valid before

mcspi3_clk active edge

TBD

ns

Hold time, mcspi3_somi valid after mcspi3_clk

active edge

TB

TBD

(1) The input timing requirements are given by considering a rise time and a fall time of 4 ns.

(2) In mcspi3_csn, n is equal to 0 or 1. The polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and

mcspi3_somi is latched is all software configurable.

Table 6-64. McSPI3 Interface Switching Requirements – Master Mode^(1)(2)(3)

NO.

PARAMETER

1.8 V

3.3 V

UNIT

MIN

TBD

MAX

MIN

TBD

MAX

SM0 t_c(CLK)

Cycle time, mcspix_clk

ns

SM1 t_w(CLK)

Pulse duration, mcspix_clk high or low

TBD

SM4 t_{d(CLKAE-SIMOV)}

Delay time, mcspix_clk active edge to

mcspix_simo shifted

SM5 t_{d(CSnA-CLKFE)}

Delay time, mcspix_csi active Modes 1

TBD

ns

to mcspix_clk first edge

and 3

Modes 0

and 2

(1) The capacitive load is equivalent to 20 pF.

(2) In mcspi3_csn, n is equal to 0 or 1. The polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and

mcspi3_somi is latched is all software configurable.

(3) This timing applies to all configurations regardless of McSPI3_CLK polarity and which clock edges are used to drive output data and

capture input data.

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Table 6-64. McSPI3 Interface Switching Requirements – Master Mode (continued)

NO.

PARAMETER

1.8 V

3.3 V

UNIT

MIN

MAX

MIN

MAX

SM6 t_{d(CLKLE-CSnI)}

Delay time, mcspix_clk last

edge to mcspix_csi inactive

Modes 1

and 3

TBD

ns

Modes 0

and 2

TBD

SM7 t_{d(CSnAE-SIMOV)}

Delay time, mcspix_csi active Modes 0

edge to mcspix_simo shifted and 2

TBD

TBDD

Mode 0 & 2

mcspix_csn(EPOL=1)

mcspix_clk(POL=0)

mcspix_clk(POL=1)

mcspix_simo

SM0

SM5

SM1

SM6

SM0

SM1

SM7

Bit n-1

SM2

SM3

Bit n-1

SM4

Bit n-2

Bit n-3

Bit n-4

Bit 0

mcspix_somi

Bit n-2

Bit n-3

Bit 0

Mode 1 & 3

mcspix_csn(EPOL=1)

mcspix_clk(POL=0)

SM0

SM1

SM0

SM1

SM5

SM6

mcspix_clk(POL=1)

mcspix_simo

SM4

Bit n-1

SM2

Bit n-2

Bit n-3

Bit 1

Bit 0

SM3

mcspix_somi

Bit n-1

Bit n-3

Bit 1

030-077

Figure 6-40. McSPI Interface Transmit and Receive in Master Mode^(1)(2)(3)

(1) The active clock edge (rising or falling) on which mcspix_simo is driven and mcspi_somi data is latched is software configurable with the

bit MSPI_CHCONFx[0] = PHA and the bit MSPI_CHCONFx[1] = POL.

(2) The polarity of mcspix_csi is software configurable with the bit MSPI_CHCONFx[6] = EPOL.

(3) In mcspix, x is equal to 1. In mcspix_csn, n is equal to 0, 1, 2, or 3.

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6.6.3 Multiport Full-Speed Universal Serial Bus (USB) Interface

The AM3517/05 processor provides three USB ports working in full- and low-speed data transactions (up

to 12Mbit/s).

Connected to either a serial link controller (TLL modes) or a serial PHY (PHY interface modes) it supports:

•

6-pin (Tx: Dat/Se0 or Tx: Dp/Dm) unidirectional mode

4-pin bidirectional mode

3-pin bidirectional mode

6.6.3.1 Multiport Full-Speed Universal Serial Bus (USB) – Unidirectional Standard 6-pin Mode

Table 6-66 and Table 6-67 assume testing over the recommended operating conditions (see Figure 6-41).

Table 6-65. Low-/Full-Speed USB Timing Conditions Unidirectional Standard 6-pin Mode

TIMING CONDITION PARAMETER

Input Conditions

1.8V, 3.3V

UNIT

t_R

Input signal rise time

Input signal fall time

2.0

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

15.0

pF

Table 6-66. Low-/Full-Speed USB Timing Requirements Unidirectional Standard 6-pin Mode

NO.

PARAMETER

1.8V, 3.3V

MIN MAX

UNIT

FSU1

FSU2

FSU3

t_d(Vp,Vm)

t_d(RCVU0)

Time duration, mmx_rxdp and mmx_rxdm low together during transition

Time duration, mmx_rxdp and mmx_rxdm high together during transition

14.0

8.0

ns

Time duration, mmx_rrxcv undefine during a single end 0 (mmx_rxdp and

mmx_rxdm low together)

14.0

FSU4

t_d(RCVU1)

Time duration, mmx_rxrcv undefine during a single end 1 (mmx_rxdp and

mmx_rxdm high together)

8.0

ns

Table 6-67. Low-/Full-Speed USB Switching Characteristics Unidirectional Standard 6-pin Mode

NO.

PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

84.8

1.5

FSU5

FSU6

FSU7

FSU8

FSU9

t_{d(TXENL-DATV)}

t_{d(TXENL-SE0V)}

t_s(DAT-SE0)

t_{d(DATI-TXENH)}

t_{d(SE0I-TXENH)}

t_R(do)

Delay time, mmx_txen_n low to mmx_txdat valid

Delay time, mmx_txen_n low to mmx_txse0 valid

Skew between mmx_txdat and mmx_txse0 transition

Delay time, mmx_txdat invalid to mmx_txen_n high

Delay time, mmx_txse0 invalid to mmx_txen_n high

Rise time, mmx_txen_n

81.8

ns

81.8

4.0

t_F(do)

Fall time, mmx_txen_n

t_R(do)

Rise time, mmx_txdat

t_F(do)

Fall time, mmx_txdat

t_R(do)

Rise time, mmx_txse0

t_F(do)

Fall time, mmx_txse0

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Transmit

mmx_txen_n

mmx_txdat

mmx_txse0

mmx_rxdp

mmx_rxdm

mmx_rxrcv

Receive

FSU5

FSU6

FSU8

FSU9

FSU7

FSU1

FSU2

FSU4

FSU1

FSU3

030-080

In mmx, x is equal to 0, 1, or 2.

Figure 6-41. Low-/Full-Speed USB Unidirectional Standard 6-pin Mode

6.6.3.2 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional Standard 4-pin Mode

Table 6-69 and Table 6-70 assume testing over the recommended operating conditions (see Figure 6-42).

Table 6-68. Low-/Full-Speed USB Timing Conditions Bidirectional Standard 4-pin Mode

TIMING CONDITION PARAMETER

1.8V, 3.3V

UNIT

Input Conditions

t_R

Input signal rise time

Input signal fall time

2.0

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

15.0

pF

Table 6-69. Low-/Full-Speed USB Timing Requirements Bidirectional Standard 4-pin Mode

NO.

PARAMETER

1.8V, 3.3V

MIN MAX

UNIT

FSU10

FSU11

FSU12

FSU13

t_d(DAT,SE0)

t_d(RCVU0)

t_d(RCVU1)

Time duration, mmx_txdat and mmx_txse0 low together during

transition

14.0

ns

Time duration, mmx_txdat and mmx_txse0 high together during

transition

8.0

Time duration, mmx_rrxcv undefine during a single end 0

(mmx_txdat and mmx_txse0 low together)

14.0

8.0

Time duration, mmx_rxrcv undefine during a single end 1

(mmx_txdat and mmx_txse0 high together)

Table 6-70. Low-/Full-Speed USB Switching Characteristics Bidirectional Standard 4-pin Mode

NO.

PARAMETER

1.8V, 3.3V

MIN

UNIT

MAX

84.8

1.5

FSU14

FSU15

FSU16

FSU17

FSU18

t_{d(TXENL-DATV)}

t_{d(TXENL-SE0V)}

t_s(DAT-SE0)

Delay time, mmx_txen_n low to mmx_txdat valid

Delay time, mmx_txen_n low to mmx_txse0 valid

Skew between mmx_txdat and mmx_txse0 transition

Delay time, mmx_txdat invalid before mmx_txen_n high

Delay time, mmx_txse0 invalid before mmx_txen_n high

Rise time, mmx_txen_n

81.8

ns

t_{d(DATV-TXENH)}

t_{d(SE0V-TXENH)}

t_R(txen)

81.8

4.0

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Table 6-70. Low-/Full-Speed USB Switching Characteristics Bidirectional Standard 4-pin Mode

(continued)

NO.

PARAMETER

1.8V, 3.3V

MIN MAX

UNIT

t_F(txen)

t_R(dat)

t_F(dat)

t_R(se0)

t_F(se0)

Fall time, mmx_txen_n

4.0

ns

Rise time, mmx_txdat

Fall time, mmx_txdat

Rise time, mmx_txse0

Fall time, mmx_txse0

Transmit

FSU14

mmx_txen_n

mmx_txdat

mmx_txse0

mmx_rxrcv

Receive

FSU17

FSU18

FSU10

FSU12

FSU11

FSU15

FSU16

FSU11

FSU13

030-081

In mmx, x is equal to 0, 1, or 2.

Figure 6-42. Low-/Full-Speed USB Bidirectional Standard 4-pin Mode

6.6.3.3 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional Standard 3-pin Mode

Table 6-72 and Table 6-73 assume testing over the recommended operating conditions below (see

Figure 6-43).

Table 6-71. Low-/Full-Speed USB Timing Conditions Bidirectional Standard 3-pin Mode

TIMING CONDITION PARAMETER

1.8V, 3.3V

UNIT

Input Conditions

t_R

Input signal rise time

Input signal fall time

2.0

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

15.0

pF

Table 6-72. Low-/Full-Speed USB Timing Requirements Bidirectional Standard 3-pin Mode

NO.

PARAMETER

1.8V, 3.3V

MIN MAX

UNIT

FSU19

FSU20

t_d(DAT,SE0)

Time duration, mmx_txdat and mmx_txse0 low together during

transition

14.0

ns

Time duration, mmx_tsdat and mmx_txse0 high together during

transition

8.0

Table 6-73. Low-/Full-Speed USB Switching Characteristics Bidirectional Standard 3-pin Mode

NO.

PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

84.8

FSU21

FSU22

t_{d(TXENL-DATV)}

t_{d(TXENL-SE0V)}

Delay time, mmx_txen_n low to mmx_txdat valid

Delay time, mmx_txen_n low to mmx_txse0 valid

81.8

ns

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Table 6-73. Low-/Full-Speed USB Switching Characteristics Bidirectional Standard 3-pin Mode

(continued)

NO.

PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

FSU23

FSU24

FSU25

t_s(DAT-SE0)

t_{d(DATI-TXENH)}

t_{d(SE0I-TXENH)}

t_R(do)

Skew between mmx_txdat and mmx_txse0 transition

Delay time, mmx_txdat invalid to mmx_txen_n high

Delay time, mmx_txse0 invalid to mmx_txen_n high

Rise time, mmx_txen_n

1.5

ns

81.8

4.0

t_F(do)

Fall time, mmx_txen_n

t_R(do)

Rise time, mmx_txdat

t_F(do)

Fall time, mmx_txdat

t_R(do)

Rise time, mmx_txse0

t_F(do)

Fall time, mmx_txse0

Transmit

mmx_txen_n

Receive

FSU19

FSU21

FSU24

FSU25

FSU20

mmx_txdat

mmx_txse0

FSU22

FSU23

FSU19

FSU20

030-082

In mmx, x is equal to 0, 1, or 2.

Figure 6-43. Low-/Full-Speed USB Bidirectional Standard 3-pin Mode

6.6.3.4 Multiport Full-Speed Universal Serial Bus (USB) – Unidirectional TLL 6-pin Mode

Table 6-75 and Table 6-76 assume testing over the recommended operating conditions (see Figure 6-44).

Table 6-74. Low-/Full-Speed USB Timing Conditions Unidirectional TLL 6-pin Mode

TIMING CONDITION PARAMETER

1.8V, 3.3V

UNIT

Input Conditions

t_R

Input signal rise time

Input signal fall time

2

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

15

pF

Table 6-75. Low-/Full-Speed USB Timing Requirements Unidirectional TLL 6-pin Mode

NO.

PARAMETER

1.8V, 3.3V

MIN MAX

UNIT

FSUT1

FSUT2

t_d(SE0,DAT)

Time duration, mmx_txse0 and mmx_txdat low together

during transition

14

ns

Time duration, mmx_txse0 and mmx_txdat high together

during transition

8

Table 6-76. Low-/Full-Speed USB Switching Characteristics Unidirectional TLL 6-pin Mode

NO.

PARAMETER

1.8V, 3.3V

UNIT

MIN

81.8

MAX

FSUT3

t_d(TXENH-DPV)

Delay time, mmx_txen_n high to mmx_rxdp valid

84.8

ns

140

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Table 6-76. Low-/Full-Speed USB Switching Characteristics Unidirectional TLL 6-pin Mode (continued)

NO.

PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

FSUT4

FSUT5

FSUT6

FSUT7

FSUT8

t_d(TXENH-DMV)

t_d(DPI-TXENL)

t_d(DMI-TXENL)

t_s(DP-DM)

Delay time, mmx_txen_n high to mmx_rxdm valid

Delay time, mmx_rxdp invalid mmx_txen_n low

Delay time, mmx_rxdm invalid mmx_txen_n low

Skew between mmx_rxdp and mmx_rxdm transition

81.8

84.8

ns

1.5

t_s(DP,DM-RCV)

Skew between mmx_rxdp, mmx_rxdm, and mmx_rxrcv

transition

t_R(rxrcv)

t_F(rxrcv)

t_R(dp)

Rise time, mmx_rxrcv

Fall time, mmx_rxrcv

Rise time, mmx_rxdp

Fall time, mmx_rxdp

Rise time, mmx_rxdm

Fall time, mmx_rxdm

4

ns

t_F(dp)

t_R(dm)

t_F(dm)

mmx_txen_n

Transmit

Receive

FSUT1

FSUT2

mmx_txdat

mmx_txse0

mmx_rxdp

mmx_rxdm

mmx_rxrcv

FSUT1

FSUT3

FSUT5

FSUT6

FSUT4

FSUT7

FSUT8

030-083

In mmx, x is equal to 0, 1, or 2.

Figure 6-44. Low-/Full-Speed USB Unidirectional TLL 6-pin Mode

6.6.3.5 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional TLL 4-pin Mode

Table 6-78 and Table 6-79 assume testing over the recommended operating conditions (see Figure 6-45).

Table 6-77. Low-/Full-Speed USB Timing Conditions Bidirectional TLL 4-pin Mode

TIMING CONDITION PARAMETER

1.8V, 3.3V

UNIT

Input Conditions

t_R

Input signal rise time

Input signal fall time

2

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

15

pF

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Table 6-78. Low-/Full-Speed USB Timing Requirements Bidirectional TLL 4-pin Mode

NO.

PARAMETER

1.8V, 3.3V

MIN MAX

UNIT

FSUT9

t_d(DAT,SE0)

Time duration, mmx_txdat and mmx_txse0 low together during

transition

14

ns

FSUT10

Time duration, mmx_tsdat and mmx_txse0 high together during

transition

8

Table 6-79. Low-/Full-Speed USB Switching Characteristics Bidirectional TLL 4-pin Mode

NO.

PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

84.8

1.5

FSUT11

FSUT12

FSUT13

FSUT14

t_{d(TXENL-DATV)}

t_{d(TXENL-SE0V)}

t_s(DAT-SE0)

Delay time, mmx_txen_n active to mmx_txdat valid

Delay time, mmx_txen_n active to mmx_txse0 valid

Skew between mmx_txdat and mmx_txse0 transition

81.8

ns

t_s(DP,DM-RCV)

Skew between mmx_rxdp, mmx_rxdm, and mmx_rxrcv

transition

1.5

FSUT15

FSUT16

t_{d(DATI-TXENL)}

t_{d(SE0I-TXENL)}

t_R(rcv)

Delay time, mmx_txse0 invalid to mmx_txen_n Low

Delay time, mmx_txdat invalid to mmx_txen_n Low

Rise time, mmx_rxrcv

81.8

ns

4

t_F(rcv)

Fall time, mmx_rxrcv

t_R(dat)

Rise time, mmx_txdat

t_F(dat)

Fall time, mmx_txdat

t_R(se0)

Rise time, mmx_txse0

t_F(se0)

Fall time, mmx_txse0

mmx_txen_n

Transmit

Receive

FSUT9

FSUT11

FSUT15

FSUT16

FSUT10

mmx_txdat

mmx_txse0

mmx_rxrcv

FSUT12

FSUT13

FSUT14

FSUT9

FSUT10

030-084

In mmx, x is equal to 0, 1, or 2.

Figure 6-45. Low-/Full-Speed USB Bidirectional TLL 4-pin Mode

6.6.3.6 Multiport Full-Speed Universal Serial Bus (USB) Bidirectional TLL 3-pin Mode

Table 6-81 and Table 6-82 assume testing over the recommended operating conditions (see Figure 6-46).

Table 6-80. Low-/Full-Speed USB Timing Conditions Bidirectional TLL 3-pin Mode

TIMING CONDITION PARAMETER

1.8V, 3.3V

UNIT

Input Conditions

t_R

Input signal rise time

Input signal fall time

2

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

15

pF

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Table 6-81. Low-/Full-Speed USB Timing Requirements Bidirectional TLL 3-pin Mode

NO.

PARAMETER

1.8V, 3.3V

MIN MAX

UNIT

FSUT17

FSUT18

t_d(DAT,SE0)

Time duration, mmx_txdat and mmx_txse0 low together during

transition

14

ns

Time duration, mmx_tsdat and mmx_txse0 high together during

transition

8

Table 6-82. Low-/Full-Speed USB Switching Characteristics Bidirectional TLL 3-pin Mode

NO.

PARAMETER

1.8V, 3.3V

MIN

UNIT

MAX

84.8

1.5

FSUT19

FSUT20

FSUT21

FSUT22

FSUT23

t_{d(TXENH-DATV)}

t_{d(TXENH-SE0V)}

t_s(DAT-SE0)

t_{d(DATI-TXENL)}

t_{d(SE0I-TXENL)}

t_R(dat)

Delay time, mmx_txen_n high to mmx_txdat valid

Delay time, mmx_txen_n high to mmx_txse0 valid

Skew between mmx_txdat and mmx_txse0 transition

Delay time, mmx_txdat invalid mmx_txen_n low

Delay time, mmx_txse0 invalid mmx_txen_n low

Rise time, mmx_txdat

81.8

ns

81.8

4

t_F(dat)

Fall time, mmx_txdat

t_R(se0)

Rise time, mmx_txse0

t_F(se0)

Fall time, mmx_txse0

Receive

mmx_txen_n

Transmit

FSUT19

FSUT20

FSUT22

FSUT17

FSUT18

mmx_txdat

mmx_txse0

FSUT21

FSUT23

FSUT17

030-085

In mmx, x is equal to 0, 1, or 2.

Figure 6-46. Low-/Full-Speed USB Bidirectional TLL 3-pin Mode

6.6.4 Multiport High-Speed Universal Serial Bus (USB) Timing

In addition to the full-speed USB controller, a high-speed (HS) USB controller is instantiated inside

AM3517/05. It allows high-speed transactions (up to 480 Mbit/s) on the USB ports 1 and 2.

•

Port 1 and port 2:

–

12-bit master mode (SDR)

12-bit TLL master mode (SDR)

8-bit TLL master mode (DDR)

Note: TLL is not available in 3.3V mode

6.6.4.1 High-Speed Universal Serial Bus (USB) on Ports 1 and 2 12-bit Master Mode

Table 6-84 and Table 6-85 assume testing over the recommended operating conditions (see Figure 6-47).

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Table 6-83. High-Speed USB Timing Conditions 12-bit Master Mode

TIMING CONDITION PARAMETER

1.8V, 3.3V

UNIT

Input Conditions

t_R

Input signal rise time

Input signal fall time

2

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

3

pF

Table 6-84. High-Speed USB Timing Requirements 12-bit Master Mode⁽¹⁾

NO.

PARAMETER

1.8V, 3.3V

MIN MAX

UNIT

HSU3 t_s(DIRV-CLKH)

t_s(NXTV-CLKH)

HSU4 t_{h(CLKH-DIRIV)}

t_{h(CLKH-NXT/IV)}

Setup time, hsusbx_dir valid before hsusbx_clk rising edge

Setup time, hsusbx_nxt valid before hsusbx_clk rising edge

Hold time, hsusbx_dir valid after hsusbx_clk rising edge

Hold time, hsusbx_nxt valid after hsusbx_clk rising edge

Setup time, hsusbx_data[0:7] valid before hsusbx_clk rising edge

Hold time, hsusbx_data[0:7] valid after hsusbx_clk rising edge

9.3

0.2

9.3

0.2

ns

HSU5 t_{s(DATAV-CLKH)}

HSU6 t_{h(CLKH-DATIV)}

(1) In hsusbx, x is equal to 1 or 2.

Table 6-85. High-Speed USB Switching Characteristics 12-bit Master Mode⁽¹⁾

N O.

PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

HSU0

HSU1

HSU2

f_p(CLK)

hsusbx_clk clock frequency

Jitter standard deviation⁽²⁾, hsusbx_clk

60

200

13

MHz

ps

t_j(CLK)

t_d(clkL-STPV)

t_{d(clkL-STPIV)}

t_d(clkL-DV)

t_d(clkL-DIV)

t_R(do)

Delay time, hsusbx_clk high to output hsusbx_stp valid

Delay time, hsusbx_clk high to output hsusbx_stp invalid

Delay time, hsusbx_clk high to output hsusbx_data[0:7] valid

Delay time, hsusbx_clk high to output hsusbx_data[0:7] invalid

Rise time, output signals

ns

2

ns

13

ns

2

ns

t_F(do)

Fall time, output signals

ns

(1) In hsusbx, x is equal to 1 or 2.

(2) The jitter probability density can be approximated by a Gaussian function.

HSU0

hsusbx_clk

HSU1

hsusbx_stp

hsusbx_dir_&_nxt

hsusbx_data[7:0]

HSU3

HSU4

HSU6

HSU5

HSU2

Data_OUT

Data_IN

030-087

In hsusbx, x is equal to 1 or 2.

Figure 6-47. High-Speed USB 12-bit Master Mode

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6.6.4.2 High-Speed Universal Serial Bus (USB) on Ports 1 and 2 12-bit TLL Master Mode

Table 6-87 and Table 6-88 assume testing over the recommended operating conditions (see Figure 6-48).

Table 6-86. High-Speed USB Timing Conditions 12-bit TLL Master Mode

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

2

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

3

pF

Table 6-87. High-Speed USB Timing Requirements 12-bit TLL Master Mode⁽¹⁾

NO.

PARAMETER

1.8V, 3.3V

MIN MAX

UNIT

HSU2 t_s(STPV-CLKH)

HSU3 t_{s(CLKH-STPIV)}

HSU4 t_{s(DATAV-CLKH)}

HSU5 t_{h(CLKH-DATIV)}

Setup time, hsusbx_tll_stp valid before hsusbx_tll_clk rising edge

Hold time, hsusbx_tll_stp valid after hsusbx_tll_clk rising edge

Setup time, hsusbx_tll_data[7:0] valid before hsusbx_tll_clk rising edge

Hold time, hsusbx_tll_data[7:0] valid after hsusbx_tll_clk rising edge

6

0

6

0

ns

(1) In hsusbx, x is equal to 1, 2, or 3.

Table 6-88. High-Speed USB Switching Characteristics 12-bit TLL Master Mode⁽¹⁾

NO.

PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

HSU0 f_p(CLK)

t_j(CLK)

hsusbx_tll_clk clock frequency

Jitter standard deviation⁽²⁾, hsusbx_tll_clk

60

200

9

MHz

ps

ns

HSU6 t_d(CLKL-DIRV)

t_{d(CLKL-DIRIV)}

t_d(CLKL-NXTV)

t_{d(CLKL-NXTIV)}

HSU7 t_d(CLKL-DV)

t_d(CLKL-DIV)

Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir valid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir invalid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt valid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt invalid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[7:0] valid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[7:0] invalid

Rise time, output signals

0

9

t_R(do)

2

t_F(do)

Fall time, output signals

(1) In hsusbx, x is equal to 1, 2, or 3.

(2) The jitter probability density can be approximated by a Gaussian function.

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HSU0

hsusbx_tll_clk

HSU3

HSU2

hsusbx_tll_stp

HSU6

HSU7

hsusbx_tll_dir_&_nxt

HSU4

HSU7

HSU5

Data_IN

Data_OUT

hsusbx_tll_data[7:0]

030-088

In hsusbx, x is equal to 1, 2, or 3.

Figure 6-48. High-Speed USB 12-bit TLL Master Mode

6.6.4.3 High-Speed Universal Serial Bus (USB) on Ports 1 and 2 8-bit TLL Master Mode

Table 6-90 and Table 6-91 assume testing over the recommended operating conditions (see Figure 6-49).

Table 6-89. High-Speed USB Timing Conditions 8-bit TLL Master Mode

TIMING CONDITION PARAMETER

Input Conditions

1.8V, 3.3V

UNIT

t_R

Input signal rise time

Input signal fall time

2

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

3

pF

Table 6-90. High-Speed USB Timing Requirements 8-bit TLL Master Mode⁽¹⁾

NO.

PARAMETER

1.8V, 3.3V

MIN MAX

UNIT

HSU2 t_s(STPV-CLKH)

HSU3 t_{s(CLKH-STPIV)}

HSU4 t_{s(DATAV-CLKH)}

HSU5 t_{h(CLKH-DATIV)}

Setup time, hsusbx_tll_stp valid before hsusbx_tll_clk rising edge

Hold time, hsusbx_tll_stp valid after hsusbx_tll_clk rising edge

Setup time, hsusbx_tll_data[3:0] valid before hsusbx_tll_clk rising edge

Hold time, hsusbx_tll_data[3:0] valid after hsusbx_tll_clk rising edge

6

0

ns

3

-0.1

(1) In hsusbx, x is equal to 1, 2, or 3.

Table 6-91. High-Speed USB Switching Characteristics 8-bit TLL Master Mode⁽¹⁾

NO.

PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

HSU0

f_p(CLK)

hsusbx_tll_clk clock frequency

Jitter standard deviation⁽²⁾, hsusbx_tll_clk

60

200

52.4%

9

MHz

ps

t_j(CLK)

HSU1

HSU6

t_j(CLK)

Duty cycle, hsusbx_tll_clk pulse duration (low and high)

Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir valid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir invalid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt valid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt invalid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[3:0] valid

47.6%

t_d(CLKL-DIRV)

t_{d(CLKL-DIRIV)}

t_d(CLKL-NXTV)

t_{d(CLKL-NXTIV)}

t_d(CLKL-DV)

ns

0

9

4

HSU7

(1) In hsusbx, x is equal to 1, 2, or 3.

(2) The jitter probability density can be approximated by a Gaussian function.

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Table 6-91. High-Speed USB Switching Characteristics 8-bit TLL Master Mode (continued)

NO.

PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

HSU8

t_d(CLKL-DIV)

t_R(do)

Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[3:0] invalid

Rise time, output signals

0

ns

2

t_F(do)

Fall time, output signals

HSU0

HSU1

hsusbx_tll_clk

HSU3

HSU2

hsusbx_tll_stp

HSU6

hsusbx_tll_dir_&_nxt

HSU5

HSU4

HSU5

HSU8

HSU7

HSU4

HSU7

Data_IN

Data_IN_(n+1)

Data_IN_(n+2)

Data_OUT

Data_OUT_(n+1)

hsusbx_tll_data[3:0]

030-089

In hsusbx, x is equal to 1, 2, or 3.

Figure 6-49. High-Speed USB 8-bit TLL Master Mode

6.6.5 USB0 OTG (USB2.0 OTG)

The AM3517/05 USB2.0 peripheral supports the following features:

•

USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s) and full speed (FS: 12 Mb/s)

USB 2.0 host at speeds HS, FS, and low speed (LS: 1.5 Mb/s)

All transfer modes (control, bulk, interrupt, and isochronous)

16 Transmit (TX) and 16 Receive (RX) endpoints in addition to endpoint 0

FIFO RAM

–

32K endpoint

Programmable size

•

Integrated USB 2.0 High Speed PHY

Connects to a standard Charge Pump for VBUS 5 V generation

RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB

6.6.5.1 USB2.0 Electrical Data/Timing

(1)

Table 6-92. USB2.0 (OTG) Switching Characteristics

NO.

PARAMETER

1.8V,3.3V

UNIT

HIGH SPEED

FULL SPEED

LOW SPEED

MIN

MAX

MIN

MAX

MIN

MAX

USB V_CRS

1

Output signal cross-over voltage

Driver Output Impedance

TBD

V

Ω

USB Z_DRV

2

TBD

USB t_r(D)

3

Rise time, USB_DP and USB_DM signals

TBD

ns

(1) In hsusbx, x is equal to 1, 2, or 3.

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Table 6-92. USB2.0 (OTG) Switching Characteristics (continued)

NO.

PARAMETER

1.8V,3.3V

UNIT

HIGH SPEED

FULL SPEED

LOW SPEED

MIN

MAX

MIN

MAX

MIN

MAX

USB t_f(D)

4

Fall time, USB_DP and USB_DM signals

Rise/Fall time, matching

Pulse duration, EOP transmitter

Pulse duration, EOP receiver

Consecutive jitter

TBD

ns

%

USB t_RFM

5

TBD

USB t_w(EOPT)

6

ns

USB t_w(EOPR)

7

ns

USB t_(cjr)

8

TBD

ns

USB t_(pjkjr)

9

Paired JK jitter

ns

USB t_(jpkjr)

10

Paired KJ jitter

ns

USB f_(op)

11

Operating frequency

TBD

Mb/s

t

– t

per

jr

OH

USB_DM

V

90% V

CRS

USB_DP

10% V

OL

t

f

t

r

SPRS550-005

Figure 6-50. USB 2.0 Integrated Transceiver Interface Timing

6.6.6 High-End Controller Area Network Controller (HECC) Timing

The AM3517/05 device has a High-End Controller Area Network Controller (HECC). The HECC uses

established protocol to communicate serially with other controllers in harsh environments. The HECC is

fully compliant with the Controller Area Network (CAN) protocol, version 2.0B.

Key features of the HECC include the following:

•

CAN, version 2.0B compliant

32 RX/TX message objects

32 receive identifier masks

Programmable wake-up on bus activity

Programmable interrupt scheme

Automatic reply to a remote request

Automatic re-transmission in case of error or loss of arbitration

Protection against reception of a new message

32-bit time stamp

Local network time counter

Programmable priority register for each message

Programmable transmission and reception time-out

HECC/SCC mode of operation

Standard-Extended Identifier

Self-test mode

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6.6.6.1 HECC Timing Requirements

Table 6-93. Timing Requirements for HECC Receive (see Figure 6-51)

1.8 V, 3.3 V

MIN

NO.

UNIT

MAX

1

2

f_(baud)

Maximum programmable baud rate

Pulse duration, receive data bit

1

3

Mbps

ns

t_{w(HECC_RX)}

-1

6.6.6.2 HECC Switching Characteristics

Table 6-94. Switching Characteristics Over Recommended Operating Conditions for HECC Transmit

(see Figure 6-51)

1.8 V, 3.3 V

NO.

PARAMETER

UNIT

MIN

MAX

3

4

f_(baud)

Maximum programmable baud rate

Pulse duration, transmit data bit

1

3

Mbps

ns

t_{w(HECC_TX)}

-1

2

4

HECCx_RX

HECCx_TX

Figure 6-51. HECC Transmit/Receive Timing

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6.6.7 Ethernet Media Access Controller (EMAC)

The Ethernet Media Access Controller (EMAC) provides an efficient interface between AM3517/05 and the

network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps

in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The EMAC controls the flow of packet data from the AM3517/05 device to the PHY. The MDIO module

controls PHY configuration and status monitoring.

Both the EMAC and the MDIO modules interface to the AM3517/05 device through a custom interface that

allows efficient data transmission and reception. This custom interface is referred to as the EMAC control

module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to

multiplex and control interrupts.

6.6.7.1 EMAC Electrical Data/ Timing

Table 6-95. RMII Input Timing Requirements

1.8V, 3.3V

NO.

PARAMETER

MIN

TYP

MAX

UNIT

ns

1

2

3

6

tc(REFCLK)

Cycle Time, REF_CLK

TBD

tw(REFCLKH)

tw(REFCLKL)

tsu(RXD-REFCLK)

Pulse Width, REF_CLK High

Pulse Width, REF_CLK Low

TBD

ns

Input Setup Time, RXD Valid before REF_CLK

High

ns

7

8

th(REFCLK-RXD)

Input Hold Time, RXD Valid after REF_CLK High

TBD

ns

tsu(CRSDV-REFCLK)

Input Setup Time, CRSDV Valid before

REF_CLK High

9

th(REFCLK-CRSDV)

tsu(RXER-REFCLK)

th(REFCLKR-RXER)

Input Hold Time, CRSDV Valid after REF_CLK

High

TBD

ns

10

11

Input Setup Time, RXER Valid before REF_CLK

High

Input Hold Time, RXER Valid after REF_CLK

High

Table 6-96. RMII Output Timing Requirements

1.8V, 3.3V

TYP

NO.

PARAMETER

MIN

MAX

TBD

UNIT

ns

4

5

td(REFCLK-TXD)

td(REFCLK-TXEN)

Output Delay Time, REF_CLK High to TXD Valid

TBD

Output Delay Time, REF_CLK High to TXEN

Valid

ns

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1

2

3

REF_CLK

5

TXEN

4

TXD[1:0]

6

7

RXD[1:0]

CRS_DV

8

9

10

11

RXER_IN

SPRS550-004

Figure 6-52. RMII Timing Diagram

6.6.8 Universal Asynchronous Receiver/Transmitter (UART)

The AM3517/05 has four UARTs (one with Infrared Data Association [IrDA] and Consumer Infrared [CIR]

modes).

Table 6-97. Timing Requirements for UARTx Receive

1.8V, 3.3V

UNIT

NO.

MIN

.96U

MAX

1.05U

4

5

t_w(URXDB)

t_w(URXSB)

Pulse duration, receive data bit (RXDn)

Pulse duration, receive start bit

ns

Table 6-98. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit

1.8V, 3.3V

NO.

PARAMETER

UNIT

MIN

MAX

UART0 Maximum programmable baud rate f_{(baud_15)}

UART0 Maximum programmable baud rate f_{(baud_30)}

UART0 Maximum programmable baud rate f_{(baud_100)}

Pulse duration, transmit data bit, 15/30/100 pF

Pulse duration, transmit start bit, 15/30/100 pF

5

1

f_(baud)

0.23 mbps

0.115

2

3

t_w(UTXDB)

t_w(UTXSB)

U - 2

U + 2

ns

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3

2

Start

Bit

UART_TXDn

Data Bits

5

4

Start

Bit

UART_RXDn

Data Bits

Figure 6-53. UART Transmit/Receive Timing

6.6.8.1 UART IrDA Interface

The IrDA module can operate in three different modes:

•

Slow infrared (SIR) (≤115.2 Kbits/s)

Medium infrared (MIR) (0.576 Mbits/s and 1.152 Mbits/s)

Fast infrared (FIR) (4 Mbits/s)

Pulse duration

90%

50%

10%

t_r

t_f

030-118

Figure 6-54. UART IrDA Pulse Parameters

6.6.8.1.1 IrDA—Receive Mode

Table 6-99. UART IrDA—Signaling Rate and Pulse Duration—Receive Mode

ELECTRICAL PULSE DURATION

SIGNALING RATE

UNIT

MIN

NOMINAL

SIR

MAX

2.4 Kbit/s

9.6 Kbit/s

1.41

78.1

19.5

9.75

4.87

3.25

1.62

88.55

22.13

11.07

5.96

µs

19.2 Kbit/s

38.4 Kbit/s

57.6 Kbit/s

115.2 Kbit/s

4.34

2.23

MIR

0.576 Mbit/s

1.152 Mbit/s

297.2

149.6

416

208

518.8

258.4

ns

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Table 6-99. UART IrDA—Signaling Rate and Pulse Duration—Receive Mode

(continued)

ELECTRICAL PULSE DURATION

SIGNALING RATE

UNIT

MIN

NOMINAL

FIR

MAX

4.0 Mbit/s (Single pulse)

4.0 Mbit/s (Double pulse)

67

125

164

289

ns

190

250

Table 6-100. UART IrDA—Rise and Fall Time—Receive

Mode

PARAMETER

MAX

UNIT

t_R

t_F

Rising time,

uart3_rx_irrx

200

ns

Falling time,

uart3_rx_irrx

200

ns

6.6.8.1.2 IrDA—Transmit Mode

Table 6-101. UART IrDA—Signaling Rate and Pulse Duration—Transmit Mode

SIGNALING RATE

ELECTRICAL PULSE DURATION

UNIT

MIN

NOMINAL

SIR

MAX

2.4 Kbit/s

9.6 Kbit/s

78.1

19.5

9.75

4.87

3.25

1.62

78.1

19.5

9.75

4.87

3.25

1.62

MIR

78.1

19.5

9.75

4.87

3.25

1.62

µs

19.2 Kbit/s

38.4 Kbit/s

57.6 Kbit/s

115.2 Kbit/s

0.576 Mbit/s

1.152 Mbit/s

414

206

416

419

211

ns

208

FIR

4.0 Mbit/s (Single pulse)

4.0 Mbit/s (Double pulse)

123

248

125

128

253

ns

250

6.6.9 HDQ / 1-Wire Interfaces

This module is intended to work with both the HDQ and the 1-Wire protocols. The protocols use a single

wire to communicate between the master and the slave. The protocols employ an asynchronous return to

1 mechanism where, after any command, the line is pulled high.

6.6.9.1 HDQ Protocol

Table 6-102 and Table 6-103 assume testing over the recommended operating conditions (see

Figure 6-55 through Figure 6-58).

Table 6-102. HDQ Timing Requirements

PARAMETER

t_CYCD

DESCRIPTION

Bit window

MIN

MAX

UNIT

253

s

t_HW1

68

t_HW0

180

t_RSPS

Command to host respond time⁽¹⁾

(1) Defined by software.

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Table 6-103. HDQ Switching Characteristics

PARAMETER

DESCRIPTION

Break timing

MIN

TYP

193

63

MAX

UNIT

t_B

s

t_BR

Break recovery

Bit window

t_CYCH

t_DW1

t_DW0

253

1.3

Sends1 (write)

Sends0 (write)

101

tB

tBR

HDQ

030-095

Figure 6-55. HDQ Break (Reset) Timing

tCYCH

tHW0

tHW1

030-096

Figure 6-56. HDQ Read Bit Timing (Data)

tCYCD

tDW0

tDW1

030-097

Figure 6-57. HDQ Write Bit Timing (Command/Address or Data)

Command _byte_written

0_(LSB)

Data_byte_received

1

tRSPS

Break

1

6

7_(MSB)

0_(LSB)

6

030-098

Figure 6-58. HDQ Communication Timing

6.6.9.2 1-Wire Protocol

Table 6-104 and Table 6-105 assume testing over the recommended operating conditions (see

Figure 6-59 through Figure 6-61).

Table 6-104. 1-Wire Timing Requirements

PARAMETER

t_PDH

DESCRIPTION

MIN

MAX

UNIT

Presence pulse delay high

Presence pulse delay low

Read bit-zero time

68

s

t_PDL

68 t_PDH

t_RDV+ t_REL

102

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Table 6-105. 1-Wire Switching Characteristics

PARAMETER

t_RSTL

DESCRIPTION

MIN

TYP

484

102

1.3

MAX

UNIT

Reset time low

s

t_RSTH

Reset time high

Write bit cycle time

Write bit-one time

Write bit-zero time

Recovery time

t_SLOT

t_LOW1

t_LOW0

101

134

13

t_REC

t_LOWR

Read bit strobe time

tRSTH

tPDL

tRTSL

tPDH

1-WIRE

030-099

Figure 6-59. 1-Wire Break (Reset) Timing

tSLOT_and_ tREC

tRDV_and_ tREL

tLOWR

1-WIRE

030-100

Figure 6-60. 1-Wire Read Bit Timing (Data)

tSLOT_and_tREC

tLOW0

1-WIRE

tLOW1

030-101

Figure 6-61. 1-Wire Write Bit Timing (Command/Address or Data)

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6.6.10 I²C Interface

The multimaster I²C peripheral provides an interface between two or more devices via an I²C serial bus.

The I²C controller supports the multimaster mode which allows more than one device capable of

controlling the bus to be connected to it. Each I²C device is recognized by a unique address and can

operate as either transmitter or receiver, according to the function of the device. In addition to being a

transmitter or receiver, a device connected to the I²C bus can also be considered as master or slave when

performing data transfers. This data transfer is carried out via two serial bidirectional wires:

•

An SDA data line

An SCL clock line

The following sections illustrate the data transfer is in master or slave configuration with 7-bit addressing

format. The I²C interface is compliant with Philips I²C specification version 2.1. It supports standard mode

(up to 100K bits/s), fast mode (up to 400K bits/s) and high-speed mode (up to 3.4Mb/s) .

6.6.10.1 I²C Standard/Fast-Speed Mode

Table 6-106. I²C Standard/Fast-Speed Mode Timings

1.8V, 3.3-V

NO.

PARAMETER⁽¹⁾

STANDARD

MODE

FAST MODE

UNIT

MIN

MAX

MIN MAX

f_SCL

Clock Frequency, i2cX_scl

100

400

kHz

s

I1

I2

I3

I4

I5

t_w(SCLH)

Pulse Duration, i2cX_scl high

4

0.6

1.3

100⁽²⁾

t_w(SCLL)

Pulse Duration, i2cX_scl low

4.7

250

s

t_{su(SDAV-SCLH)}

t_h(SCLHSDAV)

t_{su(SDAL-SCLH)}

Setup time, i2cX_sda valid before i2cX_scl active level

Hold time, i2cX_sda valid after i2cX_scl active level

ns

s

3.45⁽³⁾

0.9⁽³⁾

Setup time, i2cX_scl high after i2cX_sda low (for a

START⁽⁴⁾condition or a repeated START condition)

4.7

4

0.6

1.3

s

I6

I7

I8

t_h(SCLHSDAH)

t_{h(SCLHRSTART)}

t_w(SDAH)

Hold time, i2cX_sda low level after i2cX_scl high level

(STOP condition)

s

Hold time, i2cX_sda low level after i2cX_scl high level (for

a repeated START condition)

4

Pulse duration, i2cX_sda high between STOP and START

conditions

4.7

t_R(SCL)

t_F(SCL)

t_R(SDA)

t_F(SDA)

CB

Rise time, i2cX_scl

1000

300

1000

300

60

300

60

ns

pF

Fall time, i2cX_scl

Rise time, i2cX_sda

Fall time, i2cX_sda

Capacitive load for each bus line

(1) In i2cX, X is equal to 1, 2, or 3.

(2) A fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement t_{su(SDAV-SCLH)}250 ns must then be

met. This is automatically the case if the device does not stretch the low period of the i2cx_scl. If such a device does stretch the low

period of the i2cx_scl, it must output the next data bit to the i2cx_sda line t_r(SDA)max + t_{su(SDAV-SCLH)}= 1000 + 250 = 1250 ns (according

to the standard-mode I²C-bus specification) before the i2cx_scl line is released.

(3) The maximum t_h(SCLH-SDA)has only to be met if the device does not stretch the low period of the i2cx_scl signal.

(4) After this time, the first clock is generated.

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START REPEAT

START

STOP

i2cX_sda

I2

I5

I8

I7

I6

I1

I3

I4

I6

i2cX_scl

030-093

Figure 6-62. I²C Standard/Fast Mode

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6.6.10.2 I²C High-Speed Mode

Table 6-107. I²C HighSpeed Mode Timings⁽¹⁾⁽²⁾

1.8V, 3.3V

CB = 60 pF MAX CB = 400 pF MAX

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

f_SCL

Clock frequency, i2cX_scl

Pulse duration, i2cX_scl high

Pulse duration, i2cX_scl low

3.4

1.7

MHz

s

I1

I2

I3

t_w(SCLH)

t_w(SCLL)

60⁽³⁾

160⁽³⁾

10

120⁽³⁾

320⁽³⁾

10

s

t_{su(SDAV-SCLH)}

Setup time, i2cX_sda valid before i2cX_scl

active level

ns

I4

I5

t_h(SCLHSDAV)

Hold time, i2cX_sda valid after i2cX_scl active

level

70

0⁽²⁾

160

150

s

t_{su(SDAL-SCLH)}

Setup time, i2cX_scl high after i2cX_sda low

(for a START⁽⁴⁾condition or a repeated START

condition)

160

I6

I7

t_h(SCLHSDAH)

Hold time, i2cX_sda low level after i2cX_scl high

level (STOP condition)

160

s

t_{h(SCLHRSTART)}

Hold time, i2cX_sda low level after i2cX_scl high

level (for a repeated START condition)

ns

t_R(SCL)

Rise time, i2cX_scl

10

40

80

ns

Rise time, i2cX_scl after a repeated START

condition and after a bit acknowledge

160

t_F(SCL)

t_R(SDA)

t_F(SDA)

Fall time, i2cX_scl

Rise time, i2cX_sda

Fall time, i2cX_sda

10

40

80

ns

160

(1) In i2cX, X is equal to 1, 2, or 3.

(2) The device provides (via the I²C bus) a hold time of at least 300 ns for the i2cx_sda signal (refer to the fall and rise time of i2cx_scl) to

bridge the undefined region of the falling edge of i2cx_scl.

(3) HS-mode master devices generate a serial clock signal with a high to low ratio of 1 to 2. t_w(SCLL)> 2 t_w(SCLH)

.

(4) After this time, the first clock is generated.

START REPEAT

STOP

I7

i2cX_sda

I5

I6

I1

I2

I3

I4

i2cX_scl

030-094

Figure 6-63. I²C High-Speed ModeStep 1Step 2Step 3

(1) HS-mode master devices generate a serial clock signal with a high-to-low ratio of 1 to 2. t_w(SCLL)> 2 x t_w(SCLH)

.

(2) In i2cX, X is equal to 1, 2, or 3.

(3) After this time, the first clock is generated.

Table 6-108. Correspondence Standard vs. TI Timing References

TI-AM35x

STANDARD-I²C

S/F Mode

F_SCL

HS Mode

F_SCLH

f_SCL

I1

I2

I3

I4

I5

I6

t_w(SCLH)

T_HIGH

t_w(SCLL)

T_LOW

t_{su(SDAV-SCLH)}

t_h(SCLH-SDAV)

t_{su(SDAL-SCLH)}

t_h(SCLH-SDAH)

T_SU;DAT

T_SU;STA

T_HD;STA

T_SU;DAT

T_SU;STA

T_HD;STA

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Table 6-108. Correspondence Standard vs. TI Timing References (continued)

TI-AM35x

STANDARD-I²C

S/F Mode

T_SU;STO

T_BUF

HS Mode

I7

I8

t_{h(SCLH-RSTART)}

t_w(SDAH)

T_SU;STO

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6.7 Removable Media Interfaces

6.7.1 High-Speed Multimedia Memory Card (MMC) and Secure Digital IO Card (SDIO) Timing

The MMC/SDIO host controller provides an interface to high-speed and standard MMC, SD memory

cards, or SDIO cards. The application interface is responsible for managing transaction semantics. The

MMC/SDIO host controller deals with MMC/SDIO protocol at transmission level, packing data, adding

CRC, start/end bit, and checking for syntactical correctness.

There are three MMC interfaces on the AM3517/05:

•

MMC/SD/SDIO Interface 1:

–

1.8-V/3.3-V support

8 bits

•

MMC/SD/SDIO Interface 2:

–

1.8-V/3.3-V support

8 bits

4 bits with external transceiver allowing to support 1.8-V/3.3-V peripherals in 1.8-V mode operation.

Transceiver direction control signals are multiplexed with the upper four data bits.

•

MMC/SD/SDIO Interface 3:

–

1.8-V/3.3-V support

8 bits

6.7.1.1 MMC/SD/SDIO in SD Identification Mode

Table 6-110 and Table 6-111 assume testing over the recommended operating conditions and electrical

characteristic conditions.

Table 6-109. MMC/SD/SDIO Timing Conditions SD Identification Mode

TIMING CONDITION PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

SD Identification Mode

Input Conditions

t_R

Input signal rise time

Input signal fall time

TBD

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

TBD

pF

Table 6-110. MMC/SD/SDIO Timing Requirements SD Identification Mode^(1)(2)(3)

NO.

PARAMETER

1.8V, 3.3V

MIN MAX

UNIT

SD Identification Mode

MMC/SD/SDIO Interface 1

HSSD3/SD3

t_{su(CMDV-CLKIH)}

Setup time, mmc1_cmd valid before mmc1_clk rising

clock edge

TBD

ns

HSSD4/SD4

t_{su(CLKIH-CMDIV)}

Hold time, mmc1_cmd valid after mmc1_clk rising

clock edge

MMC/SD/SDIO Interface 2

HSSD3/SD3

t_{su(CMDV-CLKIH)}

Setup time, mmc2_cmd valid before mmc2_clk rising

clock edge

TBD

ns

HSSD4/SD4

t_{su(CLKIH-CMDIV)}

Hold time, mmc2_cmd valid after mmc2_clk rising

clock edge

(1) Timing parameters are referred to output clock specified in Table 6-111.

(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-111.

(3) Corresponding figures showing timing parameters are common with other interface modes. (See SD and HS SD modes).

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Table 6-110. MMC/SD/SDIO Timing Requirements SD Identification Mode (continued)

NO.

PARAMETER

1.8V, 3.3V

MIN MAX

UNIT

MMC/SD/SDIO Interface 3

HSSD3/SD3

t_{su(CMDV-CLKIH)}

Setup time, mmc3_cmd valid before mmc3_clk rising

clock edge

TBD

ns

HSSD4/SD4

t_{su(CLKIH-CMDIV)}

Hold time, mmc3_cmd valid after mmc3_clk rising

clock edge

Table 6-111. MMC/SD/SDIO Switching Characteristics SD Identification Mode⁽¹⁾

NO.

PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

SD Identification Mode

HSSD1/SD1

HSSD2/SD2

t_c(clk)

Cycle time⁽²⁾, output clk period

TBD

ns

ps

t_W(clkH)

t_W(clkL)

t_dc(clk)

t_j(clk)

Typical pulse duration, output clk high

Typical pulse duration, output clk low

Duty cycle error, output clk

TBD

Jitter standard deviation⁽³⁾, output clk

MMC/SD/SDIO Interface 1

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

TBD

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

HSSD5/SD5

t_d(CLKOH-CMD)

Delay time, mmc1_clk rising clock edge to mmc1_cmd

transition

TBD

MMC/SD/SDIO Interface 2

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

TBD

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

HSSD5/SD5

t_d(CLKOH-CMD)

Delay time, mmc2_clk rising clock edge to mmc2_cmd

transition

MMC/SD/SDIO Interface 3

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

TBD

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

HSSD5/SD5

t_d(CLKOH-CMD)

Delay time, mmc3_clk rising clock edge to mmc3_cmd

transition

(1) Corresponding figures showing timing parameters are common with other interface modes (see SD and HS SD modes).

(2) Related with the output clk maximum and minimum frequencies programmable in I/F module.

(3) The jitter probability density can be approximated by a Gaussian function.

Table 6-112. X Parameter

CLKD

1 or Even

Odd

X

0.5

(trunk[CLKD/2]+1)/CLKD

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Table 6-113. Y Parameter

CLKD

1 or Even

Odd

Y

0.5

(trunk[CLKD/2])/CLKD

6.7.1.2 MMC/SD/SDIO in High-Speed MMC Mode

Table 6-115 and Table 6-116 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-64 and Figure 6-65).

Table 6-114. MMC/SD/SDIO Timing Conditions High-Speed MMC Mode

TIMING CONDITION PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

High-Speed MMC Mode

Input Conditions

t_R

Input signal rise time

Input signal fall time

TBD

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

TBD

pF

Table 6-115. MMC/SD/SDIO Timing Requirements High-Speed MMC Mode^(1)(2)(3)(4)

NO.

PARAMETER

1.8 V, 3.3V

MAX

UNIT

MIN

High-Speed MMC Mode

MMC/SD/SDIO Interface 1

MMC3 t_{su(CMDV-CLKIH)}

Setup time, mmc1_cmd valid before mmc1_clk rising

clock edge

TBD

ns

MMC4 t_{su(CLKIH-CMDIV)}

MMC7 t_{su(DATxV-CLKIH)}

MMC8 t_{su(CLKIH-DATxIV)}

Hold time, mmc1_cmd valid after mmc1_clk rising clock

edge

Setup time, mmc1_datx valid before mmc1_clk rising

clock edge

Hold time, mmc1_datx valid after mmc1_clk rising clock

edge

MMC/SD/SDIO Interface 2

MMC3 t_{su(CMDV-CLKIH)}

Setup time, mmc2_cmd valid before mmc2_clk rising

clock edge

TBD

ns

MMC4 t_{su(CLKIH-CMDIV)}

MMC7 t_{su(DATxV-CLKIH)}

MMC8 t_{su(CLKIH-DATxIV)}

Hold time, mmc2_cmd valid after mmc2_clk rising clock

edge

Setup time, mmc2_datx valid before mmc2_clk rising

clock edge

Hold time, mmc2_datx valid after mmc2_clk rising clock

edge

MMC/SD/SDIO Interface 3

MMC3 t_{su(CMDV-CLKIH)}

Setup time, mmc3_cmd valid before mmc3_clk rising

clock edge

TBD

ns

MMC4 t_{su(CLKIH-CMDIV)}

MMC7 t_{su(DATxV-CLKIH)}

Hold time, mmc3_cmd valid after mmc3_clk rising clock

edge

Setup time, mmc3_datx valid before mmc3_clk rising

clock edge

(1) Timing parameters are referred to output clock specified in Table 6-116.

(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-116.

(3) Corresponding figures showing timing parameters are common with Standard MMC mode (See Figure 6-64 and Figure 6-65)

(4) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.

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Table 6-115. MMC/SD/SDIO Timing Requirements High-Speed MMC Mode (continued)

NO.

PARAMETER

1.8 V, 3.3V

MAX

TBD

UNIT

MIN

MMC8 t_{su(CLKIH-DATxIV)}

Hold time, mmc3_datx valid after mmc3_clk rising clock

edge

ns

Table 6-116. MMC/SD/SDIO Switching Characteristics High-Speed MMC Mode⁽¹⁾

N O.

PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

High-Speed MMC Mode

MMC1

MMC2

t_c(clk)

Cycle time⁽²⁾, output clk period

TBD

ns

ps

t_W(clkH)

t_W(clkL)

t_dc(clk)

t_j(clk)

Typical pulse duration, output clk high

Typical pulse duration, output clk low

Duty cycle error, output clk

TBD

Jitter standard deviation⁽³⁾, output clk

MMC/SD/SDIO Interface 1

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

TBD

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

MMC5

MMC6

t_d(CLKOH-CMD)

Delay time, mmc1_clk rising clock edge to mmc1_cmd

transition

TBD

t_{d(CLKOH-DATx)}

Delay time, mmc1_clk rising clock edge to mmc1_datx

transition

TBD

ns

MMC/SD/SDIO Interface 2

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

TBD

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

MMC5

MMC6

t_d(CLKOH-CMD)

Delay time, mmc2_clk rising clock edge to mmc2_cmd

transition

TBD

t_{d(CLKOH-DATx)}

Delay time, mmc2_clk rising clock edge to mmc2_datx

transition

TBD

ns

MMC/SD/SDIO Interface 3

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

TBD

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

MMC5

MMC6

t_d(CLKOH-CMD)

Delay time, mmc3_clk rising clock edge to mmc3_cmd

transition

TBD

t_{d(CLKOH-DATx)}

Delay time, mmc3_clk rising clock edge to mmc3_datx

transition

TBD

ns

(1) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.

(2) Related with the output clk maximum and minimum frequencies programmable in I/F module.

(3) The jitter probability density can be approximated by a Gaussian function.

Table 6-117. X Parameter

CLKD

1 or Even

Odd

X

0.5

(trunk[CLKD/2]+1)/CLKD

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Table 6-118. Y Parameter

CLKD

1 or Even

Odd

Y

0.5

(trunk[CLKD/2])/CLKD

For details about clock division factor CLKD, see the TBD.

6.7.1.3 MMC/SD/SDIO in Standard MMC Mode and MMC Identification Mode

Table 6-120 and Table 6-121 assume testing over the recommended operating conditions and electrical

characteristic conditions.

Table 6-119. MMC/SD/SDIO Timing Conditions Standard MMC Mode and MMC Identification Mode

TIMING CONDITION PARAMETER

Standard MMC Mode and MMC Identification Mode

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

TBD

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

TBD

pF

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Table 6-120. MMC/SD/SDIO Timing Requirements Standard MMC Mode and MMC Identification Mode⁽¹⁾⁽²⁾

NO.

PARAMETER

1.8 V

3.3 V

UNIT

MIN

MAX

MIN

MAX

Standard MMC Mode and MMC Identification Mode

MMC/SD/SDIO Interface 1

MMC3 t_{su(CMDV-CLKIH)}

MMC4 t_{su(CLKIH-CMDIV)}

MMC7 t_{su(DATxV-CLKIH)}

MMC8 t_{su(CLKIH-DATxIV)}

Setup time, mmc1_cmd valid before

mmc1_clk rising clock edge

TBD

ns

Hold time, mmc1_cmd valid after mmc1_clk

rising clock edge

Setup time, mmc1_datx valid before

mmc1_clk rising clock edge

Hold time, mmc1_datx valid after mmc1_clk

rising clock edge

MMC/SD/SDIO Interface 2

MMC3 t_{su(CMDV-CLKIH)}

Setup time, mmc2_cmd valid before

mmc2_clk rising clock edge

TBD

ns

MMC4 t_{su(CLKIH-CMDIV)}

MMC7 t_{su(DATxV-CLKIH)}

MMC8 t_{su(CLKIH-DATxIV)}

Hold time, mmc2_cmd valid after mmc2_clk

rising clock edge

Setup time, mmc2_datx valid before

mmc2_clk rising clock edge

Hold time, mmc2_datx valid after mmc2_clk

rising clock edge

MMC/SD/SDIO Interface 3

MMC3 t_{su(CMDV-CLKIH)}

Setup time, mmc3_cmd valid before

mmc3_clk rising clock edge

TBD

ns

MMC4 t_{su(CLKIH-CMDIV)}

MMC7 t_{su(DATxV-CLKIH)}

MMC8 t_{su(CLKIH-DATxIV)}

Hold time, mmc3_cmd valid after mmc3_clk

rising clock edge

Setup time, mmc3_datx valid before

mmc3_clk rising clock edge

Hold time, mmc3_datx valid after mmc3_clk

rising clock edge

(1) Timing parameters are referred to output clock specified in Table 6-121.

(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-121.

Table 6-121. MMC/SD/SDIO Switching Characteristics Standard MMC Mode and MMC Identification Mode

NO.

PARAMETER

1.8 V

3.3 V

UNIT

MIN

MAX

MIN

MAX

MMC Identification Mode

MMC1

MMC2

t_c(clk)

Cycle time⁽¹⁾, output clk period

TBD

ns

ps

t_W(clkH)

t_W(clkL)

t_dc(clk)

t_j(clk)

Typical pulse duration, output clk high

Typical pulse duration, output clk low

Duty cycle error, output clk

TBD

Jitter standard deviation⁽²⁾, output clk

Standard MMC Mode

MMC1

MMC2

t_c(clk)

Cycle time⁽¹⁾, output clk period

TBD

ns

ps

t_W(clkH)

t_W(clkL)

t_dc(clk)

t_j(clk)

Typical pulse duration, output clk high

Typical pulse duration, output clk low

Duty cycle error, output clk

TBD

Jitter standard deviation⁽²⁾, output clk

MMC/SD/SDIO Interface 1

t_c(clk)

Rise time, output clk

TBD

ns

(1) Related with the output clk maximum and minimum frequencies programmable in I/F module.

(2) The jitter probability density can be approximated by a Gaussian function.

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Table 6-121. MMC/SD/SDIO Switching Characteristics Standard MMC Mode and MMC Identification Mode

(continued)

NO.

PARAMETER

1.8 V

3.3 V

UNIT

MIN

MAX

TBD

MIN

MAX

TBD

t_W(clkH)

Fall time, output clk

Rise time, output data

Fall time, output data

ns

t_W(clkL)

t_dc(clk)

MMC5

MMC6

MMC5

MMC6

t_d(CLKOH-CMD)

Delay time, mmc1_clk rising clock edge to

mmc1_cmd transition

TBD

t_{d(CLKOH-DATx)}

t_d(CLKOH-CMD)

t_{d(CLKOH-DATx)}

Delay time, mmc1_clk rising clock edge to

mmc1_datx transition

TBD

ns

Delay time, mmc1_clk rising clock edge to

mmc1_cmd transition

Delay time, mmc1_clk rising clock edge to

mmc1_datx transition

MMC/SD/SDIO Interface 2

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

TBD

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

MMC5

MMC6

t_d(CLKOH-CMD)

Delay time, mmc2_clk rising clock edge to

mmc2_cmd transition

TBD

t_{d(CLKOH-DATx)}

Delay time, mmc2_clk rising clock edge to

mmc2_datx transition

TBD

ns

MMC/SD/SDIO Interface 3

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

TBD

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

MMC5

MMC6

t_d(CLKOH-CMD)

Delay time, mmc3_clk rising clock edge to

mmc3_cmd transition

TBD

t_{d(CLKOH-DATx)}

Delay time, mmc3_clk rising clock edge to

mmc3_datx transition

TBD

ns

Table 6-122. X Parameter

CLKD

1 or Even

Odd

X

0.5

(trunk[CLKD/2]+1)/CLKD

Table 6-123. Y Parameter

CLKD

1 or Even

Odd

Y

0.5

(trunk[CLKD/2])/CLKD

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For details about clock division factor CLKD, see the TBD.

MMC1

MMC2

MMC4

mmcx_clk

MMC3

MMC7

mmcx_cmd

MMC8

mmcx_dat[3:0]

030-104

In mmcx, x is equal to 1, 2, or 3.

Figure 6-64. MMC/SD/SDIO High-Speed and Standard MMC Modes Data/Command Receive

MMC1

MMC2

mmcx_clk

MMC5

MMC6

MMC5

mmcx_cmd

MMC6

mmcx_dat[3:0]

030-105

In mmcx, x is equal to 1, 2, or 3.

Figure 6-65. MMC/SD/SDIO High-Speed and Standard MMC Modes Data/Command Transmit

6.7.1.4 MMC/SD/SDIO in High-Speed SD Mode

Table 6-125 and Table 6-126 assume testing over the recommended operating conditions and electrical

characteristic conditions.

Table 6-124. MMC/SD/SDIO Timing Conditions High-Speed SD Mode

TIMING CONDITION PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

High-Speed SD Mode

Input Conditions

t_R

Input signal rise time

Input signal fall time

TBD

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

TBD

pF

Table 6-125. MMC/SD/SDIO Timing Requirements High-Speed SD Mode^(1)(2)(3)

NO.

PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

High-Speed SD Mode

MMC/SD/SDIO Interface 1

HSSD3

t_{su(CMDV-CLKIH)}

Setup time, mmc1_cmd valid before mmc1_clk rising

clock edge

TBD

ns

(1) Timing Parameters are referred to output clock specified in Table 6-126.

(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-126.

(3) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.

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Table 6-125. MMC/SD/SDIO Timing Requirements High-Speed SD Mode (continued)

NO.

PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

HSSD4

HSSD7

HSSD8

t_{su(CLKIH-CMDIV)}

t_{su(DATxV-CLKIH)}

t_{su(CLKIH-DATxIV)}

Hold time, mmc1_cmd valid after mmc1_clk rising

clock edge

TBD

ns

Setup time, mmc1_datx valid before mmc1_clk rising

clock edge

TBD

Hold time, mmc1_datx valid after mmc1_clk rising

clock edge

MMC/SD/SDIO Interface 2

HSSD3

HSSD4

HSSD7

HSSD8

t_{su(CMDV-CLKIH)}

t_{su(CLKIH-CMDIV)}

t_{su(DATxV-CLKIH)}

t_{su(CLKIH-DATxIV)}

Setup time, mmc2_cmd valid before mmc2_clk rising

clock edge

TBD

ns

Hold time, mmc2_cmd valid after mmc2_clk rising

clock edge

Setup time, mmc2_datx valid before mmc2_clk rising

clock edge

Hold time, mmc2_datx valid after mmc2_clk rising

clock edge

MMC/SD/SDIO Interface 3

HSSD3

HSSD4

HSSD7

HSSD8

t_{su(CMDV-CLKIH)}

t_{su(CLKIH-CMDIV)}

t_{su(DATxV-CLKIH)}

t_{su(CLKIH-DATxIV)}

Setup time, mmc3_cmd valid before mmc3_clk rising

clock edge

TBD

ns

Hold time, mmc3_cmd valid after mmc3_clk rising

clock edge

Setup time, mmc3_datx valid before mmc3_clk rising

clock edge

Hold time, mmc3_datx valid after mmc3_clk rising

clock edge

Table 6-126. MMC/SD/SDIO Switching Characteristics High-Speed SD Mode

NO.

PARAMETER

1.8 V, 3.3 V

UNIT

MIN

MAX

High-Speed SD Mode

HSSD1

HSSD2

t_c(clk)

Cycle time⁽¹⁾, output clk period

TBD

ns

ps

t_W(clkH)

t_W(clkL)

t_dc(clk)

t_j(clk)

Typical pulse duration, output clk high

Typical pulse duration, output clk low

Duty cycle error, output clk

TBD

Jitter standard deviation⁽²⁾, output clk

MMC/SD/SDIO Interface 1

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

TBD

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

HSSD5

HSSD6

t_d(CLKOH-CMD)

Delay time, mmc1_clk rising clock edge to mmc1_cmd

transition

TBD

t_{d(CLKOH-DATx)}

Delay time, mmc1_clk rising clock edge to mmc1_datx

transition

TBD

ns

MMC/SD/SDIO Interface 2

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

TBD

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

(1) Related with the output clk maximum and minimum frequencies programmable in I/F module.

(2) The jitter probability density can be approximated by a Gaussian function.

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Table 6-126. MMC/SD/SDIO Switching Characteristics High-Speed SD Mode (continued)

NO.

PARAMETER

1.8 V, 3.3 V

UNIT

MIN

MAX

HSSD5

HSSD6

t_d(CLKOH-CMD)

t_{d(CLKOH-DATx)}

Delay time, mmc2_clk rising clock edge to mmc2_cmd

transition

TBD

ns

Delay time, mmc2_clk rising clock edge to mmc2_datx

transition

TBD

MMC/SD/SDIO Interface 3

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

TBD

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

HSSD5

HSSD6

t_d(CLKOH-CMD)

Delay time, mmc3_clk rising clock edge to mmc3_cmd

transition

TBD

t_{d(CLKOH-DATx)}

Delay time, mmc3_clk rising clock edge to mmc3_datx

transition

TBD

ns

Table 6-127. X Parameters

CLKD

1 or Even

Odd

X

0.5

(trunk[CLKD/2]+1)/CLKD

Table 6-128. Y Parameters

CLKD

1 or Even

Odd

Y

0.5

(trunk[CLKD/2])/CLKD

For details about clock division factor CLKD, see the TBD.

HSSD1

HSSD2

mmcx_clk

HSSD3

HSSD4

mmcx_cmd

HSSD7

HSSD8

mmcx_dat[3:0]

030-106

In mmcx, x is equal to 1, 2, or 3.

Figure 6-66. MMC/SD/SDIO High-Speed SD Mode Data/Command Receive

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HSSD1

HSSD2

mmcx_clk

HSSD5

HSSD6

HSSD5

mmcx_cmd

HSSD6

mmcx_dat[3:0]

030-107

In mmcx, x is equal to 1, 2, or 3.

Figure 6-67. MMC/SD/SDIO High-Speed SD Mode Data/Command Transmit

6.7.1.5 MMC/SD/SDIO in Standard SD Mode

Table 6-130 and Table 6-131 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-68).

Table 6-129. MMC/SD/SDIO Timing Conditions Standard SD Mode

TIMING CONDITION PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

Standard SD Mode

Input Conditions

t_R

Input signal rise time

Input signal fall time

TBD

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

TBD

pF

170

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Table 6-130. MMC/SD/SDIO Timing Requirements Standard SD Mode^(1)(2)(3)

NO.

PARAMETER

1.8 V, 3.3V

MAX

UNIT

MIN

Standard SD Mode

MMC/SD/SDIO Interface 1

SD3

SD4

SD7

SD8

t_{su(CMDV-CLKIH)}

t_{su(CLKIH-CMDIV)}

t_{su(DATxV-CLKIH)}

t_{su(CLKIH-DATxIV)}

Setup time, mmc1_cmd valid before mmc1_clk rising clock

edge

TBD

ns

Hold time, mmc1_cmd valid after mmc1_clk rising clock

edge

Setup time, mmc1_datx valid before mmc1_clk rising clock

edge

Hold time, mmc1_datx valid after mmc1_clk rising clock

edge

MMC/SD/SDIO Interface 2

SD3

SD4

SD7

SD8

t_{su(CMDV-CLKIH)}

t_{su(CLKIH-CMDIV)}

t_{su(DATxV-CLKIH)}

t_{su(CLKIH-DATxIV)}

Setup time, mmc2_cmd valid before mmc2_clk rising clock

edge

TBD

ns

Hold time, mmc2_cmd valid after mmc2_clk rising clock

edge

Setup time, mmc2_datx valid before mmc2_clk rising clock

edge

Hold time, mmc2_datx valid after mmc2_clk rising clock

edge

MMC/SD/SDIO Interface 3

SD3

SD4

SD7

SD8

t_{su(CMDV-CLKIH)}

t_{su(CLKIH-CMDIV)}

t_{su(DATxV-CLKIH)}

t_{su(CLKIH-DATxIV)}

Setup time, mmc3_cmd valid before mmc3_clk rising clock

edge

TBD

ns

Hold time, mmc3_cmd valid after mmc3_clk rising clock

edge

Setup time, mmc3_datx valid before mmc3_clk rising clock

edge

Hold time, mmc3_datx valid after mmc3_clk rising clock

edge

(1) Timing parameters are referred to output clock specified in Table 6-131.

(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-131.

(3) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.

Table 6-131. MMC/SD/SDIO Switching Characteristics Standard SD Mode

NO.

PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

Standard SD Mode

SD1

SD2

t_c(clk)

Cycle time⁽¹⁾, output clk period

TBD

ns

ps

t_W(clkH)

t_W(clkL)

t_dc(clk)

t_j(clk)

Typical pulse duration, output clk high

Typical pulse duration, output clk low

Duty cycle error, output clk

TBD

Jitter standard deviation⁽²⁾, output clk

MMC/SD/SDIO Interface 1

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

TBD

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

SD5

t_d(CLKOH-CMD)

Delay time, mmc1_clk rising clock edge to mmc1_cmd

transition

TBD

(1) Related with the output clk maximum and minimum frequencies programmable in I/F module.

(2) The jitter probability density can be approximated by a Gaussian function.

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Table 6-131. MMC/SD/SDIO Switching Characteristics Standard SD Mode (continued)

NO.

PARAMETER

1.8V, 3.3V

UNIT

MIN

MAX

SD6

t_{d(CLKOH-DATx)}

Delay time, mmc1_clk rising clock edge to mmc1_datx

transition

TBD

ns

MMC/SD/SDIO Interface 2

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

TBD

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

SD5

SD6

t_d(CLKOH-CMD)

Delay time, mmc2_clk rising clock edge to mmc2_cmd

transition

TBD

t_{d(CLKOH-DATx)}

Delay time, mmc2_clk rising clock edge to mmc2_datx

transition

TBD

ns

MMC/SD/SDIO Interface 3

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

TBD

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

SD5

SD6

t_d(CLKOH-CMD)

Delay time, mmc3_clk rising clock edge to mmc3_cmd

transition

TBD

t_{d(CLKOH-DATx)}

Delay time, mmc3_clk rising clock edge to mmc3_datx

transition

TBD

ns

Table 6-132. X Parameter

CLKD

X

1 or Even

Odd

0.5

(trunk[CLKD/2]+1)/CLKD

Table 6-133. Y Parameter

CLKD

1 or Even

Odd

Y

0.5

(trunk[CLKD/2])/CLKD

For details about clock division factor CLKD, see the TBD.

SD1

SD2

SD4

mmcx_clk

SD3

mmcx_cmd

SD7

SD8

mmcx_dat[3:0]

030-108

In mmcx, x is equal to 1, 2, or 3.

Figure 6-68. MMC/SD/SDIO Standard SD Mode Data/Command Receive

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SD1

SD2

SD5

mmcx_clk

SD5

SD6

mmcx_cmd

SD6

mmcx_dat[3:0]

030-109

In mmcx, x is equal to 1, 2, or 3.

Figure 6-69. MMC/SD/SDIO Standard SD Mode Data/Command Transmit

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6.8 Test Interfaces

The emulation and trace interfaces allow tracing activities of the following CPUs:

•

ARM1136JF-STM through an Embedded Trace Macro-cell (ETM11) dedicated to enable real-time

trace of the ARM subsystem operations and a Serial Debug Trace Interface (SDTI)

All processors can be emulated via JTAG ports.

6.8.1 Embedded Trace Macro Interface (ETM)

Table 6-134 assumes testing over the recommended operating conditions (see Figure 6-70).

Table 6-134. Embedded Trace Macro Interface Switching Characteristics⁽¹⁾

NO.

PARAMETER

MIN

MAX

UNIT

f

1/t_c(CLK)

Frequency, etk_clk

Cycle time⁽²⁾, etk_clk

TBD

MHz

ns

ETM0 t_c(CLK)

TBD

ETM1 t_W(CLK)

ETM2 t_d(CLK-CTL)

ETM3 t_d(CLK-D)

Clock pulse width, etk_clk

ns

Delay time, etk_clk clock edge to etk_ctl transition

Delay time, etk_clk clock high to etk_d[15:0] transition

TBD

ns

(1) The capacitive load is equivalent to 25 pF.

(2) Cycle time is given by considering a jitter of 5%.

ETM0

ETM1

etk_clk

ETM2

etk_ctl

ETM2

ETM3

etk_d[15:0]

030-110

Figure 6-70. Embedded Trace Macro Interface

6.8.2 System Debug Trace Interface (SDTI)

The system debug trace interface (SDTI) module provides real-time software tracing functionality to the

AM3517/05 device.

The trace interface has four trace data pins and a trace clock pin.

This interface is a dual-edge interface: the data are available on rising and falling edges of sdti_clk but can

be also configured in single edge mode where data are available on falling edge of sdti_clk.

Serial interface operates in clock stop regime: serial clock is not free running, when there is no trace data

there is no trace clock.

6.8.2.1 System Debug Trace Interface in Dual-Edge Mode

Table 6-136 assumes testing over the recommended operating conditions and electrical characteristic

conditions (see Figure 6-71).

Table 6-135. System Debug Trace Interface Timing Conditions – Dual-Edge Mode

TIMING CONDITION PARAMETER

Output Conditions

C_LOAD

VALUE

UNIT

Output load capacitance

25

pF

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Table 6-136. System Debug Trace Interface Switching Characteristics – Dual-Edge Mode

NO.

PARAMETER

1.15 V

UNIT

MIN

MAX

SD1

SD2

t_c(CLK)

Cycle time, sdti_clk period

29

ns

t_w(CLK)

Typical pulse duration, sdti_clk high or low

Duty cycle error, sdti_clk

Rise time, sdti_clk

0.5*P⁽¹⁾

t_dc(CLK)

t_R(CLK)

–1.2

1.2

5

t_F(CLK)

Fall time, sdti_clk

5

SD3

t_d(CLK-TxD)

Delay time, sdti_clk transition to

sdti_txd[3:0] transition

Multiplexing mode on etk pins

Multiplexing mode on jtag_emu pins

2.3

10.9

13.9

5

t_R(CLK)

t_F(CLK)

Rise time, sdti_txd[3:0]

Fall time, sdti_txd[3:0]

ns

5

(1) P = sdti_clk clock period

SD1

SD2

sdti_clk

SD3

sdti_txd[3:0]

Header Header Ad[7:4]

Ad[3:0] Da[15:12] Da[11:8] Da[7:4]

Da[3:0]

030-111

Figure 6-71. System Debug Trace Interface – Dual-Edge Mode

6.8.2.2 System Debug Trace Interface in Single-Edge Mode

Table 6-138 assumes testing over the recommended operating conditions and electrical characteristic

conditions (see Figure 6-72).

Table 6-137. System Debug Trace Interface Timing Conditions – Single-Edge Mode

TIMING CONDITION PARAMETER

Output Conditions

VALUE

UNIT

C_LOAD

Output load capacitance

25

pF

Table 6-138. System Debug Trace Interface Switching Characteristics – Single-Edge Mode

NO.

PARAMETER

1.15 V

UNIT

MIN

MAX

SD1

SD2

t_c(CLK)

Cycle time, sdti_clk period

29

ns

t_w(CLK)

t_dc(CLK)

t_R(CLK)

t_F(CLK)

Typical pulse duration, sdti_clk high or low

Duty cycle error, sdti_clk

Rise time, sdti_clk

0.5*P⁽¹⁾

–1.2

1.2

5

Fall time, sdti_clk

5

SD3

t_d(CLK-TxD)

Delay time, sdti_clk transition to

sdti_txd[3:0] transition

Multiplexing mode on etk pins

Multiplexing mode on jtag_emu pins

2.3

26.5

33.2

5

t_R(CLK)

t_F(CLK)

Rise time, sdti_txd[3:0]

Fall time, sdti_txd[3:0]

ns

5

(1) P = sdti_clk clock period.

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SD1

SD2

sdti_clk

SD3

Header

SD3

Ad[7:4]

sdti_txd[3:0]

Header

Ad[3:0]

Da[15:12]

Da[11:8]

Da[7:4]

Da[3:0]

030-112

Figure 6-72. System Debug Trace Interface – Single-Edge Mode

6.8.3 JTAG Interfaces

AM3517/05 JTAG TAP controller handles standard IEEE JTAG interfaces. The following sections define

the timing requirements for several tools used to test the AM3517/05 processors as:

•

Free running clock tool, like XDS560 and XDS510 tools

Adaptive clock tool, like RealView ICE tool and Lauterbach tool

6.8.3.1 JTAG Free Running Clock Mode

Table 6-140 and Table 6-141 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-73).

Table 6-139. JTAG Timing Conditions Free Running Clock Mode

TIMING CONDITION PARAMETER

1.8 V

MAX

3.3 V

MAX

UNIT

Input Conditions

t_R

Input signal rise time

Input signal fall time

TBD

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

TBD

pF

Table 6-140. JTAG Timing Requirements Free Running Clock Mode⁽¹⁾

1.8 V

3.3 V

NO.

PARAMETER

MIN

MAX

MIN

MAX

UNIT

JT4

JT5

JT6

t_c(tck)

t_w(tckL)

Cycle time⁽²⁾, jtag_tck period

Typical pulse duration, jtag_tck low

Typical pulse duration, jtag_tck high

Duty cycle error, jtag_tck

ns

ps

ns

TBD

t_w(tckH)

t_dc(tck)

TBD

t_j(tck)

Cycle jitter⁽³⁾, jtag_tck

JT7

JT8

t_{su(tdiV-rtckH)}

t_{h(tdiV-rtckH)}

t_{su(tmsV-rtckH)}

t_{h(tmsV-rtckH)}

Setup time, jtag_tdi valid before jtag_rtck high

Hold time, jtag_tdi valid after jtag_rtck high

Setup time, jtag_tms valid before jtag_rtck high

Hold time, jtag_tms valid after jtag_rtck high

Setup time, jtag_emux⁽⁴⁾valid before jtag_rtck

high

JT9

JT10

JT12 t_{su(emuxV-rtckH)}

JT13 t_{h(emuxV-rtckH)}

Hold time,jtag_emux⁽⁴⁾valid after jtag_rtck high

TBD

ns

(1) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.

(2) Related with the input maximum frequency supported by the JTAG module.

(3) Maximum cycle jitter supported by jtag _tck input clock.

(4) x = 0 to 1

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Table 6-141. JTAG Switching Characteristics Free Running Clock Mode

1.8 V

3.3 V

NO.

PARAMETER

MIN

MAX

MIN

MAX

UNIT

JT1 t_c(rtck)

JT2 t_w(rtckL)

JT3 t_w(rtckH)

t_dc(rtck)

Cycle time⁽¹⁾, jtag_rtck period

Typical pulse duration, jtag_rtck low

Typical pulse duration, jtag_rtck high

Duty cycle error, jtag_rtck

TBD

ns

ps

ns

TBD

t_j(rtck)

Jitter standard deviation⁽²⁾, jtag_rtck

t_R(rtck)

Rise time, jtag_rtck

t_F(rtck)

Fall time, jtag_rtck

JT11 t_{d(rtckL-tdoV)}

t_R(tdo)

Delay time, jtag_rtck low to jtag_tdo valid

Rise time, jtag_tdo

TBD

t_F(tdo)

Fall time, jtag_tdo

JT14 t_{d(rtckH-emuxV)}

t_R(emux)

Delay time, jtag_rtck high to ,jtag_emux⁽³⁾valid

Rise time, jtag_emux⁽³⁾

Fall time, jtag_emux⁽³⁾

t_F(emux)

(1) Related with the jtag_rtck maximum frequency.

(2) The jitter probability density can be approximated by a Gaussian function.

(3) x = 0 to 1

JT4

JT5

JT6

JT3

jtag_tck

JT1

JT2

jtag_rtck

JT7

JT8

jtag_tdi

JT9

JT10

JT13

jtag_tms

JT12

jtag_emux(IN)

JT11

jtag_tdo

JT14

jtag_emux(OUT)

030-113

In jtag_emux, x is equal to 0 to 1.

Figure 6-73. JTAG Interface Timing Free Running Clock Mode

6.8.3.2 JTAG Adaptive Clock Mode

Table 6-143 and Table 6-144 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-74):

Table 6-142. JTAG Timing Conditions Adaptive Clock Mode

TIMING CONDITION PARAMETER

1.8 V

MAX

3.3 V

UNIT

Input Conditions

t_R

Input signal rise time

TBD

ns

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Table 6-142. JTAG Timing Conditions Adaptive Clock Mode (continued)

TIMING CONDITION PARAMETER

1.8 V

MAX

TBD

3.3 V

TBD

UNIT

t_F

Input signal fall time

ns

Output Conditions

C_LOAD

Output load capacitance

TBD

pF

Table 6-143. JTAG Timing Requirements Adaptive Clock Mode⁽¹⁾

1.8 V

3.3 V

NO.

PARAMETER

MIN

MAX

MIN

MAX

UNIT

JA4

JA5

JA6

t_c(tck)

Cycle time⁽²⁾, jtag_tck period

TBD

ns

ps

ns

t_w(tckL)

Typical pulse duration, jtag_tck low

Typical pulse duration, jtag_tck high

Duty cycle error, jtag_tck

TBD

t_w(tckH)

t_dc(lclk)

TBD

t_j(lclk)

Cycle jitter⁽³⁾, jtag_tck

JA7

JA8

JA9

t_{su(tdiV-tckH)}

t_h(tdiV-tckH)

t_{su(tmsV-tckH)}

Setup time, jtag_tdi valid before jtag_tck high

Hold time, jtag_tdi valid after jtag_tck high

Setup time, jtag_tms valid before jtag_tck high

Hold time, jtag_tms valid after jtag_tck high

JA10 t_h(tmsV-tckH)

(1) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.

(2) Related with the input maximum frequency supported by the JTAG module.

(3) Maximum cycle jitter supported by jtag _tck input clock.

Table 6-144. JTAG Switching Characteristics Adaptive Clock Mode

1.8 V

3.3 V

NO.

PARAMETER

MIN

MAX

MIN

MAX

UNIT

JA1

JA2

JA3

t_c(rtck)

Cycle time⁽¹⁾, jtag_rtck period

Typical pulse duration, jtag_rtck low

Typical pulse duration, jtag_rtck high

Duty cycle error, jtag_rtck

Jitter standard deviation⁽²⁾, jtag_rtck

Rise time, jtag_rtck

TBD

ns

ps

ns

t_w(rtckL)

t_w(rtckH)

t_dc(rtck)

t_j(rtck)

TBD

t_R(rtck)

t_F(rtck)

Fall time, jtag_rtck

JA11 t_{d(rtckL-tdoV)}

Delay time, jtag_rtck low to jtag_tdo valid

Rise time, jtag_tdo,

t_R(tdo)

t_F(tdo)

Fall time, jtag_tdo

(1) Related with the jtag _rtck maximum frequency programmable.

(2) The jitter probability density can be approximated by a Gaussian function.

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JA4

JA5

JA6

jtag_tck

JA7

JA9

JA8

jtag_tdi

JA10

JA1

jtag_tms

JA2

JA3

jtag_rtck

jtag_tdo

JA11

030-114

Figure 6-74. JTAG Interface Timing Adaptive Clock Mode

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7 PACKAGE CHARACTERISTICS

7.1 Package Thermal Resistance

Table 7-1 provides the thermal resistance characteristics for the recommended package types used on the

AM3517/05 Applications Processor.

Table 7-1. AM3517/05 Thermal Resistance Characteristics⁽¹⁾

Package

Power (W)

R_JA(C/W)

R_JB(C/W)

R_JC(C/W)

Board Type

AM3517/05

(ZCN Pkg.)

TBD

10.1

TBD

2S2P

(1) R_JA(Theta-JA) = Thermal Resistance Junction-to-Ambient, C/W

R_JB(Theta-JB) = Thermal Resistance Junction-to-Board, C/W

R_JC(Theta-JC) = Thermal Resistance Junction-to-Case, C/W

7.2 Device Support

7.2.1 Development Support

7.2.2 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

AM35x processors and support tools. Each device has one of three prefixes: X, P, or null (no prefix).

Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and

TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes

(TMDX) through fully qualified production devices/tools (TMDS).

Device development evolutionary flow:

X

Experimental device that is not necessarily representative of the final devices electrical

specifications and may not use production assembly flow. (TMX definition)

P

Prototype device that is not necessarily the final silicon die and may not necessarily meet

final electrical specifications. (TMP definition)

null

Production version of the silicon die that is fully qualified. (TMS definition)

Support tool development evolutionary flow:

TMDX

TMDS

Development support product that has not yet completed Texas Instruments internal

qualification testing.

Fully qualified development support product.

TMX and TMP devices and TMDX development-support tools are shipped against the following

disclaimer:

Developmental product is intended for internal evaluation purposes.

Production devices and TMDS development-support tools have been characterized fully, and the quality

and reliability of the device have been demonstrated fully. TIs standard warranty applies.

Predictions show that prototype devices (X or P), have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system

because their expected end-use failure rate still is undefined. Only qualified production devices are to be

used.

For additional description of the device nomenclature markings, see the AM35x Processor Silicon Errata

(literature number SPRZ306).

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X

AM3517

B

ZCN

( )

PREFIX

= Experimental Device

= Prototype Device

X

P

blank = commercial temperature

= extended temperature

blank = Production Device

A

PACKAGE TYPE

DEVICE

ZCN = 491-pin sPBGA

SILICON REVISION

Figure 7-1. Device Nomenclature

7.2.3 Documentation Support

7.2.3.1 Related Documentation from Texas Instruments

The following documents describe the AM3517/05 ARM Microprocessor. Copies of these documents are

available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at

www.ti.com.

The current documentation that describes the AM3517/05 ARM Microprocessor, related peripherals, and

other technical collateral, is available in the product folder at: www.ti.com.

SPRUGR0 AM35x ARM Microprocessor Technical Reference Manual. Collection of documents

providing detailed information on the Sitara^TMarchitecture including power, reset, and clock

control, interrupts, memory map, and switch fabric interconnect. Detailed information on the

microprocessor unit (MPU) subsystem as well a functional description of the peripherals

supported on AM3517/05 devices is also included.

7.2.3.2 Related Documentation from Other Sources

The following documents are related to the AM3517/05 ARM Microprocessor. Copies of these documents

can be obtained directly from the internet or from your Texas Instruments representative.

Cortex-A8 Technical Reference Manual. This is the technical reference manual for the Cortex-A8

processor. A copy of this document can be obtained via the internet at http://infocenter.arm.com. Please

see the AM3517/05 ARM Microprocessor Silicon Errata (literature number SPRZ306) to determine the

revision of the Cortex-A8 core used on your device.

ARM Core Cortex^TM-A8 (AT400/AT401) Errata Notice. Provides a list of advisories for the different

revisions of the Cortex-A8 processor. Contact your TI representative for a copy of this document. Please

see the AM3517/05 ARM Microprocessor Silicon Errata (literature number SPRZ306) to determine the

revision of the Cortex-A8 core used on your device.

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23-Oct-2009

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

XAM3517ZCN

ACTIVE

NFBGA

ZCN

491

90

TBD

Call TI

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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Addendum-Page 1

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amplifier.ti.com

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www.ti.com/security

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www.ti.com/video

dsp.ti.com

www.ti.com/clocks

interface.ti.com

logic.ti.com

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Logic

Power Mgmt

Microcontrollers

RFID

Telephony

Video & Imaging

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型号：	AM3517_16
厂家：	TEXAS INSTRUMENTS
描述：	AM3517, AM3505 Sitaraâ¢ Processors
文件：	总184页 (文件大小：2065K)
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